1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2014, The Linux Foundation. All rights reserved.
4  */
5 
6 #include <linux/module.h>
7 #include <linux/of.h>
8 #include <linux/platform_device.h>
9 
10 #include "pinctrl-msm.h"
11 
12 static const struct pinctrl_pin_desc ipq8064_pins[] = {
13 	PINCTRL_PIN(0, "GPIO_0"),
14 	PINCTRL_PIN(1, "GPIO_1"),
15 	PINCTRL_PIN(2, "GPIO_2"),
16 	PINCTRL_PIN(3, "GPIO_3"),
17 	PINCTRL_PIN(4, "GPIO_4"),
18 	PINCTRL_PIN(5, "GPIO_5"),
19 	PINCTRL_PIN(6, "GPIO_6"),
20 	PINCTRL_PIN(7, "GPIO_7"),
21 	PINCTRL_PIN(8, "GPIO_8"),
22 	PINCTRL_PIN(9, "GPIO_9"),
23 	PINCTRL_PIN(10, "GPIO_10"),
24 	PINCTRL_PIN(11, "GPIO_11"),
25 	PINCTRL_PIN(12, "GPIO_12"),
26 	PINCTRL_PIN(13, "GPIO_13"),
27 	PINCTRL_PIN(14, "GPIO_14"),
28 	PINCTRL_PIN(15, "GPIO_15"),
29 	PINCTRL_PIN(16, "GPIO_16"),
30 	PINCTRL_PIN(17, "GPIO_17"),
31 	PINCTRL_PIN(18, "GPIO_18"),
32 	PINCTRL_PIN(19, "GPIO_19"),
33 	PINCTRL_PIN(20, "GPIO_20"),
34 	PINCTRL_PIN(21, "GPIO_21"),
35 	PINCTRL_PIN(22, "GPIO_22"),
36 	PINCTRL_PIN(23, "GPIO_23"),
37 	PINCTRL_PIN(24, "GPIO_24"),
38 	PINCTRL_PIN(25, "GPIO_25"),
39 	PINCTRL_PIN(26, "GPIO_26"),
40 	PINCTRL_PIN(27, "GPIO_27"),
41 	PINCTRL_PIN(28, "GPIO_28"),
42 	PINCTRL_PIN(29, "GPIO_29"),
43 	PINCTRL_PIN(30, "GPIO_30"),
44 	PINCTRL_PIN(31, "GPIO_31"),
45 	PINCTRL_PIN(32, "GPIO_32"),
46 	PINCTRL_PIN(33, "GPIO_33"),
47 	PINCTRL_PIN(34, "GPIO_34"),
48 	PINCTRL_PIN(35, "GPIO_35"),
49 	PINCTRL_PIN(36, "GPIO_36"),
50 	PINCTRL_PIN(37, "GPIO_37"),
51 	PINCTRL_PIN(38, "GPIO_38"),
52 	PINCTRL_PIN(39, "GPIO_39"),
53 	PINCTRL_PIN(40, "GPIO_40"),
54 	PINCTRL_PIN(41, "GPIO_41"),
55 	PINCTRL_PIN(42, "GPIO_42"),
56 	PINCTRL_PIN(43, "GPIO_43"),
57 	PINCTRL_PIN(44, "GPIO_44"),
58 	PINCTRL_PIN(45, "GPIO_45"),
59 	PINCTRL_PIN(46, "GPIO_46"),
60 	PINCTRL_PIN(47, "GPIO_47"),
61 	PINCTRL_PIN(48, "GPIO_48"),
62 	PINCTRL_PIN(49, "GPIO_49"),
63 	PINCTRL_PIN(50, "GPIO_50"),
64 	PINCTRL_PIN(51, "GPIO_51"),
65 	PINCTRL_PIN(52, "GPIO_52"),
66 	PINCTRL_PIN(53, "GPIO_53"),
67 	PINCTRL_PIN(54, "GPIO_54"),
68 	PINCTRL_PIN(55, "GPIO_55"),
69 	PINCTRL_PIN(56, "GPIO_56"),
70 	PINCTRL_PIN(57, "GPIO_57"),
71 	PINCTRL_PIN(58, "GPIO_58"),
72 	PINCTRL_PIN(59, "GPIO_59"),
73 	PINCTRL_PIN(60, "GPIO_60"),
74 	PINCTRL_PIN(61, "GPIO_61"),
75 	PINCTRL_PIN(62, "GPIO_62"),
76 	PINCTRL_PIN(63, "GPIO_63"),
77 	PINCTRL_PIN(64, "GPIO_64"),
78 	PINCTRL_PIN(65, "GPIO_65"),
79 	PINCTRL_PIN(66, "GPIO_66"),
80 	PINCTRL_PIN(67, "GPIO_67"),
81 	PINCTRL_PIN(68, "GPIO_68"),
82 
83 	PINCTRL_PIN(69, "SDC3_CLK"),
84 	PINCTRL_PIN(70, "SDC3_CMD"),
85 	PINCTRL_PIN(71, "SDC3_DATA"),
86 };
87 
88 #define DECLARE_IPQ_GPIO_PINS(pin) static const unsigned int gpio##pin##_pins[] = { pin }
89 DECLARE_IPQ_GPIO_PINS(0);
90 DECLARE_IPQ_GPIO_PINS(1);
91 DECLARE_IPQ_GPIO_PINS(2);
92 DECLARE_IPQ_GPIO_PINS(3);
93 DECLARE_IPQ_GPIO_PINS(4);
94 DECLARE_IPQ_GPIO_PINS(5);
95 DECLARE_IPQ_GPIO_PINS(6);
96 DECLARE_IPQ_GPIO_PINS(7);
97 DECLARE_IPQ_GPIO_PINS(8);
98 DECLARE_IPQ_GPIO_PINS(9);
99 DECLARE_IPQ_GPIO_PINS(10);
100 DECLARE_IPQ_GPIO_PINS(11);
101 DECLARE_IPQ_GPIO_PINS(12);
102 DECLARE_IPQ_GPIO_PINS(13);
103 DECLARE_IPQ_GPIO_PINS(14);
104 DECLARE_IPQ_GPIO_PINS(15);
105 DECLARE_IPQ_GPIO_PINS(16);
106 DECLARE_IPQ_GPIO_PINS(17);
107 DECLARE_IPQ_GPIO_PINS(18);
108 DECLARE_IPQ_GPIO_PINS(19);
109 DECLARE_IPQ_GPIO_PINS(20);
110 DECLARE_IPQ_GPIO_PINS(21);
111 DECLARE_IPQ_GPIO_PINS(22);
112 DECLARE_IPQ_GPIO_PINS(23);
113 DECLARE_IPQ_GPIO_PINS(24);
114 DECLARE_IPQ_GPIO_PINS(25);
115 DECLARE_IPQ_GPIO_PINS(26);
116 DECLARE_IPQ_GPIO_PINS(27);
117 DECLARE_IPQ_GPIO_PINS(28);
118 DECLARE_IPQ_GPIO_PINS(29);
119 DECLARE_IPQ_GPIO_PINS(30);
120 DECLARE_IPQ_GPIO_PINS(31);
121 DECLARE_IPQ_GPIO_PINS(32);
122 DECLARE_IPQ_GPIO_PINS(33);
123 DECLARE_IPQ_GPIO_PINS(34);
124 DECLARE_IPQ_GPIO_PINS(35);
125 DECLARE_IPQ_GPIO_PINS(36);
126 DECLARE_IPQ_GPIO_PINS(37);
127 DECLARE_IPQ_GPIO_PINS(38);
128 DECLARE_IPQ_GPIO_PINS(39);
129 DECLARE_IPQ_GPIO_PINS(40);
130 DECLARE_IPQ_GPIO_PINS(41);
131 DECLARE_IPQ_GPIO_PINS(42);
132 DECLARE_IPQ_GPIO_PINS(43);
133 DECLARE_IPQ_GPIO_PINS(44);
134 DECLARE_IPQ_GPIO_PINS(45);
135 DECLARE_IPQ_GPIO_PINS(46);
136 DECLARE_IPQ_GPIO_PINS(47);
137 DECLARE_IPQ_GPIO_PINS(48);
138 DECLARE_IPQ_GPIO_PINS(49);
139 DECLARE_IPQ_GPIO_PINS(50);
140 DECLARE_IPQ_GPIO_PINS(51);
141 DECLARE_IPQ_GPIO_PINS(52);
142 DECLARE_IPQ_GPIO_PINS(53);
143 DECLARE_IPQ_GPIO_PINS(54);
144 DECLARE_IPQ_GPIO_PINS(55);
145 DECLARE_IPQ_GPIO_PINS(56);
146 DECLARE_IPQ_GPIO_PINS(57);
147 DECLARE_IPQ_GPIO_PINS(58);
148 DECLARE_IPQ_GPIO_PINS(59);
149 DECLARE_IPQ_GPIO_PINS(60);
150 DECLARE_IPQ_GPIO_PINS(61);
151 DECLARE_IPQ_GPIO_PINS(62);
152 DECLARE_IPQ_GPIO_PINS(63);
153 DECLARE_IPQ_GPIO_PINS(64);
154 DECLARE_IPQ_GPIO_PINS(65);
155 DECLARE_IPQ_GPIO_PINS(66);
156 DECLARE_IPQ_GPIO_PINS(67);
157 DECLARE_IPQ_GPIO_PINS(68);
158 
159 static const unsigned int sdc3_clk_pins[] = { 69 };
160 static const unsigned int sdc3_cmd_pins[] = { 70 };
161 static const unsigned int sdc3_data_pins[] = { 71 };
162 
163 #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10) \
164 	{						\
165 		.grp = PINCTRL_PINGROUP("gpio" #id, 	\
166 			gpio##id##_pins, 		\
167 			ARRAY_SIZE(gpio##id##_pins)),	\
168 		.funcs = (int[]){			\
169 			IPQ_MUX_gpio,			\
170 			IPQ_MUX_##f1,			\
171 			IPQ_MUX_##f2,			\
172 			IPQ_MUX_##f3,			\
173 			IPQ_MUX_##f4,			\
174 			IPQ_MUX_##f5,			\
175 			IPQ_MUX_##f6,			\
176 			IPQ_MUX_##f7,			\
177 			IPQ_MUX_##f8,			\
178 			IPQ_MUX_##f9,			\
179 			IPQ_MUX_##f10,			\
180 		},					\
181 		.nfuncs = 11,				\
182 		.ctl_reg = 0x1000 + 0x10 * id,		\
183 		.io_reg = 0x1004 + 0x10 * id,		\
184 		.intr_cfg_reg = 0x1008 + 0x10 * id,	\
185 		.intr_status_reg = 0x100c + 0x10 * id,	\
186 		.intr_target_reg = 0x400 + 0x4 * id,	\
187 		.mux_bit = 2,				\
188 		.pull_bit = 0,				\
189 		.drv_bit = 6,				\
190 		.oe_bit = 9,				\
191 		.in_bit = 0,				\
192 		.out_bit = 1,				\
193 		.intr_enable_bit = 0,			\
194 		.intr_status_bit = 0,			\
195 		.intr_ack_high = 1,			\
196 		.intr_target_bit = 0,			\
197 		.intr_target_kpss_val = 4,		\
198 		.intr_raw_status_bit = 3,		\
199 		.intr_polarity_bit = 1,			\
200 		.intr_detection_bit = 2,		\
201 		.intr_detection_width = 1,		\
202 	}
203 
204 #define SDC_PINGROUP(pg_name, ctl, pull, drv)		\
205 	{						\
206 		.grp = PINCTRL_PINGROUP(#pg_name, 	\
207 			pg_name##_pins, 		\
208 			ARRAY_SIZE(pg_name##_pins)),	\
209 		.ctl_reg = ctl,                         \
210 		.io_reg = 0,                            \
211 		.intr_cfg_reg = 0,                      \
212 		.intr_status_reg = 0,                   \
213 		.intr_target_reg = 0,                   \
214 		.mux_bit = -1,                          \
215 		.pull_bit = pull,                       \
216 		.drv_bit = drv,                         \
217 		.oe_bit = -1,                           \
218 		.in_bit = -1,                           \
219 		.out_bit = -1,                          \
220 		.intr_enable_bit = -1,                  \
221 		.intr_status_bit = -1,                  \
222 		.intr_target_bit = -1,                  \
223 		.intr_target_kpss_val = -1,		\
224 		.intr_raw_status_bit = -1,              \
225 		.intr_polarity_bit = -1,                \
226 		.intr_detection_bit = -1,               \
227 		.intr_detection_width = -1,             \
228 	}
229 
230 enum ipq8064_functions {
231 	IPQ_MUX_gpio,
232 	IPQ_MUX_mdio,
233 	IPQ_MUX_mi2s,
234 	IPQ_MUX_pdm,
235 	IPQ_MUX_ssbi,
236 	IPQ_MUX_spmi,
237 	IPQ_MUX_audio_pcm,
238 	IPQ_MUX_gsbi1,
239 	IPQ_MUX_gsbi2,
240 	IPQ_MUX_gsbi4,
241 	IPQ_MUX_gsbi5,
242 	IPQ_MUX_gsbi5_spi_cs1,
243 	IPQ_MUX_gsbi5_spi_cs2,
244 	IPQ_MUX_gsbi5_spi_cs3,
245 	IPQ_MUX_gsbi6,
246 	IPQ_MUX_gsbi7,
247 	IPQ_MUX_nss_spi,
248 	IPQ_MUX_sdc1,
249 	IPQ_MUX_spdif,
250 	IPQ_MUX_nand,
251 	IPQ_MUX_tsif1,
252 	IPQ_MUX_tsif2,
253 	IPQ_MUX_usb_fs_n,
254 	IPQ_MUX_usb_fs,
255 	IPQ_MUX_usb2_hsic,
256 	IPQ_MUX_rgmii2,
257 	IPQ_MUX_sata,
258 	IPQ_MUX_pcie1_rst,
259 	IPQ_MUX_pcie1_prsnt,
260 	IPQ_MUX_pcie1_pwrflt,
261 	IPQ_MUX_pcie1_pwren_n,
262 	IPQ_MUX_pcie1_pwren,
263 	IPQ_MUX_pcie1_clk_req,
264 	IPQ_MUX_pcie2_rst,
265 	IPQ_MUX_pcie2_prsnt,
266 	IPQ_MUX_pcie2_pwrflt,
267 	IPQ_MUX_pcie2_pwren_n,
268 	IPQ_MUX_pcie2_pwren,
269 	IPQ_MUX_pcie2_clk_req,
270 	IPQ_MUX_pcie3_rst,
271 	IPQ_MUX_pcie3_prsnt,
272 	IPQ_MUX_pcie3_pwrflt,
273 	IPQ_MUX_pcie3_pwren_n,
274 	IPQ_MUX_pcie3_pwren,
275 	IPQ_MUX_pcie3_clk_req,
276 	IPQ_MUX_ps_hold,
277 	IPQ_MUX_NA,
278 };
279 
280 static const char * const gpio_groups[] = {
281 	"gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
282 	"gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
283 	"gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
284 	"gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
285 	"gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
286 	"gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
287 	"gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
288 	"gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
289 	"gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
290 	"gpio64", "gpio65", "gpio66", "gpio67", "gpio68"
291 };
292 
293 static const char * const mdio_groups[] = {
294 	"gpio0", "gpio1", "gpio2", "gpio10", "gpio11", "gpio66",
295 };
296 
297 static const char * const mi2s_groups[] = {
298 	"gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32",
299 	"gpio33", "gpio55", "gpio56", "gpio57", "gpio58",
300 };
301 
302 static const char * const pdm_groups[] = {
303 	"gpio3", "gpio16", "gpio17", "gpio22", "gpio30", "gpio31",
304 	"gpio34", "gpio35", "gpio52", "gpio55", "gpio56", "gpio58",
305 	"gpio59",
306 };
307 
308 static const char * const ssbi_groups[] = {
309 	"gpio10", "gpio11",
310 };
311 
312 static const char * const spmi_groups[] = {
313 	"gpio10", "gpio11",
314 };
315 
316 static const char * const audio_pcm_groups[] = {
317 	"gpio14", "gpio15", "gpio16", "gpio17",
318 };
319 
320 static const char * const gsbi1_groups[] = {
321 	"gpio51", "gpio52", "gpio53", "gpio54",
322 };
323 
324 static const char * const gsbi2_groups[] = {
325 	"gpio22", "gpio23", "gpio24", "gpio25",
326 };
327 
328 static const char * const gsbi4_groups[] = {
329 	"gpio10", "gpio11", "gpio12", "gpio13",
330 };
331 
332 static const char * const gsbi5_groups[] = {
333 	"gpio18", "gpio19", "gpio20", "gpio21",
334 };
335 
336 static const char * const gsbi5_spi_cs1_groups[] = {
337 	"gpio6", "gpio61",
338 };
339 
340 static const char * const gsbi5_spi_cs2_groups[] = {
341 	"gpio7", "gpio62",
342 };
343 
344 static const char * const gsbi5_spi_cs3_groups[] = {
345 	"gpio2",
346 };
347 
348 static const char * const gsbi6_groups[] = {
349 	"gpio27", "gpio28", "gpio29", "gpio30", "gpio55", "gpio56",
350 	"gpio57", "gpio58",
351 };
352 
353 static const char * const gsbi7_groups[] = {
354 	"gpio6", "gpio7", "gpio8", "gpio9",
355 };
356 
357 static const char * const nss_spi_groups[] = {
358 	"gpio14", "gpio15", "gpio16", "gpio17", "gpio55", "gpio56",
359 	"gpio57", "gpio58",
360 };
361 
362 static const char * const sdc1_groups[] = {
363 	"gpio38", "gpio39", "gpio40", "gpio41", "gpio42", "gpio43",
364 	"gpio44", "gpio45", "gpio46", "gpio47",
365 };
366 
367 static const char * const spdif_groups[] = {
368 	"gpio10", "gpio48",
369 };
370 
371 static const char * const nand_groups[] = {
372 	"gpio34", "gpio35", "gpio36", "gpio37", "gpio38", "gpio39",
373 	"gpio40", "gpio41", "gpio42", "gpio43", "gpio44", "gpio45",
374 	"gpio46", "gpio47",
375 };
376 
377 static const char * const tsif1_groups[] = {
378 	"gpio55", "gpio56", "gpio57", "gpio58",
379 };
380 
381 static const char * const tsif2_groups[] = {
382 	"gpio59", "gpio60", "gpio61", "gpio62",
383 };
384 
385 static const char * const usb_fs_n_groups[] = {
386 	"gpio6",
387 };
388 
389 static const char * const usb_fs_groups[] = {
390 	"gpio6", "gpio7", "gpio8",
391 };
392 
393 static const char * const usb2_hsic_groups[] = {
394 	"gpio67", "gpio68",
395 };
396 
397 static const char * const rgmii2_groups[] = {
398 	"gpio2", "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32",
399 	"gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62", "gpio66",
400 };
401 
402 static const char * const sata_groups[] = {
403 	"gpio10",
404 };
405 
406 static const char * const pcie1_rst_groups[] = {
407 	"gpio3",
408 };
409 
410 static const char * const pcie1_prsnt_groups[] = {
411 	"gpio3", "gpio11",
412 };
413 
414 static const char * const pcie1_pwren_n_groups[] = {
415 	"gpio4", "gpio12",
416 };
417 
418 static const char * const pcie1_pwren_groups[] = {
419 	"gpio4", "gpio12",
420 };
421 
422 static const char * const pcie1_pwrflt_groups[] = {
423 	"gpio5", "gpio13",
424 };
425 
426 static const char * const pcie1_clk_req_groups[] = {
427 	"gpio5",
428 };
429 
430 static const char * const pcie2_rst_groups[] = {
431 	"gpio48",
432 };
433 
434 static const char * const pcie2_prsnt_groups[] = {
435 	"gpio11", "gpio48",
436 };
437 
438 static const char * const pcie2_pwren_n_groups[] = {
439 	"gpio12", "gpio49",
440 };
441 
442 static const char * const pcie2_pwren_groups[] = {
443 	"gpio12", "gpio49",
444 };
445 
446 static const char * const pcie2_pwrflt_groups[] = {
447 	"gpio13", "gpio50",
448 };
449 
450 static const char * const pcie2_clk_req_groups[] = {
451 	"gpio50",
452 };
453 
454 static const char * const pcie3_rst_groups[] = {
455 	"gpio63",
456 };
457 
458 static const char * const pcie3_prsnt_groups[] = {
459 	"gpio11",
460 };
461 
462 static const char * const pcie3_pwren_n_groups[] = {
463 	"gpio12",
464 };
465 
466 static const char * const pcie3_pwren_groups[] = {
467 	"gpio12",
468 };
469 
470 static const char * const pcie3_pwrflt_groups[] = {
471 	"gpio13",
472 };
473 
474 static const char * const pcie3_clk_req_groups[] = {
475 	"gpio65",
476 };
477 
478 static const char * const ps_hold_groups[] = {
479 	"gpio26",
480 };
481 
482 static const struct pinfunction ipq8064_functions[] = {
483 	IPQ_PIN_FUNCTION(gpio),
484 	IPQ_PIN_FUNCTION(mdio),
485 	IPQ_PIN_FUNCTION(ssbi),
486 	IPQ_PIN_FUNCTION(spmi),
487 	IPQ_PIN_FUNCTION(mi2s),
488 	IPQ_PIN_FUNCTION(pdm),
489 	IPQ_PIN_FUNCTION(audio_pcm),
490 	IPQ_PIN_FUNCTION(gsbi1),
491 	IPQ_PIN_FUNCTION(gsbi2),
492 	IPQ_PIN_FUNCTION(gsbi4),
493 	IPQ_PIN_FUNCTION(gsbi5),
494 	IPQ_PIN_FUNCTION(gsbi5_spi_cs1),
495 	IPQ_PIN_FUNCTION(gsbi5_spi_cs2),
496 	IPQ_PIN_FUNCTION(gsbi5_spi_cs3),
497 	IPQ_PIN_FUNCTION(gsbi6),
498 	IPQ_PIN_FUNCTION(gsbi7),
499 	IPQ_PIN_FUNCTION(nss_spi),
500 	IPQ_PIN_FUNCTION(sdc1),
501 	IPQ_PIN_FUNCTION(spdif),
502 	IPQ_PIN_FUNCTION(nand),
503 	IPQ_PIN_FUNCTION(tsif1),
504 	IPQ_PIN_FUNCTION(tsif2),
505 	IPQ_PIN_FUNCTION(usb_fs_n),
506 	IPQ_PIN_FUNCTION(usb_fs),
507 	IPQ_PIN_FUNCTION(usb2_hsic),
508 	IPQ_PIN_FUNCTION(rgmii2),
509 	IPQ_PIN_FUNCTION(sata),
510 	IPQ_PIN_FUNCTION(pcie1_rst),
511 	IPQ_PIN_FUNCTION(pcie1_prsnt),
512 	IPQ_PIN_FUNCTION(pcie1_pwren_n),
513 	IPQ_PIN_FUNCTION(pcie1_pwren),
514 	IPQ_PIN_FUNCTION(pcie1_pwrflt),
515 	IPQ_PIN_FUNCTION(pcie1_clk_req),
516 	IPQ_PIN_FUNCTION(pcie2_rst),
517 	IPQ_PIN_FUNCTION(pcie2_prsnt),
518 	IPQ_PIN_FUNCTION(pcie2_pwren_n),
519 	IPQ_PIN_FUNCTION(pcie2_pwren),
520 	IPQ_PIN_FUNCTION(pcie2_pwrflt),
521 	IPQ_PIN_FUNCTION(pcie2_clk_req),
522 	IPQ_PIN_FUNCTION(pcie3_rst),
523 	IPQ_PIN_FUNCTION(pcie3_prsnt),
524 	IPQ_PIN_FUNCTION(pcie3_pwren_n),
525 	IPQ_PIN_FUNCTION(pcie3_pwren),
526 	IPQ_PIN_FUNCTION(pcie3_pwrflt),
527 	IPQ_PIN_FUNCTION(pcie3_clk_req),
528 	IPQ_PIN_FUNCTION(ps_hold),
529 };
530 
531 static const struct msm_pingroup ipq8064_groups[] = {
532 	PINGROUP(0, mdio, NA, NA, NA, NA, NA, NA, NA, NA, NA),
533 	PINGROUP(1, mdio, NA, NA, NA, NA, NA, NA, NA, NA, NA),
534 	PINGROUP(2, gsbi5_spi_cs3, rgmii2, mdio, NA, NA, NA, NA, NA, NA, NA),
535 	PINGROUP(3, pcie1_rst, pcie1_prsnt, pdm, NA, NA, NA, NA, NA, NA, NA),
536 	PINGROUP(4, pcie1_pwren_n, pcie1_pwren, NA, NA, NA, NA, NA, NA, NA, NA),
537 	PINGROUP(5, pcie1_clk_req, pcie1_pwrflt, NA, NA, NA, NA, NA, NA, NA, NA),
538 	PINGROUP(6, gsbi7, usb_fs, gsbi5_spi_cs1, usb_fs_n, NA, NA, NA, NA, NA, NA),
539 	PINGROUP(7, gsbi7, usb_fs, gsbi5_spi_cs2, NA, NA, NA, NA, NA, NA, NA),
540 	PINGROUP(8, gsbi7, usb_fs, NA, NA, NA, NA, NA, NA, NA, NA),
541 	PINGROUP(9, gsbi7, NA, NA, NA, NA, NA, NA, NA, NA, NA),
542 	PINGROUP(10, gsbi4, spdif, sata, ssbi, mdio, spmi, NA, NA, NA, NA),
543 	PINGROUP(11, gsbi4, pcie2_prsnt, pcie1_prsnt, pcie3_prsnt, ssbi, mdio, spmi, NA, NA, NA),
544 	PINGROUP(12, gsbi4, pcie2_pwren_n, pcie1_pwren_n, pcie3_pwren_n, pcie2_pwren, pcie1_pwren, pcie3_pwren, NA, NA, NA),
545 	PINGROUP(13, gsbi4, pcie2_pwrflt, pcie1_pwrflt, pcie3_pwrflt, NA, NA, NA, NA, NA, NA),
546 	PINGROUP(14, audio_pcm, nss_spi, NA, NA, NA, NA, NA, NA, NA, NA),
547 	PINGROUP(15, audio_pcm, nss_spi, NA, NA, NA, NA, NA, NA, NA, NA),
548 	PINGROUP(16, audio_pcm, nss_spi, pdm, NA, NA, NA, NA, NA, NA, NA),
549 	PINGROUP(17, audio_pcm, nss_spi, pdm, NA, NA, NA, NA, NA, NA, NA),
550 	PINGROUP(18, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA, NA),
551 	PINGROUP(19, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA, NA),
552 	PINGROUP(20, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA, NA),
553 	PINGROUP(21, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA, NA),
554 	PINGROUP(22, gsbi2, pdm, NA, NA, NA, NA, NA, NA, NA, NA),
555 	PINGROUP(23, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA),
556 	PINGROUP(24, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA),
557 	PINGROUP(25, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA),
558 	PINGROUP(26, ps_hold, NA, NA, NA, NA, NA, NA, NA, NA, NA),
559 	PINGROUP(27, mi2s, rgmii2, gsbi6, NA, NA, NA, NA, NA, NA, NA),
560 	PINGROUP(28, mi2s, rgmii2, gsbi6, NA, NA, NA, NA, NA, NA, NA),
561 	PINGROUP(29, mi2s, rgmii2, gsbi6, NA, NA, NA, NA, NA, NA, NA),
562 	PINGROUP(30, mi2s, rgmii2, gsbi6, pdm, NA, NA, NA, NA, NA, NA),
563 	PINGROUP(31, mi2s, rgmii2, pdm, NA, NA, NA, NA, NA, NA, NA),
564 	PINGROUP(32, mi2s, rgmii2, NA, NA, NA, NA, NA, NA, NA, NA),
565 	PINGROUP(33, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA),
566 	PINGROUP(34, nand, pdm, NA, NA, NA, NA, NA, NA, NA, NA),
567 	PINGROUP(35, nand, pdm, NA, NA, NA, NA, NA, NA, NA, NA),
568 	PINGROUP(36, nand, NA, NA, NA, NA, NA, NA, NA, NA, NA),
569 	PINGROUP(37, nand, NA, NA, NA, NA, NA, NA, NA, NA, NA),
570 	PINGROUP(38, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
571 	PINGROUP(39, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
572 	PINGROUP(40, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
573 	PINGROUP(41, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
574 	PINGROUP(42, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
575 	PINGROUP(43, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
576 	PINGROUP(44, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
577 	PINGROUP(45, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
578 	PINGROUP(46, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
579 	PINGROUP(47, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
580 	PINGROUP(48, pcie2_rst, spdif, NA, NA, NA, NA, NA, NA, NA, NA),
581 	PINGROUP(49, pcie2_pwren_n, pcie2_pwren, NA, NA, NA, NA, NA, NA, NA, NA),
582 	PINGROUP(50, pcie2_clk_req, pcie2_pwrflt, NA, NA, NA, NA, NA, NA, NA, NA),
583 	PINGROUP(51, gsbi1, rgmii2, NA, NA, NA, NA, NA, NA, NA, NA),
584 	PINGROUP(52, gsbi1, rgmii2, pdm, NA, NA, NA, NA, NA, NA, NA),
585 	PINGROUP(53, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA),
586 	PINGROUP(54, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA),
587 	PINGROUP(55, tsif1, mi2s, gsbi6, pdm, nss_spi, NA, NA, NA, NA, NA),
588 	PINGROUP(56, tsif1, mi2s, gsbi6, pdm, nss_spi, NA, NA, NA, NA, NA),
589 	PINGROUP(57, tsif1, mi2s, gsbi6, nss_spi, NA, NA, NA, NA, NA, NA),
590 	PINGROUP(58, tsif1, mi2s, gsbi6, pdm, nss_spi, NA, NA, NA, NA, NA),
591 	PINGROUP(59, tsif2, rgmii2, pdm, NA, NA, NA, NA, NA, NA, NA),
592 	PINGROUP(60, tsif2, rgmii2, NA, NA, NA, NA, NA, NA, NA, NA),
593 	PINGROUP(61, tsif2, rgmii2, gsbi5_spi_cs1, NA, NA, NA, NA, NA, NA, NA),
594 	PINGROUP(62, tsif2, rgmii2, gsbi5_spi_cs2, NA, NA, NA, NA, NA, NA, NA),
595 	PINGROUP(63, pcie3_rst, NA, NA, NA, NA, NA, NA, NA, NA, NA),
596 	PINGROUP(64, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
597 	PINGROUP(65, pcie3_clk_req, NA, NA, NA, NA, NA, NA, NA, NA, NA),
598 	PINGROUP(66, rgmii2, mdio, NA, NA, NA, NA, NA, NA, NA, NA),
599 	PINGROUP(67, usb2_hsic, NA, NA, NA, NA, NA, NA, NA, NA, NA),
600 	PINGROUP(68, usb2_hsic, NA, NA, NA, NA, NA, NA, NA, NA, NA),
601 	SDC_PINGROUP(sdc3_clk, 0x204a, 14, 6),
602 	SDC_PINGROUP(sdc3_cmd, 0x204a, 11, 3),
603 	SDC_PINGROUP(sdc3_data, 0x204a, 9, 0),
604 };
605 
606 #define NUM_GPIO_PINGROUPS 69
607 
608 static const struct msm_pinctrl_soc_data ipq8064_pinctrl = {
609 	.pins = ipq8064_pins,
610 	.npins = ARRAY_SIZE(ipq8064_pins),
611 	.functions = ipq8064_functions,
612 	.nfunctions = ARRAY_SIZE(ipq8064_functions),
613 	.groups = ipq8064_groups,
614 	.ngroups = ARRAY_SIZE(ipq8064_groups),
615 	.ngpios = NUM_GPIO_PINGROUPS,
616 };
617 
618 static int ipq8064_pinctrl_probe(struct platform_device *pdev)
619 {
620 	return msm_pinctrl_probe(pdev, &ipq8064_pinctrl);
621 }
622 
623 static const struct of_device_id ipq8064_pinctrl_of_match[] = {
624 	{ .compatible = "qcom,ipq8064-pinctrl", },
625 	{ },
626 };
627 
628 static struct platform_driver ipq8064_pinctrl_driver = {
629 	.driver = {
630 		.name = "ipq8064-pinctrl",
631 		.of_match_table = ipq8064_pinctrl_of_match,
632 	},
633 	.probe = ipq8064_pinctrl_probe,
634 	.remove = msm_pinctrl_remove,
635 };
636 
637 static int __init ipq8064_pinctrl_init(void)
638 {
639 	return platform_driver_register(&ipq8064_pinctrl_driver);
640 }
641 arch_initcall(ipq8064_pinctrl_init);
642 
643 static void __exit ipq8064_pinctrl_exit(void)
644 {
645 	platform_driver_unregister(&ipq8064_pinctrl_driver);
646 }
647 module_exit(ipq8064_pinctrl_exit);
648 
649 MODULE_AUTHOR("Andy Gross <agross@codeaurora.org>");
650 MODULE_DESCRIPTION("Qualcomm IPQ8064 pinctrl driver");
651 MODULE_LICENSE("GPL v2");
652 MODULE_DEVICE_TABLE(of, ipq8064_pinctrl_of_match);
653