1 /* 2 * Zynq pin controller 3 * 4 * Copyright (C) 2014 Xilinx 5 * 6 * Sören Brinkmann <soren.brinkmann@xilinx.com> 7 * 8 * This program is free software: you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation, either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program. If not, see <http://www.gnu.org/licenses/>. 20 */ 21 #include <linux/io.h> 22 #include <linux/mfd/syscon.h> 23 #include <linux/module.h> 24 #include <linux/of.h> 25 #include <linux/platform_device.h> 26 #include <linux/pinctrl/pinctrl.h> 27 #include <linux/pinctrl/pinmux.h> 28 #include <linux/pinctrl/pinconf.h> 29 #include <linux/pinctrl/pinconf-generic.h> 30 #include <linux/regmap.h> 31 #include "pinctrl-utils.h" 32 #include "core.h" 33 34 #define ZYNQ_NUM_MIOS 54 35 36 #define ZYNQ_PCTRL_MIO_MST_TRI0 0x10c 37 #define ZYNQ_PCTRL_MIO_MST_TRI1 0x110 38 39 #define ZYNQ_PINMUX_MUX_SHIFT 1 40 #define ZYNQ_PINMUX_MUX_MASK (0x7f << ZYNQ_PINMUX_MUX_SHIFT) 41 42 /** 43 * struct zynq_pinctrl - driver data 44 * @pctrl: Pinctrl device 45 * @syscon: Syscon regmap 46 * @pctrl_offset: Offset for pinctrl into the @syscon space 47 * @groups: Pingroups 48 * @ngroupos: Number of @groups 49 * @funcs: Pinmux functions 50 * @nfuncs: Number of @funcs 51 */ 52 struct zynq_pinctrl { 53 struct pinctrl_dev *pctrl; 54 struct regmap *syscon; 55 u32 pctrl_offset; 56 const struct zynq_pctrl_group *groups; 57 unsigned int ngroups; 58 const struct zynq_pinmux_function *funcs; 59 unsigned int nfuncs; 60 }; 61 62 struct zynq_pctrl_group { 63 const char *name; 64 const unsigned int *pins; 65 const unsigned npins; 66 }; 67 68 /** 69 * struct zynq_pinmux_function - a pinmux function 70 * @name: Name of the pinmux function. 71 * @groups: List of pingroups for this function. 72 * @ngroups: Number of entries in @groups. 73 * @mux_val: Selector for this function 74 * @mux: Offset of function specific mux 75 * @mux_mask: Mask for function specific selector 76 * @mux_shift: Shift for function specific selector 77 */ 78 struct zynq_pinmux_function { 79 const char *name; 80 const char * const *groups; 81 unsigned int ngroups; 82 unsigned int mux_val; 83 u32 mux; 84 u32 mux_mask; 85 u8 mux_shift; 86 }; 87 88 enum zynq_pinmux_functions { 89 ZYNQ_PMUX_can0, 90 ZYNQ_PMUX_can1, 91 ZYNQ_PMUX_ethernet0, 92 ZYNQ_PMUX_ethernet1, 93 ZYNQ_PMUX_gpio0, 94 ZYNQ_PMUX_i2c0, 95 ZYNQ_PMUX_i2c1, 96 ZYNQ_PMUX_mdio0, 97 ZYNQ_PMUX_mdio1, 98 ZYNQ_PMUX_qspi0, 99 ZYNQ_PMUX_qspi1, 100 ZYNQ_PMUX_qspi_fbclk, 101 ZYNQ_PMUX_qspi_cs1, 102 ZYNQ_PMUX_spi0, 103 ZYNQ_PMUX_spi1, 104 ZYNQ_PMUX_spi0_ss, 105 ZYNQ_PMUX_spi1_ss, 106 ZYNQ_PMUX_sdio0, 107 ZYNQ_PMUX_sdio0_pc, 108 ZYNQ_PMUX_sdio0_cd, 109 ZYNQ_PMUX_sdio0_wp, 110 ZYNQ_PMUX_sdio1, 111 ZYNQ_PMUX_sdio1_pc, 112 ZYNQ_PMUX_sdio1_cd, 113 ZYNQ_PMUX_sdio1_wp, 114 ZYNQ_PMUX_smc0_nor, 115 ZYNQ_PMUX_smc0_nor_cs1, 116 ZYNQ_PMUX_smc0_nor_addr25, 117 ZYNQ_PMUX_smc0_nand, 118 ZYNQ_PMUX_ttc0, 119 ZYNQ_PMUX_ttc1, 120 ZYNQ_PMUX_uart0, 121 ZYNQ_PMUX_uart1, 122 ZYNQ_PMUX_usb0, 123 ZYNQ_PMUX_usb1, 124 ZYNQ_PMUX_swdt0, 125 ZYNQ_PMUX_MAX_FUNC 126 }; 127 128 static const struct pinctrl_pin_desc zynq_pins[] = { 129 PINCTRL_PIN(0, "MIO0"), 130 PINCTRL_PIN(1, "MIO1"), 131 PINCTRL_PIN(2, "MIO2"), 132 PINCTRL_PIN(3, "MIO3"), 133 PINCTRL_PIN(4, "MIO4"), 134 PINCTRL_PIN(5, "MIO5"), 135 PINCTRL_PIN(6, "MIO6"), 136 PINCTRL_PIN(7, "MIO7"), 137 PINCTRL_PIN(8, "MIO8"), 138 PINCTRL_PIN(9, "MIO9"), 139 PINCTRL_PIN(10, "MIO10"), 140 PINCTRL_PIN(11, "MIO11"), 141 PINCTRL_PIN(12, "MIO12"), 142 PINCTRL_PIN(13, "MIO13"), 143 PINCTRL_PIN(14, "MIO14"), 144 PINCTRL_PIN(15, "MIO15"), 145 PINCTRL_PIN(16, "MIO16"), 146 PINCTRL_PIN(17, "MIO17"), 147 PINCTRL_PIN(18, "MIO18"), 148 PINCTRL_PIN(19, "MIO19"), 149 PINCTRL_PIN(20, "MIO20"), 150 PINCTRL_PIN(21, "MIO21"), 151 PINCTRL_PIN(22, "MIO22"), 152 PINCTRL_PIN(23, "MIO23"), 153 PINCTRL_PIN(24, "MIO24"), 154 PINCTRL_PIN(25, "MIO25"), 155 PINCTRL_PIN(26, "MIO26"), 156 PINCTRL_PIN(27, "MIO27"), 157 PINCTRL_PIN(28, "MIO28"), 158 PINCTRL_PIN(29, "MIO29"), 159 PINCTRL_PIN(30, "MIO30"), 160 PINCTRL_PIN(31, "MIO31"), 161 PINCTRL_PIN(32, "MIO32"), 162 PINCTRL_PIN(33, "MIO33"), 163 PINCTRL_PIN(34, "MIO34"), 164 PINCTRL_PIN(35, "MIO35"), 165 PINCTRL_PIN(36, "MIO36"), 166 PINCTRL_PIN(37, "MIO37"), 167 PINCTRL_PIN(38, "MIO38"), 168 PINCTRL_PIN(39, "MIO39"), 169 PINCTRL_PIN(40, "MIO40"), 170 PINCTRL_PIN(41, "MIO41"), 171 PINCTRL_PIN(42, "MIO42"), 172 PINCTRL_PIN(43, "MIO43"), 173 PINCTRL_PIN(44, "MIO44"), 174 PINCTRL_PIN(45, "MIO45"), 175 PINCTRL_PIN(46, "MIO46"), 176 PINCTRL_PIN(47, "MIO47"), 177 PINCTRL_PIN(48, "MIO48"), 178 PINCTRL_PIN(49, "MIO49"), 179 PINCTRL_PIN(50, "MIO50"), 180 PINCTRL_PIN(51, "MIO51"), 181 PINCTRL_PIN(52, "MIO52"), 182 PINCTRL_PIN(53, "MIO53"), 183 PINCTRL_PIN(54, "EMIO_SD0_WP"), 184 PINCTRL_PIN(55, "EMIO_SD0_CD"), 185 PINCTRL_PIN(56, "EMIO_SD1_WP"), 186 PINCTRL_PIN(57, "EMIO_SD1_CD"), 187 }; 188 189 /* pin groups */ 190 static const unsigned int ethernet0_0_pins[] = {16, 17, 18, 19, 20, 21, 22, 23, 191 24, 25, 26, 27}; 192 static const unsigned int ethernet1_0_pins[] = {28, 29, 30, 31, 32, 33, 34, 35, 193 36, 37, 38, 39}; 194 static const unsigned int mdio0_0_pins[] = {52, 53}; 195 static const unsigned int mdio1_0_pins[] = {52, 53}; 196 static const unsigned int qspi0_0_pins[] = {1, 2, 3, 4, 5, 6}; 197 198 static const unsigned int qspi1_0_pins[] = {9, 10, 11, 12, 13}; 199 static const unsigned int qspi_cs1_pins[] = {0}; 200 static const unsigned int qspi_fbclk_pins[] = {8}; 201 static const unsigned int spi0_0_pins[] = {16, 17, 21}; 202 static const unsigned int spi0_0_ss0_pins[] = {18}; 203 static const unsigned int spi0_0_ss1_pins[] = {19}; 204 static const unsigned int spi0_0_ss2_pins[] = {20,}; 205 static const unsigned int spi0_1_pins[] = {28, 29, 33}; 206 static const unsigned int spi0_1_ss0_pins[] = {30}; 207 static const unsigned int spi0_1_ss1_pins[] = {31}; 208 static const unsigned int spi0_1_ss2_pins[] = {32}; 209 static const unsigned int spi0_2_pins[] = {40, 41, 45}; 210 static const unsigned int spi0_2_ss0_pins[] = {42}; 211 static const unsigned int spi0_2_ss1_pins[] = {43}; 212 static const unsigned int spi0_2_ss2_pins[] = {44}; 213 static const unsigned int spi1_0_pins[] = {10, 11, 12}; 214 static const unsigned int spi1_0_ss0_pins[] = {13}; 215 static const unsigned int spi1_0_ss1_pins[] = {14}; 216 static const unsigned int spi1_0_ss2_pins[] = {15}; 217 static const unsigned int spi1_1_pins[] = {22, 23, 24}; 218 static const unsigned int spi1_1_ss0_pins[] = {25}; 219 static const unsigned int spi1_1_ss1_pins[] = {26}; 220 static const unsigned int spi1_1_ss2_pins[] = {27}; 221 static const unsigned int spi1_2_pins[] = {34, 35, 36}; 222 static const unsigned int spi1_2_ss0_pins[] = {37}; 223 static const unsigned int spi1_2_ss1_pins[] = {38}; 224 static const unsigned int spi1_2_ss2_pins[] = {39}; 225 static const unsigned int spi1_3_pins[] = {46, 47, 48, 49}; 226 static const unsigned int spi1_3_ss0_pins[] = {49}; 227 static const unsigned int spi1_3_ss1_pins[] = {50}; 228 static const unsigned int spi1_3_ss2_pins[] = {51}; 229 230 static const unsigned int sdio0_0_pins[] = {16, 17, 18, 19, 20, 21}; 231 static const unsigned int sdio0_1_pins[] = {28, 29, 30, 31, 32, 33}; 232 static const unsigned int sdio0_2_pins[] = {40, 41, 42, 43, 44, 45}; 233 static const unsigned int sdio1_0_pins[] = {10, 11, 12, 13, 14, 15}; 234 static const unsigned int sdio1_1_pins[] = {22, 23, 24, 25, 26, 27}; 235 static const unsigned int sdio1_2_pins[] = {34, 35, 36, 37, 38, 39}; 236 static const unsigned int sdio1_3_pins[] = {46, 47, 48, 49, 40, 51}; 237 static const unsigned int sdio0_emio_wp_pins[] = {54}; 238 static const unsigned int sdio0_emio_cd_pins[] = {55}; 239 static const unsigned int sdio1_emio_wp_pins[] = {56}; 240 static const unsigned int sdio1_emio_cd_pins[] = {57}; 241 static const unsigned int smc0_nor_pins[] = {0, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13, 242 15, 16, 17, 18, 19, 20, 21, 22, 23, 243 24, 25, 26, 27, 28, 29, 30, 31, 32, 244 33, 34, 35, 36, 37, 38, 39}; 245 static const unsigned int smc0_nor_cs1_pins[] = {1}; 246 static const unsigned int smc0_nor_addr25_pins[] = {1}; 247 static const unsigned int smc0_nand_pins[] = {0, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 248 12, 13, 14, 16, 17, 18, 19, 20, 249 21, 22, 23}; 250 /* Note: CAN MIO clock inputs are modeled in the clock framework */ 251 static const unsigned int can0_0_pins[] = {10, 11}; 252 static const unsigned int can0_1_pins[] = {14, 15}; 253 static const unsigned int can0_2_pins[] = {18, 19}; 254 static const unsigned int can0_3_pins[] = {22, 23}; 255 static const unsigned int can0_4_pins[] = {26, 27}; 256 static const unsigned int can0_5_pins[] = {30, 31}; 257 static const unsigned int can0_6_pins[] = {34, 35}; 258 static const unsigned int can0_7_pins[] = {38, 39}; 259 static const unsigned int can0_8_pins[] = {42, 43}; 260 static const unsigned int can0_9_pins[] = {46, 47}; 261 static const unsigned int can0_10_pins[] = {50, 51}; 262 static const unsigned int can1_0_pins[] = {8, 9}; 263 static const unsigned int can1_1_pins[] = {12, 13}; 264 static const unsigned int can1_2_pins[] = {16, 17}; 265 static const unsigned int can1_3_pins[] = {20, 21}; 266 static const unsigned int can1_4_pins[] = {24, 25}; 267 static const unsigned int can1_5_pins[] = {28, 29}; 268 static const unsigned int can1_6_pins[] = {32, 33}; 269 static const unsigned int can1_7_pins[] = {36, 37}; 270 static const unsigned int can1_8_pins[] = {40, 41}; 271 static const unsigned int can1_9_pins[] = {44, 45}; 272 static const unsigned int can1_10_pins[] = {48, 49}; 273 static const unsigned int can1_11_pins[] = {52, 53}; 274 static const unsigned int uart0_0_pins[] = {10, 11}; 275 static const unsigned int uart0_1_pins[] = {14, 15}; 276 static const unsigned int uart0_2_pins[] = {18, 19}; 277 static const unsigned int uart0_3_pins[] = {22, 23}; 278 static const unsigned int uart0_4_pins[] = {26, 27}; 279 static const unsigned int uart0_5_pins[] = {30, 31}; 280 static const unsigned int uart0_6_pins[] = {34, 35}; 281 static const unsigned int uart0_7_pins[] = {38, 39}; 282 static const unsigned int uart0_8_pins[] = {42, 43}; 283 static const unsigned int uart0_9_pins[] = {46, 47}; 284 static const unsigned int uart0_10_pins[] = {50, 51}; 285 static const unsigned int uart1_0_pins[] = {8, 9}; 286 static const unsigned int uart1_1_pins[] = {12, 13}; 287 static const unsigned int uart1_2_pins[] = {16, 17}; 288 static const unsigned int uart1_3_pins[] = {20, 21}; 289 static const unsigned int uart1_4_pins[] = {24, 25}; 290 static const unsigned int uart1_5_pins[] = {28, 29}; 291 static const unsigned int uart1_6_pins[] = {32, 33}; 292 static const unsigned int uart1_7_pins[] = {36, 37}; 293 static const unsigned int uart1_8_pins[] = {40, 41}; 294 static const unsigned int uart1_9_pins[] = {44, 45}; 295 static const unsigned int uart1_10_pins[] = {48, 49}; 296 static const unsigned int uart1_11_pins[] = {52, 53}; 297 static const unsigned int i2c0_0_pins[] = {10, 11}; 298 static const unsigned int i2c0_1_pins[] = {14, 15}; 299 static const unsigned int i2c0_2_pins[] = {18, 19}; 300 static const unsigned int i2c0_3_pins[] = {22, 23}; 301 static const unsigned int i2c0_4_pins[] = {26, 27}; 302 static const unsigned int i2c0_5_pins[] = {30, 31}; 303 static const unsigned int i2c0_6_pins[] = {34, 35}; 304 static const unsigned int i2c0_7_pins[] = {38, 39}; 305 static const unsigned int i2c0_8_pins[] = {42, 43}; 306 static const unsigned int i2c0_9_pins[] = {46, 47}; 307 static const unsigned int i2c0_10_pins[] = {50, 51}; 308 static const unsigned int i2c1_0_pins[] = {12, 13}; 309 static const unsigned int i2c1_1_pins[] = {16, 17}; 310 static const unsigned int i2c1_2_pins[] = {20, 21}; 311 static const unsigned int i2c1_3_pins[] = {24, 25}; 312 static const unsigned int i2c1_4_pins[] = {28, 29}; 313 static const unsigned int i2c1_5_pins[] = {32, 33}; 314 static const unsigned int i2c1_6_pins[] = {36, 37}; 315 static const unsigned int i2c1_7_pins[] = {40, 41}; 316 static const unsigned int i2c1_8_pins[] = {44, 45}; 317 static const unsigned int i2c1_9_pins[] = {48, 49}; 318 static const unsigned int i2c1_10_pins[] = {52, 53}; 319 static const unsigned int ttc0_0_pins[] = {18, 19}; 320 static const unsigned int ttc0_1_pins[] = {30, 31}; 321 static const unsigned int ttc0_2_pins[] = {42, 43}; 322 static const unsigned int ttc1_0_pins[] = {16, 17}; 323 static const unsigned int ttc1_1_pins[] = {28, 29}; 324 static const unsigned int ttc1_2_pins[] = {40, 41}; 325 static const unsigned int swdt0_0_pins[] = {14, 15}; 326 static const unsigned int swdt0_1_pins[] = {26, 27}; 327 static const unsigned int swdt0_2_pins[] = {38, 39}; 328 static const unsigned int swdt0_3_pins[] = {50, 51}; 329 static const unsigned int swdt0_4_pins[] = {52, 53}; 330 static const unsigned int gpio0_0_pins[] = {0}; 331 static const unsigned int gpio0_1_pins[] = {1}; 332 static const unsigned int gpio0_2_pins[] = {2}; 333 static const unsigned int gpio0_3_pins[] = {3}; 334 static const unsigned int gpio0_4_pins[] = {4}; 335 static const unsigned int gpio0_5_pins[] = {5}; 336 static const unsigned int gpio0_6_pins[] = {6}; 337 static const unsigned int gpio0_7_pins[] = {7}; 338 static const unsigned int gpio0_8_pins[] = {8}; 339 static const unsigned int gpio0_9_pins[] = {9}; 340 static const unsigned int gpio0_10_pins[] = {10}; 341 static const unsigned int gpio0_11_pins[] = {11}; 342 static const unsigned int gpio0_12_pins[] = {12}; 343 static const unsigned int gpio0_13_pins[] = {13}; 344 static const unsigned int gpio0_14_pins[] = {14}; 345 static const unsigned int gpio0_15_pins[] = {15}; 346 static const unsigned int gpio0_16_pins[] = {16}; 347 static const unsigned int gpio0_17_pins[] = {17}; 348 static const unsigned int gpio0_18_pins[] = {18}; 349 static const unsigned int gpio0_19_pins[] = {19}; 350 static const unsigned int gpio0_20_pins[] = {20}; 351 static const unsigned int gpio0_21_pins[] = {21}; 352 static const unsigned int gpio0_22_pins[] = {22}; 353 static const unsigned int gpio0_23_pins[] = {23}; 354 static const unsigned int gpio0_24_pins[] = {24}; 355 static const unsigned int gpio0_25_pins[] = {25}; 356 static const unsigned int gpio0_26_pins[] = {26}; 357 static const unsigned int gpio0_27_pins[] = {27}; 358 static const unsigned int gpio0_28_pins[] = {28}; 359 static const unsigned int gpio0_29_pins[] = {29}; 360 static const unsigned int gpio0_30_pins[] = {30}; 361 static const unsigned int gpio0_31_pins[] = {31}; 362 static const unsigned int gpio0_32_pins[] = {32}; 363 static const unsigned int gpio0_33_pins[] = {33}; 364 static const unsigned int gpio0_34_pins[] = {34}; 365 static const unsigned int gpio0_35_pins[] = {35}; 366 static const unsigned int gpio0_36_pins[] = {36}; 367 static const unsigned int gpio0_37_pins[] = {37}; 368 static const unsigned int gpio0_38_pins[] = {38}; 369 static const unsigned int gpio0_39_pins[] = {39}; 370 static const unsigned int gpio0_40_pins[] = {40}; 371 static const unsigned int gpio0_41_pins[] = {41}; 372 static const unsigned int gpio0_42_pins[] = {42}; 373 static const unsigned int gpio0_43_pins[] = {43}; 374 static const unsigned int gpio0_44_pins[] = {44}; 375 static const unsigned int gpio0_45_pins[] = {45}; 376 static const unsigned int gpio0_46_pins[] = {46}; 377 static const unsigned int gpio0_47_pins[] = {47}; 378 static const unsigned int gpio0_48_pins[] = {48}; 379 static const unsigned int gpio0_49_pins[] = {49}; 380 static const unsigned int gpio0_50_pins[] = {50}; 381 static const unsigned int gpio0_51_pins[] = {51}; 382 static const unsigned int gpio0_52_pins[] = {52}; 383 static const unsigned int gpio0_53_pins[] = {53}; 384 static const unsigned int usb0_0_pins[] = {28, 29, 30, 31, 32, 33, 34, 35, 36, 385 37, 38, 39}; 386 static const unsigned int usb1_0_pins[] = {40, 41, 42, 43, 44, 45, 46, 47, 48, 387 49, 50, 51}; 388 389 #define DEFINE_ZYNQ_PINCTRL_GRP(nm) \ 390 { \ 391 .name = #nm "_grp", \ 392 .pins = nm ## _pins, \ 393 .npins = ARRAY_SIZE(nm ## _pins), \ 394 } 395 396 static const struct zynq_pctrl_group zynq_pctrl_groups[] = { 397 DEFINE_ZYNQ_PINCTRL_GRP(ethernet0_0), 398 DEFINE_ZYNQ_PINCTRL_GRP(ethernet1_0), 399 DEFINE_ZYNQ_PINCTRL_GRP(mdio0_0), 400 DEFINE_ZYNQ_PINCTRL_GRP(mdio1_0), 401 DEFINE_ZYNQ_PINCTRL_GRP(qspi0_0), 402 DEFINE_ZYNQ_PINCTRL_GRP(qspi1_0), 403 DEFINE_ZYNQ_PINCTRL_GRP(qspi_fbclk), 404 DEFINE_ZYNQ_PINCTRL_GRP(qspi_cs1), 405 DEFINE_ZYNQ_PINCTRL_GRP(spi0_0), 406 DEFINE_ZYNQ_PINCTRL_GRP(spi0_0_ss0), 407 DEFINE_ZYNQ_PINCTRL_GRP(spi0_0_ss1), 408 DEFINE_ZYNQ_PINCTRL_GRP(spi0_0_ss2), 409 DEFINE_ZYNQ_PINCTRL_GRP(spi0_1), 410 DEFINE_ZYNQ_PINCTRL_GRP(spi0_1_ss0), 411 DEFINE_ZYNQ_PINCTRL_GRP(spi0_1_ss1), 412 DEFINE_ZYNQ_PINCTRL_GRP(spi0_1_ss2), 413 DEFINE_ZYNQ_PINCTRL_GRP(spi0_2), 414 DEFINE_ZYNQ_PINCTRL_GRP(spi0_2_ss0), 415 DEFINE_ZYNQ_PINCTRL_GRP(spi0_2_ss1), 416 DEFINE_ZYNQ_PINCTRL_GRP(spi0_2_ss2), 417 DEFINE_ZYNQ_PINCTRL_GRP(spi1_0), 418 DEFINE_ZYNQ_PINCTRL_GRP(spi1_0_ss0), 419 DEFINE_ZYNQ_PINCTRL_GRP(spi1_0_ss1), 420 DEFINE_ZYNQ_PINCTRL_GRP(spi1_0_ss2), 421 DEFINE_ZYNQ_PINCTRL_GRP(spi1_1), 422 DEFINE_ZYNQ_PINCTRL_GRP(spi1_1_ss0), 423 DEFINE_ZYNQ_PINCTRL_GRP(spi1_1_ss1), 424 DEFINE_ZYNQ_PINCTRL_GRP(spi1_1_ss2), 425 DEFINE_ZYNQ_PINCTRL_GRP(spi1_2), 426 DEFINE_ZYNQ_PINCTRL_GRP(spi1_2_ss0), 427 DEFINE_ZYNQ_PINCTRL_GRP(spi1_2_ss1), 428 DEFINE_ZYNQ_PINCTRL_GRP(spi1_2_ss2), 429 DEFINE_ZYNQ_PINCTRL_GRP(spi1_3), 430 DEFINE_ZYNQ_PINCTRL_GRP(spi1_3_ss0), 431 DEFINE_ZYNQ_PINCTRL_GRP(spi1_3_ss1), 432 DEFINE_ZYNQ_PINCTRL_GRP(spi1_3_ss2), 433 DEFINE_ZYNQ_PINCTRL_GRP(sdio0_0), 434 DEFINE_ZYNQ_PINCTRL_GRP(sdio0_1), 435 DEFINE_ZYNQ_PINCTRL_GRP(sdio0_2), 436 DEFINE_ZYNQ_PINCTRL_GRP(sdio1_0), 437 DEFINE_ZYNQ_PINCTRL_GRP(sdio1_1), 438 DEFINE_ZYNQ_PINCTRL_GRP(sdio1_2), 439 DEFINE_ZYNQ_PINCTRL_GRP(sdio1_3), 440 DEFINE_ZYNQ_PINCTRL_GRP(sdio0_emio_wp), 441 DEFINE_ZYNQ_PINCTRL_GRP(sdio0_emio_cd), 442 DEFINE_ZYNQ_PINCTRL_GRP(sdio1_emio_wp), 443 DEFINE_ZYNQ_PINCTRL_GRP(sdio1_emio_cd), 444 DEFINE_ZYNQ_PINCTRL_GRP(smc0_nor), 445 DEFINE_ZYNQ_PINCTRL_GRP(smc0_nor_cs1), 446 DEFINE_ZYNQ_PINCTRL_GRP(smc0_nor_addr25), 447 DEFINE_ZYNQ_PINCTRL_GRP(smc0_nand), 448 DEFINE_ZYNQ_PINCTRL_GRP(can0_0), 449 DEFINE_ZYNQ_PINCTRL_GRP(can0_1), 450 DEFINE_ZYNQ_PINCTRL_GRP(can0_2), 451 DEFINE_ZYNQ_PINCTRL_GRP(can0_3), 452 DEFINE_ZYNQ_PINCTRL_GRP(can0_4), 453 DEFINE_ZYNQ_PINCTRL_GRP(can0_5), 454 DEFINE_ZYNQ_PINCTRL_GRP(can0_6), 455 DEFINE_ZYNQ_PINCTRL_GRP(can0_7), 456 DEFINE_ZYNQ_PINCTRL_GRP(can0_8), 457 DEFINE_ZYNQ_PINCTRL_GRP(can0_9), 458 DEFINE_ZYNQ_PINCTRL_GRP(can0_10), 459 DEFINE_ZYNQ_PINCTRL_GRP(can1_0), 460 DEFINE_ZYNQ_PINCTRL_GRP(can1_1), 461 DEFINE_ZYNQ_PINCTRL_GRP(can1_2), 462 DEFINE_ZYNQ_PINCTRL_GRP(can1_3), 463 DEFINE_ZYNQ_PINCTRL_GRP(can1_4), 464 DEFINE_ZYNQ_PINCTRL_GRP(can1_5), 465 DEFINE_ZYNQ_PINCTRL_GRP(can1_6), 466 DEFINE_ZYNQ_PINCTRL_GRP(can1_7), 467 DEFINE_ZYNQ_PINCTRL_GRP(can1_8), 468 DEFINE_ZYNQ_PINCTRL_GRP(can1_9), 469 DEFINE_ZYNQ_PINCTRL_GRP(can1_10), 470 DEFINE_ZYNQ_PINCTRL_GRP(can1_11), 471 DEFINE_ZYNQ_PINCTRL_GRP(uart0_0), 472 DEFINE_ZYNQ_PINCTRL_GRP(uart0_1), 473 DEFINE_ZYNQ_PINCTRL_GRP(uart0_2), 474 DEFINE_ZYNQ_PINCTRL_GRP(uart0_3), 475 DEFINE_ZYNQ_PINCTRL_GRP(uart0_4), 476 DEFINE_ZYNQ_PINCTRL_GRP(uart0_5), 477 DEFINE_ZYNQ_PINCTRL_GRP(uart0_6), 478 DEFINE_ZYNQ_PINCTRL_GRP(uart0_7), 479 DEFINE_ZYNQ_PINCTRL_GRP(uart0_8), 480 DEFINE_ZYNQ_PINCTRL_GRP(uart0_9), 481 DEFINE_ZYNQ_PINCTRL_GRP(uart0_10), 482 DEFINE_ZYNQ_PINCTRL_GRP(uart1_0), 483 DEFINE_ZYNQ_PINCTRL_GRP(uart1_1), 484 DEFINE_ZYNQ_PINCTRL_GRP(uart1_2), 485 DEFINE_ZYNQ_PINCTRL_GRP(uart1_3), 486 DEFINE_ZYNQ_PINCTRL_GRP(uart1_4), 487 DEFINE_ZYNQ_PINCTRL_GRP(uart1_5), 488 DEFINE_ZYNQ_PINCTRL_GRP(uart1_6), 489 DEFINE_ZYNQ_PINCTRL_GRP(uart1_7), 490 DEFINE_ZYNQ_PINCTRL_GRP(uart1_8), 491 DEFINE_ZYNQ_PINCTRL_GRP(uart1_9), 492 DEFINE_ZYNQ_PINCTRL_GRP(uart1_10), 493 DEFINE_ZYNQ_PINCTRL_GRP(uart1_11), 494 DEFINE_ZYNQ_PINCTRL_GRP(i2c0_0), 495 DEFINE_ZYNQ_PINCTRL_GRP(i2c0_1), 496 DEFINE_ZYNQ_PINCTRL_GRP(i2c0_2), 497 DEFINE_ZYNQ_PINCTRL_GRP(i2c0_3), 498 DEFINE_ZYNQ_PINCTRL_GRP(i2c0_4), 499 DEFINE_ZYNQ_PINCTRL_GRP(i2c0_5), 500 DEFINE_ZYNQ_PINCTRL_GRP(i2c0_6), 501 DEFINE_ZYNQ_PINCTRL_GRP(i2c0_7), 502 DEFINE_ZYNQ_PINCTRL_GRP(i2c0_8), 503 DEFINE_ZYNQ_PINCTRL_GRP(i2c0_9), 504 DEFINE_ZYNQ_PINCTRL_GRP(i2c0_10), 505 DEFINE_ZYNQ_PINCTRL_GRP(i2c1_0), 506 DEFINE_ZYNQ_PINCTRL_GRP(i2c1_1), 507 DEFINE_ZYNQ_PINCTRL_GRP(i2c1_2), 508 DEFINE_ZYNQ_PINCTRL_GRP(i2c1_3), 509 DEFINE_ZYNQ_PINCTRL_GRP(i2c1_4), 510 DEFINE_ZYNQ_PINCTRL_GRP(i2c1_5), 511 DEFINE_ZYNQ_PINCTRL_GRP(i2c1_6), 512 DEFINE_ZYNQ_PINCTRL_GRP(i2c1_7), 513 DEFINE_ZYNQ_PINCTRL_GRP(i2c1_8), 514 DEFINE_ZYNQ_PINCTRL_GRP(i2c1_9), 515 DEFINE_ZYNQ_PINCTRL_GRP(i2c1_10), 516 DEFINE_ZYNQ_PINCTRL_GRP(ttc0_0), 517 DEFINE_ZYNQ_PINCTRL_GRP(ttc0_1), 518 DEFINE_ZYNQ_PINCTRL_GRP(ttc0_2), 519 DEFINE_ZYNQ_PINCTRL_GRP(ttc1_0), 520 DEFINE_ZYNQ_PINCTRL_GRP(ttc1_1), 521 DEFINE_ZYNQ_PINCTRL_GRP(ttc1_2), 522 DEFINE_ZYNQ_PINCTRL_GRP(swdt0_0), 523 DEFINE_ZYNQ_PINCTRL_GRP(swdt0_1), 524 DEFINE_ZYNQ_PINCTRL_GRP(swdt0_2), 525 DEFINE_ZYNQ_PINCTRL_GRP(swdt0_3), 526 DEFINE_ZYNQ_PINCTRL_GRP(swdt0_4), 527 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_0), 528 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_1), 529 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_2), 530 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_3), 531 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_4), 532 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_5), 533 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_6), 534 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_7), 535 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_8), 536 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_9), 537 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_10), 538 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_11), 539 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_12), 540 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_13), 541 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_14), 542 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_15), 543 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_16), 544 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_17), 545 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_18), 546 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_19), 547 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_20), 548 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_21), 549 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_22), 550 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_23), 551 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_24), 552 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_25), 553 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_26), 554 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_27), 555 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_28), 556 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_29), 557 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_30), 558 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_31), 559 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_32), 560 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_33), 561 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_34), 562 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_35), 563 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_36), 564 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_37), 565 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_38), 566 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_39), 567 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_40), 568 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_41), 569 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_42), 570 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_43), 571 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_44), 572 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_45), 573 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_46), 574 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_47), 575 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_48), 576 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_49), 577 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_50), 578 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_51), 579 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_52), 580 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_53), 581 DEFINE_ZYNQ_PINCTRL_GRP(usb0_0), 582 DEFINE_ZYNQ_PINCTRL_GRP(usb1_0), 583 }; 584 585 /* function groups */ 586 static const char * const ethernet0_groups[] = {"ethernet0_0_grp"}; 587 static const char * const ethernet1_groups[] = {"ethernet1_0_grp"}; 588 static const char * const usb0_groups[] = {"usb0_0_grp"}; 589 static const char * const usb1_groups[] = {"usb1_0_grp"}; 590 static const char * const mdio0_groups[] = {"mdio0_0_grp"}; 591 static const char * const mdio1_groups[] = {"mdio1_0_grp"}; 592 static const char * const qspi0_groups[] = {"qspi0_0_grp"}; 593 static const char * const qspi1_groups[] = {"qspi1_0_grp"}; 594 static const char * const qspi_fbclk_groups[] = {"qspi_fbclk_grp"}; 595 static const char * const qspi_cs1_groups[] = {"qspi_cs1_grp"}; 596 static const char * const spi0_groups[] = {"spi0_0_grp", "spi0_1_grp", 597 "spi0_2_grp"}; 598 static const char * const spi1_groups[] = {"spi1_0_grp", "spi1_1_grp", 599 "spi1_2_grp", "spi1_3_grp"}; 600 static const char * const spi0_ss_groups[] = {"spi0_0_ss0_grp", 601 "spi0_0_ss1_grp", "spi0_0_ss2_grp", "spi0_1_ss0_grp", 602 "spi0_1_ss1_grp", "spi0_1_ss2_grp", "spi0_2_ss0_grp", 603 "spi0_2_ss1_grp", "spi0_2_ss2_grp"}; 604 static const char * const spi1_ss_groups[] = {"spi1_0_ss0_grp", 605 "spi1_0_ss1_grp", "spi1_0_ss2_grp", "spi1_1_ss0_grp", 606 "spi1_1_ss1_grp", "spi1_1_ss2_grp", "spi1_2_ss0_grp", 607 "spi1_2_ss1_grp", "spi1_2_ss2_grp", "spi1_3_ss0_grp", 608 "spi1_3_ss1_grp", "spi1_3_ss2_grp"}; 609 static const char * const sdio0_groups[] = {"sdio0_0_grp", "sdio0_1_grp", 610 "sdio0_2_grp"}; 611 static const char * const sdio1_groups[] = {"sdio1_0_grp", "sdio1_1_grp", 612 "sdio1_2_grp", "sdio1_3_grp"}; 613 static const char * const sdio0_pc_groups[] = {"gpio0_0_grp", 614 "gpio0_2_grp", "gpio0_4_grp", "gpio0_6_grp", 615 "gpio0_8_grp", "gpio0_10_grp", "gpio0_12_grp", 616 "gpio0_14_grp", "gpio0_16_grp", "gpio0_18_grp", 617 "gpio0_20_grp", "gpio0_22_grp", "gpio0_24_grp", 618 "gpio0_26_grp", "gpio0_28_grp", "gpio0_30_grp", 619 "gpio0_32_grp", "gpio0_34_grp", "gpio0_36_grp", 620 "gpio0_38_grp", "gpio0_40_grp", "gpio0_42_grp", 621 "gpio0_44_grp", "gpio0_46_grp", "gpio0_48_grp", 622 "gpio0_50_grp", "gpio0_52_grp"}; 623 static const char * const sdio1_pc_groups[] = {"gpio0_1_grp", 624 "gpio0_3_grp", "gpio0_5_grp", "gpio0_7_grp", 625 "gpio0_9_grp", "gpio0_11_grp", "gpio0_13_grp", 626 "gpio0_15_grp", "gpio0_17_grp", "gpio0_19_grp", 627 "gpio0_21_grp", "gpio0_23_grp", "gpio0_25_grp", 628 "gpio0_27_grp", "gpio0_29_grp", "gpio0_31_grp", 629 "gpio0_33_grp", "gpio0_35_grp", "gpio0_37_grp", 630 "gpio0_39_grp", "gpio0_41_grp", "gpio0_43_grp", 631 "gpio0_45_grp", "gpio0_47_grp", "gpio0_49_grp", 632 "gpio0_51_grp", "gpio0_53_grp"}; 633 static const char * const sdio0_cd_groups[] = {"gpio0_0_grp", 634 "gpio0_2_grp", "gpio0_4_grp", "gpio0_6_grp", 635 "gpio0_10_grp", "gpio0_12_grp", 636 "gpio0_14_grp", "gpio0_16_grp", "gpio0_18_grp", 637 "gpio0_20_grp", "gpio0_22_grp", "gpio0_24_grp", 638 "gpio0_26_grp", "gpio0_28_grp", "gpio0_30_grp", 639 "gpio0_32_grp", "gpio0_34_grp", "gpio0_36_grp", 640 "gpio0_38_grp", "gpio0_40_grp", "gpio0_42_grp", 641 "gpio0_44_grp", "gpio0_46_grp", "gpio0_48_grp", 642 "gpio0_50_grp", "gpio0_52_grp", "gpio0_1_grp", 643 "gpio0_3_grp", "gpio0_5_grp", 644 "gpio0_9_grp", "gpio0_11_grp", "gpio0_13_grp", 645 "gpio0_15_grp", "gpio0_17_grp", "gpio0_19_grp", 646 "gpio0_21_grp", "gpio0_23_grp", "gpio0_25_grp", 647 "gpio0_27_grp", "gpio0_29_grp", "gpio0_31_grp", 648 "gpio0_33_grp", "gpio0_35_grp", "gpio0_37_grp", 649 "gpio0_39_grp", "gpio0_41_grp", "gpio0_43_grp", 650 "gpio0_45_grp", "gpio0_47_grp", "gpio0_49_grp", 651 "gpio0_51_grp", "gpio0_53_grp", "sdio0_emio_cd_grp"}; 652 static const char * const sdio0_wp_groups[] = {"gpio0_0_grp", 653 "gpio0_2_grp", "gpio0_4_grp", "gpio0_6_grp", 654 "gpio0_10_grp", "gpio0_12_grp", 655 "gpio0_14_grp", "gpio0_16_grp", "gpio0_18_grp", 656 "gpio0_20_grp", "gpio0_22_grp", "gpio0_24_grp", 657 "gpio0_26_grp", "gpio0_28_grp", "gpio0_30_grp", 658 "gpio0_32_grp", "gpio0_34_grp", "gpio0_36_grp", 659 "gpio0_38_grp", "gpio0_40_grp", "gpio0_42_grp", 660 "gpio0_44_grp", "gpio0_46_grp", "gpio0_48_grp", 661 "gpio0_50_grp", "gpio0_52_grp", "gpio0_1_grp", 662 "gpio0_3_grp", "gpio0_5_grp", 663 "gpio0_9_grp", "gpio0_11_grp", "gpio0_13_grp", 664 "gpio0_15_grp", "gpio0_17_grp", "gpio0_19_grp", 665 "gpio0_21_grp", "gpio0_23_grp", "gpio0_25_grp", 666 "gpio0_27_grp", "gpio0_29_grp", "gpio0_31_grp", 667 "gpio0_33_grp", "gpio0_35_grp", "gpio0_37_grp", 668 "gpio0_39_grp", "gpio0_41_grp", "gpio0_43_grp", 669 "gpio0_45_grp", "gpio0_47_grp", "gpio0_49_grp", 670 "gpio0_51_grp", "gpio0_53_grp", "sdio0_emio_wp_grp"}; 671 static const char * const sdio1_cd_groups[] = {"gpio0_0_grp", 672 "gpio0_2_grp", "gpio0_4_grp", "gpio0_6_grp", 673 "gpio0_10_grp", "gpio0_12_grp", 674 "gpio0_14_grp", "gpio0_16_grp", "gpio0_18_grp", 675 "gpio0_20_grp", "gpio0_22_grp", "gpio0_24_grp", 676 "gpio0_26_grp", "gpio0_28_grp", "gpio0_30_grp", 677 "gpio0_32_grp", "gpio0_34_grp", "gpio0_36_grp", 678 "gpio0_38_grp", "gpio0_40_grp", "gpio0_42_grp", 679 "gpio0_44_grp", "gpio0_46_grp", "gpio0_48_grp", 680 "gpio0_50_grp", "gpio0_52_grp", "gpio0_1_grp", 681 "gpio0_3_grp", "gpio0_5_grp", 682 "gpio0_9_grp", "gpio0_11_grp", "gpio0_13_grp", 683 "gpio0_15_grp", "gpio0_17_grp", "gpio0_19_grp", 684 "gpio0_21_grp", "gpio0_23_grp", "gpio0_25_grp", 685 "gpio0_27_grp", "gpio0_29_grp", "gpio0_31_grp", 686 "gpio0_33_grp", "gpio0_35_grp", "gpio0_37_grp", 687 "gpio0_39_grp", "gpio0_41_grp", "gpio0_43_grp", 688 "gpio0_45_grp", "gpio0_47_grp", "gpio0_49_grp", 689 "gpio0_51_grp", "gpio0_53_grp", "sdio1_emio_cd_grp"}; 690 static const char * const sdio1_wp_groups[] = {"gpio0_0_grp", 691 "gpio0_2_grp", "gpio0_4_grp", "gpio0_6_grp", 692 "gpio0_10_grp", "gpio0_12_grp", 693 "gpio0_14_grp", "gpio0_16_grp", "gpio0_18_grp", 694 "gpio0_20_grp", "gpio0_22_grp", "gpio0_24_grp", 695 "gpio0_26_grp", "gpio0_28_grp", "gpio0_30_grp", 696 "gpio0_32_grp", "gpio0_34_grp", "gpio0_36_grp", 697 "gpio0_38_grp", "gpio0_40_grp", "gpio0_42_grp", 698 "gpio0_44_grp", "gpio0_46_grp", "gpio0_48_grp", 699 "gpio0_50_grp", "gpio0_52_grp", "gpio0_1_grp", 700 "gpio0_3_grp", "gpio0_5_grp", 701 "gpio0_9_grp", "gpio0_11_grp", "gpio0_13_grp", 702 "gpio0_15_grp", "gpio0_17_grp", "gpio0_19_grp", 703 "gpio0_21_grp", "gpio0_23_grp", "gpio0_25_grp", 704 "gpio0_27_grp", "gpio0_29_grp", "gpio0_31_grp", 705 "gpio0_33_grp", "gpio0_35_grp", "gpio0_37_grp", 706 "gpio0_39_grp", "gpio0_41_grp", "gpio0_43_grp", 707 "gpio0_45_grp", "gpio0_47_grp", "gpio0_49_grp", 708 "gpio0_51_grp", "gpio0_53_grp", "sdio1_emio_wp_grp"}; 709 static const char * const smc0_nor_groups[] = {"smc0_nor_grp"}; 710 static const char * const smc0_nor_cs1_groups[] = {"smc0_nor_cs1_grp"}; 711 static const char * const smc0_nor_addr25_groups[] = {"smc0_nor_addr25_grp"}; 712 static const char * const smc0_nand_groups[] = {"smc0_nand_grp"}; 713 static const char * const can0_groups[] = {"can0_0_grp", "can0_1_grp", 714 "can0_2_grp", "can0_3_grp", "can0_4_grp", "can0_5_grp", 715 "can0_6_grp", "can0_7_grp", "can0_8_grp", "can0_9_grp", 716 "can0_10_grp"}; 717 static const char * const can1_groups[] = {"can1_0_grp", "can1_1_grp", 718 "can1_2_grp", "can1_3_grp", "can1_4_grp", "can1_5_grp", 719 "can1_6_grp", "can1_7_grp", "can1_8_grp", "can1_9_grp", 720 "can1_10_grp", "can1_11_grp"}; 721 static const char * const uart0_groups[] = {"uart0_0_grp", "uart0_1_grp", 722 "uart0_2_grp", "uart0_3_grp", "uart0_4_grp", "uart0_5_grp", 723 "uart0_6_grp", "uart0_7_grp", "uart0_8_grp", "uart0_9_grp", 724 "uart0_10_grp"}; 725 static const char * const uart1_groups[] = {"uart1_0_grp", "uart1_1_grp", 726 "uart1_2_grp", "uart1_3_grp", "uart1_4_grp", "uart1_5_grp", 727 "uart1_6_grp", "uart1_7_grp", "uart1_8_grp", "uart1_9_grp", 728 "uart1_10_grp", "uart1_11_grp"}; 729 static const char * const i2c0_groups[] = {"i2c0_0_grp", "i2c0_1_grp", 730 "i2c0_2_grp", "i2c0_3_grp", "i2c0_4_grp", "i2c0_5_grp", 731 "i2c0_6_grp", "i2c0_7_grp", "i2c0_8_grp", "i2c0_9_grp", 732 "i2c0_10_grp"}; 733 static const char * const i2c1_groups[] = {"i2c1_0_grp", "i2c1_1_grp", 734 "i2c1_2_grp", "i2c1_3_grp", "i2c1_4_grp", "i2c1_5_grp", 735 "i2c1_6_grp", "i2c1_7_grp", "i2c1_8_grp", "i2c1_9_grp", 736 "i2c1_10_grp"}; 737 static const char * const ttc0_groups[] = {"ttc0_0_grp", "ttc0_1_grp", 738 "ttc0_2_grp"}; 739 static const char * const ttc1_groups[] = {"ttc1_0_grp", "ttc1_1_grp", 740 "ttc1_2_grp"}; 741 static const char * const swdt0_groups[] = {"swdt0_0_grp", "swdt0_1_grp", 742 "swdt0_2_grp", "swdt0_3_grp", "swdt0_4_grp"}; 743 static const char * const gpio0_groups[] = {"gpio0_0_grp", 744 "gpio0_2_grp", "gpio0_4_grp", "gpio0_6_grp", 745 "gpio0_8_grp", "gpio0_10_grp", "gpio0_12_grp", 746 "gpio0_14_grp", "gpio0_16_grp", "gpio0_18_grp", 747 "gpio0_20_grp", "gpio0_22_grp", "gpio0_24_grp", 748 "gpio0_26_grp", "gpio0_28_grp", "gpio0_30_grp", 749 "gpio0_32_grp", "gpio0_34_grp", "gpio0_36_grp", 750 "gpio0_38_grp", "gpio0_40_grp", "gpio0_42_grp", 751 "gpio0_44_grp", "gpio0_46_grp", "gpio0_48_grp", 752 "gpio0_50_grp", "gpio0_52_grp", "gpio0_1_grp", 753 "gpio0_3_grp", "gpio0_5_grp", "gpio0_7_grp", 754 "gpio0_9_grp", "gpio0_11_grp", "gpio0_13_grp", 755 "gpio0_15_grp", "gpio0_17_grp", "gpio0_19_grp", 756 "gpio0_21_grp", "gpio0_23_grp", "gpio0_25_grp", 757 "gpio0_27_grp", "gpio0_29_grp", "gpio0_31_grp", 758 "gpio0_33_grp", "gpio0_35_grp", "gpio0_37_grp", 759 "gpio0_39_grp", "gpio0_41_grp", "gpio0_43_grp", 760 "gpio0_45_grp", "gpio0_47_grp", "gpio0_49_grp", 761 "gpio0_51_grp", "gpio0_53_grp"}; 762 763 #define DEFINE_ZYNQ_PINMUX_FUNCTION(fname, mval) \ 764 [ZYNQ_PMUX_##fname] = { \ 765 .name = #fname, \ 766 .groups = fname##_groups, \ 767 .ngroups = ARRAY_SIZE(fname##_groups), \ 768 .mux_val = mval, \ 769 } 770 771 #define DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(fname, mval, offset, mask, shift)\ 772 [ZYNQ_PMUX_##fname] = { \ 773 .name = #fname, \ 774 .groups = fname##_groups, \ 775 .ngroups = ARRAY_SIZE(fname##_groups), \ 776 .mux_val = mval, \ 777 .mux = offset, \ 778 .mux_mask = mask, \ 779 .mux_shift = shift, \ 780 } 781 782 #define ZYNQ_SDIO_WP_SHIFT 0 783 #define ZYNQ_SDIO_WP_MASK (0x3f << ZYNQ_SDIO_WP_SHIFT) 784 #define ZYNQ_SDIO_CD_SHIFT 16 785 #define ZYNQ_SDIO_CD_MASK (0x3f << ZYNQ_SDIO_CD_SHIFT) 786 787 static const struct zynq_pinmux_function zynq_pmux_functions[] = { 788 DEFINE_ZYNQ_PINMUX_FUNCTION(ethernet0, 1), 789 DEFINE_ZYNQ_PINMUX_FUNCTION(ethernet1, 1), 790 DEFINE_ZYNQ_PINMUX_FUNCTION(usb0, 2), 791 DEFINE_ZYNQ_PINMUX_FUNCTION(usb1, 2), 792 DEFINE_ZYNQ_PINMUX_FUNCTION(mdio0, 0x40), 793 DEFINE_ZYNQ_PINMUX_FUNCTION(mdio1, 0x50), 794 DEFINE_ZYNQ_PINMUX_FUNCTION(qspi0, 1), 795 DEFINE_ZYNQ_PINMUX_FUNCTION(qspi1, 1), 796 DEFINE_ZYNQ_PINMUX_FUNCTION(qspi_fbclk, 1), 797 DEFINE_ZYNQ_PINMUX_FUNCTION(qspi_cs1, 1), 798 DEFINE_ZYNQ_PINMUX_FUNCTION(spi0, 0x50), 799 DEFINE_ZYNQ_PINMUX_FUNCTION(spi1, 0x50), 800 DEFINE_ZYNQ_PINMUX_FUNCTION(spi0_ss, 0x50), 801 DEFINE_ZYNQ_PINMUX_FUNCTION(spi1_ss, 0x50), 802 DEFINE_ZYNQ_PINMUX_FUNCTION(sdio0, 0x40), 803 DEFINE_ZYNQ_PINMUX_FUNCTION(sdio0_pc, 0xc), 804 DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio0_wp, 0, 0x130, ZYNQ_SDIO_WP_MASK, 805 ZYNQ_SDIO_WP_SHIFT), 806 DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio0_cd, 0, 0x130, ZYNQ_SDIO_CD_MASK, 807 ZYNQ_SDIO_CD_SHIFT), 808 DEFINE_ZYNQ_PINMUX_FUNCTION(sdio1, 0x40), 809 DEFINE_ZYNQ_PINMUX_FUNCTION(sdio1_pc, 0xc), 810 DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio1_wp, 0, 0x134, ZYNQ_SDIO_WP_MASK, 811 ZYNQ_SDIO_WP_SHIFT), 812 DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio1_cd, 0, 0x134, ZYNQ_SDIO_CD_MASK, 813 ZYNQ_SDIO_CD_SHIFT), 814 DEFINE_ZYNQ_PINMUX_FUNCTION(smc0_nor, 4), 815 DEFINE_ZYNQ_PINMUX_FUNCTION(smc0_nor_cs1, 8), 816 DEFINE_ZYNQ_PINMUX_FUNCTION(smc0_nor_addr25, 4), 817 DEFINE_ZYNQ_PINMUX_FUNCTION(smc0_nand, 8), 818 DEFINE_ZYNQ_PINMUX_FUNCTION(can0, 0x10), 819 DEFINE_ZYNQ_PINMUX_FUNCTION(can1, 0x10), 820 DEFINE_ZYNQ_PINMUX_FUNCTION(uart0, 0x70), 821 DEFINE_ZYNQ_PINMUX_FUNCTION(uart1, 0x70), 822 DEFINE_ZYNQ_PINMUX_FUNCTION(i2c0, 0x20), 823 DEFINE_ZYNQ_PINMUX_FUNCTION(i2c1, 0x20), 824 DEFINE_ZYNQ_PINMUX_FUNCTION(ttc0, 0x60), 825 DEFINE_ZYNQ_PINMUX_FUNCTION(ttc1, 0x60), 826 DEFINE_ZYNQ_PINMUX_FUNCTION(swdt0, 0x30), 827 DEFINE_ZYNQ_PINMUX_FUNCTION(gpio0, 0), 828 }; 829 830 831 /* pinctrl */ 832 static int zynq_pctrl_get_groups_count(struct pinctrl_dev *pctldev) 833 { 834 struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 835 836 return pctrl->ngroups; 837 } 838 839 static const char *zynq_pctrl_get_group_name(struct pinctrl_dev *pctldev, 840 unsigned selector) 841 { 842 struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 843 844 return pctrl->groups[selector].name; 845 } 846 847 static int zynq_pctrl_get_group_pins(struct pinctrl_dev *pctldev, 848 unsigned selector, 849 const unsigned **pins, 850 unsigned *num_pins) 851 { 852 struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 853 854 *pins = pctrl->groups[selector].pins; 855 *num_pins = pctrl->groups[selector].npins; 856 857 return 0; 858 } 859 860 static const struct pinctrl_ops zynq_pctrl_ops = { 861 .get_groups_count = zynq_pctrl_get_groups_count, 862 .get_group_name = zynq_pctrl_get_group_name, 863 .get_group_pins = zynq_pctrl_get_group_pins, 864 .dt_node_to_map = pinconf_generic_dt_node_to_map_all, 865 .dt_free_map = pinctrl_utils_free_map, 866 }; 867 868 /* pinmux */ 869 static int zynq_pmux_get_functions_count(struct pinctrl_dev *pctldev) 870 { 871 struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 872 873 return pctrl->nfuncs; 874 } 875 876 static const char *zynq_pmux_get_function_name(struct pinctrl_dev *pctldev, 877 unsigned selector) 878 { 879 struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 880 881 return pctrl->funcs[selector].name; 882 } 883 884 static int zynq_pmux_get_function_groups(struct pinctrl_dev *pctldev, 885 unsigned selector, 886 const char * const **groups, 887 unsigned * const num_groups) 888 { 889 struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 890 891 *groups = pctrl->funcs[selector].groups; 892 *num_groups = pctrl->funcs[selector].ngroups; 893 return 0; 894 } 895 896 static int zynq_pinmux_set_mux(struct pinctrl_dev *pctldev, 897 unsigned function, 898 unsigned group) 899 { 900 int i, ret; 901 struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 902 const struct zynq_pctrl_group *pgrp = &pctrl->groups[group]; 903 const struct zynq_pinmux_function *func = &pctrl->funcs[function]; 904 905 /* 906 * SD WP & CD are special. They have dedicated registers 907 * to mux them in 908 */ 909 if (function == ZYNQ_PMUX_sdio0_cd || function == ZYNQ_PMUX_sdio0_wp || 910 function == ZYNQ_PMUX_sdio1_cd || 911 function == ZYNQ_PMUX_sdio1_wp) { 912 u32 reg; 913 914 ret = regmap_read(pctrl->syscon, 915 pctrl->pctrl_offset + func->mux, ®); 916 if (ret) 917 return ret; 918 919 reg &= ~func->mux_mask; 920 reg |= pgrp->pins[0] << func->mux_shift; 921 ret = regmap_write(pctrl->syscon, 922 pctrl->pctrl_offset + func->mux, reg); 923 if (ret) 924 return ret; 925 } else { 926 for (i = 0; i < pgrp->npins; i++) { 927 unsigned int pin = pgrp->pins[i]; 928 u32 reg, addr = pctrl->pctrl_offset + (4 * pin); 929 930 ret = regmap_read(pctrl->syscon, addr, ®); 931 if (ret) 932 return ret; 933 934 reg &= ~ZYNQ_PINMUX_MUX_MASK; 935 reg |= func->mux_val << ZYNQ_PINMUX_MUX_SHIFT; 936 ret = regmap_write(pctrl->syscon, addr, reg); 937 if (ret) 938 return ret; 939 } 940 } 941 942 return 0; 943 } 944 945 static const struct pinmux_ops zynq_pinmux_ops = { 946 .get_functions_count = zynq_pmux_get_functions_count, 947 .get_function_name = zynq_pmux_get_function_name, 948 .get_function_groups = zynq_pmux_get_function_groups, 949 .set_mux = zynq_pinmux_set_mux, 950 }; 951 952 /* pinconfig */ 953 #define ZYNQ_PINCONF_TRISTATE BIT(0) 954 #define ZYNQ_PINCONF_SPEED BIT(8) 955 #define ZYNQ_PINCONF_PULLUP BIT(12) 956 #define ZYNQ_PINCONF_DISABLE_RECVR BIT(13) 957 958 #define ZYNQ_PINCONF_IOTYPE_SHIFT 9 959 #define ZYNQ_PINCONF_IOTYPE_MASK (7 << ZYNQ_PINCONF_IOTYPE_SHIFT) 960 961 enum zynq_io_standards { 962 zynq_iostd_min, 963 zynq_iostd_lvcmos18, 964 zynq_iostd_lvcmos25, 965 zynq_iostd_lvcmos33, 966 zynq_iostd_hstl, 967 zynq_iostd_max 968 }; 969 970 /** 971 * enum zynq_pin_config_param - possible pin configuration parameters 972 * @PIN_CONFIG_IOSTANDARD: if the pin can select an IO standard, the argument to 973 * this parameter (on a custom format) tells the driver which alternative 974 * IO standard to use. 975 */ 976 enum zynq_pin_config_param { 977 PIN_CONFIG_IOSTANDARD = PIN_CONFIG_END + 1, 978 }; 979 980 static const struct pinconf_generic_params zynq_dt_params[] = { 981 {"io-standard", PIN_CONFIG_IOSTANDARD, zynq_iostd_lvcmos18}, 982 }; 983 984 #ifdef CONFIG_DEBUG_FS 985 static const struct pin_config_item zynq_conf_items[ARRAY_SIZE(zynq_dt_params)] = { 986 PCONFDUMP(PIN_CONFIG_IOSTANDARD, "IO-standard", NULL, true), 987 }; 988 #endif 989 990 static unsigned int zynq_pinconf_iostd_get(u32 reg) 991 { 992 return (reg & ZYNQ_PINCONF_IOTYPE_MASK) >> ZYNQ_PINCONF_IOTYPE_SHIFT; 993 } 994 995 static int zynq_pinconf_cfg_get(struct pinctrl_dev *pctldev, 996 unsigned pin, 997 unsigned long *config) 998 { 999 u32 reg; 1000 int ret; 1001 unsigned int arg = 0; 1002 unsigned int param = pinconf_to_config_param(*config); 1003 struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 1004 1005 if (pin >= ZYNQ_NUM_MIOS) 1006 return -ENOTSUPP; 1007 1008 ret = regmap_read(pctrl->syscon, pctrl->pctrl_offset + (4 * pin), ®); 1009 if (ret) 1010 return -EIO; 1011 1012 switch (param) { 1013 case PIN_CONFIG_BIAS_PULL_UP: 1014 if (!(reg & ZYNQ_PINCONF_PULLUP)) 1015 return -EINVAL; 1016 arg = 1; 1017 break; 1018 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: 1019 if (!(reg & ZYNQ_PINCONF_TRISTATE)) 1020 return -EINVAL; 1021 arg = 1; 1022 break; 1023 case PIN_CONFIG_BIAS_DISABLE: 1024 if (reg & ZYNQ_PINCONF_PULLUP || reg & ZYNQ_PINCONF_TRISTATE) 1025 return -EINVAL; 1026 break; 1027 case PIN_CONFIG_SLEW_RATE: 1028 arg = !!(reg & ZYNQ_PINCONF_SPEED); 1029 break; 1030 case PIN_CONFIG_LOW_POWER_MODE: 1031 { 1032 enum zynq_io_standards iostd = zynq_pinconf_iostd_get(reg); 1033 1034 if (iostd != zynq_iostd_hstl) 1035 return -EINVAL; 1036 if (!(reg & ZYNQ_PINCONF_DISABLE_RECVR)) 1037 return -EINVAL; 1038 arg = !!(reg & ZYNQ_PINCONF_DISABLE_RECVR); 1039 break; 1040 } 1041 case PIN_CONFIG_IOSTANDARD: 1042 arg = zynq_pinconf_iostd_get(reg); 1043 break; 1044 default: 1045 return -ENOTSUPP; 1046 } 1047 1048 *config = pinconf_to_config_packed(param, arg); 1049 return 0; 1050 } 1051 1052 static int zynq_pinconf_cfg_set(struct pinctrl_dev *pctldev, 1053 unsigned pin, 1054 unsigned long *configs, 1055 unsigned num_configs) 1056 { 1057 int i, ret; 1058 u32 reg; 1059 u32 pullup = 0; 1060 u32 tristate = 0; 1061 struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 1062 1063 if (pin >= ZYNQ_NUM_MIOS) 1064 return -ENOTSUPP; 1065 1066 ret = regmap_read(pctrl->syscon, pctrl->pctrl_offset + (4 * pin), ®); 1067 if (ret) 1068 return -EIO; 1069 1070 for (i = 0; i < num_configs; i++) { 1071 unsigned int param = pinconf_to_config_param(configs[i]); 1072 unsigned int arg = pinconf_to_config_argument(configs[i]); 1073 1074 switch (param) { 1075 case PIN_CONFIG_BIAS_PULL_UP: 1076 pullup = ZYNQ_PINCONF_PULLUP; 1077 break; 1078 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: 1079 tristate = ZYNQ_PINCONF_TRISTATE; 1080 break; 1081 case PIN_CONFIG_BIAS_DISABLE: 1082 reg &= ~(ZYNQ_PINCONF_PULLUP | ZYNQ_PINCONF_TRISTATE); 1083 break; 1084 case PIN_CONFIG_SLEW_RATE: 1085 if (arg) 1086 reg |= ZYNQ_PINCONF_SPEED; 1087 else 1088 reg &= ~ZYNQ_PINCONF_SPEED; 1089 1090 break; 1091 case PIN_CONFIG_IOSTANDARD: 1092 if (arg <= zynq_iostd_min || arg >= zynq_iostd_max) { 1093 dev_warn(pctldev->dev, 1094 "unsupported IO standard '%u'\n", 1095 param); 1096 break; 1097 } 1098 reg &= ~ZYNQ_PINCONF_IOTYPE_MASK; 1099 reg |= arg << ZYNQ_PINCONF_IOTYPE_SHIFT; 1100 break; 1101 case PIN_CONFIG_LOW_POWER_MODE: 1102 if (arg) 1103 reg |= ZYNQ_PINCONF_DISABLE_RECVR; 1104 else 1105 reg &= ~ZYNQ_PINCONF_DISABLE_RECVR; 1106 1107 break; 1108 default: 1109 dev_warn(pctldev->dev, 1110 "unsupported configuration parameter '%u'\n", 1111 param); 1112 continue; 1113 } 1114 } 1115 1116 if (tristate || pullup) { 1117 reg &= ~(ZYNQ_PINCONF_PULLUP | ZYNQ_PINCONF_TRISTATE); 1118 reg |= tristate | pullup; 1119 } 1120 1121 ret = regmap_write(pctrl->syscon, pctrl->pctrl_offset + (4 * pin), reg); 1122 if (ret) 1123 return -EIO; 1124 1125 return 0; 1126 } 1127 1128 static int zynq_pinconf_group_set(struct pinctrl_dev *pctldev, 1129 unsigned selector, 1130 unsigned long *configs, 1131 unsigned num_configs) 1132 { 1133 int i, ret; 1134 struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 1135 const struct zynq_pctrl_group *pgrp = &pctrl->groups[selector]; 1136 1137 for (i = 0; i < pgrp->npins; i++) { 1138 ret = zynq_pinconf_cfg_set(pctldev, pgrp->pins[i], configs, 1139 num_configs); 1140 if (ret) 1141 return ret; 1142 } 1143 1144 return 0; 1145 } 1146 1147 static const struct pinconf_ops zynq_pinconf_ops = { 1148 .is_generic = true, 1149 .pin_config_get = zynq_pinconf_cfg_get, 1150 .pin_config_set = zynq_pinconf_cfg_set, 1151 .pin_config_group_set = zynq_pinconf_group_set, 1152 }; 1153 1154 static struct pinctrl_desc zynq_desc = { 1155 .name = "zynq_pinctrl", 1156 .pins = zynq_pins, 1157 .npins = ARRAY_SIZE(zynq_pins), 1158 .pctlops = &zynq_pctrl_ops, 1159 .pmxops = &zynq_pinmux_ops, 1160 .confops = &zynq_pinconf_ops, 1161 .num_custom_params = ARRAY_SIZE(zynq_dt_params), 1162 .custom_params = zynq_dt_params, 1163 #ifdef CONFIG_DEBUG_FS 1164 .custom_conf_items = zynq_conf_items, 1165 #endif 1166 .owner = THIS_MODULE, 1167 }; 1168 1169 static int zynq_pinctrl_probe(struct platform_device *pdev) 1170 1171 { 1172 struct resource *res; 1173 struct zynq_pinctrl *pctrl; 1174 1175 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); 1176 if (!pctrl) 1177 return -ENOMEM; 1178 1179 pctrl->syscon = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 1180 "syscon"); 1181 if (IS_ERR(pctrl->syscon)) { 1182 dev_err(&pdev->dev, "unable to get syscon\n"); 1183 return PTR_ERR(pctrl->syscon); 1184 } 1185 1186 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1187 if (!res) { 1188 dev_err(&pdev->dev, "missing IO resource\n"); 1189 return -ENODEV; 1190 } 1191 pctrl->pctrl_offset = res->start; 1192 1193 pctrl->groups = zynq_pctrl_groups; 1194 pctrl->ngroups = ARRAY_SIZE(zynq_pctrl_groups); 1195 pctrl->funcs = zynq_pmux_functions; 1196 pctrl->nfuncs = ARRAY_SIZE(zynq_pmux_functions); 1197 1198 pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &zynq_desc, pctrl); 1199 if (IS_ERR(pctrl->pctrl)) 1200 return PTR_ERR(pctrl->pctrl); 1201 1202 platform_set_drvdata(pdev, pctrl); 1203 1204 dev_info(&pdev->dev, "zynq pinctrl initialized\n"); 1205 1206 return 0; 1207 } 1208 1209 static const struct of_device_id zynq_pinctrl_of_match[] = { 1210 { .compatible = "xlnx,pinctrl-zynq" }, 1211 { } 1212 }; 1213 MODULE_DEVICE_TABLE(of, zynq_pinctrl_of_match); 1214 1215 static struct platform_driver zynq_pinctrl_driver = { 1216 .driver = { 1217 .name = "zynq-pinctrl", 1218 .of_match_table = zynq_pinctrl_of_match, 1219 }, 1220 .probe = zynq_pinctrl_probe, 1221 }; 1222 1223 static int __init zynq_pinctrl_init(void) 1224 { 1225 return platform_driver_register(&zynq_pinctrl_driver); 1226 } 1227 arch_initcall(zynq_pinctrl_init); 1228 1229 static void __exit zynq_pinctrl_exit(void) 1230 { 1231 platform_driver_unregister(&zynq_pinctrl_driver); 1232 } 1233 module_exit(zynq_pinctrl_exit); 1234 1235 MODULE_AUTHOR("Sören Brinkmann <soren.brinkmann@xilinx.com>"); 1236 MODULE_DESCRIPTION("Xilinx Zynq pinctrl driver"); 1237 MODULE_LICENSE("GPL"); 1238