1 /*
2  *  linux/drivers/pinctrl/pinmux-xway.c
3  *  based on linux/drivers/pinctrl/pinmux-pxa910.c
4  *
5  *  This program is free software; you can redistribute it and/or modify
6  *  it under the terms of the GNU General Public License version 2 as
7  *  publishhed by the Free Software Foundation.
8  *
9  *  Copyright (C) 2012 John Crispin <john@phrozen.org>
10  *  Copyright (C) 2015 Martin Schiller <mschiller@tdt.de>
11  */
12 
13 #include <linux/err.h>
14 #include <linux/slab.h>
15 #include <linux/module.h>
16 #include <linux/of_platform.h>
17 #include <linux/of_address.h>
18 #include <linux/of_gpio.h>
19 #include <linux/ioport.h>
20 #include <linux/io.h>
21 #include <linux/device.h>
22 #include <linux/platform_device.h>
23 
24 #include "pinctrl-lantiq.h"
25 
26 #include <lantiq_soc.h>
27 
28 /* we have up to 4 banks of 16 bit each */
29 #define PINS			16
30 #define PORT3			3
31 #define PORT(x)			(x / PINS)
32 #define PORT_PIN(x)		(x % PINS)
33 
34 /* we have 2 mux bits that can be set for each pin */
35 #define MUX_ALT0	0x1
36 #define MUX_ALT1	0x2
37 
38 /*
39  * each bank has this offset apart from the 4th bank that is mixed into the
40  * other 3 ranges
41  */
42 #define REG_OFF			0x30
43 
44 /* these are the offsets to our registers */
45 #define GPIO_BASE(p)		(REG_OFF * PORT(p))
46 #define GPIO_OUT(p)		GPIO_BASE(p)
47 #define GPIO_IN(p)		(GPIO_BASE(p) + 0x04)
48 #define GPIO_DIR(p)		(GPIO_BASE(p) + 0x08)
49 #define GPIO_ALT0(p)		(GPIO_BASE(p) + 0x0C)
50 #define GPIO_ALT1(p)		(GPIO_BASE(p) + 0x10)
51 #define GPIO_OD(p)		(GPIO_BASE(p) + 0x14)
52 #define GPIO_PUDSEL(p)		(GPIO_BASE(p) + 0x1c)
53 #define GPIO_PUDEN(p)		(GPIO_BASE(p) + 0x20)
54 
55 /* the 4th port needs special offsets for some registers */
56 #define GPIO3_OD		(GPIO_BASE(0) + 0x24)
57 #define GPIO3_PUDSEL		(GPIO_BASE(0) + 0x28)
58 #define GPIO3_PUDEN		(GPIO_BASE(0) + 0x2C)
59 #define GPIO3_ALT1		(GPIO_BASE(PINS) + 0x24)
60 
61 /* macros to help us access the registers */
62 #define gpio_getbit(m, r, p)	(!!(ltq_r32(m + r) & BIT(p)))
63 #define gpio_setbit(m, r, p)	ltq_w32_mask(0, BIT(p), m + r)
64 #define gpio_clearbit(m, r, p)	ltq_w32_mask(BIT(p), 0, m + r)
65 
66 #define MFP_XWAY(a, f0, f1, f2, f3)	\
67 	{				\
68 		.name = #a,		\
69 		.pin = a,		\
70 		.func = {		\
71 			XWAY_MUX_##f0,	\
72 			XWAY_MUX_##f1,	\
73 			XWAY_MUX_##f2,	\
74 			XWAY_MUX_##f3,	\
75 		},			\
76 	}
77 
78 #define GRP_MUX(a, m, p)		\
79 	{ .name = a, .mux = XWAY_MUX_##m, .pins = p, .npins = ARRAY_SIZE(p), }
80 
81 #define FUNC_MUX(f, m)		\
82 	{ .func = f, .mux = XWAY_MUX_##m, }
83 
84 enum xway_mux {
85 	XWAY_MUX_GPIO = 0,
86 	XWAY_MUX_SPI,
87 	XWAY_MUX_ASC,
88 	XWAY_MUX_USIF,
89 	XWAY_MUX_PCI,
90 	XWAY_MUX_CBUS,
91 	XWAY_MUX_CGU,
92 	XWAY_MUX_EBU,
93 	XWAY_MUX_EBU2,
94 	XWAY_MUX_JTAG,
95 	XWAY_MUX_MCD,
96 	XWAY_MUX_EXIN,
97 	XWAY_MUX_TDM,
98 	XWAY_MUX_STP,
99 	XWAY_MUX_SIN,
100 	XWAY_MUX_GPT,
101 	XWAY_MUX_NMI,
102 	XWAY_MUX_MDIO,
103 	XWAY_MUX_MII,
104 	XWAY_MUX_EPHY,
105 	XWAY_MUX_DFE,
106 	XWAY_MUX_SDIO,
107 	XWAY_MUX_GPHY,
108 	XWAY_MUX_SSI,
109 	XWAY_MUX_WIFI,
110 	XWAY_MUX_NONE = 0xffff,
111 };
112 
113 /* ---------  DEPRECATED: xr9 related code --------- */
114 /* ----------  use xrx100/xrx200 instead  ---------- */
115 #define XR9_MAX_PIN		56
116 
117 static const struct ltq_mfp_pin xway_mfp[] = {
118 	/*       pin    f0	f1	f2	f3   */
119 	MFP_XWAY(GPIO0, GPIO,	EXIN,	NONE,	TDM),
120 	MFP_XWAY(GPIO1, GPIO,	EXIN,	NONE,	NONE),
121 	MFP_XWAY(GPIO2, GPIO,	CGU,	EXIN,	GPHY),
122 	MFP_XWAY(GPIO3, GPIO,	CGU,	NONE,	PCI),
123 	MFP_XWAY(GPIO4, GPIO,	STP,	NONE,	ASC),
124 	MFP_XWAY(GPIO5, GPIO,	STP,	GPHY,	NONE),
125 	MFP_XWAY(GPIO6, GPIO,	STP,	GPT,	ASC),
126 	MFP_XWAY(GPIO7, GPIO,	CGU,	PCI,	GPHY),
127 	MFP_XWAY(GPIO8, GPIO,	CGU,	NMI,	NONE),
128 	MFP_XWAY(GPIO9, GPIO,	ASC,	SPI,	EXIN),
129 	MFP_XWAY(GPIO10, GPIO,	ASC,	SPI,	NONE),
130 	MFP_XWAY(GPIO11, GPIO,	ASC,	PCI,	SPI),
131 	MFP_XWAY(GPIO12, GPIO,	ASC,	NONE,	NONE),
132 	MFP_XWAY(GPIO13, GPIO,	EBU,	SPI,	NONE),
133 	MFP_XWAY(GPIO14, GPIO,	CGU,	PCI,	NONE),
134 	MFP_XWAY(GPIO15, GPIO,	SPI,	JTAG,	NONE),
135 	MFP_XWAY(GPIO16, GPIO,	SPI,	NONE,	JTAG),
136 	MFP_XWAY(GPIO17, GPIO,	SPI,	NONE,	JTAG),
137 	MFP_XWAY(GPIO18, GPIO,	SPI,	NONE,	JTAG),
138 	MFP_XWAY(GPIO19, GPIO,	PCI,	NONE,	NONE),
139 	MFP_XWAY(GPIO20, GPIO,	JTAG,	NONE,	NONE),
140 	MFP_XWAY(GPIO21, GPIO,	PCI,	EBU,	GPT),
141 	MFP_XWAY(GPIO22, GPIO,	SPI,	NONE,	NONE),
142 	MFP_XWAY(GPIO23, GPIO,	EBU,	PCI,	STP),
143 	MFP_XWAY(GPIO24, GPIO,	EBU,	TDM,	PCI),
144 	MFP_XWAY(GPIO25, GPIO,	TDM,	NONE,	ASC),
145 	MFP_XWAY(GPIO26, GPIO,	EBU,	NONE,	TDM),
146 	MFP_XWAY(GPIO27, GPIO,	TDM,	NONE,	ASC),
147 	MFP_XWAY(GPIO28, GPIO,	GPT,	NONE,	NONE),
148 	MFP_XWAY(GPIO29, GPIO,	PCI,	NONE,	NONE),
149 	MFP_XWAY(GPIO30, GPIO,	PCI,	NONE,	NONE),
150 	MFP_XWAY(GPIO31, GPIO,	EBU,	PCI,	NONE),
151 	MFP_XWAY(GPIO32, GPIO,	NONE,	NONE,	EBU),
152 	MFP_XWAY(GPIO33, GPIO,	NONE,	NONE,	EBU),
153 	MFP_XWAY(GPIO34, GPIO,	NONE,	NONE,	EBU),
154 	MFP_XWAY(GPIO35, GPIO,	NONE,	NONE,	EBU),
155 	MFP_XWAY(GPIO36, GPIO,	SIN,	NONE,	EBU),
156 	MFP_XWAY(GPIO37, GPIO,	PCI,	NONE,	NONE),
157 	MFP_XWAY(GPIO38, GPIO,	PCI,	NONE,	NONE),
158 	MFP_XWAY(GPIO39, GPIO,	EXIN,	NONE,	NONE),
159 	MFP_XWAY(GPIO40, GPIO,	NONE,	NONE,	NONE),
160 	MFP_XWAY(GPIO41, GPIO,	NONE,	NONE,	NONE),
161 	MFP_XWAY(GPIO42, GPIO,	MDIO,	NONE,	NONE),
162 	MFP_XWAY(GPIO43, GPIO,	MDIO,	NONE,	NONE),
163 	MFP_XWAY(GPIO44, GPIO,	MII,	SIN,	GPHY),
164 	MFP_XWAY(GPIO45, GPIO,	NONE,	GPHY,	SIN),
165 	MFP_XWAY(GPIO46, GPIO,	NONE,	NONE,	EXIN),
166 	MFP_XWAY(GPIO47, GPIO,	MII,	GPHY,	SIN),
167 	MFP_XWAY(GPIO48, GPIO,	EBU,	NONE,	NONE),
168 	MFP_XWAY(GPIO49, GPIO,	EBU,	NONE,	NONE),
169 	MFP_XWAY(GPIO50, GPIO,	NONE,	NONE,	NONE),
170 	MFP_XWAY(GPIO51, GPIO,	NONE,	NONE,	NONE),
171 	MFP_XWAY(GPIO52, GPIO,	NONE,	NONE,	NONE),
172 	MFP_XWAY(GPIO53, GPIO,	NONE,	NONE,	NONE),
173 	MFP_XWAY(GPIO54, GPIO,	NONE,	NONE,	NONE),
174 	MFP_XWAY(GPIO55, GPIO,	NONE,	NONE,	NONE),
175 };
176 
177 static const unsigned pins_jtag[] = {GPIO15, GPIO16, GPIO17, GPIO19, GPIO35};
178 static const unsigned pins_asc0[] = {GPIO11, GPIO12};
179 static const unsigned pins_asc0_cts_rts[] = {GPIO9, GPIO10};
180 static const unsigned pins_stp[] = {GPIO4, GPIO5, GPIO6};
181 static const unsigned pins_nmi[] = {GPIO8};
182 static const unsigned pins_mdio[] = {GPIO42, GPIO43};
183 
184 static const unsigned pins_gphy0_led0[] = {GPIO5};
185 static const unsigned pins_gphy0_led1[] = {GPIO7};
186 static const unsigned pins_gphy0_led2[] = {GPIO2};
187 static const unsigned pins_gphy1_led0[] = {GPIO44};
188 static const unsigned pins_gphy1_led1[] = {GPIO45};
189 static const unsigned pins_gphy1_led2[] = {GPIO47};
190 
191 static const unsigned pins_ebu_a24[] = {GPIO13};
192 static const unsigned pins_ebu_clk[] = {GPIO21};
193 static const unsigned pins_ebu_cs1[] = {GPIO23};
194 static const unsigned pins_ebu_a23[] = {GPIO24};
195 static const unsigned pins_ebu_wait[] = {GPIO26};
196 static const unsigned pins_ebu_a25[] = {GPIO31};
197 static const unsigned pins_ebu_rdy[] = {GPIO48};
198 static const unsigned pins_ebu_rd[] = {GPIO49};
199 
200 static const unsigned pins_nand_ale[] = {GPIO13};
201 static const unsigned pins_nand_cs1[] = {GPIO23};
202 static const unsigned pins_nand_cle[] = {GPIO24};
203 static const unsigned pins_nand_rdy[] = {GPIO48};
204 static const unsigned pins_nand_rd[] = {GPIO49};
205 
206 static const unsigned xway_exin_pin_map[] = {GPIO0, GPIO1, GPIO2, GPIO39, GPIO46, GPIO9};
207 
208 static const unsigned pins_exin0[] = {GPIO0};
209 static const unsigned pins_exin1[] = {GPIO1};
210 static const unsigned pins_exin2[] = {GPIO2};
211 static const unsigned pins_exin3[] = {GPIO39};
212 static const unsigned pins_exin4[] = {GPIO46};
213 static const unsigned pins_exin5[] = {GPIO9};
214 
215 static const unsigned pins_spi[] = {GPIO16, GPIO17, GPIO18};
216 static const unsigned pins_spi_cs1[] = {GPIO15};
217 static const unsigned pins_spi_cs2[] = {GPIO22};
218 static const unsigned pins_spi_cs3[] = {GPIO13};
219 static const unsigned pins_spi_cs4[] = {GPIO10};
220 static const unsigned pins_spi_cs5[] = {GPIO9};
221 static const unsigned pins_spi_cs6[] = {GPIO11};
222 
223 static const unsigned pins_gpt1[] = {GPIO28};
224 static const unsigned pins_gpt2[] = {GPIO21};
225 static const unsigned pins_gpt3[] = {GPIO6};
226 
227 static const unsigned pins_clkout0[] = {GPIO8};
228 static const unsigned pins_clkout1[] = {GPIO7};
229 static const unsigned pins_clkout2[] = {GPIO3};
230 static const unsigned pins_clkout3[] = {GPIO2};
231 
232 static const unsigned pins_pci_gnt1[] = {GPIO30};
233 static const unsigned pins_pci_gnt2[] = {GPIO23};
234 static const unsigned pins_pci_gnt3[] = {GPIO19};
235 static const unsigned pins_pci_gnt4[] = {GPIO38};
236 static const unsigned pins_pci_req1[] = {GPIO29};
237 static const unsigned pins_pci_req2[] = {GPIO31};
238 static const unsigned pins_pci_req3[] = {GPIO3};
239 static const unsigned pins_pci_req4[] = {GPIO37};
240 
241 static const struct ltq_pin_group xway_grps[] = {
242 	GRP_MUX("exin0", EXIN, pins_exin0),
243 	GRP_MUX("exin1", EXIN, pins_exin1),
244 	GRP_MUX("exin2", EXIN, pins_exin2),
245 	GRP_MUX("jtag", JTAG, pins_jtag),
246 	GRP_MUX("ebu a23", EBU, pins_ebu_a23),
247 	GRP_MUX("ebu a24", EBU, pins_ebu_a24),
248 	GRP_MUX("ebu a25", EBU, pins_ebu_a25),
249 	GRP_MUX("ebu clk", EBU, pins_ebu_clk),
250 	GRP_MUX("ebu cs1", EBU, pins_ebu_cs1),
251 	GRP_MUX("ebu wait", EBU, pins_ebu_wait),
252 	GRP_MUX("nand ale", EBU, pins_nand_ale),
253 	GRP_MUX("nand cs1", EBU, pins_nand_cs1),
254 	GRP_MUX("nand cle", EBU, pins_nand_cle),
255 	GRP_MUX("spi", SPI, pins_spi),
256 	GRP_MUX("spi_cs1", SPI, pins_spi_cs1),
257 	GRP_MUX("spi_cs2", SPI, pins_spi_cs2),
258 	GRP_MUX("spi_cs3", SPI, pins_spi_cs3),
259 	GRP_MUX("spi_cs4", SPI, pins_spi_cs4),
260 	GRP_MUX("spi_cs5", SPI, pins_spi_cs5),
261 	GRP_MUX("spi_cs6", SPI, pins_spi_cs6),
262 	GRP_MUX("asc0", ASC, pins_asc0),
263 	GRP_MUX("asc0 cts rts", ASC, pins_asc0_cts_rts),
264 	GRP_MUX("stp", STP, pins_stp),
265 	GRP_MUX("nmi", NMI, pins_nmi),
266 	GRP_MUX("gpt1", GPT, pins_gpt1),
267 	GRP_MUX("gpt2", GPT, pins_gpt2),
268 	GRP_MUX("gpt3", GPT, pins_gpt3),
269 	GRP_MUX("clkout0", CGU, pins_clkout0),
270 	GRP_MUX("clkout1", CGU, pins_clkout1),
271 	GRP_MUX("clkout2", CGU, pins_clkout2),
272 	GRP_MUX("clkout3", CGU, pins_clkout3),
273 	GRP_MUX("gnt1", PCI, pins_pci_gnt1),
274 	GRP_MUX("gnt2", PCI, pins_pci_gnt2),
275 	GRP_MUX("gnt3", PCI, pins_pci_gnt3),
276 	GRP_MUX("req1", PCI, pins_pci_req1),
277 	GRP_MUX("req2", PCI, pins_pci_req2),
278 	GRP_MUX("req3", PCI, pins_pci_req3),
279 /* xrx only */
280 	GRP_MUX("nand rdy", EBU, pins_nand_rdy),
281 	GRP_MUX("nand rd", EBU, pins_nand_rd),
282 	GRP_MUX("exin3", EXIN, pins_exin3),
283 	GRP_MUX("exin4", EXIN, pins_exin4),
284 	GRP_MUX("exin5", EXIN, pins_exin5),
285 	GRP_MUX("gnt4", PCI, pins_pci_gnt4),
286 	GRP_MUX("req4", PCI, pins_pci_gnt4),
287 	GRP_MUX("mdio", MDIO, pins_mdio),
288 	GRP_MUX("gphy0 led0", GPHY, pins_gphy0_led0),
289 	GRP_MUX("gphy0 led1", GPHY, pins_gphy0_led1),
290 	GRP_MUX("gphy0 led2", GPHY, pins_gphy0_led2),
291 	GRP_MUX("gphy1 led0", GPHY, pins_gphy1_led0),
292 	GRP_MUX("gphy1 led1", GPHY, pins_gphy1_led1),
293 	GRP_MUX("gphy1 led2", GPHY, pins_gphy1_led2),
294 };
295 
296 static const char * const xway_pci_grps[] = {"gnt1", "gnt2",
297 						"gnt3", "req1",
298 						"req2", "req3"};
299 static const char * const xway_spi_grps[] = {"spi", "spi_cs1",
300 						"spi_cs2", "spi_cs3",
301 						"spi_cs4", "spi_cs5",
302 						"spi_cs6"};
303 static const char * const xway_cgu_grps[] = {"clkout0", "clkout1",
304 						"clkout2", "clkout3"};
305 static const char * const xway_ebu_grps[] = {"ebu a23", "ebu a24",
306 						"ebu a25", "ebu cs1",
307 						"ebu wait", "ebu clk",
308 						"nand ale", "nand cs1",
309 						"nand cle"};
310 static const char * const xway_exin_grps[] = {"exin0", "exin1", "exin2"};
311 static const char * const xway_gpt_grps[] = {"gpt1", "gpt2", "gpt3"};
312 static const char * const xway_asc_grps[] = {"asc0", "asc0 cts rts"};
313 static const char * const xway_jtag_grps[] = {"jtag"};
314 static const char * const xway_stp_grps[] = {"stp"};
315 static const char * const xway_nmi_grps[] = {"nmi"};
316 
317 /* ar9/vr9/gr9 */
318 static const char * const xrx_mdio_grps[] = {"mdio"};
319 static const char * const xrx_gphy_grps[] = {"gphy0 led0", "gphy0 led1",
320 						"gphy0 led2", "gphy1 led0",
321 						"gphy1 led1", "gphy1 led2"};
322 static const char * const xrx_ebu_grps[] = {"ebu a23", "ebu a24",
323 						"ebu a25", "ebu cs1",
324 						"ebu wait", "ebu clk",
325 						"nand ale", "nand cs1",
326 						"nand cle", "nand rdy",
327 						"nand rd"};
328 static const char * const xrx_exin_grps[] = {"exin0", "exin1", "exin2",
329 						"exin3", "exin4", "exin5"};
330 static const char * const xrx_pci_grps[] = {"gnt1", "gnt2",
331 						"gnt3", "gnt4",
332 						"req1", "req2",
333 						"req3", "req4"};
334 
335 static const struct ltq_pmx_func xrx_funcs[] = {
336 	{"spi",		ARRAY_AND_SIZE(xway_spi_grps)},
337 	{"asc",		ARRAY_AND_SIZE(xway_asc_grps)},
338 	{"cgu",		ARRAY_AND_SIZE(xway_cgu_grps)},
339 	{"jtag",	ARRAY_AND_SIZE(xway_jtag_grps)},
340 	{"exin",	ARRAY_AND_SIZE(xrx_exin_grps)},
341 	{"stp",		ARRAY_AND_SIZE(xway_stp_grps)},
342 	{"gpt",		ARRAY_AND_SIZE(xway_gpt_grps)},
343 	{"nmi",		ARRAY_AND_SIZE(xway_nmi_grps)},
344 	{"pci",		ARRAY_AND_SIZE(xrx_pci_grps)},
345 	{"ebu",		ARRAY_AND_SIZE(xrx_ebu_grps)},
346 	{"mdio",	ARRAY_AND_SIZE(xrx_mdio_grps)},
347 	{"gphy",	ARRAY_AND_SIZE(xrx_gphy_grps)},
348 };
349 
350 /* ---------  ase related code --------- */
351 #define ASE_MAX_PIN		32
352 
353 static const struct ltq_mfp_pin ase_mfp[] = {
354 	/*       pin    f0	f1	f2	f3   */
355 	MFP_XWAY(GPIO0, GPIO,	EXIN,	MII,	TDM),
356 	MFP_XWAY(GPIO1, GPIO,	STP,	DFE,	EBU),
357 	MFP_XWAY(GPIO2, GPIO,	STP,	DFE,	EPHY),
358 	MFP_XWAY(GPIO3, GPIO,	STP,	EPHY,	EBU),
359 	MFP_XWAY(GPIO4, GPIO,	GPT,	EPHY,	MII),
360 	MFP_XWAY(GPIO5, GPIO,	MII,	ASC,	GPT),
361 	MFP_XWAY(GPIO6, GPIO,	MII,	ASC,	EXIN),
362 	MFP_XWAY(GPIO7, GPIO,	SPI,	MII,	JTAG),
363 	MFP_XWAY(GPIO8, GPIO,	SPI,	MII,	JTAG),
364 	MFP_XWAY(GPIO9, GPIO,	SPI,	MII,	JTAG),
365 	MFP_XWAY(GPIO10, GPIO,	SPI,	MII,	JTAG),
366 	MFP_XWAY(GPIO11, GPIO,	EBU,	CGU,	JTAG),
367 	MFP_XWAY(GPIO12, GPIO,	EBU,	MII,	SDIO),
368 	MFP_XWAY(GPIO13, GPIO,	EBU,	MII,	CGU),
369 	MFP_XWAY(GPIO14, GPIO,	EBU,	SPI,	CGU),
370 	MFP_XWAY(GPIO15, GPIO,	EBU,	SPI,	SDIO),
371 	MFP_XWAY(GPIO16, GPIO,	NONE,	NONE,	NONE),
372 	MFP_XWAY(GPIO17, GPIO,	NONE,	NONE,	NONE),
373 	MFP_XWAY(GPIO18, GPIO,	NONE,	NONE,	NONE),
374 	MFP_XWAY(GPIO19, GPIO,	EBU,	MII,	SDIO),
375 	MFP_XWAY(GPIO20, GPIO,	EBU,	MII,	SDIO),
376 	MFP_XWAY(GPIO21, GPIO,	EBU,	MII,	EBU2),
377 	MFP_XWAY(GPIO22, GPIO,	EBU,	MII,	CGU),
378 	MFP_XWAY(GPIO23, GPIO,	EBU,	MII,	CGU),
379 	MFP_XWAY(GPIO24, GPIO,	EBU,	EBU2,	MDIO),
380 	MFP_XWAY(GPIO25, GPIO,	EBU,	MII,	GPT),
381 	MFP_XWAY(GPIO26, GPIO,	EBU,	MII,	SDIO),
382 	MFP_XWAY(GPIO27, GPIO,	EBU,	NONE,	MDIO),
383 	MFP_XWAY(GPIO28, GPIO,	MII,	EBU,	SDIO),
384 	MFP_XWAY(GPIO29, GPIO,	EBU,	MII,	EXIN),
385 	MFP_XWAY(GPIO30, GPIO,	NONE,	NONE,	NONE),
386 	MFP_XWAY(GPIO31, GPIO,	NONE,	NONE,	NONE),
387 };
388 
389 static const unsigned ase_exin_pin_map[] = {GPIO6, GPIO29, GPIO0};
390 
391 static const unsigned ase_pins_exin0[] = {GPIO6};
392 static const unsigned ase_pins_exin1[] = {GPIO29};
393 static const unsigned ase_pins_exin2[] = {GPIO0};
394 
395 static const unsigned ase_pins_jtag[] = {GPIO7, GPIO8, GPIO9, GPIO10, GPIO11};
396 static const unsigned ase_pins_asc[] = {GPIO5, GPIO6};
397 static const unsigned ase_pins_stp[] = {GPIO1, GPIO2, GPIO3};
398 static const unsigned ase_pins_mdio[] = {GPIO24, GPIO27};
399 static const unsigned ase_pins_ephy_led0[] = {GPIO2};
400 static const unsigned ase_pins_ephy_led1[] = {GPIO3};
401 static const unsigned ase_pins_ephy_led2[] = {GPIO4};
402 static const unsigned ase_pins_dfe_led0[] = {GPIO1};
403 static const unsigned ase_pins_dfe_led1[] = {GPIO2};
404 
405 static const unsigned ase_pins_spi[] = {GPIO8, GPIO9, GPIO10}; /* DEPRECATED */
406 static const unsigned ase_pins_spi_di[] = {GPIO8};
407 static const unsigned ase_pins_spi_do[] = {GPIO9};
408 static const unsigned ase_pins_spi_clk[] = {GPIO10};
409 static const unsigned ase_pins_spi_cs1[] = {GPIO7};
410 static const unsigned ase_pins_spi_cs2[] = {GPIO15};
411 static const unsigned ase_pins_spi_cs3[] = {GPIO14};
412 
413 static const unsigned ase_pins_gpt1[] = {GPIO5};
414 static const unsigned ase_pins_gpt2[] = {GPIO4};
415 static const unsigned ase_pins_gpt3[] = {GPIO25};
416 
417 static const unsigned ase_pins_clkout0[] = {GPIO23};
418 static const unsigned ase_pins_clkout1[] = {GPIO22};
419 static const unsigned ase_pins_clkout2[] = {GPIO14};
420 
421 static const struct ltq_pin_group ase_grps[] = {
422 	GRP_MUX("exin0", EXIN, ase_pins_exin0),
423 	GRP_MUX("exin1", EXIN, ase_pins_exin1),
424 	GRP_MUX("exin2", EXIN, ase_pins_exin2),
425 	GRP_MUX("jtag", JTAG, ase_pins_jtag),
426 	GRP_MUX("spi", SPI, ase_pins_spi), /* DEPRECATED */
427 	GRP_MUX("spi_di", SPI, ase_pins_spi_di),
428 	GRP_MUX("spi_do", SPI, ase_pins_spi_do),
429 	GRP_MUX("spi_clk", SPI, ase_pins_spi_clk),
430 	GRP_MUX("spi_cs1", SPI, ase_pins_spi_cs1),
431 	GRP_MUX("spi_cs2", SPI, ase_pins_spi_cs2),
432 	GRP_MUX("spi_cs3", SPI, ase_pins_spi_cs3),
433 	GRP_MUX("asc", ASC, ase_pins_asc),
434 	GRP_MUX("stp", STP, ase_pins_stp),
435 	GRP_MUX("gpt1", GPT, ase_pins_gpt1),
436 	GRP_MUX("gpt2", GPT, ase_pins_gpt2),
437 	GRP_MUX("gpt3", GPT, ase_pins_gpt3),
438 	GRP_MUX("clkout0", CGU, ase_pins_clkout0),
439 	GRP_MUX("clkout1", CGU, ase_pins_clkout1),
440 	GRP_MUX("clkout2", CGU, ase_pins_clkout2),
441 	GRP_MUX("mdio", MDIO, ase_pins_mdio),
442 	GRP_MUX("dfe led0", DFE, ase_pins_dfe_led0),
443 	GRP_MUX("dfe led1", DFE, ase_pins_dfe_led1),
444 	GRP_MUX("ephy led0", EPHY, ase_pins_ephy_led0),
445 	GRP_MUX("ephy led1", EPHY, ase_pins_ephy_led1),
446 	GRP_MUX("ephy led2", EPHY, ase_pins_ephy_led2),
447 };
448 
449 static const char * const ase_exin_grps[] = {"exin0", "exin1", "exin2"};
450 static const char * const ase_gpt_grps[] = {"gpt1", "gpt2", "gpt3"};
451 static const char * const ase_cgu_grps[] = {"clkout0", "clkout1",
452 						"clkout2"};
453 static const char * const ase_mdio_grps[] = {"mdio"};
454 static const char * const ase_dfe_grps[] = {"dfe led0", "dfe led1"};
455 static const char * const ase_ephy_grps[] = {"ephy led0", "ephy led1",
456 						"ephy led2"};
457 static const char * const ase_asc_grps[] = {"asc"};
458 static const char * const ase_jtag_grps[] = {"jtag"};
459 static const char * const ase_stp_grps[] = {"stp"};
460 static const char * const ase_spi_grps[] = {"spi",  /* DEPRECATED */
461 						"spi_di", "spi_do",
462 						"spi_clk", "spi_cs1",
463 						"spi_cs2", "spi_cs3"};
464 
465 static const struct ltq_pmx_func ase_funcs[] = {
466 	{"spi",		ARRAY_AND_SIZE(ase_spi_grps)},
467 	{"asc",		ARRAY_AND_SIZE(ase_asc_grps)},
468 	{"cgu",		ARRAY_AND_SIZE(ase_cgu_grps)},
469 	{"jtag",	ARRAY_AND_SIZE(ase_jtag_grps)},
470 	{"exin",	ARRAY_AND_SIZE(ase_exin_grps)},
471 	{"stp",		ARRAY_AND_SIZE(ase_stp_grps)},
472 	{"gpt",		ARRAY_AND_SIZE(ase_gpt_grps)},
473 	{"mdio",	ARRAY_AND_SIZE(ase_mdio_grps)},
474 	{"ephy",	ARRAY_AND_SIZE(ase_ephy_grps)},
475 	{"dfe",		ARRAY_AND_SIZE(ase_dfe_grps)},
476 };
477 
478 /* ---------  danube related code --------- */
479 #define DANUBE_MAX_PIN		32
480 
481 static const struct ltq_mfp_pin danube_mfp[] = {
482 	/*       pin    f0	f1	f2	f3   */
483 	MFP_XWAY(GPIO0, GPIO,	EXIN,	SDIO,	TDM),
484 	MFP_XWAY(GPIO1, GPIO,	EXIN,	CBUS,	MII),
485 	MFP_XWAY(GPIO2, GPIO,	CGU,	EXIN,	MII),
486 	MFP_XWAY(GPIO3, GPIO,	CGU,	SDIO,	PCI),
487 	MFP_XWAY(GPIO4, GPIO,	STP,	DFE,	ASC),
488 	MFP_XWAY(GPIO5, GPIO,	STP,	MII,	DFE),
489 	MFP_XWAY(GPIO6, GPIO,	STP,	GPT,	ASC),
490 	MFP_XWAY(GPIO7, GPIO,	CGU,	CBUS,	MII),
491 	MFP_XWAY(GPIO8, GPIO,	CGU,	NMI,	MII),
492 	MFP_XWAY(GPIO9, GPIO,	ASC,	SPI,	MII),
493 	MFP_XWAY(GPIO10, GPIO,	ASC,	SPI,	MII),
494 	MFP_XWAY(GPIO11, GPIO,	ASC,	CBUS,	SPI),
495 	MFP_XWAY(GPIO12, GPIO,	ASC,	CBUS,	MCD),
496 	MFP_XWAY(GPIO13, GPIO,	EBU,	SPI,	MII),
497 	MFP_XWAY(GPIO14, GPIO,	CGU,	CBUS,	MII),
498 	MFP_XWAY(GPIO15, GPIO,	SPI,	SDIO,	JTAG),
499 	MFP_XWAY(GPIO16, GPIO,	SPI,	SDIO,	JTAG),
500 	MFP_XWAY(GPIO17, GPIO,	SPI,	SDIO,	JTAG),
501 	MFP_XWAY(GPIO18, GPIO,	SPI,	SDIO,	JTAG),
502 	MFP_XWAY(GPIO19, GPIO,	PCI,	SDIO,	MII),
503 	MFP_XWAY(GPIO20, GPIO,	JTAG,	SDIO,	MII),
504 	MFP_XWAY(GPIO21, GPIO,	PCI,	EBU,	GPT),
505 	MFP_XWAY(GPIO22, GPIO,	SPI,	MCD,	MII),
506 	MFP_XWAY(GPIO23, GPIO,	EBU,	PCI,	STP),
507 	MFP_XWAY(GPIO24, GPIO,	EBU,	TDM,	PCI),
508 	MFP_XWAY(GPIO25, GPIO,	TDM,	SDIO,	ASC),
509 	MFP_XWAY(GPIO26, GPIO,	EBU,	TDM,	SDIO),
510 	MFP_XWAY(GPIO27, GPIO,	TDM,	SDIO,	ASC),
511 	MFP_XWAY(GPIO28, GPIO,	GPT,	MII,	SDIO),
512 	MFP_XWAY(GPIO29, GPIO,	PCI,	CBUS,	MII),
513 	MFP_XWAY(GPIO30, GPIO,	PCI,	CBUS,	MII),
514 	MFP_XWAY(GPIO31, GPIO,	EBU,	PCI,	MII),
515 };
516 
517 static const unsigned danube_exin_pin_map[] = {GPIO0, GPIO1, GPIO2};
518 
519 static const unsigned danube_pins_exin0[] = {GPIO0};
520 static const unsigned danube_pins_exin1[] = {GPIO1};
521 static const unsigned danube_pins_exin2[] = {GPIO2};
522 
523 static const unsigned danube_pins_jtag[] = {GPIO15, GPIO16, GPIO17, GPIO18, GPIO20};
524 static const unsigned danube_pins_asc0[] = {GPIO11, GPIO12};
525 static const unsigned danube_pins_asc0_cts_rts[] = {GPIO9, GPIO10};
526 static const unsigned danube_pins_stp[] = {GPIO4, GPIO5, GPIO6};
527 static const unsigned danube_pins_nmi[] = {GPIO8};
528 
529 static const unsigned danube_pins_dfe_led0[] = {GPIO4};
530 static const unsigned danube_pins_dfe_led1[] = {GPIO5};
531 
532 static const unsigned danube_pins_ebu_a24[] = {GPIO13};
533 static const unsigned danube_pins_ebu_clk[] = {GPIO21};
534 static const unsigned danube_pins_ebu_cs1[] = {GPIO23};
535 static const unsigned danube_pins_ebu_a23[] = {GPIO24};
536 static const unsigned danube_pins_ebu_wait[] = {GPIO26};
537 static const unsigned danube_pins_ebu_a25[] = {GPIO31};
538 
539 static const unsigned danube_pins_nand_ale[] = {GPIO13};
540 static const unsigned danube_pins_nand_cs1[] = {GPIO23};
541 static const unsigned danube_pins_nand_cle[] = {GPIO24};
542 
543 static const unsigned danube_pins_spi[] = {GPIO16, GPIO17, GPIO18}; /* DEPRECATED */
544 static const unsigned danube_pins_spi_di[] = {GPIO16};
545 static const unsigned danube_pins_spi_do[] = {GPIO17};
546 static const unsigned danube_pins_spi_clk[] = {GPIO18};
547 static const unsigned danube_pins_spi_cs1[] = {GPIO15};
548 static const unsigned danube_pins_spi_cs2[] = {GPIO21};
549 static const unsigned danube_pins_spi_cs3[] = {GPIO13};
550 static const unsigned danube_pins_spi_cs4[] = {GPIO10};
551 static const unsigned danube_pins_spi_cs5[] = {GPIO9};
552 static const unsigned danube_pins_spi_cs6[] = {GPIO11};
553 
554 static const unsigned danube_pins_gpt1[] = {GPIO28};
555 static const unsigned danube_pins_gpt2[] = {GPIO21};
556 static const unsigned danube_pins_gpt3[] = {GPIO6};
557 
558 static const unsigned danube_pins_clkout0[] = {GPIO8};
559 static const unsigned danube_pins_clkout1[] = {GPIO7};
560 static const unsigned danube_pins_clkout2[] = {GPIO3};
561 static const unsigned danube_pins_clkout3[] = {GPIO2};
562 
563 static const unsigned danube_pins_pci_gnt1[] = {GPIO30};
564 static const unsigned danube_pins_pci_gnt2[] = {GPIO23};
565 static const unsigned danube_pins_pci_gnt3[] = {GPIO19};
566 static const unsigned danube_pins_pci_req1[] = {GPIO29};
567 static const unsigned danube_pins_pci_req2[] = {GPIO31};
568 static const unsigned danube_pins_pci_req3[] = {GPIO3};
569 
570 static const struct ltq_pin_group danube_grps[] = {
571 	GRP_MUX("exin0", EXIN, danube_pins_exin0),
572 	GRP_MUX("exin1", EXIN, danube_pins_exin1),
573 	GRP_MUX("exin2", EXIN, danube_pins_exin2),
574 	GRP_MUX("jtag", JTAG, danube_pins_jtag),
575 	GRP_MUX("ebu a23", EBU, danube_pins_ebu_a23),
576 	GRP_MUX("ebu a24", EBU, danube_pins_ebu_a24),
577 	GRP_MUX("ebu a25", EBU, danube_pins_ebu_a25),
578 	GRP_MUX("ebu clk", EBU, danube_pins_ebu_clk),
579 	GRP_MUX("ebu cs1", EBU, danube_pins_ebu_cs1),
580 	GRP_MUX("ebu wait", EBU, danube_pins_ebu_wait),
581 	GRP_MUX("nand ale", EBU, danube_pins_nand_ale),
582 	GRP_MUX("nand cs1", EBU, danube_pins_nand_cs1),
583 	GRP_MUX("nand cle", EBU, danube_pins_nand_cle),
584 	GRP_MUX("spi", SPI, danube_pins_spi), /* DEPRECATED */
585 	GRP_MUX("spi_di", SPI, danube_pins_spi_di),
586 	GRP_MUX("spi_do", SPI, danube_pins_spi_do),
587 	GRP_MUX("spi_clk", SPI, danube_pins_spi_clk),
588 	GRP_MUX("spi_cs1", SPI, danube_pins_spi_cs1),
589 	GRP_MUX("spi_cs2", SPI, danube_pins_spi_cs2),
590 	GRP_MUX("spi_cs3", SPI, danube_pins_spi_cs3),
591 	GRP_MUX("spi_cs4", SPI, danube_pins_spi_cs4),
592 	GRP_MUX("spi_cs5", SPI, danube_pins_spi_cs5),
593 	GRP_MUX("spi_cs6", SPI, danube_pins_spi_cs6),
594 	GRP_MUX("asc0", ASC, danube_pins_asc0),
595 	GRP_MUX("asc0 cts rts", ASC, danube_pins_asc0_cts_rts),
596 	GRP_MUX("stp", STP, danube_pins_stp),
597 	GRP_MUX("nmi", NMI, danube_pins_nmi),
598 	GRP_MUX("gpt1", GPT, danube_pins_gpt1),
599 	GRP_MUX("gpt2", GPT, danube_pins_gpt2),
600 	GRP_MUX("gpt3", GPT, danube_pins_gpt3),
601 	GRP_MUX("clkout0", CGU, danube_pins_clkout0),
602 	GRP_MUX("clkout1", CGU, danube_pins_clkout1),
603 	GRP_MUX("clkout2", CGU, danube_pins_clkout2),
604 	GRP_MUX("clkout3", CGU, danube_pins_clkout3),
605 	GRP_MUX("gnt1", PCI, danube_pins_pci_gnt1),
606 	GRP_MUX("gnt2", PCI, danube_pins_pci_gnt2),
607 	GRP_MUX("gnt3", PCI, danube_pins_pci_gnt3),
608 	GRP_MUX("req1", PCI, danube_pins_pci_req1),
609 	GRP_MUX("req2", PCI, danube_pins_pci_req2),
610 	GRP_MUX("req3", PCI, danube_pins_pci_req3),
611 	GRP_MUX("dfe led0", DFE, danube_pins_dfe_led0),
612 	GRP_MUX("dfe led1", DFE, danube_pins_dfe_led1),
613 };
614 
615 static const char * const danube_pci_grps[] = {"gnt1", "gnt2",
616 						"gnt3", "req1",
617 						"req2", "req3"};
618 static const char * const danube_spi_grps[] = {"spi", /* DEPRECATED */
619 						"spi_di", "spi_do",
620 						"spi_clk", "spi_cs1",
621 						"spi_cs2", "spi_cs3",
622 						"spi_cs4", "spi_cs5",
623 						"spi_cs6"};
624 static const char * const danube_cgu_grps[] = {"clkout0", "clkout1",
625 						"clkout2", "clkout3"};
626 static const char * const danube_ebu_grps[] = {"ebu a23", "ebu a24",
627 						"ebu a25", "ebu cs1",
628 						"ebu wait", "ebu clk",
629 						"nand ale", "nand cs1",
630 						"nand cle"};
631 static const char * const danube_dfe_grps[] = {"dfe led0", "dfe led1"};
632 static const char * const danube_exin_grps[] = {"exin0", "exin1", "exin2"};
633 static const char * const danube_gpt_grps[] = {"gpt1", "gpt2", "gpt3"};
634 static const char * const danube_asc_grps[] = {"asc0", "asc0 cts rts"};
635 static const char * const danube_jtag_grps[] = {"jtag"};
636 static const char * const danube_stp_grps[] = {"stp"};
637 static const char * const danube_nmi_grps[] = {"nmi"};
638 
639 static const struct ltq_pmx_func danube_funcs[] = {
640 	{"spi",		ARRAY_AND_SIZE(danube_spi_grps)},
641 	{"asc",		ARRAY_AND_SIZE(danube_asc_grps)},
642 	{"cgu",		ARRAY_AND_SIZE(danube_cgu_grps)},
643 	{"jtag",	ARRAY_AND_SIZE(danube_jtag_grps)},
644 	{"exin",	ARRAY_AND_SIZE(danube_exin_grps)},
645 	{"stp",		ARRAY_AND_SIZE(danube_stp_grps)},
646 	{"gpt",		ARRAY_AND_SIZE(danube_gpt_grps)},
647 	{"nmi",		ARRAY_AND_SIZE(danube_nmi_grps)},
648 	{"pci",		ARRAY_AND_SIZE(danube_pci_grps)},
649 	{"ebu",		ARRAY_AND_SIZE(danube_ebu_grps)},
650 	{"dfe",		ARRAY_AND_SIZE(danube_dfe_grps)},
651 };
652 
653 /* ---------  xrx100 related code --------- */
654 #define XRX100_MAX_PIN		56
655 
656 static const struct ltq_mfp_pin xrx100_mfp[] = {
657 	/*       pin    f0	f1	f2	f3   */
658 	MFP_XWAY(GPIO0, GPIO,	EXIN,	SDIO,	TDM),
659 	MFP_XWAY(GPIO1, GPIO,	EXIN,	CBUS,	SIN),
660 	MFP_XWAY(GPIO2, GPIO,	CGU,	EXIN,	NONE),
661 	MFP_XWAY(GPIO3, GPIO,	CGU,	SDIO,	PCI),
662 	MFP_XWAY(GPIO4, GPIO,	STP,	DFE,	ASC),
663 	MFP_XWAY(GPIO5, GPIO,	STP,	NONE,	DFE),
664 	MFP_XWAY(GPIO6, GPIO,	STP,	GPT,	ASC),
665 	MFP_XWAY(GPIO7, GPIO,	CGU,	CBUS,	NONE),
666 	MFP_XWAY(GPIO8, GPIO,	CGU,	NMI,	NONE),
667 	MFP_XWAY(GPIO9, GPIO,	ASC,	SPI,	EXIN),
668 	MFP_XWAY(GPIO10, GPIO,	ASC,	SPI,	EXIN),
669 	MFP_XWAY(GPIO11, GPIO,	ASC,	CBUS,	SPI),
670 	MFP_XWAY(GPIO12, GPIO,	ASC,	CBUS,	MCD),
671 	MFP_XWAY(GPIO13, GPIO,	EBU,	SPI,	NONE),
672 	MFP_XWAY(GPIO14, GPIO,	CGU,	NONE,	NONE),
673 	MFP_XWAY(GPIO15, GPIO,	SPI,	SDIO,	MCD),
674 	MFP_XWAY(GPIO16, GPIO,	SPI,	SDIO,	NONE),
675 	MFP_XWAY(GPIO17, GPIO,	SPI,	SDIO,	NONE),
676 	MFP_XWAY(GPIO18, GPIO,	SPI,	SDIO,	NONE),
677 	MFP_XWAY(GPIO19, GPIO,	PCI,	SDIO,	CGU),
678 	MFP_XWAY(GPIO20, GPIO,	NONE,	SDIO,	EBU),
679 	MFP_XWAY(GPIO21, GPIO,	PCI,	EBU,	GPT),
680 	MFP_XWAY(GPIO22, GPIO,	SPI,	NONE,	EBU),
681 	MFP_XWAY(GPIO23, GPIO,	EBU,	PCI,	STP),
682 	MFP_XWAY(GPIO24, GPIO,	EBU,	TDM,	PCI),
683 	MFP_XWAY(GPIO25, GPIO,	TDM,	SDIO,	ASC),
684 	MFP_XWAY(GPIO26, GPIO,	EBU,	TDM,	SDIO),
685 	MFP_XWAY(GPIO27, GPIO,	TDM,	SDIO,	ASC),
686 	MFP_XWAY(GPIO28, GPIO,	GPT,	NONE,	SDIO),
687 	MFP_XWAY(GPIO29, GPIO,	PCI,	CBUS,	NONE),
688 	MFP_XWAY(GPIO30, GPIO,	PCI,	CBUS,	NONE),
689 	MFP_XWAY(GPIO31, GPIO,	EBU,	PCI,	NONE),
690 	MFP_XWAY(GPIO32, GPIO,	MII,	NONE,	EBU),
691 	MFP_XWAY(GPIO33, GPIO,	MII,	NONE,	EBU),
692 	MFP_XWAY(GPIO34, GPIO,	SIN,	SSI,	NONE),
693 	MFP_XWAY(GPIO35, GPIO,	SIN,	SSI,	NONE),
694 	MFP_XWAY(GPIO36, GPIO,	SIN,	SSI,	NONE),
695 	MFP_XWAY(GPIO37, GPIO,	PCI,	NONE,	NONE),
696 	MFP_XWAY(GPIO38, GPIO,	PCI,	NONE,	NONE),
697 	MFP_XWAY(GPIO39, GPIO,	NONE,	EXIN,	NONE),
698 	MFP_XWAY(GPIO40, GPIO,	MII,	TDM,	NONE),
699 	MFP_XWAY(GPIO41, GPIO,	MII,	TDM,	NONE),
700 	MFP_XWAY(GPIO42, GPIO,	MDIO,	NONE,	NONE),
701 	MFP_XWAY(GPIO43, GPIO,	MDIO,	NONE,	NONE),
702 	MFP_XWAY(GPIO44, GPIO,	MII,	SIN,	NONE),
703 	MFP_XWAY(GPIO45, GPIO,	MII,	NONE,	SIN),
704 	MFP_XWAY(GPIO46, GPIO,	MII,	NONE,	EXIN),
705 	MFP_XWAY(GPIO47, GPIO,	MII,	NONE,	SIN),
706 	MFP_XWAY(GPIO48, GPIO,	EBU,	NONE,	NONE),
707 	MFP_XWAY(GPIO49, GPIO,	EBU,	NONE,	NONE),
708 	MFP_XWAY(GPIO50, GPIO,	NONE,	NONE,	NONE),
709 	MFP_XWAY(GPIO51, GPIO,	NONE,	NONE,	NONE),
710 	MFP_XWAY(GPIO52, GPIO,	NONE,	NONE,	NONE),
711 	MFP_XWAY(GPIO53, GPIO,	NONE,	NONE,	NONE),
712 	MFP_XWAY(GPIO54, GPIO,	NONE,	NONE,	NONE),
713 	MFP_XWAY(GPIO55, GPIO,	NONE,	NONE,	NONE),
714 };
715 
716 static const unsigned xrx100_exin_pin_map[] = {GPIO0, GPIO1, GPIO2, GPIO39, GPIO10, GPIO9};
717 
718 static const unsigned xrx100_pins_exin0[] = {GPIO0};
719 static const unsigned xrx100_pins_exin1[] = {GPIO1};
720 static const unsigned xrx100_pins_exin2[] = {GPIO2};
721 static const unsigned xrx100_pins_exin3[] = {GPIO39};
722 static const unsigned xrx100_pins_exin4[] = {GPIO10};
723 static const unsigned xrx100_pins_exin5[] = {GPIO9};
724 
725 static const unsigned xrx100_pins_asc0[] = {GPIO11, GPIO12};
726 static const unsigned xrx100_pins_asc0_cts_rts[] = {GPIO9, GPIO10};
727 static const unsigned xrx100_pins_stp[] = {GPIO4, GPIO5, GPIO6};
728 static const unsigned xrx100_pins_nmi[] = {GPIO8};
729 static const unsigned xrx100_pins_mdio[] = {GPIO42, GPIO43};
730 
731 static const unsigned xrx100_pins_dfe_led0[] = {GPIO4};
732 static const unsigned xrx100_pins_dfe_led1[] = {GPIO5};
733 
734 static const unsigned xrx100_pins_ebu_a24[] = {GPIO13};
735 static const unsigned xrx100_pins_ebu_clk[] = {GPIO21};
736 static const unsigned xrx100_pins_ebu_cs1[] = {GPIO23};
737 static const unsigned xrx100_pins_ebu_a23[] = {GPIO24};
738 static const unsigned xrx100_pins_ebu_wait[] = {GPIO26};
739 static const unsigned xrx100_pins_ebu_a25[] = {GPIO31};
740 
741 static const unsigned xrx100_pins_nand_ale[] = {GPIO13};
742 static const unsigned xrx100_pins_nand_cs1[] = {GPIO23};
743 static const unsigned xrx100_pins_nand_cle[] = {GPIO24};
744 static const unsigned xrx100_pins_nand_rdy[] = {GPIO48};
745 static const unsigned xrx100_pins_nand_rd[] = {GPIO49};
746 
747 static const unsigned xrx100_pins_spi_di[] = {GPIO16};
748 static const unsigned xrx100_pins_spi_do[] = {GPIO17};
749 static const unsigned xrx100_pins_spi_clk[] = {GPIO18};
750 static const unsigned xrx100_pins_spi_cs1[] = {GPIO15};
751 static const unsigned xrx100_pins_spi_cs2[] = {GPIO22};
752 static const unsigned xrx100_pins_spi_cs3[] = {GPIO13};
753 static const unsigned xrx100_pins_spi_cs4[] = {GPIO10};
754 static const unsigned xrx100_pins_spi_cs5[] = {GPIO9};
755 static const unsigned xrx100_pins_spi_cs6[] = {GPIO11};
756 
757 static const unsigned xrx100_pins_gpt1[] = {GPIO28};
758 static const unsigned xrx100_pins_gpt2[] = {GPIO21};
759 static const unsigned xrx100_pins_gpt3[] = {GPIO6};
760 
761 static const unsigned xrx100_pins_clkout0[] = {GPIO8};
762 static const unsigned xrx100_pins_clkout1[] = {GPIO7};
763 static const unsigned xrx100_pins_clkout2[] = {GPIO3};
764 static const unsigned xrx100_pins_clkout3[] = {GPIO2};
765 
766 static const unsigned xrx100_pins_pci_gnt1[] = {GPIO30};
767 static const unsigned xrx100_pins_pci_gnt2[] = {GPIO23};
768 static const unsigned xrx100_pins_pci_gnt3[] = {GPIO19};
769 static const unsigned xrx100_pins_pci_gnt4[] = {GPIO38};
770 static const unsigned xrx100_pins_pci_req1[] = {GPIO29};
771 static const unsigned xrx100_pins_pci_req2[] = {GPIO31};
772 static const unsigned xrx100_pins_pci_req3[] = {GPIO3};
773 static const unsigned xrx100_pins_pci_req4[] = {GPIO37};
774 
775 static const struct ltq_pin_group xrx100_grps[] = {
776 	GRP_MUX("exin0", EXIN, xrx100_pins_exin0),
777 	GRP_MUX("exin1", EXIN, xrx100_pins_exin1),
778 	GRP_MUX("exin2", EXIN, xrx100_pins_exin2),
779 	GRP_MUX("exin3", EXIN, xrx100_pins_exin3),
780 	GRP_MUX("exin4", EXIN, xrx100_pins_exin4),
781 	GRP_MUX("exin5", EXIN, xrx100_pins_exin5),
782 	GRP_MUX("ebu a23", EBU, xrx100_pins_ebu_a23),
783 	GRP_MUX("ebu a24", EBU, xrx100_pins_ebu_a24),
784 	GRP_MUX("ebu a25", EBU, xrx100_pins_ebu_a25),
785 	GRP_MUX("ebu clk", EBU, xrx100_pins_ebu_clk),
786 	GRP_MUX("ebu cs1", EBU, xrx100_pins_ebu_cs1),
787 	GRP_MUX("ebu wait", EBU, xrx100_pins_ebu_wait),
788 	GRP_MUX("nand ale", EBU, xrx100_pins_nand_ale),
789 	GRP_MUX("nand cs1", EBU, xrx100_pins_nand_cs1),
790 	GRP_MUX("nand cle", EBU, xrx100_pins_nand_cle),
791 	GRP_MUX("nand rdy", EBU, xrx100_pins_nand_rdy),
792 	GRP_MUX("nand rd", EBU, xrx100_pins_nand_rd),
793 	GRP_MUX("spi_di", SPI, xrx100_pins_spi_di),
794 	GRP_MUX("spi_do", SPI, xrx100_pins_spi_do),
795 	GRP_MUX("spi_clk", SPI, xrx100_pins_spi_clk),
796 	GRP_MUX("spi_cs1", SPI, xrx100_pins_spi_cs1),
797 	GRP_MUX("spi_cs2", SPI, xrx100_pins_spi_cs2),
798 	GRP_MUX("spi_cs3", SPI, xrx100_pins_spi_cs3),
799 	GRP_MUX("spi_cs4", SPI, xrx100_pins_spi_cs4),
800 	GRP_MUX("spi_cs5", SPI, xrx100_pins_spi_cs5),
801 	GRP_MUX("spi_cs6", SPI, xrx100_pins_spi_cs6),
802 	GRP_MUX("asc0", ASC, xrx100_pins_asc0),
803 	GRP_MUX("asc0 cts rts", ASC, xrx100_pins_asc0_cts_rts),
804 	GRP_MUX("stp", STP, xrx100_pins_stp),
805 	GRP_MUX("nmi", NMI, xrx100_pins_nmi),
806 	GRP_MUX("gpt1", GPT, xrx100_pins_gpt1),
807 	GRP_MUX("gpt2", GPT, xrx100_pins_gpt2),
808 	GRP_MUX("gpt3", GPT, xrx100_pins_gpt3),
809 	GRP_MUX("clkout0", CGU, xrx100_pins_clkout0),
810 	GRP_MUX("clkout1", CGU, xrx100_pins_clkout1),
811 	GRP_MUX("clkout2", CGU, xrx100_pins_clkout2),
812 	GRP_MUX("clkout3", CGU, xrx100_pins_clkout3),
813 	GRP_MUX("gnt1", PCI, xrx100_pins_pci_gnt1),
814 	GRP_MUX("gnt2", PCI, xrx100_pins_pci_gnt2),
815 	GRP_MUX("gnt3", PCI, xrx100_pins_pci_gnt3),
816 	GRP_MUX("gnt4", PCI, xrx100_pins_pci_gnt4),
817 	GRP_MUX("req1", PCI, xrx100_pins_pci_req1),
818 	GRP_MUX("req2", PCI, xrx100_pins_pci_req2),
819 	GRP_MUX("req3", PCI, xrx100_pins_pci_req3),
820 	GRP_MUX("req4", PCI, xrx100_pins_pci_req4),
821 	GRP_MUX("mdio", MDIO, xrx100_pins_mdio),
822 	GRP_MUX("dfe led0", DFE, xrx100_pins_dfe_led0),
823 	GRP_MUX("dfe led1", DFE, xrx100_pins_dfe_led1),
824 };
825 
826 static const char * const xrx100_pci_grps[] = {"gnt1", "gnt2",
827 						"gnt3", "gnt4",
828 						"req1", "req2",
829 						"req3", "req4"};
830 static const char * const xrx100_spi_grps[] = {"spi_di", "spi_do",
831 						"spi_clk", "spi_cs1",
832 						"spi_cs2", "spi_cs3",
833 						"spi_cs4", "spi_cs5",
834 						"spi_cs6"};
835 static const char * const xrx100_cgu_grps[] = {"clkout0", "clkout1",
836 						"clkout2", "clkout3"};
837 static const char * const xrx100_ebu_grps[] = {"ebu a23", "ebu a24",
838 						"ebu a25", "ebu cs1",
839 						"ebu wait", "ebu clk",
840 						"nand ale", "nand cs1",
841 						"nand cle", "nand rdy",
842 						"nand rd"};
843 static const char * const xrx100_exin_grps[] = {"exin0", "exin1", "exin2",
844 						"exin3", "exin4", "exin5"};
845 static const char * const xrx100_gpt_grps[] = {"gpt1", "gpt2", "gpt3"};
846 static const char * const xrx100_asc_grps[] = {"asc0", "asc0 cts rts"};
847 static const char * const xrx100_stp_grps[] = {"stp"};
848 static const char * const xrx100_nmi_grps[] = {"nmi"};
849 static const char * const xrx100_mdio_grps[] = {"mdio"};
850 static const char * const xrx100_dfe_grps[] = {"dfe led0", "dfe led1"};
851 
852 static const struct ltq_pmx_func xrx100_funcs[] = {
853 	{"spi",		ARRAY_AND_SIZE(xrx100_spi_grps)},
854 	{"asc",		ARRAY_AND_SIZE(xrx100_asc_grps)},
855 	{"cgu",		ARRAY_AND_SIZE(xrx100_cgu_grps)},
856 	{"exin",	ARRAY_AND_SIZE(xrx100_exin_grps)},
857 	{"stp",		ARRAY_AND_SIZE(xrx100_stp_grps)},
858 	{"gpt",		ARRAY_AND_SIZE(xrx100_gpt_grps)},
859 	{"nmi",		ARRAY_AND_SIZE(xrx100_nmi_grps)},
860 	{"pci",		ARRAY_AND_SIZE(xrx100_pci_grps)},
861 	{"ebu",		ARRAY_AND_SIZE(xrx100_ebu_grps)},
862 	{"mdio",	ARRAY_AND_SIZE(xrx100_mdio_grps)},
863 	{"dfe",		ARRAY_AND_SIZE(xrx100_dfe_grps)},
864 };
865 
866 /* ---------  xrx200 related code --------- */
867 #define XRX200_MAX_PIN		50
868 
869 static const struct ltq_mfp_pin xrx200_mfp[] = {
870 	/*       pin    f0	f1	f2	f3   */
871 	MFP_XWAY(GPIO0, GPIO,	EXIN,	SDIO,	TDM),
872 	MFP_XWAY(GPIO1, GPIO,	EXIN,	CBUS,	SIN),
873 	MFP_XWAY(GPIO2, GPIO,	CGU,	EXIN,	GPHY),
874 	MFP_XWAY(GPIO3, GPIO,	CGU,	SDIO,	PCI),
875 	MFP_XWAY(GPIO4, GPIO,	STP,	DFE,	USIF),
876 	MFP_XWAY(GPIO5, GPIO,	STP,	GPHY,	DFE),
877 	MFP_XWAY(GPIO6, GPIO,	STP,	GPT,	USIF),
878 	MFP_XWAY(GPIO7, GPIO,	CGU,	CBUS,	GPHY),
879 	MFP_XWAY(GPIO8, GPIO,	CGU,	NMI,	NONE),
880 	MFP_XWAY(GPIO9, GPIO,	USIF,	SPI,	EXIN),
881 	MFP_XWAY(GPIO10, GPIO,	USIF,	SPI,	EXIN),
882 	MFP_XWAY(GPIO11, GPIO,	USIF,	CBUS,	SPI),
883 	MFP_XWAY(GPIO12, GPIO,	USIF,	CBUS,	MCD),
884 	MFP_XWAY(GPIO13, GPIO,	EBU,	SPI,	NONE),
885 	MFP_XWAY(GPIO14, GPIO,	CGU,	CBUS,	USIF),
886 	MFP_XWAY(GPIO15, GPIO,	SPI,	SDIO,	MCD),
887 	MFP_XWAY(GPIO16, GPIO,	SPI,	SDIO,	NONE),
888 	MFP_XWAY(GPIO17, GPIO,	SPI,	SDIO,	NONE),
889 	MFP_XWAY(GPIO18, GPIO,	SPI,	SDIO,	NONE),
890 	MFP_XWAY(GPIO19, GPIO,	PCI,	SDIO,	CGU),
891 	MFP_XWAY(GPIO20, GPIO,	NONE,	SDIO,	EBU),
892 	MFP_XWAY(GPIO21, GPIO,	PCI,	EBU,	GPT),
893 	MFP_XWAY(GPIO22, GPIO,	SPI,	CGU,	EBU),
894 	MFP_XWAY(GPIO23, GPIO,	EBU,	PCI,	STP),
895 	MFP_XWAY(GPIO24, GPIO,	EBU,	TDM,	PCI),
896 	MFP_XWAY(GPIO25, GPIO,	TDM,	SDIO,	USIF),
897 	MFP_XWAY(GPIO26, GPIO,	EBU,	TDM,	SDIO),
898 	MFP_XWAY(GPIO27, GPIO,	TDM,	SDIO,	USIF),
899 	MFP_XWAY(GPIO28, GPIO,	GPT,	PCI,	SDIO),
900 	MFP_XWAY(GPIO29, GPIO,	PCI,	CBUS,	EXIN),
901 	MFP_XWAY(GPIO30, GPIO,	PCI,	CBUS,	NONE),
902 	MFP_XWAY(GPIO31, GPIO,	EBU,	PCI,	NONE),
903 	MFP_XWAY(GPIO32, GPIO,	MII,	NONE,	EBU),
904 	MFP_XWAY(GPIO33, GPIO,	MII,	NONE,	EBU),
905 	MFP_XWAY(GPIO34, GPIO,	SIN,	SSI,	NONE),
906 	MFP_XWAY(GPIO35, GPIO,	SIN,	SSI,	NONE),
907 	MFP_XWAY(GPIO36, GPIO,	SIN,	SSI,	EXIN),
908 	MFP_XWAY(GPIO37, GPIO,	USIF,	NONE,	PCI),
909 	MFP_XWAY(GPIO38, GPIO,	PCI,	USIF,	NONE),
910 	MFP_XWAY(GPIO39, GPIO,	USIF,	EXIN,	NONE),
911 	MFP_XWAY(GPIO40, GPIO,	MII,	TDM,	NONE),
912 	MFP_XWAY(GPIO41, GPIO,	MII,	TDM,	NONE),
913 	MFP_XWAY(GPIO42, GPIO,	MDIO,	NONE,	NONE),
914 	MFP_XWAY(GPIO43, GPIO,	MDIO,	NONE,	NONE),
915 	MFP_XWAY(GPIO44, GPIO,	MII,	SIN,	GPHY),
916 	MFP_XWAY(GPIO45, GPIO,	MII,	GPHY,	SIN),
917 	MFP_XWAY(GPIO46, GPIO,	MII,	NONE,	EXIN),
918 	MFP_XWAY(GPIO47, GPIO,	MII,	GPHY,	SIN),
919 	MFP_XWAY(GPIO48, GPIO,	EBU,	NONE,	NONE),
920 	MFP_XWAY(GPIO49, GPIO,	EBU,	NONE,	NONE),
921 };
922 
923 static const unsigned xrx200_exin_pin_map[] = {GPIO0, GPIO1, GPIO2, GPIO39, GPIO10, GPIO9};
924 
925 static const unsigned xrx200_pins_exin0[] = {GPIO0};
926 static const unsigned xrx200_pins_exin1[] = {GPIO1};
927 static const unsigned xrx200_pins_exin2[] = {GPIO2};
928 static const unsigned xrx200_pins_exin3[] = {GPIO39};
929 static const unsigned xrx200_pins_exin4[] = {GPIO10};
930 static const unsigned xrx200_pins_exin5[] = {GPIO9};
931 
932 static const unsigned xrx200_pins_usif_uart_rx[] = {GPIO11};
933 static const unsigned xrx200_pins_usif_uart_tx[] = {GPIO12};
934 static const unsigned xrx200_pins_usif_uart_rts[] = {GPIO9};
935 static const unsigned xrx200_pins_usif_uart_cts[] = {GPIO10};
936 static const unsigned xrx200_pins_usif_uart_dtr[] = {GPIO4};
937 static const unsigned xrx200_pins_usif_uart_dsr[] = {GPIO6};
938 static const unsigned xrx200_pins_usif_uart_dcd[] = {GPIO25};
939 static const unsigned xrx200_pins_usif_uart_ri[] = {GPIO27};
940 
941 static const unsigned xrx200_pins_usif_spi_di[] = {GPIO11};
942 static const unsigned xrx200_pins_usif_spi_do[] = {GPIO12};
943 static const unsigned xrx200_pins_usif_spi_clk[] = {GPIO38};
944 static const unsigned xrx200_pins_usif_spi_cs0[] = {GPIO37};
945 static const unsigned xrx200_pins_usif_spi_cs1[] = {GPIO39};
946 static const unsigned xrx200_pins_usif_spi_cs2[] = {GPIO14};
947 
948 static const unsigned xrx200_pins_stp[] = {GPIO4, GPIO5, GPIO6};
949 static const unsigned xrx200_pins_nmi[] = {GPIO8};
950 static const unsigned xrx200_pins_mdio[] = {GPIO42, GPIO43};
951 
952 static const unsigned xrx200_pins_dfe_led0[] = {GPIO4};
953 static const unsigned xrx200_pins_dfe_led1[] = {GPIO5};
954 
955 static const unsigned xrx200_pins_gphy0_led0[] = {GPIO5};
956 static const unsigned xrx200_pins_gphy0_led1[] = {GPIO7};
957 static const unsigned xrx200_pins_gphy0_led2[] = {GPIO2};
958 static const unsigned xrx200_pins_gphy1_led0[] = {GPIO44};
959 static const unsigned xrx200_pins_gphy1_led1[] = {GPIO45};
960 static const unsigned xrx200_pins_gphy1_led2[] = {GPIO47};
961 
962 static const unsigned xrx200_pins_ebu_a24[] = {GPIO13};
963 static const unsigned xrx200_pins_ebu_clk[] = {GPIO21};
964 static const unsigned xrx200_pins_ebu_cs1[] = {GPIO23};
965 static const unsigned xrx200_pins_ebu_a23[] = {GPIO24};
966 static const unsigned xrx200_pins_ebu_wait[] = {GPIO26};
967 static const unsigned xrx200_pins_ebu_a25[] = {GPIO31};
968 
969 static const unsigned xrx200_pins_nand_ale[] = {GPIO13};
970 static const unsigned xrx200_pins_nand_cs1[] = {GPIO23};
971 static const unsigned xrx200_pins_nand_cle[] = {GPIO24};
972 static const unsigned xrx200_pins_nand_rdy[] = {GPIO48};
973 static const unsigned xrx200_pins_nand_rd[] = {GPIO49};
974 
975 static const unsigned xrx200_pins_spi_di[] = {GPIO16};
976 static const unsigned xrx200_pins_spi_do[] = {GPIO17};
977 static const unsigned xrx200_pins_spi_clk[] = {GPIO18};
978 static const unsigned xrx200_pins_spi_cs1[] = {GPIO15};
979 static const unsigned xrx200_pins_spi_cs2[] = {GPIO22};
980 static const unsigned xrx200_pins_spi_cs3[] = {GPIO13};
981 static const unsigned xrx200_pins_spi_cs4[] = {GPIO10};
982 static const unsigned xrx200_pins_spi_cs5[] = {GPIO9};
983 static const unsigned xrx200_pins_spi_cs6[] = {GPIO11};
984 
985 static const unsigned xrx200_pins_gpt1[] = {GPIO28};
986 static const unsigned xrx200_pins_gpt2[] = {GPIO21};
987 static const unsigned xrx200_pins_gpt3[] = {GPIO6};
988 
989 static const unsigned xrx200_pins_clkout0[] = {GPIO8};
990 static const unsigned xrx200_pins_clkout1[] = {GPIO7};
991 static const unsigned xrx200_pins_clkout2[] = {GPIO3};
992 static const unsigned xrx200_pins_clkout3[] = {GPIO2};
993 
994 static const unsigned xrx200_pins_pci_gnt1[] = {GPIO28};
995 static const unsigned xrx200_pins_pci_gnt2[] = {GPIO23};
996 static const unsigned xrx200_pins_pci_gnt3[] = {GPIO19};
997 static const unsigned xrx200_pins_pci_gnt4[] = {GPIO38};
998 static const unsigned xrx200_pins_pci_req1[] = {GPIO29};
999 static const unsigned xrx200_pins_pci_req2[] = {GPIO31};
1000 static const unsigned xrx200_pins_pci_req3[] = {GPIO3};
1001 static const unsigned xrx200_pins_pci_req4[] = {GPIO37};
1002 
1003 static const struct ltq_pin_group xrx200_grps[] = {
1004 	GRP_MUX("exin0", EXIN, xrx200_pins_exin0),
1005 	GRP_MUX("exin1", EXIN, xrx200_pins_exin1),
1006 	GRP_MUX("exin2", EXIN, xrx200_pins_exin2),
1007 	GRP_MUX("exin3", EXIN, xrx200_pins_exin3),
1008 	GRP_MUX("exin4", EXIN, xrx200_pins_exin4),
1009 	GRP_MUX("exin5", EXIN, xrx200_pins_exin5),
1010 	GRP_MUX("ebu a23", EBU, xrx200_pins_ebu_a23),
1011 	GRP_MUX("ebu a24", EBU, xrx200_pins_ebu_a24),
1012 	GRP_MUX("ebu a25", EBU, xrx200_pins_ebu_a25),
1013 	GRP_MUX("ebu clk", EBU, xrx200_pins_ebu_clk),
1014 	GRP_MUX("ebu cs1", EBU, xrx200_pins_ebu_cs1),
1015 	GRP_MUX("ebu wait", EBU, xrx200_pins_ebu_wait),
1016 	GRP_MUX("nand ale", EBU, xrx200_pins_nand_ale),
1017 	GRP_MUX("nand cs1", EBU, xrx200_pins_nand_cs1),
1018 	GRP_MUX("nand cle", EBU, xrx200_pins_nand_cle),
1019 	GRP_MUX("nand rdy", EBU, xrx200_pins_nand_rdy),
1020 	GRP_MUX("nand rd", EBU, xrx200_pins_nand_rd),
1021 	GRP_MUX("spi_di", SPI, xrx200_pins_spi_di),
1022 	GRP_MUX("spi_do", SPI, xrx200_pins_spi_do),
1023 	GRP_MUX("spi_clk", SPI, xrx200_pins_spi_clk),
1024 	GRP_MUX("spi_cs1", SPI, xrx200_pins_spi_cs1),
1025 	GRP_MUX("spi_cs2", SPI, xrx200_pins_spi_cs2),
1026 	GRP_MUX("spi_cs3", SPI, xrx200_pins_spi_cs3),
1027 	GRP_MUX("spi_cs4", SPI, xrx200_pins_spi_cs4),
1028 	GRP_MUX("spi_cs5", SPI, xrx200_pins_spi_cs5),
1029 	GRP_MUX("spi_cs6", SPI, xrx200_pins_spi_cs6),
1030 	GRP_MUX("usif uart_rx", USIF, xrx200_pins_usif_uart_rx),
1031 	GRP_MUX("usif uart_tx", USIF, xrx200_pins_usif_uart_tx),
1032 	GRP_MUX("usif uart_rts", USIF, xrx200_pins_usif_uart_rts),
1033 	GRP_MUX("usif uart_cts", USIF, xrx200_pins_usif_uart_cts),
1034 	GRP_MUX("usif uart_dtr", USIF, xrx200_pins_usif_uart_dtr),
1035 	GRP_MUX("usif uart_dsr", USIF, xrx200_pins_usif_uart_dsr),
1036 	GRP_MUX("usif uart_dcd", USIF, xrx200_pins_usif_uart_dcd),
1037 	GRP_MUX("usif uart_ri", USIF, xrx200_pins_usif_uart_ri),
1038 	GRP_MUX("usif spi_di", USIF, xrx200_pins_usif_spi_di),
1039 	GRP_MUX("usif spi_do", USIF, xrx200_pins_usif_spi_do),
1040 	GRP_MUX("usif spi_clk", USIF, xrx200_pins_usif_spi_clk),
1041 	GRP_MUX("usif spi_cs0", USIF, xrx200_pins_usif_spi_cs0),
1042 	GRP_MUX("usif spi_cs1", USIF, xrx200_pins_usif_spi_cs1),
1043 	GRP_MUX("usif spi_cs2", USIF, xrx200_pins_usif_spi_cs2),
1044 	GRP_MUX("stp", STP, xrx200_pins_stp),
1045 	GRP_MUX("nmi", NMI, xrx200_pins_nmi),
1046 	GRP_MUX("gpt1", GPT, xrx200_pins_gpt1),
1047 	GRP_MUX("gpt2", GPT, xrx200_pins_gpt2),
1048 	GRP_MUX("gpt3", GPT, xrx200_pins_gpt3),
1049 	GRP_MUX("clkout0", CGU, xrx200_pins_clkout0),
1050 	GRP_MUX("clkout1", CGU, xrx200_pins_clkout1),
1051 	GRP_MUX("clkout2", CGU, xrx200_pins_clkout2),
1052 	GRP_MUX("clkout3", CGU, xrx200_pins_clkout3),
1053 	GRP_MUX("gnt1", PCI, xrx200_pins_pci_gnt1),
1054 	GRP_MUX("gnt2", PCI, xrx200_pins_pci_gnt2),
1055 	GRP_MUX("gnt3", PCI, xrx200_pins_pci_gnt3),
1056 	GRP_MUX("gnt4", PCI, xrx200_pins_pci_gnt4),
1057 	GRP_MUX("req1", PCI, xrx200_pins_pci_req1),
1058 	GRP_MUX("req2", PCI, xrx200_pins_pci_req2),
1059 	GRP_MUX("req3", PCI, xrx200_pins_pci_req3),
1060 	GRP_MUX("req4", PCI, xrx200_pins_pci_req4),
1061 	GRP_MUX("mdio", MDIO, xrx200_pins_mdio),
1062 	GRP_MUX("dfe led0", DFE, xrx200_pins_dfe_led0),
1063 	GRP_MUX("dfe led1", DFE, xrx200_pins_dfe_led1),
1064 	GRP_MUX("gphy0 led0", GPHY, xrx200_pins_gphy0_led0),
1065 	GRP_MUX("gphy0 led1", GPHY, xrx200_pins_gphy0_led1),
1066 	GRP_MUX("gphy0 led2", GPHY, xrx200_pins_gphy0_led2),
1067 	GRP_MUX("gphy1 led0", GPHY, xrx200_pins_gphy1_led0),
1068 	GRP_MUX("gphy1 led1", GPHY, xrx200_pins_gphy1_led1),
1069 	GRP_MUX("gphy1 led2", GPHY, xrx200_pins_gphy1_led2),
1070 };
1071 
1072 static const char * const xrx200_pci_grps[] = {"gnt1", "gnt2",
1073 						"gnt3", "gnt4",
1074 						"req1", "req2",
1075 						"req3", "req4"};
1076 static const char * const xrx200_spi_grps[] = {"spi_di", "spi_do",
1077 						"spi_clk", "spi_cs1",
1078 						"spi_cs2", "spi_cs3",
1079 						"spi_cs4", "spi_cs5",
1080 						"spi_cs6"};
1081 static const char * const xrx200_cgu_grps[] = {"clkout0", "clkout1",
1082 						"clkout2", "clkout3"};
1083 static const char * const xrx200_ebu_grps[] = {"ebu a23", "ebu a24",
1084 						"ebu a25", "ebu cs1",
1085 						"ebu wait", "ebu clk",
1086 						"nand ale", "nand cs1",
1087 						"nand cle", "nand rdy",
1088 						"nand rd"};
1089 static const char * const xrx200_exin_grps[] = {"exin0", "exin1", "exin2",
1090 						"exin3", "exin4", "exin5"};
1091 static const char * const xrx200_gpt_grps[] = {"gpt1", "gpt2", "gpt3"};
1092 static const char * const xrx200_usif_grps[] = {"usif uart_rx", "usif uart_tx",
1093 						"usif uart_rts", "usif uart_cts",
1094 						"usif uart_dtr", "usif uart_dsr",
1095 						"usif uart_dcd", "usif uart_ri",
1096 						"usif spi_di", "usif spi_do",
1097 						"usif spi_clk", "usif spi_cs0",
1098 						"usif spi_cs1", "usif spi_cs2"};
1099 static const char * const xrx200_stp_grps[] = {"stp"};
1100 static const char * const xrx200_nmi_grps[] = {"nmi"};
1101 static const char * const xrx200_mdio_grps[] = {"mdio"};
1102 static const char * const xrx200_dfe_grps[] = {"dfe led0", "dfe led1"};
1103 static const char * const xrx200_gphy_grps[] = {"gphy0 led0", "gphy0 led1",
1104 						"gphy0 led2", "gphy1 led0",
1105 						"gphy1 led1", "gphy1 led2"};
1106 
1107 static const struct ltq_pmx_func xrx200_funcs[] = {
1108 	{"spi",		ARRAY_AND_SIZE(xrx200_spi_grps)},
1109 	{"usif",	ARRAY_AND_SIZE(xrx200_usif_grps)},
1110 	{"cgu",		ARRAY_AND_SIZE(xrx200_cgu_grps)},
1111 	{"exin",	ARRAY_AND_SIZE(xrx200_exin_grps)},
1112 	{"stp",		ARRAY_AND_SIZE(xrx200_stp_grps)},
1113 	{"gpt",		ARRAY_AND_SIZE(xrx200_gpt_grps)},
1114 	{"nmi",		ARRAY_AND_SIZE(xrx200_nmi_grps)},
1115 	{"pci",		ARRAY_AND_SIZE(xrx200_pci_grps)},
1116 	{"ebu",		ARRAY_AND_SIZE(xrx200_ebu_grps)},
1117 	{"mdio",	ARRAY_AND_SIZE(xrx200_mdio_grps)},
1118 	{"dfe",		ARRAY_AND_SIZE(xrx200_dfe_grps)},
1119 	{"gphy",	ARRAY_AND_SIZE(xrx200_gphy_grps)},
1120 };
1121 
1122 /* ---------  xrx300 related code --------- */
1123 #define XRX300_MAX_PIN		64
1124 
1125 static const struct ltq_mfp_pin xrx300_mfp[] = {
1126 	/*       pin    f0	f1	f2	f3   */
1127 	MFP_XWAY(GPIO0, GPIO,	EXIN,	EPHY,	NONE),
1128 	MFP_XWAY(GPIO1, GPIO,	NONE,	EXIN,	NONE),
1129 	MFP_XWAY(GPIO2, NONE,	NONE,	NONE,	NONE),
1130 	MFP_XWAY(GPIO3, GPIO,	CGU,	NONE,	NONE),
1131 	MFP_XWAY(GPIO4, GPIO,	STP,	DFE,	NONE),
1132 	MFP_XWAY(GPIO5, GPIO,	STP,	EPHY,	DFE),
1133 	MFP_XWAY(GPIO6, GPIO,	STP,	NONE,	NONE),
1134 	MFP_XWAY(GPIO7, NONE,	NONE,	NONE,	NONE),
1135 	MFP_XWAY(GPIO8, GPIO,	CGU,	GPHY,	EPHY),
1136 	MFP_XWAY(GPIO9, GPIO,	WIFI,	NONE,	EXIN),
1137 	MFP_XWAY(GPIO10, GPIO,	USIF,	SPI,	EXIN),
1138 	MFP_XWAY(GPIO11, GPIO,	USIF,	WIFI,	SPI),
1139 	MFP_XWAY(GPIO12, NONE,	NONE,	NONE,	NONE),
1140 	MFP_XWAY(GPIO13, GPIO,	EBU,	NONE,	NONE),
1141 	MFP_XWAY(GPIO14, GPIO,	CGU,	USIF,	EPHY),
1142 	MFP_XWAY(GPIO15, GPIO,	SPI,	NONE,	MCD),
1143 	MFP_XWAY(GPIO16, GPIO,	SPI,	EXIN,	NONE),
1144 	MFP_XWAY(GPIO17, GPIO,	SPI,	NONE,	NONE),
1145 	MFP_XWAY(GPIO18, GPIO,	SPI,	NONE,	NONE),
1146 	MFP_XWAY(GPIO19, GPIO,	USIF,	NONE,	EPHY),
1147 	MFP_XWAY(GPIO20, NONE,	NONE,	NONE,	NONE),
1148 	MFP_XWAY(GPIO21, NONE,	NONE,	NONE,	NONE),
1149 	MFP_XWAY(GPIO22, NONE,	NONE,	NONE,	NONE),
1150 	MFP_XWAY(GPIO23, GPIO,	EBU,	NONE,	NONE),
1151 	MFP_XWAY(GPIO24, GPIO,	EBU,	NONE,	NONE),
1152 	MFP_XWAY(GPIO25, GPIO,	TDM,	NONE,	NONE),
1153 	MFP_XWAY(GPIO26, GPIO,	TDM,	NONE,	NONE),
1154 	MFP_XWAY(GPIO27, GPIO,	TDM,	NONE,	NONE),
1155 	MFP_XWAY(GPIO28, NONE,	NONE,	NONE,	NONE),
1156 	MFP_XWAY(GPIO29, NONE,	NONE,	NONE,	NONE),
1157 	MFP_XWAY(GPIO30, NONE,	NONE,	NONE,	NONE),
1158 	MFP_XWAY(GPIO31, NONE,	NONE,	NONE,	NONE),
1159 	MFP_XWAY(GPIO32, NONE,	NONE,	NONE,	NONE),
1160 	MFP_XWAY(GPIO33, NONE,	NONE,	NONE,	NONE),
1161 	MFP_XWAY(GPIO34, GPIO,	NONE,	SSI,	NONE),
1162 	MFP_XWAY(GPIO35, GPIO,	NONE,	SSI,	NONE),
1163 	MFP_XWAY(GPIO36, GPIO,	NONE,	SSI,	NONE),
1164 	MFP_XWAY(GPIO37, NONE,	NONE,	NONE,	NONE),
1165 	MFP_XWAY(GPIO38, NONE,	NONE,	NONE,	NONE),
1166 	MFP_XWAY(GPIO39, NONE,	NONE,	NONE,	NONE),
1167 	MFP_XWAY(GPIO40, NONE,	NONE,	NONE,	NONE),
1168 	MFP_XWAY(GPIO41, NONE,	NONE,	NONE,	NONE),
1169 	MFP_XWAY(GPIO42, GPIO,	MDIO,	NONE,	NONE),
1170 	MFP_XWAY(GPIO43, GPIO,	MDIO,	NONE,	NONE),
1171 	MFP_XWAY(GPIO44, NONE,	NONE,	NONE,	NONE),
1172 	MFP_XWAY(GPIO45, NONE,	NONE,	NONE,	NONE),
1173 	MFP_XWAY(GPIO46, NONE,	NONE,	NONE,	NONE),
1174 	MFP_XWAY(GPIO47, NONE,	NONE,	NONE,	NONE),
1175 	MFP_XWAY(GPIO48, GPIO,	EBU,	NONE,	NONE),
1176 	MFP_XWAY(GPIO49, GPIO,	EBU,	NONE,	NONE),
1177 	MFP_XWAY(GPIO50, GPIO,	EBU,	NONE,	NONE),
1178 	MFP_XWAY(GPIO51, GPIO,	EBU,	NONE,	NONE),
1179 	MFP_XWAY(GPIO52, GPIO,	EBU,	NONE,	NONE),
1180 	MFP_XWAY(GPIO53, GPIO,	EBU,	NONE,	NONE),
1181 	MFP_XWAY(GPIO54, GPIO,	EBU,	NONE,	NONE),
1182 	MFP_XWAY(GPIO55, GPIO,	EBU,	NONE,	NONE),
1183 	MFP_XWAY(GPIO56, GPIO,	EBU,	NONE,	NONE),
1184 	MFP_XWAY(GPIO57, GPIO,	EBU,	NONE,	NONE),
1185 	MFP_XWAY(GPIO58, GPIO,	EBU,	TDM,	NONE),
1186 	MFP_XWAY(GPIO59, GPIO,	EBU,	NONE,	NONE),
1187 	MFP_XWAY(GPIO60, GPIO,	EBU,	NONE,	NONE),
1188 	MFP_XWAY(GPIO61, GPIO,	EBU,	NONE,	NONE),
1189 	MFP_XWAY(GPIO62, NONE,	NONE,	NONE,	NONE),
1190 	MFP_XWAY(GPIO63, NONE,	NONE,	NONE,	NONE),
1191 };
1192 
1193 static const unsigned xrx300_exin_pin_map[] = {GPIO0, GPIO1, GPIO16, GPIO10, GPIO9};
1194 
1195 static const unsigned xrx300_pins_exin0[] = {GPIO0};
1196 static const unsigned xrx300_pins_exin1[] = {GPIO1};
1197 static const unsigned xrx300_pins_exin2[] = {GPIO16};
1198 /* EXIN3 is not available on xrX300 */
1199 static const unsigned xrx300_pins_exin4[] = {GPIO10};
1200 static const unsigned xrx300_pins_exin5[] = {GPIO9};
1201 
1202 static const unsigned xrx300_pins_usif_uart_rx[] = {GPIO11};
1203 static const unsigned xrx300_pins_usif_uart_tx[] = {GPIO10};
1204 
1205 static const unsigned xrx300_pins_usif_spi_di[] = {GPIO11};
1206 static const unsigned xrx300_pins_usif_spi_do[] = {GPIO10};
1207 static const unsigned xrx300_pins_usif_spi_clk[] = {GPIO19};
1208 static const unsigned xrx300_pins_usif_spi_cs0[] = {GPIO14};
1209 
1210 static const unsigned xrx300_pins_stp[] = {GPIO4, GPIO5, GPIO6};
1211 static const unsigned xrx300_pins_mdio[] = {GPIO42, GPIO43};
1212 
1213 static const unsigned xrx300_pins_dfe_led0[] = {GPIO4};
1214 static const unsigned xrx300_pins_dfe_led1[] = {GPIO5};
1215 
1216 static const unsigned xrx300_pins_ephy0_led0[] = {GPIO5};
1217 static const unsigned xrx300_pins_ephy0_led1[] = {GPIO8};
1218 static const unsigned xrx300_pins_ephy1_led0[] = {GPIO14};
1219 static const unsigned xrx300_pins_ephy1_led1[] = {GPIO19};
1220 
1221 static const unsigned xrx300_pins_nand_ale[] = {GPIO13};
1222 static const unsigned xrx300_pins_nand_cs1[] = {GPIO23};
1223 static const unsigned xrx300_pins_nand_cle[] = {GPIO24};
1224 static const unsigned xrx300_pins_nand_rdy[] = {GPIO48};
1225 static const unsigned xrx300_pins_nand_rd[] = {GPIO49};
1226 static const unsigned xrx300_pins_nand_d1[] = {GPIO50};
1227 static const unsigned xrx300_pins_nand_d0[] = {GPIO51};
1228 static const unsigned xrx300_pins_nand_d2[] = {GPIO52};
1229 static const unsigned xrx300_pins_nand_d7[] = {GPIO53};
1230 static const unsigned xrx300_pins_nand_d6[] = {GPIO54};
1231 static const unsigned xrx300_pins_nand_d5[] = {GPIO55};
1232 static const unsigned xrx300_pins_nand_d4[] = {GPIO56};
1233 static const unsigned xrx300_pins_nand_d3[] = {GPIO57};
1234 static const unsigned xrx300_pins_nand_cs0[] = {GPIO58};
1235 static const unsigned xrx300_pins_nand_wr[] = {GPIO59};
1236 static const unsigned xrx300_pins_nand_wp[] = {GPIO60};
1237 static const unsigned xrx300_pins_nand_se[] = {GPIO61};
1238 
1239 static const unsigned xrx300_pins_spi_di[] = {GPIO16};
1240 static const unsigned xrx300_pins_spi_do[] = {GPIO17};
1241 static const unsigned xrx300_pins_spi_clk[] = {GPIO18};
1242 static const unsigned xrx300_pins_spi_cs1[] = {GPIO15};
1243 /* SPI_CS2 is not available on xrX300 */
1244 /* SPI_CS3 is not available on xrX300 */
1245 static const unsigned xrx300_pins_spi_cs4[] = {GPIO10};
1246 /* SPI_CS5 is not available on xrX300 */
1247 static const unsigned xrx300_pins_spi_cs6[] = {GPIO11};
1248 
1249 /* CLKOUT0 is not available on xrX300 */
1250 /* CLKOUT1 is not available on xrX300 */
1251 static const unsigned xrx300_pins_clkout2[] = {GPIO3};
1252 
1253 static const struct ltq_pin_group xrx300_grps[] = {
1254 	GRP_MUX("exin0", EXIN, xrx300_pins_exin0),
1255 	GRP_MUX("exin1", EXIN, xrx300_pins_exin1),
1256 	GRP_MUX("exin2", EXIN, xrx300_pins_exin2),
1257 	GRP_MUX("exin4", EXIN, xrx300_pins_exin4),
1258 	GRP_MUX("exin5", EXIN, xrx300_pins_exin5),
1259 	GRP_MUX("nand ale", EBU, xrx300_pins_nand_ale),
1260 	GRP_MUX("nand cs1", EBU, xrx300_pins_nand_cs1),
1261 	GRP_MUX("nand cle", EBU, xrx300_pins_nand_cle),
1262 	GRP_MUX("nand rdy", EBU, xrx300_pins_nand_rdy),
1263 	GRP_MUX("nand rd", EBU, xrx300_pins_nand_rd),
1264 	GRP_MUX("nand d1", EBU, xrx300_pins_nand_d1),
1265 	GRP_MUX("nand d0", EBU, xrx300_pins_nand_d0),
1266 	GRP_MUX("nand d2", EBU, xrx300_pins_nand_d2),
1267 	GRP_MUX("nand d7", EBU, xrx300_pins_nand_d7),
1268 	GRP_MUX("nand d6", EBU, xrx300_pins_nand_d6),
1269 	GRP_MUX("nand d5", EBU, xrx300_pins_nand_d5),
1270 	GRP_MUX("nand d4", EBU, xrx300_pins_nand_d4),
1271 	GRP_MUX("nand d3", EBU, xrx300_pins_nand_d3),
1272 	GRP_MUX("nand cs0", EBU, xrx300_pins_nand_cs0),
1273 	GRP_MUX("nand wr", EBU, xrx300_pins_nand_wr),
1274 	GRP_MUX("nand wp", EBU, xrx300_pins_nand_wp),
1275 	GRP_MUX("nand se", EBU, xrx300_pins_nand_se),
1276 	GRP_MUX("spi_di", SPI, xrx300_pins_spi_di),
1277 	GRP_MUX("spi_do", SPI, xrx300_pins_spi_do),
1278 	GRP_MUX("spi_clk", SPI, xrx300_pins_spi_clk),
1279 	GRP_MUX("spi_cs1", SPI, xrx300_pins_spi_cs1),
1280 	GRP_MUX("spi_cs4", SPI, xrx300_pins_spi_cs4),
1281 	GRP_MUX("spi_cs6", SPI, xrx300_pins_spi_cs6),
1282 	GRP_MUX("usif uart_rx", USIF, xrx300_pins_usif_uart_rx),
1283 	GRP_MUX("usif uart_tx", USIF, xrx300_pins_usif_uart_tx),
1284 	GRP_MUX("usif spi_di", USIF, xrx300_pins_usif_spi_di),
1285 	GRP_MUX("usif spi_do", USIF, xrx300_pins_usif_spi_do),
1286 	GRP_MUX("usif spi_clk", USIF, xrx300_pins_usif_spi_clk),
1287 	GRP_MUX("usif spi_cs0", USIF, xrx300_pins_usif_spi_cs0),
1288 	GRP_MUX("stp", STP, xrx300_pins_stp),
1289 	GRP_MUX("clkout2", CGU, xrx300_pins_clkout2),
1290 	GRP_MUX("mdio", MDIO, xrx300_pins_mdio),
1291 	GRP_MUX("dfe led0", DFE, xrx300_pins_dfe_led0),
1292 	GRP_MUX("dfe led1", DFE, xrx300_pins_dfe_led1),
1293 	GRP_MUX("ephy0 led0", GPHY, xrx300_pins_ephy0_led0),
1294 	GRP_MUX("ephy0 led1", GPHY, xrx300_pins_ephy0_led1),
1295 	GRP_MUX("ephy1 led0", GPHY, xrx300_pins_ephy1_led0),
1296 	GRP_MUX("ephy1 led1", GPHY, xrx300_pins_ephy1_led1),
1297 };
1298 
1299 static const char * const xrx300_spi_grps[] = {"spi_di", "spi_do",
1300 						"spi_clk", "spi_cs1",
1301 						"spi_cs4", "spi_cs6"};
1302 static const char * const xrx300_cgu_grps[] = {"clkout2"};
1303 static const char * const xrx300_ebu_grps[] = {"nand ale", "nand cs1",
1304 						"nand cle", "nand rdy",
1305 						"nand rd", "nand d1",
1306 						"nand d0", "nand d2",
1307 						"nand d7", "nand d6",
1308 						"nand d5", "nand d4",
1309 						"nand d3", "nand cs0",
1310 						"nand wr", "nand wp",
1311 						"nand se"};
1312 static const char * const xrx300_exin_grps[] = {"exin0", "exin1", "exin2",
1313 						"exin4", "exin5"};
1314 static const char * const xrx300_usif_grps[] = {"usif uart_rx", "usif uart_tx",
1315 						"usif spi_di", "usif spi_do",
1316 						"usif spi_clk", "usif spi_cs0"};
1317 static const char * const xrx300_stp_grps[] = {"stp"};
1318 static const char * const xrx300_mdio_grps[] = {"mdio"};
1319 static const char * const xrx300_dfe_grps[] = {"dfe led0", "dfe led1"};
1320 static const char * const xrx300_gphy_grps[] = {"ephy0 led0", "ephy0 led1",
1321 						"ephy1 led0", "ephy1 led1"};
1322 
1323 static const struct ltq_pmx_func xrx300_funcs[] = {
1324 	{"spi",		ARRAY_AND_SIZE(xrx300_spi_grps)},
1325 	{"usif",	ARRAY_AND_SIZE(xrx300_usif_grps)},
1326 	{"cgu",		ARRAY_AND_SIZE(xrx300_cgu_grps)},
1327 	{"exin",	ARRAY_AND_SIZE(xrx300_exin_grps)},
1328 	{"stp",		ARRAY_AND_SIZE(xrx300_stp_grps)},
1329 	{"ebu",		ARRAY_AND_SIZE(xrx300_ebu_grps)},
1330 	{"mdio",	ARRAY_AND_SIZE(xrx300_mdio_grps)},
1331 	{"dfe",		ARRAY_AND_SIZE(xrx300_dfe_grps)},
1332 	{"ephy",	ARRAY_AND_SIZE(xrx300_gphy_grps)},
1333 };
1334 
1335 /* ---------  pinconf related code --------- */
1336 static int xway_pinconf_get(struct pinctrl_dev *pctldev,
1337 				unsigned pin,
1338 				unsigned long *config)
1339 {
1340 	struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctldev);
1341 	enum ltq_pinconf_param param = LTQ_PINCONF_UNPACK_PARAM(*config);
1342 	int port = PORT(pin);
1343 	u32 reg;
1344 
1345 	switch (param) {
1346 	case LTQ_PINCONF_PARAM_OPEN_DRAIN:
1347 		if (port == PORT3)
1348 			reg = GPIO3_OD;
1349 		else
1350 			reg = GPIO_OD(pin);
1351 		*config = LTQ_PINCONF_PACK(param,
1352 			!gpio_getbit(info->membase[0], reg, PORT_PIN(pin)));
1353 		break;
1354 
1355 	case LTQ_PINCONF_PARAM_PULL:
1356 		if (port == PORT3)
1357 			reg = GPIO3_PUDEN;
1358 		else
1359 			reg = GPIO_PUDEN(pin);
1360 		if (!gpio_getbit(info->membase[0], reg, PORT_PIN(pin))) {
1361 			*config = LTQ_PINCONF_PACK(param, 0);
1362 			break;
1363 		}
1364 
1365 		if (port == PORT3)
1366 			reg = GPIO3_PUDSEL;
1367 		else
1368 			reg = GPIO_PUDSEL(pin);
1369 		if (!gpio_getbit(info->membase[0], reg, PORT_PIN(pin)))
1370 			*config = LTQ_PINCONF_PACK(param, 2);
1371 		else
1372 			*config = LTQ_PINCONF_PACK(param, 1);
1373 		break;
1374 
1375 	case LTQ_PINCONF_PARAM_OUTPUT:
1376 		reg = GPIO_DIR(pin);
1377 		*config = LTQ_PINCONF_PACK(param,
1378 			gpio_getbit(info->membase[0], reg, PORT_PIN(pin)));
1379 		break;
1380 	default:
1381 		dev_err(pctldev->dev, "Invalid config param %04x\n", param);
1382 		return -ENOTSUPP;
1383 	}
1384 	return 0;
1385 }
1386 
1387 static int xway_pinconf_set(struct pinctrl_dev *pctldev,
1388 				unsigned pin,
1389 				unsigned long *configs,
1390 				unsigned num_configs)
1391 {
1392 	struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctldev);
1393 	enum ltq_pinconf_param param;
1394 	int arg;
1395 	int port = PORT(pin);
1396 	u32 reg;
1397 	int i;
1398 
1399 	for (i = 0; i < num_configs; i++) {
1400 		param = LTQ_PINCONF_UNPACK_PARAM(configs[i]);
1401 		arg = LTQ_PINCONF_UNPACK_ARG(configs[i]);
1402 
1403 		switch (param) {
1404 		case LTQ_PINCONF_PARAM_OPEN_DRAIN:
1405 			if (port == PORT3)
1406 				reg = GPIO3_OD;
1407 			else
1408 				reg = GPIO_OD(pin);
1409 			if (arg == 0)
1410 				gpio_setbit(info->membase[0],
1411 					reg,
1412 					PORT_PIN(pin));
1413 			else
1414 				gpio_clearbit(info->membase[0],
1415 					reg,
1416 					PORT_PIN(pin));
1417 			break;
1418 
1419 		case LTQ_PINCONF_PARAM_PULL:
1420 			if (port == PORT3)
1421 				reg = GPIO3_PUDEN;
1422 			else
1423 				reg = GPIO_PUDEN(pin);
1424 			if (arg == 0) {
1425 				gpio_clearbit(info->membase[0],
1426 					reg,
1427 					PORT_PIN(pin));
1428 				break;
1429 			}
1430 			gpio_setbit(info->membase[0], reg, PORT_PIN(pin));
1431 
1432 			if (port == PORT3)
1433 				reg = GPIO3_PUDSEL;
1434 			else
1435 				reg = GPIO_PUDSEL(pin);
1436 			if (arg == 1)
1437 				gpio_clearbit(info->membase[0],
1438 					reg,
1439 					PORT_PIN(pin));
1440 			else if (arg == 2)
1441 				gpio_setbit(info->membase[0],
1442 					reg,
1443 					PORT_PIN(pin));
1444 			else
1445 				dev_err(pctldev->dev,
1446 					"Invalid pull value %d\n", arg);
1447 			break;
1448 
1449 		case LTQ_PINCONF_PARAM_OUTPUT:
1450 			reg = GPIO_DIR(pin);
1451 			if (arg == 0)
1452 				gpio_clearbit(info->membase[0],
1453 					reg,
1454 					PORT_PIN(pin));
1455 			else
1456 				gpio_setbit(info->membase[0],
1457 					reg,
1458 					PORT_PIN(pin));
1459 			break;
1460 
1461 		default:
1462 			dev_err(pctldev->dev,
1463 				"Invalid config param %04x\n", param);
1464 			return -ENOTSUPP;
1465 		}
1466 	} /* for each config */
1467 
1468 	return 0;
1469 }
1470 
1471 int xway_pinconf_group_set(struct pinctrl_dev *pctldev,
1472 			unsigned selector,
1473 			unsigned long *configs,
1474 			unsigned num_configs)
1475 {
1476 	struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctldev);
1477 	int i, ret = 0;
1478 
1479 	for (i = 0; i < info->grps[selector].npins && !ret; i++)
1480 		ret = xway_pinconf_set(pctldev,
1481 				info->grps[selector].pins[i],
1482 				configs,
1483 				num_configs);
1484 
1485 	return ret;
1486 }
1487 
1488 static const struct pinconf_ops xway_pinconf_ops = {
1489 	.pin_config_get	= xway_pinconf_get,
1490 	.pin_config_set	= xway_pinconf_set,
1491 	.pin_config_group_set = xway_pinconf_group_set,
1492 };
1493 
1494 static struct pinctrl_desc xway_pctrl_desc = {
1495 	.owner		= THIS_MODULE,
1496 	.confops	= &xway_pinconf_ops,
1497 };
1498 
1499 static inline int xway_mux_apply(struct pinctrl_dev *pctrldev,
1500 				int pin, int mux)
1501 {
1502 	struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
1503 	int port = PORT(pin);
1504 	u32 alt1_reg = GPIO_ALT1(pin);
1505 
1506 	if (port == PORT3)
1507 		alt1_reg = GPIO3_ALT1;
1508 
1509 	if (mux & MUX_ALT0)
1510 		gpio_setbit(info->membase[0], GPIO_ALT0(pin), PORT_PIN(pin));
1511 	else
1512 		gpio_clearbit(info->membase[0], GPIO_ALT0(pin), PORT_PIN(pin));
1513 
1514 	if (mux & MUX_ALT1)
1515 		gpio_setbit(info->membase[0], alt1_reg, PORT_PIN(pin));
1516 	else
1517 		gpio_clearbit(info->membase[0], alt1_reg, PORT_PIN(pin));
1518 
1519 	return 0;
1520 }
1521 
1522 static const struct ltq_cfg_param xway_cfg_params[] = {
1523 	{"lantiq,pull",		LTQ_PINCONF_PARAM_PULL},
1524 	{"lantiq,open-drain",	LTQ_PINCONF_PARAM_OPEN_DRAIN},
1525 	{"lantiq,output",	LTQ_PINCONF_PARAM_OUTPUT},
1526 };
1527 
1528 static struct ltq_pinmux_info xway_info = {
1529 	.desc		= &xway_pctrl_desc,
1530 	.apply_mux	= xway_mux_apply,
1531 	.params		= xway_cfg_params,
1532 	.num_params	= ARRAY_SIZE(xway_cfg_params),
1533 };
1534 
1535 /* ---------  gpio_chip related code --------- */
1536 static void xway_gpio_set(struct gpio_chip *chip, unsigned int pin, int val)
1537 {
1538 	struct ltq_pinmux_info *info = dev_get_drvdata(chip->parent);
1539 
1540 	if (val)
1541 		gpio_setbit(info->membase[0], GPIO_OUT(pin), PORT_PIN(pin));
1542 	else
1543 		gpio_clearbit(info->membase[0], GPIO_OUT(pin), PORT_PIN(pin));
1544 }
1545 
1546 static int xway_gpio_get(struct gpio_chip *chip, unsigned int pin)
1547 {
1548 	struct ltq_pinmux_info *info = dev_get_drvdata(chip->parent);
1549 
1550 	return !!gpio_getbit(info->membase[0], GPIO_IN(pin), PORT_PIN(pin));
1551 }
1552 
1553 static int xway_gpio_dir_in(struct gpio_chip *chip, unsigned int pin)
1554 {
1555 	struct ltq_pinmux_info *info = dev_get_drvdata(chip->parent);
1556 
1557 	gpio_clearbit(info->membase[0], GPIO_DIR(pin), PORT_PIN(pin));
1558 
1559 	return 0;
1560 }
1561 
1562 static int xway_gpio_dir_out(struct gpio_chip *chip, unsigned int pin, int val)
1563 {
1564 	struct ltq_pinmux_info *info = dev_get_drvdata(chip->parent);
1565 
1566 	if (PORT(pin) == PORT3)
1567 		gpio_setbit(info->membase[0], GPIO3_OD, PORT_PIN(pin));
1568 	else
1569 		gpio_setbit(info->membase[0], GPIO_OD(pin), PORT_PIN(pin));
1570 	gpio_setbit(info->membase[0], GPIO_DIR(pin), PORT_PIN(pin));
1571 	xway_gpio_set(chip, pin, val);
1572 
1573 	return 0;
1574 }
1575 
1576 /*
1577  * gpiolib gpiod_to_irq callback function.
1578  * Returns the mapped IRQ (external interrupt) number for a given GPIO pin.
1579  */
1580 static int xway_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
1581 {
1582 	struct ltq_pinmux_info *info = dev_get_drvdata(chip->parent);
1583 	int i;
1584 
1585 	for (i = 0; i < info->num_exin; i++)
1586 		if (info->exin[i] == offset)
1587 			return ltq_eiu_get_irq(i);
1588 
1589 	return -1;
1590 }
1591 
1592 static struct gpio_chip xway_chip = {
1593 	.label = "gpio-xway",
1594 	.direction_input = xway_gpio_dir_in,
1595 	.direction_output = xway_gpio_dir_out,
1596 	.get = xway_gpio_get,
1597 	.set = xway_gpio_set,
1598 	.request = gpiochip_generic_request,
1599 	.free = gpiochip_generic_free,
1600 	.to_irq = xway_gpio_to_irq,
1601 	.base = -1,
1602 };
1603 
1604 
1605 /* --------- register the pinctrl layer --------- */
1606 struct pinctrl_xway_soc {
1607 	int pin_count;
1608 	const struct ltq_mfp_pin *mfp;
1609 	const struct ltq_pin_group *grps;
1610 	unsigned int num_grps;
1611 	const struct ltq_pmx_func *funcs;
1612 	unsigned int num_funcs;
1613 	const unsigned *exin;
1614 	unsigned int num_exin;
1615 };
1616 
1617 /* xway xr9 series (DEPRECATED: Use XWAY xRX100/xRX200 Family) */
1618 static struct pinctrl_xway_soc xr9_pinctrl = {
1619 	.pin_count = XR9_MAX_PIN,
1620 	.mfp = xway_mfp,
1621 	.grps = xway_grps,
1622 	.num_grps = ARRAY_SIZE(xway_grps),
1623 	.funcs = xrx_funcs,
1624 	.num_funcs = ARRAY_SIZE(xrx_funcs),
1625 	.exin = xway_exin_pin_map,
1626 	.num_exin = 6
1627 };
1628 
1629 /* XWAY AMAZON Family */
1630 static struct pinctrl_xway_soc ase_pinctrl = {
1631 	.pin_count = ASE_MAX_PIN,
1632 	.mfp = ase_mfp,
1633 	.grps = ase_grps,
1634 	.num_grps = ARRAY_SIZE(ase_grps),
1635 	.funcs = ase_funcs,
1636 	.num_funcs = ARRAY_SIZE(ase_funcs),
1637 	.exin = ase_exin_pin_map,
1638 	.num_exin = 3
1639 };
1640 
1641 /* XWAY DANUBE Family */
1642 static struct pinctrl_xway_soc danube_pinctrl = {
1643 	.pin_count = DANUBE_MAX_PIN,
1644 	.mfp = danube_mfp,
1645 	.grps = danube_grps,
1646 	.num_grps = ARRAY_SIZE(danube_grps),
1647 	.funcs = danube_funcs,
1648 	.num_funcs = ARRAY_SIZE(danube_funcs),
1649 	.exin = danube_exin_pin_map,
1650 	.num_exin = 3
1651 };
1652 
1653 /* XWAY xRX100 Family */
1654 static struct pinctrl_xway_soc xrx100_pinctrl = {
1655 	.pin_count = XRX100_MAX_PIN,
1656 	.mfp = xrx100_mfp,
1657 	.grps = xrx100_grps,
1658 	.num_grps = ARRAY_SIZE(xrx100_grps),
1659 	.funcs = xrx100_funcs,
1660 	.num_funcs = ARRAY_SIZE(xrx100_funcs),
1661 	.exin = xrx100_exin_pin_map,
1662 	.num_exin = 6
1663 };
1664 
1665 /* XWAY xRX200 Family */
1666 static struct pinctrl_xway_soc xrx200_pinctrl = {
1667 	.pin_count = XRX200_MAX_PIN,
1668 	.mfp = xrx200_mfp,
1669 	.grps = xrx200_grps,
1670 	.num_grps = ARRAY_SIZE(xrx200_grps),
1671 	.funcs = xrx200_funcs,
1672 	.num_funcs = ARRAY_SIZE(xrx200_funcs),
1673 	.exin = xrx200_exin_pin_map,
1674 	.num_exin = 6
1675 };
1676 
1677 /* XWAY xRX300 Family */
1678 static struct pinctrl_xway_soc xrx300_pinctrl = {
1679 	.pin_count = XRX300_MAX_PIN,
1680 	.mfp = xrx300_mfp,
1681 	.grps = xrx300_grps,
1682 	.num_grps = ARRAY_SIZE(xrx300_grps),
1683 	.funcs = xrx300_funcs,
1684 	.num_funcs = ARRAY_SIZE(xrx300_funcs),
1685 	.exin = xrx300_exin_pin_map,
1686 	.num_exin = 5
1687 };
1688 
1689 static struct pinctrl_gpio_range xway_gpio_range = {
1690 	.name	= "XWAY GPIO",
1691 	.gc	= &xway_chip,
1692 };
1693 
1694 static const struct of_device_id xway_match[] = {
1695 	{ .compatible = "lantiq,pinctrl-xway", .data = &danube_pinctrl}, /*DEPRECATED*/
1696 	{ .compatible = "lantiq,pinctrl-xr9", .data = &xr9_pinctrl}, /*DEPRECATED*/
1697 	{ .compatible = "lantiq,pinctrl-ase", .data = &ase_pinctrl}, /*DEPRECATED*/
1698 	{ .compatible = "lantiq,ase-pinctrl", .data = &ase_pinctrl},
1699 	{ .compatible = "lantiq,danube-pinctrl", .data = &danube_pinctrl},
1700 	{ .compatible = "lantiq,xrx100-pinctrl", .data = &xrx100_pinctrl},
1701 	{ .compatible = "lantiq,xrx200-pinctrl", .data = &xrx200_pinctrl},
1702 	{ .compatible = "lantiq,xrx300-pinctrl", .data = &xrx300_pinctrl},
1703 	{},
1704 };
1705 MODULE_DEVICE_TABLE(of, xway_match);
1706 
1707 static int pinmux_xway_probe(struct platform_device *pdev)
1708 {
1709 	const struct of_device_id *match;
1710 	const struct pinctrl_xway_soc *xway_soc;
1711 	struct resource *res;
1712 	int ret, i;
1713 
1714 	/* get and remap our register range */
1715 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1716 	xway_info.membase[0] = devm_ioremap_resource(&pdev->dev, res);
1717 	if (IS_ERR(xway_info.membase[0]))
1718 		return PTR_ERR(xway_info.membase[0]);
1719 
1720 	match = of_match_device(xway_match, &pdev->dev);
1721 	if (match)
1722 		xway_soc = (const struct pinctrl_xway_soc *) match->data;
1723 	else
1724 		xway_soc = &danube_pinctrl;
1725 
1726 	/* find out how many pads we have */
1727 	xway_chip.ngpio = xway_soc->pin_count;
1728 
1729 	/* load our pad descriptors */
1730 	xway_info.pads = devm_kcalloc(&pdev->dev,
1731 			xway_chip.ngpio, sizeof(struct pinctrl_pin_desc),
1732 			GFP_KERNEL);
1733 	if (!xway_info.pads)
1734 		return -ENOMEM;
1735 
1736 	for (i = 0; i < xway_chip.ngpio; i++) {
1737 		/* strlen("ioXY") + 1 = 5 */
1738 		char *name = devm_kzalloc(&pdev->dev, 5, GFP_KERNEL);
1739 
1740 		if (!name)
1741 			return -ENOMEM;
1742 
1743 		snprintf(name, 5, "io%d", i);
1744 		xway_info.pads[i].number = GPIO0 + i;
1745 		xway_info.pads[i].name = name;
1746 	}
1747 	xway_pctrl_desc.pins = xway_info.pads;
1748 
1749 	/* register the gpio chip */
1750 	xway_chip.parent = &pdev->dev;
1751 	ret = devm_gpiochip_add_data(&pdev->dev, &xway_chip, NULL);
1752 	if (ret) {
1753 		dev_err(&pdev->dev, "Failed to register gpio chip\n");
1754 		return ret;
1755 	}
1756 
1757 	/* setup the data needed by pinctrl */
1758 	xway_pctrl_desc.name	= dev_name(&pdev->dev);
1759 	xway_pctrl_desc.npins	= xway_chip.ngpio;
1760 
1761 	xway_info.num_pads	= xway_chip.ngpio;
1762 	xway_info.num_mfp	= xway_chip.ngpio;
1763 	xway_info.mfp		= xway_soc->mfp;
1764 	xway_info.grps		= xway_soc->grps;
1765 	xway_info.num_grps	= xway_soc->num_grps;
1766 	xway_info.funcs		= xway_soc->funcs;
1767 	xway_info.num_funcs	= xway_soc->num_funcs;
1768 	xway_info.exin		= xway_soc->exin;
1769 	xway_info.num_exin	= xway_soc->num_exin;
1770 
1771 	/* register with the generic lantiq layer */
1772 	ret = ltq_pinctrl_register(pdev, &xway_info);
1773 	if (ret) {
1774 		dev_err(&pdev->dev, "Failed to register pinctrl driver\n");
1775 		return ret;
1776 	}
1777 
1778 	/* finish with registering the gpio range in pinctrl */
1779 	xway_gpio_range.npins = xway_chip.ngpio;
1780 	xway_gpio_range.base = xway_chip.base;
1781 	pinctrl_add_gpio_range(xway_info.pctrl, &xway_gpio_range);
1782 	dev_info(&pdev->dev, "Init done\n");
1783 	return 0;
1784 }
1785 
1786 static struct platform_driver pinmux_xway_driver = {
1787 	.probe	= pinmux_xway_probe,
1788 	.driver = {
1789 		.name	= "pinctrl-xway",
1790 		.of_match_table = xway_match,
1791 	},
1792 };
1793 
1794 static int __init pinmux_xway_init(void)
1795 {
1796 	return platform_driver_register(&pinmux_xway_driver);
1797 }
1798 
1799 core_initcall_sync(pinmux_xway_init);
1800