1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2016, BayLibre, SAS. All rights reserved.
4  * Author: Neil Armstrong <narmstrong@baylibre.com>
5  *
6  * Copyright (c) 2010, Code Aurora Forum. All rights reserved.
7  *
8  * Driver for Semtech SX150X I2C GPIO Expanders
9  * The handling of the 4-bit chips (SX1501/SX1504/SX1507) is untested.
10  *
11  * Author: Gregory Bean <gbean@codeaurora.org>
12  */
13 
14 #include <linux/regmap.h>
15 #include <linux/i2c.h>
16 #include <linux/init.h>
17 #include <linux/interrupt.h>
18 #include <linux/irq.h>
19 #include <linux/mutex.h>
20 #include <linux/slab.h>
21 #include <linux/of.h>
22 #include <linux/of_device.h>
23 #include <linux/gpio/driver.h>
24 #include <linux/pinctrl/pinconf.h>
25 #include <linux/pinctrl/pinctrl.h>
26 #include <linux/pinctrl/pinmux.h>
27 #include <linux/pinctrl/pinconf-generic.h>
28 
29 #include "core.h"
30 #include "pinconf.h"
31 #include "pinctrl-utils.h"
32 
33 /* The chip models of sx150x */
34 enum {
35 	SX150X_123 = 0,
36 	SX150X_456,
37 	SX150X_789,
38 };
39 enum {
40 	SX150X_789_REG_MISC_AUTOCLEAR_OFF = 1 << 0,
41 	SX150X_MAX_REGISTER = 0xad,
42 	SX150X_IRQ_TYPE_EDGE_RISING = 0x1,
43 	SX150X_IRQ_TYPE_EDGE_FALLING = 0x2,
44 	SX150X_789_RESET_KEY1 = 0x12,
45 	SX150X_789_RESET_KEY2 = 0x34,
46 };
47 
48 struct sx150x_123_pri {
49 	u8 reg_pld_mode;
50 	u8 reg_pld_table0;
51 	u8 reg_pld_table1;
52 	u8 reg_pld_table2;
53 	u8 reg_pld_table3;
54 	u8 reg_pld_table4;
55 	u8 reg_advanced;
56 };
57 
58 struct sx150x_456_pri {
59 	u8 reg_pld_mode;
60 	u8 reg_pld_table0;
61 	u8 reg_pld_table1;
62 	u8 reg_pld_table2;
63 	u8 reg_pld_table3;
64 	u8 reg_pld_table4;
65 	u8 reg_advanced;
66 };
67 
68 struct sx150x_789_pri {
69 	u8 reg_drain;
70 	u8 reg_polarity;
71 	u8 reg_clock;
72 	u8 reg_misc;
73 	u8 reg_reset;
74 	u8 ngpios;
75 };
76 
77 struct sx150x_device_data {
78 	u8 model;
79 	u8 reg_pullup;
80 	u8 reg_pulldn;
81 	u8 reg_dir;
82 	u8 reg_data;
83 	u8 reg_irq_mask;
84 	u8 reg_irq_src;
85 	u8 reg_sense;
86 	u8 ngpios;
87 	union {
88 		struct sx150x_123_pri x123;
89 		struct sx150x_456_pri x456;
90 		struct sx150x_789_pri x789;
91 	} pri;
92 	const struct pinctrl_pin_desc *pins;
93 	unsigned int npins;
94 };
95 
96 struct sx150x_pinctrl {
97 	struct device *dev;
98 	struct i2c_client *client;
99 	struct pinctrl_dev *pctldev;
100 	struct pinctrl_desc pinctrl_desc;
101 	struct gpio_chip gpio;
102 	struct regmap *regmap;
103 	struct {
104 		u32 sense;
105 		u32 masked;
106 	} irq;
107 	struct mutex lock;
108 	const struct sx150x_device_data *data;
109 };
110 
111 static const struct pinctrl_pin_desc sx150x_4_pins[] = {
112 	PINCTRL_PIN(0, "gpio0"),
113 	PINCTRL_PIN(1, "gpio1"),
114 	PINCTRL_PIN(2, "gpio2"),
115 	PINCTRL_PIN(3, "gpio3"),
116 	PINCTRL_PIN(4, "oscio"),
117 };
118 
119 static const struct pinctrl_pin_desc sx150x_8_pins[] = {
120 	PINCTRL_PIN(0, "gpio0"),
121 	PINCTRL_PIN(1, "gpio1"),
122 	PINCTRL_PIN(2, "gpio2"),
123 	PINCTRL_PIN(3, "gpio3"),
124 	PINCTRL_PIN(4, "gpio4"),
125 	PINCTRL_PIN(5, "gpio5"),
126 	PINCTRL_PIN(6, "gpio6"),
127 	PINCTRL_PIN(7, "gpio7"),
128 	PINCTRL_PIN(8, "oscio"),
129 };
130 
131 static const struct pinctrl_pin_desc sx150x_16_pins[] = {
132 	PINCTRL_PIN(0, "gpio0"),
133 	PINCTRL_PIN(1, "gpio1"),
134 	PINCTRL_PIN(2, "gpio2"),
135 	PINCTRL_PIN(3, "gpio3"),
136 	PINCTRL_PIN(4, "gpio4"),
137 	PINCTRL_PIN(5, "gpio5"),
138 	PINCTRL_PIN(6, "gpio6"),
139 	PINCTRL_PIN(7, "gpio7"),
140 	PINCTRL_PIN(8, "gpio8"),
141 	PINCTRL_PIN(9, "gpio9"),
142 	PINCTRL_PIN(10, "gpio10"),
143 	PINCTRL_PIN(11, "gpio11"),
144 	PINCTRL_PIN(12, "gpio12"),
145 	PINCTRL_PIN(13, "gpio13"),
146 	PINCTRL_PIN(14, "gpio14"),
147 	PINCTRL_PIN(15, "gpio15"),
148 	PINCTRL_PIN(16, "oscio"),
149 };
150 
151 static const struct sx150x_device_data sx1501q_device_data = {
152 	.model = SX150X_123,
153 	.reg_pullup	= 0x02,
154 	.reg_pulldn	= 0x03,
155 	.reg_dir	= 0x01,
156 	.reg_data	= 0x00,
157 	.reg_irq_mask	= 0x05,
158 	.reg_irq_src	= 0x08,
159 	.reg_sense	= 0x07,
160 	.pri.x123 = {
161 		.reg_pld_mode	= 0x10,
162 		.reg_pld_table0	= 0x11,
163 		.reg_pld_table2	= 0x13,
164 		.reg_advanced	= 0xad,
165 	},
166 	.ngpios	= 4,
167 	.pins = sx150x_4_pins,
168 	.npins = 4, /* oscio not available */
169 };
170 
171 static const struct sx150x_device_data sx1502q_device_data = {
172 	.model = SX150X_123,
173 	.reg_pullup	= 0x02,
174 	.reg_pulldn	= 0x03,
175 	.reg_dir	= 0x01,
176 	.reg_data	= 0x00,
177 	.reg_irq_mask	= 0x05,
178 	.reg_irq_src	= 0x08,
179 	.reg_sense	= 0x06,
180 	.pri.x123 = {
181 		.reg_pld_mode	= 0x10,
182 		.reg_pld_table0	= 0x11,
183 		.reg_pld_table1	= 0x12,
184 		.reg_pld_table2	= 0x13,
185 		.reg_pld_table3	= 0x14,
186 		.reg_pld_table4	= 0x15,
187 		.reg_advanced	= 0xad,
188 	},
189 	.ngpios	= 8,
190 	.pins = sx150x_8_pins,
191 	.npins = 8, /* oscio not available */
192 };
193 
194 static const struct sx150x_device_data sx1503q_device_data = {
195 	.model = SX150X_123,
196 	.reg_pullup	= 0x04,
197 	.reg_pulldn	= 0x06,
198 	.reg_dir	= 0x02,
199 	.reg_data	= 0x00,
200 	.reg_irq_mask	= 0x08,
201 	.reg_irq_src	= 0x0e,
202 	.reg_sense	= 0x0a,
203 	.pri.x123 = {
204 		.reg_pld_mode	= 0x20,
205 		.reg_pld_table0	= 0x22,
206 		.reg_pld_table1	= 0x24,
207 		.reg_pld_table2	= 0x26,
208 		.reg_pld_table3	= 0x28,
209 		.reg_pld_table4	= 0x2a,
210 		.reg_advanced	= 0xad,
211 	},
212 	.ngpios	= 16,
213 	.pins = sx150x_16_pins,
214 	.npins  = 16, /* oscio not available */
215 };
216 
217 static const struct sx150x_device_data sx1504q_device_data = {
218 	.model = SX150X_456,
219 	.reg_pullup	= 0x02,
220 	.reg_pulldn	= 0x03,
221 	.reg_dir	= 0x01,
222 	.reg_data	= 0x00,
223 	.reg_irq_mask	= 0x05,
224 	.reg_irq_src	= 0x08,
225 	.reg_sense	= 0x07,
226 	.pri.x456 = {
227 		.reg_pld_mode	= 0x10,
228 		.reg_pld_table0	= 0x11,
229 		.reg_pld_table2	= 0x13,
230 	},
231 	.ngpios	= 4,
232 	.pins = sx150x_4_pins,
233 	.npins = 4, /* oscio not available */
234 };
235 
236 static const struct sx150x_device_data sx1505q_device_data = {
237 	.model = SX150X_456,
238 	.reg_pullup	= 0x02,
239 	.reg_pulldn	= 0x03,
240 	.reg_dir	= 0x01,
241 	.reg_data	= 0x00,
242 	.reg_irq_mask	= 0x05,
243 	.reg_irq_src	= 0x08,
244 	.reg_sense	= 0x06,
245 	.pri.x456 = {
246 		.reg_pld_mode	= 0x10,
247 		.reg_pld_table0	= 0x11,
248 		.reg_pld_table1	= 0x12,
249 		.reg_pld_table2	= 0x13,
250 		.reg_pld_table3	= 0x14,
251 		.reg_pld_table4	= 0x15,
252 	},
253 	.ngpios	= 8,
254 	.pins = sx150x_8_pins,
255 	.npins = 8, /* oscio not available */
256 };
257 
258 static const struct sx150x_device_data sx1506q_device_data = {
259 	.model = SX150X_456,
260 	.reg_pullup	= 0x04,
261 	.reg_pulldn	= 0x06,
262 	.reg_dir	= 0x02,
263 	.reg_data	= 0x00,
264 	.reg_irq_mask	= 0x08,
265 	.reg_irq_src	= 0x0e,
266 	.reg_sense	= 0x0a,
267 	.pri.x456 = {
268 		.reg_pld_mode	= 0x20,
269 		.reg_pld_table0	= 0x22,
270 		.reg_pld_table1	= 0x24,
271 		.reg_pld_table2	= 0x26,
272 		.reg_pld_table3	= 0x28,
273 		.reg_pld_table4	= 0x2a,
274 		.reg_advanced	= 0xad,
275 	},
276 	.ngpios	= 16,
277 	.pins = sx150x_16_pins,
278 	.npins = 16, /* oscio not available */
279 };
280 
281 static const struct sx150x_device_data sx1507q_device_data = {
282 	.model = SX150X_789,
283 	.reg_pullup	= 0x03,
284 	.reg_pulldn	= 0x04,
285 	.reg_dir	= 0x07,
286 	.reg_data	= 0x08,
287 	.reg_irq_mask	= 0x09,
288 	.reg_irq_src	= 0x0b,
289 	.reg_sense	= 0x0a,
290 	.pri.x789 = {
291 		.reg_drain	= 0x05,
292 		.reg_polarity	= 0x06,
293 		.reg_clock	= 0x0d,
294 		.reg_misc	= 0x0e,
295 		.reg_reset	= 0x7d,
296 	},
297 	.ngpios = 4,
298 	.pins = sx150x_4_pins,
299 	.npins = ARRAY_SIZE(sx150x_4_pins),
300 };
301 
302 static const struct sx150x_device_data sx1508q_device_data = {
303 	.model = SX150X_789,
304 	.reg_pullup	= 0x03,
305 	.reg_pulldn	= 0x04,
306 	.reg_dir	= 0x07,
307 	.reg_data	= 0x08,
308 	.reg_irq_mask	= 0x09,
309 	.reg_irq_src	= 0x0c,
310 	.reg_sense	= 0x0a,
311 	.pri.x789 = {
312 		.reg_drain	= 0x05,
313 		.reg_polarity	= 0x06,
314 		.reg_clock	= 0x0f,
315 		.reg_misc	= 0x10,
316 		.reg_reset	= 0x7d,
317 	},
318 	.ngpios = 8,
319 	.pins = sx150x_8_pins,
320 	.npins = ARRAY_SIZE(sx150x_8_pins),
321 };
322 
323 static const struct sx150x_device_data sx1509q_device_data = {
324 	.model = SX150X_789,
325 	.reg_pullup	= 0x06,
326 	.reg_pulldn	= 0x08,
327 	.reg_dir	= 0x0e,
328 	.reg_data	= 0x10,
329 	.reg_irq_mask	= 0x12,
330 	.reg_irq_src	= 0x18,
331 	.reg_sense	= 0x14,
332 	.pri.x789 = {
333 		.reg_drain	= 0x0a,
334 		.reg_polarity	= 0x0c,
335 		.reg_clock	= 0x1e,
336 		.reg_misc	= 0x1f,
337 		.reg_reset	= 0x7d,
338 	},
339 	.ngpios	= 16,
340 	.pins = sx150x_16_pins,
341 	.npins = ARRAY_SIZE(sx150x_16_pins),
342 };
343 
344 static int sx150x_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
345 {
346 	return 0;
347 }
348 
349 static const char *sx150x_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
350 						unsigned int group)
351 {
352 	return NULL;
353 }
354 
355 static int sx150x_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
356 					unsigned int group,
357 					const unsigned int **pins,
358 					unsigned int *num_pins)
359 {
360 	return -ENOTSUPP;
361 }
362 
363 static const struct pinctrl_ops sx150x_pinctrl_ops = {
364 	.get_groups_count = sx150x_pinctrl_get_groups_count,
365 	.get_group_name = sx150x_pinctrl_get_group_name,
366 	.get_group_pins = sx150x_pinctrl_get_group_pins,
367 #ifdef CONFIG_OF
368 	.dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
369 	.dt_free_map = pinctrl_utils_free_map,
370 #endif
371 };
372 
373 static bool sx150x_pin_is_oscio(struct sx150x_pinctrl *pctl, unsigned int pin)
374 {
375 	if (pin >= pctl->data->npins)
376 		return false;
377 
378 	/* OSCIO pin is only present in 789 devices */
379 	if (pctl->data->model != SX150X_789)
380 		return false;
381 
382 	return !strcmp(pctl->data->pins[pin].name, "oscio");
383 }
384 
385 static int sx150x_gpio_get_direction(struct gpio_chip *chip,
386 				      unsigned int offset)
387 {
388 	struct sx150x_pinctrl *pctl = gpiochip_get_data(chip);
389 	unsigned int value;
390 	int ret;
391 
392 	if (sx150x_pin_is_oscio(pctl, offset))
393 		return GPIO_LINE_DIRECTION_OUT;
394 
395 	ret = regmap_read(pctl->regmap, pctl->data->reg_dir, &value);
396 	if (ret < 0)
397 		return ret;
398 
399 	if (value & BIT(offset))
400 		return GPIO_LINE_DIRECTION_IN;
401 
402 	return GPIO_LINE_DIRECTION_OUT;
403 }
404 
405 static int sx150x_gpio_get(struct gpio_chip *chip, unsigned int offset)
406 {
407 	struct sx150x_pinctrl *pctl = gpiochip_get_data(chip);
408 	unsigned int value;
409 	int ret;
410 
411 	if (sx150x_pin_is_oscio(pctl, offset))
412 		return -EINVAL;
413 
414 	ret = regmap_read(pctl->regmap, pctl->data->reg_data, &value);
415 	if (ret < 0)
416 		return ret;
417 
418 	return !!(value & BIT(offset));
419 }
420 
421 static int __sx150x_gpio_set(struct sx150x_pinctrl *pctl, unsigned int offset,
422 			     int value)
423 {
424 	return regmap_write_bits(pctl->regmap, pctl->data->reg_data,
425 				 BIT(offset), value ? BIT(offset) : 0);
426 }
427 
428 static int sx150x_gpio_oscio_set(struct sx150x_pinctrl *pctl,
429 				 int value)
430 {
431 	return regmap_write(pctl->regmap,
432 			    pctl->data->pri.x789.reg_clock,
433 			    (value ? 0x1f : 0x10));
434 }
435 
436 static void sx150x_gpio_set(struct gpio_chip *chip, unsigned int offset,
437 			    int value)
438 {
439 	struct sx150x_pinctrl *pctl = gpiochip_get_data(chip);
440 
441 	if (sx150x_pin_is_oscio(pctl, offset))
442 		sx150x_gpio_oscio_set(pctl, value);
443 	else
444 		__sx150x_gpio_set(pctl, offset, value);
445 }
446 
447 static void sx150x_gpio_set_multiple(struct gpio_chip *chip,
448 				     unsigned long *mask,
449 				     unsigned long *bits)
450 {
451 	struct sx150x_pinctrl *pctl = gpiochip_get_data(chip);
452 
453 	regmap_write_bits(pctl->regmap, pctl->data->reg_data, *mask, *bits);
454 }
455 
456 static int sx150x_gpio_direction_input(struct gpio_chip *chip,
457 				       unsigned int offset)
458 {
459 	struct sx150x_pinctrl *pctl = gpiochip_get_data(chip);
460 
461 	if (sx150x_pin_is_oscio(pctl, offset))
462 		return -EINVAL;
463 
464 	return regmap_write_bits(pctl->regmap,
465 				 pctl->data->reg_dir,
466 				 BIT(offset), BIT(offset));
467 }
468 
469 static int sx150x_gpio_direction_output(struct gpio_chip *chip,
470 					unsigned int offset, int value)
471 {
472 	struct sx150x_pinctrl *pctl = gpiochip_get_data(chip);
473 	int ret;
474 
475 	if (sx150x_pin_is_oscio(pctl, offset))
476 		return sx150x_gpio_oscio_set(pctl, value);
477 
478 	ret = __sx150x_gpio_set(pctl, offset, value);
479 	if (ret < 0)
480 		return ret;
481 
482 	return regmap_write_bits(pctl->regmap,
483 				 pctl->data->reg_dir,
484 				 BIT(offset), 0);
485 }
486 
487 static void sx150x_irq_mask(struct irq_data *d)
488 {
489 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
490 	struct sx150x_pinctrl *pctl = gpiochip_get_data(gc);
491 	unsigned int n = irqd_to_hwirq(d);
492 
493 	pctl->irq.masked |= BIT(n);
494 	gpiochip_disable_irq(gc, n);
495 }
496 
497 static void sx150x_irq_unmask(struct irq_data *d)
498 {
499 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
500 	struct sx150x_pinctrl *pctl = gpiochip_get_data(gc);
501 	unsigned int n = irqd_to_hwirq(d);
502 
503 	gpiochip_enable_irq(gc, n);
504 	pctl->irq.masked &= ~BIT(n);
505 }
506 
507 static void sx150x_irq_set_sense(struct sx150x_pinctrl *pctl,
508 				 unsigned int line, unsigned int sense)
509 {
510 	/*
511 	 * Every interrupt line is represented by two bits shifted
512 	 * proportionally to the line number
513 	 */
514 	const unsigned int n = line * 2;
515 	const unsigned int mask = ~((SX150X_IRQ_TYPE_EDGE_RISING |
516 				     SX150X_IRQ_TYPE_EDGE_FALLING) << n);
517 
518 	pctl->irq.sense &= mask;
519 	pctl->irq.sense |= sense << n;
520 }
521 
522 static int sx150x_irq_set_type(struct irq_data *d, unsigned int flow_type)
523 {
524 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
525 	struct sx150x_pinctrl *pctl = gpiochip_get_data(gc);
526 	unsigned int n, val = 0;
527 
528 	if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
529 		return -EINVAL;
530 
531 	n = irqd_to_hwirq(d);
532 
533 	if (flow_type & IRQ_TYPE_EDGE_RISING)
534 		val |= SX150X_IRQ_TYPE_EDGE_RISING;
535 	if (flow_type & IRQ_TYPE_EDGE_FALLING)
536 		val |= SX150X_IRQ_TYPE_EDGE_FALLING;
537 
538 	sx150x_irq_set_sense(pctl, n, val);
539 	return 0;
540 }
541 
542 static irqreturn_t sx150x_irq_thread_fn(int irq, void *dev_id)
543 {
544 	struct sx150x_pinctrl *pctl = (struct sx150x_pinctrl *)dev_id;
545 	unsigned long n, status;
546 	unsigned int val;
547 	int err;
548 
549 	err = regmap_read(pctl->regmap, pctl->data->reg_irq_src, &val);
550 	if (err < 0)
551 		return IRQ_NONE;
552 
553 	err = regmap_write(pctl->regmap, pctl->data->reg_irq_src, val);
554 	if (err < 0)
555 		return IRQ_NONE;
556 
557 	status = val;
558 	for_each_set_bit(n, &status, pctl->data->ngpios)
559 		handle_nested_irq(irq_find_mapping(pctl->gpio.irq.domain, n));
560 
561 	return IRQ_HANDLED;
562 }
563 
564 static void sx150x_irq_bus_lock(struct irq_data *d)
565 {
566 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
567 	struct sx150x_pinctrl *pctl = gpiochip_get_data(gc);
568 
569 	mutex_lock(&pctl->lock);
570 }
571 
572 static void sx150x_irq_bus_sync_unlock(struct irq_data *d)
573 {
574 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
575 	struct sx150x_pinctrl *pctl = gpiochip_get_data(gc);
576 
577 	regmap_write(pctl->regmap, pctl->data->reg_irq_mask, pctl->irq.masked);
578 	regmap_write(pctl->regmap, pctl->data->reg_sense, pctl->irq.sense);
579 	mutex_unlock(&pctl->lock);
580 }
581 
582 
583 static void sx150x_irq_print_chip(struct irq_data *d, struct seq_file *p)
584 {
585 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
586 	struct sx150x_pinctrl *pctl = gpiochip_get_data(gc);
587 
588 	seq_printf(p, pctl->client->name);
589 }
590 
591 static const struct irq_chip sx150x_irq_chip = {
592 	.irq_mask = sx150x_irq_mask,
593 	.irq_unmask = sx150x_irq_unmask,
594 	.irq_set_type = sx150x_irq_set_type,
595 	.irq_bus_lock = sx150x_irq_bus_lock,
596 	.irq_bus_sync_unlock = sx150x_irq_bus_sync_unlock,
597 	.irq_print_chip = sx150x_irq_print_chip,
598 	.flags = IRQCHIP_IMMUTABLE,
599 	GPIOCHIP_IRQ_RESOURCE_HELPERS,
600 };
601 
602 static int sx150x_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
603 			      unsigned long *config)
604 {
605 	struct sx150x_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
606 	unsigned int param = pinconf_to_config_param(*config);
607 	int ret;
608 	u32 arg;
609 	unsigned int data;
610 
611 	if (sx150x_pin_is_oscio(pctl, pin)) {
612 		switch (param) {
613 		case PIN_CONFIG_DRIVE_PUSH_PULL:
614 		case PIN_CONFIG_OUTPUT:
615 			ret = regmap_read(pctl->regmap,
616 					  pctl->data->pri.x789.reg_clock,
617 					  &data);
618 			if (ret < 0)
619 				return ret;
620 
621 			if (param == PIN_CONFIG_DRIVE_PUSH_PULL)
622 				arg = (data & 0x1f) ? 1 : 0;
623 			else {
624 				if ((data & 0x1f) == 0x1f)
625 					arg = 1;
626 				else if ((data & 0x1f) == 0x10)
627 					arg = 0;
628 				else
629 					return -EINVAL;
630 			}
631 
632 			break;
633 		default:
634 			return -ENOTSUPP;
635 		}
636 
637 		goto out;
638 	}
639 
640 	switch (param) {
641 	case PIN_CONFIG_BIAS_PULL_DOWN:
642 		ret = regmap_read(pctl->regmap,
643 				  pctl->data->reg_pulldn,
644 				  &data);
645 		data &= BIT(pin);
646 
647 		if (ret < 0)
648 			return ret;
649 
650 		if (!ret)
651 			return -EINVAL;
652 
653 		arg = 1;
654 		break;
655 
656 	case PIN_CONFIG_BIAS_PULL_UP:
657 		ret = regmap_read(pctl->regmap,
658 				  pctl->data->reg_pullup,
659 				  &data);
660 		data &= BIT(pin);
661 
662 		if (ret < 0)
663 			return ret;
664 
665 		if (!ret)
666 			return -EINVAL;
667 
668 		arg = 1;
669 		break;
670 
671 	case PIN_CONFIG_DRIVE_OPEN_DRAIN:
672 		if (pctl->data->model != SX150X_789)
673 			return -ENOTSUPP;
674 
675 		ret = regmap_read(pctl->regmap,
676 				  pctl->data->pri.x789.reg_drain,
677 				  &data);
678 		data &= BIT(pin);
679 
680 		if (ret < 0)
681 			return ret;
682 
683 		if (!data)
684 			return -EINVAL;
685 
686 		arg = 1;
687 		break;
688 
689 	case PIN_CONFIG_DRIVE_PUSH_PULL:
690 		if (pctl->data->model != SX150X_789)
691 			arg = true;
692 		else {
693 			ret = regmap_read(pctl->regmap,
694 					  pctl->data->pri.x789.reg_drain,
695 					  &data);
696 			data &= BIT(pin);
697 
698 			if (ret < 0)
699 				return ret;
700 
701 			if (data)
702 				return -EINVAL;
703 
704 			arg = 1;
705 		}
706 		break;
707 
708 	case PIN_CONFIG_OUTPUT:
709 		ret = sx150x_gpio_get_direction(&pctl->gpio, pin);
710 		if (ret < 0)
711 			return ret;
712 
713 		if (ret == GPIO_LINE_DIRECTION_IN)
714 			return -EINVAL;
715 
716 		ret = sx150x_gpio_get(&pctl->gpio, pin);
717 		if (ret < 0)
718 			return ret;
719 
720 		arg = ret;
721 		break;
722 
723 	default:
724 		return -ENOTSUPP;
725 	}
726 
727 out:
728 	*config = pinconf_to_config_packed(param, arg);
729 
730 	return 0;
731 }
732 
733 static int sx150x_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
734 			      unsigned long *configs, unsigned int num_configs)
735 {
736 	struct sx150x_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
737 	enum pin_config_param param;
738 	u32 arg;
739 	int i;
740 	int ret;
741 
742 	for (i = 0; i < num_configs; i++) {
743 		param = pinconf_to_config_param(configs[i]);
744 		arg = pinconf_to_config_argument(configs[i]);
745 
746 		if (sx150x_pin_is_oscio(pctl, pin)) {
747 			if (param == PIN_CONFIG_OUTPUT) {
748 				ret = sx150x_gpio_direction_output(&pctl->gpio,
749 								   pin, arg);
750 				if (ret < 0)
751 					return ret;
752 
753 				continue;
754 			} else
755 				return -ENOTSUPP;
756 		}
757 
758 		switch (param) {
759 		case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
760 		case PIN_CONFIG_BIAS_DISABLE:
761 			ret = regmap_write_bits(pctl->regmap,
762 						pctl->data->reg_pulldn,
763 						BIT(pin), 0);
764 			if (ret < 0)
765 				return ret;
766 
767 			ret = regmap_write_bits(pctl->regmap,
768 						pctl->data->reg_pullup,
769 						BIT(pin), 0);
770 			if (ret < 0)
771 				return ret;
772 
773 			break;
774 
775 		case PIN_CONFIG_BIAS_PULL_UP:
776 			ret = regmap_write_bits(pctl->regmap,
777 						pctl->data->reg_pullup,
778 						BIT(pin), BIT(pin));
779 			if (ret < 0)
780 				return ret;
781 
782 			break;
783 
784 		case PIN_CONFIG_BIAS_PULL_DOWN:
785 			ret = regmap_write_bits(pctl->regmap,
786 						pctl->data->reg_pulldn,
787 						BIT(pin), BIT(pin));
788 			if (ret < 0)
789 				return ret;
790 
791 			break;
792 
793 		case PIN_CONFIG_DRIVE_OPEN_DRAIN:
794 			if (pctl->data->model != SX150X_789 ||
795 			    sx150x_pin_is_oscio(pctl, pin))
796 				return -ENOTSUPP;
797 
798 			ret = regmap_write_bits(pctl->regmap,
799 						pctl->data->pri.x789.reg_drain,
800 						BIT(pin), BIT(pin));
801 			if (ret < 0)
802 				return ret;
803 
804 			break;
805 
806 		case PIN_CONFIG_DRIVE_PUSH_PULL:
807 			if (pctl->data->model != SX150X_789 ||
808 			    sx150x_pin_is_oscio(pctl, pin))
809 				return 0;
810 
811 			ret = regmap_write_bits(pctl->regmap,
812 						pctl->data->pri.x789.reg_drain,
813 						BIT(pin), 0);
814 			if (ret < 0)
815 				return ret;
816 
817 			break;
818 
819 		case PIN_CONFIG_OUTPUT:
820 			ret = sx150x_gpio_direction_output(&pctl->gpio,
821 							   pin, arg);
822 			if (ret < 0)
823 				return ret;
824 
825 			break;
826 
827 		default:
828 			return -ENOTSUPP;
829 		}
830 	} /* for each config */
831 
832 	return 0;
833 }
834 
835 static const struct pinconf_ops sx150x_pinconf_ops = {
836 	.pin_config_get = sx150x_pinconf_get,
837 	.pin_config_set = sx150x_pinconf_set,
838 	.is_generic = true,
839 };
840 
841 static const struct i2c_device_id sx150x_id[] = {
842 	{"sx1501q", (kernel_ulong_t) &sx1501q_device_data },
843 	{"sx1502q", (kernel_ulong_t) &sx1502q_device_data },
844 	{"sx1503q", (kernel_ulong_t) &sx1503q_device_data },
845 	{"sx1504q", (kernel_ulong_t) &sx1504q_device_data },
846 	{"sx1505q", (kernel_ulong_t) &sx1505q_device_data },
847 	{"sx1506q", (kernel_ulong_t) &sx1506q_device_data },
848 	{"sx1507q", (kernel_ulong_t) &sx1507q_device_data },
849 	{"sx1508q", (kernel_ulong_t) &sx1508q_device_data },
850 	{"sx1509q", (kernel_ulong_t) &sx1509q_device_data },
851 	{}
852 };
853 
854 static const struct of_device_id sx150x_of_match[] = {
855 	{ .compatible = "semtech,sx1501q", .data = &sx1501q_device_data },
856 	{ .compatible = "semtech,sx1502q", .data = &sx1502q_device_data },
857 	{ .compatible = "semtech,sx1503q", .data = &sx1503q_device_data },
858 	{ .compatible = "semtech,sx1504q", .data = &sx1504q_device_data },
859 	{ .compatible = "semtech,sx1505q", .data = &sx1505q_device_data },
860 	{ .compatible = "semtech,sx1506q", .data = &sx1506q_device_data },
861 	{ .compatible = "semtech,sx1507q", .data = &sx1507q_device_data },
862 	{ .compatible = "semtech,sx1508q", .data = &sx1508q_device_data },
863 	{ .compatible = "semtech,sx1509q", .data = &sx1509q_device_data },
864 	{},
865 };
866 
867 static int sx150x_reset(struct sx150x_pinctrl *pctl)
868 {
869 	int err;
870 
871 	err = i2c_smbus_write_byte_data(pctl->client,
872 					pctl->data->pri.x789.reg_reset,
873 					SX150X_789_RESET_KEY1);
874 	if (err < 0)
875 		return err;
876 
877 	err = i2c_smbus_write_byte_data(pctl->client,
878 					pctl->data->pri.x789.reg_reset,
879 					SX150X_789_RESET_KEY2);
880 	return err;
881 }
882 
883 static int sx150x_init_misc(struct sx150x_pinctrl *pctl)
884 {
885 	u8 reg, value;
886 
887 	switch (pctl->data->model) {
888 	case SX150X_789:
889 		reg   = pctl->data->pri.x789.reg_misc;
890 		value = SX150X_789_REG_MISC_AUTOCLEAR_OFF;
891 		break;
892 	case SX150X_456:
893 		reg   = pctl->data->pri.x456.reg_advanced;
894 		value = 0x00;
895 
896 		/*
897 		 * Only SX1506 has RegAdvanced, SX1504/5 are expected
898 		 * to initialize this offset to zero
899 		 */
900 		if (!reg)
901 			return 0;
902 		break;
903 	case SX150X_123:
904 		reg   = pctl->data->pri.x123.reg_advanced;
905 		value = 0x00;
906 		break;
907 	default:
908 		WARN(1, "Unknown chip model %d\n", pctl->data->model);
909 		return -EINVAL;
910 	}
911 
912 	return regmap_write(pctl->regmap, reg, value);
913 }
914 
915 static int sx150x_init_hw(struct sx150x_pinctrl *pctl)
916 {
917 	const u8 reg[] = {
918 		[SX150X_789] = pctl->data->pri.x789.reg_polarity,
919 		[SX150X_456] = pctl->data->pri.x456.reg_pld_mode,
920 		[SX150X_123] = pctl->data->pri.x123.reg_pld_mode,
921 	};
922 	int err;
923 
924 	if (pctl->data->model == SX150X_789 &&
925 	    of_property_read_bool(pctl->dev->of_node, "semtech,probe-reset")) {
926 		err = sx150x_reset(pctl);
927 		if (err < 0)
928 			return err;
929 	}
930 
931 	err = sx150x_init_misc(pctl);
932 	if (err < 0)
933 		return err;
934 
935 	/* Set all pins to work in normal mode */
936 	return regmap_write(pctl->regmap, reg[pctl->data->model], 0);
937 }
938 
939 static int sx150x_regmap_reg_width(struct sx150x_pinctrl *pctl,
940 				   unsigned int reg)
941 {
942 	const struct sx150x_device_data *data = pctl->data;
943 
944 	if (reg == data->reg_sense) {
945 		/*
946 		 * RegSense packs two bits of configuration per GPIO,
947 		 * so we'd need to read twice as many bits as there
948 		 * are GPIO in our chip
949 		 */
950 		return 2 * data->ngpios;
951 	} else if ((data->model == SX150X_789 &&
952 		    (reg == data->pri.x789.reg_misc ||
953 		     reg == data->pri.x789.reg_clock ||
954 		     reg == data->pri.x789.reg_reset))
955 		   ||
956 		   (data->model == SX150X_123 &&
957 		    reg == data->pri.x123.reg_advanced)
958 		   ||
959 		   (data->model == SX150X_456 &&
960 		    data->pri.x456.reg_advanced &&
961 		    reg == data->pri.x456.reg_advanced)) {
962 		return 8;
963 	} else {
964 		return data->ngpios;
965 	}
966 }
967 
968 static unsigned int sx150x_maybe_swizzle(struct sx150x_pinctrl *pctl,
969 					 unsigned int reg, unsigned int val)
970 {
971 	unsigned int a, b;
972 	const struct sx150x_device_data *data = pctl->data;
973 
974 	/*
975 	 * Whereas SX1509 presents RegSense in a simple layout as such:
976 	 *	reg     [ f f e e d d c c ]
977 	 *	reg + 1 [ b b a a 9 9 8 8 ]
978 	 *	reg + 2 [ 7 7 6 6 5 5 4 4 ]
979 	 *	reg + 3 [ 3 3 2 2 1 1 0 0 ]
980 	 *
981 	 * SX1503 and SX1506 deviate from that data layout, instead storing
982 	 * their contents as follows:
983 	 *
984 	 *	reg     [ f f e e d d c c ]
985 	 *	reg + 1 [ 7 7 6 6 5 5 4 4 ]
986 	 *	reg + 2 [ b b a a 9 9 8 8 ]
987 	 *	reg + 3 [ 3 3 2 2 1 1 0 0 ]
988 	 *
989 	 * so, taking that into account, we swap two
990 	 * inner bytes of a 4-byte result
991 	 */
992 
993 	if (reg == data->reg_sense &&
994 	    data->ngpios == 16 &&
995 	    (data->model == SX150X_123 ||
996 	     data->model == SX150X_456)) {
997 		a = val & 0x00ff0000;
998 		b = val & 0x0000ff00;
999 
1000 		val &= 0xff0000ff;
1001 		val |= b << 8;
1002 		val |= a >> 8;
1003 	}
1004 
1005 	return val;
1006 }
1007 
1008 /*
1009  * In order to mask the differences between 16 and 8 bit expander
1010  * devices we set up a sligthly ficticious regmap that pretends to be
1011  * a set of 32-bit (to accommodate RegSenseLow/RegSenseHigh
1012  * pair/quartet) registers and transparently reconstructs those
1013  * registers via multiple I2C/SMBus reads
1014  *
1015  * This way the rest of the driver code, interfacing with the chip via
1016  * regmap API, can work assuming that each GPIO pin is represented by
1017  * a group of bits at an offset proportional to GPIO number within a
1018  * given register.
1019  */
1020 static int sx150x_regmap_reg_read(void *context, unsigned int reg,
1021 				  unsigned int *result)
1022 {
1023 	int ret, n;
1024 	struct sx150x_pinctrl *pctl = context;
1025 	struct i2c_client *i2c = pctl->client;
1026 	const int width = sx150x_regmap_reg_width(pctl, reg);
1027 	unsigned int idx, val;
1028 
1029 	/*
1030 	 * There are four potential cases covered by this function:
1031 	 *
1032 	 * 1) 8-pin chip, single configuration bit register
1033 	 *
1034 	 *	This is trivial the code below just needs to read:
1035 	 *		reg  [ 7 6 5 4 3 2 1 0 ]
1036 	 *
1037 	 * 2) 8-pin chip, double configuration bit register (RegSense)
1038 	 *
1039 	 *	The read will be done as follows:
1040 	 *		reg      [ 7 7 6 6 5 5 4 4 ]
1041 	 *		reg + 1  [ 3 3 2 2 1 1 0 0 ]
1042 	 *
1043 	 * 3) 16-pin chip, single configuration bit register
1044 	 *
1045 	 *	The read will be done as follows:
1046 	 *		reg     [ f e d c b a 9 8 ]
1047 	 *		reg + 1 [ 7 6 5 4 3 2 1 0 ]
1048 	 *
1049 	 * 4) 16-pin chip, double configuration bit register (RegSense)
1050 	 *
1051 	 *	The read will be done as follows:
1052 	 *		reg     [ f f e e d d c c ]
1053 	 *		reg + 1 [ b b a a 9 9 8 8 ]
1054 	 *		reg + 2 [ 7 7 6 6 5 5 4 4 ]
1055 	 *		reg + 3 [ 3 3 2 2 1 1 0 0 ]
1056 	 */
1057 
1058 	for (n = width, val = 0, idx = reg; n > 0; n -= 8, idx++) {
1059 		val <<= 8;
1060 
1061 		ret = i2c_smbus_read_byte_data(i2c, idx);
1062 		if (ret < 0)
1063 			return ret;
1064 
1065 		val |= ret;
1066 	}
1067 
1068 	*result = sx150x_maybe_swizzle(pctl, reg, val);
1069 
1070 	return 0;
1071 }
1072 
1073 static int sx150x_regmap_reg_write(void *context, unsigned int reg,
1074 				   unsigned int val)
1075 {
1076 	int ret, n;
1077 	struct sx150x_pinctrl *pctl = context;
1078 	struct i2c_client *i2c = pctl->client;
1079 	const int width = sx150x_regmap_reg_width(pctl, reg);
1080 
1081 	val = sx150x_maybe_swizzle(pctl, reg, val);
1082 
1083 	n = (width - 1) & ~7;
1084 	do {
1085 		const u8 byte = (val >> n) & 0xff;
1086 
1087 		ret = i2c_smbus_write_byte_data(i2c, reg, byte);
1088 		if (ret < 0)
1089 			return ret;
1090 
1091 		reg++;
1092 		n -= 8;
1093 	} while (n >= 0);
1094 
1095 	return 0;
1096 }
1097 
1098 static bool sx150x_reg_volatile(struct device *dev, unsigned int reg)
1099 {
1100 	struct sx150x_pinctrl *pctl = i2c_get_clientdata(to_i2c_client(dev));
1101 
1102 	return reg == pctl->data->reg_irq_src || reg == pctl->data->reg_data;
1103 }
1104 
1105 static const struct regmap_config sx150x_regmap_config = {
1106 	.reg_bits = 8,
1107 	.val_bits = 32,
1108 
1109 	.cache_type = REGCACHE_RBTREE,
1110 
1111 	.reg_read = sx150x_regmap_reg_read,
1112 	.reg_write = sx150x_regmap_reg_write,
1113 
1114 	.max_register = SX150X_MAX_REGISTER,
1115 	.volatile_reg = sx150x_reg_volatile,
1116 };
1117 
1118 static int sx150x_probe(struct i2c_client *client)
1119 {
1120 	const struct i2c_device_id *id = i2c_client_get_device_id(client);
1121 	static const u32 i2c_funcs = I2C_FUNC_SMBUS_BYTE_DATA |
1122 				     I2C_FUNC_SMBUS_WRITE_WORD_DATA;
1123 	struct device *dev = &client->dev;
1124 	struct sx150x_pinctrl *pctl;
1125 	int ret;
1126 
1127 	if (!i2c_check_functionality(client->adapter, i2c_funcs))
1128 		return -ENOSYS;
1129 
1130 	pctl = devm_kzalloc(dev, sizeof(*pctl), GFP_KERNEL);
1131 	if (!pctl)
1132 		return -ENOMEM;
1133 
1134 	i2c_set_clientdata(client, pctl);
1135 
1136 	pctl->dev = dev;
1137 	pctl->client = client;
1138 
1139 	if (dev->of_node)
1140 		pctl->data = of_device_get_match_data(dev);
1141 	else
1142 		pctl->data = (struct sx150x_device_data *)id->driver_data;
1143 
1144 	if (!pctl->data)
1145 		return -EINVAL;
1146 
1147 	pctl->regmap = devm_regmap_init(dev, NULL, pctl,
1148 					&sx150x_regmap_config);
1149 	if (IS_ERR(pctl->regmap)) {
1150 		ret = PTR_ERR(pctl->regmap);
1151 		dev_err(dev, "Failed to allocate register map: %d\n",
1152 			ret);
1153 		return ret;
1154 	}
1155 
1156 	mutex_init(&pctl->lock);
1157 
1158 	ret = sx150x_init_hw(pctl);
1159 	if (ret)
1160 		return ret;
1161 
1162 	/* Pinctrl_desc */
1163 	pctl->pinctrl_desc.name = "sx150x-pinctrl";
1164 	pctl->pinctrl_desc.pctlops = &sx150x_pinctrl_ops;
1165 	pctl->pinctrl_desc.confops = &sx150x_pinconf_ops;
1166 	pctl->pinctrl_desc.pins = pctl->data->pins;
1167 	pctl->pinctrl_desc.npins = pctl->data->npins;
1168 	pctl->pinctrl_desc.owner = THIS_MODULE;
1169 
1170 	ret = devm_pinctrl_register_and_init(dev, &pctl->pinctrl_desc,
1171 					     pctl, &pctl->pctldev);
1172 	if (ret) {
1173 		dev_err(dev, "Failed to register pinctrl device\n");
1174 		return ret;
1175 	}
1176 
1177 	/* Register GPIO controller */
1178 	pctl->gpio.base = -1;
1179 	pctl->gpio.ngpio = pctl->data->npins;
1180 	pctl->gpio.get_direction = sx150x_gpio_get_direction;
1181 	pctl->gpio.direction_input = sx150x_gpio_direction_input;
1182 	pctl->gpio.direction_output = sx150x_gpio_direction_output;
1183 	pctl->gpio.get = sx150x_gpio_get;
1184 	pctl->gpio.set = sx150x_gpio_set;
1185 	pctl->gpio.set_config = gpiochip_generic_config;
1186 	pctl->gpio.parent = dev;
1187 	pctl->gpio.can_sleep = true;
1188 	pctl->gpio.label = devm_kstrdup(dev, client->name, GFP_KERNEL);
1189 	if (!pctl->gpio.label)
1190 		return -ENOMEM;
1191 
1192 	/*
1193 	 * Setting multiple pins is not safe when all pins are not
1194 	 * handled by the same regmap register. The oscio pin (present
1195 	 * on the SX150X_789 chips) lives in its own register, so
1196 	 * would require locking that is not in place at this time.
1197 	 */
1198 	if (pctl->data->model != SX150X_789)
1199 		pctl->gpio.set_multiple = sx150x_gpio_set_multiple;
1200 
1201 	/* Add Interrupt support if an irq is specified */
1202 	if (client->irq > 0) {
1203 		struct gpio_irq_chip *girq;
1204 
1205 		pctl->irq.masked = ~0;
1206 		pctl->irq.sense = 0;
1207 		/*
1208 		 * Because sx150x_irq_threaded_fn invokes all of the
1209 		 * nested interrupt handlers via handle_nested_irq,
1210 		 * any "handler" assigned to struct gpio_irq_chip
1211 		 * below is going to be ignored, so the choice of the
1212 		 * function does not matter that much.
1213 		 *
1214 		 * We set it to handle_bad_irq to avoid confusion,
1215 		 * plus it will be instantly noticeable if it is ever
1216 		 * called (should not happen)
1217 		 */
1218 		girq = &pctl->gpio.irq;
1219 		gpio_irq_chip_set_chip(girq, &sx150x_irq_chip);
1220 		/* This will let us handle the parent IRQ in the driver */
1221 		girq->parent_handler = NULL;
1222 		girq->num_parents = 0;
1223 		girq->parents = NULL;
1224 		girq->default_type = IRQ_TYPE_NONE;
1225 		girq->handler = handle_bad_irq;
1226 		girq->threaded = true;
1227 
1228 		ret = devm_request_threaded_irq(dev, client->irq, NULL,
1229 						sx150x_irq_thread_fn,
1230 						IRQF_ONESHOT | IRQF_SHARED |
1231 						IRQF_TRIGGER_FALLING,
1232 						client->name, pctl);
1233 		if (ret < 0)
1234 			return ret;
1235 	}
1236 
1237 	ret = devm_gpiochip_add_data(dev, &pctl->gpio, pctl);
1238 	if (ret)
1239 		return ret;
1240 
1241 	/*
1242 	 * Pin control functions need to be enabled AFTER registering the
1243 	 * GPIO chip because sx150x_pinconf_set() calls
1244 	 * sx150x_gpio_direction_output().
1245 	 */
1246 	ret = pinctrl_enable(pctl->pctldev);
1247 	if (ret) {
1248 		dev_err(dev, "Failed to enable pinctrl device\n");
1249 		return ret;
1250 	}
1251 
1252 	ret = gpiochip_add_pin_range(&pctl->gpio, dev_name(dev),
1253 				     0, 0, pctl->data->npins);
1254 	if (ret)
1255 		return ret;
1256 
1257 	return 0;
1258 }
1259 
1260 static struct i2c_driver sx150x_driver = {
1261 	.driver = {
1262 		.name = "sx150x-pinctrl",
1263 		.of_match_table = sx150x_of_match,
1264 	},
1265 	.probe = sx150x_probe,
1266 	.id_table = sx150x_id,
1267 };
1268 
1269 static int __init sx150x_init(void)
1270 {
1271 	return i2c_add_driver(&sx150x_driver);
1272 }
1273 subsys_initcall(sx150x_init);
1274