1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for STMicroelectronics Multi-Function eXpander (STMFX) GPIO expander 4 * 5 * Copyright (C) 2019 STMicroelectronics 6 * Author(s): Amelie Delaunay <amelie.delaunay@st.com>. 7 */ 8 #include <linux/gpio/driver.h> 9 #include <linux/interrupt.h> 10 #include <linux/mfd/stmfx.h> 11 #include <linux/module.h> 12 #include <linux/platform_device.h> 13 #include <linux/seq_file.h> 14 15 #include <linux/pinctrl/pinconf.h> 16 #include <linux/pinctrl/pinmux.h> 17 18 #include "core.h" 19 #include "pinctrl-utils.h" 20 21 /* GPIOs expander */ 22 /* GPIO_STATE1 0x10, GPIO_STATE2 0x11, GPIO_STATE3 0x12 */ 23 #define STMFX_REG_GPIO_STATE STMFX_REG_GPIO_STATE1 /* R */ 24 /* GPIO_DIR1 0x60, GPIO_DIR2 0x61, GPIO_DIR3 0x63 */ 25 #define STMFX_REG_GPIO_DIR STMFX_REG_GPIO_DIR1 /* RW */ 26 /* GPIO_TYPE1 0x64, GPIO_TYPE2 0x65, GPIO_TYPE3 0x66 */ 27 #define STMFX_REG_GPIO_TYPE STMFX_REG_GPIO_TYPE1 /* RW */ 28 /* GPIO_PUPD1 0x68, GPIO_PUPD2 0x69, GPIO_PUPD3 0x6A */ 29 #define STMFX_REG_GPIO_PUPD STMFX_REG_GPIO_PUPD1 /* RW */ 30 /* GPO_SET1 0x6C, GPO_SET2 0x6D, GPO_SET3 0x6E */ 31 #define STMFX_REG_GPO_SET STMFX_REG_GPO_SET1 /* RW */ 32 /* GPO_CLR1 0x70, GPO_CLR2 0x71, GPO_CLR3 0x72 */ 33 #define STMFX_REG_GPO_CLR STMFX_REG_GPO_CLR1 /* RW */ 34 /* IRQ_GPI_SRC1 0x48, IRQ_GPI_SRC2 0x49, IRQ_GPI_SRC3 0x4A */ 35 #define STMFX_REG_IRQ_GPI_SRC STMFX_REG_IRQ_GPI_SRC1 /* RW */ 36 /* IRQ_GPI_EVT1 0x4C, IRQ_GPI_EVT2 0x4D, IRQ_GPI_EVT3 0x4E */ 37 #define STMFX_REG_IRQ_GPI_EVT STMFX_REG_IRQ_GPI_EVT1 /* RW */ 38 /* IRQ_GPI_TYPE1 0x50, IRQ_GPI_TYPE2 0x51, IRQ_GPI_TYPE3 0x52 */ 39 #define STMFX_REG_IRQ_GPI_TYPE STMFX_REG_IRQ_GPI_TYPE1 /* RW */ 40 /* IRQ_GPI_PENDING1 0x0C, IRQ_GPI_PENDING2 0x0D, IRQ_GPI_PENDING3 0x0E*/ 41 #define STMFX_REG_IRQ_GPI_PENDING STMFX_REG_IRQ_GPI_PENDING1 /* R */ 42 /* IRQ_GPI_ACK1 0x54, IRQ_GPI_ACK2 0x55, IRQ_GPI_ACK3 0x56 */ 43 #define STMFX_REG_IRQ_GPI_ACK STMFX_REG_IRQ_GPI_ACK1 /* RW */ 44 45 #define NR_GPIO_REGS 3 46 #define NR_GPIOS_PER_REG 8 47 #define get_reg(offset) ((offset) / NR_GPIOS_PER_REG) 48 #define get_shift(offset) ((offset) % NR_GPIOS_PER_REG) 49 #define get_mask(offset) (BIT(get_shift(offset))) 50 51 /* 52 * STMFX pinctrl can have up to 24 pins if STMFX other functions are not used. 53 * Pins availability is managed thanks to gpio-ranges property. 54 */ 55 static const struct pinctrl_pin_desc stmfx_pins[] = { 56 PINCTRL_PIN(0, "gpio0"), 57 PINCTRL_PIN(1, "gpio1"), 58 PINCTRL_PIN(2, "gpio2"), 59 PINCTRL_PIN(3, "gpio3"), 60 PINCTRL_PIN(4, "gpio4"), 61 PINCTRL_PIN(5, "gpio5"), 62 PINCTRL_PIN(6, "gpio6"), 63 PINCTRL_PIN(7, "gpio7"), 64 PINCTRL_PIN(8, "gpio8"), 65 PINCTRL_PIN(9, "gpio9"), 66 PINCTRL_PIN(10, "gpio10"), 67 PINCTRL_PIN(11, "gpio11"), 68 PINCTRL_PIN(12, "gpio12"), 69 PINCTRL_PIN(13, "gpio13"), 70 PINCTRL_PIN(14, "gpio14"), 71 PINCTRL_PIN(15, "gpio15"), 72 PINCTRL_PIN(16, "agpio0"), 73 PINCTRL_PIN(17, "agpio1"), 74 PINCTRL_PIN(18, "agpio2"), 75 PINCTRL_PIN(19, "agpio3"), 76 PINCTRL_PIN(20, "agpio4"), 77 PINCTRL_PIN(21, "agpio5"), 78 PINCTRL_PIN(22, "agpio6"), 79 PINCTRL_PIN(23, "agpio7"), 80 }; 81 82 struct stmfx_pinctrl { 83 struct device *dev; 84 struct stmfx *stmfx; 85 struct pinctrl_dev *pctl_dev; 86 struct pinctrl_desc pctl_desc; 87 struct gpio_chip gpio_chip; 88 struct irq_chip irq_chip; 89 struct mutex lock; /* IRQ bus lock */ 90 unsigned long gpio_valid_mask; 91 /* Cache of IRQ_GPI_* registers for bus_lock */ 92 u8 irq_gpi_src[NR_GPIO_REGS]; 93 u8 irq_gpi_type[NR_GPIO_REGS]; 94 u8 irq_gpi_evt[NR_GPIO_REGS]; 95 u8 irq_toggle_edge[NR_GPIO_REGS]; 96 #ifdef CONFIG_PM 97 /* Backup of GPIO_* registers for suspend/resume */ 98 u8 bkp_gpio_state[NR_GPIO_REGS]; 99 u8 bkp_gpio_dir[NR_GPIO_REGS]; 100 u8 bkp_gpio_type[NR_GPIO_REGS]; 101 u8 bkp_gpio_pupd[NR_GPIO_REGS]; 102 #endif 103 }; 104 105 static int stmfx_gpio_get(struct gpio_chip *gc, unsigned int offset) 106 { 107 struct stmfx_pinctrl *pctl = gpiochip_get_data(gc); 108 u32 reg = STMFX_REG_GPIO_STATE + get_reg(offset); 109 u32 mask = get_mask(offset); 110 u32 value; 111 int ret; 112 113 ret = regmap_read(pctl->stmfx->map, reg, &value); 114 115 return ret ? ret : !!(value & mask); 116 } 117 118 static void stmfx_gpio_set(struct gpio_chip *gc, unsigned int offset, int value) 119 { 120 struct stmfx_pinctrl *pctl = gpiochip_get_data(gc); 121 u32 reg = value ? STMFX_REG_GPO_SET : STMFX_REG_GPO_CLR; 122 u32 mask = get_mask(offset); 123 124 regmap_write_bits(pctl->stmfx->map, reg + get_reg(offset), 125 mask, mask); 126 } 127 128 static int stmfx_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) 129 { 130 struct stmfx_pinctrl *pctl = gpiochip_get_data(gc); 131 u32 reg = STMFX_REG_GPIO_DIR + get_reg(offset); 132 u32 mask = get_mask(offset); 133 u32 val; 134 int ret; 135 136 ret = regmap_read(pctl->stmfx->map, reg, &val); 137 /* 138 * On stmfx, gpio pins direction is (0)input, (1)output. 139 */ 140 if (ret) 141 return ret; 142 143 if (val & mask) 144 return GPIO_LINE_DIRECTION_OUT; 145 146 return GPIO_LINE_DIRECTION_IN; 147 } 148 149 static int stmfx_gpio_direction_input(struct gpio_chip *gc, unsigned int offset) 150 { 151 struct stmfx_pinctrl *pctl = gpiochip_get_data(gc); 152 u32 reg = STMFX_REG_GPIO_DIR + get_reg(offset); 153 u32 mask = get_mask(offset); 154 155 return regmap_write_bits(pctl->stmfx->map, reg, mask, 0); 156 } 157 158 static int stmfx_gpio_direction_output(struct gpio_chip *gc, 159 unsigned int offset, int value) 160 { 161 struct stmfx_pinctrl *pctl = gpiochip_get_data(gc); 162 u32 reg = STMFX_REG_GPIO_DIR + get_reg(offset); 163 u32 mask = get_mask(offset); 164 165 stmfx_gpio_set(gc, offset, value); 166 167 return regmap_write_bits(pctl->stmfx->map, reg, mask, mask); 168 } 169 170 static int stmfx_pinconf_get_pupd(struct stmfx_pinctrl *pctl, 171 unsigned int offset) 172 { 173 u32 reg = STMFX_REG_GPIO_PUPD + get_reg(offset); 174 u32 pupd, mask = get_mask(offset); 175 int ret; 176 177 ret = regmap_read(pctl->stmfx->map, reg, &pupd); 178 if (ret) 179 return ret; 180 181 return !!(pupd & mask); 182 } 183 184 static int stmfx_pinconf_set_pupd(struct stmfx_pinctrl *pctl, 185 unsigned int offset, u32 pupd) 186 { 187 u32 reg = STMFX_REG_GPIO_PUPD + get_reg(offset); 188 u32 mask = get_mask(offset); 189 190 return regmap_write_bits(pctl->stmfx->map, reg, mask, pupd ? mask : 0); 191 } 192 193 static int stmfx_pinconf_get_type(struct stmfx_pinctrl *pctl, 194 unsigned int offset) 195 { 196 u32 reg = STMFX_REG_GPIO_TYPE + get_reg(offset); 197 u32 type, mask = get_mask(offset); 198 int ret; 199 200 ret = regmap_read(pctl->stmfx->map, reg, &type); 201 if (ret) 202 return ret; 203 204 return !!(type & mask); 205 } 206 207 static int stmfx_pinconf_set_type(struct stmfx_pinctrl *pctl, 208 unsigned int offset, u32 type) 209 { 210 u32 reg = STMFX_REG_GPIO_TYPE + get_reg(offset); 211 u32 mask = get_mask(offset); 212 213 return regmap_write_bits(pctl->stmfx->map, reg, mask, type ? mask : 0); 214 } 215 216 static int stmfx_pinconf_get(struct pinctrl_dev *pctldev, 217 unsigned int pin, unsigned long *config) 218 { 219 struct stmfx_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 220 u32 param = pinconf_to_config_param(*config); 221 struct pinctrl_gpio_range *range; 222 u32 arg = 0; 223 int ret, dir, type, pupd; 224 225 range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin); 226 if (!range) 227 return -EINVAL; 228 229 dir = stmfx_gpio_get_direction(&pctl->gpio_chip, pin); 230 if (dir < 0) 231 return dir; 232 233 /* 234 * Currently the gpiolib IN is 1 and OUT is 0 but let's not count 235 * on it just to be on the safe side also in the future :) 236 */ 237 dir = (dir == GPIO_LINE_DIRECTION_IN) ? 1 : 0; 238 239 type = stmfx_pinconf_get_type(pctl, pin); 240 if (type < 0) 241 return type; 242 pupd = stmfx_pinconf_get_pupd(pctl, pin); 243 if (pupd < 0) 244 return pupd; 245 246 switch (param) { 247 case PIN_CONFIG_BIAS_DISABLE: 248 if ((!dir && (!type || !pupd)) || (dir && !type)) 249 arg = 1; 250 break; 251 case PIN_CONFIG_BIAS_PULL_DOWN: 252 if (dir && type && !pupd) 253 arg = 1; 254 break; 255 case PIN_CONFIG_BIAS_PULL_UP: 256 if (type && pupd) 257 arg = 1; 258 break; 259 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 260 if ((!dir && type) || (dir && !type)) 261 arg = 1; 262 break; 263 case PIN_CONFIG_DRIVE_PUSH_PULL: 264 if ((!dir && !type) || (dir && type)) 265 arg = 1; 266 break; 267 case PIN_CONFIG_OUTPUT: 268 if (dir) 269 return -EINVAL; 270 271 ret = stmfx_gpio_get(&pctl->gpio_chip, pin); 272 if (ret < 0) 273 return ret; 274 275 arg = ret; 276 break; 277 default: 278 return -ENOTSUPP; 279 } 280 281 *config = pinconf_to_config_packed(param, arg); 282 283 return 0; 284 } 285 286 static int stmfx_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 287 unsigned long *configs, unsigned int num_configs) 288 { 289 struct stmfx_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 290 struct pinctrl_gpio_range *range; 291 enum pin_config_param param; 292 u32 arg; 293 int i, ret; 294 295 range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin); 296 if (!range) { 297 dev_err(pctldev->dev, "pin %d is not available\n", pin); 298 return -EINVAL; 299 } 300 301 for (i = 0; i < num_configs; i++) { 302 param = pinconf_to_config_param(configs[i]); 303 arg = pinconf_to_config_argument(configs[i]); 304 305 switch (param) { 306 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: 307 case PIN_CONFIG_BIAS_DISABLE: 308 case PIN_CONFIG_DRIVE_PUSH_PULL: 309 ret = stmfx_pinconf_set_type(pctl, pin, 0); 310 if (ret) 311 return ret; 312 break; 313 case PIN_CONFIG_BIAS_PULL_DOWN: 314 ret = stmfx_pinconf_set_type(pctl, pin, 1); 315 if (ret) 316 return ret; 317 ret = stmfx_pinconf_set_pupd(pctl, pin, 0); 318 if (ret) 319 return ret; 320 break; 321 case PIN_CONFIG_BIAS_PULL_UP: 322 ret = stmfx_pinconf_set_type(pctl, pin, 1); 323 if (ret) 324 return ret; 325 ret = stmfx_pinconf_set_pupd(pctl, pin, 1); 326 if (ret) 327 return ret; 328 break; 329 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 330 ret = stmfx_pinconf_set_type(pctl, pin, 1); 331 if (ret) 332 return ret; 333 break; 334 case PIN_CONFIG_OUTPUT: 335 ret = stmfx_gpio_direction_output(&pctl->gpio_chip, 336 pin, arg); 337 if (ret) 338 return ret; 339 break; 340 default: 341 return -ENOTSUPP; 342 } 343 } 344 345 return 0; 346 } 347 348 static void stmfx_pinconf_dbg_show(struct pinctrl_dev *pctldev, 349 struct seq_file *s, unsigned int offset) 350 { 351 struct stmfx_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 352 struct pinctrl_gpio_range *range; 353 int dir, type, pupd, val; 354 355 range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, offset); 356 if (!range) 357 return; 358 359 dir = stmfx_gpio_get_direction(&pctl->gpio_chip, offset); 360 if (dir < 0) 361 return; 362 type = stmfx_pinconf_get_type(pctl, offset); 363 if (type < 0) 364 return; 365 pupd = stmfx_pinconf_get_pupd(pctl, offset); 366 if (pupd < 0) 367 return; 368 val = stmfx_gpio_get(&pctl->gpio_chip, offset); 369 if (val < 0) 370 return; 371 372 if (dir == GPIO_LINE_DIRECTION_OUT) { 373 seq_printf(s, "output %s ", val ? "high" : "low"); 374 if (type) 375 seq_printf(s, "open drain %s internal pull-up ", 376 pupd ? "with" : "without"); 377 else 378 seq_puts(s, "push pull no pull "); 379 } else { 380 seq_printf(s, "input %s ", val ? "high" : "low"); 381 if (type) 382 seq_printf(s, "with internal pull-%s ", 383 pupd ? "up" : "down"); 384 else 385 seq_printf(s, "%s ", pupd ? "floating" : "analog"); 386 } 387 } 388 389 static const struct pinconf_ops stmfx_pinconf_ops = { 390 .pin_config_get = stmfx_pinconf_get, 391 .pin_config_set = stmfx_pinconf_set, 392 .pin_config_dbg_show = stmfx_pinconf_dbg_show, 393 }; 394 395 static int stmfx_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) 396 { 397 return 0; 398 } 399 400 static const char *stmfx_pinctrl_get_group_name(struct pinctrl_dev *pctldev, 401 unsigned int selector) 402 { 403 return NULL; 404 } 405 406 static int stmfx_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, 407 unsigned int selector, 408 const unsigned int **pins, 409 unsigned int *num_pins) 410 { 411 return -ENOTSUPP; 412 } 413 414 static const struct pinctrl_ops stmfx_pinctrl_ops = { 415 .get_groups_count = stmfx_pinctrl_get_groups_count, 416 .get_group_name = stmfx_pinctrl_get_group_name, 417 .get_group_pins = stmfx_pinctrl_get_group_pins, 418 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, 419 .dt_free_map = pinctrl_utils_free_map, 420 }; 421 422 static void stmfx_pinctrl_irq_mask(struct irq_data *data) 423 { 424 struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data); 425 struct stmfx_pinctrl *pctl = gpiochip_get_data(gpio_chip); 426 u32 reg = get_reg(data->hwirq); 427 u32 mask = get_mask(data->hwirq); 428 429 pctl->irq_gpi_src[reg] &= ~mask; 430 } 431 432 static void stmfx_pinctrl_irq_unmask(struct irq_data *data) 433 { 434 struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data); 435 struct stmfx_pinctrl *pctl = gpiochip_get_data(gpio_chip); 436 u32 reg = get_reg(data->hwirq); 437 u32 mask = get_mask(data->hwirq); 438 439 pctl->irq_gpi_src[reg] |= mask; 440 } 441 442 static int stmfx_pinctrl_irq_set_type(struct irq_data *data, unsigned int type) 443 { 444 struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data); 445 struct stmfx_pinctrl *pctl = gpiochip_get_data(gpio_chip); 446 u32 reg = get_reg(data->hwirq); 447 u32 mask = get_mask(data->hwirq); 448 449 if (type == IRQ_TYPE_NONE) 450 return -EINVAL; 451 452 if (type & IRQ_TYPE_EDGE_BOTH) { 453 pctl->irq_gpi_evt[reg] |= mask; 454 irq_set_handler_locked(data, handle_edge_irq); 455 } else { 456 pctl->irq_gpi_evt[reg] &= ~mask; 457 irq_set_handler_locked(data, handle_level_irq); 458 } 459 460 if ((type & IRQ_TYPE_EDGE_RISING) || (type & IRQ_TYPE_LEVEL_HIGH)) 461 pctl->irq_gpi_type[reg] |= mask; 462 else 463 pctl->irq_gpi_type[reg] &= ~mask; 464 465 /* 466 * In case of (type & IRQ_TYPE_EDGE_BOTH), we need to know current 467 * GPIO value to set the right edge trigger. But in atomic context 468 * here we can't access registers over I2C. That's why (type & 469 * IRQ_TYPE_EDGE_BOTH) will be managed in .irq_sync_unlock. 470 */ 471 472 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) 473 pctl->irq_toggle_edge[reg] |= mask; 474 else 475 pctl->irq_toggle_edge[reg] &= mask; 476 477 return 0; 478 } 479 480 static void stmfx_pinctrl_irq_bus_lock(struct irq_data *data) 481 { 482 struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data); 483 struct stmfx_pinctrl *pctl = gpiochip_get_data(gpio_chip); 484 485 mutex_lock(&pctl->lock); 486 } 487 488 static void stmfx_pinctrl_irq_bus_sync_unlock(struct irq_data *data) 489 { 490 struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data); 491 struct stmfx_pinctrl *pctl = gpiochip_get_data(gpio_chip); 492 u32 reg = get_reg(data->hwirq); 493 u32 mask = get_mask(data->hwirq); 494 495 /* 496 * In case of IRQ_TYPE_EDGE_BOTH), read the current GPIO value 497 * (this couldn't be done in .irq_set_type because of atomic context) 498 * to set the right irq trigger type. 499 */ 500 if (pctl->irq_toggle_edge[reg] & mask) { 501 if (stmfx_gpio_get(gpio_chip, data->hwirq)) 502 pctl->irq_gpi_type[reg] &= ~mask; 503 else 504 pctl->irq_gpi_type[reg] |= mask; 505 } 506 507 regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_EVT, 508 pctl->irq_gpi_evt, NR_GPIO_REGS); 509 regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_TYPE, 510 pctl->irq_gpi_type, NR_GPIO_REGS); 511 regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_SRC, 512 pctl->irq_gpi_src, NR_GPIO_REGS); 513 514 mutex_unlock(&pctl->lock); 515 } 516 517 static int stmfx_gpio_irq_request_resources(struct irq_data *data) 518 { 519 struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data); 520 int ret; 521 522 ret = stmfx_gpio_direction_input(gpio_chip, data->hwirq); 523 if (ret) 524 return ret; 525 526 return gpiochip_reqres_irq(gpio_chip, data->hwirq); 527 } 528 529 static void stmfx_gpio_irq_release_resources(struct irq_data *data) 530 { 531 struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data); 532 533 return gpiochip_relres_irq(gpio_chip, data->hwirq); 534 } 535 536 static void stmfx_pinctrl_irq_toggle_trigger(struct stmfx_pinctrl *pctl, 537 unsigned int offset) 538 { 539 u32 reg = get_reg(offset); 540 u32 mask = get_mask(offset); 541 int val; 542 543 if (!(pctl->irq_toggle_edge[reg] & mask)) 544 return; 545 546 val = stmfx_gpio_get(&pctl->gpio_chip, offset); 547 if (val < 0) 548 return; 549 550 if (val) { 551 pctl->irq_gpi_type[reg] &= mask; 552 regmap_write_bits(pctl->stmfx->map, 553 STMFX_REG_IRQ_GPI_TYPE + reg, 554 mask, 0); 555 556 } else { 557 pctl->irq_gpi_type[reg] |= mask; 558 regmap_write_bits(pctl->stmfx->map, 559 STMFX_REG_IRQ_GPI_TYPE + reg, 560 mask, mask); 561 } 562 } 563 564 static irqreturn_t stmfx_pinctrl_irq_thread_fn(int irq, void *dev_id) 565 { 566 struct stmfx_pinctrl *pctl = (struct stmfx_pinctrl *)dev_id; 567 struct gpio_chip *gc = &pctl->gpio_chip; 568 u8 pending[NR_GPIO_REGS]; 569 u8 src[NR_GPIO_REGS] = {0, 0, 0}; 570 unsigned long n, status; 571 int i, ret; 572 573 ret = regmap_bulk_read(pctl->stmfx->map, STMFX_REG_IRQ_GPI_PENDING, 574 &pending, NR_GPIO_REGS); 575 if (ret) 576 return IRQ_NONE; 577 578 regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_SRC, 579 src, NR_GPIO_REGS); 580 581 BUILD_BUG_ON(NR_GPIO_REGS > sizeof(status)); 582 for (i = 0, status = 0; i < NR_GPIO_REGS; i++) 583 status |= (unsigned long)pending[i] << (i * 8); 584 for_each_set_bit(n, &status, gc->ngpio) { 585 handle_nested_irq(irq_find_mapping(gc->irq.domain, n)); 586 stmfx_pinctrl_irq_toggle_trigger(pctl, n); 587 } 588 589 regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_SRC, 590 pctl->irq_gpi_src, NR_GPIO_REGS); 591 592 return IRQ_HANDLED; 593 } 594 595 static int stmfx_pinctrl_gpio_function_enable(struct stmfx_pinctrl *pctl) 596 { 597 struct pinctrl_gpio_range *gpio_range; 598 struct pinctrl_dev *pctl_dev = pctl->pctl_dev; 599 u32 func = STMFX_FUNC_GPIO; 600 601 pctl->gpio_valid_mask = GENMASK(15, 0); 602 603 gpio_range = pinctrl_find_gpio_range_from_pin(pctl_dev, 16); 604 if (gpio_range) { 605 func |= STMFX_FUNC_ALTGPIO_LOW; 606 pctl->gpio_valid_mask |= GENMASK(19, 16); 607 } 608 609 gpio_range = pinctrl_find_gpio_range_from_pin(pctl_dev, 20); 610 if (gpio_range) { 611 func |= STMFX_FUNC_ALTGPIO_HIGH; 612 pctl->gpio_valid_mask |= GENMASK(23, 20); 613 } 614 615 return stmfx_function_enable(pctl->stmfx, func); 616 } 617 618 static int stmfx_pinctrl_probe(struct platform_device *pdev) 619 { 620 struct stmfx *stmfx = dev_get_drvdata(pdev->dev.parent); 621 struct device_node *np = pdev->dev.of_node; 622 struct stmfx_pinctrl *pctl; 623 struct gpio_irq_chip *girq; 624 int irq, ret; 625 626 pctl = devm_kzalloc(stmfx->dev, sizeof(*pctl), GFP_KERNEL); 627 if (!pctl) 628 return -ENOMEM; 629 630 platform_set_drvdata(pdev, pctl); 631 632 pctl->dev = &pdev->dev; 633 pctl->stmfx = stmfx; 634 635 if (!of_find_property(np, "gpio-ranges", NULL)) { 636 dev_err(pctl->dev, "missing required gpio-ranges property\n"); 637 return -EINVAL; 638 } 639 640 irq = platform_get_irq(pdev, 0); 641 if (irq <= 0) 642 return -ENXIO; 643 644 mutex_init(&pctl->lock); 645 646 /* Register pin controller */ 647 pctl->pctl_desc.name = "stmfx-pinctrl"; 648 pctl->pctl_desc.pctlops = &stmfx_pinctrl_ops; 649 pctl->pctl_desc.confops = &stmfx_pinconf_ops; 650 pctl->pctl_desc.pins = stmfx_pins; 651 pctl->pctl_desc.npins = ARRAY_SIZE(stmfx_pins); 652 pctl->pctl_desc.owner = THIS_MODULE; 653 pctl->pctl_desc.link_consumers = true; 654 655 ret = devm_pinctrl_register_and_init(pctl->dev, &pctl->pctl_desc, 656 pctl, &pctl->pctl_dev); 657 if (ret) { 658 dev_err(pctl->dev, "pinctrl registration failed\n"); 659 return ret; 660 } 661 662 ret = pinctrl_enable(pctl->pctl_dev); 663 if (ret) { 664 dev_err(pctl->dev, "pinctrl enable failed\n"); 665 return ret; 666 } 667 668 /* Register gpio controller */ 669 pctl->gpio_chip.label = "stmfx-gpio"; 670 pctl->gpio_chip.parent = pctl->dev; 671 pctl->gpio_chip.get_direction = stmfx_gpio_get_direction; 672 pctl->gpio_chip.direction_input = stmfx_gpio_direction_input; 673 pctl->gpio_chip.direction_output = stmfx_gpio_direction_output; 674 pctl->gpio_chip.get = stmfx_gpio_get; 675 pctl->gpio_chip.set = stmfx_gpio_set; 676 pctl->gpio_chip.set_config = gpiochip_generic_config; 677 pctl->gpio_chip.base = -1; 678 pctl->gpio_chip.ngpio = pctl->pctl_desc.npins; 679 pctl->gpio_chip.can_sleep = true; 680 681 pctl->irq_chip.name = dev_name(pctl->dev); 682 pctl->irq_chip.irq_mask = stmfx_pinctrl_irq_mask; 683 pctl->irq_chip.irq_unmask = stmfx_pinctrl_irq_unmask; 684 pctl->irq_chip.irq_set_type = stmfx_pinctrl_irq_set_type; 685 pctl->irq_chip.irq_bus_lock = stmfx_pinctrl_irq_bus_lock; 686 pctl->irq_chip.irq_bus_sync_unlock = stmfx_pinctrl_irq_bus_sync_unlock; 687 pctl->irq_chip.irq_request_resources = stmfx_gpio_irq_request_resources; 688 pctl->irq_chip.irq_release_resources = stmfx_gpio_irq_release_resources; 689 690 girq = &pctl->gpio_chip.irq; 691 girq->chip = &pctl->irq_chip; 692 /* This will let us handle the parent IRQ in the driver */ 693 girq->parent_handler = NULL; 694 girq->num_parents = 0; 695 girq->parents = NULL; 696 girq->default_type = IRQ_TYPE_NONE; 697 girq->handler = handle_bad_irq; 698 girq->threaded = true; 699 700 ret = devm_gpiochip_add_data(pctl->dev, &pctl->gpio_chip, pctl); 701 if (ret) { 702 dev_err(pctl->dev, "gpio_chip registration failed\n"); 703 return ret; 704 } 705 706 ret = stmfx_pinctrl_gpio_function_enable(pctl); 707 if (ret) 708 return ret; 709 710 ret = devm_request_threaded_irq(pctl->dev, irq, NULL, 711 stmfx_pinctrl_irq_thread_fn, 712 IRQF_ONESHOT, 713 pctl->irq_chip.name, pctl); 714 if (ret) { 715 dev_err(pctl->dev, "cannot request irq%d\n", irq); 716 return ret; 717 } 718 719 dev_info(pctl->dev, 720 "%ld GPIOs available\n", hweight_long(pctl->gpio_valid_mask)); 721 722 return 0; 723 } 724 725 static int stmfx_pinctrl_remove(struct platform_device *pdev) 726 { 727 struct stmfx *stmfx = dev_get_drvdata(pdev->dev.parent); 728 729 return stmfx_function_disable(stmfx, 730 STMFX_FUNC_GPIO | 731 STMFX_FUNC_ALTGPIO_LOW | 732 STMFX_FUNC_ALTGPIO_HIGH); 733 } 734 735 #ifdef CONFIG_PM_SLEEP 736 static int stmfx_pinctrl_backup_regs(struct stmfx_pinctrl *pctl) 737 { 738 int ret; 739 740 ret = regmap_bulk_read(pctl->stmfx->map, STMFX_REG_GPIO_STATE, 741 &pctl->bkp_gpio_state, NR_GPIO_REGS); 742 if (ret) 743 return ret; 744 ret = regmap_bulk_read(pctl->stmfx->map, STMFX_REG_GPIO_DIR, 745 &pctl->bkp_gpio_dir, NR_GPIO_REGS); 746 if (ret) 747 return ret; 748 ret = regmap_bulk_read(pctl->stmfx->map, STMFX_REG_GPIO_TYPE, 749 &pctl->bkp_gpio_type, NR_GPIO_REGS); 750 if (ret) 751 return ret; 752 ret = regmap_bulk_read(pctl->stmfx->map, STMFX_REG_GPIO_PUPD, 753 &pctl->bkp_gpio_pupd, NR_GPIO_REGS); 754 if (ret) 755 return ret; 756 757 return 0; 758 } 759 760 static int stmfx_pinctrl_restore_regs(struct stmfx_pinctrl *pctl) 761 { 762 int ret; 763 764 ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_GPIO_DIR, 765 pctl->bkp_gpio_dir, NR_GPIO_REGS); 766 if (ret) 767 return ret; 768 ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_GPIO_TYPE, 769 pctl->bkp_gpio_type, NR_GPIO_REGS); 770 if (ret) 771 return ret; 772 ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_GPIO_PUPD, 773 pctl->bkp_gpio_pupd, NR_GPIO_REGS); 774 if (ret) 775 return ret; 776 ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_GPO_SET, 777 pctl->bkp_gpio_state, NR_GPIO_REGS); 778 if (ret) 779 return ret; 780 ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_EVT, 781 pctl->irq_gpi_evt, NR_GPIO_REGS); 782 if (ret) 783 return ret; 784 ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_TYPE, 785 pctl->irq_gpi_type, NR_GPIO_REGS); 786 if (ret) 787 return ret; 788 ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_SRC, 789 pctl->irq_gpi_src, NR_GPIO_REGS); 790 if (ret) 791 return ret; 792 793 return 0; 794 } 795 796 static int stmfx_pinctrl_suspend(struct device *dev) 797 { 798 struct stmfx_pinctrl *pctl = dev_get_drvdata(dev); 799 int ret; 800 801 ret = stmfx_pinctrl_backup_regs(pctl); 802 if (ret) { 803 dev_err(pctl->dev, "registers backup failure\n"); 804 return ret; 805 } 806 807 return 0; 808 } 809 810 static int stmfx_pinctrl_resume(struct device *dev) 811 { 812 struct stmfx_pinctrl *pctl = dev_get_drvdata(dev); 813 int ret; 814 815 ret = stmfx_pinctrl_restore_regs(pctl); 816 if (ret) { 817 dev_err(pctl->dev, "registers restoration failure\n"); 818 return ret; 819 } 820 821 return 0; 822 } 823 #endif 824 825 static SIMPLE_DEV_PM_OPS(stmfx_pinctrl_dev_pm_ops, 826 stmfx_pinctrl_suspend, stmfx_pinctrl_resume); 827 828 static const struct of_device_id stmfx_pinctrl_of_match[] = { 829 { .compatible = "st,stmfx-0300-pinctrl", }, 830 {}, 831 }; 832 MODULE_DEVICE_TABLE(of, stmfx_pinctrl_of_match); 833 834 static struct platform_driver stmfx_pinctrl_driver = { 835 .driver = { 836 .name = "stmfx-pinctrl", 837 .of_match_table = stmfx_pinctrl_of_match, 838 .pm = &stmfx_pinctrl_dev_pm_ops, 839 }, 840 .probe = stmfx_pinctrl_probe, 841 .remove = stmfx_pinctrl_remove, 842 }; 843 module_platform_driver(stmfx_pinctrl_driver); 844 845 MODULE_DESCRIPTION("STMFX pinctrl/GPIO driver"); 846 MODULE_AUTHOR("Amelie Delaunay <amelie.delaunay@st.com>"); 847 MODULE_LICENSE("GPL v2"); 848