1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2013 STMicroelectronics (R&D) Limited. 4 * Authors: 5 * Srinivas Kandagatla <srinivas.kandagatla@st.com> 6 */ 7 8 #include <linux/init.h> 9 #include <linux/module.h> 10 #include <linux/slab.h> 11 #include <linux/err.h> 12 #include <linux/io.h> 13 #include <linux/of.h> 14 #include <linux/of_irq.h> 15 #include <linux/of_gpio.h> /* of_get_named_gpio() */ 16 #include <linux/of_address.h> 17 #include <linux/gpio/driver.h> 18 #include <linux/regmap.h> 19 #include <linux/mfd/syscon.h> 20 #include <linux/pinctrl/pinctrl.h> 21 #include <linux/pinctrl/pinmux.h> 22 #include <linux/pinctrl/pinconf.h> 23 #include <linux/platform_device.h> 24 #include "core.h" 25 26 /* PIO Block registers */ 27 /* PIO output */ 28 #define REG_PIO_POUT 0x00 29 /* Set bits of POUT */ 30 #define REG_PIO_SET_POUT 0x04 31 /* Clear bits of POUT */ 32 #define REG_PIO_CLR_POUT 0x08 33 /* PIO input */ 34 #define REG_PIO_PIN 0x10 35 /* PIO configuration */ 36 #define REG_PIO_PC(n) (0x20 + (n) * 0x10) 37 /* Set bits of PC[2:0] */ 38 #define REG_PIO_SET_PC(n) (0x24 + (n) * 0x10) 39 /* Clear bits of PC[2:0] */ 40 #define REG_PIO_CLR_PC(n) (0x28 + (n) * 0x10) 41 /* PIO input comparison */ 42 #define REG_PIO_PCOMP 0x50 43 /* Set bits of PCOMP */ 44 #define REG_PIO_SET_PCOMP 0x54 45 /* Clear bits of PCOMP */ 46 #define REG_PIO_CLR_PCOMP 0x58 47 /* PIO input comparison mask */ 48 #define REG_PIO_PMASK 0x60 49 /* Set bits of PMASK */ 50 #define REG_PIO_SET_PMASK 0x64 51 /* Clear bits of PMASK */ 52 #define REG_PIO_CLR_PMASK 0x68 53 54 #define ST_GPIO_DIRECTION_BIDIR 0x1 55 #define ST_GPIO_DIRECTION_OUT 0x2 56 #define ST_GPIO_DIRECTION_IN 0x4 57 58 /** 59 * Packed style retime configuration. 60 * There are two registers cfg0 and cfg1 in this style for each bank. 61 * Each field in this register is 8 bit corresponding to 8 pins in the bank. 62 */ 63 #define RT_P_CFGS_PER_BANK 2 64 #define RT_P_CFG0_CLK1NOTCLK0_FIELD(reg) REG_FIELD(reg, 0, 7) 65 #define RT_P_CFG0_DELAY_0_FIELD(reg) REG_FIELD(reg, 16, 23) 66 #define RT_P_CFG0_DELAY_1_FIELD(reg) REG_FIELD(reg, 24, 31) 67 #define RT_P_CFG1_INVERTCLK_FIELD(reg) REG_FIELD(reg, 0, 7) 68 #define RT_P_CFG1_RETIME_FIELD(reg) REG_FIELD(reg, 8, 15) 69 #define RT_P_CFG1_CLKNOTDATA_FIELD(reg) REG_FIELD(reg, 16, 23) 70 #define RT_P_CFG1_DOUBLE_EDGE_FIELD(reg) REG_FIELD(reg, 24, 31) 71 72 /** 73 * Dedicated style retime Configuration register 74 * each register is dedicated per pin. 75 */ 76 #define RT_D_CFGS_PER_BANK 8 77 #define RT_D_CFG_CLK_SHIFT 0 78 #define RT_D_CFG_CLK_MASK (0x3 << 0) 79 #define RT_D_CFG_CLKNOTDATA_SHIFT 2 80 #define RT_D_CFG_CLKNOTDATA_MASK BIT(2) 81 #define RT_D_CFG_DELAY_SHIFT 3 82 #define RT_D_CFG_DELAY_MASK (0xf << 3) 83 #define RT_D_CFG_DELAY_INNOTOUT_SHIFT 7 84 #define RT_D_CFG_DELAY_INNOTOUT_MASK BIT(7) 85 #define RT_D_CFG_DOUBLE_EDGE_SHIFT 8 86 #define RT_D_CFG_DOUBLE_EDGE_MASK BIT(8) 87 #define RT_D_CFG_INVERTCLK_SHIFT 9 88 #define RT_D_CFG_INVERTCLK_MASK BIT(9) 89 #define RT_D_CFG_RETIME_SHIFT 10 90 #define RT_D_CFG_RETIME_MASK BIT(10) 91 92 /* 93 * Pinconf is represented in an opaque unsigned long variable. 94 * Below is the bit allocation details for each possible configuration. 95 * All the bit fields can be encapsulated into four variables 96 * (direction, retime-type, retime-clk, retime-delay) 97 * 98 * +----------------+ 99 *[31:28]| reserved-3 | 100 * +----------------+------------- 101 *[27] | oe | | 102 * +----------------+ v 103 *[26] | pu | [Direction ] 104 * +----------------+ ^ 105 *[25] | od | | 106 * +----------------+------------- 107 *[24] | reserved-2 | 108 * +----------------+------------- 109 *[23] | retime | | 110 * +----------------+ | 111 *[22] | retime-invclk | | 112 * +----------------+ v 113 *[21] |retime-clknotdat| [Retime-type ] 114 * +----------------+ ^ 115 *[20] | retime-de | | 116 * +----------------+------------- 117 *[19:18]| retime-clk |------>[Retime-Clk ] 118 * +----------------+ 119 *[17:16]| reserved-1 | 120 * +----------------+ 121 *[15..0]| retime-delay |------>[Retime Delay] 122 * +----------------+ 123 */ 124 125 #define ST_PINCONF_UNPACK(conf, param)\ 126 ((conf >> ST_PINCONF_ ##param ##_SHIFT) \ 127 & ST_PINCONF_ ##param ##_MASK) 128 129 #define ST_PINCONF_PACK(conf, val, param) (conf |=\ 130 ((val & ST_PINCONF_ ##param ##_MASK) << \ 131 ST_PINCONF_ ##param ##_SHIFT)) 132 133 /* Output enable */ 134 #define ST_PINCONF_OE_MASK 0x1 135 #define ST_PINCONF_OE_SHIFT 27 136 #define ST_PINCONF_OE BIT(27) 137 #define ST_PINCONF_UNPACK_OE(conf) ST_PINCONF_UNPACK(conf, OE) 138 #define ST_PINCONF_PACK_OE(conf) ST_PINCONF_PACK(conf, 1, OE) 139 140 /* Pull Up */ 141 #define ST_PINCONF_PU_MASK 0x1 142 #define ST_PINCONF_PU_SHIFT 26 143 #define ST_PINCONF_PU BIT(26) 144 #define ST_PINCONF_UNPACK_PU(conf) ST_PINCONF_UNPACK(conf, PU) 145 #define ST_PINCONF_PACK_PU(conf) ST_PINCONF_PACK(conf, 1, PU) 146 147 /* Open Drain */ 148 #define ST_PINCONF_OD_MASK 0x1 149 #define ST_PINCONF_OD_SHIFT 25 150 #define ST_PINCONF_OD BIT(25) 151 #define ST_PINCONF_UNPACK_OD(conf) ST_PINCONF_UNPACK(conf, OD) 152 #define ST_PINCONF_PACK_OD(conf) ST_PINCONF_PACK(conf, 1, OD) 153 154 #define ST_PINCONF_RT_MASK 0x1 155 #define ST_PINCONF_RT_SHIFT 23 156 #define ST_PINCONF_RT BIT(23) 157 #define ST_PINCONF_UNPACK_RT(conf) ST_PINCONF_UNPACK(conf, RT) 158 #define ST_PINCONF_PACK_RT(conf) ST_PINCONF_PACK(conf, 1, RT) 159 160 #define ST_PINCONF_RT_INVERTCLK_MASK 0x1 161 #define ST_PINCONF_RT_INVERTCLK_SHIFT 22 162 #define ST_PINCONF_RT_INVERTCLK BIT(22) 163 #define ST_PINCONF_UNPACK_RT_INVERTCLK(conf) \ 164 ST_PINCONF_UNPACK(conf, RT_INVERTCLK) 165 #define ST_PINCONF_PACK_RT_INVERTCLK(conf) \ 166 ST_PINCONF_PACK(conf, 1, RT_INVERTCLK) 167 168 #define ST_PINCONF_RT_CLKNOTDATA_MASK 0x1 169 #define ST_PINCONF_RT_CLKNOTDATA_SHIFT 21 170 #define ST_PINCONF_RT_CLKNOTDATA BIT(21) 171 #define ST_PINCONF_UNPACK_RT_CLKNOTDATA(conf) \ 172 ST_PINCONF_UNPACK(conf, RT_CLKNOTDATA) 173 #define ST_PINCONF_PACK_RT_CLKNOTDATA(conf) \ 174 ST_PINCONF_PACK(conf, 1, RT_CLKNOTDATA) 175 176 #define ST_PINCONF_RT_DOUBLE_EDGE_MASK 0x1 177 #define ST_PINCONF_RT_DOUBLE_EDGE_SHIFT 20 178 #define ST_PINCONF_RT_DOUBLE_EDGE BIT(20) 179 #define ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(conf) \ 180 ST_PINCONF_UNPACK(conf, RT_DOUBLE_EDGE) 181 #define ST_PINCONF_PACK_RT_DOUBLE_EDGE(conf) \ 182 ST_PINCONF_PACK(conf, 1, RT_DOUBLE_EDGE) 183 184 #define ST_PINCONF_RT_CLK_MASK 0x3 185 #define ST_PINCONF_RT_CLK_SHIFT 18 186 #define ST_PINCONF_RT_CLK BIT(18) 187 #define ST_PINCONF_UNPACK_RT_CLK(conf) ST_PINCONF_UNPACK(conf, RT_CLK) 188 #define ST_PINCONF_PACK_RT_CLK(conf, val) ST_PINCONF_PACK(conf, val, RT_CLK) 189 190 /* RETIME_DELAY in Pico Secs */ 191 #define ST_PINCONF_RT_DELAY_MASK 0xffff 192 #define ST_PINCONF_RT_DELAY_SHIFT 0 193 #define ST_PINCONF_UNPACK_RT_DELAY(conf) ST_PINCONF_UNPACK(conf, RT_DELAY) 194 #define ST_PINCONF_PACK_RT_DELAY(conf, val) \ 195 ST_PINCONF_PACK(conf, val, RT_DELAY) 196 197 #define ST_GPIO_PINS_PER_BANK (8) 198 #define OF_GPIO_ARGS_MIN (4) 199 #define OF_RT_ARGS_MIN (2) 200 201 #define gpio_range_to_bank(chip) \ 202 container_of(chip, struct st_gpio_bank, range) 203 204 #define pc_to_bank(pc) \ 205 container_of(pc, struct st_gpio_bank, pc) 206 207 enum st_retime_style { 208 st_retime_style_none, 209 st_retime_style_packed, 210 st_retime_style_dedicated, 211 }; 212 213 struct st_retime_dedicated { 214 struct regmap_field *rt[ST_GPIO_PINS_PER_BANK]; 215 }; 216 217 struct st_retime_packed { 218 struct regmap_field *clk1notclk0; 219 struct regmap_field *delay_0; 220 struct regmap_field *delay_1; 221 struct regmap_field *invertclk; 222 struct regmap_field *retime; 223 struct regmap_field *clknotdata; 224 struct regmap_field *double_edge; 225 }; 226 227 struct st_pio_control { 228 u32 rt_pin_mask; 229 struct regmap_field *alt, *oe, *pu, *od; 230 /* retiming */ 231 union { 232 struct st_retime_packed rt_p; 233 struct st_retime_dedicated rt_d; 234 } rt; 235 }; 236 237 struct st_pctl_data { 238 const enum st_retime_style rt_style; 239 const unsigned int *input_delays; 240 const int ninput_delays; 241 const unsigned int *output_delays; 242 const int noutput_delays; 243 /* register offset information */ 244 const int alt, oe, pu, od, rt; 245 }; 246 247 struct st_pinconf { 248 int pin; 249 const char *name; 250 unsigned long config; 251 int altfunc; 252 }; 253 254 struct st_pmx_func { 255 const char *name; 256 const char **groups; 257 unsigned ngroups; 258 }; 259 260 struct st_pctl_group { 261 const char *name; 262 unsigned int *pins; 263 unsigned npins; 264 struct st_pinconf *pin_conf; 265 }; 266 267 /* 268 * Edge triggers are not supported at hardware level, it is supported by 269 * software by exploiting the level trigger support in hardware. 270 * Software uses a virtual register (EDGE_CONF) for edge trigger configuration 271 * of each gpio pin in a GPIO bank. 272 * 273 * Each bank has a 32 bit EDGE_CONF register which is divided in to 8 parts of 274 * 4-bits. Each 4-bit space is allocated for each pin in a gpio bank. 275 * 276 * bit allocation per pin is: 277 * Bits: [0 - 3] | [4 - 7] [8 - 11] ... ... ... ... [ 28 - 31] 278 * -------------------------------------------------------- 279 * | pin-0 | pin-2 | pin-3 | ... ... ... ... | pin -7 | 280 * -------------------------------------------------------- 281 * 282 * A pin can have one of following the values in its edge configuration field. 283 * 284 * ------- ---------------------------- 285 * [0-3] - Description 286 * ------- ---------------------------- 287 * 0000 - No edge IRQ. 288 * 0001 - Falling edge IRQ. 289 * 0010 - Rising edge IRQ. 290 * 0011 - Rising and Falling edge IRQ. 291 * ------- ---------------------------- 292 */ 293 294 #define ST_IRQ_EDGE_CONF_BITS_PER_PIN 4 295 #define ST_IRQ_EDGE_MASK 0xf 296 #define ST_IRQ_EDGE_FALLING BIT(0) 297 #define ST_IRQ_EDGE_RISING BIT(1) 298 #define ST_IRQ_EDGE_BOTH (BIT(0) | BIT(1)) 299 300 #define ST_IRQ_RISING_EDGE_CONF(pin) \ 301 (ST_IRQ_EDGE_RISING << (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN)) 302 303 #define ST_IRQ_FALLING_EDGE_CONF(pin) \ 304 (ST_IRQ_EDGE_FALLING << (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN)) 305 306 #define ST_IRQ_BOTH_EDGE_CONF(pin) \ 307 (ST_IRQ_EDGE_BOTH << (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN)) 308 309 #define ST_IRQ_EDGE_CONF(conf, pin) \ 310 (conf >> (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN) & ST_IRQ_EDGE_MASK) 311 312 struct st_gpio_bank { 313 struct gpio_chip gpio_chip; 314 struct pinctrl_gpio_range range; 315 void __iomem *base; 316 struct st_pio_control pc; 317 unsigned long irq_edge_conf; 318 spinlock_t lock; 319 }; 320 321 struct st_pinctrl { 322 struct device *dev; 323 struct pinctrl_dev *pctl; 324 struct st_gpio_bank *banks; 325 int nbanks; 326 struct st_pmx_func *functions; 327 int nfunctions; 328 struct st_pctl_group *groups; 329 int ngroups; 330 struct regmap *regmap; 331 const struct st_pctl_data *data; 332 void __iomem *irqmux_base; 333 }; 334 335 /* SOC specific data */ 336 337 static const unsigned int stih407_delays[] = {0, 300, 500, 750, 1000, 1250, 338 1500, 1750, 2000, 2250, 2500, 2750, 3000, 3250 }; 339 340 static const struct st_pctl_data stih407_data = { 341 .rt_style = st_retime_style_dedicated, 342 .input_delays = stih407_delays, 343 .ninput_delays = ARRAY_SIZE(stih407_delays), 344 .output_delays = stih407_delays, 345 .noutput_delays = ARRAY_SIZE(stih407_delays), 346 .alt = 0, .oe = 40, .pu = 50, .od = 60, .rt = 100, 347 }; 348 349 static const struct st_pctl_data stih407_flashdata = { 350 .rt_style = st_retime_style_none, 351 .input_delays = stih407_delays, 352 .ninput_delays = ARRAY_SIZE(stih407_delays), 353 .output_delays = stih407_delays, 354 .noutput_delays = ARRAY_SIZE(stih407_delays), 355 .alt = 0, 356 .oe = -1, /* Not Available */ 357 .pu = -1, /* Not Available */ 358 .od = 60, 359 .rt = 100, 360 }; 361 362 static struct st_pio_control *st_get_pio_control( 363 struct pinctrl_dev *pctldev, int pin) 364 { 365 struct pinctrl_gpio_range *range = 366 pinctrl_find_gpio_range_from_pin(pctldev, pin); 367 struct st_gpio_bank *bank = gpio_range_to_bank(range); 368 369 return &bank->pc; 370 } 371 372 /* Low level functions.. */ 373 static inline int st_gpio_bank(int gpio) 374 { 375 return gpio/ST_GPIO_PINS_PER_BANK; 376 } 377 378 static inline int st_gpio_pin(int gpio) 379 { 380 return gpio%ST_GPIO_PINS_PER_BANK; 381 } 382 383 static void st_pinconf_set_config(struct st_pio_control *pc, 384 int pin, unsigned long config) 385 { 386 struct regmap_field *output_enable = pc->oe; 387 struct regmap_field *pull_up = pc->pu; 388 struct regmap_field *open_drain = pc->od; 389 unsigned int oe_value, pu_value, od_value; 390 unsigned long mask = BIT(pin); 391 392 if (output_enable) { 393 regmap_field_read(output_enable, &oe_value); 394 oe_value &= ~mask; 395 if (config & ST_PINCONF_OE) 396 oe_value |= mask; 397 regmap_field_write(output_enable, oe_value); 398 } 399 400 if (pull_up) { 401 regmap_field_read(pull_up, &pu_value); 402 pu_value &= ~mask; 403 if (config & ST_PINCONF_PU) 404 pu_value |= mask; 405 regmap_field_write(pull_up, pu_value); 406 } 407 408 if (open_drain) { 409 regmap_field_read(open_drain, &od_value); 410 od_value &= ~mask; 411 if (config & ST_PINCONF_OD) 412 od_value |= mask; 413 regmap_field_write(open_drain, od_value); 414 } 415 } 416 417 static void st_pctl_set_function(struct st_pio_control *pc, 418 int pin_id, int function) 419 { 420 struct regmap_field *alt = pc->alt; 421 unsigned int val; 422 int pin = st_gpio_pin(pin_id); 423 int offset = pin * 4; 424 425 if (!alt) 426 return; 427 428 regmap_field_read(alt, &val); 429 val &= ~(0xf << offset); 430 val |= function << offset; 431 regmap_field_write(alt, val); 432 } 433 434 static unsigned int st_pctl_get_pin_function(struct st_pio_control *pc, int pin) 435 { 436 struct regmap_field *alt = pc->alt; 437 unsigned int val; 438 int offset = pin * 4; 439 440 if (!alt) 441 return 0; 442 443 regmap_field_read(alt, &val); 444 445 return (val >> offset) & 0xf; 446 } 447 448 static unsigned long st_pinconf_delay_to_bit(unsigned int delay, 449 const struct st_pctl_data *data, unsigned long config) 450 { 451 const unsigned int *delay_times; 452 int num_delay_times, i, closest_index = -1; 453 unsigned int closest_divergence = UINT_MAX; 454 455 if (ST_PINCONF_UNPACK_OE(config)) { 456 delay_times = data->output_delays; 457 num_delay_times = data->noutput_delays; 458 } else { 459 delay_times = data->input_delays; 460 num_delay_times = data->ninput_delays; 461 } 462 463 for (i = 0; i < num_delay_times; i++) { 464 unsigned int divergence = abs(delay - delay_times[i]); 465 466 if (divergence == 0) 467 return i; 468 469 if (divergence < closest_divergence) { 470 closest_divergence = divergence; 471 closest_index = i; 472 } 473 } 474 475 pr_warn("Attempt to set delay %d, closest available %d\n", 476 delay, delay_times[closest_index]); 477 478 return closest_index; 479 } 480 481 static unsigned long st_pinconf_bit_to_delay(unsigned int index, 482 const struct st_pctl_data *data, unsigned long output) 483 { 484 const unsigned int *delay_times; 485 int num_delay_times; 486 487 if (output) { 488 delay_times = data->output_delays; 489 num_delay_times = data->noutput_delays; 490 } else { 491 delay_times = data->input_delays; 492 num_delay_times = data->ninput_delays; 493 } 494 495 if (index < num_delay_times) { 496 return delay_times[index]; 497 } else { 498 pr_warn("Delay not found in/out delay list\n"); 499 return 0; 500 } 501 } 502 503 static void st_regmap_field_bit_set_clear_pin(struct regmap_field *field, 504 int enable, int pin) 505 { 506 unsigned int val = 0; 507 508 regmap_field_read(field, &val); 509 if (enable) 510 val |= BIT(pin); 511 else 512 val &= ~BIT(pin); 513 regmap_field_write(field, val); 514 } 515 516 static void st_pinconf_set_retime_packed(struct st_pinctrl *info, 517 struct st_pio_control *pc, unsigned long config, int pin) 518 { 519 const struct st_pctl_data *data = info->data; 520 struct st_retime_packed *rt_p = &pc->rt.rt_p; 521 unsigned int delay; 522 523 st_regmap_field_bit_set_clear_pin(rt_p->clk1notclk0, 524 ST_PINCONF_UNPACK_RT_CLK(config), pin); 525 526 st_regmap_field_bit_set_clear_pin(rt_p->clknotdata, 527 ST_PINCONF_UNPACK_RT_CLKNOTDATA(config), pin); 528 529 st_regmap_field_bit_set_clear_pin(rt_p->double_edge, 530 ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(config), pin); 531 532 st_regmap_field_bit_set_clear_pin(rt_p->invertclk, 533 ST_PINCONF_UNPACK_RT_INVERTCLK(config), pin); 534 535 st_regmap_field_bit_set_clear_pin(rt_p->retime, 536 ST_PINCONF_UNPACK_RT(config), pin); 537 538 delay = st_pinconf_delay_to_bit(ST_PINCONF_UNPACK_RT_DELAY(config), 539 data, config); 540 /* 2 bit delay, lsb */ 541 st_regmap_field_bit_set_clear_pin(rt_p->delay_0, delay & 0x1, pin); 542 /* 2 bit delay, msb */ 543 st_regmap_field_bit_set_clear_pin(rt_p->delay_1, delay & 0x2, pin); 544 } 545 546 static void st_pinconf_set_retime_dedicated(struct st_pinctrl *info, 547 struct st_pio_control *pc, unsigned long config, int pin) 548 { 549 int input = ST_PINCONF_UNPACK_OE(config) ? 0 : 1; 550 int clk = ST_PINCONF_UNPACK_RT_CLK(config); 551 int clknotdata = ST_PINCONF_UNPACK_RT_CLKNOTDATA(config); 552 int double_edge = ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(config); 553 int invertclk = ST_PINCONF_UNPACK_RT_INVERTCLK(config); 554 int retime = ST_PINCONF_UNPACK_RT(config); 555 556 unsigned long delay = st_pinconf_delay_to_bit( 557 ST_PINCONF_UNPACK_RT_DELAY(config), 558 info->data, config); 559 struct st_retime_dedicated *rt_d = &pc->rt.rt_d; 560 561 unsigned long retime_config = 562 ((clk) << RT_D_CFG_CLK_SHIFT) | 563 ((delay) << RT_D_CFG_DELAY_SHIFT) | 564 ((input) << RT_D_CFG_DELAY_INNOTOUT_SHIFT) | 565 ((retime) << RT_D_CFG_RETIME_SHIFT) | 566 ((clknotdata) << RT_D_CFG_CLKNOTDATA_SHIFT) | 567 ((invertclk) << RT_D_CFG_INVERTCLK_SHIFT) | 568 ((double_edge) << RT_D_CFG_DOUBLE_EDGE_SHIFT); 569 570 regmap_field_write(rt_d->rt[pin], retime_config); 571 } 572 573 static void st_pinconf_get_direction(struct st_pio_control *pc, 574 int pin, unsigned long *config) 575 { 576 unsigned int oe_value, pu_value, od_value; 577 578 if (pc->oe) { 579 regmap_field_read(pc->oe, &oe_value); 580 if (oe_value & BIT(pin)) 581 ST_PINCONF_PACK_OE(*config); 582 } 583 584 if (pc->pu) { 585 regmap_field_read(pc->pu, &pu_value); 586 if (pu_value & BIT(pin)) 587 ST_PINCONF_PACK_PU(*config); 588 } 589 590 if (pc->od) { 591 regmap_field_read(pc->od, &od_value); 592 if (od_value & BIT(pin)) 593 ST_PINCONF_PACK_OD(*config); 594 } 595 } 596 597 static int st_pinconf_get_retime_packed(struct st_pinctrl *info, 598 struct st_pio_control *pc, int pin, unsigned long *config) 599 { 600 const struct st_pctl_data *data = info->data; 601 struct st_retime_packed *rt_p = &pc->rt.rt_p; 602 unsigned int delay_bits, delay, delay0, delay1, val; 603 int output = ST_PINCONF_UNPACK_OE(*config); 604 605 if (!regmap_field_read(rt_p->retime, &val) && (val & BIT(pin))) 606 ST_PINCONF_PACK_RT(*config); 607 608 if (!regmap_field_read(rt_p->clk1notclk0, &val) && (val & BIT(pin))) 609 ST_PINCONF_PACK_RT_CLK(*config, 1); 610 611 if (!regmap_field_read(rt_p->clknotdata, &val) && (val & BIT(pin))) 612 ST_PINCONF_PACK_RT_CLKNOTDATA(*config); 613 614 if (!regmap_field_read(rt_p->double_edge, &val) && (val & BIT(pin))) 615 ST_PINCONF_PACK_RT_DOUBLE_EDGE(*config); 616 617 if (!regmap_field_read(rt_p->invertclk, &val) && (val & BIT(pin))) 618 ST_PINCONF_PACK_RT_INVERTCLK(*config); 619 620 regmap_field_read(rt_p->delay_0, &delay0); 621 regmap_field_read(rt_p->delay_1, &delay1); 622 delay_bits = (((delay1 & BIT(pin)) ? 1 : 0) << 1) | 623 (((delay0 & BIT(pin)) ? 1 : 0)); 624 delay = st_pinconf_bit_to_delay(delay_bits, data, output); 625 ST_PINCONF_PACK_RT_DELAY(*config, delay); 626 627 return 0; 628 } 629 630 static int st_pinconf_get_retime_dedicated(struct st_pinctrl *info, 631 struct st_pio_control *pc, int pin, unsigned long *config) 632 { 633 unsigned int value; 634 unsigned long delay_bits, delay, rt_clk; 635 int output = ST_PINCONF_UNPACK_OE(*config); 636 struct st_retime_dedicated *rt_d = &pc->rt.rt_d; 637 638 regmap_field_read(rt_d->rt[pin], &value); 639 640 rt_clk = (value & RT_D_CFG_CLK_MASK) >> RT_D_CFG_CLK_SHIFT; 641 ST_PINCONF_PACK_RT_CLK(*config, rt_clk); 642 643 delay_bits = (value & RT_D_CFG_DELAY_MASK) >> RT_D_CFG_DELAY_SHIFT; 644 delay = st_pinconf_bit_to_delay(delay_bits, info->data, output); 645 ST_PINCONF_PACK_RT_DELAY(*config, delay); 646 647 if (value & RT_D_CFG_CLKNOTDATA_MASK) 648 ST_PINCONF_PACK_RT_CLKNOTDATA(*config); 649 650 if (value & RT_D_CFG_DOUBLE_EDGE_MASK) 651 ST_PINCONF_PACK_RT_DOUBLE_EDGE(*config); 652 653 if (value & RT_D_CFG_INVERTCLK_MASK) 654 ST_PINCONF_PACK_RT_INVERTCLK(*config); 655 656 if (value & RT_D_CFG_RETIME_MASK) 657 ST_PINCONF_PACK_RT(*config); 658 659 return 0; 660 } 661 662 /* GPIO related functions */ 663 664 static inline void __st_gpio_set(struct st_gpio_bank *bank, 665 unsigned offset, int value) 666 { 667 if (value) 668 writel(BIT(offset), bank->base + REG_PIO_SET_POUT); 669 else 670 writel(BIT(offset), bank->base + REG_PIO_CLR_POUT); 671 } 672 673 static void st_gpio_direction(struct st_gpio_bank *bank, 674 unsigned int gpio, unsigned int direction) 675 { 676 int offset = st_gpio_pin(gpio); 677 int i = 0; 678 /** 679 * There are three configuration registers (PIOn_PC0, PIOn_PC1 680 * and PIOn_PC2) for each port. These are used to configure the 681 * PIO port pins. Each pin can be configured as an input, output, 682 * bidirectional, or alternative function pin. Three bits, one bit 683 * from each of the three registers, configure the corresponding bit of 684 * the port. Valid bit settings is: 685 * 686 * PC2 PC1 PC0 Direction. 687 * 0 0 0 [Input Weak pull-up] 688 * 0 0 or 1 1 [Bidirection] 689 * 0 1 0 [Output] 690 * 1 0 0 [Input] 691 * 692 * PIOn_SET_PC and PIOn_CLR_PC registers are used to set and clear bits 693 * individually. 694 */ 695 for (i = 0; i <= 2; i++) { 696 if (direction & BIT(i)) 697 writel(BIT(offset), bank->base + REG_PIO_SET_PC(i)); 698 else 699 writel(BIT(offset), bank->base + REG_PIO_CLR_PC(i)); 700 } 701 } 702 703 static int st_gpio_get(struct gpio_chip *chip, unsigned offset) 704 { 705 struct st_gpio_bank *bank = gpiochip_get_data(chip); 706 707 return !!(readl(bank->base + REG_PIO_PIN) & BIT(offset)); 708 } 709 710 static void st_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 711 { 712 struct st_gpio_bank *bank = gpiochip_get_data(chip); 713 __st_gpio_set(bank, offset, value); 714 } 715 716 static int st_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 717 { 718 pinctrl_gpio_direction_input(chip->base + offset); 719 720 return 0; 721 } 722 723 static int st_gpio_direction_output(struct gpio_chip *chip, 724 unsigned offset, int value) 725 { 726 struct st_gpio_bank *bank = gpiochip_get_data(chip); 727 728 __st_gpio_set(bank, offset, value); 729 pinctrl_gpio_direction_output(chip->base + offset); 730 731 return 0; 732 } 733 734 static int st_gpio_get_direction(struct gpio_chip *chip, unsigned offset) 735 { 736 struct st_gpio_bank *bank = gpiochip_get_data(chip); 737 struct st_pio_control pc = bank->pc; 738 unsigned long config; 739 unsigned int direction = 0; 740 unsigned int function; 741 unsigned int value; 742 int i = 0; 743 744 /* Alternate function direction is handled by Pinctrl */ 745 function = st_pctl_get_pin_function(&pc, offset); 746 if (function) { 747 st_pinconf_get_direction(&pc, offset, &config); 748 if (ST_PINCONF_UNPACK_OE(config)) 749 return GPIO_LINE_DIRECTION_OUT; 750 751 return GPIO_LINE_DIRECTION_IN; 752 } 753 754 /* 755 * GPIO direction is handled differently 756 * - See st_gpio_direction() above for an explanation 757 */ 758 for (i = 0; i <= 2; i++) { 759 value = readl(bank->base + REG_PIO_PC(i)); 760 direction |= ((value >> offset) & 0x1) << i; 761 } 762 763 if (direction == ST_GPIO_DIRECTION_IN) 764 return GPIO_LINE_DIRECTION_IN; 765 766 return GPIO_LINE_DIRECTION_OUT; 767 } 768 769 /* Pinctrl Groups */ 770 static int st_pctl_get_groups_count(struct pinctrl_dev *pctldev) 771 { 772 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 773 774 return info->ngroups; 775 } 776 777 static const char *st_pctl_get_group_name(struct pinctrl_dev *pctldev, 778 unsigned selector) 779 { 780 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 781 782 return info->groups[selector].name; 783 } 784 785 static int st_pctl_get_group_pins(struct pinctrl_dev *pctldev, 786 unsigned selector, const unsigned **pins, unsigned *npins) 787 { 788 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 789 790 if (selector >= info->ngroups) 791 return -EINVAL; 792 793 *pins = info->groups[selector].pins; 794 *npins = info->groups[selector].npins; 795 796 return 0; 797 } 798 799 static inline const struct st_pctl_group *st_pctl_find_group_by_name( 800 const struct st_pinctrl *info, const char *name) 801 { 802 int i; 803 804 for (i = 0; i < info->ngroups; i++) { 805 if (!strcmp(info->groups[i].name, name)) 806 return &info->groups[i]; 807 } 808 809 return NULL; 810 } 811 812 static int st_pctl_dt_node_to_map(struct pinctrl_dev *pctldev, 813 struct device_node *np, struct pinctrl_map **map, unsigned *num_maps) 814 { 815 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 816 const struct st_pctl_group *grp; 817 struct pinctrl_map *new_map; 818 struct device_node *parent; 819 int map_num, i; 820 821 grp = st_pctl_find_group_by_name(info, np->name); 822 if (!grp) { 823 dev_err(info->dev, "unable to find group for node %pOFn\n", 824 np); 825 return -EINVAL; 826 } 827 828 map_num = grp->npins + 1; 829 new_map = devm_kcalloc(pctldev->dev, 830 map_num, sizeof(*new_map), GFP_KERNEL); 831 if (!new_map) 832 return -ENOMEM; 833 834 parent = of_get_parent(np); 835 if (!parent) { 836 devm_kfree(pctldev->dev, new_map); 837 return -EINVAL; 838 } 839 840 *map = new_map; 841 *num_maps = map_num; 842 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP; 843 new_map[0].data.mux.function = parent->name; 844 new_map[0].data.mux.group = np->name; 845 of_node_put(parent); 846 847 /* create config map per pin */ 848 new_map++; 849 for (i = 0; i < grp->npins; i++) { 850 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN; 851 new_map[i].data.configs.group_or_pin = 852 pin_get_name(pctldev, grp->pins[i]); 853 new_map[i].data.configs.configs = &grp->pin_conf[i].config; 854 new_map[i].data.configs.num_configs = 1; 855 } 856 dev_info(pctldev->dev, "maps: function %s group %s num %d\n", 857 (*map)->data.mux.function, grp->name, map_num); 858 859 return 0; 860 } 861 862 static void st_pctl_dt_free_map(struct pinctrl_dev *pctldev, 863 struct pinctrl_map *map, unsigned num_maps) 864 { 865 } 866 867 static const struct pinctrl_ops st_pctlops = { 868 .get_groups_count = st_pctl_get_groups_count, 869 .get_group_pins = st_pctl_get_group_pins, 870 .get_group_name = st_pctl_get_group_name, 871 .dt_node_to_map = st_pctl_dt_node_to_map, 872 .dt_free_map = st_pctl_dt_free_map, 873 }; 874 875 /* Pinmux */ 876 static int st_pmx_get_funcs_count(struct pinctrl_dev *pctldev) 877 { 878 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 879 880 return info->nfunctions; 881 } 882 883 static const char *st_pmx_get_fname(struct pinctrl_dev *pctldev, 884 unsigned selector) 885 { 886 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 887 888 return info->functions[selector].name; 889 } 890 891 static int st_pmx_get_groups(struct pinctrl_dev *pctldev, 892 unsigned selector, const char * const **grps, unsigned * const ngrps) 893 { 894 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 895 *grps = info->functions[selector].groups; 896 *ngrps = info->functions[selector].ngroups; 897 898 return 0; 899 } 900 901 static int st_pmx_set_mux(struct pinctrl_dev *pctldev, unsigned fselector, 902 unsigned group) 903 { 904 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 905 struct st_pinconf *conf = info->groups[group].pin_conf; 906 struct st_pio_control *pc; 907 int i; 908 909 for (i = 0; i < info->groups[group].npins; i++) { 910 pc = st_get_pio_control(pctldev, conf[i].pin); 911 st_pctl_set_function(pc, conf[i].pin, conf[i].altfunc); 912 } 913 914 return 0; 915 } 916 917 static int st_pmx_set_gpio_direction(struct pinctrl_dev *pctldev, 918 struct pinctrl_gpio_range *range, unsigned gpio, 919 bool input) 920 { 921 struct st_gpio_bank *bank = gpio_range_to_bank(range); 922 /* 923 * When a PIO bank is used in its primary function mode (altfunc = 0) 924 * Output Enable (OE), Open Drain(OD), and Pull Up (PU) 925 * for the primary PIO functions are driven by the related PIO block 926 */ 927 st_pctl_set_function(&bank->pc, gpio, 0); 928 st_gpio_direction(bank, gpio, input ? 929 ST_GPIO_DIRECTION_IN : ST_GPIO_DIRECTION_OUT); 930 931 return 0; 932 } 933 934 static const struct pinmux_ops st_pmxops = { 935 .get_functions_count = st_pmx_get_funcs_count, 936 .get_function_name = st_pmx_get_fname, 937 .get_function_groups = st_pmx_get_groups, 938 .set_mux = st_pmx_set_mux, 939 .gpio_set_direction = st_pmx_set_gpio_direction, 940 .strict = true, 941 }; 942 943 /* Pinconf */ 944 static void st_pinconf_get_retime(struct st_pinctrl *info, 945 struct st_pio_control *pc, int pin, unsigned long *config) 946 { 947 if (info->data->rt_style == st_retime_style_packed) 948 st_pinconf_get_retime_packed(info, pc, pin, config); 949 else if (info->data->rt_style == st_retime_style_dedicated) 950 if ((BIT(pin) & pc->rt_pin_mask)) 951 st_pinconf_get_retime_dedicated(info, pc, 952 pin, config); 953 } 954 955 static void st_pinconf_set_retime(struct st_pinctrl *info, 956 struct st_pio_control *pc, int pin, unsigned long config) 957 { 958 if (info->data->rt_style == st_retime_style_packed) 959 st_pinconf_set_retime_packed(info, pc, config, pin); 960 else if (info->data->rt_style == st_retime_style_dedicated) 961 if ((BIT(pin) & pc->rt_pin_mask)) 962 st_pinconf_set_retime_dedicated(info, pc, 963 config, pin); 964 } 965 966 static int st_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin_id, 967 unsigned long *configs, unsigned num_configs) 968 { 969 int pin = st_gpio_pin(pin_id); 970 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 971 struct st_pio_control *pc = st_get_pio_control(pctldev, pin_id); 972 int i; 973 974 for (i = 0; i < num_configs; i++) { 975 st_pinconf_set_config(pc, pin, configs[i]); 976 st_pinconf_set_retime(info, pc, pin, configs[i]); 977 } /* for each config */ 978 979 return 0; 980 } 981 982 static int st_pinconf_get(struct pinctrl_dev *pctldev, 983 unsigned pin_id, unsigned long *config) 984 { 985 int pin = st_gpio_pin(pin_id); 986 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 987 struct st_pio_control *pc = st_get_pio_control(pctldev, pin_id); 988 989 *config = 0; 990 st_pinconf_get_direction(pc, pin, config); 991 st_pinconf_get_retime(info, pc, pin, config); 992 993 return 0; 994 } 995 996 static void st_pinconf_dbg_show(struct pinctrl_dev *pctldev, 997 struct seq_file *s, unsigned pin_id) 998 { 999 struct st_pio_control *pc; 1000 unsigned long config; 1001 unsigned int function; 1002 int offset = st_gpio_pin(pin_id); 1003 char f[16]; 1004 int oe; 1005 1006 mutex_unlock(&pctldev->mutex); 1007 pc = st_get_pio_control(pctldev, pin_id); 1008 st_pinconf_get(pctldev, pin_id, &config); 1009 mutex_lock(&pctldev->mutex); 1010 1011 function = st_pctl_get_pin_function(pc, offset); 1012 if (function) 1013 snprintf(f, 10, "Alt Fn %u", function); 1014 else 1015 snprintf(f, 5, "GPIO"); 1016 1017 oe = st_gpio_get_direction(&pc_to_bank(pc)->gpio_chip, offset); 1018 seq_printf(s, "[OE:%d,PU:%ld,OD:%ld]\t%s\n" 1019 "\t\t[retime:%ld,invclk:%ld,clknotdat:%ld," 1020 "de:%ld,rt-clk:%ld,rt-delay:%ld]", 1021 (oe == GPIO_LINE_DIRECTION_OUT), 1022 ST_PINCONF_UNPACK_PU(config), 1023 ST_PINCONF_UNPACK_OD(config), 1024 f, 1025 ST_PINCONF_UNPACK_RT(config), 1026 ST_PINCONF_UNPACK_RT_INVERTCLK(config), 1027 ST_PINCONF_UNPACK_RT_CLKNOTDATA(config), 1028 ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(config), 1029 ST_PINCONF_UNPACK_RT_CLK(config), 1030 ST_PINCONF_UNPACK_RT_DELAY(config)); 1031 } 1032 1033 static const struct pinconf_ops st_confops = { 1034 .pin_config_get = st_pinconf_get, 1035 .pin_config_set = st_pinconf_set, 1036 .pin_config_dbg_show = st_pinconf_dbg_show, 1037 }; 1038 1039 static void st_pctl_dt_child_count(struct st_pinctrl *info, 1040 struct device_node *np) 1041 { 1042 struct device_node *child; 1043 for_each_child_of_node(np, child) { 1044 if (of_property_read_bool(child, "gpio-controller")) { 1045 info->nbanks++; 1046 } else { 1047 info->nfunctions++; 1048 info->ngroups += of_get_child_count(child); 1049 } 1050 } 1051 } 1052 1053 static int st_pctl_dt_setup_retime_packed(struct st_pinctrl *info, 1054 int bank, struct st_pio_control *pc) 1055 { 1056 struct device *dev = info->dev; 1057 struct regmap *rm = info->regmap; 1058 const struct st_pctl_data *data = info->data; 1059 /* 2 registers per bank */ 1060 int reg = (data->rt + bank * RT_P_CFGS_PER_BANK) * 4; 1061 struct st_retime_packed *rt_p = &pc->rt.rt_p; 1062 /* cfg0 */ 1063 struct reg_field clk1notclk0 = RT_P_CFG0_CLK1NOTCLK0_FIELD(reg); 1064 struct reg_field delay_0 = RT_P_CFG0_DELAY_0_FIELD(reg); 1065 struct reg_field delay_1 = RT_P_CFG0_DELAY_1_FIELD(reg); 1066 /* cfg1 */ 1067 struct reg_field invertclk = RT_P_CFG1_INVERTCLK_FIELD(reg + 4); 1068 struct reg_field retime = RT_P_CFG1_RETIME_FIELD(reg + 4); 1069 struct reg_field clknotdata = RT_P_CFG1_CLKNOTDATA_FIELD(reg + 4); 1070 struct reg_field double_edge = RT_P_CFG1_DOUBLE_EDGE_FIELD(reg + 4); 1071 1072 rt_p->clk1notclk0 = devm_regmap_field_alloc(dev, rm, clk1notclk0); 1073 rt_p->delay_0 = devm_regmap_field_alloc(dev, rm, delay_0); 1074 rt_p->delay_1 = devm_regmap_field_alloc(dev, rm, delay_1); 1075 rt_p->invertclk = devm_regmap_field_alloc(dev, rm, invertclk); 1076 rt_p->retime = devm_regmap_field_alloc(dev, rm, retime); 1077 rt_p->clknotdata = devm_regmap_field_alloc(dev, rm, clknotdata); 1078 rt_p->double_edge = devm_regmap_field_alloc(dev, rm, double_edge); 1079 1080 if (IS_ERR(rt_p->clk1notclk0) || IS_ERR(rt_p->delay_0) || 1081 IS_ERR(rt_p->delay_1) || IS_ERR(rt_p->invertclk) || 1082 IS_ERR(rt_p->retime) || IS_ERR(rt_p->clknotdata) || 1083 IS_ERR(rt_p->double_edge)) 1084 return -EINVAL; 1085 1086 return 0; 1087 } 1088 1089 static int st_pctl_dt_setup_retime_dedicated(struct st_pinctrl *info, 1090 int bank, struct st_pio_control *pc) 1091 { 1092 struct device *dev = info->dev; 1093 struct regmap *rm = info->regmap; 1094 const struct st_pctl_data *data = info->data; 1095 /* 8 registers per bank */ 1096 int reg_offset = (data->rt + bank * RT_D_CFGS_PER_BANK) * 4; 1097 struct st_retime_dedicated *rt_d = &pc->rt.rt_d; 1098 unsigned int j; 1099 u32 pin_mask = pc->rt_pin_mask; 1100 1101 for (j = 0; j < RT_D_CFGS_PER_BANK; j++) { 1102 if (BIT(j) & pin_mask) { 1103 struct reg_field reg = REG_FIELD(reg_offset, 0, 31); 1104 rt_d->rt[j] = devm_regmap_field_alloc(dev, rm, reg); 1105 if (IS_ERR(rt_d->rt[j])) 1106 return -EINVAL; 1107 reg_offset += 4; 1108 } 1109 } 1110 return 0; 1111 } 1112 1113 static int st_pctl_dt_setup_retime(struct st_pinctrl *info, 1114 int bank, struct st_pio_control *pc) 1115 { 1116 const struct st_pctl_data *data = info->data; 1117 if (data->rt_style == st_retime_style_packed) 1118 return st_pctl_dt_setup_retime_packed(info, bank, pc); 1119 else if (data->rt_style == st_retime_style_dedicated) 1120 return st_pctl_dt_setup_retime_dedicated(info, bank, pc); 1121 1122 return -EINVAL; 1123 } 1124 1125 1126 static struct regmap_field *st_pc_get_value(struct device *dev, 1127 struct regmap *regmap, int bank, 1128 int data, int lsb, int msb) 1129 { 1130 struct reg_field reg = REG_FIELD((data + bank) * 4, lsb, msb); 1131 1132 if (data < 0) 1133 return NULL; 1134 1135 return devm_regmap_field_alloc(dev, regmap, reg); 1136 } 1137 1138 static void st_parse_syscfgs(struct st_pinctrl *info, int bank, 1139 struct device_node *np) 1140 { 1141 const struct st_pctl_data *data = info->data; 1142 /** 1143 * For a given shared register like OE/PU/OD, there are 8 bits per bank 1144 * 0:7 belongs to bank0, 8:15 belongs to bank1 ... 1145 * So each register is shared across 4 banks. 1146 */ 1147 int lsb = (bank%4) * ST_GPIO_PINS_PER_BANK; 1148 int msb = lsb + ST_GPIO_PINS_PER_BANK - 1; 1149 struct st_pio_control *pc = &info->banks[bank].pc; 1150 struct device *dev = info->dev; 1151 struct regmap *regmap = info->regmap; 1152 1153 pc->alt = st_pc_get_value(dev, regmap, bank, data->alt, 0, 31); 1154 pc->oe = st_pc_get_value(dev, regmap, bank/4, data->oe, lsb, msb); 1155 pc->pu = st_pc_get_value(dev, regmap, bank/4, data->pu, lsb, msb); 1156 pc->od = st_pc_get_value(dev, regmap, bank/4, data->od, lsb, msb); 1157 1158 /* retime avaiable for all pins by default */ 1159 pc->rt_pin_mask = 0xff; 1160 of_property_read_u32(np, "st,retime-pin-mask", &pc->rt_pin_mask); 1161 st_pctl_dt_setup_retime(info, bank, pc); 1162 1163 return; 1164 } 1165 1166 /* 1167 * Each pin is represented in of the below forms. 1168 * <bank offset mux direction rt_type rt_delay rt_clk> 1169 */ 1170 static int st_pctl_dt_parse_groups(struct device_node *np, 1171 struct st_pctl_group *grp, struct st_pinctrl *info, int idx) 1172 { 1173 /* bank pad direction val altfunction */ 1174 const __be32 *list; 1175 struct property *pp; 1176 struct st_pinconf *conf; 1177 struct device_node *pins; 1178 int i = 0, npins = 0, nr_props, ret = 0; 1179 1180 pins = of_get_child_by_name(np, "st,pins"); 1181 if (!pins) 1182 return -ENODATA; 1183 1184 for_each_property_of_node(pins, pp) { 1185 /* Skip those we do not want to proceed */ 1186 if (!strcmp(pp->name, "name")) 1187 continue; 1188 1189 if (pp->length / sizeof(__be32) >= OF_GPIO_ARGS_MIN) { 1190 npins++; 1191 } else { 1192 pr_warn("Invalid st,pins in %pOFn node\n", np); 1193 ret = -EINVAL; 1194 goto out_put_node; 1195 } 1196 } 1197 1198 grp->npins = npins; 1199 grp->name = np->name; 1200 grp->pins = devm_kcalloc(info->dev, npins, sizeof(u32), GFP_KERNEL); 1201 grp->pin_conf = devm_kcalloc(info->dev, 1202 npins, sizeof(*conf), GFP_KERNEL); 1203 1204 if (!grp->pins || !grp->pin_conf) { 1205 ret = -ENOMEM; 1206 goto out_put_node; 1207 } 1208 1209 /* <bank offset mux direction rt_type rt_delay rt_clk> */ 1210 for_each_property_of_node(pins, pp) { 1211 if (!strcmp(pp->name, "name")) 1212 continue; 1213 nr_props = pp->length/sizeof(u32); 1214 list = pp->value; 1215 conf = &grp->pin_conf[i]; 1216 1217 /* bank & offset */ 1218 be32_to_cpup(list++); 1219 be32_to_cpup(list++); 1220 conf->pin = of_get_named_gpio(pins, pp->name, 0); 1221 conf->name = pp->name; 1222 grp->pins[i] = conf->pin; 1223 /* mux */ 1224 conf->altfunc = be32_to_cpup(list++); 1225 conf->config = 0; 1226 /* direction */ 1227 conf->config |= be32_to_cpup(list++); 1228 /* rt_type rt_delay rt_clk */ 1229 if (nr_props >= OF_GPIO_ARGS_MIN + OF_RT_ARGS_MIN) { 1230 /* rt_type */ 1231 conf->config |= be32_to_cpup(list++); 1232 /* rt_delay */ 1233 conf->config |= be32_to_cpup(list++); 1234 /* rt_clk */ 1235 if (nr_props > OF_GPIO_ARGS_MIN + OF_RT_ARGS_MIN) 1236 conf->config |= be32_to_cpup(list++); 1237 } 1238 i++; 1239 } 1240 1241 out_put_node: 1242 of_node_put(pins); 1243 1244 return ret; 1245 } 1246 1247 static int st_pctl_parse_functions(struct device_node *np, 1248 struct st_pinctrl *info, u32 index, int *grp_index) 1249 { 1250 struct device_node *child; 1251 struct st_pmx_func *func; 1252 struct st_pctl_group *grp; 1253 int ret, i; 1254 1255 func = &info->functions[index]; 1256 func->name = np->name; 1257 func->ngroups = of_get_child_count(np); 1258 if (func->ngroups == 0) { 1259 dev_err(info->dev, "No groups defined\n"); 1260 return -EINVAL; 1261 } 1262 func->groups = devm_kcalloc(info->dev, 1263 func->ngroups, sizeof(char *), GFP_KERNEL); 1264 if (!func->groups) 1265 return -ENOMEM; 1266 1267 i = 0; 1268 for_each_child_of_node(np, child) { 1269 func->groups[i] = child->name; 1270 grp = &info->groups[*grp_index]; 1271 *grp_index += 1; 1272 ret = st_pctl_dt_parse_groups(child, grp, info, i++); 1273 if (ret) { 1274 of_node_put(child); 1275 return ret; 1276 } 1277 } 1278 dev_info(info->dev, "Function[%d\t name:%s,\tgroups:%d]\n", 1279 index, func->name, func->ngroups); 1280 1281 return 0; 1282 } 1283 1284 static void st_gpio_irq_mask(struct irq_data *d) 1285 { 1286 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1287 struct st_gpio_bank *bank = gpiochip_get_data(gc); 1288 1289 writel(BIT(d->hwirq), bank->base + REG_PIO_CLR_PMASK); 1290 } 1291 1292 static void st_gpio_irq_unmask(struct irq_data *d) 1293 { 1294 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1295 struct st_gpio_bank *bank = gpiochip_get_data(gc); 1296 1297 writel(BIT(d->hwirq), bank->base + REG_PIO_SET_PMASK); 1298 } 1299 1300 static int st_gpio_irq_request_resources(struct irq_data *d) 1301 { 1302 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1303 1304 st_gpio_direction_input(gc, d->hwirq); 1305 1306 return gpiochip_lock_as_irq(gc, d->hwirq); 1307 } 1308 1309 static void st_gpio_irq_release_resources(struct irq_data *d) 1310 { 1311 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1312 1313 gpiochip_unlock_as_irq(gc, d->hwirq); 1314 } 1315 1316 static int st_gpio_irq_set_type(struct irq_data *d, unsigned type) 1317 { 1318 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1319 struct st_gpio_bank *bank = gpiochip_get_data(gc); 1320 unsigned long flags; 1321 int comp, pin = d->hwirq; 1322 u32 val; 1323 u32 pin_edge_conf = 0; 1324 1325 switch (type) { 1326 case IRQ_TYPE_LEVEL_HIGH: 1327 comp = 0; 1328 break; 1329 case IRQ_TYPE_EDGE_FALLING: 1330 comp = 0; 1331 pin_edge_conf = ST_IRQ_FALLING_EDGE_CONF(pin); 1332 break; 1333 case IRQ_TYPE_LEVEL_LOW: 1334 comp = 1; 1335 break; 1336 case IRQ_TYPE_EDGE_RISING: 1337 comp = 1; 1338 pin_edge_conf = ST_IRQ_RISING_EDGE_CONF(pin); 1339 break; 1340 case IRQ_TYPE_EDGE_BOTH: 1341 comp = st_gpio_get(&bank->gpio_chip, pin); 1342 pin_edge_conf = ST_IRQ_BOTH_EDGE_CONF(pin); 1343 break; 1344 default: 1345 return -EINVAL; 1346 } 1347 1348 spin_lock_irqsave(&bank->lock, flags); 1349 bank->irq_edge_conf &= ~(ST_IRQ_EDGE_MASK << ( 1350 pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN)); 1351 bank->irq_edge_conf |= pin_edge_conf; 1352 spin_unlock_irqrestore(&bank->lock, flags); 1353 1354 val = readl(bank->base + REG_PIO_PCOMP); 1355 val &= ~BIT(pin); 1356 val |= (comp << pin); 1357 writel(val, bank->base + REG_PIO_PCOMP); 1358 1359 return 0; 1360 } 1361 1362 /* 1363 * As edge triggers are not supported at hardware level, it is supported by 1364 * software by exploiting the level trigger support in hardware. 1365 * 1366 * Steps for detection raising edge interrupt in software. 1367 * 1368 * Step 1: CONFIGURE pin to detect level LOW interrupts. 1369 * 1370 * Step 2: DETECT level LOW interrupt and in irqmux/gpio bank interrupt handler, 1371 * if the value of pin is low, then CONFIGURE pin for level HIGH interrupt. 1372 * IGNORE calling the actual interrupt handler for the pin at this stage. 1373 * 1374 * Step 3: DETECT level HIGH interrupt and in irqmux/gpio-bank interrupt handler 1375 * if the value of pin is HIGH, CONFIGURE pin for level LOW interrupt and then 1376 * DISPATCH the interrupt to the interrupt handler of the pin. 1377 * 1378 * step-1 ________ __________ 1379 * | | step - 3 1380 * | | 1381 * step -2 |_____| 1382 * 1383 * falling edge is also detected int the same way. 1384 * 1385 */ 1386 static void __gpio_irq_handler(struct st_gpio_bank *bank) 1387 { 1388 unsigned long port_in, port_mask, port_comp, active_irqs; 1389 unsigned long bank_edge_mask, flags; 1390 int n, val, ecfg; 1391 1392 spin_lock_irqsave(&bank->lock, flags); 1393 bank_edge_mask = bank->irq_edge_conf; 1394 spin_unlock_irqrestore(&bank->lock, flags); 1395 1396 for (;;) { 1397 port_in = readl(bank->base + REG_PIO_PIN); 1398 port_comp = readl(bank->base + REG_PIO_PCOMP); 1399 port_mask = readl(bank->base + REG_PIO_PMASK); 1400 1401 active_irqs = (port_in ^ port_comp) & port_mask; 1402 1403 if (active_irqs == 0) 1404 break; 1405 1406 for_each_set_bit(n, &active_irqs, BITS_PER_LONG) { 1407 /* check if we are detecting fake edges ... */ 1408 ecfg = ST_IRQ_EDGE_CONF(bank_edge_mask, n); 1409 1410 if (ecfg) { 1411 /* edge detection. */ 1412 val = st_gpio_get(&bank->gpio_chip, n); 1413 1414 writel(BIT(n), 1415 val ? bank->base + REG_PIO_SET_PCOMP : 1416 bank->base + REG_PIO_CLR_PCOMP); 1417 1418 if (ecfg != ST_IRQ_EDGE_BOTH && 1419 !((ecfg & ST_IRQ_EDGE_FALLING) ^ val)) 1420 continue; 1421 } 1422 1423 generic_handle_domain_irq(bank->gpio_chip.irq.domain, n); 1424 } 1425 } 1426 } 1427 1428 static void st_gpio_irq_handler(struct irq_desc *desc) 1429 { 1430 /* interrupt dedicated per bank */ 1431 struct irq_chip *chip = irq_desc_get_chip(desc); 1432 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 1433 struct st_gpio_bank *bank = gpiochip_get_data(gc); 1434 1435 chained_irq_enter(chip, desc); 1436 __gpio_irq_handler(bank); 1437 chained_irq_exit(chip, desc); 1438 } 1439 1440 static void st_gpio_irqmux_handler(struct irq_desc *desc) 1441 { 1442 struct irq_chip *chip = irq_desc_get_chip(desc); 1443 struct st_pinctrl *info = irq_desc_get_handler_data(desc); 1444 unsigned long status; 1445 int n; 1446 1447 chained_irq_enter(chip, desc); 1448 1449 status = readl(info->irqmux_base); 1450 1451 for_each_set_bit(n, &status, info->nbanks) 1452 __gpio_irq_handler(&info->banks[n]); 1453 1454 chained_irq_exit(chip, desc); 1455 } 1456 1457 static const struct gpio_chip st_gpio_template = { 1458 .request = gpiochip_generic_request, 1459 .free = gpiochip_generic_free, 1460 .get = st_gpio_get, 1461 .set = st_gpio_set, 1462 .direction_input = st_gpio_direction_input, 1463 .direction_output = st_gpio_direction_output, 1464 .get_direction = st_gpio_get_direction, 1465 .ngpio = ST_GPIO_PINS_PER_BANK, 1466 }; 1467 1468 static struct irq_chip st_gpio_irqchip = { 1469 .name = "GPIO", 1470 .irq_request_resources = st_gpio_irq_request_resources, 1471 .irq_release_resources = st_gpio_irq_release_resources, 1472 .irq_disable = st_gpio_irq_mask, 1473 .irq_mask = st_gpio_irq_mask, 1474 .irq_unmask = st_gpio_irq_unmask, 1475 .irq_set_type = st_gpio_irq_set_type, 1476 .flags = IRQCHIP_SKIP_SET_WAKE, 1477 }; 1478 1479 static int st_gpiolib_register_bank(struct st_pinctrl *info, 1480 int bank_nr, struct device_node *np) 1481 { 1482 struct st_gpio_bank *bank = &info->banks[bank_nr]; 1483 struct pinctrl_gpio_range *range = &bank->range; 1484 struct device *dev = info->dev; 1485 int bank_num = of_alias_get_id(np, "gpio"); 1486 struct resource res, irq_res; 1487 int err; 1488 1489 if (of_address_to_resource(np, 0, &res)) 1490 return -ENODEV; 1491 1492 bank->base = devm_ioremap_resource(dev, &res); 1493 if (IS_ERR(bank->base)) 1494 return PTR_ERR(bank->base); 1495 1496 bank->gpio_chip = st_gpio_template; 1497 bank->gpio_chip.base = bank_num * ST_GPIO_PINS_PER_BANK; 1498 bank->gpio_chip.ngpio = ST_GPIO_PINS_PER_BANK; 1499 bank->gpio_chip.of_node = np; 1500 bank->gpio_chip.parent = dev; 1501 spin_lock_init(&bank->lock); 1502 1503 of_property_read_string(np, "st,bank-name", &range->name); 1504 bank->gpio_chip.label = range->name; 1505 1506 range->id = bank_num; 1507 range->pin_base = range->base = range->id * ST_GPIO_PINS_PER_BANK; 1508 range->npins = bank->gpio_chip.ngpio; 1509 range->gc = &bank->gpio_chip; 1510 1511 /** 1512 * GPIO bank can have one of the two possible types of 1513 * interrupt-wirings. 1514 * 1515 * First type is via irqmux, single interrupt is used by multiple 1516 * gpio banks. This reduces number of overall interrupts numbers 1517 * required. All these banks belong to a single pincontroller. 1518 * _________ 1519 * | |----> [gpio-bank (n) ] 1520 * | |----> [gpio-bank (n + 1)] 1521 * [irqN]-- | irq-mux |----> [gpio-bank (n + 2)] 1522 * | |----> [gpio-bank (... )] 1523 * |_________|----> [gpio-bank (n + 7)] 1524 * 1525 * Second type has a dedicated interrupt per each gpio bank. 1526 * 1527 * [irqN]----> [gpio-bank (n)] 1528 */ 1529 1530 if (of_irq_to_resource(np, 0, &irq_res) > 0) { 1531 struct gpio_irq_chip *girq; 1532 int gpio_irq = irq_res.start; 1533 1534 /* This is not a valid IRQ */ 1535 if (gpio_irq <= 0) { 1536 dev_err(dev, "invalid IRQ for %pOF bank\n", np); 1537 goto skip_irq; 1538 } 1539 /* We need to have a mux as well */ 1540 if (!info->irqmux_base) { 1541 dev_err(dev, "no irqmux for %pOF bank\n", np); 1542 goto skip_irq; 1543 } 1544 1545 girq = &bank->gpio_chip.irq; 1546 girq->chip = &st_gpio_irqchip; 1547 girq->parent_handler = st_gpio_irq_handler; 1548 girq->num_parents = 1; 1549 girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents), 1550 GFP_KERNEL); 1551 if (!girq->parents) 1552 return -ENOMEM; 1553 girq->parents[0] = gpio_irq; 1554 girq->default_type = IRQ_TYPE_NONE; 1555 girq->handler = handle_simple_irq; 1556 } 1557 1558 skip_irq: 1559 err = gpiochip_add_data(&bank->gpio_chip, bank); 1560 if (err) { 1561 dev_err(dev, "Failed to add gpiochip(%d)!\n", bank_num); 1562 return err; 1563 } 1564 dev_info(dev, "%s bank added.\n", range->name); 1565 1566 return 0; 1567 } 1568 1569 static const struct of_device_id st_pctl_of_match[] = { 1570 { .compatible = "st,stih407-sbc-pinctrl", .data = &stih407_data}, 1571 { .compatible = "st,stih407-front-pinctrl", .data = &stih407_data}, 1572 { .compatible = "st,stih407-rear-pinctrl", .data = &stih407_data}, 1573 { .compatible = "st,stih407-flash-pinctrl", .data = &stih407_flashdata}, 1574 { /* sentinel */ } 1575 }; 1576 1577 static int st_pctl_probe_dt(struct platform_device *pdev, 1578 struct pinctrl_desc *pctl_desc, struct st_pinctrl *info) 1579 { 1580 int ret = 0; 1581 int i = 0, j = 0, k = 0, bank; 1582 struct pinctrl_pin_desc *pdesc; 1583 struct device_node *np = pdev->dev.of_node; 1584 struct device_node *child; 1585 int grp_index = 0; 1586 int irq = 0; 1587 struct resource *res; 1588 1589 st_pctl_dt_child_count(info, np); 1590 if (!info->nbanks) { 1591 dev_err(&pdev->dev, "you need at least one gpio bank\n"); 1592 return -EINVAL; 1593 } 1594 1595 dev_info(&pdev->dev, "nbanks = %d\n", info->nbanks); 1596 dev_info(&pdev->dev, "nfunctions = %d\n", info->nfunctions); 1597 dev_info(&pdev->dev, "ngroups = %d\n", info->ngroups); 1598 1599 info->functions = devm_kcalloc(&pdev->dev, 1600 info->nfunctions, sizeof(*info->functions), GFP_KERNEL); 1601 1602 info->groups = devm_kcalloc(&pdev->dev, 1603 info->ngroups, sizeof(*info->groups), 1604 GFP_KERNEL); 1605 1606 info->banks = devm_kcalloc(&pdev->dev, 1607 info->nbanks, sizeof(*info->banks), GFP_KERNEL); 1608 1609 if (!info->functions || !info->groups || !info->banks) 1610 return -ENOMEM; 1611 1612 info->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg"); 1613 if (IS_ERR(info->regmap)) { 1614 dev_err(info->dev, "No syscfg phandle specified\n"); 1615 return PTR_ERR(info->regmap); 1616 } 1617 info->data = of_match_node(st_pctl_of_match, np)->data; 1618 1619 irq = platform_get_irq(pdev, 0); 1620 1621 if (irq > 0) { 1622 res = platform_get_resource_byname(pdev, 1623 IORESOURCE_MEM, "irqmux"); 1624 info->irqmux_base = devm_ioremap_resource(&pdev->dev, res); 1625 1626 if (IS_ERR(info->irqmux_base)) 1627 return PTR_ERR(info->irqmux_base); 1628 1629 irq_set_chained_handler_and_data(irq, st_gpio_irqmux_handler, 1630 info); 1631 1632 } 1633 1634 pctl_desc->npins = info->nbanks * ST_GPIO_PINS_PER_BANK; 1635 pdesc = devm_kcalloc(&pdev->dev, 1636 pctl_desc->npins, sizeof(*pdesc), GFP_KERNEL); 1637 if (!pdesc) 1638 return -ENOMEM; 1639 1640 pctl_desc->pins = pdesc; 1641 1642 bank = 0; 1643 for_each_child_of_node(np, child) { 1644 if (of_property_read_bool(child, "gpio-controller")) { 1645 const char *bank_name = NULL; 1646 ret = st_gpiolib_register_bank(info, bank, child); 1647 if (ret) { 1648 of_node_put(child); 1649 return ret; 1650 } 1651 1652 k = info->banks[bank].range.pin_base; 1653 bank_name = info->banks[bank].range.name; 1654 for (j = 0; j < ST_GPIO_PINS_PER_BANK; j++, k++) { 1655 pdesc->number = k; 1656 pdesc->name = kasprintf(GFP_KERNEL, "%s[%d]", 1657 bank_name, j); 1658 pdesc++; 1659 } 1660 st_parse_syscfgs(info, bank, child); 1661 bank++; 1662 } else { 1663 ret = st_pctl_parse_functions(child, info, 1664 i++, &grp_index); 1665 if (ret) { 1666 dev_err(&pdev->dev, "No functions found.\n"); 1667 of_node_put(child); 1668 return ret; 1669 } 1670 } 1671 } 1672 1673 return 0; 1674 } 1675 1676 static int st_pctl_probe(struct platform_device *pdev) 1677 { 1678 struct st_pinctrl *info; 1679 struct pinctrl_desc *pctl_desc; 1680 int ret, i; 1681 1682 if (!pdev->dev.of_node) { 1683 dev_err(&pdev->dev, "device node not found.\n"); 1684 return -EINVAL; 1685 } 1686 1687 pctl_desc = devm_kzalloc(&pdev->dev, sizeof(*pctl_desc), GFP_KERNEL); 1688 if (!pctl_desc) 1689 return -ENOMEM; 1690 1691 info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL); 1692 if (!info) 1693 return -ENOMEM; 1694 1695 info->dev = &pdev->dev; 1696 platform_set_drvdata(pdev, info); 1697 ret = st_pctl_probe_dt(pdev, pctl_desc, info); 1698 if (ret) 1699 return ret; 1700 1701 pctl_desc->owner = THIS_MODULE; 1702 pctl_desc->pctlops = &st_pctlops; 1703 pctl_desc->pmxops = &st_pmxops; 1704 pctl_desc->confops = &st_confops; 1705 pctl_desc->name = dev_name(&pdev->dev); 1706 1707 info->pctl = devm_pinctrl_register(&pdev->dev, pctl_desc, info); 1708 if (IS_ERR(info->pctl)) { 1709 dev_err(&pdev->dev, "Failed pinctrl registration\n"); 1710 return PTR_ERR(info->pctl); 1711 } 1712 1713 for (i = 0; i < info->nbanks; i++) 1714 pinctrl_add_gpio_range(info->pctl, &info->banks[i].range); 1715 1716 return 0; 1717 } 1718 1719 static struct platform_driver st_pctl_driver = { 1720 .driver = { 1721 .name = "st-pinctrl", 1722 .of_match_table = st_pctl_of_match, 1723 }, 1724 .probe = st_pctl_probe, 1725 }; 1726 1727 static int __init st_pctl_init(void) 1728 { 1729 return platform_driver_register(&st_pctl_driver); 1730 } 1731 arch_initcall(st_pctl_init); 1732