1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2013 STMicroelectronics (R&D) Limited. 4 * Authors: 5 * Srinivas Kandagatla <srinivas.kandagatla@st.com> 6 */ 7 8 #include <linux/init.h> 9 #include <linux/module.h> 10 #include <linux/slab.h> 11 #include <linux/err.h> 12 #include <linux/io.h> 13 #include <linux/of.h> 14 #include <linux/of_irq.h> 15 #include <linux/of_gpio.h> 16 #include <linux/of_address.h> 17 #include <linux/regmap.h> 18 #include <linux/mfd/syscon.h> 19 #include <linux/pinctrl/pinctrl.h> 20 #include <linux/pinctrl/pinmux.h> 21 #include <linux/pinctrl/pinconf.h> 22 #include <linux/platform_device.h> 23 #include "core.h" 24 25 /* PIO Block registers */ 26 /* PIO output */ 27 #define REG_PIO_POUT 0x00 28 /* Set bits of POUT */ 29 #define REG_PIO_SET_POUT 0x04 30 /* Clear bits of POUT */ 31 #define REG_PIO_CLR_POUT 0x08 32 /* PIO input */ 33 #define REG_PIO_PIN 0x10 34 /* PIO configuration */ 35 #define REG_PIO_PC(n) (0x20 + (n) * 0x10) 36 /* Set bits of PC[2:0] */ 37 #define REG_PIO_SET_PC(n) (0x24 + (n) * 0x10) 38 /* Clear bits of PC[2:0] */ 39 #define REG_PIO_CLR_PC(n) (0x28 + (n) * 0x10) 40 /* PIO input comparison */ 41 #define REG_PIO_PCOMP 0x50 42 /* Set bits of PCOMP */ 43 #define REG_PIO_SET_PCOMP 0x54 44 /* Clear bits of PCOMP */ 45 #define REG_PIO_CLR_PCOMP 0x58 46 /* PIO input comparison mask */ 47 #define REG_PIO_PMASK 0x60 48 /* Set bits of PMASK */ 49 #define REG_PIO_SET_PMASK 0x64 50 /* Clear bits of PMASK */ 51 #define REG_PIO_CLR_PMASK 0x68 52 53 #define ST_GPIO_DIRECTION_BIDIR 0x1 54 #define ST_GPIO_DIRECTION_OUT 0x2 55 #define ST_GPIO_DIRECTION_IN 0x4 56 57 /** 58 * Packed style retime configuration. 59 * There are two registers cfg0 and cfg1 in this style for each bank. 60 * Each field in this register is 8 bit corresponding to 8 pins in the bank. 61 */ 62 #define RT_P_CFGS_PER_BANK 2 63 #define RT_P_CFG0_CLK1NOTCLK0_FIELD(reg) REG_FIELD(reg, 0, 7) 64 #define RT_P_CFG0_DELAY_0_FIELD(reg) REG_FIELD(reg, 16, 23) 65 #define RT_P_CFG0_DELAY_1_FIELD(reg) REG_FIELD(reg, 24, 31) 66 #define RT_P_CFG1_INVERTCLK_FIELD(reg) REG_FIELD(reg, 0, 7) 67 #define RT_P_CFG1_RETIME_FIELD(reg) REG_FIELD(reg, 8, 15) 68 #define RT_P_CFG1_CLKNOTDATA_FIELD(reg) REG_FIELD(reg, 16, 23) 69 #define RT_P_CFG1_DOUBLE_EDGE_FIELD(reg) REG_FIELD(reg, 24, 31) 70 71 /** 72 * Dedicated style retime Configuration register 73 * each register is dedicated per pin. 74 */ 75 #define RT_D_CFGS_PER_BANK 8 76 #define RT_D_CFG_CLK_SHIFT 0 77 #define RT_D_CFG_CLK_MASK (0x3 << 0) 78 #define RT_D_CFG_CLKNOTDATA_SHIFT 2 79 #define RT_D_CFG_CLKNOTDATA_MASK BIT(2) 80 #define RT_D_CFG_DELAY_SHIFT 3 81 #define RT_D_CFG_DELAY_MASK (0xf << 3) 82 #define RT_D_CFG_DELAY_INNOTOUT_SHIFT 7 83 #define RT_D_CFG_DELAY_INNOTOUT_MASK BIT(7) 84 #define RT_D_CFG_DOUBLE_EDGE_SHIFT 8 85 #define RT_D_CFG_DOUBLE_EDGE_MASK BIT(8) 86 #define RT_D_CFG_INVERTCLK_SHIFT 9 87 #define RT_D_CFG_INVERTCLK_MASK BIT(9) 88 #define RT_D_CFG_RETIME_SHIFT 10 89 #define RT_D_CFG_RETIME_MASK BIT(10) 90 91 /* 92 * Pinconf is represented in an opaque unsigned long variable. 93 * Below is the bit allocation details for each possible configuration. 94 * All the bit fields can be encapsulated into four variables 95 * (direction, retime-type, retime-clk, retime-delay) 96 * 97 * +----------------+ 98 *[31:28]| reserved-3 | 99 * +----------------+------------- 100 *[27] | oe | | 101 * +----------------+ v 102 *[26] | pu | [Direction ] 103 * +----------------+ ^ 104 *[25] | od | | 105 * +----------------+------------- 106 *[24] | reserved-2 | 107 * +----------------+------------- 108 *[23] | retime | | 109 * +----------------+ | 110 *[22] | retime-invclk | | 111 * +----------------+ v 112 *[21] |retime-clknotdat| [Retime-type ] 113 * +----------------+ ^ 114 *[20] | retime-de | | 115 * +----------------+------------- 116 *[19:18]| retime-clk |------>[Retime-Clk ] 117 * +----------------+ 118 *[17:16]| reserved-1 | 119 * +----------------+ 120 *[15..0]| retime-delay |------>[Retime Delay] 121 * +----------------+ 122 */ 123 124 #define ST_PINCONF_UNPACK(conf, param)\ 125 ((conf >> ST_PINCONF_ ##param ##_SHIFT) \ 126 & ST_PINCONF_ ##param ##_MASK) 127 128 #define ST_PINCONF_PACK(conf, val, param) (conf |=\ 129 ((val & ST_PINCONF_ ##param ##_MASK) << \ 130 ST_PINCONF_ ##param ##_SHIFT)) 131 132 /* Output enable */ 133 #define ST_PINCONF_OE_MASK 0x1 134 #define ST_PINCONF_OE_SHIFT 27 135 #define ST_PINCONF_OE BIT(27) 136 #define ST_PINCONF_UNPACK_OE(conf) ST_PINCONF_UNPACK(conf, OE) 137 #define ST_PINCONF_PACK_OE(conf) ST_PINCONF_PACK(conf, 1, OE) 138 139 /* Pull Up */ 140 #define ST_PINCONF_PU_MASK 0x1 141 #define ST_PINCONF_PU_SHIFT 26 142 #define ST_PINCONF_PU BIT(26) 143 #define ST_PINCONF_UNPACK_PU(conf) ST_PINCONF_UNPACK(conf, PU) 144 #define ST_PINCONF_PACK_PU(conf) ST_PINCONF_PACK(conf, 1, PU) 145 146 /* Open Drain */ 147 #define ST_PINCONF_OD_MASK 0x1 148 #define ST_PINCONF_OD_SHIFT 25 149 #define ST_PINCONF_OD BIT(25) 150 #define ST_PINCONF_UNPACK_OD(conf) ST_PINCONF_UNPACK(conf, OD) 151 #define ST_PINCONF_PACK_OD(conf) ST_PINCONF_PACK(conf, 1, OD) 152 153 #define ST_PINCONF_RT_MASK 0x1 154 #define ST_PINCONF_RT_SHIFT 23 155 #define ST_PINCONF_RT BIT(23) 156 #define ST_PINCONF_UNPACK_RT(conf) ST_PINCONF_UNPACK(conf, RT) 157 #define ST_PINCONF_PACK_RT(conf) ST_PINCONF_PACK(conf, 1, RT) 158 159 #define ST_PINCONF_RT_INVERTCLK_MASK 0x1 160 #define ST_PINCONF_RT_INVERTCLK_SHIFT 22 161 #define ST_PINCONF_RT_INVERTCLK BIT(22) 162 #define ST_PINCONF_UNPACK_RT_INVERTCLK(conf) \ 163 ST_PINCONF_UNPACK(conf, RT_INVERTCLK) 164 #define ST_PINCONF_PACK_RT_INVERTCLK(conf) \ 165 ST_PINCONF_PACK(conf, 1, RT_INVERTCLK) 166 167 #define ST_PINCONF_RT_CLKNOTDATA_MASK 0x1 168 #define ST_PINCONF_RT_CLKNOTDATA_SHIFT 21 169 #define ST_PINCONF_RT_CLKNOTDATA BIT(21) 170 #define ST_PINCONF_UNPACK_RT_CLKNOTDATA(conf) \ 171 ST_PINCONF_UNPACK(conf, RT_CLKNOTDATA) 172 #define ST_PINCONF_PACK_RT_CLKNOTDATA(conf) \ 173 ST_PINCONF_PACK(conf, 1, RT_CLKNOTDATA) 174 175 #define ST_PINCONF_RT_DOUBLE_EDGE_MASK 0x1 176 #define ST_PINCONF_RT_DOUBLE_EDGE_SHIFT 20 177 #define ST_PINCONF_RT_DOUBLE_EDGE BIT(20) 178 #define ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(conf) \ 179 ST_PINCONF_UNPACK(conf, RT_DOUBLE_EDGE) 180 #define ST_PINCONF_PACK_RT_DOUBLE_EDGE(conf) \ 181 ST_PINCONF_PACK(conf, 1, RT_DOUBLE_EDGE) 182 183 #define ST_PINCONF_RT_CLK_MASK 0x3 184 #define ST_PINCONF_RT_CLK_SHIFT 18 185 #define ST_PINCONF_RT_CLK BIT(18) 186 #define ST_PINCONF_UNPACK_RT_CLK(conf) ST_PINCONF_UNPACK(conf, RT_CLK) 187 #define ST_PINCONF_PACK_RT_CLK(conf, val) ST_PINCONF_PACK(conf, val, RT_CLK) 188 189 /* RETIME_DELAY in Pico Secs */ 190 #define ST_PINCONF_RT_DELAY_MASK 0xffff 191 #define ST_PINCONF_RT_DELAY_SHIFT 0 192 #define ST_PINCONF_UNPACK_RT_DELAY(conf) ST_PINCONF_UNPACK(conf, RT_DELAY) 193 #define ST_PINCONF_PACK_RT_DELAY(conf, val) \ 194 ST_PINCONF_PACK(conf, val, RT_DELAY) 195 196 #define ST_GPIO_PINS_PER_BANK (8) 197 #define OF_GPIO_ARGS_MIN (4) 198 #define OF_RT_ARGS_MIN (2) 199 200 #define gpio_range_to_bank(chip) \ 201 container_of(chip, struct st_gpio_bank, range) 202 203 #define pc_to_bank(pc) \ 204 container_of(pc, struct st_gpio_bank, pc) 205 206 enum st_retime_style { 207 st_retime_style_none, 208 st_retime_style_packed, 209 st_retime_style_dedicated, 210 }; 211 212 struct st_retime_dedicated { 213 struct regmap_field *rt[ST_GPIO_PINS_PER_BANK]; 214 }; 215 216 struct st_retime_packed { 217 struct regmap_field *clk1notclk0; 218 struct regmap_field *delay_0; 219 struct regmap_field *delay_1; 220 struct regmap_field *invertclk; 221 struct regmap_field *retime; 222 struct regmap_field *clknotdata; 223 struct regmap_field *double_edge; 224 }; 225 226 struct st_pio_control { 227 u32 rt_pin_mask; 228 struct regmap_field *alt, *oe, *pu, *od; 229 /* retiming */ 230 union { 231 struct st_retime_packed rt_p; 232 struct st_retime_dedicated rt_d; 233 } rt; 234 }; 235 236 struct st_pctl_data { 237 const enum st_retime_style rt_style; 238 const unsigned int *input_delays; 239 const int ninput_delays; 240 const unsigned int *output_delays; 241 const int noutput_delays; 242 /* register offset information */ 243 const int alt, oe, pu, od, rt; 244 }; 245 246 struct st_pinconf { 247 int pin; 248 const char *name; 249 unsigned long config; 250 int altfunc; 251 }; 252 253 struct st_pmx_func { 254 const char *name; 255 const char **groups; 256 unsigned ngroups; 257 }; 258 259 struct st_pctl_group { 260 const char *name; 261 unsigned int *pins; 262 unsigned npins; 263 struct st_pinconf *pin_conf; 264 }; 265 266 /* 267 * Edge triggers are not supported at hardware level, it is supported by 268 * software by exploiting the level trigger support in hardware. 269 * Software uses a virtual register (EDGE_CONF) for edge trigger configuration 270 * of each gpio pin in a GPIO bank. 271 * 272 * Each bank has a 32 bit EDGE_CONF register which is divided in to 8 parts of 273 * 4-bits. Each 4-bit space is allocated for each pin in a gpio bank. 274 * 275 * bit allocation per pin is: 276 * Bits: [0 - 3] | [4 - 7] [8 - 11] ... ... ... ... [ 28 - 31] 277 * -------------------------------------------------------- 278 * | pin-0 | pin-2 | pin-3 | ... ... ... ... | pin -7 | 279 * -------------------------------------------------------- 280 * 281 * A pin can have one of following the values in its edge configuration field. 282 * 283 * ------- ---------------------------- 284 * [0-3] - Description 285 * ------- ---------------------------- 286 * 0000 - No edge IRQ. 287 * 0001 - Falling edge IRQ. 288 * 0010 - Rising edge IRQ. 289 * 0011 - Rising and Falling edge IRQ. 290 * ------- ---------------------------- 291 */ 292 293 #define ST_IRQ_EDGE_CONF_BITS_PER_PIN 4 294 #define ST_IRQ_EDGE_MASK 0xf 295 #define ST_IRQ_EDGE_FALLING BIT(0) 296 #define ST_IRQ_EDGE_RISING BIT(1) 297 #define ST_IRQ_EDGE_BOTH (BIT(0) | BIT(1)) 298 299 #define ST_IRQ_RISING_EDGE_CONF(pin) \ 300 (ST_IRQ_EDGE_RISING << (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN)) 301 302 #define ST_IRQ_FALLING_EDGE_CONF(pin) \ 303 (ST_IRQ_EDGE_FALLING << (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN)) 304 305 #define ST_IRQ_BOTH_EDGE_CONF(pin) \ 306 (ST_IRQ_EDGE_BOTH << (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN)) 307 308 #define ST_IRQ_EDGE_CONF(conf, pin) \ 309 (conf >> (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN) & ST_IRQ_EDGE_MASK) 310 311 struct st_gpio_bank { 312 struct gpio_chip gpio_chip; 313 struct pinctrl_gpio_range range; 314 void __iomem *base; 315 struct st_pio_control pc; 316 unsigned long irq_edge_conf; 317 spinlock_t lock; 318 }; 319 320 struct st_pinctrl { 321 struct device *dev; 322 struct pinctrl_dev *pctl; 323 struct st_gpio_bank *banks; 324 int nbanks; 325 struct st_pmx_func *functions; 326 int nfunctions; 327 struct st_pctl_group *groups; 328 int ngroups; 329 struct regmap *regmap; 330 const struct st_pctl_data *data; 331 void __iomem *irqmux_base; 332 }; 333 334 /* SOC specific data */ 335 336 static const unsigned int stih407_delays[] = {0, 300, 500, 750, 1000, 1250, 337 1500, 1750, 2000, 2250, 2500, 2750, 3000, 3250 }; 338 339 static const struct st_pctl_data stih407_data = { 340 .rt_style = st_retime_style_dedicated, 341 .input_delays = stih407_delays, 342 .ninput_delays = ARRAY_SIZE(stih407_delays), 343 .output_delays = stih407_delays, 344 .noutput_delays = ARRAY_SIZE(stih407_delays), 345 .alt = 0, .oe = 40, .pu = 50, .od = 60, .rt = 100, 346 }; 347 348 static const struct st_pctl_data stih407_flashdata = { 349 .rt_style = st_retime_style_none, 350 .input_delays = stih407_delays, 351 .ninput_delays = ARRAY_SIZE(stih407_delays), 352 .output_delays = stih407_delays, 353 .noutput_delays = ARRAY_SIZE(stih407_delays), 354 .alt = 0, 355 .oe = -1, /* Not Available */ 356 .pu = -1, /* Not Available */ 357 .od = 60, 358 .rt = 100, 359 }; 360 361 static struct st_pio_control *st_get_pio_control( 362 struct pinctrl_dev *pctldev, int pin) 363 { 364 struct pinctrl_gpio_range *range = 365 pinctrl_find_gpio_range_from_pin(pctldev, pin); 366 struct st_gpio_bank *bank = gpio_range_to_bank(range); 367 368 return &bank->pc; 369 } 370 371 /* Low level functions.. */ 372 static inline int st_gpio_bank(int gpio) 373 { 374 return gpio/ST_GPIO_PINS_PER_BANK; 375 } 376 377 static inline int st_gpio_pin(int gpio) 378 { 379 return gpio%ST_GPIO_PINS_PER_BANK; 380 } 381 382 static void st_pinconf_set_config(struct st_pio_control *pc, 383 int pin, unsigned long config) 384 { 385 struct regmap_field *output_enable = pc->oe; 386 struct regmap_field *pull_up = pc->pu; 387 struct regmap_field *open_drain = pc->od; 388 unsigned int oe_value, pu_value, od_value; 389 unsigned long mask = BIT(pin); 390 391 if (output_enable) { 392 regmap_field_read(output_enable, &oe_value); 393 oe_value &= ~mask; 394 if (config & ST_PINCONF_OE) 395 oe_value |= mask; 396 regmap_field_write(output_enable, oe_value); 397 } 398 399 if (pull_up) { 400 regmap_field_read(pull_up, &pu_value); 401 pu_value &= ~mask; 402 if (config & ST_PINCONF_PU) 403 pu_value |= mask; 404 regmap_field_write(pull_up, pu_value); 405 } 406 407 if (open_drain) { 408 regmap_field_read(open_drain, &od_value); 409 od_value &= ~mask; 410 if (config & ST_PINCONF_OD) 411 od_value |= mask; 412 regmap_field_write(open_drain, od_value); 413 } 414 } 415 416 static void st_pctl_set_function(struct st_pio_control *pc, 417 int pin_id, int function) 418 { 419 struct regmap_field *alt = pc->alt; 420 unsigned int val; 421 int pin = st_gpio_pin(pin_id); 422 int offset = pin * 4; 423 424 if (!alt) 425 return; 426 427 regmap_field_read(alt, &val); 428 val &= ~(0xf << offset); 429 val |= function << offset; 430 regmap_field_write(alt, val); 431 } 432 433 static unsigned int st_pctl_get_pin_function(struct st_pio_control *pc, int pin) 434 { 435 struct regmap_field *alt = pc->alt; 436 unsigned int val; 437 int offset = pin * 4; 438 439 if (!alt) 440 return 0; 441 442 regmap_field_read(alt, &val); 443 444 return (val >> offset) & 0xf; 445 } 446 447 static unsigned long st_pinconf_delay_to_bit(unsigned int delay, 448 const struct st_pctl_data *data, unsigned long config) 449 { 450 const unsigned int *delay_times; 451 int num_delay_times, i, closest_index = -1; 452 unsigned int closest_divergence = UINT_MAX; 453 454 if (ST_PINCONF_UNPACK_OE(config)) { 455 delay_times = data->output_delays; 456 num_delay_times = data->noutput_delays; 457 } else { 458 delay_times = data->input_delays; 459 num_delay_times = data->ninput_delays; 460 } 461 462 for (i = 0; i < num_delay_times; i++) { 463 unsigned int divergence = abs(delay - delay_times[i]); 464 465 if (divergence == 0) 466 return i; 467 468 if (divergence < closest_divergence) { 469 closest_divergence = divergence; 470 closest_index = i; 471 } 472 } 473 474 pr_warn("Attempt to set delay %d, closest available %d\n", 475 delay, delay_times[closest_index]); 476 477 return closest_index; 478 } 479 480 static unsigned long st_pinconf_bit_to_delay(unsigned int index, 481 const struct st_pctl_data *data, unsigned long output) 482 { 483 const unsigned int *delay_times; 484 int num_delay_times; 485 486 if (output) { 487 delay_times = data->output_delays; 488 num_delay_times = data->noutput_delays; 489 } else { 490 delay_times = data->input_delays; 491 num_delay_times = data->ninput_delays; 492 } 493 494 if (index < num_delay_times) { 495 return delay_times[index]; 496 } else { 497 pr_warn("Delay not found in/out delay list\n"); 498 return 0; 499 } 500 } 501 502 static void st_regmap_field_bit_set_clear_pin(struct regmap_field *field, 503 int enable, int pin) 504 { 505 unsigned int val = 0; 506 507 regmap_field_read(field, &val); 508 if (enable) 509 val |= BIT(pin); 510 else 511 val &= ~BIT(pin); 512 regmap_field_write(field, val); 513 } 514 515 static void st_pinconf_set_retime_packed(struct st_pinctrl *info, 516 struct st_pio_control *pc, unsigned long config, int pin) 517 { 518 const struct st_pctl_data *data = info->data; 519 struct st_retime_packed *rt_p = &pc->rt.rt_p; 520 unsigned int delay; 521 522 st_regmap_field_bit_set_clear_pin(rt_p->clk1notclk0, 523 ST_PINCONF_UNPACK_RT_CLK(config), pin); 524 525 st_regmap_field_bit_set_clear_pin(rt_p->clknotdata, 526 ST_PINCONF_UNPACK_RT_CLKNOTDATA(config), pin); 527 528 st_regmap_field_bit_set_clear_pin(rt_p->double_edge, 529 ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(config), pin); 530 531 st_regmap_field_bit_set_clear_pin(rt_p->invertclk, 532 ST_PINCONF_UNPACK_RT_INVERTCLK(config), pin); 533 534 st_regmap_field_bit_set_clear_pin(rt_p->retime, 535 ST_PINCONF_UNPACK_RT(config), pin); 536 537 delay = st_pinconf_delay_to_bit(ST_PINCONF_UNPACK_RT_DELAY(config), 538 data, config); 539 /* 2 bit delay, lsb */ 540 st_regmap_field_bit_set_clear_pin(rt_p->delay_0, delay & 0x1, pin); 541 /* 2 bit delay, msb */ 542 st_regmap_field_bit_set_clear_pin(rt_p->delay_1, delay & 0x2, pin); 543 544 } 545 546 static void st_pinconf_set_retime_dedicated(struct st_pinctrl *info, 547 struct st_pio_control *pc, unsigned long config, int pin) 548 { 549 int input = ST_PINCONF_UNPACK_OE(config) ? 0 : 1; 550 int clk = ST_PINCONF_UNPACK_RT_CLK(config); 551 int clknotdata = ST_PINCONF_UNPACK_RT_CLKNOTDATA(config); 552 int double_edge = ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(config); 553 int invertclk = ST_PINCONF_UNPACK_RT_INVERTCLK(config); 554 int retime = ST_PINCONF_UNPACK_RT(config); 555 556 unsigned long delay = st_pinconf_delay_to_bit( 557 ST_PINCONF_UNPACK_RT_DELAY(config), 558 info->data, config); 559 struct st_retime_dedicated *rt_d = &pc->rt.rt_d; 560 561 unsigned long retime_config = 562 ((clk) << RT_D_CFG_CLK_SHIFT) | 563 ((delay) << RT_D_CFG_DELAY_SHIFT) | 564 ((input) << RT_D_CFG_DELAY_INNOTOUT_SHIFT) | 565 ((retime) << RT_D_CFG_RETIME_SHIFT) | 566 ((clknotdata) << RT_D_CFG_CLKNOTDATA_SHIFT) | 567 ((invertclk) << RT_D_CFG_INVERTCLK_SHIFT) | 568 ((double_edge) << RT_D_CFG_DOUBLE_EDGE_SHIFT); 569 570 regmap_field_write(rt_d->rt[pin], retime_config); 571 } 572 573 static void st_pinconf_get_direction(struct st_pio_control *pc, 574 int pin, unsigned long *config) 575 { 576 unsigned int oe_value, pu_value, od_value; 577 578 if (pc->oe) { 579 regmap_field_read(pc->oe, &oe_value); 580 if (oe_value & BIT(pin)) 581 ST_PINCONF_PACK_OE(*config); 582 } 583 584 if (pc->pu) { 585 regmap_field_read(pc->pu, &pu_value); 586 if (pu_value & BIT(pin)) 587 ST_PINCONF_PACK_PU(*config); 588 } 589 590 if (pc->od) { 591 regmap_field_read(pc->od, &od_value); 592 if (od_value & BIT(pin)) 593 ST_PINCONF_PACK_OD(*config); 594 } 595 } 596 597 static int st_pinconf_get_retime_packed(struct st_pinctrl *info, 598 struct st_pio_control *pc, int pin, unsigned long *config) 599 { 600 const struct st_pctl_data *data = info->data; 601 struct st_retime_packed *rt_p = &pc->rt.rt_p; 602 unsigned int delay_bits, delay, delay0, delay1, val; 603 int output = ST_PINCONF_UNPACK_OE(*config); 604 605 if (!regmap_field_read(rt_p->retime, &val) && (val & BIT(pin))) 606 ST_PINCONF_PACK_RT(*config); 607 608 if (!regmap_field_read(rt_p->clk1notclk0, &val) && (val & BIT(pin))) 609 ST_PINCONF_PACK_RT_CLK(*config, 1); 610 611 if (!regmap_field_read(rt_p->clknotdata, &val) && (val & BIT(pin))) 612 ST_PINCONF_PACK_RT_CLKNOTDATA(*config); 613 614 if (!regmap_field_read(rt_p->double_edge, &val) && (val & BIT(pin))) 615 ST_PINCONF_PACK_RT_DOUBLE_EDGE(*config); 616 617 if (!regmap_field_read(rt_p->invertclk, &val) && (val & BIT(pin))) 618 ST_PINCONF_PACK_RT_INVERTCLK(*config); 619 620 regmap_field_read(rt_p->delay_0, &delay0); 621 regmap_field_read(rt_p->delay_1, &delay1); 622 delay_bits = (((delay1 & BIT(pin)) ? 1 : 0) << 1) | 623 (((delay0 & BIT(pin)) ? 1 : 0)); 624 delay = st_pinconf_bit_to_delay(delay_bits, data, output); 625 ST_PINCONF_PACK_RT_DELAY(*config, delay); 626 627 return 0; 628 } 629 630 static int st_pinconf_get_retime_dedicated(struct st_pinctrl *info, 631 struct st_pio_control *pc, int pin, unsigned long *config) 632 { 633 unsigned int value; 634 unsigned long delay_bits, delay, rt_clk; 635 int output = ST_PINCONF_UNPACK_OE(*config); 636 struct st_retime_dedicated *rt_d = &pc->rt.rt_d; 637 638 regmap_field_read(rt_d->rt[pin], &value); 639 640 rt_clk = (value & RT_D_CFG_CLK_MASK) >> RT_D_CFG_CLK_SHIFT; 641 ST_PINCONF_PACK_RT_CLK(*config, rt_clk); 642 643 delay_bits = (value & RT_D_CFG_DELAY_MASK) >> RT_D_CFG_DELAY_SHIFT; 644 delay = st_pinconf_bit_to_delay(delay_bits, info->data, output); 645 ST_PINCONF_PACK_RT_DELAY(*config, delay); 646 647 if (value & RT_D_CFG_CLKNOTDATA_MASK) 648 ST_PINCONF_PACK_RT_CLKNOTDATA(*config); 649 650 if (value & RT_D_CFG_DOUBLE_EDGE_MASK) 651 ST_PINCONF_PACK_RT_DOUBLE_EDGE(*config); 652 653 if (value & RT_D_CFG_INVERTCLK_MASK) 654 ST_PINCONF_PACK_RT_INVERTCLK(*config); 655 656 if (value & RT_D_CFG_RETIME_MASK) 657 ST_PINCONF_PACK_RT(*config); 658 659 return 0; 660 } 661 662 /* GPIO related functions */ 663 664 static inline void __st_gpio_set(struct st_gpio_bank *bank, 665 unsigned offset, int value) 666 { 667 if (value) 668 writel(BIT(offset), bank->base + REG_PIO_SET_POUT); 669 else 670 writel(BIT(offset), bank->base + REG_PIO_CLR_POUT); 671 } 672 673 static void st_gpio_direction(struct st_gpio_bank *bank, 674 unsigned int gpio, unsigned int direction) 675 { 676 int offset = st_gpio_pin(gpio); 677 int i = 0; 678 /** 679 * There are three configuration registers (PIOn_PC0, PIOn_PC1 680 * and PIOn_PC2) for each port. These are used to configure the 681 * PIO port pins. Each pin can be configured as an input, output, 682 * bidirectional, or alternative function pin. Three bits, one bit 683 * from each of the three registers, configure the corresponding bit of 684 * the port. Valid bit settings is: 685 * 686 * PC2 PC1 PC0 Direction. 687 * 0 0 0 [Input Weak pull-up] 688 * 0 0 or 1 1 [Bidirection] 689 * 0 1 0 [Output] 690 * 1 0 0 [Input] 691 * 692 * PIOn_SET_PC and PIOn_CLR_PC registers are used to set and clear bits 693 * individually. 694 */ 695 for (i = 0; i <= 2; i++) { 696 if (direction & BIT(i)) 697 writel(BIT(offset), bank->base + REG_PIO_SET_PC(i)); 698 else 699 writel(BIT(offset), bank->base + REG_PIO_CLR_PC(i)); 700 } 701 } 702 703 static int st_gpio_get(struct gpio_chip *chip, unsigned offset) 704 { 705 struct st_gpio_bank *bank = gpiochip_get_data(chip); 706 707 return !!(readl(bank->base + REG_PIO_PIN) & BIT(offset)); 708 } 709 710 static void st_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 711 { 712 struct st_gpio_bank *bank = gpiochip_get_data(chip); 713 __st_gpio_set(bank, offset, value); 714 } 715 716 static int st_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 717 { 718 pinctrl_gpio_direction_input(chip->base + offset); 719 720 return 0; 721 } 722 723 static int st_gpio_direction_output(struct gpio_chip *chip, 724 unsigned offset, int value) 725 { 726 struct st_gpio_bank *bank = gpiochip_get_data(chip); 727 728 __st_gpio_set(bank, offset, value); 729 pinctrl_gpio_direction_output(chip->base + offset); 730 731 return 0; 732 } 733 734 static int st_gpio_get_direction(struct gpio_chip *chip, unsigned offset) 735 { 736 struct st_gpio_bank *bank = gpiochip_get_data(chip); 737 struct st_pio_control pc = bank->pc; 738 unsigned long config; 739 unsigned int direction = 0; 740 unsigned int function; 741 unsigned int value; 742 int i = 0; 743 744 /* Alternate function direction is handled by Pinctrl */ 745 function = st_pctl_get_pin_function(&pc, offset); 746 if (function) { 747 st_pinconf_get_direction(&pc, offset, &config); 748 return !ST_PINCONF_UNPACK_OE(config); 749 } 750 751 /* 752 * GPIO direction is handled differently 753 * - See st_gpio_direction() above for an explanation 754 */ 755 for (i = 0; i <= 2; i++) { 756 value = readl(bank->base + REG_PIO_PC(i)); 757 direction |= ((value >> offset) & 0x1) << i; 758 } 759 760 return (direction == ST_GPIO_DIRECTION_IN); 761 } 762 763 /* Pinctrl Groups */ 764 static int st_pctl_get_groups_count(struct pinctrl_dev *pctldev) 765 { 766 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 767 768 return info->ngroups; 769 } 770 771 static const char *st_pctl_get_group_name(struct pinctrl_dev *pctldev, 772 unsigned selector) 773 { 774 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 775 776 return info->groups[selector].name; 777 } 778 779 static int st_pctl_get_group_pins(struct pinctrl_dev *pctldev, 780 unsigned selector, const unsigned **pins, unsigned *npins) 781 { 782 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 783 784 if (selector >= info->ngroups) 785 return -EINVAL; 786 787 *pins = info->groups[selector].pins; 788 *npins = info->groups[selector].npins; 789 790 return 0; 791 } 792 793 static inline const struct st_pctl_group *st_pctl_find_group_by_name( 794 const struct st_pinctrl *info, const char *name) 795 { 796 int i; 797 798 for (i = 0; i < info->ngroups; i++) { 799 if (!strcmp(info->groups[i].name, name)) 800 return &info->groups[i]; 801 } 802 803 return NULL; 804 } 805 806 static int st_pctl_dt_node_to_map(struct pinctrl_dev *pctldev, 807 struct device_node *np, struct pinctrl_map **map, unsigned *num_maps) 808 { 809 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 810 const struct st_pctl_group *grp; 811 struct pinctrl_map *new_map; 812 struct device_node *parent; 813 int map_num, i; 814 815 grp = st_pctl_find_group_by_name(info, np->name); 816 if (!grp) { 817 dev_err(info->dev, "unable to find group for node %pOFn\n", 818 np); 819 return -EINVAL; 820 } 821 822 map_num = grp->npins + 1; 823 new_map = devm_kcalloc(pctldev->dev, 824 map_num, sizeof(*new_map), GFP_KERNEL); 825 if (!new_map) 826 return -ENOMEM; 827 828 parent = of_get_parent(np); 829 if (!parent) { 830 devm_kfree(pctldev->dev, new_map); 831 return -EINVAL; 832 } 833 834 *map = new_map; 835 *num_maps = map_num; 836 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP; 837 new_map[0].data.mux.function = parent->name; 838 new_map[0].data.mux.group = np->name; 839 of_node_put(parent); 840 841 /* create config map per pin */ 842 new_map++; 843 for (i = 0; i < grp->npins; i++) { 844 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN; 845 new_map[i].data.configs.group_or_pin = 846 pin_get_name(pctldev, grp->pins[i]); 847 new_map[i].data.configs.configs = &grp->pin_conf[i].config; 848 new_map[i].data.configs.num_configs = 1; 849 } 850 dev_info(pctldev->dev, "maps: function %s group %s num %d\n", 851 (*map)->data.mux.function, grp->name, map_num); 852 853 return 0; 854 } 855 856 static void st_pctl_dt_free_map(struct pinctrl_dev *pctldev, 857 struct pinctrl_map *map, unsigned num_maps) 858 { 859 } 860 861 static const struct pinctrl_ops st_pctlops = { 862 .get_groups_count = st_pctl_get_groups_count, 863 .get_group_pins = st_pctl_get_group_pins, 864 .get_group_name = st_pctl_get_group_name, 865 .dt_node_to_map = st_pctl_dt_node_to_map, 866 .dt_free_map = st_pctl_dt_free_map, 867 }; 868 869 /* Pinmux */ 870 static int st_pmx_get_funcs_count(struct pinctrl_dev *pctldev) 871 { 872 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 873 874 return info->nfunctions; 875 } 876 877 static const char *st_pmx_get_fname(struct pinctrl_dev *pctldev, 878 unsigned selector) 879 { 880 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 881 882 return info->functions[selector].name; 883 } 884 885 static int st_pmx_get_groups(struct pinctrl_dev *pctldev, 886 unsigned selector, const char * const **grps, unsigned * const ngrps) 887 { 888 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 889 *grps = info->functions[selector].groups; 890 *ngrps = info->functions[selector].ngroups; 891 892 return 0; 893 } 894 895 static int st_pmx_set_mux(struct pinctrl_dev *pctldev, unsigned fselector, 896 unsigned group) 897 { 898 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 899 struct st_pinconf *conf = info->groups[group].pin_conf; 900 struct st_pio_control *pc; 901 int i; 902 903 for (i = 0; i < info->groups[group].npins; i++) { 904 pc = st_get_pio_control(pctldev, conf[i].pin); 905 st_pctl_set_function(pc, conf[i].pin, conf[i].altfunc); 906 } 907 908 return 0; 909 } 910 911 static int st_pmx_set_gpio_direction(struct pinctrl_dev *pctldev, 912 struct pinctrl_gpio_range *range, unsigned gpio, 913 bool input) 914 { 915 struct st_gpio_bank *bank = gpio_range_to_bank(range); 916 /* 917 * When a PIO bank is used in its primary function mode (altfunc = 0) 918 * Output Enable (OE), Open Drain(OD), and Pull Up (PU) 919 * for the primary PIO functions are driven by the related PIO block 920 */ 921 st_pctl_set_function(&bank->pc, gpio, 0); 922 st_gpio_direction(bank, gpio, input ? 923 ST_GPIO_DIRECTION_IN : ST_GPIO_DIRECTION_OUT); 924 925 return 0; 926 } 927 928 static const struct pinmux_ops st_pmxops = { 929 .get_functions_count = st_pmx_get_funcs_count, 930 .get_function_name = st_pmx_get_fname, 931 .get_function_groups = st_pmx_get_groups, 932 .set_mux = st_pmx_set_mux, 933 .gpio_set_direction = st_pmx_set_gpio_direction, 934 .strict = true, 935 }; 936 937 /* Pinconf */ 938 static void st_pinconf_get_retime(struct st_pinctrl *info, 939 struct st_pio_control *pc, int pin, unsigned long *config) 940 { 941 if (info->data->rt_style == st_retime_style_packed) 942 st_pinconf_get_retime_packed(info, pc, pin, config); 943 else if (info->data->rt_style == st_retime_style_dedicated) 944 if ((BIT(pin) & pc->rt_pin_mask)) 945 st_pinconf_get_retime_dedicated(info, pc, 946 pin, config); 947 } 948 949 static void st_pinconf_set_retime(struct st_pinctrl *info, 950 struct st_pio_control *pc, int pin, unsigned long config) 951 { 952 if (info->data->rt_style == st_retime_style_packed) 953 st_pinconf_set_retime_packed(info, pc, config, pin); 954 else if (info->data->rt_style == st_retime_style_dedicated) 955 if ((BIT(pin) & pc->rt_pin_mask)) 956 st_pinconf_set_retime_dedicated(info, pc, 957 config, pin); 958 } 959 960 static int st_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin_id, 961 unsigned long *configs, unsigned num_configs) 962 { 963 int pin = st_gpio_pin(pin_id); 964 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 965 struct st_pio_control *pc = st_get_pio_control(pctldev, pin_id); 966 int i; 967 968 for (i = 0; i < num_configs; i++) { 969 st_pinconf_set_config(pc, pin, configs[i]); 970 st_pinconf_set_retime(info, pc, pin, configs[i]); 971 } /* for each config */ 972 973 return 0; 974 } 975 976 static int st_pinconf_get(struct pinctrl_dev *pctldev, 977 unsigned pin_id, unsigned long *config) 978 { 979 int pin = st_gpio_pin(pin_id); 980 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 981 struct st_pio_control *pc = st_get_pio_control(pctldev, pin_id); 982 983 *config = 0; 984 st_pinconf_get_direction(pc, pin, config); 985 st_pinconf_get_retime(info, pc, pin, config); 986 987 return 0; 988 } 989 990 static void st_pinconf_dbg_show(struct pinctrl_dev *pctldev, 991 struct seq_file *s, unsigned pin_id) 992 { 993 struct st_pio_control *pc; 994 unsigned long config; 995 unsigned int function; 996 int offset = st_gpio_pin(pin_id); 997 char f[16]; 998 999 mutex_unlock(&pctldev->mutex); 1000 pc = st_get_pio_control(pctldev, pin_id); 1001 st_pinconf_get(pctldev, pin_id, &config); 1002 mutex_lock(&pctldev->mutex); 1003 1004 function = st_pctl_get_pin_function(pc, offset); 1005 if (function) 1006 snprintf(f, 10, "Alt Fn %u", function); 1007 else 1008 snprintf(f, 5, "GPIO"); 1009 1010 seq_printf(s, "[OE:%d,PU:%ld,OD:%ld]\t%s\n" 1011 "\t\t[retime:%ld,invclk:%ld,clknotdat:%ld," 1012 "de:%ld,rt-clk:%ld,rt-delay:%ld]", 1013 !st_gpio_get_direction(&pc_to_bank(pc)->gpio_chip, offset), 1014 ST_PINCONF_UNPACK_PU(config), 1015 ST_PINCONF_UNPACK_OD(config), 1016 f, 1017 ST_PINCONF_UNPACK_RT(config), 1018 ST_PINCONF_UNPACK_RT_INVERTCLK(config), 1019 ST_PINCONF_UNPACK_RT_CLKNOTDATA(config), 1020 ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(config), 1021 ST_PINCONF_UNPACK_RT_CLK(config), 1022 ST_PINCONF_UNPACK_RT_DELAY(config)); 1023 } 1024 1025 static const struct pinconf_ops st_confops = { 1026 .pin_config_get = st_pinconf_get, 1027 .pin_config_set = st_pinconf_set, 1028 .pin_config_dbg_show = st_pinconf_dbg_show, 1029 }; 1030 1031 static void st_pctl_dt_child_count(struct st_pinctrl *info, 1032 struct device_node *np) 1033 { 1034 struct device_node *child; 1035 for_each_child_of_node(np, child) { 1036 if (of_property_read_bool(child, "gpio-controller")) { 1037 info->nbanks++; 1038 } else { 1039 info->nfunctions++; 1040 info->ngroups += of_get_child_count(child); 1041 } 1042 } 1043 } 1044 1045 static int st_pctl_dt_setup_retime_packed(struct st_pinctrl *info, 1046 int bank, struct st_pio_control *pc) 1047 { 1048 struct device *dev = info->dev; 1049 struct regmap *rm = info->regmap; 1050 const struct st_pctl_data *data = info->data; 1051 /* 2 registers per bank */ 1052 int reg = (data->rt + bank * RT_P_CFGS_PER_BANK) * 4; 1053 struct st_retime_packed *rt_p = &pc->rt.rt_p; 1054 /* cfg0 */ 1055 struct reg_field clk1notclk0 = RT_P_CFG0_CLK1NOTCLK0_FIELD(reg); 1056 struct reg_field delay_0 = RT_P_CFG0_DELAY_0_FIELD(reg); 1057 struct reg_field delay_1 = RT_P_CFG0_DELAY_1_FIELD(reg); 1058 /* cfg1 */ 1059 struct reg_field invertclk = RT_P_CFG1_INVERTCLK_FIELD(reg + 4); 1060 struct reg_field retime = RT_P_CFG1_RETIME_FIELD(reg + 4); 1061 struct reg_field clknotdata = RT_P_CFG1_CLKNOTDATA_FIELD(reg + 4); 1062 struct reg_field double_edge = RT_P_CFG1_DOUBLE_EDGE_FIELD(reg + 4); 1063 1064 rt_p->clk1notclk0 = devm_regmap_field_alloc(dev, rm, clk1notclk0); 1065 rt_p->delay_0 = devm_regmap_field_alloc(dev, rm, delay_0); 1066 rt_p->delay_1 = devm_regmap_field_alloc(dev, rm, delay_1); 1067 rt_p->invertclk = devm_regmap_field_alloc(dev, rm, invertclk); 1068 rt_p->retime = devm_regmap_field_alloc(dev, rm, retime); 1069 rt_p->clknotdata = devm_regmap_field_alloc(dev, rm, clknotdata); 1070 rt_p->double_edge = devm_regmap_field_alloc(dev, rm, double_edge); 1071 1072 if (IS_ERR(rt_p->clk1notclk0) || IS_ERR(rt_p->delay_0) || 1073 IS_ERR(rt_p->delay_1) || IS_ERR(rt_p->invertclk) || 1074 IS_ERR(rt_p->retime) || IS_ERR(rt_p->clknotdata) || 1075 IS_ERR(rt_p->double_edge)) 1076 return -EINVAL; 1077 1078 return 0; 1079 } 1080 1081 static int st_pctl_dt_setup_retime_dedicated(struct st_pinctrl *info, 1082 int bank, struct st_pio_control *pc) 1083 { 1084 struct device *dev = info->dev; 1085 struct regmap *rm = info->regmap; 1086 const struct st_pctl_data *data = info->data; 1087 /* 8 registers per bank */ 1088 int reg_offset = (data->rt + bank * RT_D_CFGS_PER_BANK) * 4; 1089 struct st_retime_dedicated *rt_d = &pc->rt.rt_d; 1090 unsigned int j; 1091 u32 pin_mask = pc->rt_pin_mask; 1092 1093 for (j = 0; j < RT_D_CFGS_PER_BANK; j++) { 1094 if (BIT(j) & pin_mask) { 1095 struct reg_field reg = REG_FIELD(reg_offset, 0, 31); 1096 rt_d->rt[j] = devm_regmap_field_alloc(dev, rm, reg); 1097 if (IS_ERR(rt_d->rt[j])) 1098 return -EINVAL; 1099 reg_offset += 4; 1100 } 1101 } 1102 return 0; 1103 } 1104 1105 static int st_pctl_dt_setup_retime(struct st_pinctrl *info, 1106 int bank, struct st_pio_control *pc) 1107 { 1108 const struct st_pctl_data *data = info->data; 1109 if (data->rt_style == st_retime_style_packed) 1110 return st_pctl_dt_setup_retime_packed(info, bank, pc); 1111 else if (data->rt_style == st_retime_style_dedicated) 1112 return st_pctl_dt_setup_retime_dedicated(info, bank, pc); 1113 1114 return -EINVAL; 1115 } 1116 1117 1118 static struct regmap_field *st_pc_get_value(struct device *dev, 1119 struct regmap *regmap, int bank, 1120 int data, int lsb, int msb) 1121 { 1122 struct reg_field reg = REG_FIELD((data + bank) * 4, lsb, msb); 1123 1124 if (data < 0) 1125 return NULL; 1126 1127 return devm_regmap_field_alloc(dev, regmap, reg); 1128 } 1129 1130 static void st_parse_syscfgs(struct st_pinctrl *info, int bank, 1131 struct device_node *np) 1132 { 1133 const struct st_pctl_data *data = info->data; 1134 /** 1135 * For a given shared register like OE/PU/OD, there are 8 bits per bank 1136 * 0:7 belongs to bank0, 8:15 belongs to bank1 ... 1137 * So each register is shared across 4 banks. 1138 */ 1139 int lsb = (bank%4) * ST_GPIO_PINS_PER_BANK; 1140 int msb = lsb + ST_GPIO_PINS_PER_BANK - 1; 1141 struct st_pio_control *pc = &info->banks[bank].pc; 1142 struct device *dev = info->dev; 1143 struct regmap *regmap = info->regmap; 1144 1145 pc->alt = st_pc_get_value(dev, regmap, bank, data->alt, 0, 31); 1146 pc->oe = st_pc_get_value(dev, regmap, bank/4, data->oe, lsb, msb); 1147 pc->pu = st_pc_get_value(dev, regmap, bank/4, data->pu, lsb, msb); 1148 pc->od = st_pc_get_value(dev, regmap, bank/4, data->od, lsb, msb); 1149 1150 /* retime avaiable for all pins by default */ 1151 pc->rt_pin_mask = 0xff; 1152 of_property_read_u32(np, "st,retime-pin-mask", &pc->rt_pin_mask); 1153 st_pctl_dt_setup_retime(info, bank, pc); 1154 1155 return; 1156 } 1157 1158 /* 1159 * Each pin is represented in of the below forms. 1160 * <bank offset mux direction rt_type rt_delay rt_clk> 1161 */ 1162 static int st_pctl_dt_parse_groups(struct device_node *np, 1163 struct st_pctl_group *grp, struct st_pinctrl *info, int idx) 1164 { 1165 /* bank pad direction val altfunction */ 1166 const __be32 *list; 1167 struct property *pp; 1168 struct st_pinconf *conf; 1169 struct device_node *pins; 1170 int i = 0, npins = 0, nr_props, ret = 0; 1171 1172 pins = of_get_child_by_name(np, "st,pins"); 1173 if (!pins) 1174 return -ENODATA; 1175 1176 for_each_property_of_node(pins, pp) { 1177 /* Skip those we do not want to proceed */ 1178 if (!strcmp(pp->name, "name")) 1179 continue; 1180 1181 if (pp->length / sizeof(__be32) >= OF_GPIO_ARGS_MIN) { 1182 npins++; 1183 } else { 1184 pr_warn("Invalid st,pins in %pOFn node\n", np); 1185 ret = -EINVAL; 1186 goto out_put_node; 1187 } 1188 } 1189 1190 grp->npins = npins; 1191 grp->name = np->name; 1192 grp->pins = devm_kcalloc(info->dev, npins, sizeof(u32), GFP_KERNEL); 1193 grp->pin_conf = devm_kcalloc(info->dev, 1194 npins, sizeof(*conf), GFP_KERNEL); 1195 1196 if (!grp->pins || !grp->pin_conf) { 1197 ret = -ENOMEM; 1198 goto out_put_node; 1199 } 1200 1201 /* <bank offset mux direction rt_type rt_delay rt_clk> */ 1202 for_each_property_of_node(pins, pp) { 1203 if (!strcmp(pp->name, "name")) 1204 continue; 1205 nr_props = pp->length/sizeof(u32); 1206 list = pp->value; 1207 conf = &grp->pin_conf[i]; 1208 1209 /* bank & offset */ 1210 be32_to_cpup(list++); 1211 be32_to_cpup(list++); 1212 conf->pin = of_get_named_gpio(pins, pp->name, 0); 1213 conf->name = pp->name; 1214 grp->pins[i] = conf->pin; 1215 /* mux */ 1216 conf->altfunc = be32_to_cpup(list++); 1217 conf->config = 0; 1218 /* direction */ 1219 conf->config |= be32_to_cpup(list++); 1220 /* rt_type rt_delay rt_clk */ 1221 if (nr_props >= OF_GPIO_ARGS_MIN + OF_RT_ARGS_MIN) { 1222 /* rt_type */ 1223 conf->config |= be32_to_cpup(list++); 1224 /* rt_delay */ 1225 conf->config |= be32_to_cpup(list++); 1226 /* rt_clk */ 1227 if (nr_props > OF_GPIO_ARGS_MIN + OF_RT_ARGS_MIN) 1228 conf->config |= be32_to_cpup(list++); 1229 } 1230 i++; 1231 } 1232 1233 out_put_node: 1234 of_node_put(pins); 1235 1236 return ret; 1237 } 1238 1239 static int st_pctl_parse_functions(struct device_node *np, 1240 struct st_pinctrl *info, u32 index, int *grp_index) 1241 { 1242 struct device_node *child; 1243 struct st_pmx_func *func; 1244 struct st_pctl_group *grp; 1245 int ret, i; 1246 1247 func = &info->functions[index]; 1248 func->name = np->name; 1249 func->ngroups = of_get_child_count(np); 1250 if (func->ngroups == 0) { 1251 dev_err(info->dev, "No groups defined\n"); 1252 return -EINVAL; 1253 } 1254 func->groups = devm_kcalloc(info->dev, 1255 func->ngroups, sizeof(char *), GFP_KERNEL); 1256 if (!func->groups) 1257 return -ENOMEM; 1258 1259 i = 0; 1260 for_each_child_of_node(np, child) { 1261 func->groups[i] = child->name; 1262 grp = &info->groups[*grp_index]; 1263 *grp_index += 1; 1264 ret = st_pctl_dt_parse_groups(child, grp, info, i++); 1265 if (ret) 1266 return ret; 1267 } 1268 dev_info(info->dev, "Function[%d\t name:%s,\tgroups:%d]\n", 1269 index, func->name, func->ngroups); 1270 1271 return 0; 1272 } 1273 1274 static void st_gpio_irq_mask(struct irq_data *d) 1275 { 1276 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1277 struct st_gpio_bank *bank = gpiochip_get_data(gc); 1278 1279 writel(BIT(d->hwirq), bank->base + REG_PIO_CLR_PMASK); 1280 } 1281 1282 static void st_gpio_irq_unmask(struct irq_data *d) 1283 { 1284 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1285 struct st_gpio_bank *bank = gpiochip_get_data(gc); 1286 1287 writel(BIT(d->hwirq), bank->base + REG_PIO_SET_PMASK); 1288 } 1289 1290 static int st_gpio_irq_request_resources(struct irq_data *d) 1291 { 1292 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1293 1294 st_gpio_direction_input(gc, d->hwirq); 1295 1296 return gpiochip_lock_as_irq(gc, d->hwirq); 1297 } 1298 1299 static void st_gpio_irq_release_resources(struct irq_data *d) 1300 { 1301 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1302 1303 gpiochip_unlock_as_irq(gc, d->hwirq); 1304 } 1305 1306 static int st_gpio_irq_set_type(struct irq_data *d, unsigned type) 1307 { 1308 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1309 struct st_gpio_bank *bank = gpiochip_get_data(gc); 1310 unsigned long flags; 1311 int comp, pin = d->hwirq; 1312 u32 val; 1313 u32 pin_edge_conf = 0; 1314 1315 switch (type) { 1316 case IRQ_TYPE_LEVEL_HIGH: 1317 comp = 0; 1318 break; 1319 case IRQ_TYPE_EDGE_FALLING: 1320 comp = 0; 1321 pin_edge_conf = ST_IRQ_FALLING_EDGE_CONF(pin); 1322 break; 1323 case IRQ_TYPE_LEVEL_LOW: 1324 comp = 1; 1325 break; 1326 case IRQ_TYPE_EDGE_RISING: 1327 comp = 1; 1328 pin_edge_conf = ST_IRQ_RISING_EDGE_CONF(pin); 1329 break; 1330 case IRQ_TYPE_EDGE_BOTH: 1331 comp = st_gpio_get(&bank->gpio_chip, pin); 1332 pin_edge_conf = ST_IRQ_BOTH_EDGE_CONF(pin); 1333 break; 1334 default: 1335 return -EINVAL; 1336 } 1337 1338 spin_lock_irqsave(&bank->lock, flags); 1339 bank->irq_edge_conf &= ~(ST_IRQ_EDGE_MASK << ( 1340 pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN)); 1341 bank->irq_edge_conf |= pin_edge_conf; 1342 spin_unlock_irqrestore(&bank->lock, flags); 1343 1344 val = readl(bank->base + REG_PIO_PCOMP); 1345 val &= ~BIT(pin); 1346 val |= (comp << pin); 1347 writel(val, bank->base + REG_PIO_PCOMP); 1348 1349 return 0; 1350 } 1351 1352 /* 1353 * As edge triggers are not supported at hardware level, it is supported by 1354 * software by exploiting the level trigger support in hardware. 1355 * 1356 * Steps for detection raising edge interrupt in software. 1357 * 1358 * Step 1: CONFIGURE pin to detect level LOW interrupts. 1359 * 1360 * Step 2: DETECT level LOW interrupt and in irqmux/gpio bank interrupt handler, 1361 * if the value of pin is low, then CONFIGURE pin for level HIGH interrupt. 1362 * IGNORE calling the actual interrupt handler for the pin at this stage. 1363 * 1364 * Step 3: DETECT level HIGH interrupt and in irqmux/gpio-bank interrupt handler 1365 * if the value of pin is HIGH, CONFIGURE pin for level LOW interrupt and then 1366 * DISPATCH the interrupt to the interrupt handler of the pin. 1367 * 1368 * step-1 ________ __________ 1369 * | | step - 3 1370 * | | 1371 * step -2 |_____| 1372 * 1373 * falling edge is also detected int the same way. 1374 * 1375 */ 1376 static void __gpio_irq_handler(struct st_gpio_bank *bank) 1377 { 1378 unsigned long port_in, port_mask, port_comp, active_irqs; 1379 unsigned long bank_edge_mask, flags; 1380 int n, val, ecfg; 1381 1382 spin_lock_irqsave(&bank->lock, flags); 1383 bank_edge_mask = bank->irq_edge_conf; 1384 spin_unlock_irqrestore(&bank->lock, flags); 1385 1386 for (;;) { 1387 port_in = readl(bank->base + REG_PIO_PIN); 1388 port_comp = readl(bank->base + REG_PIO_PCOMP); 1389 port_mask = readl(bank->base + REG_PIO_PMASK); 1390 1391 active_irqs = (port_in ^ port_comp) & port_mask; 1392 1393 if (active_irqs == 0) 1394 break; 1395 1396 for_each_set_bit(n, &active_irqs, BITS_PER_LONG) { 1397 /* check if we are detecting fake edges ... */ 1398 ecfg = ST_IRQ_EDGE_CONF(bank_edge_mask, n); 1399 1400 if (ecfg) { 1401 /* edge detection. */ 1402 val = st_gpio_get(&bank->gpio_chip, n); 1403 1404 writel(BIT(n), 1405 val ? bank->base + REG_PIO_SET_PCOMP : 1406 bank->base + REG_PIO_CLR_PCOMP); 1407 1408 if (ecfg != ST_IRQ_EDGE_BOTH && 1409 !((ecfg & ST_IRQ_EDGE_FALLING) ^ val)) 1410 continue; 1411 } 1412 1413 generic_handle_irq(irq_find_mapping(bank->gpio_chip.irq.domain, n)); 1414 } 1415 } 1416 } 1417 1418 static void st_gpio_irq_handler(struct irq_desc *desc) 1419 { 1420 /* interrupt dedicated per bank */ 1421 struct irq_chip *chip = irq_desc_get_chip(desc); 1422 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 1423 struct st_gpio_bank *bank = gpiochip_get_data(gc); 1424 1425 chained_irq_enter(chip, desc); 1426 __gpio_irq_handler(bank); 1427 chained_irq_exit(chip, desc); 1428 } 1429 1430 static void st_gpio_irqmux_handler(struct irq_desc *desc) 1431 { 1432 struct irq_chip *chip = irq_desc_get_chip(desc); 1433 struct st_pinctrl *info = irq_desc_get_handler_data(desc); 1434 unsigned long status; 1435 int n; 1436 1437 chained_irq_enter(chip, desc); 1438 1439 status = readl(info->irqmux_base); 1440 1441 for_each_set_bit(n, &status, info->nbanks) 1442 __gpio_irq_handler(&info->banks[n]); 1443 1444 chained_irq_exit(chip, desc); 1445 } 1446 1447 static const struct gpio_chip st_gpio_template = { 1448 .request = gpiochip_generic_request, 1449 .free = gpiochip_generic_free, 1450 .get = st_gpio_get, 1451 .set = st_gpio_set, 1452 .direction_input = st_gpio_direction_input, 1453 .direction_output = st_gpio_direction_output, 1454 .get_direction = st_gpio_get_direction, 1455 .ngpio = ST_GPIO_PINS_PER_BANK, 1456 }; 1457 1458 static struct irq_chip st_gpio_irqchip = { 1459 .name = "GPIO", 1460 .irq_request_resources = st_gpio_irq_request_resources, 1461 .irq_release_resources = st_gpio_irq_release_resources, 1462 .irq_disable = st_gpio_irq_mask, 1463 .irq_mask = st_gpio_irq_mask, 1464 .irq_unmask = st_gpio_irq_unmask, 1465 .irq_set_type = st_gpio_irq_set_type, 1466 .flags = IRQCHIP_SKIP_SET_WAKE, 1467 }; 1468 1469 static int st_gpiolib_register_bank(struct st_pinctrl *info, 1470 int bank_nr, struct device_node *np) 1471 { 1472 struct st_gpio_bank *bank = &info->banks[bank_nr]; 1473 struct pinctrl_gpio_range *range = &bank->range; 1474 struct device *dev = info->dev; 1475 int bank_num = of_alias_get_id(np, "gpio"); 1476 struct resource res, irq_res; 1477 int gpio_irq = 0, err; 1478 1479 if (of_address_to_resource(np, 0, &res)) 1480 return -ENODEV; 1481 1482 bank->base = devm_ioremap_resource(dev, &res); 1483 if (IS_ERR(bank->base)) 1484 return PTR_ERR(bank->base); 1485 1486 bank->gpio_chip = st_gpio_template; 1487 bank->gpio_chip.base = bank_num * ST_GPIO_PINS_PER_BANK; 1488 bank->gpio_chip.ngpio = ST_GPIO_PINS_PER_BANK; 1489 bank->gpio_chip.of_node = np; 1490 bank->gpio_chip.parent = dev; 1491 spin_lock_init(&bank->lock); 1492 1493 of_property_read_string(np, "st,bank-name", &range->name); 1494 bank->gpio_chip.label = range->name; 1495 1496 range->id = bank_num; 1497 range->pin_base = range->base = range->id * ST_GPIO_PINS_PER_BANK; 1498 range->npins = bank->gpio_chip.ngpio; 1499 range->gc = &bank->gpio_chip; 1500 err = gpiochip_add_data(&bank->gpio_chip, bank); 1501 if (err) { 1502 dev_err(dev, "Failed to add gpiochip(%d)!\n", bank_num); 1503 return err; 1504 } 1505 dev_info(dev, "%s bank added.\n", range->name); 1506 1507 /** 1508 * GPIO bank can have one of the two possible types of 1509 * interrupt-wirings. 1510 * 1511 * First type is via irqmux, single interrupt is used by multiple 1512 * gpio banks. This reduces number of overall interrupts numbers 1513 * required. All these banks belong to a single pincontroller. 1514 * _________ 1515 * | |----> [gpio-bank (n) ] 1516 * | |----> [gpio-bank (n + 1)] 1517 * [irqN]-- | irq-mux |----> [gpio-bank (n + 2)] 1518 * | |----> [gpio-bank (... )] 1519 * |_________|----> [gpio-bank (n + 7)] 1520 * 1521 * Second type has a dedicated interrupt per each gpio bank. 1522 * 1523 * [irqN]----> [gpio-bank (n)] 1524 */ 1525 1526 if (of_irq_to_resource(np, 0, &irq_res) > 0) { 1527 gpio_irq = irq_res.start; 1528 gpiochip_set_chained_irqchip(&bank->gpio_chip, &st_gpio_irqchip, 1529 gpio_irq, st_gpio_irq_handler); 1530 } 1531 1532 if (info->irqmux_base || gpio_irq > 0) { 1533 err = gpiochip_irqchip_add(&bank->gpio_chip, &st_gpio_irqchip, 1534 0, handle_simple_irq, 1535 IRQ_TYPE_NONE); 1536 if (err) { 1537 gpiochip_remove(&bank->gpio_chip); 1538 dev_info(dev, "could not add irqchip\n"); 1539 return err; 1540 } 1541 } else { 1542 dev_info(dev, "No IRQ support for %pOF bank\n", np); 1543 } 1544 1545 return 0; 1546 } 1547 1548 static const struct of_device_id st_pctl_of_match[] = { 1549 { .compatible = "st,stih407-sbc-pinctrl", .data = &stih407_data}, 1550 { .compatible = "st,stih407-front-pinctrl", .data = &stih407_data}, 1551 { .compatible = "st,stih407-rear-pinctrl", .data = &stih407_data}, 1552 { .compatible = "st,stih407-flash-pinctrl", .data = &stih407_flashdata}, 1553 { /* sentinel */ } 1554 }; 1555 1556 static int st_pctl_probe_dt(struct platform_device *pdev, 1557 struct pinctrl_desc *pctl_desc, struct st_pinctrl *info) 1558 { 1559 int ret = 0; 1560 int i = 0, j = 0, k = 0, bank; 1561 struct pinctrl_pin_desc *pdesc; 1562 struct device_node *np = pdev->dev.of_node; 1563 struct device_node *child; 1564 int grp_index = 0; 1565 int irq = 0; 1566 struct resource *res; 1567 1568 st_pctl_dt_child_count(info, np); 1569 if (!info->nbanks) { 1570 dev_err(&pdev->dev, "you need atleast one gpio bank\n"); 1571 return -EINVAL; 1572 } 1573 1574 dev_info(&pdev->dev, "nbanks = %d\n", info->nbanks); 1575 dev_info(&pdev->dev, "nfunctions = %d\n", info->nfunctions); 1576 dev_info(&pdev->dev, "ngroups = %d\n", info->ngroups); 1577 1578 info->functions = devm_kcalloc(&pdev->dev, 1579 info->nfunctions, sizeof(*info->functions), GFP_KERNEL); 1580 1581 info->groups = devm_kcalloc(&pdev->dev, 1582 info->ngroups, sizeof(*info->groups), 1583 GFP_KERNEL); 1584 1585 info->banks = devm_kcalloc(&pdev->dev, 1586 info->nbanks, sizeof(*info->banks), GFP_KERNEL); 1587 1588 if (!info->functions || !info->groups || !info->banks) 1589 return -ENOMEM; 1590 1591 info->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg"); 1592 if (IS_ERR(info->regmap)) { 1593 dev_err(info->dev, "No syscfg phandle specified\n"); 1594 return PTR_ERR(info->regmap); 1595 } 1596 info->data = of_match_node(st_pctl_of_match, np)->data; 1597 1598 irq = platform_get_irq(pdev, 0); 1599 1600 if (irq > 0) { 1601 res = platform_get_resource_byname(pdev, 1602 IORESOURCE_MEM, "irqmux"); 1603 info->irqmux_base = devm_ioremap_resource(&pdev->dev, res); 1604 1605 if (IS_ERR(info->irqmux_base)) 1606 return PTR_ERR(info->irqmux_base); 1607 1608 irq_set_chained_handler_and_data(irq, st_gpio_irqmux_handler, 1609 info); 1610 1611 } 1612 1613 pctl_desc->npins = info->nbanks * ST_GPIO_PINS_PER_BANK; 1614 pdesc = devm_kcalloc(&pdev->dev, 1615 pctl_desc->npins, sizeof(*pdesc), GFP_KERNEL); 1616 if (!pdesc) 1617 return -ENOMEM; 1618 1619 pctl_desc->pins = pdesc; 1620 1621 bank = 0; 1622 for_each_child_of_node(np, child) { 1623 if (of_property_read_bool(child, "gpio-controller")) { 1624 const char *bank_name = NULL; 1625 ret = st_gpiolib_register_bank(info, bank, child); 1626 if (ret) 1627 return ret; 1628 1629 k = info->banks[bank].range.pin_base; 1630 bank_name = info->banks[bank].range.name; 1631 for (j = 0; j < ST_GPIO_PINS_PER_BANK; j++, k++) { 1632 pdesc->number = k; 1633 pdesc->name = kasprintf(GFP_KERNEL, "%s[%d]", 1634 bank_name, j); 1635 pdesc++; 1636 } 1637 st_parse_syscfgs(info, bank, child); 1638 bank++; 1639 } else { 1640 ret = st_pctl_parse_functions(child, info, 1641 i++, &grp_index); 1642 if (ret) { 1643 dev_err(&pdev->dev, "No functions found.\n"); 1644 return ret; 1645 } 1646 } 1647 } 1648 1649 return 0; 1650 } 1651 1652 static int st_pctl_probe(struct platform_device *pdev) 1653 { 1654 struct st_pinctrl *info; 1655 struct pinctrl_desc *pctl_desc; 1656 int ret, i; 1657 1658 if (!pdev->dev.of_node) { 1659 dev_err(&pdev->dev, "device node not found.\n"); 1660 return -EINVAL; 1661 } 1662 1663 pctl_desc = devm_kzalloc(&pdev->dev, sizeof(*pctl_desc), GFP_KERNEL); 1664 if (!pctl_desc) 1665 return -ENOMEM; 1666 1667 info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL); 1668 if (!info) 1669 return -ENOMEM; 1670 1671 info->dev = &pdev->dev; 1672 platform_set_drvdata(pdev, info); 1673 ret = st_pctl_probe_dt(pdev, pctl_desc, info); 1674 if (ret) 1675 return ret; 1676 1677 pctl_desc->owner = THIS_MODULE; 1678 pctl_desc->pctlops = &st_pctlops; 1679 pctl_desc->pmxops = &st_pmxops; 1680 pctl_desc->confops = &st_confops; 1681 pctl_desc->name = dev_name(&pdev->dev); 1682 1683 info->pctl = devm_pinctrl_register(&pdev->dev, pctl_desc, info); 1684 if (IS_ERR(info->pctl)) { 1685 dev_err(&pdev->dev, "Failed pinctrl registration\n"); 1686 return PTR_ERR(info->pctl); 1687 } 1688 1689 for (i = 0; i < info->nbanks; i++) 1690 pinctrl_add_gpio_range(info->pctl, &info->banks[i].range); 1691 1692 return 0; 1693 } 1694 1695 static struct platform_driver st_pctl_driver = { 1696 .driver = { 1697 .name = "st-pinctrl", 1698 .of_match_table = st_pctl_of_match, 1699 }, 1700 .probe = st_pctl_probe, 1701 }; 1702 1703 static int __init st_pctl_init(void) 1704 { 1705 return platform_driver_register(&st_pctl_driver); 1706 } 1707 arch_initcall(st_pctl_init); 1708