1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2013 STMicroelectronics (R&D) Limited. 4 * Authors: 5 * Srinivas Kandagatla <srinivas.kandagatla@st.com> 6 */ 7 8 #include <linux/init.h> 9 #include <linux/module.h> 10 #include <linux/slab.h> 11 #include <linux/err.h> 12 #include <linux/io.h> 13 #include <linux/of.h> 14 #include <linux/of_irq.h> 15 #include <linux/of_address.h> 16 #include <linux/gpio/driver.h> 17 #include <linux/regmap.h> 18 #include <linux/mfd/syscon.h> 19 #include <linux/pinctrl/pinctrl.h> 20 #include <linux/pinctrl/pinmux.h> 21 #include <linux/pinctrl/pinconf.h> 22 #include <linux/platform_device.h> 23 #include "core.h" 24 25 /* PIO Block registers */ 26 /* PIO output */ 27 #define REG_PIO_POUT 0x00 28 /* Set bits of POUT */ 29 #define REG_PIO_SET_POUT 0x04 30 /* Clear bits of POUT */ 31 #define REG_PIO_CLR_POUT 0x08 32 /* PIO input */ 33 #define REG_PIO_PIN 0x10 34 /* PIO configuration */ 35 #define REG_PIO_PC(n) (0x20 + (n) * 0x10) 36 /* Set bits of PC[2:0] */ 37 #define REG_PIO_SET_PC(n) (0x24 + (n) * 0x10) 38 /* Clear bits of PC[2:0] */ 39 #define REG_PIO_CLR_PC(n) (0x28 + (n) * 0x10) 40 /* PIO input comparison */ 41 #define REG_PIO_PCOMP 0x50 42 /* Set bits of PCOMP */ 43 #define REG_PIO_SET_PCOMP 0x54 44 /* Clear bits of PCOMP */ 45 #define REG_PIO_CLR_PCOMP 0x58 46 /* PIO input comparison mask */ 47 #define REG_PIO_PMASK 0x60 48 /* Set bits of PMASK */ 49 #define REG_PIO_SET_PMASK 0x64 50 /* Clear bits of PMASK */ 51 #define REG_PIO_CLR_PMASK 0x68 52 53 #define ST_GPIO_DIRECTION_BIDIR 0x1 54 #define ST_GPIO_DIRECTION_OUT 0x2 55 #define ST_GPIO_DIRECTION_IN 0x4 56 57 /* 58 * Packed style retime configuration. 59 * There are two registers cfg0 and cfg1 in this style for each bank. 60 * Each field in this register is 8 bit corresponding to 8 pins in the bank. 61 */ 62 #define RT_P_CFGS_PER_BANK 2 63 #define RT_P_CFG0_CLK1NOTCLK0_FIELD(reg) REG_FIELD(reg, 0, 7) 64 #define RT_P_CFG0_DELAY_0_FIELD(reg) REG_FIELD(reg, 16, 23) 65 #define RT_P_CFG0_DELAY_1_FIELD(reg) REG_FIELD(reg, 24, 31) 66 #define RT_P_CFG1_INVERTCLK_FIELD(reg) REG_FIELD(reg, 0, 7) 67 #define RT_P_CFG1_RETIME_FIELD(reg) REG_FIELD(reg, 8, 15) 68 #define RT_P_CFG1_CLKNOTDATA_FIELD(reg) REG_FIELD(reg, 16, 23) 69 #define RT_P_CFG1_DOUBLE_EDGE_FIELD(reg) REG_FIELD(reg, 24, 31) 70 71 /* 72 * Dedicated style retime Configuration register 73 * each register is dedicated per pin. 74 */ 75 #define RT_D_CFGS_PER_BANK 8 76 #define RT_D_CFG_CLK_SHIFT 0 77 #define RT_D_CFG_CLK_MASK (0x3 << 0) 78 #define RT_D_CFG_CLKNOTDATA_SHIFT 2 79 #define RT_D_CFG_CLKNOTDATA_MASK BIT(2) 80 #define RT_D_CFG_DELAY_SHIFT 3 81 #define RT_D_CFG_DELAY_MASK (0xf << 3) 82 #define RT_D_CFG_DELAY_INNOTOUT_SHIFT 7 83 #define RT_D_CFG_DELAY_INNOTOUT_MASK BIT(7) 84 #define RT_D_CFG_DOUBLE_EDGE_SHIFT 8 85 #define RT_D_CFG_DOUBLE_EDGE_MASK BIT(8) 86 #define RT_D_CFG_INVERTCLK_SHIFT 9 87 #define RT_D_CFG_INVERTCLK_MASK BIT(9) 88 #define RT_D_CFG_RETIME_SHIFT 10 89 #define RT_D_CFG_RETIME_MASK BIT(10) 90 91 /* 92 * Pinconf is represented in an opaque unsigned long variable. 93 * Below is the bit allocation details for each possible configuration. 94 * All the bit fields can be encapsulated into four variables 95 * (direction, retime-type, retime-clk, retime-delay) 96 * 97 * +----------------+ 98 *[31:28]| reserved-3 | 99 * +----------------+------------- 100 *[27] | oe | | 101 * +----------------+ v 102 *[26] | pu | [Direction ] 103 * +----------------+ ^ 104 *[25] | od | | 105 * +----------------+------------- 106 *[24] | reserved-2 | 107 * +----------------+------------- 108 *[23] | retime | | 109 * +----------------+ | 110 *[22] | retime-invclk | | 111 * +----------------+ v 112 *[21] |retime-clknotdat| [Retime-type ] 113 * +----------------+ ^ 114 *[20] | retime-de | | 115 * +----------------+------------- 116 *[19:18]| retime-clk |------>[Retime-Clk ] 117 * +----------------+ 118 *[17:16]| reserved-1 | 119 * +----------------+ 120 *[15..0]| retime-delay |------>[Retime Delay] 121 * +----------------+ 122 */ 123 124 #define ST_PINCONF_UNPACK(conf, param)\ 125 ((conf >> ST_PINCONF_ ##param ##_SHIFT) \ 126 & ST_PINCONF_ ##param ##_MASK) 127 128 #define ST_PINCONF_PACK(conf, val, param) (conf |=\ 129 ((val & ST_PINCONF_ ##param ##_MASK) << \ 130 ST_PINCONF_ ##param ##_SHIFT)) 131 132 /* Output enable */ 133 #define ST_PINCONF_OE_MASK 0x1 134 #define ST_PINCONF_OE_SHIFT 27 135 #define ST_PINCONF_OE BIT(27) 136 #define ST_PINCONF_UNPACK_OE(conf) ST_PINCONF_UNPACK(conf, OE) 137 #define ST_PINCONF_PACK_OE(conf) ST_PINCONF_PACK(conf, 1, OE) 138 139 /* Pull Up */ 140 #define ST_PINCONF_PU_MASK 0x1 141 #define ST_PINCONF_PU_SHIFT 26 142 #define ST_PINCONF_PU BIT(26) 143 #define ST_PINCONF_UNPACK_PU(conf) ST_PINCONF_UNPACK(conf, PU) 144 #define ST_PINCONF_PACK_PU(conf) ST_PINCONF_PACK(conf, 1, PU) 145 146 /* Open Drain */ 147 #define ST_PINCONF_OD_MASK 0x1 148 #define ST_PINCONF_OD_SHIFT 25 149 #define ST_PINCONF_OD BIT(25) 150 #define ST_PINCONF_UNPACK_OD(conf) ST_PINCONF_UNPACK(conf, OD) 151 #define ST_PINCONF_PACK_OD(conf) ST_PINCONF_PACK(conf, 1, OD) 152 153 #define ST_PINCONF_RT_MASK 0x1 154 #define ST_PINCONF_RT_SHIFT 23 155 #define ST_PINCONF_RT BIT(23) 156 #define ST_PINCONF_UNPACK_RT(conf) ST_PINCONF_UNPACK(conf, RT) 157 #define ST_PINCONF_PACK_RT(conf) ST_PINCONF_PACK(conf, 1, RT) 158 159 #define ST_PINCONF_RT_INVERTCLK_MASK 0x1 160 #define ST_PINCONF_RT_INVERTCLK_SHIFT 22 161 #define ST_PINCONF_RT_INVERTCLK BIT(22) 162 #define ST_PINCONF_UNPACK_RT_INVERTCLK(conf) \ 163 ST_PINCONF_UNPACK(conf, RT_INVERTCLK) 164 #define ST_PINCONF_PACK_RT_INVERTCLK(conf) \ 165 ST_PINCONF_PACK(conf, 1, RT_INVERTCLK) 166 167 #define ST_PINCONF_RT_CLKNOTDATA_MASK 0x1 168 #define ST_PINCONF_RT_CLKNOTDATA_SHIFT 21 169 #define ST_PINCONF_RT_CLKNOTDATA BIT(21) 170 #define ST_PINCONF_UNPACK_RT_CLKNOTDATA(conf) \ 171 ST_PINCONF_UNPACK(conf, RT_CLKNOTDATA) 172 #define ST_PINCONF_PACK_RT_CLKNOTDATA(conf) \ 173 ST_PINCONF_PACK(conf, 1, RT_CLKNOTDATA) 174 175 #define ST_PINCONF_RT_DOUBLE_EDGE_MASK 0x1 176 #define ST_PINCONF_RT_DOUBLE_EDGE_SHIFT 20 177 #define ST_PINCONF_RT_DOUBLE_EDGE BIT(20) 178 #define ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(conf) \ 179 ST_PINCONF_UNPACK(conf, RT_DOUBLE_EDGE) 180 #define ST_PINCONF_PACK_RT_DOUBLE_EDGE(conf) \ 181 ST_PINCONF_PACK(conf, 1, RT_DOUBLE_EDGE) 182 183 #define ST_PINCONF_RT_CLK_MASK 0x3 184 #define ST_PINCONF_RT_CLK_SHIFT 18 185 #define ST_PINCONF_RT_CLK BIT(18) 186 #define ST_PINCONF_UNPACK_RT_CLK(conf) ST_PINCONF_UNPACK(conf, RT_CLK) 187 #define ST_PINCONF_PACK_RT_CLK(conf, val) ST_PINCONF_PACK(conf, val, RT_CLK) 188 189 /* RETIME_DELAY in Pico Secs */ 190 #define ST_PINCONF_RT_DELAY_MASK 0xffff 191 #define ST_PINCONF_RT_DELAY_SHIFT 0 192 #define ST_PINCONF_UNPACK_RT_DELAY(conf) ST_PINCONF_UNPACK(conf, RT_DELAY) 193 #define ST_PINCONF_PACK_RT_DELAY(conf, val) \ 194 ST_PINCONF_PACK(conf, val, RT_DELAY) 195 196 #define ST_GPIO_PINS_PER_BANK (8) 197 #define OF_GPIO_ARGS_MIN (4) 198 #define OF_RT_ARGS_MIN (2) 199 200 #define gpio_range_to_bank(chip) \ 201 container_of(chip, struct st_gpio_bank, range) 202 203 #define pc_to_bank(pc) \ 204 container_of(pc, struct st_gpio_bank, pc) 205 206 enum st_retime_style { 207 st_retime_style_none, 208 st_retime_style_packed, 209 st_retime_style_dedicated, 210 }; 211 212 struct st_retime_dedicated { 213 struct regmap_field *rt[ST_GPIO_PINS_PER_BANK]; 214 }; 215 216 struct st_retime_packed { 217 struct regmap_field *clk1notclk0; 218 struct regmap_field *delay_0; 219 struct regmap_field *delay_1; 220 struct regmap_field *invertclk; 221 struct regmap_field *retime; 222 struct regmap_field *clknotdata; 223 struct regmap_field *double_edge; 224 }; 225 226 struct st_pio_control { 227 u32 rt_pin_mask; 228 struct regmap_field *alt, *oe, *pu, *od; 229 /* retiming */ 230 union { 231 struct st_retime_packed rt_p; 232 struct st_retime_dedicated rt_d; 233 } rt; 234 }; 235 236 struct st_pctl_data { 237 const enum st_retime_style rt_style; 238 const unsigned int *input_delays; 239 const int ninput_delays; 240 const unsigned int *output_delays; 241 const int noutput_delays; 242 /* register offset information */ 243 const int alt, oe, pu, od, rt; 244 }; 245 246 struct st_pinconf { 247 int pin; 248 const char *name; 249 unsigned long config; 250 int altfunc; 251 }; 252 253 struct st_pmx_func { 254 const char *name; 255 const char **groups; 256 unsigned ngroups; 257 }; 258 259 struct st_pctl_group { 260 const char *name; 261 unsigned int *pins; 262 unsigned npins; 263 struct st_pinconf *pin_conf; 264 }; 265 266 /* 267 * Edge triggers are not supported at hardware level, it is supported by 268 * software by exploiting the level trigger support in hardware. 269 * Software uses a virtual register (EDGE_CONF) for edge trigger configuration 270 * of each gpio pin in a GPIO bank. 271 * 272 * Each bank has a 32 bit EDGE_CONF register which is divided in to 8 parts of 273 * 4-bits. Each 4-bit space is allocated for each pin in a gpio bank. 274 * 275 * bit allocation per pin is: 276 * Bits: [0 - 3] | [4 - 7] [8 - 11] ... ... ... ... [ 28 - 31] 277 * -------------------------------------------------------- 278 * | pin-0 | pin-2 | pin-3 | ... ... ... ... | pin -7 | 279 * -------------------------------------------------------- 280 * 281 * A pin can have one of following the values in its edge configuration field. 282 * 283 * ------- ---------------------------- 284 * [0-3] - Description 285 * ------- ---------------------------- 286 * 0000 - No edge IRQ. 287 * 0001 - Falling edge IRQ. 288 * 0010 - Rising edge IRQ. 289 * 0011 - Rising and Falling edge IRQ. 290 * ------- ---------------------------- 291 */ 292 293 #define ST_IRQ_EDGE_CONF_BITS_PER_PIN 4 294 #define ST_IRQ_EDGE_MASK 0xf 295 #define ST_IRQ_EDGE_FALLING BIT(0) 296 #define ST_IRQ_EDGE_RISING BIT(1) 297 #define ST_IRQ_EDGE_BOTH (BIT(0) | BIT(1)) 298 299 #define ST_IRQ_RISING_EDGE_CONF(pin) \ 300 (ST_IRQ_EDGE_RISING << (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN)) 301 302 #define ST_IRQ_FALLING_EDGE_CONF(pin) \ 303 (ST_IRQ_EDGE_FALLING << (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN)) 304 305 #define ST_IRQ_BOTH_EDGE_CONF(pin) \ 306 (ST_IRQ_EDGE_BOTH << (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN)) 307 308 #define ST_IRQ_EDGE_CONF(conf, pin) \ 309 (conf >> (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN) & ST_IRQ_EDGE_MASK) 310 311 struct st_gpio_bank { 312 struct gpio_chip gpio_chip; 313 struct pinctrl_gpio_range range; 314 void __iomem *base; 315 struct st_pio_control pc; 316 unsigned long irq_edge_conf; 317 spinlock_t lock; 318 }; 319 320 struct st_pinctrl { 321 struct device *dev; 322 struct pinctrl_dev *pctl; 323 struct st_gpio_bank *banks; 324 int nbanks; 325 struct st_pmx_func *functions; 326 int nfunctions; 327 struct st_pctl_group *groups; 328 int ngroups; 329 struct regmap *regmap; 330 const struct st_pctl_data *data; 331 void __iomem *irqmux_base; 332 }; 333 334 /* SOC specific data */ 335 336 static const unsigned int stih407_delays[] = {0, 300, 500, 750, 1000, 1250, 337 1500, 1750, 2000, 2250, 2500, 2750, 3000, 3250 }; 338 339 static const struct st_pctl_data stih407_data = { 340 .rt_style = st_retime_style_dedicated, 341 .input_delays = stih407_delays, 342 .ninput_delays = ARRAY_SIZE(stih407_delays), 343 .output_delays = stih407_delays, 344 .noutput_delays = ARRAY_SIZE(stih407_delays), 345 .alt = 0, .oe = 40, .pu = 50, .od = 60, .rt = 100, 346 }; 347 348 static const struct st_pctl_data stih407_flashdata = { 349 .rt_style = st_retime_style_none, 350 .input_delays = stih407_delays, 351 .ninput_delays = ARRAY_SIZE(stih407_delays), 352 .output_delays = stih407_delays, 353 .noutput_delays = ARRAY_SIZE(stih407_delays), 354 .alt = 0, 355 .oe = -1, /* Not Available */ 356 .pu = -1, /* Not Available */ 357 .od = 60, 358 .rt = 100, 359 }; 360 361 static struct st_pio_control *st_get_pio_control( 362 struct pinctrl_dev *pctldev, int pin) 363 { 364 struct pinctrl_gpio_range *range = 365 pinctrl_find_gpio_range_from_pin(pctldev, pin); 366 struct st_gpio_bank *bank = gpio_range_to_bank(range); 367 368 return &bank->pc; 369 } 370 371 /* Low level functions.. */ 372 static inline int st_gpio_bank(int gpio) 373 { 374 return gpio/ST_GPIO_PINS_PER_BANK; 375 } 376 377 static inline int st_gpio_pin(int gpio) 378 { 379 return gpio%ST_GPIO_PINS_PER_BANK; 380 } 381 382 static void st_pinconf_set_config(struct st_pio_control *pc, 383 int pin, unsigned long config) 384 { 385 struct regmap_field *output_enable = pc->oe; 386 struct regmap_field *pull_up = pc->pu; 387 struct regmap_field *open_drain = pc->od; 388 unsigned int oe_value, pu_value, od_value; 389 unsigned long mask = BIT(pin); 390 391 if (output_enable) { 392 regmap_field_read(output_enable, &oe_value); 393 oe_value &= ~mask; 394 if (config & ST_PINCONF_OE) 395 oe_value |= mask; 396 regmap_field_write(output_enable, oe_value); 397 } 398 399 if (pull_up) { 400 regmap_field_read(pull_up, &pu_value); 401 pu_value &= ~mask; 402 if (config & ST_PINCONF_PU) 403 pu_value |= mask; 404 regmap_field_write(pull_up, pu_value); 405 } 406 407 if (open_drain) { 408 regmap_field_read(open_drain, &od_value); 409 od_value &= ~mask; 410 if (config & ST_PINCONF_OD) 411 od_value |= mask; 412 regmap_field_write(open_drain, od_value); 413 } 414 } 415 416 static void st_pctl_set_function(struct st_pio_control *pc, 417 int pin_id, int function) 418 { 419 struct regmap_field *alt = pc->alt; 420 unsigned int val; 421 int pin = st_gpio_pin(pin_id); 422 int offset = pin * 4; 423 424 if (!alt) 425 return; 426 427 regmap_field_read(alt, &val); 428 val &= ~(0xf << offset); 429 val |= function << offset; 430 regmap_field_write(alt, val); 431 } 432 433 static unsigned int st_pctl_get_pin_function(struct st_pio_control *pc, int pin) 434 { 435 struct regmap_field *alt = pc->alt; 436 unsigned int val; 437 int offset = pin * 4; 438 439 if (!alt) 440 return 0; 441 442 regmap_field_read(alt, &val); 443 444 return (val >> offset) & 0xf; 445 } 446 447 static unsigned long st_pinconf_delay_to_bit(unsigned int delay, 448 const struct st_pctl_data *data, unsigned long config) 449 { 450 const unsigned int *delay_times; 451 int num_delay_times, i, closest_index = -1; 452 unsigned int closest_divergence = UINT_MAX; 453 454 if (ST_PINCONF_UNPACK_OE(config)) { 455 delay_times = data->output_delays; 456 num_delay_times = data->noutput_delays; 457 } else { 458 delay_times = data->input_delays; 459 num_delay_times = data->ninput_delays; 460 } 461 462 for (i = 0; i < num_delay_times; i++) { 463 unsigned int divergence = abs(delay - delay_times[i]); 464 465 if (divergence == 0) 466 return i; 467 468 if (divergence < closest_divergence) { 469 closest_divergence = divergence; 470 closest_index = i; 471 } 472 } 473 474 pr_warn("Attempt to set delay %d, closest available %d\n", 475 delay, delay_times[closest_index]); 476 477 return closest_index; 478 } 479 480 static unsigned long st_pinconf_bit_to_delay(unsigned int index, 481 const struct st_pctl_data *data, unsigned long output) 482 { 483 const unsigned int *delay_times; 484 int num_delay_times; 485 486 if (output) { 487 delay_times = data->output_delays; 488 num_delay_times = data->noutput_delays; 489 } else { 490 delay_times = data->input_delays; 491 num_delay_times = data->ninput_delays; 492 } 493 494 if (index < num_delay_times) { 495 return delay_times[index]; 496 } else { 497 pr_warn("Delay not found in/out delay list\n"); 498 return 0; 499 } 500 } 501 502 static void st_regmap_field_bit_set_clear_pin(struct regmap_field *field, 503 int enable, int pin) 504 { 505 unsigned int val = 0; 506 507 regmap_field_read(field, &val); 508 if (enable) 509 val |= BIT(pin); 510 else 511 val &= ~BIT(pin); 512 regmap_field_write(field, val); 513 } 514 515 static void st_pinconf_set_retime_packed(struct st_pinctrl *info, 516 struct st_pio_control *pc, unsigned long config, int pin) 517 { 518 const struct st_pctl_data *data = info->data; 519 struct st_retime_packed *rt_p = &pc->rt.rt_p; 520 unsigned int delay; 521 522 st_regmap_field_bit_set_clear_pin(rt_p->clk1notclk0, 523 ST_PINCONF_UNPACK_RT_CLK(config), pin); 524 525 st_regmap_field_bit_set_clear_pin(rt_p->clknotdata, 526 ST_PINCONF_UNPACK_RT_CLKNOTDATA(config), pin); 527 528 st_regmap_field_bit_set_clear_pin(rt_p->double_edge, 529 ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(config), pin); 530 531 st_regmap_field_bit_set_clear_pin(rt_p->invertclk, 532 ST_PINCONF_UNPACK_RT_INVERTCLK(config), pin); 533 534 st_regmap_field_bit_set_clear_pin(rt_p->retime, 535 ST_PINCONF_UNPACK_RT(config), pin); 536 537 delay = st_pinconf_delay_to_bit(ST_PINCONF_UNPACK_RT_DELAY(config), 538 data, config); 539 /* 2 bit delay, lsb */ 540 st_regmap_field_bit_set_clear_pin(rt_p->delay_0, delay & 0x1, pin); 541 /* 2 bit delay, msb */ 542 st_regmap_field_bit_set_clear_pin(rt_p->delay_1, delay & 0x2, pin); 543 } 544 545 static void st_pinconf_set_retime_dedicated(struct st_pinctrl *info, 546 struct st_pio_control *pc, unsigned long config, int pin) 547 { 548 int input = ST_PINCONF_UNPACK_OE(config) ? 0 : 1; 549 int clk = ST_PINCONF_UNPACK_RT_CLK(config); 550 int clknotdata = ST_PINCONF_UNPACK_RT_CLKNOTDATA(config); 551 int double_edge = ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(config); 552 int invertclk = ST_PINCONF_UNPACK_RT_INVERTCLK(config); 553 int retime = ST_PINCONF_UNPACK_RT(config); 554 555 unsigned long delay = st_pinconf_delay_to_bit( 556 ST_PINCONF_UNPACK_RT_DELAY(config), 557 info->data, config); 558 struct st_retime_dedicated *rt_d = &pc->rt.rt_d; 559 560 unsigned long retime_config = 561 ((clk) << RT_D_CFG_CLK_SHIFT) | 562 ((delay) << RT_D_CFG_DELAY_SHIFT) | 563 ((input) << RT_D_CFG_DELAY_INNOTOUT_SHIFT) | 564 ((retime) << RT_D_CFG_RETIME_SHIFT) | 565 ((clknotdata) << RT_D_CFG_CLKNOTDATA_SHIFT) | 566 ((invertclk) << RT_D_CFG_INVERTCLK_SHIFT) | 567 ((double_edge) << RT_D_CFG_DOUBLE_EDGE_SHIFT); 568 569 regmap_field_write(rt_d->rt[pin], retime_config); 570 } 571 572 static void st_pinconf_get_direction(struct st_pio_control *pc, 573 int pin, unsigned long *config) 574 { 575 unsigned int oe_value, pu_value, od_value; 576 577 if (pc->oe) { 578 regmap_field_read(pc->oe, &oe_value); 579 if (oe_value & BIT(pin)) 580 ST_PINCONF_PACK_OE(*config); 581 } 582 583 if (pc->pu) { 584 regmap_field_read(pc->pu, &pu_value); 585 if (pu_value & BIT(pin)) 586 ST_PINCONF_PACK_PU(*config); 587 } 588 589 if (pc->od) { 590 regmap_field_read(pc->od, &od_value); 591 if (od_value & BIT(pin)) 592 ST_PINCONF_PACK_OD(*config); 593 } 594 } 595 596 static int st_pinconf_get_retime_packed(struct st_pinctrl *info, 597 struct st_pio_control *pc, int pin, unsigned long *config) 598 { 599 const struct st_pctl_data *data = info->data; 600 struct st_retime_packed *rt_p = &pc->rt.rt_p; 601 unsigned int delay_bits, delay, delay0, delay1, val; 602 int output = ST_PINCONF_UNPACK_OE(*config); 603 604 if (!regmap_field_read(rt_p->retime, &val) && (val & BIT(pin))) 605 ST_PINCONF_PACK_RT(*config); 606 607 if (!regmap_field_read(rt_p->clk1notclk0, &val) && (val & BIT(pin))) 608 ST_PINCONF_PACK_RT_CLK(*config, 1); 609 610 if (!regmap_field_read(rt_p->clknotdata, &val) && (val & BIT(pin))) 611 ST_PINCONF_PACK_RT_CLKNOTDATA(*config); 612 613 if (!regmap_field_read(rt_p->double_edge, &val) && (val & BIT(pin))) 614 ST_PINCONF_PACK_RT_DOUBLE_EDGE(*config); 615 616 if (!regmap_field_read(rt_p->invertclk, &val) && (val & BIT(pin))) 617 ST_PINCONF_PACK_RT_INVERTCLK(*config); 618 619 regmap_field_read(rt_p->delay_0, &delay0); 620 regmap_field_read(rt_p->delay_1, &delay1); 621 delay_bits = (((delay1 & BIT(pin)) ? 1 : 0) << 1) | 622 (((delay0 & BIT(pin)) ? 1 : 0)); 623 delay = st_pinconf_bit_to_delay(delay_bits, data, output); 624 ST_PINCONF_PACK_RT_DELAY(*config, delay); 625 626 return 0; 627 } 628 629 static int st_pinconf_get_retime_dedicated(struct st_pinctrl *info, 630 struct st_pio_control *pc, int pin, unsigned long *config) 631 { 632 unsigned int value; 633 unsigned long delay_bits, delay, rt_clk; 634 int output = ST_PINCONF_UNPACK_OE(*config); 635 struct st_retime_dedicated *rt_d = &pc->rt.rt_d; 636 637 regmap_field_read(rt_d->rt[pin], &value); 638 639 rt_clk = (value & RT_D_CFG_CLK_MASK) >> RT_D_CFG_CLK_SHIFT; 640 ST_PINCONF_PACK_RT_CLK(*config, rt_clk); 641 642 delay_bits = (value & RT_D_CFG_DELAY_MASK) >> RT_D_CFG_DELAY_SHIFT; 643 delay = st_pinconf_bit_to_delay(delay_bits, info->data, output); 644 ST_PINCONF_PACK_RT_DELAY(*config, delay); 645 646 if (value & RT_D_CFG_CLKNOTDATA_MASK) 647 ST_PINCONF_PACK_RT_CLKNOTDATA(*config); 648 649 if (value & RT_D_CFG_DOUBLE_EDGE_MASK) 650 ST_PINCONF_PACK_RT_DOUBLE_EDGE(*config); 651 652 if (value & RT_D_CFG_INVERTCLK_MASK) 653 ST_PINCONF_PACK_RT_INVERTCLK(*config); 654 655 if (value & RT_D_CFG_RETIME_MASK) 656 ST_PINCONF_PACK_RT(*config); 657 658 return 0; 659 } 660 661 /* GPIO related functions */ 662 663 static inline void __st_gpio_set(struct st_gpio_bank *bank, 664 unsigned offset, int value) 665 { 666 if (value) 667 writel(BIT(offset), bank->base + REG_PIO_SET_POUT); 668 else 669 writel(BIT(offset), bank->base + REG_PIO_CLR_POUT); 670 } 671 672 static void st_gpio_direction(struct st_gpio_bank *bank, 673 unsigned int gpio, unsigned int direction) 674 { 675 int offset = st_gpio_pin(gpio); 676 int i = 0; 677 /** 678 * There are three configuration registers (PIOn_PC0, PIOn_PC1 679 * and PIOn_PC2) for each port. These are used to configure the 680 * PIO port pins. Each pin can be configured as an input, output, 681 * bidirectional, or alternative function pin. Three bits, one bit 682 * from each of the three registers, configure the corresponding bit of 683 * the port. Valid bit settings is: 684 * 685 * PC2 PC1 PC0 Direction. 686 * 0 0 0 [Input Weak pull-up] 687 * 0 0 or 1 1 [Bidirection] 688 * 0 1 0 [Output] 689 * 1 0 0 [Input] 690 * 691 * PIOn_SET_PC and PIOn_CLR_PC registers are used to set and clear bits 692 * individually. 693 */ 694 for (i = 0; i <= 2; i++) { 695 if (direction & BIT(i)) 696 writel(BIT(offset), bank->base + REG_PIO_SET_PC(i)); 697 else 698 writel(BIT(offset), bank->base + REG_PIO_CLR_PC(i)); 699 } 700 } 701 702 static int st_gpio_get(struct gpio_chip *chip, unsigned offset) 703 { 704 struct st_gpio_bank *bank = gpiochip_get_data(chip); 705 706 return !!(readl(bank->base + REG_PIO_PIN) & BIT(offset)); 707 } 708 709 static void st_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 710 { 711 struct st_gpio_bank *bank = gpiochip_get_data(chip); 712 __st_gpio_set(bank, offset, value); 713 } 714 715 static int st_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 716 { 717 pinctrl_gpio_direction_input(chip->base + offset); 718 719 return 0; 720 } 721 722 static int st_gpio_direction_output(struct gpio_chip *chip, 723 unsigned offset, int value) 724 { 725 struct st_gpio_bank *bank = gpiochip_get_data(chip); 726 727 __st_gpio_set(bank, offset, value); 728 pinctrl_gpio_direction_output(chip->base + offset); 729 730 return 0; 731 } 732 733 static int st_gpio_get_direction(struct gpio_chip *chip, unsigned offset) 734 { 735 struct st_gpio_bank *bank = gpiochip_get_data(chip); 736 struct st_pio_control pc = bank->pc; 737 unsigned long config; 738 unsigned int direction = 0; 739 unsigned int function; 740 unsigned int value; 741 int i = 0; 742 743 /* Alternate function direction is handled by Pinctrl */ 744 function = st_pctl_get_pin_function(&pc, offset); 745 if (function) { 746 st_pinconf_get_direction(&pc, offset, &config); 747 if (ST_PINCONF_UNPACK_OE(config)) 748 return GPIO_LINE_DIRECTION_OUT; 749 750 return GPIO_LINE_DIRECTION_IN; 751 } 752 753 /* 754 * GPIO direction is handled differently 755 * - See st_gpio_direction() above for an explanation 756 */ 757 for (i = 0; i <= 2; i++) { 758 value = readl(bank->base + REG_PIO_PC(i)); 759 direction |= ((value >> offset) & 0x1) << i; 760 } 761 762 if (direction == ST_GPIO_DIRECTION_IN) 763 return GPIO_LINE_DIRECTION_IN; 764 765 return GPIO_LINE_DIRECTION_OUT; 766 } 767 768 /* Pinctrl Groups */ 769 static int st_pctl_get_groups_count(struct pinctrl_dev *pctldev) 770 { 771 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 772 773 return info->ngroups; 774 } 775 776 static const char *st_pctl_get_group_name(struct pinctrl_dev *pctldev, 777 unsigned selector) 778 { 779 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 780 781 return info->groups[selector].name; 782 } 783 784 static int st_pctl_get_group_pins(struct pinctrl_dev *pctldev, 785 unsigned selector, const unsigned **pins, unsigned *npins) 786 { 787 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 788 789 if (selector >= info->ngroups) 790 return -EINVAL; 791 792 *pins = info->groups[selector].pins; 793 *npins = info->groups[selector].npins; 794 795 return 0; 796 } 797 798 static inline const struct st_pctl_group *st_pctl_find_group_by_name( 799 const struct st_pinctrl *info, const char *name) 800 { 801 int i; 802 803 for (i = 0; i < info->ngroups; i++) { 804 if (!strcmp(info->groups[i].name, name)) 805 return &info->groups[i]; 806 } 807 808 return NULL; 809 } 810 811 static int st_pctl_dt_node_to_map(struct pinctrl_dev *pctldev, 812 struct device_node *np, struct pinctrl_map **map, unsigned *num_maps) 813 { 814 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 815 const struct st_pctl_group *grp; 816 struct device *dev = info->dev; 817 struct pinctrl_map *new_map; 818 struct device_node *parent; 819 int map_num, i; 820 821 grp = st_pctl_find_group_by_name(info, np->name); 822 if (!grp) { 823 dev_err(dev, "unable to find group for node %pOFn\n", np); 824 return -EINVAL; 825 } 826 827 map_num = grp->npins + 1; 828 new_map = devm_kcalloc(dev, map_num, sizeof(*new_map), GFP_KERNEL); 829 if (!new_map) 830 return -ENOMEM; 831 832 parent = of_get_parent(np); 833 if (!parent) { 834 devm_kfree(dev, new_map); 835 return -EINVAL; 836 } 837 838 *map = new_map; 839 *num_maps = map_num; 840 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP; 841 new_map[0].data.mux.function = parent->name; 842 new_map[0].data.mux.group = np->name; 843 of_node_put(parent); 844 845 /* create config map per pin */ 846 new_map++; 847 for (i = 0; i < grp->npins; i++) { 848 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN; 849 new_map[i].data.configs.group_or_pin = 850 pin_get_name(pctldev, grp->pins[i]); 851 new_map[i].data.configs.configs = &grp->pin_conf[i].config; 852 new_map[i].data.configs.num_configs = 1; 853 } 854 dev_info(dev, "maps: function %s group %s num %d\n", 855 (*map)->data.mux.function, grp->name, map_num); 856 857 return 0; 858 } 859 860 static void st_pctl_dt_free_map(struct pinctrl_dev *pctldev, 861 struct pinctrl_map *map, unsigned num_maps) 862 { 863 } 864 865 static const struct pinctrl_ops st_pctlops = { 866 .get_groups_count = st_pctl_get_groups_count, 867 .get_group_pins = st_pctl_get_group_pins, 868 .get_group_name = st_pctl_get_group_name, 869 .dt_node_to_map = st_pctl_dt_node_to_map, 870 .dt_free_map = st_pctl_dt_free_map, 871 }; 872 873 /* Pinmux */ 874 static int st_pmx_get_funcs_count(struct pinctrl_dev *pctldev) 875 { 876 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 877 878 return info->nfunctions; 879 } 880 881 static const char *st_pmx_get_fname(struct pinctrl_dev *pctldev, 882 unsigned selector) 883 { 884 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 885 886 return info->functions[selector].name; 887 } 888 889 static int st_pmx_get_groups(struct pinctrl_dev *pctldev, 890 unsigned selector, const char * const **grps, unsigned * const ngrps) 891 { 892 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 893 *grps = info->functions[selector].groups; 894 *ngrps = info->functions[selector].ngroups; 895 896 return 0; 897 } 898 899 static int st_pmx_set_mux(struct pinctrl_dev *pctldev, unsigned fselector, 900 unsigned group) 901 { 902 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 903 struct st_pinconf *conf = info->groups[group].pin_conf; 904 struct st_pio_control *pc; 905 int i; 906 907 for (i = 0; i < info->groups[group].npins; i++) { 908 pc = st_get_pio_control(pctldev, conf[i].pin); 909 st_pctl_set_function(pc, conf[i].pin, conf[i].altfunc); 910 } 911 912 return 0; 913 } 914 915 static int st_pmx_set_gpio_direction(struct pinctrl_dev *pctldev, 916 struct pinctrl_gpio_range *range, unsigned gpio, 917 bool input) 918 { 919 struct st_gpio_bank *bank = gpio_range_to_bank(range); 920 /* 921 * When a PIO bank is used in its primary function mode (altfunc = 0) 922 * Output Enable (OE), Open Drain(OD), and Pull Up (PU) 923 * for the primary PIO functions are driven by the related PIO block 924 */ 925 st_pctl_set_function(&bank->pc, gpio, 0); 926 st_gpio_direction(bank, gpio, input ? 927 ST_GPIO_DIRECTION_IN : ST_GPIO_DIRECTION_OUT); 928 929 return 0; 930 } 931 932 static const struct pinmux_ops st_pmxops = { 933 .get_functions_count = st_pmx_get_funcs_count, 934 .get_function_name = st_pmx_get_fname, 935 .get_function_groups = st_pmx_get_groups, 936 .set_mux = st_pmx_set_mux, 937 .gpio_set_direction = st_pmx_set_gpio_direction, 938 .strict = true, 939 }; 940 941 /* Pinconf */ 942 static void st_pinconf_get_retime(struct st_pinctrl *info, 943 struct st_pio_control *pc, int pin, unsigned long *config) 944 { 945 if (info->data->rt_style == st_retime_style_packed) 946 st_pinconf_get_retime_packed(info, pc, pin, config); 947 else if (info->data->rt_style == st_retime_style_dedicated) 948 if ((BIT(pin) & pc->rt_pin_mask)) 949 st_pinconf_get_retime_dedicated(info, pc, 950 pin, config); 951 } 952 953 static void st_pinconf_set_retime(struct st_pinctrl *info, 954 struct st_pio_control *pc, int pin, unsigned long config) 955 { 956 if (info->data->rt_style == st_retime_style_packed) 957 st_pinconf_set_retime_packed(info, pc, config, pin); 958 else if (info->data->rt_style == st_retime_style_dedicated) 959 if ((BIT(pin) & pc->rt_pin_mask)) 960 st_pinconf_set_retime_dedicated(info, pc, 961 config, pin); 962 } 963 964 static int st_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin_id, 965 unsigned long *configs, unsigned num_configs) 966 { 967 int pin = st_gpio_pin(pin_id); 968 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 969 struct st_pio_control *pc = st_get_pio_control(pctldev, pin_id); 970 int i; 971 972 for (i = 0; i < num_configs; i++) { 973 st_pinconf_set_config(pc, pin, configs[i]); 974 st_pinconf_set_retime(info, pc, pin, configs[i]); 975 } /* for each config */ 976 977 return 0; 978 } 979 980 static int st_pinconf_get(struct pinctrl_dev *pctldev, 981 unsigned pin_id, unsigned long *config) 982 { 983 int pin = st_gpio_pin(pin_id); 984 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 985 struct st_pio_control *pc = st_get_pio_control(pctldev, pin_id); 986 987 *config = 0; 988 st_pinconf_get_direction(pc, pin, config); 989 st_pinconf_get_retime(info, pc, pin, config); 990 991 return 0; 992 } 993 994 static void st_pinconf_dbg_show(struct pinctrl_dev *pctldev, 995 struct seq_file *s, unsigned pin_id) 996 { 997 struct st_pio_control *pc; 998 unsigned long config; 999 unsigned int function; 1000 int offset = st_gpio_pin(pin_id); 1001 char f[16]; 1002 int oe; 1003 1004 mutex_unlock(&pctldev->mutex); 1005 pc = st_get_pio_control(pctldev, pin_id); 1006 st_pinconf_get(pctldev, pin_id, &config); 1007 mutex_lock(&pctldev->mutex); 1008 1009 function = st_pctl_get_pin_function(pc, offset); 1010 if (function) 1011 snprintf(f, 10, "Alt Fn %u", function); 1012 else 1013 snprintf(f, 5, "GPIO"); 1014 1015 oe = st_gpio_get_direction(&pc_to_bank(pc)->gpio_chip, offset); 1016 seq_printf(s, "[OE:%d,PU:%ld,OD:%ld]\t%s\n" 1017 "\t\t[retime:%ld,invclk:%ld,clknotdat:%ld," 1018 "de:%ld,rt-clk:%ld,rt-delay:%ld]", 1019 (oe == GPIO_LINE_DIRECTION_OUT), 1020 ST_PINCONF_UNPACK_PU(config), 1021 ST_PINCONF_UNPACK_OD(config), 1022 f, 1023 ST_PINCONF_UNPACK_RT(config), 1024 ST_PINCONF_UNPACK_RT_INVERTCLK(config), 1025 ST_PINCONF_UNPACK_RT_CLKNOTDATA(config), 1026 ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(config), 1027 ST_PINCONF_UNPACK_RT_CLK(config), 1028 ST_PINCONF_UNPACK_RT_DELAY(config)); 1029 } 1030 1031 static const struct pinconf_ops st_confops = { 1032 .pin_config_get = st_pinconf_get, 1033 .pin_config_set = st_pinconf_set, 1034 .pin_config_dbg_show = st_pinconf_dbg_show, 1035 }; 1036 1037 static void st_pctl_dt_child_count(struct st_pinctrl *info, 1038 struct device_node *np) 1039 { 1040 struct device_node *child; 1041 for_each_child_of_node(np, child) { 1042 if (of_property_read_bool(child, "gpio-controller")) { 1043 info->nbanks++; 1044 } else { 1045 info->nfunctions++; 1046 info->ngroups += of_get_child_count(child); 1047 } 1048 } 1049 } 1050 1051 static int st_pctl_dt_setup_retime_packed(struct st_pinctrl *info, 1052 int bank, struct st_pio_control *pc) 1053 { 1054 struct device *dev = info->dev; 1055 struct regmap *rm = info->regmap; 1056 const struct st_pctl_data *data = info->data; 1057 /* 2 registers per bank */ 1058 int reg = (data->rt + bank * RT_P_CFGS_PER_BANK) * 4; 1059 struct st_retime_packed *rt_p = &pc->rt.rt_p; 1060 /* cfg0 */ 1061 struct reg_field clk1notclk0 = RT_P_CFG0_CLK1NOTCLK0_FIELD(reg); 1062 struct reg_field delay_0 = RT_P_CFG0_DELAY_0_FIELD(reg); 1063 struct reg_field delay_1 = RT_P_CFG0_DELAY_1_FIELD(reg); 1064 /* cfg1 */ 1065 struct reg_field invertclk = RT_P_CFG1_INVERTCLK_FIELD(reg + 4); 1066 struct reg_field retime = RT_P_CFG1_RETIME_FIELD(reg + 4); 1067 struct reg_field clknotdata = RT_P_CFG1_CLKNOTDATA_FIELD(reg + 4); 1068 struct reg_field double_edge = RT_P_CFG1_DOUBLE_EDGE_FIELD(reg + 4); 1069 1070 rt_p->clk1notclk0 = devm_regmap_field_alloc(dev, rm, clk1notclk0); 1071 rt_p->delay_0 = devm_regmap_field_alloc(dev, rm, delay_0); 1072 rt_p->delay_1 = devm_regmap_field_alloc(dev, rm, delay_1); 1073 rt_p->invertclk = devm_regmap_field_alloc(dev, rm, invertclk); 1074 rt_p->retime = devm_regmap_field_alloc(dev, rm, retime); 1075 rt_p->clknotdata = devm_regmap_field_alloc(dev, rm, clknotdata); 1076 rt_p->double_edge = devm_regmap_field_alloc(dev, rm, double_edge); 1077 1078 if (IS_ERR(rt_p->clk1notclk0) || IS_ERR(rt_p->delay_0) || 1079 IS_ERR(rt_p->delay_1) || IS_ERR(rt_p->invertclk) || 1080 IS_ERR(rt_p->retime) || IS_ERR(rt_p->clknotdata) || 1081 IS_ERR(rt_p->double_edge)) 1082 return -EINVAL; 1083 1084 return 0; 1085 } 1086 1087 static int st_pctl_dt_setup_retime_dedicated(struct st_pinctrl *info, 1088 int bank, struct st_pio_control *pc) 1089 { 1090 struct device *dev = info->dev; 1091 struct regmap *rm = info->regmap; 1092 const struct st_pctl_data *data = info->data; 1093 /* 8 registers per bank */ 1094 int reg_offset = (data->rt + bank * RT_D_CFGS_PER_BANK) * 4; 1095 struct st_retime_dedicated *rt_d = &pc->rt.rt_d; 1096 unsigned int j; 1097 u32 pin_mask = pc->rt_pin_mask; 1098 1099 for (j = 0; j < RT_D_CFGS_PER_BANK; j++) { 1100 if (BIT(j) & pin_mask) { 1101 struct reg_field reg = REG_FIELD(reg_offset, 0, 31); 1102 rt_d->rt[j] = devm_regmap_field_alloc(dev, rm, reg); 1103 if (IS_ERR(rt_d->rt[j])) 1104 return -EINVAL; 1105 reg_offset += 4; 1106 } 1107 } 1108 return 0; 1109 } 1110 1111 static int st_pctl_dt_setup_retime(struct st_pinctrl *info, 1112 int bank, struct st_pio_control *pc) 1113 { 1114 const struct st_pctl_data *data = info->data; 1115 if (data->rt_style == st_retime_style_packed) 1116 return st_pctl_dt_setup_retime_packed(info, bank, pc); 1117 else if (data->rt_style == st_retime_style_dedicated) 1118 return st_pctl_dt_setup_retime_dedicated(info, bank, pc); 1119 1120 return -EINVAL; 1121 } 1122 1123 1124 static struct regmap_field *st_pc_get_value(struct device *dev, 1125 struct regmap *regmap, int bank, 1126 int data, int lsb, int msb) 1127 { 1128 struct reg_field reg = REG_FIELD((data + bank) * 4, lsb, msb); 1129 1130 if (data < 0) 1131 return NULL; 1132 1133 return devm_regmap_field_alloc(dev, regmap, reg); 1134 } 1135 1136 static void st_parse_syscfgs(struct st_pinctrl *info, int bank, 1137 struct device_node *np) 1138 { 1139 const struct st_pctl_data *data = info->data; 1140 /** 1141 * For a given shared register like OE/PU/OD, there are 8 bits per bank 1142 * 0:7 belongs to bank0, 8:15 belongs to bank1 ... 1143 * So each register is shared across 4 banks. 1144 */ 1145 int lsb = (bank%4) * ST_GPIO_PINS_PER_BANK; 1146 int msb = lsb + ST_GPIO_PINS_PER_BANK - 1; 1147 struct st_pio_control *pc = &info->banks[bank].pc; 1148 struct device *dev = info->dev; 1149 struct regmap *regmap = info->regmap; 1150 1151 pc->alt = st_pc_get_value(dev, regmap, bank, data->alt, 0, 31); 1152 pc->oe = st_pc_get_value(dev, regmap, bank/4, data->oe, lsb, msb); 1153 pc->pu = st_pc_get_value(dev, regmap, bank/4, data->pu, lsb, msb); 1154 pc->od = st_pc_get_value(dev, regmap, bank/4, data->od, lsb, msb); 1155 1156 /* retime avaiable for all pins by default */ 1157 pc->rt_pin_mask = 0xff; 1158 of_property_read_u32(np, "st,retime-pin-mask", &pc->rt_pin_mask); 1159 st_pctl_dt_setup_retime(info, bank, pc); 1160 1161 return; 1162 } 1163 1164 static int st_pctl_dt_calculate_pin(struct st_pinctrl *info, 1165 phandle bank, unsigned int offset) 1166 { 1167 struct device_node *np; 1168 struct gpio_chip *chip; 1169 int retval = -EINVAL; 1170 int i; 1171 1172 np = of_find_node_by_phandle(bank); 1173 if (!np) 1174 return -EINVAL; 1175 1176 for (i = 0; i < info->nbanks; i++) { 1177 chip = &info->banks[i].gpio_chip; 1178 if (chip->of_node == np) { 1179 if (offset < chip->ngpio) 1180 retval = chip->base + offset; 1181 break; 1182 } 1183 } 1184 1185 of_node_put(np); 1186 return retval; 1187 } 1188 1189 /* 1190 * Each pin is represented in of the below forms. 1191 * <bank offset mux direction rt_type rt_delay rt_clk> 1192 */ 1193 static int st_pctl_dt_parse_groups(struct device_node *np, 1194 struct st_pctl_group *grp, struct st_pinctrl *info, int idx) 1195 { 1196 /* bank pad direction val altfunction */ 1197 const __be32 *list; 1198 struct property *pp; 1199 struct device *dev = info->dev; 1200 struct st_pinconf *conf; 1201 struct device_node *pins; 1202 phandle bank; 1203 unsigned int offset; 1204 int i = 0, npins = 0, nr_props, ret = 0; 1205 1206 pins = of_get_child_by_name(np, "st,pins"); 1207 if (!pins) 1208 return -ENODATA; 1209 1210 for_each_property_of_node(pins, pp) { 1211 /* Skip those we do not want to proceed */ 1212 if (!strcmp(pp->name, "name")) 1213 continue; 1214 1215 if (pp->length / sizeof(__be32) >= OF_GPIO_ARGS_MIN) { 1216 npins++; 1217 } else { 1218 pr_warn("Invalid st,pins in %pOFn node\n", np); 1219 ret = -EINVAL; 1220 goto out_put_node; 1221 } 1222 } 1223 1224 grp->npins = npins; 1225 grp->name = np->name; 1226 grp->pins = devm_kcalloc(dev, npins, sizeof(*grp->pins), GFP_KERNEL); 1227 grp->pin_conf = devm_kcalloc(dev, npins, sizeof(*grp->pin_conf), GFP_KERNEL); 1228 1229 if (!grp->pins || !grp->pin_conf) { 1230 ret = -ENOMEM; 1231 goto out_put_node; 1232 } 1233 1234 /* <bank offset mux direction rt_type rt_delay rt_clk> */ 1235 for_each_property_of_node(pins, pp) { 1236 if (!strcmp(pp->name, "name")) 1237 continue; 1238 nr_props = pp->length/sizeof(u32); 1239 list = pp->value; 1240 conf = &grp->pin_conf[i]; 1241 1242 /* bank & offset */ 1243 bank = be32_to_cpup(list++); 1244 offset = be32_to_cpup(list++); 1245 conf->pin = st_pctl_dt_calculate_pin(info, bank, offset); 1246 conf->name = pp->name; 1247 grp->pins[i] = conf->pin; 1248 /* mux */ 1249 conf->altfunc = be32_to_cpup(list++); 1250 conf->config = 0; 1251 /* direction */ 1252 conf->config |= be32_to_cpup(list++); 1253 /* rt_type rt_delay rt_clk */ 1254 if (nr_props >= OF_GPIO_ARGS_MIN + OF_RT_ARGS_MIN) { 1255 /* rt_type */ 1256 conf->config |= be32_to_cpup(list++); 1257 /* rt_delay */ 1258 conf->config |= be32_to_cpup(list++); 1259 /* rt_clk */ 1260 if (nr_props > OF_GPIO_ARGS_MIN + OF_RT_ARGS_MIN) 1261 conf->config |= be32_to_cpup(list++); 1262 } 1263 i++; 1264 } 1265 1266 out_put_node: 1267 of_node_put(pins); 1268 1269 return ret; 1270 } 1271 1272 static int st_pctl_parse_functions(struct device_node *np, 1273 struct st_pinctrl *info, u32 index, int *grp_index) 1274 { 1275 struct device *dev = info->dev; 1276 struct device_node *child; 1277 struct st_pmx_func *func; 1278 struct st_pctl_group *grp; 1279 int ret, i; 1280 1281 func = &info->functions[index]; 1282 func->name = np->name; 1283 func->ngroups = of_get_child_count(np); 1284 if (func->ngroups == 0) 1285 return dev_err_probe(dev, -EINVAL, "No groups defined\n"); 1286 func->groups = devm_kcalloc(dev, func->ngroups, sizeof(*func->groups), GFP_KERNEL); 1287 if (!func->groups) 1288 return -ENOMEM; 1289 1290 i = 0; 1291 for_each_child_of_node(np, child) { 1292 func->groups[i] = child->name; 1293 grp = &info->groups[*grp_index]; 1294 *grp_index += 1; 1295 ret = st_pctl_dt_parse_groups(child, grp, info, i++); 1296 if (ret) { 1297 of_node_put(child); 1298 return ret; 1299 } 1300 } 1301 dev_info(dev, "Function[%d\t name:%s,\tgroups:%d]\n", index, func->name, func->ngroups); 1302 1303 return 0; 1304 } 1305 1306 static void st_gpio_irq_mask(struct irq_data *d) 1307 { 1308 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1309 struct st_gpio_bank *bank = gpiochip_get_data(gc); 1310 1311 writel(BIT(d->hwirq), bank->base + REG_PIO_CLR_PMASK); 1312 } 1313 1314 static void st_gpio_irq_unmask(struct irq_data *d) 1315 { 1316 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1317 struct st_gpio_bank *bank = gpiochip_get_data(gc); 1318 1319 writel(BIT(d->hwirq), bank->base + REG_PIO_SET_PMASK); 1320 } 1321 1322 static int st_gpio_irq_request_resources(struct irq_data *d) 1323 { 1324 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1325 1326 st_gpio_direction_input(gc, d->hwirq); 1327 1328 return gpiochip_lock_as_irq(gc, d->hwirq); 1329 } 1330 1331 static void st_gpio_irq_release_resources(struct irq_data *d) 1332 { 1333 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1334 1335 gpiochip_unlock_as_irq(gc, d->hwirq); 1336 } 1337 1338 static int st_gpio_irq_set_type(struct irq_data *d, unsigned type) 1339 { 1340 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1341 struct st_gpio_bank *bank = gpiochip_get_data(gc); 1342 unsigned long flags; 1343 int comp, pin = d->hwirq; 1344 u32 val; 1345 u32 pin_edge_conf = 0; 1346 1347 switch (type) { 1348 case IRQ_TYPE_LEVEL_HIGH: 1349 comp = 0; 1350 break; 1351 case IRQ_TYPE_EDGE_FALLING: 1352 comp = 0; 1353 pin_edge_conf = ST_IRQ_FALLING_EDGE_CONF(pin); 1354 break; 1355 case IRQ_TYPE_LEVEL_LOW: 1356 comp = 1; 1357 break; 1358 case IRQ_TYPE_EDGE_RISING: 1359 comp = 1; 1360 pin_edge_conf = ST_IRQ_RISING_EDGE_CONF(pin); 1361 break; 1362 case IRQ_TYPE_EDGE_BOTH: 1363 comp = st_gpio_get(&bank->gpio_chip, pin); 1364 pin_edge_conf = ST_IRQ_BOTH_EDGE_CONF(pin); 1365 break; 1366 default: 1367 return -EINVAL; 1368 } 1369 1370 spin_lock_irqsave(&bank->lock, flags); 1371 bank->irq_edge_conf &= ~(ST_IRQ_EDGE_MASK << ( 1372 pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN)); 1373 bank->irq_edge_conf |= pin_edge_conf; 1374 spin_unlock_irqrestore(&bank->lock, flags); 1375 1376 val = readl(bank->base + REG_PIO_PCOMP); 1377 val &= ~BIT(pin); 1378 val |= (comp << pin); 1379 writel(val, bank->base + REG_PIO_PCOMP); 1380 1381 return 0; 1382 } 1383 1384 /* 1385 * As edge triggers are not supported at hardware level, it is supported by 1386 * software by exploiting the level trigger support in hardware. 1387 * 1388 * Steps for detection raising edge interrupt in software. 1389 * 1390 * Step 1: CONFIGURE pin to detect level LOW interrupts. 1391 * 1392 * Step 2: DETECT level LOW interrupt and in irqmux/gpio bank interrupt handler, 1393 * if the value of pin is low, then CONFIGURE pin for level HIGH interrupt. 1394 * IGNORE calling the actual interrupt handler for the pin at this stage. 1395 * 1396 * Step 3: DETECT level HIGH interrupt and in irqmux/gpio-bank interrupt handler 1397 * if the value of pin is HIGH, CONFIGURE pin for level LOW interrupt and then 1398 * DISPATCH the interrupt to the interrupt handler of the pin. 1399 * 1400 * step-1 ________ __________ 1401 * | | step - 3 1402 * | | 1403 * step -2 |_____| 1404 * 1405 * falling edge is also detected int the same way. 1406 * 1407 */ 1408 static void __gpio_irq_handler(struct st_gpio_bank *bank) 1409 { 1410 unsigned long port_in, port_mask, port_comp, active_irqs; 1411 unsigned long bank_edge_mask, flags; 1412 int n, val, ecfg; 1413 1414 spin_lock_irqsave(&bank->lock, flags); 1415 bank_edge_mask = bank->irq_edge_conf; 1416 spin_unlock_irqrestore(&bank->lock, flags); 1417 1418 for (;;) { 1419 port_in = readl(bank->base + REG_PIO_PIN); 1420 port_comp = readl(bank->base + REG_PIO_PCOMP); 1421 port_mask = readl(bank->base + REG_PIO_PMASK); 1422 1423 active_irqs = (port_in ^ port_comp) & port_mask; 1424 1425 if (active_irqs == 0) 1426 break; 1427 1428 for_each_set_bit(n, &active_irqs, BITS_PER_LONG) { 1429 /* check if we are detecting fake edges ... */ 1430 ecfg = ST_IRQ_EDGE_CONF(bank_edge_mask, n); 1431 1432 if (ecfg) { 1433 /* edge detection. */ 1434 val = st_gpio_get(&bank->gpio_chip, n); 1435 1436 writel(BIT(n), 1437 val ? bank->base + REG_PIO_SET_PCOMP : 1438 bank->base + REG_PIO_CLR_PCOMP); 1439 1440 if (ecfg != ST_IRQ_EDGE_BOTH && 1441 !((ecfg & ST_IRQ_EDGE_FALLING) ^ val)) 1442 continue; 1443 } 1444 1445 generic_handle_domain_irq(bank->gpio_chip.irq.domain, n); 1446 } 1447 } 1448 } 1449 1450 static void st_gpio_irq_handler(struct irq_desc *desc) 1451 { 1452 /* interrupt dedicated per bank */ 1453 struct irq_chip *chip = irq_desc_get_chip(desc); 1454 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 1455 struct st_gpio_bank *bank = gpiochip_get_data(gc); 1456 1457 chained_irq_enter(chip, desc); 1458 __gpio_irq_handler(bank); 1459 chained_irq_exit(chip, desc); 1460 } 1461 1462 static void st_gpio_irqmux_handler(struct irq_desc *desc) 1463 { 1464 struct irq_chip *chip = irq_desc_get_chip(desc); 1465 struct st_pinctrl *info = irq_desc_get_handler_data(desc); 1466 unsigned long status; 1467 int n; 1468 1469 chained_irq_enter(chip, desc); 1470 1471 status = readl(info->irqmux_base); 1472 1473 for_each_set_bit(n, &status, info->nbanks) 1474 __gpio_irq_handler(&info->banks[n]); 1475 1476 chained_irq_exit(chip, desc); 1477 } 1478 1479 static const struct gpio_chip st_gpio_template = { 1480 .request = gpiochip_generic_request, 1481 .free = gpiochip_generic_free, 1482 .get = st_gpio_get, 1483 .set = st_gpio_set, 1484 .direction_input = st_gpio_direction_input, 1485 .direction_output = st_gpio_direction_output, 1486 .get_direction = st_gpio_get_direction, 1487 .ngpio = ST_GPIO_PINS_PER_BANK, 1488 }; 1489 1490 static struct irq_chip st_gpio_irqchip = { 1491 .name = "GPIO", 1492 .irq_request_resources = st_gpio_irq_request_resources, 1493 .irq_release_resources = st_gpio_irq_release_resources, 1494 .irq_disable = st_gpio_irq_mask, 1495 .irq_mask = st_gpio_irq_mask, 1496 .irq_unmask = st_gpio_irq_unmask, 1497 .irq_set_type = st_gpio_irq_set_type, 1498 .flags = IRQCHIP_SKIP_SET_WAKE, 1499 }; 1500 1501 static int st_gpiolib_register_bank(struct st_pinctrl *info, 1502 int bank_nr, struct device_node *np) 1503 { 1504 struct st_gpio_bank *bank = &info->banks[bank_nr]; 1505 struct pinctrl_gpio_range *range = &bank->range; 1506 struct device *dev = info->dev; 1507 int bank_num = of_alias_get_id(np, "gpio"); 1508 struct resource res, irq_res; 1509 int err; 1510 1511 if (of_address_to_resource(np, 0, &res)) 1512 return -ENODEV; 1513 1514 bank->base = devm_ioremap_resource(dev, &res); 1515 if (IS_ERR(bank->base)) 1516 return PTR_ERR(bank->base); 1517 1518 bank->gpio_chip = st_gpio_template; 1519 bank->gpio_chip.base = bank_num * ST_GPIO_PINS_PER_BANK; 1520 bank->gpio_chip.ngpio = ST_GPIO_PINS_PER_BANK; 1521 bank->gpio_chip.of_node = np; 1522 bank->gpio_chip.parent = dev; 1523 spin_lock_init(&bank->lock); 1524 1525 of_property_read_string(np, "st,bank-name", &range->name); 1526 bank->gpio_chip.label = range->name; 1527 1528 range->id = bank_num; 1529 range->pin_base = range->base = range->id * ST_GPIO_PINS_PER_BANK; 1530 range->npins = bank->gpio_chip.ngpio; 1531 range->gc = &bank->gpio_chip; 1532 1533 /** 1534 * GPIO bank can have one of the two possible types of 1535 * interrupt-wirings. 1536 * 1537 * First type is via irqmux, single interrupt is used by multiple 1538 * gpio banks. This reduces number of overall interrupts numbers 1539 * required. All these banks belong to a single pincontroller. 1540 * _________ 1541 * | |----> [gpio-bank (n) ] 1542 * | |----> [gpio-bank (n + 1)] 1543 * [irqN]-- | irq-mux |----> [gpio-bank (n + 2)] 1544 * | |----> [gpio-bank (... )] 1545 * |_________|----> [gpio-bank (n + 7)] 1546 * 1547 * Second type has a dedicated interrupt per each gpio bank. 1548 * 1549 * [irqN]----> [gpio-bank (n)] 1550 */ 1551 1552 if (of_irq_to_resource(np, 0, &irq_res) > 0) { 1553 struct gpio_irq_chip *girq; 1554 int gpio_irq = irq_res.start; 1555 1556 /* This is not a valid IRQ */ 1557 if (gpio_irq <= 0) { 1558 dev_err(dev, "invalid IRQ for %pOF bank\n", np); 1559 goto skip_irq; 1560 } 1561 /* We need to have a mux as well */ 1562 if (!info->irqmux_base) { 1563 dev_err(dev, "no irqmux for %pOF bank\n", np); 1564 goto skip_irq; 1565 } 1566 1567 girq = &bank->gpio_chip.irq; 1568 girq->chip = &st_gpio_irqchip; 1569 girq->parent_handler = st_gpio_irq_handler; 1570 girq->num_parents = 1; 1571 girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents), 1572 GFP_KERNEL); 1573 if (!girq->parents) 1574 return -ENOMEM; 1575 girq->parents[0] = gpio_irq; 1576 girq->default_type = IRQ_TYPE_NONE; 1577 girq->handler = handle_simple_irq; 1578 } 1579 1580 skip_irq: 1581 err = gpiochip_add_data(&bank->gpio_chip, bank); 1582 if (err) 1583 return dev_err_probe(dev, err, "Failed to add gpiochip(%d)!\n", bank_num); 1584 dev_info(dev, "%s bank added.\n", range->name); 1585 1586 return 0; 1587 } 1588 1589 static const struct of_device_id st_pctl_of_match[] = { 1590 { .compatible = "st,stih407-sbc-pinctrl", .data = &stih407_data}, 1591 { .compatible = "st,stih407-front-pinctrl", .data = &stih407_data}, 1592 { .compatible = "st,stih407-rear-pinctrl", .data = &stih407_data}, 1593 { .compatible = "st,stih407-flash-pinctrl", .data = &stih407_flashdata}, 1594 { /* sentinel */ } 1595 }; 1596 1597 static int st_pctl_probe_dt(struct platform_device *pdev, 1598 struct pinctrl_desc *pctl_desc, struct st_pinctrl *info) 1599 { 1600 struct device *dev = &pdev->dev; 1601 int ret = 0; 1602 int i = 0, j = 0, k = 0, bank; 1603 struct pinctrl_pin_desc *pdesc; 1604 struct device_node *np = dev->of_node; 1605 struct device_node *child; 1606 int grp_index = 0; 1607 int irq = 0; 1608 1609 st_pctl_dt_child_count(info, np); 1610 if (!info->nbanks) 1611 return dev_err_probe(dev, -EINVAL, "you need at least one gpio bank\n"); 1612 1613 dev_info(dev, "nbanks = %d\n", info->nbanks); 1614 dev_info(dev, "nfunctions = %d\n", info->nfunctions); 1615 dev_info(dev, "ngroups = %d\n", info->ngroups); 1616 1617 info->functions = devm_kcalloc(dev, info->nfunctions, sizeof(*info->functions), GFP_KERNEL); 1618 1619 info->groups = devm_kcalloc(dev, info->ngroups, sizeof(*info->groups), GFP_KERNEL); 1620 1621 info->banks = devm_kcalloc(dev, info->nbanks, sizeof(*info->banks), GFP_KERNEL); 1622 1623 if (!info->functions || !info->groups || !info->banks) 1624 return -ENOMEM; 1625 1626 info->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg"); 1627 if (IS_ERR(info->regmap)) 1628 return dev_err_probe(dev, PTR_ERR(info->regmap), "No syscfg phandle specified\n"); 1629 info->data = of_match_node(st_pctl_of_match, np)->data; 1630 1631 irq = platform_get_irq(pdev, 0); 1632 1633 if (irq > 0) { 1634 info->irqmux_base = devm_platform_ioremap_resource_byname(pdev, "irqmux"); 1635 if (IS_ERR(info->irqmux_base)) 1636 return PTR_ERR(info->irqmux_base); 1637 1638 irq_set_chained_handler_and_data(irq, st_gpio_irqmux_handler, 1639 info); 1640 } 1641 1642 pctl_desc->npins = info->nbanks * ST_GPIO_PINS_PER_BANK; 1643 pdesc = devm_kcalloc(dev, pctl_desc->npins, sizeof(*pdesc), GFP_KERNEL); 1644 if (!pdesc) 1645 return -ENOMEM; 1646 1647 pctl_desc->pins = pdesc; 1648 1649 bank = 0; 1650 for_each_child_of_node(np, child) { 1651 if (of_property_read_bool(child, "gpio-controller")) { 1652 const char *bank_name = NULL; 1653 char **pin_names; 1654 1655 ret = st_gpiolib_register_bank(info, bank, child); 1656 if (ret) { 1657 of_node_put(child); 1658 return ret; 1659 } 1660 1661 k = info->banks[bank].range.pin_base; 1662 bank_name = info->banks[bank].range.name; 1663 1664 pin_names = devm_kasprintf_strarray(dev, bank_name, ST_GPIO_PINS_PER_BANK); 1665 if (IS_ERR(pin_names)) { 1666 of_node_put(child); 1667 return PTR_ERR(pin_names); 1668 } 1669 1670 for (j = 0; j < ST_GPIO_PINS_PER_BANK; j++, k++) { 1671 pdesc->number = k; 1672 pdesc->name = pin_names[j]; 1673 pdesc++; 1674 } 1675 st_parse_syscfgs(info, bank, child); 1676 bank++; 1677 } else { 1678 ret = st_pctl_parse_functions(child, info, 1679 i++, &grp_index); 1680 if (ret) { 1681 dev_err(dev, "No functions found.\n"); 1682 of_node_put(child); 1683 return ret; 1684 } 1685 } 1686 } 1687 1688 return 0; 1689 } 1690 1691 static int st_pctl_probe(struct platform_device *pdev) 1692 { 1693 struct device *dev = &pdev->dev; 1694 struct st_pinctrl *info; 1695 struct pinctrl_desc *pctl_desc; 1696 int ret, i; 1697 1698 if (!dev->of_node) { 1699 dev_err(dev, "device node not found.\n"); 1700 return -EINVAL; 1701 } 1702 1703 pctl_desc = devm_kzalloc(dev, sizeof(*pctl_desc), GFP_KERNEL); 1704 if (!pctl_desc) 1705 return -ENOMEM; 1706 1707 info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL); 1708 if (!info) 1709 return -ENOMEM; 1710 1711 info->dev = dev; 1712 platform_set_drvdata(pdev, info); 1713 ret = st_pctl_probe_dt(pdev, pctl_desc, info); 1714 if (ret) 1715 return ret; 1716 1717 pctl_desc->owner = THIS_MODULE; 1718 pctl_desc->pctlops = &st_pctlops; 1719 pctl_desc->pmxops = &st_pmxops; 1720 pctl_desc->confops = &st_confops; 1721 pctl_desc->name = dev_name(dev); 1722 1723 info->pctl = devm_pinctrl_register(dev, pctl_desc, info); 1724 if (IS_ERR(info->pctl)) 1725 return dev_err_probe(dev, PTR_ERR(info->pctl), "Failed pinctrl registration\n"); 1726 1727 for (i = 0; i < info->nbanks; i++) 1728 pinctrl_add_gpio_range(info->pctl, &info->banks[i].range); 1729 1730 return 0; 1731 } 1732 1733 static struct platform_driver st_pctl_driver = { 1734 .driver = { 1735 .name = "st-pinctrl", 1736 .of_match_table = st_pctl_of_match, 1737 }, 1738 .probe = st_pctl_probe, 1739 }; 1740 1741 static int __init st_pctl_init(void) 1742 { 1743 return platform_driver_register(&st_pctl_driver); 1744 } 1745 arch_initcall(st_pctl_init); 1746