1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2013 STMicroelectronics (R&D) Limited. 4 * Authors: 5 * Srinivas Kandagatla <srinivas.kandagatla@st.com> 6 */ 7 8 #include <linux/init.h> 9 #include <linux/module.h> 10 #include <linux/slab.h> 11 #include <linux/err.h> 12 #include <linux/io.h> 13 #include <linux/of.h> 14 #include <linux/of_irq.h> 15 #include <linux/of_gpio.h> /* of_get_named_gpio() */ 16 #include <linux/of_address.h> 17 #include <linux/gpio/driver.h> 18 #include <linux/regmap.h> 19 #include <linux/mfd/syscon.h> 20 #include <linux/pinctrl/pinctrl.h> 21 #include <linux/pinctrl/pinmux.h> 22 #include <linux/pinctrl/pinconf.h> 23 #include <linux/platform_device.h> 24 #include "core.h" 25 26 /* PIO Block registers */ 27 /* PIO output */ 28 #define REG_PIO_POUT 0x00 29 /* Set bits of POUT */ 30 #define REG_PIO_SET_POUT 0x04 31 /* Clear bits of POUT */ 32 #define REG_PIO_CLR_POUT 0x08 33 /* PIO input */ 34 #define REG_PIO_PIN 0x10 35 /* PIO configuration */ 36 #define REG_PIO_PC(n) (0x20 + (n) * 0x10) 37 /* Set bits of PC[2:0] */ 38 #define REG_PIO_SET_PC(n) (0x24 + (n) * 0x10) 39 /* Clear bits of PC[2:0] */ 40 #define REG_PIO_CLR_PC(n) (0x28 + (n) * 0x10) 41 /* PIO input comparison */ 42 #define REG_PIO_PCOMP 0x50 43 /* Set bits of PCOMP */ 44 #define REG_PIO_SET_PCOMP 0x54 45 /* Clear bits of PCOMP */ 46 #define REG_PIO_CLR_PCOMP 0x58 47 /* PIO input comparison mask */ 48 #define REG_PIO_PMASK 0x60 49 /* Set bits of PMASK */ 50 #define REG_PIO_SET_PMASK 0x64 51 /* Clear bits of PMASK */ 52 #define REG_PIO_CLR_PMASK 0x68 53 54 #define ST_GPIO_DIRECTION_BIDIR 0x1 55 #define ST_GPIO_DIRECTION_OUT 0x2 56 #define ST_GPIO_DIRECTION_IN 0x4 57 58 /** 59 * Packed style retime configuration. 60 * There are two registers cfg0 and cfg1 in this style for each bank. 61 * Each field in this register is 8 bit corresponding to 8 pins in the bank. 62 */ 63 #define RT_P_CFGS_PER_BANK 2 64 #define RT_P_CFG0_CLK1NOTCLK0_FIELD(reg) REG_FIELD(reg, 0, 7) 65 #define RT_P_CFG0_DELAY_0_FIELD(reg) REG_FIELD(reg, 16, 23) 66 #define RT_P_CFG0_DELAY_1_FIELD(reg) REG_FIELD(reg, 24, 31) 67 #define RT_P_CFG1_INVERTCLK_FIELD(reg) REG_FIELD(reg, 0, 7) 68 #define RT_P_CFG1_RETIME_FIELD(reg) REG_FIELD(reg, 8, 15) 69 #define RT_P_CFG1_CLKNOTDATA_FIELD(reg) REG_FIELD(reg, 16, 23) 70 #define RT_P_CFG1_DOUBLE_EDGE_FIELD(reg) REG_FIELD(reg, 24, 31) 71 72 /** 73 * Dedicated style retime Configuration register 74 * each register is dedicated per pin. 75 */ 76 #define RT_D_CFGS_PER_BANK 8 77 #define RT_D_CFG_CLK_SHIFT 0 78 #define RT_D_CFG_CLK_MASK (0x3 << 0) 79 #define RT_D_CFG_CLKNOTDATA_SHIFT 2 80 #define RT_D_CFG_CLKNOTDATA_MASK BIT(2) 81 #define RT_D_CFG_DELAY_SHIFT 3 82 #define RT_D_CFG_DELAY_MASK (0xf << 3) 83 #define RT_D_CFG_DELAY_INNOTOUT_SHIFT 7 84 #define RT_D_CFG_DELAY_INNOTOUT_MASK BIT(7) 85 #define RT_D_CFG_DOUBLE_EDGE_SHIFT 8 86 #define RT_D_CFG_DOUBLE_EDGE_MASK BIT(8) 87 #define RT_D_CFG_INVERTCLK_SHIFT 9 88 #define RT_D_CFG_INVERTCLK_MASK BIT(9) 89 #define RT_D_CFG_RETIME_SHIFT 10 90 #define RT_D_CFG_RETIME_MASK BIT(10) 91 92 /* 93 * Pinconf is represented in an opaque unsigned long variable. 94 * Below is the bit allocation details for each possible configuration. 95 * All the bit fields can be encapsulated into four variables 96 * (direction, retime-type, retime-clk, retime-delay) 97 * 98 * +----------------+ 99 *[31:28]| reserved-3 | 100 * +----------------+------------- 101 *[27] | oe | | 102 * +----------------+ v 103 *[26] | pu | [Direction ] 104 * +----------------+ ^ 105 *[25] | od | | 106 * +----------------+------------- 107 *[24] | reserved-2 | 108 * +----------------+------------- 109 *[23] | retime | | 110 * +----------------+ | 111 *[22] | retime-invclk | | 112 * +----------------+ v 113 *[21] |retime-clknotdat| [Retime-type ] 114 * +----------------+ ^ 115 *[20] | retime-de | | 116 * +----------------+------------- 117 *[19:18]| retime-clk |------>[Retime-Clk ] 118 * +----------------+ 119 *[17:16]| reserved-1 | 120 * +----------------+ 121 *[15..0]| retime-delay |------>[Retime Delay] 122 * +----------------+ 123 */ 124 125 #define ST_PINCONF_UNPACK(conf, param)\ 126 ((conf >> ST_PINCONF_ ##param ##_SHIFT) \ 127 & ST_PINCONF_ ##param ##_MASK) 128 129 #define ST_PINCONF_PACK(conf, val, param) (conf |=\ 130 ((val & ST_PINCONF_ ##param ##_MASK) << \ 131 ST_PINCONF_ ##param ##_SHIFT)) 132 133 /* Output enable */ 134 #define ST_PINCONF_OE_MASK 0x1 135 #define ST_PINCONF_OE_SHIFT 27 136 #define ST_PINCONF_OE BIT(27) 137 #define ST_PINCONF_UNPACK_OE(conf) ST_PINCONF_UNPACK(conf, OE) 138 #define ST_PINCONF_PACK_OE(conf) ST_PINCONF_PACK(conf, 1, OE) 139 140 /* Pull Up */ 141 #define ST_PINCONF_PU_MASK 0x1 142 #define ST_PINCONF_PU_SHIFT 26 143 #define ST_PINCONF_PU BIT(26) 144 #define ST_PINCONF_UNPACK_PU(conf) ST_PINCONF_UNPACK(conf, PU) 145 #define ST_PINCONF_PACK_PU(conf) ST_PINCONF_PACK(conf, 1, PU) 146 147 /* Open Drain */ 148 #define ST_PINCONF_OD_MASK 0x1 149 #define ST_PINCONF_OD_SHIFT 25 150 #define ST_PINCONF_OD BIT(25) 151 #define ST_PINCONF_UNPACK_OD(conf) ST_PINCONF_UNPACK(conf, OD) 152 #define ST_PINCONF_PACK_OD(conf) ST_PINCONF_PACK(conf, 1, OD) 153 154 #define ST_PINCONF_RT_MASK 0x1 155 #define ST_PINCONF_RT_SHIFT 23 156 #define ST_PINCONF_RT BIT(23) 157 #define ST_PINCONF_UNPACK_RT(conf) ST_PINCONF_UNPACK(conf, RT) 158 #define ST_PINCONF_PACK_RT(conf) ST_PINCONF_PACK(conf, 1, RT) 159 160 #define ST_PINCONF_RT_INVERTCLK_MASK 0x1 161 #define ST_PINCONF_RT_INVERTCLK_SHIFT 22 162 #define ST_PINCONF_RT_INVERTCLK BIT(22) 163 #define ST_PINCONF_UNPACK_RT_INVERTCLK(conf) \ 164 ST_PINCONF_UNPACK(conf, RT_INVERTCLK) 165 #define ST_PINCONF_PACK_RT_INVERTCLK(conf) \ 166 ST_PINCONF_PACK(conf, 1, RT_INVERTCLK) 167 168 #define ST_PINCONF_RT_CLKNOTDATA_MASK 0x1 169 #define ST_PINCONF_RT_CLKNOTDATA_SHIFT 21 170 #define ST_PINCONF_RT_CLKNOTDATA BIT(21) 171 #define ST_PINCONF_UNPACK_RT_CLKNOTDATA(conf) \ 172 ST_PINCONF_UNPACK(conf, RT_CLKNOTDATA) 173 #define ST_PINCONF_PACK_RT_CLKNOTDATA(conf) \ 174 ST_PINCONF_PACK(conf, 1, RT_CLKNOTDATA) 175 176 #define ST_PINCONF_RT_DOUBLE_EDGE_MASK 0x1 177 #define ST_PINCONF_RT_DOUBLE_EDGE_SHIFT 20 178 #define ST_PINCONF_RT_DOUBLE_EDGE BIT(20) 179 #define ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(conf) \ 180 ST_PINCONF_UNPACK(conf, RT_DOUBLE_EDGE) 181 #define ST_PINCONF_PACK_RT_DOUBLE_EDGE(conf) \ 182 ST_PINCONF_PACK(conf, 1, RT_DOUBLE_EDGE) 183 184 #define ST_PINCONF_RT_CLK_MASK 0x3 185 #define ST_PINCONF_RT_CLK_SHIFT 18 186 #define ST_PINCONF_RT_CLK BIT(18) 187 #define ST_PINCONF_UNPACK_RT_CLK(conf) ST_PINCONF_UNPACK(conf, RT_CLK) 188 #define ST_PINCONF_PACK_RT_CLK(conf, val) ST_PINCONF_PACK(conf, val, RT_CLK) 189 190 /* RETIME_DELAY in Pico Secs */ 191 #define ST_PINCONF_RT_DELAY_MASK 0xffff 192 #define ST_PINCONF_RT_DELAY_SHIFT 0 193 #define ST_PINCONF_UNPACK_RT_DELAY(conf) ST_PINCONF_UNPACK(conf, RT_DELAY) 194 #define ST_PINCONF_PACK_RT_DELAY(conf, val) \ 195 ST_PINCONF_PACK(conf, val, RT_DELAY) 196 197 #define ST_GPIO_PINS_PER_BANK (8) 198 #define OF_GPIO_ARGS_MIN (4) 199 #define OF_RT_ARGS_MIN (2) 200 201 #define gpio_range_to_bank(chip) \ 202 container_of(chip, struct st_gpio_bank, range) 203 204 #define pc_to_bank(pc) \ 205 container_of(pc, struct st_gpio_bank, pc) 206 207 enum st_retime_style { 208 st_retime_style_none, 209 st_retime_style_packed, 210 st_retime_style_dedicated, 211 }; 212 213 struct st_retime_dedicated { 214 struct regmap_field *rt[ST_GPIO_PINS_PER_BANK]; 215 }; 216 217 struct st_retime_packed { 218 struct regmap_field *clk1notclk0; 219 struct regmap_field *delay_0; 220 struct regmap_field *delay_1; 221 struct regmap_field *invertclk; 222 struct regmap_field *retime; 223 struct regmap_field *clknotdata; 224 struct regmap_field *double_edge; 225 }; 226 227 struct st_pio_control { 228 u32 rt_pin_mask; 229 struct regmap_field *alt, *oe, *pu, *od; 230 /* retiming */ 231 union { 232 struct st_retime_packed rt_p; 233 struct st_retime_dedicated rt_d; 234 } rt; 235 }; 236 237 struct st_pctl_data { 238 const enum st_retime_style rt_style; 239 const unsigned int *input_delays; 240 const int ninput_delays; 241 const unsigned int *output_delays; 242 const int noutput_delays; 243 /* register offset information */ 244 const int alt, oe, pu, od, rt; 245 }; 246 247 struct st_pinconf { 248 int pin; 249 const char *name; 250 unsigned long config; 251 int altfunc; 252 }; 253 254 struct st_pmx_func { 255 const char *name; 256 const char **groups; 257 unsigned ngroups; 258 }; 259 260 struct st_pctl_group { 261 const char *name; 262 unsigned int *pins; 263 unsigned npins; 264 struct st_pinconf *pin_conf; 265 }; 266 267 /* 268 * Edge triggers are not supported at hardware level, it is supported by 269 * software by exploiting the level trigger support in hardware. 270 * Software uses a virtual register (EDGE_CONF) for edge trigger configuration 271 * of each gpio pin in a GPIO bank. 272 * 273 * Each bank has a 32 bit EDGE_CONF register which is divided in to 8 parts of 274 * 4-bits. Each 4-bit space is allocated for each pin in a gpio bank. 275 * 276 * bit allocation per pin is: 277 * Bits: [0 - 3] | [4 - 7] [8 - 11] ... ... ... ... [ 28 - 31] 278 * -------------------------------------------------------- 279 * | pin-0 | pin-2 | pin-3 | ... ... ... ... | pin -7 | 280 * -------------------------------------------------------- 281 * 282 * A pin can have one of following the values in its edge configuration field. 283 * 284 * ------- ---------------------------- 285 * [0-3] - Description 286 * ------- ---------------------------- 287 * 0000 - No edge IRQ. 288 * 0001 - Falling edge IRQ. 289 * 0010 - Rising edge IRQ. 290 * 0011 - Rising and Falling edge IRQ. 291 * ------- ---------------------------- 292 */ 293 294 #define ST_IRQ_EDGE_CONF_BITS_PER_PIN 4 295 #define ST_IRQ_EDGE_MASK 0xf 296 #define ST_IRQ_EDGE_FALLING BIT(0) 297 #define ST_IRQ_EDGE_RISING BIT(1) 298 #define ST_IRQ_EDGE_BOTH (BIT(0) | BIT(1)) 299 300 #define ST_IRQ_RISING_EDGE_CONF(pin) \ 301 (ST_IRQ_EDGE_RISING << (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN)) 302 303 #define ST_IRQ_FALLING_EDGE_CONF(pin) \ 304 (ST_IRQ_EDGE_FALLING << (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN)) 305 306 #define ST_IRQ_BOTH_EDGE_CONF(pin) \ 307 (ST_IRQ_EDGE_BOTH << (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN)) 308 309 #define ST_IRQ_EDGE_CONF(conf, pin) \ 310 (conf >> (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN) & ST_IRQ_EDGE_MASK) 311 312 struct st_gpio_bank { 313 struct gpio_chip gpio_chip; 314 struct pinctrl_gpio_range range; 315 void __iomem *base; 316 struct st_pio_control pc; 317 unsigned long irq_edge_conf; 318 spinlock_t lock; 319 }; 320 321 struct st_pinctrl { 322 struct device *dev; 323 struct pinctrl_dev *pctl; 324 struct st_gpio_bank *banks; 325 int nbanks; 326 struct st_pmx_func *functions; 327 int nfunctions; 328 struct st_pctl_group *groups; 329 int ngroups; 330 struct regmap *regmap; 331 const struct st_pctl_data *data; 332 void __iomem *irqmux_base; 333 }; 334 335 /* SOC specific data */ 336 337 static const unsigned int stih407_delays[] = {0, 300, 500, 750, 1000, 1250, 338 1500, 1750, 2000, 2250, 2500, 2750, 3000, 3250 }; 339 340 static const struct st_pctl_data stih407_data = { 341 .rt_style = st_retime_style_dedicated, 342 .input_delays = stih407_delays, 343 .ninput_delays = ARRAY_SIZE(stih407_delays), 344 .output_delays = stih407_delays, 345 .noutput_delays = ARRAY_SIZE(stih407_delays), 346 .alt = 0, .oe = 40, .pu = 50, .od = 60, .rt = 100, 347 }; 348 349 static const struct st_pctl_data stih407_flashdata = { 350 .rt_style = st_retime_style_none, 351 .input_delays = stih407_delays, 352 .ninput_delays = ARRAY_SIZE(stih407_delays), 353 .output_delays = stih407_delays, 354 .noutput_delays = ARRAY_SIZE(stih407_delays), 355 .alt = 0, 356 .oe = -1, /* Not Available */ 357 .pu = -1, /* Not Available */ 358 .od = 60, 359 .rt = 100, 360 }; 361 362 static struct st_pio_control *st_get_pio_control( 363 struct pinctrl_dev *pctldev, int pin) 364 { 365 struct pinctrl_gpio_range *range = 366 pinctrl_find_gpio_range_from_pin(pctldev, pin); 367 struct st_gpio_bank *bank = gpio_range_to_bank(range); 368 369 return &bank->pc; 370 } 371 372 /* Low level functions.. */ 373 static inline int st_gpio_bank(int gpio) 374 { 375 return gpio/ST_GPIO_PINS_PER_BANK; 376 } 377 378 static inline int st_gpio_pin(int gpio) 379 { 380 return gpio%ST_GPIO_PINS_PER_BANK; 381 } 382 383 static void st_pinconf_set_config(struct st_pio_control *pc, 384 int pin, unsigned long config) 385 { 386 struct regmap_field *output_enable = pc->oe; 387 struct regmap_field *pull_up = pc->pu; 388 struct regmap_field *open_drain = pc->od; 389 unsigned int oe_value, pu_value, od_value; 390 unsigned long mask = BIT(pin); 391 392 if (output_enable) { 393 regmap_field_read(output_enable, &oe_value); 394 oe_value &= ~mask; 395 if (config & ST_PINCONF_OE) 396 oe_value |= mask; 397 regmap_field_write(output_enable, oe_value); 398 } 399 400 if (pull_up) { 401 regmap_field_read(pull_up, &pu_value); 402 pu_value &= ~mask; 403 if (config & ST_PINCONF_PU) 404 pu_value |= mask; 405 regmap_field_write(pull_up, pu_value); 406 } 407 408 if (open_drain) { 409 regmap_field_read(open_drain, &od_value); 410 od_value &= ~mask; 411 if (config & ST_PINCONF_OD) 412 od_value |= mask; 413 regmap_field_write(open_drain, od_value); 414 } 415 } 416 417 static void st_pctl_set_function(struct st_pio_control *pc, 418 int pin_id, int function) 419 { 420 struct regmap_field *alt = pc->alt; 421 unsigned int val; 422 int pin = st_gpio_pin(pin_id); 423 int offset = pin * 4; 424 425 if (!alt) 426 return; 427 428 regmap_field_read(alt, &val); 429 val &= ~(0xf << offset); 430 val |= function << offset; 431 regmap_field_write(alt, val); 432 } 433 434 static unsigned int st_pctl_get_pin_function(struct st_pio_control *pc, int pin) 435 { 436 struct regmap_field *alt = pc->alt; 437 unsigned int val; 438 int offset = pin * 4; 439 440 if (!alt) 441 return 0; 442 443 regmap_field_read(alt, &val); 444 445 return (val >> offset) & 0xf; 446 } 447 448 static unsigned long st_pinconf_delay_to_bit(unsigned int delay, 449 const struct st_pctl_data *data, unsigned long config) 450 { 451 const unsigned int *delay_times; 452 int num_delay_times, i, closest_index = -1; 453 unsigned int closest_divergence = UINT_MAX; 454 455 if (ST_PINCONF_UNPACK_OE(config)) { 456 delay_times = data->output_delays; 457 num_delay_times = data->noutput_delays; 458 } else { 459 delay_times = data->input_delays; 460 num_delay_times = data->ninput_delays; 461 } 462 463 for (i = 0; i < num_delay_times; i++) { 464 unsigned int divergence = abs(delay - delay_times[i]); 465 466 if (divergence == 0) 467 return i; 468 469 if (divergence < closest_divergence) { 470 closest_divergence = divergence; 471 closest_index = i; 472 } 473 } 474 475 pr_warn("Attempt to set delay %d, closest available %d\n", 476 delay, delay_times[closest_index]); 477 478 return closest_index; 479 } 480 481 static unsigned long st_pinconf_bit_to_delay(unsigned int index, 482 const struct st_pctl_data *data, unsigned long output) 483 { 484 const unsigned int *delay_times; 485 int num_delay_times; 486 487 if (output) { 488 delay_times = data->output_delays; 489 num_delay_times = data->noutput_delays; 490 } else { 491 delay_times = data->input_delays; 492 num_delay_times = data->ninput_delays; 493 } 494 495 if (index < num_delay_times) { 496 return delay_times[index]; 497 } else { 498 pr_warn("Delay not found in/out delay list\n"); 499 return 0; 500 } 501 } 502 503 static void st_regmap_field_bit_set_clear_pin(struct regmap_field *field, 504 int enable, int pin) 505 { 506 unsigned int val = 0; 507 508 regmap_field_read(field, &val); 509 if (enable) 510 val |= BIT(pin); 511 else 512 val &= ~BIT(pin); 513 regmap_field_write(field, val); 514 } 515 516 static void st_pinconf_set_retime_packed(struct st_pinctrl *info, 517 struct st_pio_control *pc, unsigned long config, int pin) 518 { 519 const struct st_pctl_data *data = info->data; 520 struct st_retime_packed *rt_p = &pc->rt.rt_p; 521 unsigned int delay; 522 523 st_regmap_field_bit_set_clear_pin(rt_p->clk1notclk0, 524 ST_PINCONF_UNPACK_RT_CLK(config), pin); 525 526 st_regmap_field_bit_set_clear_pin(rt_p->clknotdata, 527 ST_PINCONF_UNPACK_RT_CLKNOTDATA(config), pin); 528 529 st_regmap_field_bit_set_clear_pin(rt_p->double_edge, 530 ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(config), pin); 531 532 st_regmap_field_bit_set_clear_pin(rt_p->invertclk, 533 ST_PINCONF_UNPACK_RT_INVERTCLK(config), pin); 534 535 st_regmap_field_bit_set_clear_pin(rt_p->retime, 536 ST_PINCONF_UNPACK_RT(config), pin); 537 538 delay = st_pinconf_delay_to_bit(ST_PINCONF_UNPACK_RT_DELAY(config), 539 data, config); 540 /* 2 bit delay, lsb */ 541 st_regmap_field_bit_set_clear_pin(rt_p->delay_0, delay & 0x1, pin); 542 /* 2 bit delay, msb */ 543 st_regmap_field_bit_set_clear_pin(rt_p->delay_1, delay & 0x2, pin); 544 545 } 546 547 static void st_pinconf_set_retime_dedicated(struct st_pinctrl *info, 548 struct st_pio_control *pc, unsigned long config, int pin) 549 { 550 int input = ST_PINCONF_UNPACK_OE(config) ? 0 : 1; 551 int clk = ST_PINCONF_UNPACK_RT_CLK(config); 552 int clknotdata = ST_PINCONF_UNPACK_RT_CLKNOTDATA(config); 553 int double_edge = ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(config); 554 int invertclk = ST_PINCONF_UNPACK_RT_INVERTCLK(config); 555 int retime = ST_PINCONF_UNPACK_RT(config); 556 557 unsigned long delay = st_pinconf_delay_to_bit( 558 ST_PINCONF_UNPACK_RT_DELAY(config), 559 info->data, config); 560 struct st_retime_dedicated *rt_d = &pc->rt.rt_d; 561 562 unsigned long retime_config = 563 ((clk) << RT_D_CFG_CLK_SHIFT) | 564 ((delay) << RT_D_CFG_DELAY_SHIFT) | 565 ((input) << RT_D_CFG_DELAY_INNOTOUT_SHIFT) | 566 ((retime) << RT_D_CFG_RETIME_SHIFT) | 567 ((clknotdata) << RT_D_CFG_CLKNOTDATA_SHIFT) | 568 ((invertclk) << RT_D_CFG_INVERTCLK_SHIFT) | 569 ((double_edge) << RT_D_CFG_DOUBLE_EDGE_SHIFT); 570 571 regmap_field_write(rt_d->rt[pin], retime_config); 572 } 573 574 static void st_pinconf_get_direction(struct st_pio_control *pc, 575 int pin, unsigned long *config) 576 { 577 unsigned int oe_value, pu_value, od_value; 578 579 if (pc->oe) { 580 regmap_field_read(pc->oe, &oe_value); 581 if (oe_value & BIT(pin)) 582 ST_PINCONF_PACK_OE(*config); 583 } 584 585 if (pc->pu) { 586 regmap_field_read(pc->pu, &pu_value); 587 if (pu_value & BIT(pin)) 588 ST_PINCONF_PACK_PU(*config); 589 } 590 591 if (pc->od) { 592 regmap_field_read(pc->od, &od_value); 593 if (od_value & BIT(pin)) 594 ST_PINCONF_PACK_OD(*config); 595 } 596 } 597 598 static int st_pinconf_get_retime_packed(struct st_pinctrl *info, 599 struct st_pio_control *pc, int pin, unsigned long *config) 600 { 601 const struct st_pctl_data *data = info->data; 602 struct st_retime_packed *rt_p = &pc->rt.rt_p; 603 unsigned int delay_bits, delay, delay0, delay1, val; 604 int output = ST_PINCONF_UNPACK_OE(*config); 605 606 if (!regmap_field_read(rt_p->retime, &val) && (val & BIT(pin))) 607 ST_PINCONF_PACK_RT(*config); 608 609 if (!regmap_field_read(rt_p->clk1notclk0, &val) && (val & BIT(pin))) 610 ST_PINCONF_PACK_RT_CLK(*config, 1); 611 612 if (!regmap_field_read(rt_p->clknotdata, &val) && (val & BIT(pin))) 613 ST_PINCONF_PACK_RT_CLKNOTDATA(*config); 614 615 if (!regmap_field_read(rt_p->double_edge, &val) && (val & BIT(pin))) 616 ST_PINCONF_PACK_RT_DOUBLE_EDGE(*config); 617 618 if (!regmap_field_read(rt_p->invertclk, &val) && (val & BIT(pin))) 619 ST_PINCONF_PACK_RT_INVERTCLK(*config); 620 621 regmap_field_read(rt_p->delay_0, &delay0); 622 regmap_field_read(rt_p->delay_1, &delay1); 623 delay_bits = (((delay1 & BIT(pin)) ? 1 : 0) << 1) | 624 (((delay0 & BIT(pin)) ? 1 : 0)); 625 delay = st_pinconf_bit_to_delay(delay_bits, data, output); 626 ST_PINCONF_PACK_RT_DELAY(*config, delay); 627 628 return 0; 629 } 630 631 static int st_pinconf_get_retime_dedicated(struct st_pinctrl *info, 632 struct st_pio_control *pc, int pin, unsigned long *config) 633 { 634 unsigned int value; 635 unsigned long delay_bits, delay, rt_clk; 636 int output = ST_PINCONF_UNPACK_OE(*config); 637 struct st_retime_dedicated *rt_d = &pc->rt.rt_d; 638 639 regmap_field_read(rt_d->rt[pin], &value); 640 641 rt_clk = (value & RT_D_CFG_CLK_MASK) >> RT_D_CFG_CLK_SHIFT; 642 ST_PINCONF_PACK_RT_CLK(*config, rt_clk); 643 644 delay_bits = (value & RT_D_CFG_DELAY_MASK) >> RT_D_CFG_DELAY_SHIFT; 645 delay = st_pinconf_bit_to_delay(delay_bits, info->data, output); 646 ST_PINCONF_PACK_RT_DELAY(*config, delay); 647 648 if (value & RT_D_CFG_CLKNOTDATA_MASK) 649 ST_PINCONF_PACK_RT_CLKNOTDATA(*config); 650 651 if (value & RT_D_CFG_DOUBLE_EDGE_MASK) 652 ST_PINCONF_PACK_RT_DOUBLE_EDGE(*config); 653 654 if (value & RT_D_CFG_INVERTCLK_MASK) 655 ST_PINCONF_PACK_RT_INVERTCLK(*config); 656 657 if (value & RT_D_CFG_RETIME_MASK) 658 ST_PINCONF_PACK_RT(*config); 659 660 return 0; 661 } 662 663 /* GPIO related functions */ 664 665 static inline void __st_gpio_set(struct st_gpio_bank *bank, 666 unsigned offset, int value) 667 { 668 if (value) 669 writel(BIT(offset), bank->base + REG_PIO_SET_POUT); 670 else 671 writel(BIT(offset), bank->base + REG_PIO_CLR_POUT); 672 } 673 674 static void st_gpio_direction(struct st_gpio_bank *bank, 675 unsigned int gpio, unsigned int direction) 676 { 677 int offset = st_gpio_pin(gpio); 678 int i = 0; 679 /** 680 * There are three configuration registers (PIOn_PC0, PIOn_PC1 681 * and PIOn_PC2) for each port. These are used to configure the 682 * PIO port pins. Each pin can be configured as an input, output, 683 * bidirectional, or alternative function pin. Three bits, one bit 684 * from each of the three registers, configure the corresponding bit of 685 * the port. Valid bit settings is: 686 * 687 * PC2 PC1 PC0 Direction. 688 * 0 0 0 [Input Weak pull-up] 689 * 0 0 or 1 1 [Bidirection] 690 * 0 1 0 [Output] 691 * 1 0 0 [Input] 692 * 693 * PIOn_SET_PC and PIOn_CLR_PC registers are used to set and clear bits 694 * individually. 695 */ 696 for (i = 0; i <= 2; i++) { 697 if (direction & BIT(i)) 698 writel(BIT(offset), bank->base + REG_PIO_SET_PC(i)); 699 else 700 writel(BIT(offset), bank->base + REG_PIO_CLR_PC(i)); 701 } 702 } 703 704 static int st_gpio_get(struct gpio_chip *chip, unsigned offset) 705 { 706 struct st_gpio_bank *bank = gpiochip_get_data(chip); 707 708 return !!(readl(bank->base + REG_PIO_PIN) & BIT(offset)); 709 } 710 711 static void st_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 712 { 713 struct st_gpio_bank *bank = gpiochip_get_data(chip); 714 __st_gpio_set(bank, offset, value); 715 } 716 717 static int st_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 718 { 719 pinctrl_gpio_direction_input(chip->base + offset); 720 721 return 0; 722 } 723 724 static int st_gpio_direction_output(struct gpio_chip *chip, 725 unsigned offset, int value) 726 { 727 struct st_gpio_bank *bank = gpiochip_get_data(chip); 728 729 __st_gpio_set(bank, offset, value); 730 pinctrl_gpio_direction_output(chip->base + offset); 731 732 return 0; 733 } 734 735 static int st_gpio_get_direction(struct gpio_chip *chip, unsigned offset) 736 { 737 struct st_gpio_bank *bank = gpiochip_get_data(chip); 738 struct st_pio_control pc = bank->pc; 739 unsigned long config; 740 unsigned int direction = 0; 741 unsigned int function; 742 unsigned int value; 743 int i = 0; 744 745 /* Alternate function direction is handled by Pinctrl */ 746 function = st_pctl_get_pin_function(&pc, offset); 747 if (function) { 748 st_pinconf_get_direction(&pc, offset, &config); 749 return !ST_PINCONF_UNPACK_OE(config); 750 } 751 752 /* 753 * GPIO direction is handled differently 754 * - See st_gpio_direction() above for an explanation 755 */ 756 for (i = 0; i <= 2; i++) { 757 value = readl(bank->base + REG_PIO_PC(i)); 758 direction |= ((value >> offset) & 0x1) << i; 759 } 760 761 return (direction == ST_GPIO_DIRECTION_IN); 762 } 763 764 /* Pinctrl Groups */ 765 static int st_pctl_get_groups_count(struct pinctrl_dev *pctldev) 766 { 767 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 768 769 return info->ngroups; 770 } 771 772 static const char *st_pctl_get_group_name(struct pinctrl_dev *pctldev, 773 unsigned selector) 774 { 775 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 776 777 return info->groups[selector].name; 778 } 779 780 static int st_pctl_get_group_pins(struct pinctrl_dev *pctldev, 781 unsigned selector, const unsigned **pins, unsigned *npins) 782 { 783 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 784 785 if (selector >= info->ngroups) 786 return -EINVAL; 787 788 *pins = info->groups[selector].pins; 789 *npins = info->groups[selector].npins; 790 791 return 0; 792 } 793 794 static inline const struct st_pctl_group *st_pctl_find_group_by_name( 795 const struct st_pinctrl *info, const char *name) 796 { 797 int i; 798 799 for (i = 0; i < info->ngroups; i++) { 800 if (!strcmp(info->groups[i].name, name)) 801 return &info->groups[i]; 802 } 803 804 return NULL; 805 } 806 807 static int st_pctl_dt_node_to_map(struct pinctrl_dev *pctldev, 808 struct device_node *np, struct pinctrl_map **map, unsigned *num_maps) 809 { 810 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 811 const struct st_pctl_group *grp; 812 struct pinctrl_map *new_map; 813 struct device_node *parent; 814 int map_num, i; 815 816 grp = st_pctl_find_group_by_name(info, np->name); 817 if (!grp) { 818 dev_err(info->dev, "unable to find group for node %pOFn\n", 819 np); 820 return -EINVAL; 821 } 822 823 map_num = grp->npins + 1; 824 new_map = devm_kcalloc(pctldev->dev, 825 map_num, sizeof(*new_map), GFP_KERNEL); 826 if (!new_map) 827 return -ENOMEM; 828 829 parent = of_get_parent(np); 830 if (!parent) { 831 devm_kfree(pctldev->dev, new_map); 832 return -EINVAL; 833 } 834 835 *map = new_map; 836 *num_maps = map_num; 837 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP; 838 new_map[0].data.mux.function = parent->name; 839 new_map[0].data.mux.group = np->name; 840 of_node_put(parent); 841 842 /* create config map per pin */ 843 new_map++; 844 for (i = 0; i < grp->npins; i++) { 845 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN; 846 new_map[i].data.configs.group_or_pin = 847 pin_get_name(pctldev, grp->pins[i]); 848 new_map[i].data.configs.configs = &grp->pin_conf[i].config; 849 new_map[i].data.configs.num_configs = 1; 850 } 851 dev_info(pctldev->dev, "maps: function %s group %s num %d\n", 852 (*map)->data.mux.function, grp->name, map_num); 853 854 return 0; 855 } 856 857 static void st_pctl_dt_free_map(struct pinctrl_dev *pctldev, 858 struct pinctrl_map *map, unsigned num_maps) 859 { 860 } 861 862 static const struct pinctrl_ops st_pctlops = { 863 .get_groups_count = st_pctl_get_groups_count, 864 .get_group_pins = st_pctl_get_group_pins, 865 .get_group_name = st_pctl_get_group_name, 866 .dt_node_to_map = st_pctl_dt_node_to_map, 867 .dt_free_map = st_pctl_dt_free_map, 868 }; 869 870 /* Pinmux */ 871 static int st_pmx_get_funcs_count(struct pinctrl_dev *pctldev) 872 { 873 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 874 875 return info->nfunctions; 876 } 877 878 static const char *st_pmx_get_fname(struct pinctrl_dev *pctldev, 879 unsigned selector) 880 { 881 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 882 883 return info->functions[selector].name; 884 } 885 886 static int st_pmx_get_groups(struct pinctrl_dev *pctldev, 887 unsigned selector, const char * const **grps, unsigned * const ngrps) 888 { 889 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 890 *grps = info->functions[selector].groups; 891 *ngrps = info->functions[selector].ngroups; 892 893 return 0; 894 } 895 896 static int st_pmx_set_mux(struct pinctrl_dev *pctldev, unsigned fselector, 897 unsigned group) 898 { 899 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 900 struct st_pinconf *conf = info->groups[group].pin_conf; 901 struct st_pio_control *pc; 902 int i; 903 904 for (i = 0; i < info->groups[group].npins; i++) { 905 pc = st_get_pio_control(pctldev, conf[i].pin); 906 st_pctl_set_function(pc, conf[i].pin, conf[i].altfunc); 907 } 908 909 return 0; 910 } 911 912 static int st_pmx_set_gpio_direction(struct pinctrl_dev *pctldev, 913 struct pinctrl_gpio_range *range, unsigned gpio, 914 bool input) 915 { 916 struct st_gpio_bank *bank = gpio_range_to_bank(range); 917 /* 918 * When a PIO bank is used in its primary function mode (altfunc = 0) 919 * Output Enable (OE), Open Drain(OD), and Pull Up (PU) 920 * for the primary PIO functions are driven by the related PIO block 921 */ 922 st_pctl_set_function(&bank->pc, gpio, 0); 923 st_gpio_direction(bank, gpio, input ? 924 ST_GPIO_DIRECTION_IN : ST_GPIO_DIRECTION_OUT); 925 926 return 0; 927 } 928 929 static const struct pinmux_ops st_pmxops = { 930 .get_functions_count = st_pmx_get_funcs_count, 931 .get_function_name = st_pmx_get_fname, 932 .get_function_groups = st_pmx_get_groups, 933 .set_mux = st_pmx_set_mux, 934 .gpio_set_direction = st_pmx_set_gpio_direction, 935 .strict = true, 936 }; 937 938 /* Pinconf */ 939 static void st_pinconf_get_retime(struct st_pinctrl *info, 940 struct st_pio_control *pc, int pin, unsigned long *config) 941 { 942 if (info->data->rt_style == st_retime_style_packed) 943 st_pinconf_get_retime_packed(info, pc, pin, config); 944 else if (info->data->rt_style == st_retime_style_dedicated) 945 if ((BIT(pin) & pc->rt_pin_mask)) 946 st_pinconf_get_retime_dedicated(info, pc, 947 pin, config); 948 } 949 950 static void st_pinconf_set_retime(struct st_pinctrl *info, 951 struct st_pio_control *pc, int pin, unsigned long config) 952 { 953 if (info->data->rt_style == st_retime_style_packed) 954 st_pinconf_set_retime_packed(info, pc, config, pin); 955 else if (info->data->rt_style == st_retime_style_dedicated) 956 if ((BIT(pin) & pc->rt_pin_mask)) 957 st_pinconf_set_retime_dedicated(info, pc, 958 config, pin); 959 } 960 961 static int st_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin_id, 962 unsigned long *configs, unsigned num_configs) 963 { 964 int pin = st_gpio_pin(pin_id); 965 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 966 struct st_pio_control *pc = st_get_pio_control(pctldev, pin_id); 967 int i; 968 969 for (i = 0; i < num_configs; i++) { 970 st_pinconf_set_config(pc, pin, configs[i]); 971 st_pinconf_set_retime(info, pc, pin, configs[i]); 972 } /* for each config */ 973 974 return 0; 975 } 976 977 static int st_pinconf_get(struct pinctrl_dev *pctldev, 978 unsigned pin_id, unsigned long *config) 979 { 980 int pin = st_gpio_pin(pin_id); 981 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 982 struct st_pio_control *pc = st_get_pio_control(pctldev, pin_id); 983 984 *config = 0; 985 st_pinconf_get_direction(pc, pin, config); 986 st_pinconf_get_retime(info, pc, pin, config); 987 988 return 0; 989 } 990 991 static void st_pinconf_dbg_show(struct pinctrl_dev *pctldev, 992 struct seq_file *s, unsigned pin_id) 993 { 994 struct st_pio_control *pc; 995 unsigned long config; 996 unsigned int function; 997 int offset = st_gpio_pin(pin_id); 998 char f[16]; 999 1000 mutex_unlock(&pctldev->mutex); 1001 pc = st_get_pio_control(pctldev, pin_id); 1002 st_pinconf_get(pctldev, pin_id, &config); 1003 mutex_lock(&pctldev->mutex); 1004 1005 function = st_pctl_get_pin_function(pc, offset); 1006 if (function) 1007 snprintf(f, 10, "Alt Fn %u", function); 1008 else 1009 snprintf(f, 5, "GPIO"); 1010 1011 seq_printf(s, "[OE:%d,PU:%ld,OD:%ld]\t%s\n" 1012 "\t\t[retime:%ld,invclk:%ld,clknotdat:%ld," 1013 "de:%ld,rt-clk:%ld,rt-delay:%ld]", 1014 !st_gpio_get_direction(&pc_to_bank(pc)->gpio_chip, offset), 1015 ST_PINCONF_UNPACK_PU(config), 1016 ST_PINCONF_UNPACK_OD(config), 1017 f, 1018 ST_PINCONF_UNPACK_RT(config), 1019 ST_PINCONF_UNPACK_RT_INVERTCLK(config), 1020 ST_PINCONF_UNPACK_RT_CLKNOTDATA(config), 1021 ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(config), 1022 ST_PINCONF_UNPACK_RT_CLK(config), 1023 ST_PINCONF_UNPACK_RT_DELAY(config)); 1024 } 1025 1026 static const struct pinconf_ops st_confops = { 1027 .pin_config_get = st_pinconf_get, 1028 .pin_config_set = st_pinconf_set, 1029 .pin_config_dbg_show = st_pinconf_dbg_show, 1030 }; 1031 1032 static void st_pctl_dt_child_count(struct st_pinctrl *info, 1033 struct device_node *np) 1034 { 1035 struct device_node *child; 1036 for_each_child_of_node(np, child) { 1037 if (of_property_read_bool(child, "gpio-controller")) { 1038 info->nbanks++; 1039 } else { 1040 info->nfunctions++; 1041 info->ngroups += of_get_child_count(child); 1042 } 1043 } 1044 } 1045 1046 static int st_pctl_dt_setup_retime_packed(struct st_pinctrl *info, 1047 int bank, struct st_pio_control *pc) 1048 { 1049 struct device *dev = info->dev; 1050 struct regmap *rm = info->regmap; 1051 const struct st_pctl_data *data = info->data; 1052 /* 2 registers per bank */ 1053 int reg = (data->rt + bank * RT_P_CFGS_PER_BANK) * 4; 1054 struct st_retime_packed *rt_p = &pc->rt.rt_p; 1055 /* cfg0 */ 1056 struct reg_field clk1notclk0 = RT_P_CFG0_CLK1NOTCLK0_FIELD(reg); 1057 struct reg_field delay_0 = RT_P_CFG0_DELAY_0_FIELD(reg); 1058 struct reg_field delay_1 = RT_P_CFG0_DELAY_1_FIELD(reg); 1059 /* cfg1 */ 1060 struct reg_field invertclk = RT_P_CFG1_INVERTCLK_FIELD(reg + 4); 1061 struct reg_field retime = RT_P_CFG1_RETIME_FIELD(reg + 4); 1062 struct reg_field clknotdata = RT_P_CFG1_CLKNOTDATA_FIELD(reg + 4); 1063 struct reg_field double_edge = RT_P_CFG1_DOUBLE_EDGE_FIELD(reg + 4); 1064 1065 rt_p->clk1notclk0 = devm_regmap_field_alloc(dev, rm, clk1notclk0); 1066 rt_p->delay_0 = devm_regmap_field_alloc(dev, rm, delay_0); 1067 rt_p->delay_1 = devm_regmap_field_alloc(dev, rm, delay_1); 1068 rt_p->invertclk = devm_regmap_field_alloc(dev, rm, invertclk); 1069 rt_p->retime = devm_regmap_field_alloc(dev, rm, retime); 1070 rt_p->clknotdata = devm_regmap_field_alloc(dev, rm, clknotdata); 1071 rt_p->double_edge = devm_regmap_field_alloc(dev, rm, double_edge); 1072 1073 if (IS_ERR(rt_p->clk1notclk0) || IS_ERR(rt_p->delay_0) || 1074 IS_ERR(rt_p->delay_1) || IS_ERR(rt_p->invertclk) || 1075 IS_ERR(rt_p->retime) || IS_ERR(rt_p->clknotdata) || 1076 IS_ERR(rt_p->double_edge)) 1077 return -EINVAL; 1078 1079 return 0; 1080 } 1081 1082 static int st_pctl_dt_setup_retime_dedicated(struct st_pinctrl *info, 1083 int bank, struct st_pio_control *pc) 1084 { 1085 struct device *dev = info->dev; 1086 struct regmap *rm = info->regmap; 1087 const struct st_pctl_data *data = info->data; 1088 /* 8 registers per bank */ 1089 int reg_offset = (data->rt + bank * RT_D_CFGS_PER_BANK) * 4; 1090 struct st_retime_dedicated *rt_d = &pc->rt.rt_d; 1091 unsigned int j; 1092 u32 pin_mask = pc->rt_pin_mask; 1093 1094 for (j = 0; j < RT_D_CFGS_PER_BANK; j++) { 1095 if (BIT(j) & pin_mask) { 1096 struct reg_field reg = REG_FIELD(reg_offset, 0, 31); 1097 rt_d->rt[j] = devm_regmap_field_alloc(dev, rm, reg); 1098 if (IS_ERR(rt_d->rt[j])) 1099 return -EINVAL; 1100 reg_offset += 4; 1101 } 1102 } 1103 return 0; 1104 } 1105 1106 static int st_pctl_dt_setup_retime(struct st_pinctrl *info, 1107 int bank, struct st_pio_control *pc) 1108 { 1109 const struct st_pctl_data *data = info->data; 1110 if (data->rt_style == st_retime_style_packed) 1111 return st_pctl_dt_setup_retime_packed(info, bank, pc); 1112 else if (data->rt_style == st_retime_style_dedicated) 1113 return st_pctl_dt_setup_retime_dedicated(info, bank, pc); 1114 1115 return -EINVAL; 1116 } 1117 1118 1119 static struct regmap_field *st_pc_get_value(struct device *dev, 1120 struct regmap *regmap, int bank, 1121 int data, int lsb, int msb) 1122 { 1123 struct reg_field reg = REG_FIELD((data + bank) * 4, lsb, msb); 1124 1125 if (data < 0) 1126 return NULL; 1127 1128 return devm_regmap_field_alloc(dev, regmap, reg); 1129 } 1130 1131 static void st_parse_syscfgs(struct st_pinctrl *info, int bank, 1132 struct device_node *np) 1133 { 1134 const struct st_pctl_data *data = info->data; 1135 /** 1136 * For a given shared register like OE/PU/OD, there are 8 bits per bank 1137 * 0:7 belongs to bank0, 8:15 belongs to bank1 ... 1138 * So each register is shared across 4 banks. 1139 */ 1140 int lsb = (bank%4) * ST_GPIO_PINS_PER_BANK; 1141 int msb = lsb + ST_GPIO_PINS_PER_BANK - 1; 1142 struct st_pio_control *pc = &info->banks[bank].pc; 1143 struct device *dev = info->dev; 1144 struct regmap *regmap = info->regmap; 1145 1146 pc->alt = st_pc_get_value(dev, regmap, bank, data->alt, 0, 31); 1147 pc->oe = st_pc_get_value(dev, regmap, bank/4, data->oe, lsb, msb); 1148 pc->pu = st_pc_get_value(dev, regmap, bank/4, data->pu, lsb, msb); 1149 pc->od = st_pc_get_value(dev, regmap, bank/4, data->od, lsb, msb); 1150 1151 /* retime avaiable for all pins by default */ 1152 pc->rt_pin_mask = 0xff; 1153 of_property_read_u32(np, "st,retime-pin-mask", &pc->rt_pin_mask); 1154 st_pctl_dt_setup_retime(info, bank, pc); 1155 1156 return; 1157 } 1158 1159 /* 1160 * Each pin is represented in of the below forms. 1161 * <bank offset mux direction rt_type rt_delay rt_clk> 1162 */ 1163 static int st_pctl_dt_parse_groups(struct device_node *np, 1164 struct st_pctl_group *grp, struct st_pinctrl *info, int idx) 1165 { 1166 /* bank pad direction val altfunction */ 1167 const __be32 *list; 1168 struct property *pp; 1169 struct st_pinconf *conf; 1170 struct device_node *pins; 1171 int i = 0, npins = 0, nr_props, ret = 0; 1172 1173 pins = of_get_child_by_name(np, "st,pins"); 1174 if (!pins) 1175 return -ENODATA; 1176 1177 for_each_property_of_node(pins, pp) { 1178 /* Skip those we do not want to proceed */ 1179 if (!strcmp(pp->name, "name")) 1180 continue; 1181 1182 if (pp->length / sizeof(__be32) >= OF_GPIO_ARGS_MIN) { 1183 npins++; 1184 } else { 1185 pr_warn("Invalid st,pins in %pOFn node\n", np); 1186 ret = -EINVAL; 1187 goto out_put_node; 1188 } 1189 } 1190 1191 grp->npins = npins; 1192 grp->name = np->name; 1193 grp->pins = devm_kcalloc(info->dev, npins, sizeof(u32), GFP_KERNEL); 1194 grp->pin_conf = devm_kcalloc(info->dev, 1195 npins, sizeof(*conf), GFP_KERNEL); 1196 1197 if (!grp->pins || !grp->pin_conf) { 1198 ret = -ENOMEM; 1199 goto out_put_node; 1200 } 1201 1202 /* <bank offset mux direction rt_type rt_delay rt_clk> */ 1203 for_each_property_of_node(pins, pp) { 1204 if (!strcmp(pp->name, "name")) 1205 continue; 1206 nr_props = pp->length/sizeof(u32); 1207 list = pp->value; 1208 conf = &grp->pin_conf[i]; 1209 1210 /* bank & offset */ 1211 be32_to_cpup(list++); 1212 be32_to_cpup(list++); 1213 conf->pin = of_get_named_gpio(pins, pp->name, 0); 1214 conf->name = pp->name; 1215 grp->pins[i] = conf->pin; 1216 /* mux */ 1217 conf->altfunc = be32_to_cpup(list++); 1218 conf->config = 0; 1219 /* direction */ 1220 conf->config |= be32_to_cpup(list++); 1221 /* rt_type rt_delay rt_clk */ 1222 if (nr_props >= OF_GPIO_ARGS_MIN + OF_RT_ARGS_MIN) { 1223 /* rt_type */ 1224 conf->config |= be32_to_cpup(list++); 1225 /* rt_delay */ 1226 conf->config |= be32_to_cpup(list++); 1227 /* rt_clk */ 1228 if (nr_props > OF_GPIO_ARGS_MIN + OF_RT_ARGS_MIN) 1229 conf->config |= be32_to_cpup(list++); 1230 } 1231 i++; 1232 } 1233 1234 out_put_node: 1235 of_node_put(pins); 1236 1237 return ret; 1238 } 1239 1240 static int st_pctl_parse_functions(struct device_node *np, 1241 struct st_pinctrl *info, u32 index, int *grp_index) 1242 { 1243 struct device_node *child; 1244 struct st_pmx_func *func; 1245 struct st_pctl_group *grp; 1246 int ret, i; 1247 1248 func = &info->functions[index]; 1249 func->name = np->name; 1250 func->ngroups = of_get_child_count(np); 1251 if (func->ngroups == 0) { 1252 dev_err(info->dev, "No groups defined\n"); 1253 return -EINVAL; 1254 } 1255 func->groups = devm_kcalloc(info->dev, 1256 func->ngroups, sizeof(char *), GFP_KERNEL); 1257 if (!func->groups) 1258 return -ENOMEM; 1259 1260 i = 0; 1261 for_each_child_of_node(np, child) { 1262 func->groups[i] = child->name; 1263 grp = &info->groups[*grp_index]; 1264 *grp_index += 1; 1265 ret = st_pctl_dt_parse_groups(child, grp, info, i++); 1266 if (ret) { 1267 of_node_put(child); 1268 return ret; 1269 } 1270 } 1271 dev_info(info->dev, "Function[%d\t name:%s,\tgroups:%d]\n", 1272 index, func->name, func->ngroups); 1273 1274 return 0; 1275 } 1276 1277 static void st_gpio_irq_mask(struct irq_data *d) 1278 { 1279 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1280 struct st_gpio_bank *bank = gpiochip_get_data(gc); 1281 1282 writel(BIT(d->hwirq), bank->base + REG_PIO_CLR_PMASK); 1283 } 1284 1285 static void st_gpio_irq_unmask(struct irq_data *d) 1286 { 1287 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1288 struct st_gpio_bank *bank = gpiochip_get_data(gc); 1289 1290 writel(BIT(d->hwirq), bank->base + REG_PIO_SET_PMASK); 1291 } 1292 1293 static int st_gpio_irq_request_resources(struct irq_data *d) 1294 { 1295 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1296 1297 st_gpio_direction_input(gc, d->hwirq); 1298 1299 return gpiochip_lock_as_irq(gc, d->hwirq); 1300 } 1301 1302 static void st_gpio_irq_release_resources(struct irq_data *d) 1303 { 1304 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1305 1306 gpiochip_unlock_as_irq(gc, d->hwirq); 1307 } 1308 1309 static int st_gpio_irq_set_type(struct irq_data *d, unsigned type) 1310 { 1311 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1312 struct st_gpio_bank *bank = gpiochip_get_data(gc); 1313 unsigned long flags; 1314 int comp, pin = d->hwirq; 1315 u32 val; 1316 u32 pin_edge_conf = 0; 1317 1318 switch (type) { 1319 case IRQ_TYPE_LEVEL_HIGH: 1320 comp = 0; 1321 break; 1322 case IRQ_TYPE_EDGE_FALLING: 1323 comp = 0; 1324 pin_edge_conf = ST_IRQ_FALLING_EDGE_CONF(pin); 1325 break; 1326 case IRQ_TYPE_LEVEL_LOW: 1327 comp = 1; 1328 break; 1329 case IRQ_TYPE_EDGE_RISING: 1330 comp = 1; 1331 pin_edge_conf = ST_IRQ_RISING_EDGE_CONF(pin); 1332 break; 1333 case IRQ_TYPE_EDGE_BOTH: 1334 comp = st_gpio_get(&bank->gpio_chip, pin); 1335 pin_edge_conf = ST_IRQ_BOTH_EDGE_CONF(pin); 1336 break; 1337 default: 1338 return -EINVAL; 1339 } 1340 1341 spin_lock_irqsave(&bank->lock, flags); 1342 bank->irq_edge_conf &= ~(ST_IRQ_EDGE_MASK << ( 1343 pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN)); 1344 bank->irq_edge_conf |= pin_edge_conf; 1345 spin_unlock_irqrestore(&bank->lock, flags); 1346 1347 val = readl(bank->base + REG_PIO_PCOMP); 1348 val &= ~BIT(pin); 1349 val |= (comp << pin); 1350 writel(val, bank->base + REG_PIO_PCOMP); 1351 1352 return 0; 1353 } 1354 1355 /* 1356 * As edge triggers are not supported at hardware level, it is supported by 1357 * software by exploiting the level trigger support in hardware. 1358 * 1359 * Steps for detection raising edge interrupt in software. 1360 * 1361 * Step 1: CONFIGURE pin to detect level LOW interrupts. 1362 * 1363 * Step 2: DETECT level LOW interrupt and in irqmux/gpio bank interrupt handler, 1364 * if the value of pin is low, then CONFIGURE pin for level HIGH interrupt. 1365 * IGNORE calling the actual interrupt handler for the pin at this stage. 1366 * 1367 * Step 3: DETECT level HIGH interrupt and in irqmux/gpio-bank interrupt handler 1368 * if the value of pin is HIGH, CONFIGURE pin for level LOW interrupt and then 1369 * DISPATCH the interrupt to the interrupt handler of the pin. 1370 * 1371 * step-1 ________ __________ 1372 * | | step - 3 1373 * | | 1374 * step -2 |_____| 1375 * 1376 * falling edge is also detected int the same way. 1377 * 1378 */ 1379 static void __gpio_irq_handler(struct st_gpio_bank *bank) 1380 { 1381 unsigned long port_in, port_mask, port_comp, active_irqs; 1382 unsigned long bank_edge_mask, flags; 1383 int n, val, ecfg; 1384 1385 spin_lock_irqsave(&bank->lock, flags); 1386 bank_edge_mask = bank->irq_edge_conf; 1387 spin_unlock_irqrestore(&bank->lock, flags); 1388 1389 for (;;) { 1390 port_in = readl(bank->base + REG_PIO_PIN); 1391 port_comp = readl(bank->base + REG_PIO_PCOMP); 1392 port_mask = readl(bank->base + REG_PIO_PMASK); 1393 1394 active_irqs = (port_in ^ port_comp) & port_mask; 1395 1396 if (active_irqs == 0) 1397 break; 1398 1399 for_each_set_bit(n, &active_irqs, BITS_PER_LONG) { 1400 /* check if we are detecting fake edges ... */ 1401 ecfg = ST_IRQ_EDGE_CONF(bank_edge_mask, n); 1402 1403 if (ecfg) { 1404 /* edge detection. */ 1405 val = st_gpio_get(&bank->gpio_chip, n); 1406 1407 writel(BIT(n), 1408 val ? bank->base + REG_PIO_SET_PCOMP : 1409 bank->base + REG_PIO_CLR_PCOMP); 1410 1411 if (ecfg != ST_IRQ_EDGE_BOTH && 1412 !((ecfg & ST_IRQ_EDGE_FALLING) ^ val)) 1413 continue; 1414 } 1415 1416 generic_handle_irq(irq_find_mapping(bank->gpio_chip.irq.domain, n)); 1417 } 1418 } 1419 } 1420 1421 static void st_gpio_irq_handler(struct irq_desc *desc) 1422 { 1423 /* interrupt dedicated per bank */ 1424 struct irq_chip *chip = irq_desc_get_chip(desc); 1425 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 1426 struct st_gpio_bank *bank = gpiochip_get_data(gc); 1427 1428 chained_irq_enter(chip, desc); 1429 __gpio_irq_handler(bank); 1430 chained_irq_exit(chip, desc); 1431 } 1432 1433 static void st_gpio_irqmux_handler(struct irq_desc *desc) 1434 { 1435 struct irq_chip *chip = irq_desc_get_chip(desc); 1436 struct st_pinctrl *info = irq_desc_get_handler_data(desc); 1437 unsigned long status; 1438 int n; 1439 1440 chained_irq_enter(chip, desc); 1441 1442 status = readl(info->irqmux_base); 1443 1444 for_each_set_bit(n, &status, info->nbanks) 1445 __gpio_irq_handler(&info->banks[n]); 1446 1447 chained_irq_exit(chip, desc); 1448 } 1449 1450 static const struct gpio_chip st_gpio_template = { 1451 .request = gpiochip_generic_request, 1452 .free = gpiochip_generic_free, 1453 .get = st_gpio_get, 1454 .set = st_gpio_set, 1455 .direction_input = st_gpio_direction_input, 1456 .direction_output = st_gpio_direction_output, 1457 .get_direction = st_gpio_get_direction, 1458 .ngpio = ST_GPIO_PINS_PER_BANK, 1459 }; 1460 1461 static struct irq_chip st_gpio_irqchip = { 1462 .name = "GPIO", 1463 .irq_request_resources = st_gpio_irq_request_resources, 1464 .irq_release_resources = st_gpio_irq_release_resources, 1465 .irq_disable = st_gpio_irq_mask, 1466 .irq_mask = st_gpio_irq_mask, 1467 .irq_unmask = st_gpio_irq_unmask, 1468 .irq_set_type = st_gpio_irq_set_type, 1469 .flags = IRQCHIP_SKIP_SET_WAKE, 1470 }; 1471 1472 static int st_gpiolib_register_bank(struct st_pinctrl *info, 1473 int bank_nr, struct device_node *np) 1474 { 1475 struct st_gpio_bank *bank = &info->banks[bank_nr]; 1476 struct pinctrl_gpio_range *range = &bank->range; 1477 struct device *dev = info->dev; 1478 int bank_num = of_alias_get_id(np, "gpio"); 1479 struct resource res, irq_res; 1480 int gpio_irq = 0, err; 1481 1482 if (of_address_to_resource(np, 0, &res)) 1483 return -ENODEV; 1484 1485 bank->base = devm_ioremap_resource(dev, &res); 1486 if (IS_ERR(bank->base)) 1487 return PTR_ERR(bank->base); 1488 1489 bank->gpio_chip = st_gpio_template; 1490 bank->gpio_chip.base = bank_num * ST_GPIO_PINS_PER_BANK; 1491 bank->gpio_chip.ngpio = ST_GPIO_PINS_PER_BANK; 1492 bank->gpio_chip.of_node = np; 1493 bank->gpio_chip.parent = dev; 1494 spin_lock_init(&bank->lock); 1495 1496 of_property_read_string(np, "st,bank-name", &range->name); 1497 bank->gpio_chip.label = range->name; 1498 1499 range->id = bank_num; 1500 range->pin_base = range->base = range->id * ST_GPIO_PINS_PER_BANK; 1501 range->npins = bank->gpio_chip.ngpio; 1502 range->gc = &bank->gpio_chip; 1503 err = gpiochip_add_data(&bank->gpio_chip, bank); 1504 if (err) { 1505 dev_err(dev, "Failed to add gpiochip(%d)!\n", bank_num); 1506 return err; 1507 } 1508 dev_info(dev, "%s bank added.\n", range->name); 1509 1510 /** 1511 * GPIO bank can have one of the two possible types of 1512 * interrupt-wirings. 1513 * 1514 * First type is via irqmux, single interrupt is used by multiple 1515 * gpio banks. This reduces number of overall interrupts numbers 1516 * required. All these banks belong to a single pincontroller. 1517 * _________ 1518 * | |----> [gpio-bank (n) ] 1519 * | |----> [gpio-bank (n + 1)] 1520 * [irqN]-- | irq-mux |----> [gpio-bank (n + 2)] 1521 * | |----> [gpio-bank (... )] 1522 * |_________|----> [gpio-bank (n + 7)] 1523 * 1524 * Second type has a dedicated interrupt per each gpio bank. 1525 * 1526 * [irqN]----> [gpio-bank (n)] 1527 */ 1528 1529 if (of_irq_to_resource(np, 0, &irq_res) > 0) { 1530 gpio_irq = irq_res.start; 1531 gpiochip_set_chained_irqchip(&bank->gpio_chip, &st_gpio_irqchip, 1532 gpio_irq, st_gpio_irq_handler); 1533 } 1534 1535 if (info->irqmux_base || gpio_irq > 0) { 1536 err = gpiochip_irqchip_add(&bank->gpio_chip, &st_gpio_irqchip, 1537 0, handle_simple_irq, 1538 IRQ_TYPE_NONE); 1539 if (err) { 1540 gpiochip_remove(&bank->gpio_chip); 1541 dev_info(dev, "could not add irqchip\n"); 1542 return err; 1543 } 1544 } else { 1545 dev_info(dev, "No IRQ support for %pOF bank\n", np); 1546 } 1547 1548 return 0; 1549 } 1550 1551 static const struct of_device_id st_pctl_of_match[] = { 1552 { .compatible = "st,stih407-sbc-pinctrl", .data = &stih407_data}, 1553 { .compatible = "st,stih407-front-pinctrl", .data = &stih407_data}, 1554 { .compatible = "st,stih407-rear-pinctrl", .data = &stih407_data}, 1555 { .compatible = "st,stih407-flash-pinctrl", .data = &stih407_flashdata}, 1556 { /* sentinel */ } 1557 }; 1558 1559 static int st_pctl_probe_dt(struct platform_device *pdev, 1560 struct pinctrl_desc *pctl_desc, struct st_pinctrl *info) 1561 { 1562 int ret = 0; 1563 int i = 0, j = 0, k = 0, bank; 1564 struct pinctrl_pin_desc *pdesc; 1565 struct device_node *np = pdev->dev.of_node; 1566 struct device_node *child; 1567 int grp_index = 0; 1568 int irq = 0; 1569 struct resource *res; 1570 1571 st_pctl_dt_child_count(info, np); 1572 if (!info->nbanks) { 1573 dev_err(&pdev->dev, "you need atleast one gpio bank\n"); 1574 return -EINVAL; 1575 } 1576 1577 dev_info(&pdev->dev, "nbanks = %d\n", info->nbanks); 1578 dev_info(&pdev->dev, "nfunctions = %d\n", info->nfunctions); 1579 dev_info(&pdev->dev, "ngroups = %d\n", info->ngroups); 1580 1581 info->functions = devm_kcalloc(&pdev->dev, 1582 info->nfunctions, sizeof(*info->functions), GFP_KERNEL); 1583 1584 info->groups = devm_kcalloc(&pdev->dev, 1585 info->ngroups, sizeof(*info->groups), 1586 GFP_KERNEL); 1587 1588 info->banks = devm_kcalloc(&pdev->dev, 1589 info->nbanks, sizeof(*info->banks), GFP_KERNEL); 1590 1591 if (!info->functions || !info->groups || !info->banks) 1592 return -ENOMEM; 1593 1594 info->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg"); 1595 if (IS_ERR(info->regmap)) { 1596 dev_err(info->dev, "No syscfg phandle specified\n"); 1597 return PTR_ERR(info->regmap); 1598 } 1599 info->data = of_match_node(st_pctl_of_match, np)->data; 1600 1601 irq = platform_get_irq(pdev, 0); 1602 1603 if (irq > 0) { 1604 res = platform_get_resource_byname(pdev, 1605 IORESOURCE_MEM, "irqmux"); 1606 info->irqmux_base = devm_ioremap_resource(&pdev->dev, res); 1607 1608 if (IS_ERR(info->irqmux_base)) 1609 return PTR_ERR(info->irqmux_base); 1610 1611 irq_set_chained_handler_and_data(irq, st_gpio_irqmux_handler, 1612 info); 1613 1614 } 1615 1616 pctl_desc->npins = info->nbanks * ST_GPIO_PINS_PER_BANK; 1617 pdesc = devm_kcalloc(&pdev->dev, 1618 pctl_desc->npins, sizeof(*pdesc), GFP_KERNEL); 1619 if (!pdesc) 1620 return -ENOMEM; 1621 1622 pctl_desc->pins = pdesc; 1623 1624 bank = 0; 1625 for_each_child_of_node(np, child) { 1626 if (of_property_read_bool(child, "gpio-controller")) { 1627 const char *bank_name = NULL; 1628 ret = st_gpiolib_register_bank(info, bank, child); 1629 if (ret) { 1630 of_node_put(child); 1631 return ret; 1632 } 1633 1634 k = info->banks[bank].range.pin_base; 1635 bank_name = info->banks[bank].range.name; 1636 for (j = 0; j < ST_GPIO_PINS_PER_BANK; j++, k++) { 1637 pdesc->number = k; 1638 pdesc->name = kasprintf(GFP_KERNEL, "%s[%d]", 1639 bank_name, j); 1640 pdesc++; 1641 } 1642 st_parse_syscfgs(info, bank, child); 1643 bank++; 1644 } else { 1645 ret = st_pctl_parse_functions(child, info, 1646 i++, &grp_index); 1647 if (ret) { 1648 dev_err(&pdev->dev, "No functions found.\n"); 1649 of_node_put(child); 1650 return ret; 1651 } 1652 } 1653 } 1654 1655 return 0; 1656 } 1657 1658 static int st_pctl_probe(struct platform_device *pdev) 1659 { 1660 struct st_pinctrl *info; 1661 struct pinctrl_desc *pctl_desc; 1662 int ret, i; 1663 1664 if (!pdev->dev.of_node) { 1665 dev_err(&pdev->dev, "device node not found.\n"); 1666 return -EINVAL; 1667 } 1668 1669 pctl_desc = devm_kzalloc(&pdev->dev, sizeof(*pctl_desc), GFP_KERNEL); 1670 if (!pctl_desc) 1671 return -ENOMEM; 1672 1673 info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL); 1674 if (!info) 1675 return -ENOMEM; 1676 1677 info->dev = &pdev->dev; 1678 platform_set_drvdata(pdev, info); 1679 ret = st_pctl_probe_dt(pdev, pctl_desc, info); 1680 if (ret) 1681 return ret; 1682 1683 pctl_desc->owner = THIS_MODULE; 1684 pctl_desc->pctlops = &st_pctlops; 1685 pctl_desc->pmxops = &st_pmxops; 1686 pctl_desc->confops = &st_confops; 1687 pctl_desc->name = dev_name(&pdev->dev); 1688 1689 info->pctl = devm_pinctrl_register(&pdev->dev, pctl_desc, info); 1690 if (IS_ERR(info->pctl)) { 1691 dev_err(&pdev->dev, "Failed pinctrl registration\n"); 1692 return PTR_ERR(info->pctl); 1693 } 1694 1695 for (i = 0; i < info->nbanks; i++) 1696 pinctrl_add_gpio_range(info->pctl, &info->banks[i].range); 1697 1698 return 0; 1699 } 1700 1701 static struct platform_driver st_pctl_driver = { 1702 .driver = { 1703 .name = "st-pinctrl", 1704 .of_match_table = st_pctl_of_match, 1705 }, 1706 .probe = st_pctl_probe, 1707 }; 1708 1709 static int __init st_pctl_init(void) 1710 { 1711 return platform_driver_register(&st_pctl_driver); 1712 } 1713 arch_initcall(st_pctl_init); 1714