1 /* 2 * Copyright (C) 2013 STMicroelectronics (R&D) Limited. 3 * Authors: 4 * Srinivas Kandagatla <srinivas.kandagatla@st.com> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #include <linux/init.h> 12 #include <linux/module.h> 13 #include <linux/slab.h> 14 #include <linux/err.h> 15 #include <linux/io.h> 16 #include <linux/of.h> 17 #include <linux/of_irq.h> 18 #include <linux/of_gpio.h> 19 #include <linux/of_address.h> 20 #include <linux/regmap.h> 21 #include <linux/mfd/syscon.h> 22 #include <linux/pinctrl/pinctrl.h> 23 #include <linux/pinctrl/pinmux.h> 24 #include <linux/pinctrl/pinconf.h> 25 #include <linux/platform_device.h> 26 #include "core.h" 27 28 /* PIO Block registers */ 29 /* PIO output */ 30 #define REG_PIO_POUT 0x00 31 /* Set bits of POUT */ 32 #define REG_PIO_SET_POUT 0x04 33 /* Clear bits of POUT */ 34 #define REG_PIO_CLR_POUT 0x08 35 /* PIO input */ 36 #define REG_PIO_PIN 0x10 37 /* PIO configuration */ 38 #define REG_PIO_PC(n) (0x20 + (n) * 0x10) 39 /* Set bits of PC[2:0] */ 40 #define REG_PIO_SET_PC(n) (0x24 + (n) * 0x10) 41 /* Clear bits of PC[2:0] */ 42 #define REG_PIO_CLR_PC(n) (0x28 + (n) * 0x10) 43 /* PIO input comparison */ 44 #define REG_PIO_PCOMP 0x50 45 /* Set bits of PCOMP */ 46 #define REG_PIO_SET_PCOMP 0x54 47 /* Clear bits of PCOMP */ 48 #define REG_PIO_CLR_PCOMP 0x58 49 /* PIO input comparison mask */ 50 #define REG_PIO_PMASK 0x60 51 /* Set bits of PMASK */ 52 #define REG_PIO_SET_PMASK 0x64 53 /* Clear bits of PMASK */ 54 #define REG_PIO_CLR_PMASK 0x68 55 56 #define ST_GPIO_DIRECTION_BIDIR 0x1 57 #define ST_GPIO_DIRECTION_OUT 0x2 58 #define ST_GPIO_DIRECTION_IN 0x4 59 60 /** 61 * Packed style retime configuration. 62 * There are two registers cfg0 and cfg1 in this style for each bank. 63 * Each field in this register is 8 bit corresponding to 8 pins in the bank. 64 */ 65 #define RT_P_CFGS_PER_BANK 2 66 #define RT_P_CFG0_CLK1NOTCLK0_FIELD(reg) REG_FIELD(reg, 0, 7) 67 #define RT_P_CFG0_DELAY_0_FIELD(reg) REG_FIELD(reg, 16, 23) 68 #define RT_P_CFG0_DELAY_1_FIELD(reg) REG_FIELD(reg, 24, 31) 69 #define RT_P_CFG1_INVERTCLK_FIELD(reg) REG_FIELD(reg, 0, 7) 70 #define RT_P_CFG1_RETIME_FIELD(reg) REG_FIELD(reg, 8, 15) 71 #define RT_P_CFG1_CLKNOTDATA_FIELD(reg) REG_FIELD(reg, 16, 23) 72 #define RT_P_CFG1_DOUBLE_EDGE_FIELD(reg) REG_FIELD(reg, 24, 31) 73 74 /** 75 * Dedicated style retime Configuration register 76 * each register is dedicated per pin. 77 */ 78 #define RT_D_CFGS_PER_BANK 8 79 #define RT_D_CFG_CLK_SHIFT 0 80 #define RT_D_CFG_CLK_MASK (0x3 << 0) 81 #define RT_D_CFG_CLKNOTDATA_SHIFT 2 82 #define RT_D_CFG_CLKNOTDATA_MASK BIT(2) 83 #define RT_D_CFG_DELAY_SHIFT 3 84 #define RT_D_CFG_DELAY_MASK (0xf << 3) 85 #define RT_D_CFG_DELAY_INNOTOUT_SHIFT 7 86 #define RT_D_CFG_DELAY_INNOTOUT_MASK BIT(7) 87 #define RT_D_CFG_DOUBLE_EDGE_SHIFT 8 88 #define RT_D_CFG_DOUBLE_EDGE_MASK BIT(8) 89 #define RT_D_CFG_INVERTCLK_SHIFT 9 90 #define RT_D_CFG_INVERTCLK_MASK BIT(9) 91 #define RT_D_CFG_RETIME_SHIFT 10 92 #define RT_D_CFG_RETIME_MASK BIT(10) 93 94 /* 95 * Pinconf is represented in an opaque unsigned long variable. 96 * Below is the bit allocation details for each possible configuration. 97 * All the bit fields can be encapsulated into four variables 98 * (direction, retime-type, retime-clk, retime-delay) 99 * 100 * +----------------+ 101 *[31:28]| reserved-3 | 102 * +----------------+------------- 103 *[27] | oe | | 104 * +----------------+ v 105 *[26] | pu | [Direction ] 106 * +----------------+ ^ 107 *[25] | od | | 108 * +----------------+------------- 109 *[24] | reserved-2 | 110 * +----------------+------------- 111 *[23] | retime | | 112 * +----------------+ | 113 *[22] | retime-invclk | | 114 * +----------------+ v 115 *[21] |retime-clknotdat| [Retime-type ] 116 * +----------------+ ^ 117 *[20] | retime-de | | 118 * +----------------+------------- 119 *[19:18]| retime-clk |------>[Retime-Clk ] 120 * +----------------+ 121 *[17:16]| reserved-1 | 122 * +----------------+ 123 *[15..0]| retime-delay |------>[Retime Delay] 124 * +----------------+ 125 */ 126 127 #define ST_PINCONF_UNPACK(conf, param)\ 128 ((conf >> ST_PINCONF_ ##param ##_SHIFT) \ 129 & ST_PINCONF_ ##param ##_MASK) 130 131 #define ST_PINCONF_PACK(conf, val, param) (conf |=\ 132 ((val & ST_PINCONF_ ##param ##_MASK) << \ 133 ST_PINCONF_ ##param ##_SHIFT)) 134 135 /* Output enable */ 136 #define ST_PINCONF_OE_MASK 0x1 137 #define ST_PINCONF_OE_SHIFT 27 138 #define ST_PINCONF_OE BIT(27) 139 #define ST_PINCONF_UNPACK_OE(conf) ST_PINCONF_UNPACK(conf, OE) 140 #define ST_PINCONF_PACK_OE(conf) ST_PINCONF_PACK(conf, 1, OE) 141 142 /* Pull Up */ 143 #define ST_PINCONF_PU_MASK 0x1 144 #define ST_PINCONF_PU_SHIFT 26 145 #define ST_PINCONF_PU BIT(26) 146 #define ST_PINCONF_UNPACK_PU(conf) ST_PINCONF_UNPACK(conf, PU) 147 #define ST_PINCONF_PACK_PU(conf) ST_PINCONF_PACK(conf, 1, PU) 148 149 /* Open Drain */ 150 #define ST_PINCONF_OD_MASK 0x1 151 #define ST_PINCONF_OD_SHIFT 25 152 #define ST_PINCONF_OD BIT(25) 153 #define ST_PINCONF_UNPACK_OD(conf) ST_PINCONF_UNPACK(conf, OD) 154 #define ST_PINCONF_PACK_OD(conf) ST_PINCONF_PACK(conf, 1, OD) 155 156 #define ST_PINCONF_RT_MASK 0x1 157 #define ST_PINCONF_RT_SHIFT 23 158 #define ST_PINCONF_RT BIT(23) 159 #define ST_PINCONF_UNPACK_RT(conf) ST_PINCONF_UNPACK(conf, RT) 160 #define ST_PINCONF_PACK_RT(conf) ST_PINCONF_PACK(conf, 1, RT) 161 162 #define ST_PINCONF_RT_INVERTCLK_MASK 0x1 163 #define ST_PINCONF_RT_INVERTCLK_SHIFT 22 164 #define ST_PINCONF_RT_INVERTCLK BIT(22) 165 #define ST_PINCONF_UNPACK_RT_INVERTCLK(conf) \ 166 ST_PINCONF_UNPACK(conf, RT_INVERTCLK) 167 #define ST_PINCONF_PACK_RT_INVERTCLK(conf) \ 168 ST_PINCONF_PACK(conf, 1, RT_INVERTCLK) 169 170 #define ST_PINCONF_RT_CLKNOTDATA_MASK 0x1 171 #define ST_PINCONF_RT_CLKNOTDATA_SHIFT 21 172 #define ST_PINCONF_RT_CLKNOTDATA BIT(21) 173 #define ST_PINCONF_UNPACK_RT_CLKNOTDATA(conf) \ 174 ST_PINCONF_UNPACK(conf, RT_CLKNOTDATA) 175 #define ST_PINCONF_PACK_RT_CLKNOTDATA(conf) \ 176 ST_PINCONF_PACK(conf, 1, RT_CLKNOTDATA) 177 178 #define ST_PINCONF_RT_DOUBLE_EDGE_MASK 0x1 179 #define ST_PINCONF_RT_DOUBLE_EDGE_SHIFT 20 180 #define ST_PINCONF_RT_DOUBLE_EDGE BIT(20) 181 #define ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(conf) \ 182 ST_PINCONF_UNPACK(conf, RT_DOUBLE_EDGE) 183 #define ST_PINCONF_PACK_RT_DOUBLE_EDGE(conf) \ 184 ST_PINCONF_PACK(conf, 1, RT_DOUBLE_EDGE) 185 186 #define ST_PINCONF_RT_CLK_MASK 0x3 187 #define ST_PINCONF_RT_CLK_SHIFT 18 188 #define ST_PINCONF_RT_CLK BIT(18) 189 #define ST_PINCONF_UNPACK_RT_CLK(conf) ST_PINCONF_UNPACK(conf, RT_CLK) 190 #define ST_PINCONF_PACK_RT_CLK(conf, val) ST_PINCONF_PACK(conf, val, RT_CLK) 191 192 /* RETIME_DELAY in Pico Secs */ 193 #define ST_PINCONF_RT_DELAY_MASK 0xffff 194 #define ST_PINCONF_RT_DELAY_SHIFT 0 195 #define ST_PINCONF_UNPACK_RT_DELAY(conf) ST_PINCONF_UNPACK(conf, RT_DELAY) 196 #define ST_PINCONF_PACK_RT_DELAY(conf, val) \ 197 ST_PINCONF_PACK(conf, val, RT_DELAY) 198 199 #define ST_GPIO_PINS_PER_BANK (8) 200 #define OF_GPIO_ARGS_MIN (4) 201 #define OF_RT_ARGS_MIN (2) 202 203 #define gpio_range_to_bank(chip) \ 204 container_of(chip, struct st_gpio_bank, range) 205 206 #define gpio_chip_to_bank(chip) \ 207 container_of(chip, struct st_gpio_bank, gpio_chip) 208 209 #define pc_to_bank(pc) \ 210 container_of(pc, struct st_gpio_bank, pc) 211 212 enum st_retime_style { 213 st_retime_style_none, 214 st_retime_style_packed, 215 st_retime_style_dedicated, 216 }; 217 218 struct st_retime_dedicated { 219 struct regmap_field *rt[ST_GPIO_PINS_PER_BANK]; 220 }; 221 222 struct st_retime_packed { 223 struct regmap_field *clk1notclk0; 224 struct regmap_field *delay_0; 225 struct regmap_field *delay_1; 226 struct regmap_field *invertclk; 227 struct regmap_field *retime; 228 struct regmap_field *clknotdata; 229 struct regmap_field *double_edge; 230 }; 231 232 struct st_pio_control { 233 u32 rt_pin_mask; 234 struct regmap_field *alt, *oe, *pu, *od; 235 /* retiming */ 236 union { 237 struct st_retime_packed rt_p; 238 struct st_retime_dedicated rt_d; 239 } rt; 240 }; 241 242 struct st_pctl_data { 243 const enum st_retime_style rt_style; 244 const unsigned int *input_delays; 245 const int ninput_delays; 246 const unsigned int *output_delays; 247 const int noutput_delays; 248 /* register offset information */ 249 const int alt, oe, pu, od, rt; 250 }; 251 252 struct st_pinconf { 253 int pin; 254 const char *name; 255 unsigned long config; 256 int altfunc; 257 }; 258 259 struct st_pmx_func { 260 const char *name; 261 const char **groups; 262 unsigned ngroups; 263 }; 264 265 struct st_pctl_group { 266 const char *name; 267 unsigned int *pins; 268 unsigned npins; 269 struct st_pinconf *pin_conf; 270 }; 271 272 /* 273 * Edge triggers are not supported at hardware level, it is supported by 274 * software by exploiting the level trigger support in hardware. 275 * Software uses a virtual register (EDGE_CONF) for edge trigger configuration 276 * of each gpio pin in a GPIO bank. 277 * 278 * Each bank has a 32 bit EDGE_CONF register which is divided in to 8 parts of 279 * 4-bits. Each 4-bit space is allocated for each pin in a gpio bank. 280 * 281 * bit allocation per pin is: 282 * Bits: [0 - 3] | [4 - 7] [8 - 11] ... ... ... ... [ 28 - 31] 283 * -------------------------------------------------------- 284 * | pin-0 | pin-2 | pin-3 | ... ... ... ... | pin -7 | 285 * -------------------------------------------------------- 286 * 287 * A pin can have one of following the values in its edge configuration field. 288 * 289 * ------- ---------------------------- 290 * [0-3] - Description 291 * ------- ---------------------------- 292 * 0000 - No edge IRQ. 293 * 0001 - Falling edge IRQ. 294 * 0010 - Rising edge IRQ. 295 * 0011 - Rising and Falling edge IRQ. 296 * ------- ---------------------------- 297 */ 298 299 #define ST_IRQ_EDGE_CONF_BITS_PER_PIN 4 300 #define ST_IRQ_EDGE_MASK 0xf 301 #define ST_IRQ_EDGE_FALLING BIT(0) 302 #define ST_IRQ_EDGE_RISING BIT(1) 303 #define ST_IRQ_EDGE_BOTH (BIT(0) | BIT(1)) 304 305 #define ST_IRQ_RISING_EDGE_CONF(pin) \ 306 (ST_IRQ_EDGE_RISING << (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN)) 307 308 #define ST_IRQ_FALLING_EDGE_CONF(pin) \ 309 (ST_IRQ_EDGE_FALLING << (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN)) 310 311 #define ST_IRQ_BOTH_EDGE_CONF(pin) \ 312 (ST_IRQ_EDGE_BOTH << (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN)) 313 314 #define ST_IRQ_EDGE_CONF(conf, pin) \ 315 (conf >> (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN) & ST_IRQ_EDGE_MASK) 316 317 struct st_gpio_bank { 318 struct gpio_chip gpio_chip; 319 struct pinctrl_gpio_range range; 320 void __iomem *base; 321 struct st_pio_control pc; 322 unsigned long irq_edge_conf; 323 spinlock_t lock; 324 }; 325 326 struct st_pinctrl { 327 struct device *dev; 328 struct pinctrl_dev *pctl; 329 struct st_gpio_bank *banks; 330 int nbanks; 331 struct st_pmx_func *functions; 332 int nfunctions; 333 struct st_pctl_group *groups; 334 int ngroups; 335 struct regmap *regmap; 336 const struct st_pctl_data *data; 337 void __iomem *irqmux_base; 338 }; 339 340 /* SOC specific data */ 341 /* STiH415 data */ 342 static const unsigned int stih415_input_delays[] = {0, 500, 1000, 1500}; 343 static const unsigned int stih415_output_delays[] = {0, 1000, 2000, 3000}; 344 345 #define STIH415_PCTRL_COMMON_DATA \ 346 .rt_style = st_retime_style_packed, \ 347 .input_delays = stih415_input_delays, \ 348 .ninput_delays = ARRAY_SIZE(stih415_input_delays), \ 349 .output_delays = stih415_output_delays, \ 350 .noutput_delays = ARRAY_SIZE(stih415_output_delays) 351 352 static const struct st_pctl_data stih415_sbc_data = { 353 STIH415_PCTRL_COMMON_DATA, 354 .alt = 0, .oe = 5, .pu = 7, .od = 9, .rt = 16, 355 }; 356 357 static const struct st_pctl_data stih415_front_data = { 358 STIH415_PCTRL_COMMON_DATA, 359 .alt = 0, .oe = 8, .pu = 10, .od = 12, .rt = 16, 360 }; 361 362 static const struct st_pctl_data stih415_rear_data = { 363 STIH415_PCTRL_COMMON_DATA, 364 .alt = 0, .oe = 6, .pu = 8, .od = 10, .rt = 38, 365 }; 366 367 static const struct st_pctl_data stih415_left_data = { 368 STIH415_PCTRL_COMMON_DATA, 369 .alt = 0, .oe = 3, .pu = 4, .od = 5, .rt = 6, 370 }; 371 372 static const struct st_pctl_data stih415_right_data = { 373 STIH415_PCTRL_COMMON_DATA, 374 .alt = 0, .oe = 5, .pu = 7, .od = 9, .rt = 11, 375 }; 376 377 /* STiH416 data */ 378 static const unsigned int stih416_delays[] = {0, 300, 500, 750, 1000, 1250, 379 1500, 1750, 2000, 2250, 2500, 2750, 3000, 3250 }; 380 381 static const struct st_pctl_data stih416_data = { 382 .rt_style = st_retime_style_dedicated, 383 .input_delays = stih416_delays, 384 .ninput_delays = ARRAY_SIZE(stih416_delays), 385 .output_delays = stih416_delays, 386 .noutput_delays = ARRAY_SIZE(stih416_delays), 387 .alt = 0, .oe = 40, .pu = 50, .od = 60, .rt = 100, 388 }; 389 390 static const struct st_pctl_data stih407_flashdata = { 391 .rt_style = st_retime_style_none, 392 .input_delays = stih416_delays, 393 .ninput_delays = ARRAY_SIZE(stih416_delays), 394 .output_delays = stih416_delays, 395 .noutput_delays = ARRAY_SIZE(stih416_delays), 396 .alt = 0, 397 .oe = -1, /* Not Available */ 398 .pu = -1, /* Not Available */ 399 .od = 60, 400 .rt = 100, 401 }; 402 403 static struct st_pio_control *st_get_pio_control( 404 struct pinctrl_dev *pctldev, int pin) 405 { 406 struct pinctrl_gpio_range *range = 407 pinctrl_find_gpio_range_from_pin(pctldev, pin); 408 struct st_gpio_bank *bank = gpio_range_to_bank(range); 409 410 return &bank->pc; 411 } 412 413 /* Low level functions.. */ 414 static inline int st_gpio_bank(int gpio) 415 { 416 return gpio/ST_GPIO_PINS_PER_BANK; 417 } 418 419 static inline int st_gpio_pin(int gpio) 420 { 421 return gpio%ST_GPIO_PINS_PER_BANK; 422 } 423 424 static void st_pinconf_set_config(struct st_pio_control *pc, 425 int pin, unsigned long config) 426 { 427 struct regmap_field *output_enable = pc->oe; 428 struct regmap_field *pull_up = pc->pu; 429 struct regmap_field *open_drain = pc->od; 430 unsigned int oe_value, pu_value, od_value; 431 unsigned long mask = BIT(pin); 432 433 if (output_enable) { 434 regmap_field_read(output_enable, &oe_value); 435 oe_value &= ~mask; 436 if (config & ST_PINCONF_OE) 437 oe_value |= mask; 438 regmap_field_write(output_enable, oe_value); 439 } 440 441 if (pull_up) { 442 regmap_field_read(pull_up, &pu_value); 443 pu_value &= ~mask; 444 if (config & ST_PINCONF_PU) 445 pu_value |= mask; 446 regmap_field_write(pull_up, pu_value); 447 } 448 449 if (open_drain) { 450 regmap_field_read(open_drain, &od_value); 451 od_value &= ~mask; 452 if (config & ST_PINCONF_OD) 453 od_value |= mask; 454 regmap_field_write(open_drain, od_value); 455 } 456 } 457 458 static void st_pctl_set_function(struct st_pio_control *pc, 459 int pin_id, int function) 460 { 461 struct regmap_field *alt = pc->alt; 462 unsigned int val; 463 int pin = st_gpio_pin(pin_id); 464 int offset = pin * 4; 465 466 if (!alt) 467 return; 468 469 regmap_field_read(alt, &val); 470 val &= ~(0xf << offset); 471 val |= function << offset; 472 regmap_field_write(alt, val); 473 } 474 475 static unsigned int st_pctl_get_pin_function(struct st_pio_control *pc, int pin) 476 { 477 struct regmap_field *alt = pc->alt; 478 unsigned int val; 479 int offset = pin * 4; 480 481 if (!alt) 482 return 0; 483 484 regmap_field_read(alt, &val); 485 486 return (val >> offset) & 0xf; 487 } 488 489 static unsigned long st_pinconf_delay_to_bit(unsigned int delay, 490 const struct st_pctl_data *data, unsigned long config) 491 { 492 const unsigned int *delay_times; 493 int num_delay_times, i, closest_index = -1; 494 unsigned int closest_divergence = UINT_MAX; 495 496 if (ST_PINCONF_UNPACK_OE(config)) { 497 delay_times = data->output_delays; 498 num_delay_times = data->noutput_delays; 499 } else { 500 delay_times = data->input_delays; 501 num_delay_times = data->ninput_delays; 502 } 503 504 for (i = 0; i < num_delay_times; i++) { 505 unsigned int divergence = abs(delay - delay_times[i]); 506 507 if (divergence == 0) 508 return i; 509 510 if (divergence < closest_divergence) { 511 closest_divergence = divergence; 512 closest_index = i; 513 } 514 } 515 516 pr_warn("Attempt to set delay %d, closest available %d\n", 517 delay, delay_times[closest_index]); 518 519 return closest_index; 520 } 521 522 static unsigned long st_pinconf_bit_to_delay(unsigned int index, 523 const struct st_pctl_data *data, unsigned long output) 524 { 525 const unsigned int *delay_times; 526 int num_delay_times; 527 528 if (output) { 529 delay_times = data->output_delays; 530 num_delay_times = data->noutput_delays; 531 } else { 532 delay_times = data->input_delays; 533 num_delay_times = data->ninput_delays; 534 } 535 536 if (index < num_delay_times) { 537 return delay_times[index]; 538 } else { 539 pr_warn("Delay not found in/out delay list\n"); 540 return 0; 541 } 542 } 543 544 static void st_regmap_field_bit_set_clear_pin(struct regmap_field *field, 545 int enable, int pin) 546 { 547 unsigned int val = 0; 548 549 regmap_field_read(field, &val); 550 if (enable) 551 val |= BIT(pin); 552 else 553 val &= ~BIT(pin); 554 regmap_field_write(field, val); 555 } 556 557 static void st_pinconf_set_retime_packed(struct st_pinctrl *info, 558 struct st_pio_control *pc, unsigned long config, int pin) 559 { 560 const struct st_pctl_data *data = info->data; 561 struct st_retime_packed *rt_p = &pc->rt.rt_p; 562 unsigned int delay; 563 564 st_regmap_field_bit_set_clear_pin(rt_p->clk1notclk0, 565 ST_PINCONF_UNPACK_RT_CLK(config), pin); 566 567 st_regmap_field_bit_set_clear_pin(rt_p->clknotdata, 568 ST_PINCONF_UNPACK_RT_CLKNOTDATA(config), pin); 569 570 st_regmap_field_bit_set_clear_pin(rt_p->double_edge, 571 ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(config), pin); 572 573 st_regmap_field_bit_set_clear_pin(rt_p->invertclk, 574 ST_PINCONF_UNPACK_RT_INVERTCLK(config), pin); 575 576 st_regmap_field_bit_set_clear_pin(rt_p->retime, 577 ST_PINCONF_UNPACK_RT(config), pin); 578 579 delay = st_pinconf_delay_to_bit(ST_PINCONF_UNPACK_RT_DELAY(config), 580 data, config); 581 /* 2 bit delay, lsb */ 582 st_regmap_field_bit_set_clear_pin(rt_p->delay_0, delay & 0x1, pin); 583 /* 2 bit delay, msb */ 584 st_regmap_field_bit_set_clear_pin(rt_p->delay_1, delay & 0x2, pin); 585 586 } 587 588 static void st_pinconf_set_retime_dedicated(struct st_pinctrl *info, 589 struct st_pio_control *pc, unsigned long config, int pin) 590 { 591 int input = ST_PINCONF_UNPACK_OE(config) ? 0 : 1; 592 int clk = ST_PINCONF_UNPACK_RT_CLK(config); 593 int clknotdata = ST_PINCONF_UNPACK_RT_CLKNOTDATA(config); 594 int double_edge = ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(config); 595 int invertclk = ST_PINCONF_UNPACK_RT_INVERTCLK(config); 596 int retime = ST_PINCONF_UNPACK_RT(config); 597 598 unsigned long delay = st_pinconf_delay_to_bit( 599 ST_PINCONF_UNPACK_RT_DELAY(config), 600 info->data, config); 601 struct st_retime_dedicated *rt_d = &pc->rt.rt_d; 602 603 unsigned long retime_config = 604 ((clk) << RT_D_CFG_CLK_SHIFT) | 605 ((delay) << RT_D_CFG_DELAY_SHIFT) | 606 ((input) << RT_D_CFG_DELAY_INNOTOUT_SHIFT) | 607 ((retime) << RT_D_CFG_RETIME_SHIFT) | 608 ((clknotdata) << RT_D_CFG_CLKNOTDATA_SHIFT) | 609 ((invertclk) << RT_D_CFG_INVERTCLK_SHIFT) | 610 ((double_edge) << RT_D_CFG_DOUBLE_EDGE_SHIFT); 611 612 regmap_field_write(rt_d->rt[pin], retime_config); 613 } 614 615 static void st_pinconf_get_direction(struct st_pio_control *pc, 616 int pin, unsigned long *config) 617 { 618 unsigned int oe_value, pu_value, od_value; 619 620 if (pc->oe) { 621 regmap_field_read(pc->oe, &oe_value); 622 if (oe_value & BIT(pin)) 623 ST_PINCONF_PACK_OE(*config); 624 } 625 626 if (pc->pu) { 627 regmap_field_read(pc->pu, &pu_value); 628 if (pu_value & BIT(pin)) 629 ST_PINCONF_PACK_PU(*config); 630 } 631 632 if (pc->od) { 633 regmap_field_read(pc->od, &od_value); 634 if (od_value & BIT(pin)) 635 ST_PINCONF_PACK_OD(*config); 636 } 637 } 638 639 static int st_pinconf_get_retime_packed(struct st_pinctrl *info, 640 struct st_pio_control *pc, int pin, unsigned long *config) 641 { 642 const struct st_pctl_data *data = info->data; 643 struct st_retime_packed *rt_p = &pc->rt.rt_p; 644 unsigned int delay_bits, delay, delay0, delay1, val; 645 int output = ST_PINCONF_UNPACK_OE(*config); 646 647 if (!regmap_field_read(rt_p->retime, &val) && (val & BIT(pin))) 648 ST_PINCONF_PACK_RT(*config); 649 650 if (!regmap_field_read(rt_p->clk1notclk0, &val) && (val & BIT(pin))) 651 ST_PINCONF_PACK_RT_CLK(*config, 1); 652 653 if (!regmap_field_read(rt_p->clknotdata, &val) && (val & BIT(pin))) 654 ST_PINCONF_PACK_RT_CLKNOTDATA(*config); 655 656 if (!regmap_field_read(rt_p->double_edge, &val) && (val & BIT(pin))) 657 ST_PINCONF_PACK_RT_DOUBLE_EDGE(*config); 658 659 if (!regmap_field_read(rt_p->invertclk, &val) && (val & BIT(pin))) 660 ST_PINCONF_PACK_RT_INVERTCLK(*config); 661 662 regmap_field_read(rt_p->delay_0, &delay0); 663 regmap_field_read(rt_p->delay_1, &delay1); 664 delay_bits = (((delay1 & BIT(pin)) ? 1 : 0) << 1) | 665 (((delay0 & BIT(pin)) ? 1 : 0)); 666 delay = st_pinconf_bit_to_delay(delay_bits, data, output); 667 ST_PINCONF_PACK_RT_DELAY(*config, delay); 668 669 return 0; 670 } 671 672 static int st_pinconf_get_retime_dedicated(struct st_pinctrl *info, 673 struct st_pio_control *pc, int pin, unsigned long *config) 674 { 675 unsigned int value; 676 unsigned long delay_bits, delay, rt_clk; 677 int output = ST_PINCONF_UNPACK_OE(*config); 678 struct st_retime_dedicated *rt_d = &pc->rt.rt_d; 679 680 regmap_field_read(rt_d->rt[pin], &value); 681 682 rt_clk = (value & RT_D_CFG_CLK_MASK) >> RT_D_CFG_CLK_SHIFT; 683 ST_PINCONF_PACK_RT_CLK(*config, rt_clk); 684 685 delay_bits = (value & RT_D_CFG_DELAY_MASK) >> RT_D_CFG_DELAY_SHIFT; 686 delay = st_pinconf_bit_to_delay(delay_bits, info->data, output); 687 ST_PINCONF_PACK_RT_DELAY(*config, delay); 688 689 if (value & RT_D_CFG_CLKNOTDATA_MASK) 690 ST_PINCONF_PACK_RT_CLKNOTDATA(*config); 691 692 if (value & RT_D_CFG_DOUBLE_EDGE_MASK) 693 ST_PINCONF_PACK_RT_DOUBLE_EDGE(*config); 694 695 if (value & RT_D_CFG_INVERTCLK_MASK) 696 ST_PINCONF_PACK_RT_INVERTCLK(*config); 697 698 if (value & RT_D_CFG_RETIME_MASK) 699 ST_PINCONF_PACK_RT(*config); 700 701 return 0; 702 } 703 704 /* GPIO related functions */ 705 706 static inline void __st_gpio_set(struct st_gpio_bank *bank, 707 unsigned offset, int value) 708 { 709 if (value) 710 writel(BIT(offset), bank->base + REG_PIO_SET_POUT); 711 else 712 writel(BIT(offset), bank->base + REG_PIO_CLR_POUT); 713 } 714 715 static void st_gpio_direction(struct st_gpio_bank *bank, 716 unsigned int gpio, unsigned int direction) 717 { 718 int offset = st_gpio_pin(gpio); 719 int i = 0; 720 /** 721 * There are three configuration registers (PIOn_PC0, PIOn_PC1 722 * and PIOn_PC2) for each port. These are used to configure the 723 * PIO port pins. Each pin can be configured as an input, output, 724 * bidirectional, or alternative function pin. Three bits, one bit 725 * from each of the three registers, configure the corresponding bit of 726 * the port. Valid bit settings is: 727 * 728 * PC2 PC1 PC0 Direction. 729 * 0 0 0 [Input Weak pull-up] 730 * 0 0 or 1 1 [Bidirection] 731 * 0 1 0 [Output] 732 * 1 0 0 [Input] 733 * 734 * PIOn_SET_PC and PIOn_CLR_PC registers are used to set and clear bits 735 * individually. 736 */ 737 for (i = 0; i <= 2; i++) { 738 if (direction & BIT(i)) 739 writel(BIT(offset), bank->base + REG_PIO_SET_PC(i)); 740 else 741 writel(BIT(offset), bank->base + REG_PIO_CLR_PC(i)); 742 } 743 } 744 745 static int st_gpio_request(struct gpio_chip *chip, unsigned offset) 746 { 747 return pinctrl_request_gpio(chip->base + offset); 748 } 749 750 static void st_gpio_free(struct gpio_chip *chip, unsigned offset) 751 { 752 pinctrl_free_gpio(chip->base + offset); 753 } 754 755 static int st_gpio_get(struct gpio_chip *chip, unsigned offset) 756 { 757 struct st_gpio_bank *bank = gpio_chip_to_bank(chip); 758 759 return !!(readl(bank->base + REG_PIO_PIN) & BIT(offset)); 760 } 761 762 static void st_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 763 { 764 struct st_gpio_bank *bank = gpio_chip_to_bank(chip); 765 __st_gpio_set(bank, offset, value); 766 } 767 768 static int st_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 769 { 770 pinctrl_gpio_direction_input(chip->base + offset); 771 772 return 0; 773 } 774 775 static int st_gpio_direction_output(struct gpio_chip *chip, 776 unsigned offset, int value) 777 { 778 struct st_gpio_bank *bank = gpio_chip_to_bank(chip); 779 780 __st_gpio_set(bank, offset, value); 781 pinctrl_gpio_direction_output(chip->base + offset); 782 783 return 0; 784 } 785 786 static int st_gpio_get_direction(struct gpio_chip *chip, unsigned offset) 787 { 788 struct st_gpio_bank *bank = gpio_chip_to_bank(chip); 789 struct st_pio_control pc = bank->pc; 790 unsigned long config; 791 unsigned int direction = 0; 792 unsigned int function; 793 unsigned int value; 794 int i = 0; 795 796 /* Alternate function direction is handled by Pinctrl */ 797 function = st_pctl_get_pin_function(&pc, offset); 798 if (function) { 799 st_pinconf_get_direction(&pc, offset, &config); 800 return !ST_PINCONF_UNPACK_OE(config); 801 } 802 803 /* 804 * GPIO direction is handled differently 805 * - See st_gpio_direction() above for an explanation 806 */ 807 for (i = 0; i <= 2; i++) { 808 value = readl(bank->base + REG_PIO_PC(i)); 809 direction |= ((value >> offset) & 0x1) << i; 810 } 811 812 return (direction == ST_GPIO_DIRECTION_IN); 813 } 814 815 static int st_gpio_xlate(struct gpio_chip *gc, 816 const struct of_phandle_args *gpiospec, u32 *flags) 817 { 818 if (WARN_ON(gc->of_gpio_n_cells < 1)) 819 return -EINVAL; 820 821 if (WARN_ON(gpiospec->args_count < gc->of_gpio_n_cells)) 822 return -EINVAL; 823 824 if (gpiospec->args[0] > gc->ngpio) 825 return -EINVAL; 826 827 return gpiospec->args[0]; 828 } 829 830 /* Pinctrl Groups */ 831 static int st_pctl_get_groups_count(struct pinctrl_dev *pctldev) 832 { 833 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 834 835 return info->ngroups; 836 } 837 838 static const char *st_pctl_get_group_name(struct pinctrl_dev *pctldev, 839 unsigned selector) 840 { 841 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 842 843 return info->groups[selector].name; 844 } 845 846 static int st_pctl_get_group_pins(struct pinctrl_dev *pctldev, 847 unsigned selector, const unsigned **pins, unsigned *npins) 848 { 849 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 850 851 if (selector >= info->ngroups) 852 return -EINVAL; 853 854 *pins = info->groups[selector].pins; 855 *npins = info->groups[selector].npins; 856 857 return 0; 858 } 859 860 static const inline struct st_pctl_group *st_pctl_find_group_by_name( 861 const struct st_pinctrl *info, const char *name) 862 { 863 int i; 864 865 for (i = 0; i < info->ngroups; i++) { 866 if (!strcmp(info->groups[i].name, name)) 867 return &info->groups[i]; 868 } 869 870 return NULL; 871 } 872 873 static int st_pctl_dt_node_to_map(struct pinctrl_dev *pctldev, 874 struct device_node *np, struct pinctrl_map **map, unsigned *num_maps) 875 { 876 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 877 const struct st_pctl_group *grp; 878 struct pinctrl_map *new_map; 879 struct device_node *parent; 880 int map_num, i; 881 882 grp = st_pctl_find_group_by_name(info, np->name); 883 if (!grp) { 884 dev_err(info->dev, "unable to find group for node %s\n", 885 np->name); 886 return -EINVAL; 887 } 888 889 map_num = grp->npins + 1; 890 new_map = devm_kzalloc(pctldev->dev, 891 sizeof(*new_map) * map_num, GFP_KERNEL); 892 if (!new_map) 893 return -ENOMEM; 894 895 parent = of_get_parent(np); 896 if (!parent) { 897 devm_kfree(pctldev->dev, new_map); 898 return -EINVAL; 899 } 900 901 *map = new_map; 902 *num_maps = map_num; 903 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP; 904 new_map[0].data.mux.function = parent->name; 905 new_map[0].data.mux.group = np->name; 906 of_node_put(parent); 907 908 /* create config map per pin */ 909 new_map++; 910 for (i = 0; i < grp->npins; i++) { 911 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN; 912 new_map[i].data.configs.group_or_pin = 913 pin_get_name(pctldev, grp->pins[i]); 914 new_map[i].data.configs.configs = &grp->pin_conf[i].config; 915 new_map[i].data.configs.num_configs = 1; 916 } 917 dev_info(pctldev->dev, "maps: function %s group %s num %d\n", 918 (*map)->data.mux.function, grp->name, map_num); 919 920 return 0; 921 } 922 923 static void st_pctl_dt_free_map(struct pinctrl_dev *pctldev, 924 struct pinctrl_map *map, unsigned num_maps) 925 { 926 } 927 928 static struct pinctrl_ops st_pctlops = { 929 .get_groups_count = st_pctl_get_groups_count, 930 .get_group_pins = st_pctl_get_group_pins, 931 .get_group_name = st_pctl_get_group_name, 932 .dt_node_to_map = st_pctl_dt_node_to_map, 933 .dt_free_map = st_pctl_dt_free_map, 934 }; 935 936 /* Pinmux */ 937 static int st_pmx_get_funcs_count(struct pinctrl_dev *pctldev) 938 { 939 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 940 941 return info->nfunctions; 942 } 943 944 static const char *st_pmx_get_fname(struct pinctrl_dev *pctldev, 945 unsigned selector) 946 { 947 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 948 949 return info->functions[selector].name; 950 } 951 952 static int st_pmx_get_groups(struct pinctrl_dev *pctldev, 953 unsigned selector, const char * const **grps, unsigned * const ngrps) 954 { 955 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 956 *grps = info->functions[selector].groups; 957 *ngrps = info->functions[selector].ngroups; 958 959 return 0; 960 } 961 962 static int st_pmx_set_mux(struct pinctrl_dev *pctldev, unsigned fselector, 963 unsigned group) 964 { 965 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 966 struct st_pinconf *conf = info->groups[group].pin_conf; 967 struct st_pio_control *pc; 968 int i; 969 970 for (i = 0; i < info->groups[group].npins; i++) { 971 pc = st_get_pio_control(pctldev, conf[i].pin); 972 st_pctl_set_function(pc, conf[i].pin, conf[i].altfunc); 973 } 974 975 return 0; 976 } 977 978 static int st_pmx_set_gpio_direction(struct pinctrl_dev *pctldev, 979 struct pinctrl_gpio_range *range, unsigned gpio, 980 bool input) 981 { 982 struct st_gpio_bank *bank = gpio_range_to_bank(range); 983 /* 984 * When a PIO bank is used in its primary function mode (altfunc = 0) 985 * Output Enable (OE), Open Drain(OD), and Pull Up (PU) 986 * for the primary PIO functions are driven by the related PIO block 987 */ 988 st_pctl_set_function(&bank->pc, gpio, 0); 989 st_gpio_direction(bank, gpio, input ? 990 ST_GPIO_DIRECTION_IN : ST_GPIO_DIRECTION_OUT); 991 992 return 0; 993 } 994 995 static struct pinmux_ops st_pmxops = { 996 .get_functions_count = st_pmx_get_funcs_count, 997 .get_function_name = st_pmx_get_fname, 998 .get_function_groups = st_pmx_get_groups, 999 .set_mux = st_pmx_set_mux, 1000 .gpio_set_direction = st_pmx_set_gpio_direction, 1001 }; 1002 1003 /* Pinconf */ 1004 static void st_pinconf_get_retime(struct st_pinctrl *info, 1005 struct st_pio_control *pc, int pin, unsigned long *config) 1006 { 1007 if (info->data->rt_style == st_retime_style_packed) 1008 st_pinconf_get_retime_packed(info, pc, pin, config); 1009 else if (info->data->rt_style == st_retime_style_dedicated) 1010 if ((BIT(pin) & pc->rt_pin_mask)) 1011 st_pinconf_get_retime_dedicated(info, pc, 1012 pin, config); 1013 } 1014 1015 static void st_pinconf_set_retime(struct st_pinctrl *info, 1016 struct st_pio_control *pc, int pin, unsigned long config) 1017 { 1018 if (info->data->rt_style == st_retime_style_packed) 1019 st_pinconf_set_retime_packed(info, pc, config, pin); 1020 else if (info->data->rt_style == st_retime_style_dedicated) 1021 if ((BIT(pin) & pc->rt_pin_mask)) 1022 st_pinconf_set_retime_dedicated(info, pc, 1023 config, pin); 1024 } 1025 1026 static int st_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin_id, 1027 unsigned long *configs, unsigned num_configs) 1028 { 1029 int pin = st_gpio_pin(pin_id); 1030 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1031 struct st_pio_control *pc = st_get_pio_control(pctldev, pin_id); 1032 int i; 1033 1034 for (i = 0; i < num_configs; i++) { 1035 st_pinconf_set_config(pc, pin, configs[i]); 1036 st_pinconf_set_retime(info, pc, pin, configs[i]); 1037 } /* for each config */ 1038 1039 return 0; 1040 } 1041 1042 static int st_pinconf_get(struct pinctrl_dev *pctldev, 1043 unsigned pin_id, unsigned long *config) 1044 { 1045 int pin = st_gpio_pin(pin_id); 1046 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1047 struct st_pio_control *pc = st_get_pio_control(pctldev, pin_id); 1048 1049 *config = 0; 1050 st_pinconf_get_direction(pc, pin, config); 1051 st_pinconf_get_retime(info, pc, pin, config); 1052 1053 return 0; 1054 } 1055 1056 static void st_pinconf_dbg_show(struct pinctrl_dev *pctldev, 1057 struct seq_file *s, unsigned pin_id) 1058 { 1059 struct st_pio_control *pc; 1060 unsigned long config; 1061 unsigned int function; 1062 int offset = st_gpio_pin(pin_id); 1063 char f[16]; 1064 1065 mutex_unlock(&pctldev->mutex); 1066 pc = st_get_pio_control(pctldev, pin_id); 1067 st_pinconf_get(pctldev, pin_id, &config); 1068 mutex_lock(&pctldev->mutex); 1069 1070 function = st_pctl_get_pin_function(pc, offset); 1071 if (function) 1072 snprintf(f, 10, "Alt Fn %d", function); 1073 else 1074 snprintf(f, 5, "GPIO"); 1075 1076 seq_printf(s, "[OE:%d,PU:%ld,OD:%ld]\t%s\n" 1077 "\t\t[retime:%ld,invclk:%ld,clknotdat:%ld," 1078 "de:%ld,rt-clk:%ld,rt-delay:%ld]", 1079 !st_gpio_get_direction(&pc_to_bank(pc)->gpio_chip, offset), 1080 ST_PINCONF_UNPACK_PU(config), 1081 ST_PINCONF_UNPACK_OD(config), 1082 f, 1083 ST_PINCONF_UNPACK_RT(config), 1084 ST_PINCONF_UNPACK_RT_INVERTCLK(config), 1085 ST_PINCONF_UNPACK_RT_CLKNOTDATA(config), 1086 ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(config), 1087 ST_PINCONF_UNPACK_RT_CLK(config), 1088 ST_PINCONF_UNPACK_RT_DELAY(config)); 1089 } 1090 1091 static struct pinconf_ops st_confops = { 1092 .pin_config_get = st_pinconf_get, 1093 .pin_config_set = st_pinconf_set, 1094 .pin_config_dbg_show = st_pinconf_dbg_show, 1095 }; 1096 1097 static void st_pctl_dt_child_count(struct st_pinctrl *info, 1098 struct device_node *np) 1099 { 1100 struct device_node *child; 1101 for_each_child_of_node(np, child) { 1102 if (of_property_read_bool(child, "gpio-controller")) { 1103 info->nbanks++; 1104 } else { 1105 info->nfunctions++; 1106 info->ngroups += of_get_child_count(child); 1107 } 1108 } 1109 } 1110 1111 static int st_pctl_dt_setup_retime_packed(struct st_pinctrl *info, 1112 int bank, struct st_pio_control *pc) 1113 { 1114 struct device *dev = info->dev; 1115 struct regmap *rm = info->regmap; 1116 const struct st_pctl_data *data = info->data; 1117 /* 2 registers per bank */ 1118 int reg = (data->rt + bank * RT_P_CFGS_PER_BANK) * 4; 1119 struct st_retime_packed *rt_p = &pc->rt.rt_p; 1120 /* cfg0 */ 1121 struct reg_field clk1notclk0 = RT_P_CFG0_CLK1NOTCLK0_FIELD(reg); 1122 struct reg_field delay_0 = RT_P_CFG0_DELAY_0_FIELD(reg); 1123 struct reg_field delay_1 = RT_P_CFG0_DELAY_1_FIELD(reg); 1124 /* cfg1 */ 1125 struct reg_field invertclk = RT_P_CFG1_INVERTCLK_FIELD(reg + 4); 1126 struct reg_field retime = RT_P_CFG1_RETIME_FIELD(reg + 4); 1127 struct reg_field clknotdata = RT_P_CFG1_CLKNOTDATA_FIELD(reg + 4); 1128 struct reg_field double_edge = RT_P_CFG1_DOUBLE_EDGE_FIELD(reg + 4); 1129 1130 rt_p->clk1notclk0 = devm_regmap_field_alloc(dev, rm, clk1notclk0); 1131 rt_p->delay_0 = devm_regmap_field_alloc(dev, rm, delay_0); 1132 rt_p->delay_1 = devm_regmap_field_alloc(dev, rm, delay_1); 1133 rt_p->invertclk = devm_regmap_field_alloc(dev, rm, invertclk); 1134 rt_p->retime = devm_regmap_field_alloc(dev, rm, retime); 1135 rt_p->clknotdata = devm_regmap_field_alloc(dev, rm, clknotdata); 1136 rt_p->double_edge = devm_regmap_field_alloc(dev, rm, double_edge); 1137 1138 if (IS_ERR(rt_p->clk1notclk0) || IS_ERR(rt_p->delay_0) || 1139 IS_ERR(rt_p->delay_1) || IS_ERR(rt_p->invertclk) || 1140 IS_ERR(rt_p->retime) || IS_ERR(rt_p->clknotdata) || 1141 IS_ERR(rt_p->double_edge)) 1142 return -EINVAL; 1143 1144 return 0; 1145 } 1146 1147 static int st_pctl_dt_setup_retime_dedicated(struct st_pinctrl *info, 1148 int bank, struct st_pio_control *pc) 1149 { 1150 struct device *dev = info->dev; 1151 struct regmap *rm = info->regmap; 1152 const struct st_pctl_data *data = info->data; 1153 /* 8 registers per bank */ 1154 int reg_offset = (data->rt + bank * RT_D_CFGS_PER_BANK) * 4; 1155 struct st_retime_dedicated *rt_d = &pc->rt.rt_d; 1156 unsigned int j; 1157 u32 pin_mask = pc->rt_pin_mask; 1158 1159 for (j = 0; j < RT_D_CFGS_PER_BANK; j++) { 1160 if (BIT(j) & pin_mask) { 1161 struct reg_field reg = REG_FIELD(reg_offset, 0, 31); 1162 rt_d->rt[j] = devm_regmap_field_alloc(dev, rm, reg); 1163 if (IS_ERR(rt_d->rt[j])) 1164 return -EINVAL; 1165 reg_offset += 4; 1166 } 1167 } 1168 return 0; 1169 } 1170 1171 static int st_pctl_dt_setup_retime(struct st_pinctrl *info, 1172 int bank, struct st_pio_control *pc) 1173 { 1174 const struct st_pctl_data *data = info->data; 1175 if (data->rt_style == st_retime_style_packed) 1176 return st_pctl_dt_setup_retime_packed(info, bank, pc); 1177 else if (data->rt_style == st_retime_style_dedicated) 1178 return st_pctl_dt_setup_retime_dedicated(info, bank, pc); 1179 1180 return -EINVAL; 1181 } 1182 1183 1184 static struct regmap_field *st_pc_get_value(struct device *dev, 1185 struct regmap *regmap, int bank, 1186 int data, int lsb, int msb) 1187 { 1188 struct reg_field reg = REG_FIELD((data + bank) * 4, lsb, msb); 1189 1190 if (data < 0) 1191 return NULL; 1192 1193 return devm_regmap_field_alloc(dev, regmap, reg); 1194 } 1195 1196 static void st_parse_syscfgs(struct st_pinctrl *info, int bank, 1197 struct device_node *np) 1198 { 1199 const struct st_pctl_data *data = info->data; 1200 /** 1201 * For a given shared register like OE/PU/OD, there are 8 bits per bank 1202 * 0:7 belongs to bank0, 8:15 belongs to bank1 ... 1203 * So each register is shared across 4 banks. 1204 */ 1205 int lsb = (bank%4) * ST_GPIO_PINS_PER_BANK; 1206 int msb = lsb + ST_GPIO_PINS_PER_BANK - 1; 1207 struct st_pio_control *pc = &info->banks[bank].pc; 1208 struct device *dev = info->dev; 1209 struct regmap *regmap = info->regmap; 1210 1211 pc->alt = st_pc_get_value(dev, regmap, bank, data->alt, 0, 31); 1212 pc->oe = st_pc_get_value(dev, regmap, bank/4, data->oe, lsb, msb); 1213 pc->pu = st_pc_get_value(dev, regmap, bank/4, data->pu, lsb, msb); 1214 pc->od = st_pc_get_value(dev, regmap, bank/4, data->od, lsb, msb); 1215 1216 /* retime avaiable for all pins by default */ 1217 pc->rt_pin_mask = 0xff; 1218 of_property_read_u32(np, "st,retime-pin-mask", &pc->rt_pin_mask); 1219 st_pctl_dt_setup_retime(info, bank, pc); 1220 1221 return; 1222 } 1223 1224 /* 1225 * Each pin is represented in of the below forms. 1226 * <bank offset mux direction rt_type rt_delay rt_clk> 1227 */ 1228 static int st_pctl_dt_parse_groups(struct device_node *np, 1229 struct st_pctl_group *grp, struct st_pinctrl *info, int idx) 1230 { 1231 /* bank pad direction val altfunction */ 1232 const __be32 *list; 1233 struct property *pp; 1234 struct st_pinconf *conf; 1235 struct device_node *pins; 1236 int i = 0, npins = 0, nr_props; 1237 1238 pins = of_get_child_by_name(np, "st,pins"); 1239 if (!pins) 1240 return -ENODATA; 1241 1242 for_each_property_of_node(pins, pp) { 1243 /* Skip those we do not want to proceed */ 1244 if (!strcmp(pp->name, "name")) 1245 continue; 1246 1247 if (pp && (pp->length/sizeof(__be32)) >= OF_GPIO_ARGS_MIN) { 1248 npins++; 1249 } else { 1250 pr_warn("Invalid st,pins in %s node\n", np->name); 1251 return -EINVAL; 1252 } 1253 } 1254 1255 grp->npins = npins; 1256 grp->name = np->name; 1257 grp->pins = devm_kzalloc(info->dev, npins * sizeof(u32), GFP_KERNEL); 1258 grp->pin_conf = devm_kzalloc(info->dev, 1259 npins * sizeof(*conf), GFP_KERNEL); 1260 1261 if (!grp->pins || !grp->pin_conf) 1262 return -ENOMEM; 1263 1264 /* <bank offset mux direction rt_type rt_delay rt_clk> */ 1265 for_each_property_of_node(pins, pp) { 1266 if (!strcmp(pp->name, "name")) 1267 continue; 1268 nr_props = pp->length/sizeof(u32); 1269 list = pp->value; 1270 conf = &grp->pin_conf[i]; 1271 1272 /* bank & offset */ 1273 be32_to_cpup(list++); 1274 be32_to_cpup(list++); 1275 conf->pin = of_get_named_gpio(pins, pp->name, 0); 1276 conf->name = pp->name; 1277 grp->pins[i] = conf->pin; 1278 /* mux */ 1279 conf->altfunc = be32_to_cpup(list++); 1280 conf->config = 0; 1281 /* direction */ 1282 conf->config |= be32_to_cpup(list++); 1283 /* rt_type rt_delay rt_clk */ 1284 if (nr_props >= OF_GPIO_ARGS_MIN + OF_RT_ARGS_MIN) { 1285 /* rt_type */ 1286 conf->config |= be32_to_cpup(list++); 1287 /* rt_delay */ 1288 conf->config |= be32_to_cpup(list++); 1289 /* rt_clk */ 1290 if (nr_props > OF_GPIO_ARGS_MIN + OF_RT_ARGS_MIN) 1291 conf->config |= be32_to_cpup(list++); 1292 } 1293 i++; 1294 } 1295 of_node_put(pins); 1296 1297 return 0; 1298 } 1299 1300 static int st_pctl_parse_functions(struct device_node *np, 1301 struct st_pinctrl *info, u32 index, int *grp_index) 1302 { 1303 struct device_node *child; 1304 struct st_pmx_func *func; 1305 struct st_pctl_group *grp; 1306 int ret, i; 1307 1308 func = &info->functions[index]; 1309 func->name = np->name; 1310 func->ngroups = of_get_child_count(np); 1311 if (func->ngroups == 0) { 1312 dev_err(info->dev, "No groups defined\n"); 1313 return -EINVAL; 1314 } 1315 func->groups = devm_kzalloc(info->dev, 1316 func->ngroups * sizeof(char *), GFP_KERNEL); 1317 if (!func->groups) 1318 return -ENOMEM; 1319 1320 i = 0; 1321 for_each_child_of_node(np, child) { 1322 func->groups[i] = child->name; 1323 grp = &info->groups[*grp_index]; 1324 *grp_index += 1; 1325 ret = st_pctl_dt_parse_groups(child, grp, info, i++); 1326 if (ret) 1327 return ret; 1328 } 1329 dev_info(info->dev, "Function[%d\t name:%s,\tgroups:%d]\n", 1330 index, func->name, func->ngroups); 1331 1332 return 0; 1333 } 1334 1335 static void st_gpio_irq_mask(struct irq_data *d) 1336 { 1337 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1338 struct st_gpio_bank *bank = gpio_chip_to_bank(gc); 1339 1340 writel(BIT(d->hwirq), bank->base + REG_PIO_CLR_PMASK); 1341 } 1342 1343 static void st_gpio_irq_unmask(struct irq_data *d) 1344 { 1345 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1346 struct st_gpio_bank *bank = gpio_chip_to_bank(gc); 1347 1348 writel(BIT(d->hwirq), bank->base + REG_PIO_SET_PMASK); 1349 } 1350 1351 static int st_gpio_irq_set_type(struct irq_data *d, unsigned type) 1352 { 1353 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1354 struct st_gpio_bank *bank = gpio_chip_to_bank(gc); 1355 unsigned long flags; 1356 int comp, pin = d->hwirq; 1357 u32 val; 1358 u32 pin_edge_conf = 0; 1359 1360 switch (type) { 1361 case IRQ_TYPE_LEVEL_HIGH: 1362 comp = 0; 1363 break; 1364 case IRQ_TYPE_EDGE_FALLING: 1365 comp = 0; 1366 pin_edge_conf = ST_IRQ_FALLING_EDGE_CONF(pin); 1367 break; 1368 case IRQ_TYPE_LEVEL_LOW: 1369 comp = 1; 1370 break; 1371 case IRQ_TYPE_EDGE_RISING: 1372 comp = 1; 1373 pin_edge_conf = ST_IRQ_RISING_EDGE_CONF(pin); 1374 break; 1375 case IRQ_TYPE_EDGE_BOTH: 1376 comp = st_gpio_get(&bank->gpio_chip, pin); 1377 pin_edge_conf = ST_IRQ_BOTH_EDGE_CONF(pin); 1378 break; 1379 default: 1380 return -EINVAL; 1381 } 1382 1383 spin_lock_irqsave(&bank->lock, flags); 1384 bank->irq_edge_conf &= ~(ST_IRQ_EDGE_MASK << ( 1385 pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN)); 1386 bank->irq_edge_conf |= pin_edge_conf; 1387 spin_unlock_irqrestore(&bank->lock, flags); 1388 1389 val = readl(bank->base + REG_PIO_PCOMP); 1390 val &= ~BIT(pin); 1391 val |= (comp << pin); 1392 writel(val, bank->base + REG_PIO_PCOMP); 1393 1394 return 0; 1395 } 1396 1397 /* 1398 * As edge triggers are not supported at hardware level, it is supported by 1399 * software by exploiting the level trigger support in hardware. 1400 * 1401 * Steps for detection raising edge interrupt in software. 1402 * 1403 * Step 1: CONFIGURE pin to detect level LOW interrupts. 1404 * 1405 * Step 2: DETECT level LOW interrupt and in irqmux/gpio bank interrupt handler, 1406 * if the value of pin is low, then CONFIGURE pin for level HIGH interrupt. 1407 * IGNORE calling the actual interrupt handler for the pin at this stage. 1408 * 1409 * Step 3: DETECT level HIGH interrupt and in irqmux/gpio-bank interrupt handler 1410 * if the value of pin is HIGH, CONFIGURE pin for level LOW interrupt and then 1411 * DISPATCH the interrupt to the interrupt handler of the pin. 1412 * 1413 * step-1 ________ __________ 1414 * | | step - 3 1415 * | | 1416 * step -2 |_____| 1417 * 1418 * falling edge is also detected int the same way. 1419 * 1420 */ 1421 static void __gpio_irq_handler(struct st_gpio_bank *bank) 1422 { 1423 unsigned long port_in, port_mask, port_comp, active_irqs; 1424 unsigned long bank_edge_mask, flags; 1425 int n, val, ecfg; 1426 1427 spin_lock_irqsave(&bank->lock, flags); 1428 bank_edge_mask = bank->irq_edge_conf; 1429 spin_unlock_irqrestore(&bank->lock, flags); 1430 1431 for (;;) { 1432 port_in = readl(bank->base + REG_PIO_PIN); 1433 port_comp = readl(bank->base + REG_PIO_PCOMP); 1434 port_mask = readl(bank->base + REG_PIO_PMASK); 1435 1436 active_irqs = (port_in ^ port_comp) & port_mask; 1437 1438 if (active_irqs == 0) 1439 break; 1440 1441 for_each_set_bit(n, &active_irqs, BITS_PER_LONG) { 1442 /* check if we are detecting fake edges ... */ 1443 ecfg = ST_IRQ_EDGE_CONF(bank_edge_mask, n); 1444 1445 if (ecfg) { 1446 /* edge detection. */ 1447 val = st_gpio_get(&bank->gpio_chip, n); 1448 1449 writel(BIT(n), 1450 val ? bank->base + REG_PIO_SET_PCOMP : 1451 bank->base + REG_PIO_CLR_PCOMP); 1452 1453 if (ecfg != ST_IRQ_EDGE_BOTH && 1454 !((ecfg & ST_IRQ_EDGE_FALLING) ^ val)) 1455 continue; 1456 } 1457 1458 generic_handle_irq(irq_find_mapping(bank->gpio_chip.irqdomain, n)); 1459 } 1460 } 1461 } 1462 1463 static void st_gpio_irq_handler(unsigned irq, struct irq_desc *desc) 1464 { 1465 /* interrupt dedicated per bank */ 1466 struct irq_chip *chip = irq_get_chip(irq); 1467 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 1468 struct st_gpio_bank *bank = gpio_chip_to_bank(gc); 1469 1470 chained_irq_enter(chip, desc); 1471 __gpio_irq_handler(bank); 1472 chained_irq_exit(chip, desc); 1473 } 1474 1475 static void st_gpio_irqmux_handler(unsigned irq, struct irq_desc *desc) 1476 { 1477 struct irq_chip *chip = irq_get_chip(irq); 1478 struct st_pinctrl *info = irq_get_handler_data(irq); 1479 unsigned long status; 1480 int n; 1481 1482 chained_irq_enter(chip, desc); 1483 1484 status = readl(info->irqmux_base); 1485 1486 for_each_set_bit(n, &status, info->nbanks) 1487 __gpio_irq_handler(&info->banks[n]); 1488 1489 chained_irq_exit(chip, desc); 1490 } 1491 1492 static struct gpio_chip st_gpio_template = { 1493 .request = st_gpio_request, 1494 .free = st_gpio_free, 1495 .get = st_gpio_get, 1496 .set = st_gpio_set, 1497 .direction_input = st_gpio_direction_input, 1498 .direction_output = st_gpio_direction_output, 1499 .get_direction = st_gpio_get_direction, 1500 .ngpio = ST_GPIO_PINS_PER_BANK, 1501 .of_gpio_n_cells = 1, 1502 .of_xlate = st_gpio_xlate, 1503 }; 1504 1505 static struct irq_chip st_gpio_irqchip = { 1506 .name = "GPIO", 1507 .irq_disable = st_gpio_irq_mask, 1508 .irq_mask = st_gpio_irq_mask, 1509 .irq_unmask = st_gpio_irq_unmask, 1510 .irq_set_type = st_gpio_irq_set_type, 1511 .flags = IRQCHIP_SKIP_SET_WAKE, 1512 }; 1513 1514 static int st_gpiolib_register_bank(struct st_pinctrl *info, 1515 int bank_nr, struct device_node *np) 1516 { 1517 struct st_gpio_bank *bank = &info->banks[bank_nr]; 1518 struct pinctrl_gpio_range *range = &bank->range; 1519 struct device *dev = info->dev; 1520 int bank_num = of_alias_get_id(np, "gpio"); 1521 struct resource res, irq_res; 1522 int gpio_irq = 0, err; 1523 1524 if (of_address_to_resource(np, 0, &res)) 1525 return -ENODEV; 1526 1527 bank->base = devm_ioremap_resource(dev, &res); 1528 if (IS_ERR(bank->base)) 1529 return PTR_ERR(bank->base); 1530 1531 bank->gpio_chip = st_gpio_template; 1532 bank->gpio_chip.base = bank_num * ST_GPIO_PINS_PER_BANK; 1533 bank->gpio_chip.ngpio = ST_GPIO_PINS_PER_BANK; 1534 bank->gpio_chip.of_node = np; 1535 bank->gpio_chip.dev = dev; 1536 spin_lock_init(&bank->lock); 1537 1538 of_property_read_string(np, "st,bank-name", &range->name); 1539 bank->gpio_chip.label = range->name; 1540 1541 range->id = bank_num; 1542 range->pin_base = range->base = range->id * ST_GPIO_PINS_PER_BANK; 1543 range->npins = bank->gpio_chip.ngpio; 1544 range->gc = &bank->gpio_chip; 1545 err = gpiochip_add(&bank->gpio_chip); 1546 if (err) { 1547 dev_err(dev, "Failed to add gpiochip(%d)!\n", bank_num); 1548 return err; 1549 } 1550 dev_info(dev, "%s bank added.\n", range->name); 1551 1552 /** 1553 * GPIO bank can have one of the two possible types of 1554 * interrupt-wirings. 1555 * 1556 * First type is via irqmux, single interrupt is used by multiple 1557 * gpio banks. This reduces number of overall interrupts numbers 1558 * required. All these banks belong to a single pincontroller. 1559 * _________ 1560 * | |----> [gpio-bank (n) ] 1561 * | |----> [gpio-bank (n + 1)] 1562 * [irqN]-- | irq-mux |----> [gpio-bank (n + 2)] 1563 * | |----> [gpio-bank (... )] 1564 * |_________|----> [gpio-bank (n + 7)] 1565 * 1566 * Second type has a dedicated interrupt per each gpio bank. 1567 * 1568 * [irqN]----> [gpio-bank (n)] 1569 */ 1570 1571 if (of_irq_to_resource(np, 0, &irq_res)) { 1572 gpio_irq = irq_res.start; 1573 gpiochip_set_chained_irqchip(&bank->gpio_chip, &st_gpio_irqchip, 1574 gpio_irq, st_gpio_irq_handler); 1575 } 1576 1577 if (info->irqmux_base || gpio_irq > 0) { 1578 err = gpiochip_irqchip_add(&bank->gpio_chip, &st_gpio_irqchip, 1579 0, handle_simple_irq, 1580 IRQ_TYPE_LEVEL_LOW); 1581 if (err) { 1582 gpiochip_remove(&bank->gpio_chip); 1583 dev_info(dev, "could not add irqchip\n"); 1584 return err; 1585 } 1586 } else { 1587 dev_info(dev, "No IRQ support for %s bank\n", np->full_name); 1588 } 1589 1590 return 0; 1591 } 1592 1593 static const struct of_device_id st_pctl_of_match[] = { 1594 { .compatible = "st,stih415-sbc-pinctrl", .data = &stih415_sbc_data }, 1595 { .compatible = "st,stih415-rear-pinctrl", .data = &stih415_rear_data }, 1596 { .compatible = "st,stih415-left-pinctrl", .data = &stih415_left_data }, 1597 { .compatible = "st,stih415-right-pinctrl", 1598 .data = &stih415_right_data }, 1599 { .compatible = "st,stih415-front-pinctrl", 1600 .data = &stih415_front_data }, 1601 { .compatible = "st,stih416-sbc-pinctrl", .data = &stih416_data}, 1602 { .compatible = "st,stih416-front-pinctrl", .data = &stih416_data}, 1603 { .compatible = "st,stih416-rear-pinctrl", .data = &stih416_data}, 1604 { .compatible = "st,stih416-fvdp-fe-pinctrl", .data = &stih416_data}, 1605 { .compatible = "st,stih416-fvdp-lite-pinctrl", .data = &stih416_data}, 1606 { .compatible = "st,stih407-sbc-pinctrl", .data = &stih416_data}, 1607 { .compatible = "st,stih407-front-pinctrl", .data = &stih416_data}, 1608 { .compatible = "st,stih407-rear-pinctrl", .data = &stih416_data}, 1609 { .compatible = "st,stih407-flash-pinctrl", .data = &stih407_flashdata}, 1610 { /* sentinel */ } 1611 }; 1612 1613 static int st_pctl_probe_dt(struct platform_device *pdev, 1614 struct pinctrl_desc *pctl_desc, struct st_pinctrl *info) 1615 { 1616 int ret = 0; 1617 int i = 0, j = 0, k = 0, bank; 1618 struct pinctrl_pin_desc *pdesc; 1619 struct device_node *np = pdev->dev.of_node; 1620 struct device_node *child; 1621 int grp_index = 0; 1622 int irq = 0; 1623 struct resource *res; 1624 1625 st_pctl_dt_child_count(info, np); 1626 if (!info->nbanks) { 1627 dev_err(&pdev->dev, "you need atleast one gpio bank\n"); 1628 return -EINVAL; 1629 } 1630 1631 dev_info(&pdev->dev, "nbanks = %d\n", info->nbanks); 1632 dev_info(&pdev->dev, "nfunctions = %d\n", info->nfunctions); 1633 dev_info(&pdev->dev, "ngroups = %d\n", info->ngroups); 1634 1635 info->functions = devm_kzalloc(&pdev->dev, 1636 info->nfunctions * sizeof(*info->functions), GFP_KERNEL); 1637 1638 info->groups = devm_kzalloc(&pdev->dev, 1639 info->ngroups * sizeof(*info->groups) , GFP_KERNEL); 1640 1641 info->banks = devm_kzalloc(&pdev->dev, 1642 info->nbanks * sizeof(*info->banks), GFP_KERNEL); 1643 1644 if (!info->functions || !info->groups || !info->banks) 1645 return -ENOMEM; 1646 1647 info->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg"); 1648 if (IS_ERR(info->regmap)) { 1649 dev_err(info->dev, "No syscfg phandle specified\n"); 1650 return PTR_ERR(info->regmap); 1651 } 1652 info->data = of_match_node(st_pctl_of_match, np)->data; 1653 1654 irq = platform_get_irq(pdev, 0); 1655 1656 if (irq > 0) { 1657 res = platform_get_resource_byname(pdev, 1658 IORESOURCE_MEM, "irqmux"); 1659 info->irqmux_base = devm_ioremap_resource(&pdev->dev, res); 1660 1661 if (IS_ERR(info->irqmux_base)) 1662 return PTR_ERR(info->irqmux_base); 1663 1664 irq_set_chained_handler(irq, st_gpio_irqmux_handler); 1665 irq_set_handler_data(irq, info); 1666 1667 } 1668 1669 pctl_desc->npins = info->nbanks * ST_GPIO_PINS_PER_BANK; 1670 pdesc = devm_kzalloc(&pdev->dev, 1671 sizeof(*pdesc) * pctl_desc->npins, GFP_KERNEL); 1672 if (!pdesc) 1673 return -ENOMEM; 1674 1675 pctl_desc->pins = pdesc; 1676 1677 bank = 0; 1678 for_each_child_of_node(np, child) { 1679 if (of_property_read_bool(child, "gpio-controller")) { 1680 const char *bank_name = NULL; 1681 ret = st_gpiolib_register_bank(info, bank, child); 1682 if (ret) 1683 return ret; 1684 1685 k = info->banks[bank].range.pin_base; 1686 bank_name = info->banks[bank].range.name; 1687 for (j = 0; j < ST_GPIO_PINS_PER_BANK; j++, k++) { 1688 pdesc->number = k; 1689 pdesc->name = kasprintf(GFP_KERNEL, "%s[%d]", 1690 bank_name, j); 1691 pdesc++; 1692 } 1693 st_parse_syscfgs(info, bank, child); 1694 bank++; 1695 } else { 1696 ret = st_pctl_parse_functions(child, info, 1697 i++, &grp_index); 1698 if (ret) { 1699 dev_err(&pdev->dev, "No functions found.\n"); 1700 return ret; 1701 } 1702 } 1703 } 1704 1705 return 0; 1706 } 1707 1708 static int st_pctl_probe(struct platform_device *pdev) 1709 { 1710 struct st_pinctrl *info; 1711 struct pinctrl_desc *pctl_desc; 1712 int ret, i; 1713 1714 if (!pdev->dev.of_node) { 1715 dev_err(&pdev->dev, "device node not found.\n"); 1716 return -EINVAL; 1717 } 1718 1719 pctl_desc = devm_kzalloc(&pdev->dev, sizeof(*pctl_desc), GFP_KERNEL); 1720 if (!pctl_desc) 1721 return -ENOMEM; 1722 1723 info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL); 1724 if (!info) 1725 return -ENOMEM; 1726 1727 info->dev = &pdev->dev; 1728 platform_set_drvdata(pdev, info); 1729 ret = st_pctl_probe_dt(pdev, pctl_desc, info); 1730 if (ret) 1731 return ret; 1732 1733 pctl_desc->owner = THIS_MODULE; 1734 pctl_desc->pctlops = &st_pctlops; 1735 pctl_desc->pmxops = &st_pmxops; 1736 pctl_desc->confops = &st_confops; 1737 pctl_desc->name = dev_name(&pdev->dev); 1738 1739 info->pctl = pinctrl_register(pctl_desc, &pdev->dev, info); 1740 if (!info->pctl) { 1741 dev_err(&pdev->dev, "Failed pinctrl registration\n"); 1742 return -EINVAL; 1743 } 1744 1745 for (i = 0; i < info->nbanks; i++) 1746 pinctrl_add_gpio_range(info->pctl, &info->banks[i].range); 1747 1748 return 0; 1749 } 1750 1751 static struct platform_driver st_pctl_driver = { 1752 .driver = { 1753 .name = "st-pinctrl", 1754 .of_match_table = st_pctl_of_match, 1755 }, 1756 .probe = st_pctl_probe, 1757 }; 1758 1759 static int __init st_pctl_init(void) 1760 { 1761 return platform_driver_register(&st_pctl_driver); 1762 } 1763 arch_initcall(st_pctl_init); 1764