1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
4 * Authors:
5 * Srinivas Kandagatla <srinivas.kandagatla@st.com>
6 */
7
8 #include <linux/err.h>
9 #include <linux/gpio/driver.h>
10 #include <linux/init.h>
11 #include <linux/io.h>
12 #include <linux/mfd/syscon.h>
13 #include <linux/module.h>
14 #include <linux/of.h>
15 #include <linux/of_address.h>
16 #include <linux/of_irq.h>
17 #include <linux/platform_device.h>
18 #include <linux/regmap.h>
19 #include <linux/seq_file.h>
20 #include <linux/slab.h>
21 #include <linux/string_helpers.h>
22
23 #include <linux/pinctrl/consumer.h>
24 #include <linux/pinctrl/pinconf.h>
25 #include <linux/pinctrl/pinctrl.h>
26 #include <linux/pinctrl/pinmux.h>
27
28 #include "core.h"
29
30 /* PIO Block registers */
31 /* PIO output */
32 #define REG_PIO_POUT 0x00
33 /* Set bits of POUT */
34 #define REG_PIO_SET_POUT 0x04
35 /* Clear bits of POUT */
36 #define REG_PIO_CLR_POUT 0x08
37 /* PIO input */
38 #define REG_PIO_PIN 0x10
39 /* PIO configuration */
40 #define REG_PIO_PC(n) (0x20 + (n) * 0x10)
41 /* Set bits of PC[2:0] */
42 #define REG_PIO_SET_PC(n) (0x24 + (n) * 0x10)
43 /* Clear bits of PC[2:0] */
44 #define REG_PIO_CLR_PC(n) (0x28 + (n) * 0x10)
45 /* PIO input comparison */
46 #define REG_PIO_PCOMP 0x50
47 /* Set bits of PCOMP */
48 #define REG_PIO_SET_PCOMP 0x54
49 /* Clear bits of PCOMP */
50 #define REG_PIO_CLR_PCOMP 0x58
51 /* PIO input comparison mask */
52 #define REG_PIO_PMASK 0x60
53 /* Set bits of PMASK */
54 #define REG_PIO_SET_PMASK 0x64
55 /* Clear bits of PMASK */
56 #define REG_PIO_CLR_PMASK 0x68
57
58 #define ST_GPIO_DIRECTION_BIDIR 0x1
59 #define ST_GPIO_DIRECTION_OUT 0x2
60 #define ST_GPIO_DIRECTION_IN 0x4
61
62 /*
63 * Packed style retime configuration.
64 * There are two registers cfg0 and cfg1 in this style for each bank.
65 * Each field in this register is 8 bit corresponding to 8 pins in the bank.
66 */
67 #define RT_P_CFGS_PER_BANK 2
68 #define RT_P_CFG0_CLK1NOTCLK0_FIELD(reg) REG_FIELD(reg, 0, 7)
69 #define RT_P_CFG0_DELAY_0_FIELD(reg) REG_FIELD(reg, 16, 23)
70 #define RT_P_CFG0_DELAY_1_FIELD(reg) REG_FIELD(reg, 24, 31)
71 #define RT_P_CFG1_INVERTCLK_FIELD(reg) REG_FIELD(reg, 0, 7)
72 #define RT_P_CFG1_RETIME_FIELD(reg) REG_FIELD(reg, 8, 15)
73 #define RT_P_CFG1_CLKNOTDATA_FIELD(reg) REG_FIELD(reg, 16, 23)
74 #define RT_P_CFG1_DOUBLE_EDGE_FIELD(reg) REG_FIELD(reg, 24, 31)
75
76 /*
77 * Dedicated style retime Configuration register
78 * each register is dedicated per pin.
79 */
80 #define RT_D_CFGS_PER_BANK 8
81 #define RT_D_CFG_CLK_SHIFT 0
82 #define RT_D_CFG_CLK_MASK (0x3 << 0)
83 #define RT_D_CFG_CLKNOTDATA_SHIFT 2
84 #define RT_D_CFG_CLKNOTDATA_MASK BIT(2)
85 #define RT_D_CFG_DELAY_SHIFT 3
86 #define RT_D_CFG_DELAY_MASK (0xf << 3)
87 #define RT_D_CFG_DELAY_INNOTOUT_SHIFT 7
88 #define RT_D_CFG_DELAY_INNOTOUT_MASK BIT(7)
89 #define RT_D_CFG_DOUBLE_EDGE_SHIFT 8
90 #define RT_D_CFG_DOUBLE_EDGE_MASK BIT(8)
91 #define RT_D_CFG_INVERTCLK_SHIFT 9
92 #define RT_D_CFG_INVERTCLK_MASK BIT(9)
93 #define RT_D_CFG_RETIME_SHIFT 10
94 #define RT_D_CFG_RETIME_MASK BIT(10)
95
96 /*
97 * Pinconf is represented in an opaque unsigned long variable.
98 * Below is the bit allocation details for each possible configuration.
99 * All the bit fields can be encapsulated into four variables
100 * (direction, retime-type, retime-clk, retime-delay)
101 *
102 * +----------------+
103 *[31:28]| reserved-3 |
104 * +----------------+-------------
105 *[27] | oe | |
106 * +----------------+ v
107 *[26] | pu | [Direction ]
108 * +----------------+ ^
109 *[25] | od | |
110 * +----------------+-------------
111 *[24] | reserved-2 |
112 * +----------------+-------------
113 *[23] | retime | |
114 * +----------------+ |
115 *[22] | retime-invclk | |
116 * +----------------+ v
117 *[21] |retime-clknotdat| [Retime-type ]
118 * +----------------+ ^
119 *[20] | retime-de | |
120 * +----------------+-------------
121 *[19:18]| retime-clk |------>[Retime-Clk ]
122 * +----------------+
123 *[17:16]| reserved-1 |
124 * +----------------+
125 *[15..0]| retime-delay |------>[Retime Delay]
126 * +----------------+
127 */
128
129 #define ST_PINCONF_UNPACK(conf, param)\
130 ((conf >> ST_PINCONF_ ##param ##_SHIFT) \
131 & ST_PINCONF_ ##param ##_MASK)
132
133 #define ST_PINCONF_PACK(conf, val, param) (conf |=\
134 ((val & ST_PINCONF_ ##param ##_MASK) << \
135 ST_PINCONF_ ##param ##_SHIFT))
136
137 /* Output enable */
138 #define ST_PINCONF_OE_MASK 0x1
139 #define ST_PINCONF_OE_SHIFT 27
140 #define ST_PINCONF_OE BIT(27)
141 #define ST_PINCONF_UNPACK_OE(conf) ST_PINCONF_UNPACK(conf, OE)
142 #define ST_PINCONF_PACK_OE(conf) ST_PINCONF_PACK(conf, 1, OE)
143
144 /* Pull Up */
145 #define ST_PINCONF_PU_MASK 0x1
146 #define ST_PINCONF_PU_SHIFT 26
147 #define ST_PINCONF_PU BIT(26)
148 #define ST_PINCONF_UNPACK_PU(conf) ST_PINCONF_UNPACK(conf, PU)
149 #define ST_PINCONF_PACK_PU(conf) ST_PINCONF_PACK(conf, 1, PU)
150
151 /* Open Drain */
152 #define ST_PINCONF_OD_MASK 0x1
153 #define ST_PINCONF_OD_SHIFT 25
154 #define ST_PINCONF_OD BIT(25)
155 #define ST_PINCONF_UNPACK_OD(conf) ST_PINCONF_UNPACK(conf, OD)
156 #define ST_PINCONF_PACK_OD(conf) ST_PINCONF_PACK(conf, 1, OD)
157
158 #define ST_PINCONF_RT_MASK 0x1
159 #define ST_PINCONF_RT_SHIFT 23
160 #define ST_PINCONF_RT BIT(23)
161 #define ST_PINCONF_UNPACK_RT(conf) ST_PINCONF_UNPACK(conf, RT)
162 #define ST_PINCONF_PACK_RT(conf) ST_PINCONF_PACK(conf, 1, RT)
163
164 #define ST_PINCONF_RT_INVERTCLK_MASK 0x1
165 #define ST_PINCONF_RT_INVERTCLK_SHIFT 22
166 #define ST_PINCONF_RT_INVERTCLK BIT(22)
167 #define ST_PINCONF_UNPACK_RT_INVERTCLK(conf) \
168 ST_PINCONF_UNPACK(conf, RT_INVERTCLK)
169 #define ST_PINCONF_PACK_RT_INVERTCLK(conf) \
170 ST_PINCONF_PACK(conf, 1, RT_INVERTCLK)
171
172 #define ST_PINCONF_RT_CLKNOTDATA_MASK 0x1
173 #define ST_PINCONF_RT_CLKNOTDATA_SHIFT 21
174 #define ST_PINCONF_RT_CLKNOTDATA BIT(21)
175 #define ST_PINCONF_UNPACK_RT_CLKNOTDATA(conf) \
176 ST_PINCONF_UNPACK(conf, RT_CLKNOTDATA)
177 #define ST_PINCONF_PACK_RT_CLKNOTDATA(conf) \
178 ST_PINCONF_PACK(conf, 1, RT_CLKNOTDATA)
179
180 #define ST_PINCONF_RT_DOUBLE_EDGE_MASK 0x1
181 #define ST_PINCONF_RT_DOUBLE_EDGE_SHIFT 20
182 #define ST_PINCONF_RT_DOUBLE_EDGE BIT(20)
183 #define ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(conf) \
184 ST_PINCONF_UNPACK(conf, RT_DOUBLE_EDGE)
185 #define ST_PINCONF_PACK_RT_DOUBLE_EDGE(conf) \
186 ST_PINCONF_PACK(conf, 1, RT_DOUBLE_EDGE)
187
188 #define ST_PINCONF_RT_CLK_MASK 0x3
189 #define ST_PINCONF_RT_CLK_SHIFT 18
190 #define ST_PINCONF_RT_CLK BIT(18)
191 #define ST_PINCONF_UNPACK_RT_CLK(conf) ST_PINCONF_UNPACK(conf, RT_CLK)
192 #define ST_PINCONF_PACK_RT_CLK(conf, val) ST_PINCONF_PACK(conf, val, RT_CLK)
193
194 /* RETIME_DELAY in Pico Secs */
195 #define ST_PINCONF_RT_DELAY_MASK 0xffff
196 #define ST_PINCONF_RT_DELAY_SHIFT 0
197 #define ST_PINCONF_UNPACK_RT_DELAY(conf) ST_PINCONF_UNPACK(conf, RT_DELAY)
198 #define ST_PINCONF_PACK_RT_DELAY(conf, val) \
199 ST_PINCONF_PACK(conf, val, RT_DELAY)
200
201 #define ST_GPIO_PINS_PER_BANK (8)
202 #define OF_GPIO_ARGS_MIN (4)
203 #define OF_RT_ARGS_MIN (2)
204
205 #define gpio_range_to_bank(chip) \
206 container_of(chip, struct st_gpio_bank, range)
207
208 #define pc_to_bank(pc) \
209 container_of(pc, struct st_gpio_bank, pc)
210
211 enum st_retime_style {
212 st_retime_style_none,
213 st_retime_style_packed,
214 st_retime_style_dedicated,
215 };
216
217 struct st_retime_dedicated {
218 struct regmap_field *rt[ST_GPIO_PINS_PER_BANK];
219 };
220
221 struct st_retime_packed {
222 struct regmap_field *clk1notclk0;
223 struct regmap_field *delay_0;
224 struct regmap_field *delay_1;
225 struct regmap_field *invertclk;
226 struct regmap_field *retime;
227 struct regmap_field *clknotdata;
228 struct regmap_field *double_edge;
229 };
230
231 struct st_pio_control {
232 u32 rt_pin_mask;
233 struct regmap_field *alt, *oe, *pu, *od;
234 /* retiming */
235 union {
236 struct st_retime_packed rt_p;
237 struct st_retime_dedicated rt_d;
238 } rt;
239 };
240
241 struct st_pctl_data {
242 const enum st_retime_style rt_style;
243 const unsigned int *input_delays;
244 const int ninput_delays;
245 const unsigned int *output_delays;
246 const int noutput_delays;
247 /* register offset information */
248 const int alt, oe, pu, od, rt;
249 };
250
251 struct st_pinconf {
252 int pin;
253 const char *name;
254 unsigned long config;
255 int altfunc;
256 };
257
258 struct st_pmx_func {
259 const char *name;
260 const char **groups;
261 unsigned ngroups;
262 };
263
264 struct st_pctl_group {
265 const char *name;
266 unsigned int *pins;
267 unsigned npins;
268 struct st_pinconf *pin_conf;
269 };
270
271 /*
272 * Edge triggers are not supported at hardware level, it is supported by
273 * software by exploiting the level trigger support in hardware.
274 * Software uses a virtual register (EDGE_CONF) for edge trigger configuration
275 * of each gpio pin in a GPIO bank.
276 *
277 * Each bank has a 32 bit EDGE_CONF register which is divided in to 8 parts of
278 * 4-bits. Each 4-bit space is allocated for each pin in a gpio bank.
279 *
280 * bit allocation per pin is:
281 * Bits: [0 - 3] | [4 - 7] [8 - 11] ... ... ... ... [ 28 - 31]
282 * --------------------------------------------------------
283 * | pin-0 | pin-2 | pin-3 | ... ... ... ... | pin -7 |
284 * --------------------------------------------------------
285 *
286 * A pin can have one of following the values in its edge configuration field.
287 *
288 * ------- ----------------------------
289 * [0-3] - Description
290 * ------- ----------------------------
291 * 0000 - No edge IRQ.
292 * 0001 - Falling edge IRQ.
293 * 0010 - Rising edge IRQ.
294 * 0011 - Rising and Falling edge IRQ.
295 * ------- ----------------------------
296 */
297
298 #define ST_IRQ_EDGE_CONF_BITS_PER_PIN 4
299 #define ST_IRQ_EDGE_MASK 0xf
300 #define ST_IRQ_EDGE_FALLING BIT(0)
301 #define ST_IRQ_EDGE_RISING BIT(1)
302 #define ST_IRQ_EDGE_BOTH (BIT(0) | BIT(1))
303
304 #define ST_IRQ_RISING_EDGE_CONF(pin) \
305 (ST_IRQ_EDGE_RISING << (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN))
306
307 #define ST_IRQ_FALLING_EDGE_CONF(pin) \
308 (ST_IRQ_EDGE_FALLING << (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN))
309
310 #define ST_IRQ_BOTH_EDGE_CONF(pin) \
311 (ST_IRQ_EDGE_BOTH << (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN))
312
313 #define ST_IRQ_EDGE_CONF(conf, pin) \
314 (conf >> (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN) & ST_IRQ_EDGE_MASK)
315
316 struct st_gpio_bank {
317 struct gpio_chip gpio_chip;
318 struct pinctrl_gpio_range range;
319 void __iomem *base;
320 struct st_pio_control pc;
321 unsigned long irq_edge_conf;
322 spinlock_t lock;
323 };
324
325 struct st_pinctrl {
326 struct device *dev;
327 struct pinctrl_dev *pctl;
328 struct st_gpio_bank *banks;
329 int nbanks;
330 struct st_pmx_func *functions;
331 int nfunctions;
332 struct st_pctl_group *groups;
333 int ngroups;
334 struct regmap *regmap;
335 const struct st_pctl_data *data;
336 void __iomem *irqmux_base;
337 };
338
339 /* SOC specific data */
340
341 static const unsigned int stih407_delays[] = {0, 300, 500, 750, 1000, 1250,
342 1500, 1750, 2000, 2250, 2500, 2750, 3000, 3250 };
343
344 static const struct st_pctl_data stih407_data = {
345 .rt_style = st_retime_style_dedicated,
346 .input_delays = stih407_delays,
347 .ninput_delays = ARRAY_SIZE(stih407_delays),
348 .output_delays = stih407_delays,
349 .noutput_delays = ARRAY_SIZE(stih407_delays),
350 .alt = 0, .oe = 40, .pu = 50, .od = 60, .rt = 100,
351 };
352
353 static const struct st_pctl_data stih407_flashdata = {
354 .rt_style = st_retime_style_none,
355 .input_delays = stih407_delays,
356 .ninput_delays = ARRAY_SIZE(stih407_delays),
357 .output_delays = stih407_delays,
358 .noutput_delays = ARRAY_SIZE(stih407_delays),
359 .alt = 0,
360 .oe = -1, /* Not Available */
361 .pu = -1, /* Not Available */
362 .od = 60,
363 .rt = 100,
364 };
365
st_get_pio_control(struct pinctrl_dev * pctldev,int pin)366 static struct st_pio_control *st_get_pio_control(
367 struct pinctrl_dev *pctldev, int pin)
368 {
369 struct pinctrl_gpio_range *range =
370 pinctrl_find_gpio_range_from_pin(pctldev, pin);
371 struct st_gpio_bank *bank = gpio_range_to_bank(range);
372
373 return &bank->pc;
374 }
375
376 /* Low level functions.. */
st_gpio_bank(int gpio)377 static inline int st_gpio_bank(int gpio)
378 {
379 return gpio/ST_GPIO_PINS_PER_BANK;
380 }
381
st_gpio_pin(int gpio)382 static inline int st_gpio_pin(int gpio)
383 {
384 return gpio%ST_GPIO_PINS_PER_BANK;
385 }
386
st_pinconf_set_config(struct st_pio_control * pc,int pin,unsigned long config)387 static void st_pinconf_set_config(struct st_pio_control *pc,
388 int pin, unsigned long config)
389 {
390 struct regmap_field *output_enable = pc->oe;
391 struct regmap_field *pull_up = pc->pu;
392 struct regmap_field *open_drain = pc->od;
393 unsigned int oe_value, pu_value, od_value;
394 unsigned long mask = BIT(pin);
395
396 if (output_enable) {
397 regmap_field_read(output_enable, &oe_value);
398 oe_value &= ~mask;
399 if (config & ST_PINCONF_OE)
400 oe_value |= mask;
401 regmap_field_write(output_enable, oe_value);
402 }
403
404 if (pull_up) {
405 regmap_field_read(pull_up, &pu_value);
406 pu_value &= ~mask;
407 if (config & ST_PINCONF_PU)
408 pu_value |= mask;
409 regmap_field_write(pull_up, pu_value);
410 }
411
412 if (open_drain) {
413 regmap_field_read(open_drain, &od_value);
414 od_value &= ~mask;
415 if (config & ST_PINCONF_OD)
416 od_value |= mask;
417 regmap_field_write(open_drain, od_value);
418 }
419 }
420
st_pctl_set_function(struct st_pio_control * pc,int pin_id,int function)421 static void st_pctl_set_function(struct st_pio_control *pc,
422 int pin_id, int function)
423 {
424 struct regmap_field *alt = pc->alt;
425 unsigned int val;
426 int pin = st_gpio_pin(pin_id);
427 int offset = pin * 4;
428
429 if (!alt)
430 return;
431
432 regmap_field_read(alt, &val);
433 val &= ~(0xf << offset);
434 val |= function << offset;
435 regmap_field_write(alt, val);
436 }
437
st_pctl_get_pin_function(struct st_pio_control * pc,int pin)438 static unsigned int st_pctl_get_pin_function(struct st_pio_control *pc, int pin)
439 {
440 struct regmap_field *alt = pc->alt;
441 unsigned int val;
442 int offset = pin * 4;
443
444 if (!alt)
445 return 0;
446
447 regmap_field_read(alt, &val);
448
449 return (val >> offset) & 0xf;
450 }
451
st_pinconf_delay_to_bit(unsigned int delay,const struct st_pctl_data * data,unsigned long config)452 static unsigned long st_pinconf_delay_to_bit(unsigned int delay,
453 const struct st_pctl_data *data, unsigned long config)
454 {
455 const unsigned int *delay_times;
456 int num_delay_times, i, closest_index = -1;
457 unsigned int closest_divergence = UINT_MAX;
458
459 if (ST_PINCONF_UNPACK_OE(config)) {
460 delay_times = data->output_delays;
461 num_delay_times = data->noutput_delays;
462 } else {
463 delay_times = data->input_delays;
464 num_delay_times = data->ninput_delays;
465 }
466
467 for (i = 0; i < num_delay_times; i++) {
468 unsigned int divergence = abs(delay - delay_times[i]);
469
470 if (divergence == 0)
471 return i;
472
473 if (divergence < closest_divergence) {
474 closest_divergence = divergence;
475 closest_index = i;
476 }
477 }
478
479 pr_warn("Attempt to set delay %d, closest available %d\n",
480 delay, delay_times[closest_index]);
481
482 return closest_index;
483 }
484
st_pinconf_bit_to_delay(unsigned int index,const struct st_pctl_data * data,unsigned long output)485 static unsigned long st_pinconf_bit_to_delay(unsigned int index,
486 const struct st_pctl_data *data, unsigned long output)
487 {
488 const unsigned int *delay_times;
489 int num_delay_times;
490
491 if (output) {
492 delay_times = data->output_delays;
493 num_delay_times = data->noutput_delays;
494 } else {
495 delay_times = data->input_delays;
496 num_delay_times = data->ninput_delays;
497 }
498
499 if (index < num_delay_times) {
500 return delay_times[index];
501 } else {
502 pr_warn("Delay not found in/out delay list\n");
503 return 0;
504 }
505 }
506
st_regmap_field_bit_set_clear_pin(struct regmap_field * field,int enable,int pin)507 static void st_regmap_field_bit_set_clear_pin(struct regmap_field *field,
508 int enable, int pin)
509 {
510 unsigned int val = 0;
511
512 regmap_field_read(field, &val);
513 if (enable)
514 val |= BIT(pin);
515 else
516 val &= ~BIT(pin);
517 regmap_field_write(field, val);
518 }
519
st_pinconf_set_retime_packed(struct st_pinctrl * info,struct st_pio_control * pc,unsigned long config,int pin)520 static void st_pinconf_set_retime_packed(struct st_pinctrl *info,
521 struct st_pio_control *pc, unsigned long config, int pin)
522 {
523 const struct st_pctl_data *data = info->data;
524 struct st_retime_packed *rt_p = &pc->rt.rt_p;
525 unsigned int delay;
526
527 st_regmap_field_bit_set_clear_pin(rt_p->clk1notclk0,
528 ST_PINCONF_UNPACK_RT_CLK(config), pin);
529
530 st_regmap_field_bit_set_clear_pin(rt_p->clknotdata,
531 ST_PINCONF_UNPACK_RT_CLKNOTDATA(config), pin);
532
533 st_regmap_field_bit_set_clear_pin(rt_p->double_edge,
534 ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(config), pin);
535
536 st_regmap_field_bit_set_clear_pin(rt_p->invertclk,
537 ST_PINCONF_UNPACK_RT_INVERTCLK(config), pin);
538
539 st_regmap_field_bit_set_clear_pin(rt_p->retime,
540 ST_PINCONF_UNPACK_RT(config), pin);
541
542 delay = st_pinconf_delay_to_bit(ST_PINCONF_UNPACK_RT_DELAY(config),
543 data, config);
544 /* 2 bit delay, lsb */
545 st_regmap_field_bit_set_clear_pin(rt_p->delay_0, delay & 0x1, pin);
546 /* 2 bit delay, msb */
547 st_regmap_field_bit_set_clear_pin(rt_p->delay_1, delay & 0x2, pin);
548 }
549
st_pinconf_set_retime_dedicated(struct st_pinctrl * info,struct st_pio_control * pc,unsigned long config,int pin)550 static void st_pinconf_set_retime_dedicated(struct st_pinctrl *info,
551 struct st_pio_control *pc, unsigned long config, int pin)
552 {
553 int input = ST_PINCONF_UNPACK_OE(config) ? 0 : 1;
554 int clk = ST_PINCONF_UNPACK_RT_CLK(config);
555 int clknotdata = ST_PINCONF_UNPACK_RT_CLKNOTDATA(config);
556 int double_edge = ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(config);
557 int invertclk = ST_PINCONF_UNPACK_RT_INVERTCLK(config);
558 int retime = ST_PINCONF_UNPACK_RT(config);
559
560 unsigned long delay = st_pinconf_delay_to_bit(
561 ST_PINCONF_UNPACK_RT_DELAY(config),
562 info->data, config);
563 struct st_retime_dedicated *rt_d = &pc->rt.rt_d;
564
565 unsigned long retime_config =
566 ((clk) << RT_D_CFG_CLK_SHIFT) |
567 ((delay) << RT_D_CFG_DELAY_SHIFT) |
568 ((input) << RT_D_CFG_DELAY_INNOTOUT_SHIFT) |
569 ((retime) << RT_D_CFG_RETIME_SHIFT) |
570 ((clknotdata) << RT_D_CFG_CLKNOTDATA_SHIFT) |
571 ((invertclk) << RT_D_CFG_INVERTCLK_SHIFT) |
572 ((double_edge) << RT_D_CFG_DOUBLE_EDGE_SHIFT);
573
574 regmap_field_write(rt_d->rt[pin], retime_config);
575 }
576
st_pinconf_get_direction(struct st_pio_control * pc,int pin,unsigned long * config)577 static void st_pinconf_get_direction(struct st_pio_control *pc,
578 int pin, unsigned long *config)
579 {
580 unsigned int oe_value, pu_value, od_value;
581
582 if (pc->oe) {
583 regmap_field_read(pc->oe, &oe_value);
584 if (oe_value & BIT(pin))
585 ST_PINCONF_PACK_OE(*config);
586 }
587
588 if (pc->pu) {
589 regmap_field_read(pc->pu, &pu_value);
590 if (pu_value & BIT(pin))
591 ST_PINCONF_PACK_PU(*config);
592 }
593
594 if (pc->od) {
595 regmap_field_read(pc->od, &od_value);
596 if (od_value & BIT(pin))
597 ST_PINCONF_PACK_OD(*config);
598 }
599 }
600
st_pinconf_get_retime_packed(struct st_pinctrl * info,struct st_pio_control * pc,int pin,unsigned long * config)601 static int st_pinconf_get_retime_packed(struct st_pinctrl *info,
602 struct st_pio_control *pc, int pin, unsigned long *config)
603 {
604 const struct st_pctl_data *data = info->data;
605 struct st_retime_packed *rt_p = &pc->rt.rt_p;
606 unsigned int delay_bits, delay, delay0, delay1, val;
607 int output = ST_PINCONF_UNPACK_OE(*config);
608
609 if (!regmap_field_read(rt_p->retime, &val) && (val & BIT(pin)))
610 ST_PINCONF_PACK_RT(*config);
611
612 if (!regmap_field_read(rt_p->clk1notclk0, &val) && (val & BIT(pin)))
613 ST_PINCONF_PACK_RT_CLK(*config, 1);
614
615 if (!regmap_field_read(rt_p->clknotdata, &val) && (val & BIT(pin)))
616 ST_PINCONF_PACK_RT_CLKNOTDATA(*config);
617
618 if (!regmap_field_read(rt_p->double_edge, &val) && (val & BIT(pin)))
619 ST_PINCONF_PACK_RT_DOUBLE_EDGE(*config);
620
621 if (!regmap_field_read(rt_p->invertclk, &val) && (val & BIT(pin)))
622 ST_PINCONF_PACK_RT_INVERTCLK(*config);
623
624 regmap_field_read(rt_p->delay_0, &delay0);
625 regmap_field_read(rt_p->delay_1, &delay1);
626 delay_bits = (((delay1 & BIT(pin)) ? 1 : 0) << 1) |
627 (((delay0 & BIT(pin)) ? 1 : 0));
628 delay = st_pinconf_bit_to_delay(delay_bits, data, output);
629 ST_PINCONF_PACK_RT_DELAY(*config, delay);
630
631 return 0;
632 }
633
st_pinconf_get_retime_dedicated(struct st_pinctrl * info,struct st_pio_control * pc,int pin,unsigned long * config)634 static int st_pinconf_get_retime_dedicated(struct st_pinctrl *info,
635 struct st_pio_control *pc, int pin, unsigned long *config)
636 {
637 unsigned int value;
638 unsigned long delay_bits, delay, rt_clk;
639 int output = ST_PINCONF_UNPACK_OE(*config);
640 struct st_retime_dedicated *rt_d = &pc->rt.rt_d;
641
642 regmap_field_read(rt_d->rt[pin], &value);
643
644 rt_clk = (value & RT_D_CFG_CLK_MASK) >> RT_D_CFG_CLK_SHIFT;
645 ST_PINCONF_PACK_RT_CLK(*config, rt_clk);
646
647 delay_bits = (value & RT_D_CFG_DELAY_MASK) >> RT_D_CFG_DELAY_SHIFT;
648 delay = st_pinconf_bit_to_delay(delay_bits, info->data, output);
649 ST_PINCONF_PACK_RT_DELAY(*config, delay);
650
651 if (value & RT_D_CFG_CLKNOTDATA_MASK)
652 ST_PINCONF_PACK_RT_CLKNOTDATA(*config);
653
654 if (value & RT_D_CFG_DOUBLE_EDGE_MASK)
655 ST_PINCONF_PACK_RT_DOUBLE_EDGE(*config);
656
657 if (value & RT_D_CFG_INVERTCLK_MASK)
658 ST_PINCONF_PACK_RT_INVERTCLK(*config);
659
660 if (value & RT_D_CFG_RETIME_MASK)
661 ST_PINCONF_PACK_RT(*config);
662
663 return 0;
664 }
665
666 /* GPIO related functions */
667
__st_gpio_set(struct st_gpio_bank * bank,unsigned offset,int value)668 static inline void __st_gpio_set(struct st_gpio_bank *bank,
669 unsigned offset, int value)
670 {
671 if (value)
672 writel(BIT(offset), bank->base + REG_PIO_SET_POUT);
673 else
674 writel(BIT(offset), bank->base + REG_PIO_CLR_POUT);
675 }
676
st_gpio_direction(struct st_gpio_bank * bank,unsigned int gpio,unsigned int direction)677 static void st_gpio_direction(struct st_gpio_bank *bank,
678 unsigned int gpio, unsigned int direction)
679 {
680 int offset = st_gpio_pin(gpio);
681 int i = 0;
682 /**
683 * There are three configuration registers (PIOn_PC0, PIOn_PC1
684 * and PIOn_PC2) for each port. These are used to configure the
685 * PIO port pins. Each pin can be configured as an input, output,
686 * bidirectional, or alternative function pin. Three bits, one bit
687 * from each of the three registers, configure the corresponding bit of
688 * the port. Valid bit settings is:
689 *
690 * PC2 PC1 PC0 Direction.
691 * 0 0 0 [Input Weak pull-up]
692 * 0 0 or 1 1 [Bidirection]
693 * 0 1 0 [Output]
694 * 1 0 0 [Input]
695 *
696 * PIOn_SET_PC and PIOn_CLR_PC registers are used to set and clear bits
697 * individually.
698 */
699 for (i = 0; i <= 2; i++) {
700 if (direction & BIT(i))
701 writel(BIT(offset), bank->base + REG_PIO_SET_PC(i));
702 else
703 writel(BIT(offset), bank->base + REG_PIO_CLR_PC(i));
704 }
705 }
706
st_gpio_get(struct gpio_chip * chip,unsigned offset)707 static int st_gpio_get(struct gpio_chip *chip, unsigned offset)
708 {
709 struct st_gpio_bank *bank = gpiochip_get_data(chip);
710
711 return !!(readl(bank->base + REG_PIO_PIN) & BIT(offset));
712 }
713
st_gpio_set(struct gpio_chip * chip,unsigned offset,int value)714 static void st_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
715 {
716 struct st_gpio_bank *bank = gpiochip_get_data(chip);
717 __st_gpio_set(bank, offset, value);
718 }
719
st_gpio_direction_input(struct gpio_chip * chip,unsigned offset)720 static int st_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
721 {
722 pinctrl_gpio_direction_input(chip->base + offset);
723
724 return 0;
725 }
726
st_gpio_direction_output(struct gpio_chip * chip,unsigned offset,int value)727 static int st_gpio_direction_output(struct gpio_chip *chip,
728 unsigned offset, int value)
729 {
730 struct st_gpio_bank *bank = gpiochip_get_data(chip);
731
732 __st_gpio_set(bank, offset, value);
733 pinctrl_gpio_direction_output(chip->base + offset);
734
735 return 0;
736 }
737
st_gpio_get_direction(struct gpio_chip * chip,unsigned offset)738 static int st_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
739 {
740 struct st_gpio_bank *bank = gpiochip_get_data(chip);
741 struct st_pio_control pc = bank->pc;
742 unsigned long config;
743 unsigned int direction = 0;
744 unsigned int function;
745 unsigned int value;
746 int i = 0;
747
748 /* Alternate function direction is handled by Pinctrl */
749 function = st_pctl_get_pin_function(&pc, offset);
750 if (function) {
751 st_pinconf_get_direction(&pc, offset, &config);
752 if (ST_PINCONF_UNPACK_OE(config))
753 return GPIO_LINE_DIRECTION_OUT;
754
755 return GPIO_LINE_DIRECTION_IN;
756 }
757
758 /*
759 * GPIO direction is handled differently
760 * - See st_gpio_direction() above for an explanation
761 */
762 for (i = 0; i <= 2; i++) {
763 value = readl(bank->base + REG_PIO_PC(i));
764 direction |= ((value >> offset) & 0x1) << i;
765 }
766
767 if (direction == ST_GPIO_DIRECTION_IN)
768 return GPIO_LINE_DIRECTION_IN;
769
770 return GPIO_LINE_DIRECTION_OUT;
771 }
772
773 /* Pinctrl Groups */
st_pctl_get_groups_count(struct pinctrl_dev * pctldev)774 static int st_pctl_get_groups_count(struct pinctrl_dev *pctldev)
775 {
776 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
777
778 return info->ngroups;
779 }
780
st_pctl_get_group_name(struct pinctrl_dev * pctldev,unsigned selector)781 static const char *st_pctl_get_group_name(struct pinctrl_dev *pctldev,
782 unsigned selector)
783 {
784 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
785
786 return info->groups[selector].name;
787 }
788
st_pctl_get_group_pins(struct pinctrl_dev * pctldev,unsigned selector,const unsigned ** pins,unsigned * npins)789 static int st_pctl_get_group_pins(struct pinctrl_dev *pctldev,
790 unsigned selector, const unsigned **pins, unsigned *npins)
791 {
792 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
793
794 if (selector >= info->ngroups)
795 return -EINVAL;
796
797 *pins = info->groups[selector].pins;
798 *npins = info->groups[selector].npins;
799
800 return 0;
801 }
802
st_pctl_find_group_by_name(const struct st_pinctrl * info,const char * name)803 static inline const struct st_pctl_group *st_pctl_find_group_by_name(
804 const struct st_pinctrl *info, const char *name)
805 {
806 int i;
807
808 for (i = 0; i < info->ngroups; i++) {
809 if (!strcmp(info->groups[i].name, name))
810 return &info->groups[i];
811 }
812
813 return NULL;
814 }
815
st_pctl_dt_node_to_map(struct pinctrl_dev * pctldev,struct device_node * np,struct pinctrl_map ** map,unsigned * num_maps)816 static int st_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
817 struct device_node *np, struct pinctrl_map **map, unsigned *num_maps)
818 {
819 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
820 const struct st_pctl_group *grp;
821 struct device *dev = info->dev;
822 struct pinctrl_map *new_map;
823 struct device_node *parent;
824 int map_num, i;
825
826 grp = st_pctl_find_group_by_name(info, np->name);
827 if (!grp) {
828 dev_err(dev, "unable to find group for node %pOFn\n", np);
829 return -EINVAL;
830 }
831
832 map_num = grp->npins + 1;
833 new_map = devm_kcalloc(dev, map_num, sizeof(*new_map), GFP_KERNEL);
834 if (!new_map)
835 return -ENOMEM;
836
837 parent = of_get_parent(np);
838 if (!parent) {
839 devm_kfree(dev, new_map);
840 return -EINVAL;
841 }
842
843 *map = new_map;
844 *num_maps = map_num;
845 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
846 new_map[0].data.mux.function = parent->name;
847 new_map[0].data.mux.group = np->name;
848 of_node_put(parent);
849
850 /* create config map per pin */
851 new_map++;
852 for (i = 0; i < grp->npins; i++) {
853 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
854 new_map[i].data.configs.group_or_pin =
855 pin_get_name(pctldev, grp->pins[i]);
856 new_map[i].data.configs.configs = &grp->pin_conf[i].config;
857 new_map[i].data.configs.num_configs = 1;
858 }
859 dev_info(dev, "maps: function %s group %s num %d\n",
860 (*map)->data.mux.function, grp->name, map_num);
861
862 return 0;
863 }
864
st_pctl_dt_free_map(struct pinctrl_dev * pctldev,struct pinctrl_map * map,unsigned num_maps)865 static void st_pctl_dt_free_map(struct pinctrl_dev *pctldev,
866 struct pinctrl_map *map, unsigned num_maps)
867 {
868 }
869
870 static const struct pinctrl_ops st_pctlops = {
871 .get_groups_count = st_pctl_get_groups_count,
872 .get_group_pins = st_pctl_get_group_pins,
873 .get_group_name = st_pctl_get_group_name,
874 .dt_node_to_map = st_pctl_dt_node_to_map,
875 .dt_free_map = st_pctl_dt_free_map,
876 };
877
878 /* Pinmux */
st_pmx_get_funcs_count(struct pinctrl_dev * pctldev)879 static int st_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
880 {
881 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
882
883 return info->nfunctions;
884 }
885
st_pmx_get_fname(struct pinctrl_dev * pctldev,unsigned selector)886 static const char *st_pmx_get_fname(struct pinctrl_dev *pctldev,
887 unsigned selector)
888 {
889 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
890
891 return info->functions[selector].name;
892 }
893
st_pmx_get_groups(struct pinctrl_dev * pctldev,unsigned selector,const char * const ** grps,unsigned * const ngrps)894 static int st_pmx_get_groups(struct pinctrl_dev *pctldev,
895 unsigned selector, const char * const **grps, unsigned * const ngrps)
896 {
897 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
898 *grps = info->functions[selector].groups;
899 *ngrps = info->functions[selector].ngroups;
900
901 return 0;
902 }
903
st_pmx_set_mux(struct pinctrl_dev * pctldev,unsigned fselector,unsigned group)904 static int st_pmx_set_mux(struct pinctrl_dev *pctldev, unsigned fselector,
905 unsigned group)
906 {
907 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
908 struct st_pinconf *conf = info->groups[group].pin_conf;
909 struct st_pio_control *pc;
910 int i;
911
912 for (i = 0; i < info->groups[group].npins; i++) {
913 pc = st_get_pio_control(pctldev, conf[i].pin);
914 st_pctl_set_function(pc, conf[i].pin, conf[i].altfunc);
915 }
916
917 return 0;
918 }
919
st_pmx_set_gpio_direction(struct pinctrl_dev * pctldev,struct pinctrl_gpio_range * range,unsigned gpio,bool input)920 static int st_pmx_set_gpio_direction(struct pinctrl_dev *pctldev,
921 struct pinctrl_gpio_range *range, unsigned gpio,
922 bool input)
923 {
924 struct st_gpio_bank *bank = gpio_range_to_bank(range);
925 /*
926 * When a PIO bank is used in its primary function mode (altfunc = 0)
927 * Output Enable (OE), Open Drain(OD), and Pull Up (PU)
928 * for the primary PIO functions are driven by the related PIO block
929 */
930 st_pctl_set_function(&bank->pc, gpio, 0);
931 st_gpio_direction(bank, gpio, input ?
932 ST_GPIO_DIRECTION_IN : ST_GPIO_DIRECTION_OUT);
933
934 return 0;
935 }
936
937 static const struct pinmux_ops st_pmxops = {
938 .get_functions_count = st_pmx_get_funcs_count,
939 .get_function_name = st_pmx_get_fname,
940 .get_function_groups = st_pmx_get_groups,
941 .set_mux = st_pmx_set_mux,
942 .gpio_set_direction = st_pmx_set_gpio_direction,
943 .strict = true,
944 };
945
946 /* Pinconf */
st_pinconf_get_retime(struct st_pinctrl * info,struct st_pio_control * pc,int pin,unsigned long * config)947 static void st_pinconf_get_retime(struct st_pinctrl *info,
948 struct st_pio_control *pc, int pin, unsigned long *config)
949 {
950 if (info->data->rt_style == st_retime_style_packed)
951 st_pinconf_get_retime_packed(info, pc, pin, config);
952 else if (info->data->rt_style == st_retime_style_dedicated)
953 if ((BIT(pin) & pc->rt_pin_mask))
954 st_pinconf_get_retime_dedicated(info, pc,
955 pin, config);
956 }
957
st_pinconf_set_retime(struct st_pinctrl * info,struct st_pio_control * pc,int pin,unsigned long config)958 static void st_pinconf_set_retime(struct st_pinctrl *info,
959 struct st_pio_control *pc, int pin, unsigned long config)
960 {
961 if (info->data->rt_style == st_retime_style_packed)
962 st_pinconf_set_retime_packed(info, pc, config, pin);
963 else if (info->data->rt_style == st_retime_style_dedicated)
964 if ((BIT(pin) & pc->rt_pin_mask))
965 st_pinconf_set_retime_dedicated(info, pc,
966 config, pin);
967 }
968
st_pinconf_set(struct pinctrl_dev * pctldev,unsigned pin_id,unsigned long * configs,unsigned num_configs)969 static int st_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin_id,
970 unsigned long *configs, unsigned num_configs)
971 {
972 int pin = st_gpio_pin(pin_id);
973 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
974 struct st_pio_control *pc = st_get_pio_control(pctldev, pin_id);
975 int i;
976
977 for (i = 0; i < num_configs; i++) {
978 st_pinconf_set_config(pc, pin, configs[i]);
979 st_pinconf_set_retime(info, pc, pin, configs[i]);
980 } /* for each config */
981
982 return 0;
983 }
984
st_pinconf_get(struct pinctrl_dev * pctldev,unsigned pin_id,unsigned long * config)985 static int st_pinconf_get(struct pinctrl_dev *pctldev,
986 unsigned pin_id, unsigned long *config)
987 {
988 int pin = st_gpio_pin(pin_id);
989 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
990 struct st_pio_control *pc = st_get_pio_control(pctldev, pin_id);
991
992 *config = 0;
993 st_pinconf_get_direction(pc, pin, config);
994 st_pinconf_get_retime(info, pc, pin, config);
995
996 return 0;
997 }
998
st_pinconf_dbg_show(struct pinctrl_dev * pctldev,struct seq_file * s,unsigned pin_id)999 static void st_pinconf_dbg_show(struct pinctrl_dev *pctldev,
1000 struct seq_file *s, unsigned pin_id)
1001 {
1002 struct st_pio_control *pc;
1003 unsigned long config;
1004 unsigned int function;
1005 int offset = st_gpio_pin(pin_id);
1006 char f[16];
1007 int oe;
1008
1009 mutex_unlock(&pctldev->mutex);
1010 pc = st_get_pio_control(pctldev, pin_id);
1011 st_pinconf_get(pctldev, pin_id, &config);
1012 mutex_lock(&pctldev->mutex);
1013
1014 function = st_pctl_get_pin_function(pc, offset);
1015 if (function)
1016 snprintf(f, 10, "Alt Fn %u", function);
1017 else
1018 snprintf(f, 5, "GPIO");
1019
1020 oe = st_gpio_get_direction(&pc_to_bank(pc)->gpio_chip, offset);
1021 seq_printf(s, "[OE:%d,PU:%ld,OD:%ld]\t%s\n"
1022 "\t\t[retime:%ld,invclk:%ld,clknotdat:%ld,"
1023 "de:%ld,rt-clk:%ld,rt-delay:%ld]",
1024 (oe == GPIO_LINE_DIRECTION_OUT),
1025 ST_PINCONF_UNPACK_PU(config),
1026 ST_PINCONF_UNPACK_OD(config),
1027 f,
1028 ST_PINCONF_UNPACK_RT(config),
1029 ST_PINCONF_UNPACK_RT_INVERTCLK(config),
1030 ST_PINCONF_UNPACK_RT_CLKNOTDATA(config),
1031 ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(config),
1032 ST_PINCONF_UNPACK_RT_CLK(config),
1033 ST_PINCONF_UNPACK_RT_DELAY(config));
1034 }
1035
1036 static const struct pinconf_ops st_confops = {
1037 .pin_config_get = st_pinconf_get,
1038 .pin_config_set = st_pinconf_set,
1039 .pin_config_dbg_show = st_pinconf_dbg_show,
1040 };
1041
st_pctl_dt_child_count(struct st_pinctrl * info,struct device_node * np)1042 static void st_pctl_dt_child_count(struct st_pinctrl *info,
1043 struct device_node *np)
1044 {
1045 struct device_node *child;
1046 for_each_child_of_node(np, child) {
1047 if (of_property_read_bool(child, "gpio-controller")) {
1048 info->nbanks++;
1049 } else {
1050 info->nfunctions++;
1051 info->ngroups += of_get_child_count(child);
1052 }
1053 }
1054 }
1055
st_pctl_dt_setup_retime_packed(struct st_pinctrl * info,int bank,struct st_pio_control * pc)1056 static int st_pctl_dt_setup_retime_packed(struct st_pinctrl *info,
1057 int bank, struct st_pio_control *pc)
1058 {
1059 struct device *dev = info->dev;
1060 struct regmap *rm = info->regmap;
1061 const struct st_pctl_data *data = info->data;
1062 /* 2 registers per bank */
1063 int reg = (data->rt + bank * RT_P_CFGS_PER_BANK) * 4;
1064 struct st_retime_packed *rt_p = &pc->rt.rt_p;
1065 /* cfg0 */
1066 struct reg_field clk1notclk0 = RT_P_CFG0_CLK1NOTCLK0_FIELD(reg);
1067 struct reg_field delay_0 = RT_P_CFG0_DELAY_0_FIELD(reg);
1068 struct reg_field delay_1 = RT_P_CFG0_DELAY_1_FIELD(reg);
1069 /* cfg1 */
1070 struct reg_field invertclk = RT_P_CFG1_INVERTCLK_FIELD(reg + 4);
1071 struct reg_field retime = RT_P_CFG1_RETIME_FIELD(reg + 4);
1072 struct reg_field clknotdata = RT_P_CFG1_CLKNOTDATA_FIELD(reg + 4);
1073 struct reg_field double_edge = RT_P_CFG1_DOUBLE_EDGE_FIELD(reg + 4);
1074
1075 rt_p->clk1notclk0 = devm_regmap_field_alloc(dev, rm, clk1notclk0);
1076 rt_p->delay_0 = devm_regmap_field_alloc(dev, rm, delay_0);
1077 rt_p->delay_1 = devm_regmap_field_alloc(dev, rm, delay_1);
1078 rt_p->invertclk = devm_regmap_field_alloc(dev, rm, invertclk);
1079 rt_p->retime = devm_regmap_field_alloc(dev, rm, retime);
1080 rt_p->clknotdata = devm_regmap_field_alloc(dev, rm, clknotdata);
1081 rt_p->double_edge = devm_regmap_field_alloc(dev, rm, double_edge);
1082
1083 if (IS_ERR(rt_p->clk1notclk0) || IS_ERR(rt_p->delay_0) ||
1084 IS_ERR(rt_p->delay_1) || IS_ERR(rt_p->invertclk) ||
1085 IS_ERR(rt_p->retime) || IS_ERR(rt_p->clknotdata) ||
1086 IS_ERR(rt_p->double_edge))
1087 return -EINVAL;
1088
1089 return 0;
1090 }
1091
st_pctl_dt_setup_retime_dedicated(struct st_pinctrl * info,int bank,struct st_pio_control * pc)1092 static int st_pctl_dt_setup_retime_dedicated(struct st_pinctrl *info,
1093 int bank, struct st_pio_control *pc)
1094 {
1095 struct device *dev = info->dev;
1096 struct regmap *rm = info->regmap;
1097 const struct st_pctl_data *data = info->data;
1098 /* 8 registers per bank */
1099 int reg_offset = (data->rt + bank * RT_D_CFGS_PER_BANK) * 4;
1100 struct st_retime_dedicated *rt_d = &pc->rt.rt_d;
1101 unsigned int j;
1102 u32 pin_mask = pc->rt_pin_mask;
1103
1104 for (j = 0; j < RT_D_CFGS_PER_BANK; j++) {
1105 if (BIT(j) & pin_mask) {
1106 struct reg_field reg = REG_FIELD(reg_offset, 0, 31);
1107 rt_d->rt[j] = devm_regmap_field_alloc(dev, rm, reg);
1108 if (IS_ERR(rt_d->rt[j]))
1109 return -EINVAL;
1110 reg_offset += 4;
1111 }
1112 }
1113 return 0;
1114 }
1115
st_pctl_dt_setup_retime(struct st_pinctrl * info,int bank,struct st_pio_control * pc)1116 static int st_pctl_dt_setup_retime(struct st_pinctrl *info,
1117 int bank, struct st_pio_control *pc)
1118 {
1119 const struct st_pctl_data *data = info->data;
1120 if (data->rt_style == st_retime_style_packed)
1121 return st_pctl_dt_setup_retime_packed(info, bank, pc);
1122 else if (data->rt_style == st_retime_style_dedicated)
1123 return st_pctl_dt_setup_retime_dedicated(info, bank, pc);
1124
1125 return -EINVAL;
1126 }
1127
1128
st_pc_get_value(struct device * dev,struct regmap * regmap,int bank,int data,int lsb,int msb)1129 static struct regmap_field *st_pc_get_value(struct device *dev,
1130 struct regmap *regmap, int bank,
1131 int data, int lsb, int msb)
1132 {
1133 struct reg_field reg = REG_FIELD((data + bank) * 4, lsb, msb);
1134
1135 if (data < 0)
1136 return NULL;
1137
1138 return devm_regmap_field_alloc(dev, regmap, reg);
1139 }
1140
st_parse_syscfgs(struct st_pinctrl * info,int bank,struct device_node * np)1141 static void st_parse_syscfgs(struct st_pinctrl *info, int bank,
1142 struct device_node *np)
1143 {
1144 const struct st_pctl_data *data = info->data;
1145 /**
1146 * For a given shared register like OE/PU/OD, there are 8 bits per bank
1147 * 0:7 belongs to bank0, 8:15 belongs to bank1 ...
1148 * So each register is shared across 4 banks.
1149 */
1150 int lsb = (bank%4) * ST_GPIO_PINS_PER_BANK;
1151 int msb = lsb + ST_GPIO_PINS_PER_BANK - 1;
1152 struct st_pio_control *pc = &info->banks[bank].pc;
1153 struct device *dev = info->dev;
1154 struct regmap *regmap = info->regmap;
1155
1156 pc->alt = st_pc_get_value(dev, regmap, bank, data->alt, 0, 31);
1157 pc->oe = st_pc_get_value(dev, regmap, bank/4, data->oe, lsb, msb);
1158 pc->pu = st_pc_get_value(dev, regmap, bank/4, data->pu, lsb, msb);
1159 pc->od = st_pc_get_value(dev, regmap, bank/4, data->od, lsb, msb);
1160
1161 /* retime avaiable for all pins by default */
1162 pc->rt_pin_mask = 0xff;
1163 of_property_read_u32(np, "st,retime-pin-mask", &pc->rt_pin_mask);
1164 st_pctl_dt_setup_retime(info, bank, pc);
1165
1166 return;
1167 }
1168
st_pctl_dt_calculate_pin(struct st_pinctrl * info,phandle bank,unsigned int offset)1169 static int st_pctl_dt_calculate_pin(struct st_pinctrl *info,
1170 phandle bank, unsigned int offset)
1171 {
1172 struct device_node *np;
1173 struct gpio_chip *chip;
1174 int retval = -EINVAL;
1175 int i;
1176
1177 np = of_find_node_by_phandle(bank);
1178 if (!np)
1179 return -EINVAL;
1180
1181 for (i = 0; i < info->nbanks; i++) {
1182 chip = &info->banks[i].gpio_chip;
1183 if (chip->fwnode == of_fwnode_handle(np)) {
1184 if (offset < chip->ngpio)
1185 retval = chip->base + offset;
1186 break;
1187 }
1188 }
1189
1190 of_node_put(np);
1191 return retval;
1192 }
1193
1194 /*
1195 * Each pin is represented in of the below forms.
1196 * <bank offset mux direction rt_type rt_delay rt_clk>
1197 */
st_pctl_dt_parse_groups(struct device_node * np,struct st_pctl_group * grp,struct st_pinctrl * info,int idx)1198 static int st_pctl_dt_parse_groups(struct device_node *np,
1199 struct st_pctl_group *grp, struct st_pinctrl *info, int idx)
1200 {
1201 /* bank pad direction val altfunction */
1202 const __be32 *list;
1203 struct property *pp;
1204 struct device *dev = info->dev;
1205 struct st_pinconf *conf;
1206 struct device_node *pins;
1207 phandle bank;
1208 unsigned int offset;
1209 int i = 0, npins = 0, nr_props, ret = 0;
1210
1211 pins = of_get_child_by_name(np, "st,pins");
1212 if (!pins)
1213 return -ENODATA;
1214
1215 for_each_property_of_node(pins, pp) {
1216 /* Skip those we do not want to proceed */
1217 if (!strcmp(pp->name, "name"))
1218 continue;
1219
1220 if (pp->length / sizeof(__be32) >= OF_GPIO_ARGS_MIN) {
1221 npins++;
1222 } else {
1223 pr_warn("Invalid st,pins in %pOFn node\n", np);
1224 ret = -EINVAL;
1225 goto out_put_node;
1226 }
1227 }
1228
1229 grp->npins = npins;
1230 grp->name = np->name;
1231 grp->pins = devm_kcalloc(dev, npins, sizeof(*grp->pins), GFP_KERNEL);
1232 grp->pin_conf = devm_kcalloc(dev, npins, sizeof(*grp->pin_conf), GFP_KERNEL);
1233
1234 if (!grp->pins || !grp->pin_conf) {
1235 ret = -ENOMEM;
1236 goto out_put_node;
1237 }
1238
1239 /* <bank offset mux direction rt_type rt_delay rt_clk> */
1240 for_each_property_of_node(pins, pp) {
1241 if (!strcmp(pp->name, "name"))
1242 continue;
1243 nr_props = pp->length/sizeof(u32);
1244 list = pp->value;
1245 conf = &grp->pin_conf[i];
1246
1247 /* bank & offset */
1248 bank = be32_to_cpup(list++);
1249 offset = be32_to_cpup(list++);
1250 conf->pin = st_pctl_dt_calculate_pin(info, bank, offset);
1251 conf->name = pp->name;
1252 grp->pins[i] = conf->pin;
1253 /* mux */
1254 conf->altfunc = be32_to_cpup(list++);
1255 conf->config = 0;
1256 /* direction */
1257 conf->config |= be32_to_cpup(list++);
1258 /* rt_type rt_delay rt_clk */
1259 if (nr_props >= OF_GPIO_ARGS_MIN + OF_RT_ARGS_MIN) {
1260 /* rt_type */
1261 conf->config |= be32_to_cpup(list++);
1262 /* rt_delay */
1263 conf->config |= be32_to_cpup(list++);
1264 /* rt_clk */
1265 if (nr_props > OF_GPIO_ARGS_MIN + OF_RT_ARGS_MIN)
1266 conf->config |= be32_to_cpup(list++);
1267 }
1268 i++;
1269 }
1270
1271 out_put_node:
1272 of_node_put(pins);
1273
1274 return ret;
1275 }
1276
st_pctl_parse_functions(struct device_node * np,struct st_pinctrl * info,u32 index,int * grp_index)1277 static int st_pctl_parse_functions(struct device_node *np,
1278 struct st_pinctrl *info, u32 index, int *grp_index)
1279 {
1280 struct device *dev = info->dev;
1281 struct device_node *child;
1282 struct st_pmx_func *func;
1283 struct st_pctl_group *grp;
1284 int ret, i;
1285
1286 func = &info->functions[index];
1287 func->name = np->name;
1288 func->ngroups = of_get_child_count(np);
1289 if (func->ngroups == 0)
1290 return dev_err_probe(dev, -EINVAL, "No groups defined\n");
1291 func->groups = devm_kcalloc(dev, func->ngroups, sizeof(*func->groups), GFP_KERNEL);
1292 if (!func->groups)
1293 return -ENOMEM;
1294
1295 i = 0;
1296 for_each_child_of_node(np, child) {
1297 func->groups[i] = child->name;
1298 grp = &info->groups[*grp_index];
1299 *grp_index += 1;
1300 ret = st_pctl_dt_parse_groups(child, grp, info, i++);
1301 if (ret) {
1302 of_node_put(child);
1303 return ret;
1304 }
1305 }
1306 dev_info(dev, "Function[%d\t name:%s,\tgroups:%d]\n", index, func->name, func->ngroups);
1307
1308 return 0;
1309 }
1310
st_gpio_irq_mask(struct irq_data * d)1311 static void st_gpio_irq_mask(struct irq_data *d)
1312 {
1313 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1314 struct st_gpio_bank *bank = gpiochip_get_data(gc);
1315
1316 writel(BIT(irqd_to_hwirq(d)), bank->base + REG_PIO_CLR_PMASK);
1317 gpiochip_disable_irq(gc, irqd_to_hwirq(d));
1318 }
1319
st_gpio_irq_unmask(struct irq_data * d)1320 static void st_gpio_irq_unmask(struct irq_data *d)
1321 {
1322 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1323 struct st_gpio_bank *bank = gpiochip_get_data(gc);
1324
1325 gpiochip_enable_irq(gc, irqd_to_hwirq(d));
1326 writel(BIT(irqd_to_hwirq(d)), bank->base + REG_PIO_SET_PMASK);
1327 }
1328
st_gpio_irq_request_resources(struct irq_data * d)1329 static int st_gpio_irq_request_resources(struct irq_data *d)
1330 {
1331 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1332
1333 st_gpio_direction_input(gc, d->hwirq);
1334
1335 return gpiochip_reqres_irq(gc, d->hwirq);
1336 }
1337
st_gpio_irq_release_resources(struct irq_data * d)1338 static void st_gpio_irq_release_resources(struct irq_data *d)
1339 {
1340 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1341
1342 gpiochip_relres_irq(gc, d->hwirq);
1343 }
1344
st_gpio_irq_set_type(struct irq_data * d,unsigned type)1345 static int st_gpio_irq_set_type(struct irq_data *d, unsigned type)
1346 {
1347 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1348 struct st_gpio_bank *bank = gpiochip_get_data(gc);
1349 unsigned long flags;
1350 int comp, pin = d->hwirq;
1351 u32 val;
1352 u32 pin_edge_conf = 0;
1353
1354 switch (type) {
1355 case IRQ_TYPE_LEVEL_HIGH:
1356 comp = 0;
1357 break;
1358 case IRQ_TYPE_EDGE_FALLING:
1359 comp = 0;
1360 pin_edge_conf = ST_IRQ_FALLING_EDGE_CONF(pin);
1361 break;
1362 case IRQ_TYPE_LEVEL_LOW:
1363 comp = 1;
1364 break;
1365 case IRQ_TYPE_EDGE_RISING:
1366 comp = 1;
1367 pin_edge_conf = ST_IRQ_RISING_EDGE_CONF(pin);
1368 break;
1369 case IRQ_TYPE_EDGE_BOTH:
1370 comp = st_gpio_get(&bank->gpio_chip, pin);
1371 pin_edge_conf = ST_IRQ_BOTH_EDGE_CONF(pin);
1372 break;
1373 default:
1374 return -EINVAL;
1375 }
1376
1377 spin_lock_irqsave(&bank->lock, flags);
1378 bank->irq_edge_conf &= ~(ST_IRQ_EDGE_MASK << (
1379 pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN));
1380 bank->irq_edge_conf |= pin_edge_conf;
1381 spin_unlock_irqrestore(&bank->lock, flags);
1382
1383 val = readl(bank->base + REG_PIO_PCOMP);
1384 val &= ~BIT(pin);
1385 val |= (comp << pin);
1386 writel(val, bank->base + REG_PIO_PCOMP);
1387
1388 return 0;
1389 }
1390
1391 /*
1392 * As edge triggers are not supported at hardware level, it is supported by
1393 * software by exploiting the level trigger support in hardware.
1394 *
1395 * Steps for detection raising edge interrupt in software.
1396 *
1397 * Step 1: CONFIGURE pin to detect level LOW interrupts.
1398 *
1399 * Step 2: DETECT level LOW interrupt and in irqmux/gpio bank interrupt handler,
1400 * if the value of pin is low, then CONFIGURE pin for level HIGH interrupt.
1401 * IGNORE calling the actual interrupt handler for the pin at this stage.
1402 *
1403 * Step 3: DETECT level HIGH interrupt and in irqmux/gpio-bank interrupt handler
1404 * if the value of pin is HIGH, CONFIGURE pin for level LOW interrupt and then
1405 * DISPATCH the interrupt to the interrupt handler of the pin.
1406 *
1407 * step-1 ________ __________
1408 * | | step - 3
1409 * | |
1410 * step -2 |_____|
1411 *
1412 * falling edge is also detected int the same way.
1413 *
1414 */
__gpio_irq_handler(struct st_gpio_bank * bank)1415 static void __gpio_irq_handler(struct st_gpio_bank *bank)
1416 {
1417 unsigned long port_in, port_mask, port_comp, active_irqs;
1418 unsigned long bank_edge_mask, flags;
1419 int n, val, ecfg;
1420
1421 spin_lock_irqsave(&bank->lock, flags);
1422 bank_edge_mask = bank->irq_edge_conf;
1423 spin_unlock_irqrestore(&bank->lock, flags);
1424
1425 for (;;) {
1426 port_in = readl(bank->base + REG_PIO_PIN);
1427 port_comp = readl(bank->base + REG_PIO_PCOMP);
1428 port_mask = readl(bank->base + REG_PIO_PMASK);
1429
1430 active_irqs = (port_in ^ port_comp) & port_mask;
1431
1432 if (active_irqs == 0)
1433 break;
1434
1435 for_each_set_bit(n, &active_irqs, BITS_PER_LONG) {
1436 /* check if we are detecting fake edges ... */
1437 ecfg = ST_IRQ_EDGE_CONF(bank_edge_mask, n);
1438
1439 if (ecfg) {
1440 /* edge detection. */
1441 val = st_gpio_get(&bank->gpio_chip, n);
1442
1443 writel(BIT(n),
1444 val ? bank->base + REG_PIO_SET_PCOMP :
1445 bank->base + REG_PIO_CLR_PCOMP);
1446
1447 if (ecfg != ST_IRQ_EDGE_BOTH &&
1448 !((ecfg & ST_IRQ_EDGE_FALLING) ^ val))
1449 continue;
1450 }
1451
1452 generic_handle_domain_irq(bank->gpio_chip.irq.domain, n);
1453 }
1454 }
1455 }
1456
st_gpio_irq_handler(struct irq_desc * desc)1457 static void st_gpio_irq_handler(struct irq_desc *desc)
1458 {
1459 /* interrupt dedicated per bank */
1460 struct irq_chip *chip = irq_desc_get_chip(desc);
1461 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
1462 struct st_gpio_bank *bank = gpiochip_get_data(gc);
1463
1464 chained_irq_enter(chip, desc);
1465 __gpio_irq_handler(bank);
1466 chained_irq_exit(chip, desc);
1467 }
1468
st_gpio_irqmux_handler(struct irq_desc * desc)1469 static void st_gpio_irqmux_handler(struct irq_desc *desc)
1470 {
1471 struct irq_chip *chip = irq_desc_get_chip(desc);
1472 struct st_pinctrl *info = irq_desc_get_handler_data(desc);
1473 unsigned long status;
1474 int n;
1475
1476 chained_irq_enter(chip, desc);
1477
1478 status = readl(info->irqmux_base);
1479
1480 for_each_set_bit(n, &status, info->nbanks)
1481 __gpio_irq_handler(&info->banks[n]);
1482
1483 chained_irq_exit(chip, desc);
1484 }
1485
1486 static const struct gpio_chip st_gpio_template = {
1487 .request = gpiochip_generic_request,
1488 .free = gpiochip_generic_free,
1489 .get = st_gpio_get,
1490 .set = st_gpio_set,
1491 .direction_input = st_gpio_direction_input,
1492 .direction_output = st_gpio_direction_output,
1493 .get_direction = st_gpio_get_direction,
1494 .ngpio = ST_GPIO_PINS_PER_BANK,
1495 };
1496
1497 static const struct irq_chip st_gpio_irqchip = {
1498 .name = "GPIO",
1499 .irq_request_resources = st_gpio_irq_request_resources,
1500 .irq_release_resources = st_gpio_irq_release_resources,
1501 .irq_disable = st_gpio_irq_mask,
1502 .irq_mask = st_gpio_irq_mask,
1503 .irq_unmask = st_gpio_irq_unmask,
1504 .irq_set_type = st_gpio_irq_set_type,
1505 .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_IMMUTABLE,
1506 };
1507
st_gpiolib_register_bank(struct st_pinctrl * info,int bank_nr,struct device_node * np)1508 static int st_gpiolib_register_bank(struct st_pinctrl *info,
1509 int bank_nr, struct device_node *np)
1510 {
1511 struct st_gpio_bank *bank = &info->banks[bank_nr];
1512 struct pinctrl_gpio_range *range = &bank->range;
1513 struct device *dev = info->dev;
1514 int bank_num = of_alias_get_id(np, "gpio");
1515 struct resource res, irq_res;
1516 int err;
1517
1518 if (of_address_to_resource(np, 0, &res))
1519 return -ENODEV;
1520
1521 bank->base = devm_ioremap_resource(dev, &res);
1522 if (IS_ERR(bank->base))
1523 return PTR_ERR(bank->base);
1524
1525 bank->gpio_chip = st_gpio_template;
1526 bank->gpio_chip.base = bank_num * ST_GPIO_PINS_PER_BANK;
1527 bank->gpio_chip.ngpio = ST_GPIO_PINS_PER_BANK;
1528 bank->gpio_chip.fwnode = of_fwnode_handle(np);
1529 bank->gpio_chip.parent = dev;
1530 spin_lock_init(&bank->lock);
1531
1532 of_property_read_string(np, "st,bank-name", &range->name);
1533 bank->gpio_chip.label = range->name;
1534
1535 range->id = bank_num;
1536 range->pin_base = range->base = range->id * ST_GPIO_PINS_PER_BANK;
1537 range->npins = bank->gpio_chip.ngpio;
1538 range->gc = &bank->gpio_chip;
1539
1540 /**
1541 * GPIO bank can have one of the two possible types of
1542 * interrupt-wirings.
1543 *
1544 * First type is via irqmux, single interrupt is used by multiple
1545 * gpio banks. This reduces number of overall interrupts numbers
1546 * required. All these banks belong to a single pincontroller.
1547 * _________
1548 * | |----> [gpio-bank (n) ]
1549 * | |----> [gpio-bank (n + 1)]
1550 * [irqN]-- | irq-mux |----> [gpio-bank (n + 2)]
1551 * | |----> [gpio-bank (... )]
1552 * |_________|----> [gpio-bank (n + 7)]
1553 *
1554 * Second type has a dedicated interrupt per each gpio bank.
1555 *
1556 * [irqN]----> [gpio-bank (n)]
1557 */
1558
1559 if (of_irq_to_resource(np, 0, &irq_res) > 0) {
1560 struct gpio_irq_chip *girq;
1561 int gpio_irq = irq_res.start;
1562
1563 /* This is not a valid IRQ */
1564 if (gpio_irq <= 0) {
1565 dev_err(dev, "invalid IRQ for %pOF bank\n", np);
1566 goto skip_irq;
1567 }
1568 /* We need to have a mux as well */
1569 if (!info->irqmux_base) {
1570 dev_err(dev, "no irqmux for %pOF bank\n", np);
1571 goto skip_irq;
1572 }
1573
1574 girq = &bank->gpio_chip.irq;
1575 gpio_irq_chip_set_chip(girq, &st_gpio_irqchip);
1576 girq->parent_handler = st_gpio_irq_handler;
1577 girq->num_parents = 1;
1578 girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents),
1579 GFP_KERNEL);
1580 if (!girq->parents)
1581 return -ENOMEM;
1582 girq->parents[0] = gpio_irq;
1583 girq->default_type = IRQ_TYPE_NONE;
1584 girq->handler = handle_simple_irq;
1585 }
1586
1587 skip_irq:
1588 err = gpiochip_add_data(&bank->gpio_chip, bank);
1589 if (err)
1590 return dev_err_probe(dev, err, "Failed to add gpiochip(%d)!\n", bank_num);
1591 dev_info(dev, "%s bank added.\n", range->name);
1592
1593 return 0;
1594 }
1595
1596 static const struct of_device_id st_pctl_of_match[] = {
1597 { .compatible = "st,stih407-sbc-pinctrl", .data = &stih407_data},
1598 { .compatible = "st,stih407-front-pinctrl", .data = &stih407_data},
1599 { .compatible = "st,stih407-rear-pinctrl", .data = &stih407_data},
1600 { .compatible = "st,stih407-flash-pinctrl", .data = &stih407_flashdata},
1601 { /* sentinel */ }
1602 };
1603
st_pctl_probe_dt(struct platform_device * pdev,struct pinctrl_desc * pctl_desc,struct st_pinctrl * info)1604 static int st_pctl_probe_dt(struct platform_device *pdev,
1605 struct pinctrl_desc *pctl_desc, struct st_pinctrl *info)
1606 {
1607 struct device *dev = &pdev->dev;
1608 int ret = 0;
1609 int i = 0, j = 0, k = 0, bank;
1610 struct pinctrl_pin_desc *pdesc;
1611 struct device_node *np = dev->of_node;
1612 struct device_node *child;
1613 int grp_index = 0;
1614 int irq = 0;
1615
1616 st_pctl_dt_child_count(info, np);
1617 if (!info->nbanks)
1618 return dev_err_probe(dev, -EINVAL, "you need at least one gpio bank\n");
1619
1620 dev_info(dev, "nbanks = %d\n", info->nbanks);
1621 dev_info(dev, "nfunctions = %d\n", info->nfunctions);
1622 dev_info(dev, "ngroups = %d\n", info->ngroups);
1623
1624 info->functions = devm_kcalloc(dev, info->nfunctions, sizeof(*info->functions), GFP_KERNEL);
1625
1626 info->groups = devm_kcalloc(dev, info->ngroups, sizeof(*info->groups), GFP_KERNEL);
1627
1628 info->banks = devm_kcalloc(dev, info->nbanks, sizeof(*info->banks), GFP_KERNEL);
1629
1630 if (!info->functions || !info->groups || !info->banks)
1631 return -ENOMEM;
1632
1633 info->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
1634 if (IS_ERR(info->regmap))
1635 return dev_err_probe(dev, PTR_ERR(info->regmap), "No syscfg phandle specified\n");
1636 info->data = of_match_node(st_pctl_of_match, np)->data;
1637
1638 irq = platform_get_irq(pdev, 0);
1639
1640 if (irq > 0) {
1641 info->irqmux_base = devm_platform_ioremap_resource_byname(pdev, "irqmux");
1642 if (IS_ERR(info->irqmux_base))
1643 return PTR_ERR(info->irqmux_base);
1644
1645 irq_set_chained_handler_and_data(irq, st_gpio_irqmux_handler,
1646 info);
1647 }
1648
1649 pctl_desc->npins = info->nbanks * ST_GPIO_PINS_PER_BANK;
1650 pdesc = devm_kcalloc(dev, pctl_desc->npins, sizeof(*pdesc), GFP_KERNEL);
1651 if (!pdesc)
1652 return -ENOMEM;
1653
1654 pctl_desc->pins = pdesc;
1655
1656 bank = 0;
1657 for_each_child_of_node(np, child) {
1658 if (of_property_read_bool(child, "gpio-controller")) {
1659 const char *bank_name = NULL;
1660 char **pin_names;
1661
1662 ret = st_gpiolib_register_bank(info, bank, child);
1663 if (ret) {
1664 of_node_put(child);
1665 return ret;
1666 }
1667
1668 k = info->banks[bank].range.pin_base;
1669 bank_name = info->banks[bank].range.name;
1670
1671 pin_names = devm_kasprintf_strarray(dev, bank_name, ST_GPIO_PINS_PER_BANK);
1672 if (IS_ERR(pin_names)) {
1673 of_node_put(child);
1674 return PTR_ERR(pin_names);
1675 }
1676
1677 for (j = 0; j < ST_GPIO_PINS_PER_BANK; j++, k++) {
1678 pdesc->number = k;
1679 pdesc->name = pin_names[j];
1680 pdesc++;
1681 }
1682 st_parse_syscfgs(info, bank, child);
1683 bank++;
1684 } else {
1685 ret = st_pctl_parse_functions(child, info,
1686 i++, &grp_index);
1687 if (ret) {
1688 dev_err(dev, "No functions found.\n");
1689 of_node_put(child);
1690 return ret;
1691 }
1692 }
1693 }
1694
1695 return 0;
1696 }
1697
st_pctl_probe(struct platform_device * pdev)1698 static int st_pctl_probe(struct platform_device *pdev)
1699 {
1700 struct device *dev = &pdev->dev;
1701 struct st_pinctrl *info;
1702 struct pinctrl_desc *pctl_desc;
1703 int ret, i;
1704
1705 if (!dev->of_node) {
1706 dev_err(dev, "device node not found.\n");
1707 return -EINVAL;
1708 }
1709
1710 pctl_desc = devm_kzalloc(dev, sizeof(*pctl_desc), GFP_KERNEL);
1711 if (!pctl_desc)
1712 return -ENOMEM;
1713
1714 info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
1715 if (!info)
1716 return -ENOMEM;
1717
1718 info->dev = dev;
1719 platform_set_drvdata(pdev, info);
1720 ret = st_pctl_probe_dt(pdev, pctl_desc, info);
1721 if (ret)
1722 return ret;
1723
1724 pctl_desc->owner = THIS_MODULE;
1725 pctl_desc->pctlops = &st_pctlops;
1726 pctl_desc->pmxops = &st_pmxops;
1727 pctl_desc->confops = &st_confops;
1728 pctl_desc->name = dev_name(dev);
1729
1730 info->pctl = devm_pinctrl_register(dev, pctl_desc, info);
1731 if (IS_ERR(info->pctl))
1732 return dev_err_probe(dev, PTR_ERR(info->pctl), "Failed pinctrl registration\n");
1733
1734 for (i = 0; i < info->nbanks; i++)
1735 pinctrl_add_gpio_range(info->pctl, &info->banks[i].range);
1736
1737 return 0;
1738 }
1739
1740 static struct platform_driver st_pctl_driver = {
1741 .driver = {
1742 .name = "st-pinctrl",
1743 .of_match_table = st_pctl_of_match,
1744 },
1745 .probe = st_pctl_probe,
1746 };
1747
st_pctl_init(void)1748 static int __init st_pctl_init(void)
1749 {
1750 return platform_driver_register(&st_pctl_driver);
1751 }
1752 arch_initcall(st_pctl_init);
1753