1 /*
2  * Generic device tree based pinctrl driver for one register per pin
3  * type pinmux controllers
4  *
5  * Copyright (C) 2012 Texas Instruments, Inc.
6  *
7  * This file is licensed under the terms of the GNU General Public
8  * License version 2. This program is licensed "as is" without any
9  * warranty of any kind, whether express or implied.
10  */
11 
12 #include <linux/init.h>
13 #include <linux/module.h>
14 #include <linux/io.h>
15 #include <linux/slab.h>
16 #include <linux/err.h>
17 #include <linux/list.h>
18 #include <linux/interrupt.h>
19 #include <linux/irqchip/chained_irq.h>
20 #include <linux/of.h>
21 #include <linux/of_device.h>
22 #include <linux/of_address.h>
23 #include <linux/of_irq.h>
24 #include <linux/seq_file.h>
25 
26 #include <linux/pinctrl/pinconf-generic.h>
27 #include <linux/pinctrl/pinconf.h>
28 #include <linux/pinctrl/pinctrl.h>
29 #include <linux/pinctrl/pinmux.h>
30 
31 #include <linux/platform_data/pinctrl-single.h>
32 
33 #include "core.h"
34 #include "devicetree.h"
35 #include "pinconf.h"
36 #include "pinmux.h"
37 
38 #define DRIVER_NAME			"pinctrl-single"
39 #define PCS_OFF_DISABLED		~0U
40 
41 /**
42  * struct pcs_func_vals - mux function register offset and value pair
43  * @reg:	register virtual address
44  * @val:	register value
45  * @mask:	mask
46  */
47 struct pcs_func_vals {
48 	void __iomem *reg;
49 	unsigned val;
50 	unsigned mask;
51 };
52 
53 /**
54  * struct pcs_conf_vals - pinconf parameter, pinconf register offset
55  * and value, enable, disable, mask
56  * @param:	config parameter
57  * @val:	user input bits in the pinconf register
58  * @enable:	enable bits in the pinconf register
59  * @disable:	disable bits in the pinconf register
60  * @mask:	mask bits in the register value
61  */
62 struct pcs_conf_vals {
63 	enum pin_config_param param;
64 	unsigned val;
65 	unsigned enable;
66 	unsigned disable;
67 	unsigned mask;
68 };
69 
70 /**
71  * struct pcs_conf_type - pinconf property name, pinconf param pair
72  * @name:	property name in DTS file
73  * @param:	config parameter
74  */
75 struct pcs_conf_type {
76 	const char *name;
77 	enum pin_config_param param;
78 };
79 
80 /**
81  * struct pcs_function - pinctrl function
82  * @name:	pinctrl function name
83  * @vals:	register and vals array
84  * @nvals:	number of entries in vals array
85  * @pgnames:	array of pingroup names the function uses
86  * @npgnames:	number of pingroup names the function uses
87  * @conf:	array of pin configurations
88  * @nconfs:	number of pin configurations available
89  * @node:	list node
90  */
91 struct pcs_function {
92 	const char *name;
93 	struct pcs_func_vals *vals;
94 	unsigned nvals;
95 	const char **pgnames;
96 	int npgnames;
97 	struct pcs_conf_vals *conf;
98 	int nconfs;
99 	struct list_head node;
100 };
101 
102 /**
103  * struct pcs_gpiofunc_range - pin ranges with same mux value of gpio function
104  * @offset:	offset base of pins
105  * @npins:	number pins with the same mux value of gpio function
106  * @gpiofunc:	mux value of gpio function
107  * @node:	list node
108  */
109 struct pcs_gpiofunc_range {
110 	unsigned offset;
111 	unsigned npins;
112 	unsigned gpiofunc;
113 	struct list_head node;
114 };
115 
116 /**
117  * struct pcs_data - wrapper for data needed by pinctrl framework
118  * @pa:		pindesc array
119  * @cur:	index to current element
120  *
121  * REVISIT: We should be able to drop this eventually by adding
122  * support for registering pins individually in the pinctrl
123  * framework for those drivers that don't need a static array.
124  */
125 struct pcs_data {
126 	struct pinctrl_pin_desc *pa;
127 	int cur;
128 };
129 
130 /**
131  * struct pcs_soc_data - SoC specific settings
132  * @flags:	initial SoC specific PCS_FEAT_xxx values
133  * @irq:	optional interrupt for the controller
134  * @irq_enable_mask:	optional SoC specific interrupt enable mask
135  * @irq_status_mask:	optional SoC specific interrupt status mask
136  * @rearm:	optional SoC specific wake-up rearm function
137  */
138 struct pcs_soc_data {
139 	unsigned flags;
140 	int irq;
141 	unsigned irq_enable_mask;
142 	unsigned irq_status_mask;
143 	void (*rearm)(void);
144 };
145 
146 /**
147  * struct pcs_device - pinctrl device instance
148  * @res:	resources
149  * @base:	virtual address of the controller
150  * @saved_vals: saved values for the controller
151  * @size:	size of the ioremapped area
152  * @dev:	device entry
153  * @np:		device tree node
154  * @pctl:	pin controller device
155  * @flags:	mask of PCS_FEAT_xxx values
156  * @missing_nr_pinctrl_cells: for legacy binding, may go away
157  * @socdata:	soc specific data
158  * @lock:	spinlock for register access
159  * @mutex:	mutex protecting the lists
160  * @width:	bits per mux register
161  * @fmask:	function register mask
162  * @fshift:	function register shift
163  * @foff:	value to turn mux off
164  * @fmax:	max number of functions in fmask
165  * @bits_per_mux: number of bits per mux
166  * @bits_per_pin: number of bits per pin
167  * @pins:	physical pins on the SoC
168  * @gpiofuncs:	list of gpio functions
169  * @irqs:	list of interrupt registers
170  * @chip:	chip container for this instance
171  * @domain:	IRQ domain for this instance
172  * @desc:	pin controller descriptor
173  * @read:	register read function to use
174  * @write:	register write function to use
175  */
176 struct pcs_device {
177 	struct resource *res;
178 	void __iomem *base;
179 	void *saved_vals;
180 	unsigned size;
181 	struct device *dev;
182 	struct device_node *np;
183 	struct pinctrl_dev *pctl;
184 	unsigned flags;
185 #define PCS_CONTEXT_LOSS_OFF	(1 << 3)
186 #define PCS_QUIRK_SHARED_IRQ	(1 << 2)
187 #define PCS_FEAT_IRQ		(1 << 1)
188 #define PCS_FEAT_PINCONF	(1 << 0)
189 	struct property *missing_nr_pinctrl_cells;
190 	struct pcs_soc_data socdata;
191 	raw_spinlock_t lock;
192 	struct mutex mutex;
193 	unsigned width;
194 	unsigned fmask;
195 	unsigned fshift;
196 	unsigned foff;
197 	unsigned fmax;
198 	bool bits_per_mux;
199 	unsigned bits_per_pin;
200 	struct pcs_data pins;
201 	struct list_head gpiofuncs;
202 	struct list_head irqs;
203 	struct irq_chip chip;
204 	struct irq_domain *domain;
205 	struct pinctrl_desc desc;
206 	unsigned (*read)(void __iomem *reg);
207 	void (*write)(unsigned val, void __iomem *reg);
208 };
209 
210 #define PCS_QUIRK_HAS_SHARED_IRQ	(pcs->flags & PCS_QUIRK_SHARED_IRQ)
211 #define PCS_HAS_IRQ		(pcs->flags & PCS_FEAT_IRQ)
212 #define PCS_HAS_PINCONF		(pcs->flags & PCS_FEAT_PINCONF)
213 
214 static int pcs_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin,
215 			   unsigned long *config);
216 static int pcs_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin,
217 			   unsigned long *configs, unsigned num_configs);
218 
219 static enum pin_config_param pcs_bias[] = {
220 	PIN_CONFIG_BIAS_PULL_DOWN,
221 	PIN_CONFIG_BIAS_PULL_UP,
222 };
223 
224 /*
225  * This lock class tells lockdep that irqchip core that this single
226  * pinctrl can be in a different category than its parents, so it won't
227  * report false recursion.
228  */
229 static struct lock_class_key pcs_lock_class;
230 
231 /* Class for the IRQ request mutex */
232 static struct lock_class_key pcs_request_class;
233 
234 /*
235  * REVISIT: Reads and writes could eventually use regmap or something
236  * generic. But at least on omaps, some mux registers are performance
237  * critical as they may need to be remuxed every time before and after
238  * idle. Adding tests for register access width for every read and
239  * write like regmap is doing is not desired, and caching the registers
240  * does not help in this case.
241  */
242 
243 static unsigned __maybe_unused pcs_readb(void __iomem *reg)
244 {
245 	return readb(reg);
246 }
247 
248 static unsigned __maybe_unused pcs_readw(void __iomem *reg)
249 {
250 	return readw(reg);
251 }
252 
253 static unsigned __maybe_unused pcs_readl(void __iomem *reg)
254 {
255 	return readl(reg);
256 }
257 
258 static void __maybe_unused pcs_writeb(unsigned val, void __iomem *reg)
259 {
260 	writeb(val, reg);
261 }
262 
263 static void __maybe_unused pcs_writew(unsigned val, void __iomem *reg)
264 {
265 	writew(val, reg);
266 }
267 
268 static void __maybe_unused pcs_writel(unsigned val, void __iomem *reg)
269 {
270 	writel(val, reg);
271 }
272 
273 static unsigned int pcs_pin_reg_offset_get(struct pcs_device *pcs,
274 					   unsigned int pin)
275 {
276 	unsigned int mux_bytes = pcs->width / BITS_PER_BYTE;
277 
278 	if (pcs->bits_per_mux) {
279 		unsigned int pin_offset_bytes;
280 
281 		pin_offset_bytes = (pcs->bits_per_pin * pin) / BITS_PER_BYTE;
282 		return (pin_offset_bytes / mux_bytes) * mux_bytes;
283 	}
284 
285 	return pin * mux_bytes;
286 }
287 
288 static unsigned int pcs_pin_shift_reg_get(struct pcs_device *pcs,
289 					  unsigned int pin)
290 {
291 	return (pin % (pcs->width / pcs->bits_per_pin)) * pcs->bits_per_pin;
292 }
293 
294 static void pcs_pin_dbg_show(struct pinctrl_dev *pctldev,
295 					struct seq_file *s,
296 					unsigned pin)
297 {
298 	struct pcs_device *pcs;
299 	unsigned int val;
300 	unsigned long offset;
301 	size_t pa;
302 
303 	pcs = pinctrl_dev_get_drvdata(pctldev);
304 
305 	offset = pcs_pin_reg_offset_get(pcs, pin);
306 	val = pcs->read(pcs->base + offset);
307 
308 	if (pcs->bits_per_mux)
309 		val &= pcs->fmask << pcs_pin_shift_reg_get(pcs, pin);
310 
311 	pa = pcs->res->start + offset;
312 
313 	seq_printf(s, "%zx %08x %s ", pa, val, DRIVER_NAME);
314 }
315 
316 static void pcs_dt_free_map(struct pinctrl_dev *pctldev,
317 				struct pinctrl_map *map, unsigned num_maps)
318 {
319 	struct pcs_device *pcs;
320 
321 	pcs = pinctrl_dev_get_drvdata(pctldev);
322 	devm_kfree(pcs->dev, map);
323 }
324 
325 static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev,
326 				struct device_node *np_config,
327 				struct pinctrl_map **map, unsigned *num_maps);
328 
329 static const struct pinctrl_ops pcs_pinctrl_ops = {
330 	.get_groups_count = pinctrl_generic_get_group_count,
331 	.get_group_name = pinctrl_generic_get_group_name,
332 	.get_group_pins = pinctrl_generic_get_group_pins,
333 	.pin_dbg_show = pcs_pin_dbg_show,
334 	.dt_node_to_map = pcs_dt_node_to_map,
335 	.dt_free_map = pcs_dt_free_map,
336 };
337 
338 static int pcs_get_function(struct pinctrl_dev *pctldev, unsigned pin,
339 			    struct pcs_function **func)
340 {
341 	struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
342 	struct pin_desc *pdesc = pin_desc_get(pctldev, pin);
343 	const struct pinctrl_setting_mux *setting;
344 	struct function_desc *function;
345 	unsigned fselector;
346 
347 	/* If pin is not described in DTS & enabled, mux_setting is NULL. */
348 	setting = pdesc->mux_setting;
349 	if (!setting)
350 		return -ENOTSUPP;
351 	fselector = setting->func;
352 	function = pinmux_generic_get_function(pctldev, fselector);
353 	*func = function->data;
354 	if (!(*func)) {
355 		dev_err(pcs->dev, "%s could not find function%i\n",
356 			__func__, fselector);
357 		return -ENOTSUPP;
358 	}
359 	return 0;
360 }
361 
362 static int pcs_set_mux(struct pinctrl_dev *pctldev, unsigned fselector,
363 	unsigned group)
364 {
365 	struct pcs_device *pcs;
366 	struct function_desc *function;
367 	struct pcs_function *func;
368 	int i;
369 
370 	pcs = pinctrl_dev_get_drvdata(pctldev);
371 	/* If function mask is null, needn't enable it. */
372 	if (!pcs->fmask)
373 		return 0;
374 	function = pinmux_generic_get_function(pctldev, fselector);
375 	if (!function)
376 		return -EINVAL;
377 	func = function->data;
378 	if (!func)
379 		return -EINVAL;
380 
381 	dev_dbg(pcs->dev, "enabling %s function%i\n",
382 		func->name, fselector);
383 
384 	for (i = 0; i < func->nvals; i++) {
385 		struct pcs_func_vals *vals;
386 		unsigned long flags;
387 		unsigned val, mask;
388 
389 		vals = &func->vals[i];
390 		raw_spin_lock_irqsave(&pcs->lock, flags);
391 		val = pcs->read(vals->reg);
392 
393 		if (pcs->bits_per_mux)
394 			mask = vals->mask;
395 		else
396 			mask = pcs->fmask;
397 
398 		val &= ~mask;
399 		val |= (vals->val & mask);
400 		pcs->write(val, vals->reg);
401 		raw_spin_unlock_irqrestore(&pcs->lock, flags);
402 	}
403 
404 	return 0;
405 }
406 
407 static int pcs_request_gpio(struct pinctrl_dev *pctldev,
408 			    struct pinctrl_gpio_range *range, unsigned pin)
409 {
410 	struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
411 	struct pcs_gpiofunc_range *frange = NULL;
412 	struct list_head *pos, *tmp;
413 	unsigned data;
414 
415 	/* If function mask is null, return directly. */
416 	if (!pcs->fmask)
417 		return -ENOTSUPP;
418 
419 	list_for_each_safe(pos, tmp, &pcs->gpiofuncs) {
420 		u32 offset;
421 
422 		frange = list_entry(pos, struct pcs_gpiofunc_range, node);
423 		if (pin >= frange->offset + frange->npins
424 			|| pin < frange->offset)
425 			continue;
426 
427 		offset = pcs_pin_reg_offset_get(pcs, pin);
428 
429 		if (pcs->bits_per_mux) {
430 			int pin_shift = pcs_pin_shift_reg_get(pcs, pin);
431 
432 			data = pcs->read(pcs->base + offset);
433 			data &= ~(pcs->fmask << pin_shift);
434 			data |= frange->gpiofunc << pin_shift;
435 			pcs->write(data, pcs->base + offset);
436 		} else {
437 			data = pcs->read(pcs->base + offset);
438 			data &= ~pcs->fmask;
439 			data |= frange->gpiofunc;
440 			pcs->write(data, pcs->base + offset);
441 		}
442 		break;
443 	}
444 	return 0;
445 }
446 
447 static const struct pinmux_ops pcs_pinmux_ops = {
448 	.get_functions_count = pinmux_generic_get_function_count,
449 	.get_function_name = pinmux_generic_get_function_name,
450 	.get_function_groups = pinmux_generic_get_function_groups,
451 	.set_mux = pcs_set_mux,
452 	.gpio_request_enable = pcs_request_gpio,
453 };
454 
455 /* Clear BIAS value */
456 static void pcs_pinconf_clear_bias(struct pinctrl_dev *pctldev, unsigned pin)
457 {
458 	unsigned long config;
459 	int i;
460 	for (i = 0; i < ARRAY_SIZE(pcs_bias); i++) {
461 		config = pinconf_to_config_packed(pcs_bias[i], 0);
462 		pcs_pinconf_set(pctldev, pin, &config, 1);
463 	}
464 }
465 
466 /*
467  * Check whether PIN_CONFIG_BIAS_DISABLE is valid.
468  * It's depend on that PULL_DOWN & PULL_UP configs are all invalid.
469  */
470 static bool pcs_pinconf_bias_disable(struct pinctrl_dev *pctldev, unsigned pin)
471 {
472 	unsigned long config;
473 	int i;
474 
475 	for (i = 0; i < ARRAY_SIZE(pcs_bias); i++) {
476 		config = pinconf_to_config_packed(pcs_bias[i], 0);
477 		if (!pcs_pinconf_get(pctldev, pin, &config))
478 			goto out;
479 	}
480 	return true;
481 out:
482 	return false;
483 }
484 
485 static int pcs_pinconf_get(struct pinctrl_dev *pctldev,
486 				unsigned pin, unsigned long *config)
487 {
488 	struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
489 	struct pcs_function *func;
490 	enum pin_config_param param;
491 	unsigned offset = 0, data = 0, i, j, ret;
492 
493 	ret = pcs_get_function(pctldev, pin, &func);
494 	if (ret)
495 		return ret;
496 
497 	for (i = 0; i < func->nconfs; i++) {
498 		param = pinconf_to_config_param(*config);
499 		if (param == PIN_CONFIG_BIAS_DISABLE) {
500 			if (pcs_pinconf_bias_disable(pctldev, pin)) {
501 				*config = 0;
502 				return 0;
503 			} else {
504 				return -ENOTSUPP;
505 			}
506 		} else if (param != func->conf[i].param) {
507 			continue;
508 		}
509 
510 		offset = pin * (pcs->width / BITS_PER_BYTE);
511 		data = pcs->read(pcs->base + offset) & func->conf[i].mask;
512 		switch (func->conf[i].param) {
513 		/* 4 parameters */
514 		case PIN_CONFIG_BIAS_PULL_DOWN:
515 		case PIN_CONFIG_BIAS_PULL_UP:
516 		case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
517 			if ((data != func->conf[i].enable) ||
518 			    (data == func->conf[i].disable))
519 				return -ENOTSUPP;
520 			*config = 0;
521 			break;
522 		/* 2 parameters */
523 		case PIN_CONFIG_INPUT_SCHMITT:
524 			for (j = 0; j < func->nconfs; j++) {
525 				switch (func->conf[j].param) {
526 				case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
527 					if (data != func->conf[j].enable)
528 						return -ENOTSUPP;
529 					break;
530 				default:
531 					break;
532 				}
533 			}
534 			*config = data;
535 			break;
536 		case PIN_CONFIG_DRIVE_STRENGTH:
537 		case PIN_CONFIG_SLEW_RATE:
538 		case PIN_CONFIG_MODE_LOW_POWER:
539 		case PIN_CONFIG_INPUT_ENABLE:
540 		default:
541 			*config = data;
542 			break;
543 		}
544 		return 0;
545 	}
546 	return -ENOTSUPP;
547 }
548 
549 static int pcs_pinconf_set(struct pinctrl_dev *pctldev,
550 				unsigned pin, unsigned long *configs,
551 				unsigned num_configs)
552 {
553 	struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
554 	struct pcs_function *func;
555 	unsigned offset = 0, shift = 0, i, data, ret;
556 	u32 arg;
557 	int j;
558 
559 	ret = pcs_get_function(pctldev, pin, &func);
560 	if (ret)
561 		return ret;
562 
563 	for (j = 0; j < num_configs; j++) {
564 		for (i = 0; i < func->nconfs; i++) {
565 			if (pinconf_to_config_param(configs[j])
566 				!= func->conf[i].param)
567 				continue;
568 
569 			offset = pin * (pcs->width / BITS_PER_BYTE);
570 			data = pcs->read(pcs->base + offset);
571 			arg = pinconf_to_config_argument(configs[j]);
572 			switch (func->conf[i].param) {
573 			/* 2 parameters */
574 			case PIN_CONFIG_INPUT_SCHMITT:
575 			case PIN_CONFIG_DRIVE_STRENGTH:
576 			case PIN_CONFIG_SLEW_RATE:
577 			case PIN_CONFIG_MODE_LOW_POWER:
578 			case PIN_CONFIG_INPUT_ENABLE:
579 				shift = ffs(func->conf[i].mask) - 1;
580 				data &= ~func->conf[i].mask;
581 				data |= (arg << shift) & func->conf[i].mask;
582 				break;
583 			/* 4 parameters */
584 			case PIN_CONFIG_BIAS_DISABLE:
585 				pcs_pinconf_clear_bias(pctldev, pin);
586 				break;
587 			case PIN_CONFIG_BIAS_PULL_DOWN:
588 			case PIN_CONFIG_BIAS_PULL_UP:
589 				if (arg)
590 					pcs_pinconf_clear_bias(pctldev, pin);
591 				fallthrough;
592 			case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
593 				data &= ~func->conf[i].mask;
594 				if (arg)
595 					data |= func->conf[i].enable;
596 				else
597 					data |= func->conf[i].disable;
598 				break;
599 			default:
600 				return -ENOTSUPP;
601 			}
602 			pcs->write(data, pcs->base + offset);
603 
604 			break;
605 		}
606 		if (i >= func->nconfs)
607 			return -ENOTSUPP;
608 	} /* for each config */
609 
610 	return 0;
611 }
612 
613 static int pcs_pinconf_group_get(struct pinctrl_dev *pctldev,
614 				unsigned group, unsigned long *config)
615 {
616 	const unsigned *pins;
617 	unsigned npins, old = 0;
618 	int i, ret;
619 
620 	ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
621 	if (ret)
622 		return ret;
623 	for (i = 0; i < npins; i++) {
624 		if (pcs_pinconf_get(pctldev, pins[i], config))
625 			return -ENOTSUPP;
626 		/* configs do not match between two pins */
627 		if (i && (old != *config))
628 			return -ENOTSUPP;
629 		old = *config;
630 	}
631 	return 0;
632 }
633 
634 static int pcs_pinconf_group_set(struct pinctrl_dev *pctldev,
635 				unsigned group, unsigned long *configs,
636 				unsigned num_configs)
637 {
638 	const unsigned *pins;
639 	unsigned npins;
640 	int i, ret;
641 
642 	ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
643 	if (ret)
644 		return ret;
645 	for (i = 0; i < npins; i++) {
646 		if (pcs_pinconf_set(pctldev, pins[i], configs, num_configs))
647 			return -ENOTSUPP;
648 	}
649 	return 0;
650 }
651 
652 static void pcs_pinconf_dbg_show(struct pinctrl_dev *pctldev,
653 				struct seq_file *s, unsigned pin)
654 {
655 }
656 
657 static void pcs_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
658 				struct seq_file *s, unsigned selector)
659 {
660 }
661 
662 static void pcs_pinconf_config_dbg_show(struct pinctrl_dev *pctldev,
663 					struct seq_file *s,
664 					unsigned long config)
665 {
666 	pinconf_generic_dump_config(pctldev, s, config);
667 }
668 
669 static const struct pinconf_ops pcs_pinconf_ops = {
670 	.pin_config_get = pcs_pinconf_get,
671 	.pin_config_set = pcs_pinconf_set,
672 	.pin_config_group_get = pcs_pinconf_group_get,
673 	.pin_config_group_set = pcs_pinconf_group_set,
674 	.pin_config_dbg_show = pcs_pinconf_dbg_show,
675 	.pin_config_group_dbg_show = pcs_pinconf_group_dbg_show,
676 	.pin_config_config_dbg_show = pcs_pinconf_config_dbg_show,
677 	.is_generic = true,
678 };
679 
680 /**
681  * pcs_add_pin() - add a pin to the static per controller pin array
682  * @pcs: pcs driver instance
683  * @offset: register offset from base
684  */
685 static int pcs_add_pin(struct pcs_device *pcs, unsigned int offset)
686 {
687 	struct pcs_soc_data *pcs_soc = &pcs->socdata;
688 	struct pinctrl_pin_desc *pin;
689 	int i;
690 
691 	i = pcs->pins.cur;
692 	if (i >= pcs->desc.npins) {
693 		dev_err(pcs->dev, "too many pins, max %i\n",
694 			pcs->desc.npins);
695 		return -ENOMEM;
696 	}
697 
698 	if (pcs_soc->irq_enable_mask) {
699 		unsigned val;
700 
701 		val = pcs->read(pcs->base + offset);
702 		if (val & pcs_soc->irq_enable_mask) {
703 			dev_dbg(pcs->dev, "irq enabled at boot for pin at %lx (%x), clearing\n",
704 				(unsigned long)pcs->res->start + offset, val);
705 			val &= ~pcs_soc->irq_enable_mask;
706 			pcs->write(val, pcs->base + offset);
707 		}
708 	}
709 
710 	pin = &pcs->pins.pa[i];
711 	pin->number = i;
712 	pcs->pins.cur++;
713 
714 	return i;
715 }
716 
717 /**
718  * pcs_allocate_pin_table() - adds all the pins for the pinctrl driver
719  * @pcs: pcs driver instance
720  *
721  * In case of errors, resources are freed in pcs_free_resources.
722  *
723  * If your hardware needs holes in the address space, then just set
724  * up multiple driver instances.
725  */
726 static int pcs_allocate_pin_table(struct pcs_device *pcs)
727 {
728 	int mux_bytes, nr_pins, i;
729 
730 	mux_bytes = pcs->width / BITS_PER_BYTE;
731 
732 	if (pcs->bits_per_mux && pcs->fmask) {
733 		pcs->bits_per_pin = fls(pcs->fmask);
734 		nr_pins = (pcs->size * BITS_PER_BYTE) / pcs->bits_per_pin;
735 	} else {
736 		nr_pins = pcs->size / mux_bytes;
737 	}
738 
739 	dev_dbg(pcs->dev, "allocating %i pins\n", nr_pins);
740 	pcs->pins.pa = devm_kcalloc(pcs->dev,
741 				nr_pins, sizeof(*pcs->pins.pa),
742 				GFP_KERNEL);
743 	if (!pcs->pins.pa)
744 		return -ENOMEM;
745 
746 	pcs->desc.pins = pcs->pins.pa;
747 	pcs->desc.npins = nr_pins;
748 
749 	for (i = 0; i < pcs->desc.npins; i++) {
750 		unsigned offset;
751 		int res;
752 
753 		offset = pcs_pin_reg_offset_get(pcs, i);
754 		res = pcs_add_pin(pcs, offset);
755 		if (res < 0) {
756 			dev_err(pcs->dev, "error adding pins: %i\n", res);
757 			return res;
758 		}
759 	}
760 
761 	return 0;
762 }
763 
764 /**
765  * pcs_add_function() - adds a new function to the function list
766  * @pcs: pcs driver instance
767  * @fcn: new function allocated
768  * @name: name of the function
769  * @vals: array of mux register value pairs used by the function
770  * @nvals: number of mux register value pairs
771  * @pgnames: array of pingroup names for the function
772  * @npgnames: number of pingroup names
773  *
774  * Caller must take care of locking.
775  */
776 static int pcs_add_function(struct pcs_device *pcs,
777 			    struct pcs_function **fcn,
778 			    const char *name,
779 			    struct pcs_func_vals *vals,
780 			    unsigned int nvals,
781 			    const char **pgnames,
782 			    unsigned int npgnames)
783 {
784 	struct pcs_function *function;
785 	int selector;
786 
787 	function = devm_kzalloc(pcs->dev, sizeof(*function), GFP_KERNEL);
788 	if (!function)
789 		return -ENOMEM;
790 
791 	function->vals = vals;
792 	function->nvals = nvals;
793 	function->name = name;
794 
795 	selector = pinmux_generic_add_function(pcs->pctl, name,
796 					       pgnames, npgnames,
797 					       function);
798 	if (selector < 0) {
799 		devm_kfree(pcs->dev, function);
800 		*fcn = NULL;
801 	} else {
802 		*fcn = function;
803 	}
804 
805 	return selector;
806 }
807 
808 /**
809  * pcs_get_pin_by_offset() - get a pin index based on the register offset
810  * @pcs: pcs driver instance
811  * @offset: register offset from the base
812  *
813  * Note that this is OK as long as the pins are in a static array.
814  */
815 static int pcs_get_pin_by_offset(struct pcs_device *pcs, unsigned offset)
816 {
817 	unsigned index;
818 
819 	if (offset >= pcs->size) {
820 		dev_err(pcs->dev, "mux offset out of range: 0x%x (0x%x)\n",
821 			offset, pcs->size);
822 		return -EINVAL;
823 	}
824 
825 	if (pcs->bits_per_mux)
826 		index = (offset * BITS_PER_BYTE) / pcs->bits_per_pin;
827 	else
828 		index = offset / (pcs->width / BITS_PER_BYTE);
829 
830 	return index;
831 }
832 
833 /*
834  * check whether data matches enable bits or disable bits
835  * Return value: 1 for matching enable bits, 0 for matching disable bits,
836  *               and negative value for matching failure.
837  */
838 static int pcs_config_match(unsigned data, unsigned enable, unsigned disable)
839 {
840 	int ret = -EINVAL;
841 
842 	if (data == enable)
843 		ret = 1;
844 	else if (data == disable)
845 		ret = 0;
846 	return ret;
847 }
848 
849 static void add_config(struct pcs_conf_vals **conf, enum pin_config_param param,
850 		       unsigned value, unsigned enable, unsigned disable,
851 		       unsigned mask)
852 {
853 	(*conf)->param = param;
854 	(*conf)->val = value;
855 	(*conf)->enable = enable;
856 	(*conf)->disable = disable;
857 	(*conf)->mask = mask;
858 	(*conf)++;
859 }
860 
861 static void add_setting(unsigned long **setting, enum pin_config_param param,
862 			unsigned arg)
863 {
864 	**setting = pinconf_to_config_packed(param, arg);
865 	(*setting)++;
866 }
867 
868 /* add pinconf setting with 2 parameters */
869 static void pcs_add_conf2(struct pcs_device *pcs, struct device_node *np,
870 			  const char *name, enum pin_config_param param,
871 			  struct pcs_conf_vals **conf, unsigned long **settings)
872 {
873 	unsigned value[2], shift;
874 	int ret;
875 
876 	ret = of_property_read_u32_array(np, name, value, 2);
877 	if (ret)
878 		return;
879 	/* set value & mask */
880 	value[0] &= value[1];
881 	shift = ffs(value[1]) - 1;
882 	/* skip enable & disable */
883 	add_config(conf, param, value[0], 0, 0, value[1]);
884 	add_setting(settings, param, value[0] >> shift);
885 }
886 
887 /* add pinconf setting with 4 parameters */
888 static void pcs_add_conf4(struct pcs_device *pcs, struct device_node *np,
889 			  const char *name, enum pin_config_param param,
890 			  struct pcs_conf_vals **conf, unsigned long **settings)
891 {
892 	unsigned value[4];
893 	int ret;
894 
895 	/* value to set, enable, disable, mask */
896 	ret = of_property_read_u32_array(np, name, value, 4);
897 	if (ret)
898 		return;
899 	if (!value[3]) {
900 		dev_err(pcs->dev, "mask field of the property can't be 0\n");
901 		return;
902 	}
903 	value[0] &= value[3];
904 	value[1] &= value[3];
905 	value[2] &= value[3];
906 	ret = pcs_config_match(value[0], value[1], value[2]);
907 	if (ret < 0)
908 		dev_dbg(pcs->dev, "failed to match enable or disable bits\n");
909 	add_config(conf, param, value[0], value[1], value[2], value[3]);
910 	add_setting(settings, param, ret);
911 }
912 
913 static int pcs_parse_pinconf(struct pcs_device *pcs, struct device_node *np,
914 			     struct pcs_function *func,
915 			     struct pinctrl_map **map)
916 
917 {
918 	struct pinctrl_map *m = *map;
919 	int i = 0, nconfs = 0;
920 	unsigned long *settings = NULL, *s = NULL;
921 	struct pcs_conf_vals *conf = NULL;
922 	static const struct pcs_conf_type prop2[] = {
923 		{ "pinctrl-single,drive-strength", PIN_CONFIG_DRIVE_STRENGTH, },
924 		{ "pinctrl-single,slew-rate", PIN_CONFIG_SLEW_RATE, },
925 		{ "pinctrl-single,input-enable", PIN_CONFIG_INPUT_ENABLE, },
926 		{ "pinctrl-single,input-schmitt", PIN_CONFIG_INPUT_SCHMITT, },
927 		{ "pinctrl-single,low-power-mode", PIN_CONFIG_MODE_LOW_POWER, },
928 	};
929 	static const struct pcs_conf_type prop4[] = {
930 		{ "pinctrl-single,bias-pullup", PIN_CONFIG_BIAS_PULL_UP, },
931 		{ "pinctrl-single,bias-pulldown", PIN_CONFIG_BIAS_PULL_DOWN, },
932 		{ "pinctrl-single,input-schmitt-enable",
933 			PIN_CONFIG_INPUT_SCHMITT_ENABLE, },
934 	};
935 
936 	/* If pinconf isn't supported, don't parse properties in below. */
937 	if (!PCS_HAS_PINCONF)
938 		return -ENOTSUPP;
939 
940 	/* cacluate how much properties are supported in current node */
941 	for (i = 0; i < ARRAY_SIZE(prop2); i++) {
942 		if (of_find_property(np, prop2[i].name, NULL))
943 			nconfs++;
944 	}
945 	for (i = 0; i < ARRAY_SIZE(prop4); i++) {
946 		if (of_find_property(np, prop4[i].name, NULL))
947 			nconfs++;
948 	}
949 	if (!nconfs)
950 		return -ENOTSUPP;
951 
952 	func->conf = devm_kcalloc(pcs->dev,
953 				  nconfs, sizeof(struct pcs_conf_vals),
954 				  GFP_KERNEL);
955 	if (!func->conf)
956 		return -ENOMEM;
957 	func->nconfs = nconfs;
958 	conf = &(func->conf[0]);
959 	m++;
960 	settings = devm_kcalloc(pcs->dev, nconfs, sizeof(unsigned long),
961 				GFP_KERNEL);
962 	if (!settings)
963 		return -ENOMEM;
964 	s = &settings[0];
965 
966 	for (i = 0; i < ARRAY_SIZE(prop2); i++)
967 		pcs_add_conf2(pcs, np, prop2[i].name, prop2[i].param,
968 			      &conf, &s);
969 	for (i = 0; i < ARRAY_SIZE(prop4); i++)
970 		pcs_add_conf4(pcs, np, prop4[i].name, prop4[i].param,
971 			      &conf, &s);
972 	m->type = PIN_MAP_TYPE_CONFIGS_GROUP;
973 	m->data.configs.group_or_pin = np->name;
974 	m->data.configs.configs = settings;
975 	m->data.configs.num_configs = nconfs;
976 	return 0;
977 }
978 
979 /**
980  * pcs_parse_one_pinctrl_entry() - parses a device tree mux entry
981  * @pcs: pinctrl driver instance
982  * @np: device node of the mux entry
983  * @map: map entry
984  * @num_maps: number of map
985  * @pgnames: pingroup names
986  *
987  * Note that this binding currently supports only sets of one register + value.
988  *
989  * Also note that this driver tries to avoid understanding pin and function
990  * names because of the extra bloat they would cause especially in the case of
991  * a large number of pins. This driver just sets what is specified for the board
992  * in the .dts file. Further user space debugging tools can be developed to
993  * decipher the pin and function names using debugfs.
994  *
995  * If you are concerned about the boot time, set up the static pins in
996  * the bootloader, and only set up selected pins as device tree entries.
997  */
998 static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs,
999 						struct device_node *np,
1000 						struct pinctrl_map **map,
1001 						unsigned *num_maps,
1002 						const char **pgnames)
1003 {
1004 	const char *name = "pinctrl-single,pins";
1005 	struct pcs_func_vals *vals;
1006 	int rows, *pins, found = 0, res = -ENOMEM, i, fsel, gsel;
1007 	struct pcs_function *function = NULL;
1008 
1009 	rows = pinctrl_count_index_with_args(np, name);
1010 	if (rows <= 0) {
1011 		dev_err(pcs->dev, "Invalid number of rows: %d\n", rows);
1012 		return -EINVAL;
1013 	}
1014 
1015 	vals = devm_kcalloc(pcs->dev, rows, sizeof(*vals), GFP_KERNEL);
1016 	if (!vals)
1017 		return -ENOMEM;
1018 
1019 	pins = devm_kcalloc(pcs->dev, rows, sizeof(*pins), GFP_KERNEL);
1020 	if (!pins)
1021 		goto free_vals;
1022 
1023 	for (i = 0; i < rows; i++) {
1024 		struct of_phandle_args pinctrl_spec;
1025 		unsigned int offset;
1026 		int pin;
1027 
1028 		res = pinctrl_parse_index_with_args(np, name, i, &pinctrl_spec);
1029 		if (res)
1030 			return res;
1031 
1032 		if (pinctrl_spec.args_count < 2 || pinctrl_spec.args_count > 3) {
1033 			dev_err(pcs->dev, "invalid args_count for spec: %i\n",
1034 				pinctrl_spec.args_count);
1035 			break;
1036 		}
1037 
1038 		offset = pinctrl_spec.args[0];
1039 		vals[found].reg = pcs->base + offset;
1040 
1041 		switch (pinctrl_spec.args_count) {
1042 		case 2:
1043 			vals[found].val = pinctrl_spec.args[1];
1044 			break;
1045 		case 3:
1046 			vals[found].val = (pinctrl_spec.args[1] | pinctrl_spec.args[2]);
1047 			break;
1048 		}
1049 
1050 		dev_dbg(pcs->dev, "%pOFn index: 0x%x value: 0x%x\n",
1051 			pinctrl_spec.np, offset, vals[found].val);
1052 
1053 		pin = pcs_get_pin_by_offset(pcs, offset);
1054 		if (pin < 0) {
1055 			dev_err(pcs->dev,
1056 				"could not add functions for %pOFn %ux\n",
1057 				np, offset);
1058 			break;
1059 		}
1060 		pins[found++] = pin;
1061 	}
1062 
1063 	pgnames[0] = np->name;
1064 	mutex_lock(&pcs->mutex);
1065 	fsel = pcs_add_function(pcs, &function, np->name, vals, found,
1066 				pgnames, 1);
1067 	if (fsel < 0) {
1068 		res = fsel;
1069 		goto free_pins;
1070 	}
1071 
1072 	gsel = pinctrl_generic_add_group(pcs->pctl, np->name, pins, found, pcs);
1073 	if (gsel < 0) {
1074 		res = gsel;
1075 		goto free_function;
1076 	}
1077 
1078 	(*map)->type = PIN_MAP_TYPE_MUX_GROUP;
1079 	(*map)->data.mux.group = np->name;
1080 	(*map)->data.mux.function = np->name;
1081 
1082 	if (PCS_HAS_PINCONF && function) {
1083 		res = pcs_parse_pinconf(pcs, np, function, map);
1084 		if (res == 0)
1085 			*num_maps = 2;
1086 		else if (res == -ENOTSUPP)
1087 			*num_maps = 1;
1088 		else
1089 			goto free_pingroups;
1090 	} else {
1091 		*num_maps = 1;
1092 	}
1093 	mutex_unlock(&pcs->mutex);
1094 
1095 	return 0;
1096 
1097 free_pingroups:
1098 	pinctrl_generic_remove_group(pcs->pctl, gsel);
1099 	*num_maps = 1;
1100 free_function:
1101 	pinmux_generic_remove_function(pcs->pctl, fsel);
1102 free_pins:
1103 	mutex_unlock(&pcs->mutex);
1104 	devm_kfree(pcs->dev, pins);
1105 
1106 free_vals:
1107 	devm_kfree(pcs->dev, vals);
1108 
1109 	return res;
1110 }
1111 
1112 static int pcs_parse_bits_in_pinctrl_entry(struct pcs_device *pcs,
1113 						struct device_node *np,
1114 						struct pinctrl_map **map,
1115 						unsigned *num_maps,
1116 						const char **pgnames)
1117 {
1118 	const char *name = "pinctrl-single,bits";
1119 	struct pcs_func_vals *vals;
1120 	int rows, *pins, found = 0, res = -ENOMEM, i, fsel;
1121 	int npins_in_row;
1122 	struct pcs_function *function = NULL;
1123 
1124 	rows = pinctrl_count_index_with_args(np, name);
1125 	if (rows <= 0) {
1126 		dev_err(pcs->dev, "Invalid number of rows: %d\n", rows);
1127 		return -EINVAL;
1128 	}
1129 
1130 	if (PCS_HAS_PINCONF) {
1131 		dev_err(pcs->dev, "pinconf not supported\n");
1132 		return -ENOTSUPP;
1133 	}
1134 
1135 	npins_in_row = pcs->width / pcs->bits_per_pin;
1136 
1137 	vals = devm_kzalloc(pcs->dev,
1138 			    array3_size(rows, npins_in_row, sizeof(*vals)),
1139 			    GFP_KERNEL);
1140 	if (!vals)
1141 		return -ENOMEM;
1142 
1143 	pins = devm_kzalloc(pcs->dev,
1144 			    array3_size(rows, npins_in_row, sizeof(*pins)),
1145 			    GFP_KERNEL);
1146 	if (!pins)
1147 		goto free_vals;
1148 
1149 	for (i = 0; i < rows; i++) {
1150 		struct of_phandle_args pinctrl_spec;
1151 		unsigned offset, val;
1152 		unsigned mask, bit_pos, val_pos, mask_pos, submask;
1153 		unsigned pin_num_from_lsb;
1154 		int pin;
1155 
1156 		res = pinctrl_parse_index_with_args(np, name, i, &pinctrl_spec);
1157 		if (res)
1158 			return res;
1159 
1160 		if (pinctrl_spec.args_count < 3) {
1161 			dev_err(pcs->dev, "invalid args_count for spec: %i\n",
1162 				pinctrl_spec.args_count);
1163 			break;
1164 		}
1165 
1166 		/* Index plus two value cells */
1167 		offset = pinctrl_spec.args[0];
1168 		val = pinctrl_spec.args[1];
1169 		mask = pinctrl_spec.args[2];
1170 
1171 		dev_dbg(pcs->dev, "%pOFn index: 0x%x value: 0x%x mask: 0x%x\n",
1172 			pinctrl_spec.np, offset, val, mask);
1173 
1174 		/* Parse pins in each row from LSB */
1175 		while (mask) {
1176 			bit_pos = __ffs(mask);
1177 			pin_num_from_lsb = bit_pos / pcs->bits_per_pin;
1178 			mask_pos = ((pcs->fmask) << bit_pos);
1179 			val_pos = val & mask_pos;
1180 			submask = mask & mask_pos;
1181 
1182 			if ((mask & mask_pos) == 0) {
1183 				dev_err(pcs->dev,
1184 					"Invalid mask for %pOFn at 0x%x\n",
1185 					np, offset);
1186 				break;
1187 			}
1188 
1189 			mask &= ~mask_pos;
1190 
1191 			if (submask != mask_pos) {
1192 				dev_warn(pcs->dev,
1193 						"Invalid submask 0x%x for %pOFn at 0x%x\n",
1194 						submask, np, offset);
1195 				continue;
1196 			}
1197 
1198 			vals[found].mask = submask;
1199 			vals[found].reg = pcs->base + offset;
1200 			vals[found].val = val_pos;
1201 
1202 			pin = pcs_get_pin_by_offset(pcs, offset);
1203 			if (pin < 0) {
1204 				dev_err(pcs->dev,
1205 					"could not add functions for %pOFn %ux\n",
1206 					np, offset);
1207 				break;
1208 			}
1209 			pins[found++] = pin + pin_num_from_lsb;
1210 		}
1211 	}
1212 
1213 	pgnames[0] = np->name;
1214 	mutex_lock(&pcs->mutex);
1215 	fsel = pcs_add_function(pcs, &function, np->name, vals, found,
1216 				pgnames, 1);
1217 	if (fsel < 0) {
1218 		res = fsel;
1219 		goto free_pins;
1220 	}
1221 
1222 	res = pinctrl_generic_add_group(pcs->pctl, np->name, pins, found, pcs);
1223 	if (res < 0)
1224 		goto free_function;
1225 
1226 	(*map)->type = PIN_MAP_TYPE_MUX_GROUP;
1227 	(*map)->data.mux.group = np->name;
1228 	(*map)->data.mux.function = np->name;
1229 
1230 	*num_maps = 1;
1231 	mutex_unlock(&pcs->mutex);
1232 
1233 	return 0;
1234 
1235 free_function:
1236 	pinmux_generic_remove_function(pcs->pctl, fsel);
1237 free_pins:
1238 	mutex_unlock(&pcs->mutex);
1239 	devm_kfree(pcs->dev, pins);
1240 
1241 free_vals:
1242 	devm_kfree(pcs->dev, vals);
1243 
1244 	return res;
1245 }
1246 /**
1247  * pcs_dt_node_to_map() - allocates and parses pinctrl maps
1248  * @pctldev: pinctrl instance
1249  * @np_config: device tree pinmux entry
1250  * @map: array of map entries
1251  * @num_maps: number of maps
1252  */
1253 static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev,
1254 				struct device_node *np_config,
1255 				struct pinctrl_map **map, unsigned *num_maps)
1256 {
1257 	struct pcs_device *pcs;
1258 	const char **pgnames;
1259 	int ret;
1260 
1261 	pcs = pinctrl_dev_get_drvdata(pctldev);
1262 
1263 	/* create 2 maps. One is for pinmux, and the other is for pinconf. */
1264 	*map = devm_kcalloc(pcs->dev, 2, sizeof(**map), GFP_KERNEL);
1265 	if (!*map)
1266 		return -ENOMEM;
1267 
1268 	*num_maps = 0;
1269 
1270 	pgnames = devm_kzalloc(pcs->dev, sizeof(*pgnames), GFP_KERNEL);
1271 	if (!pgnames) {
1272 		ret = -ENOMEM;
1273 		goto free_map;
1274 	}
1275 
1276 	if (pcs->bits_per_mux) {
1277 		ret = pcs_parse_bits_in_pinctrl_entry(pcs, np_config, map,
1278 				num_maps, pgnames);
1279 		if (ret < 0) {
1280 			dev_err(pcs->dev, "no pins entries for %pOFn\n",
1281 				np_config);
1282 			goto free_pgnames;
1283 		}
1284 	} else {
1285 		ret = pcs_parse_one_pinctrl_entry(pcs, np_config, map,
1286 				num_maps, pgnames);
1287 		if (ret < 0) {
1288 			dev_err(pcs->dev, "no pins entries for %pOFn\n",
1289 				np_config);
1290 			goto free_pgnames;
1291 		}
1292 	}
1293 
1294 	return 0;
1295 
1296 free_pgnames:
1297 	devm_kfree(pcs->dev, pgnames);
1298 free_map:
1299 	devm_kfree(pcs->dev, *map);
1300 
1301 	return ret;
1302 }
1303 
1304 /**
1305  * pcs_irq_free() - free interrupt
1306  * @pcs: pcs driver instance
1307  */
1308 static void pcs_irq_free(struct pcs_device *pcs)
1309 {
1310 	struct pcs_soc_data *pcs_soc = &pcs->socdata;
1311 
1312 	if (pcs_soc->irq < 0)
1313 		return;
1314 
1315 	if (pcs->domain)
1316 		irq_domain_remove(pcs->domain);
1317 
1318 	if (PCS_QUIRK_HAS_SHARED_IRQ)
1319 		free_irq(pcs_soc->irq, pcs_soc);
1320 	else
1321 		irq_set_chained_handler(pcs_soc->irq, NULL);
1322 }
1323 
1324 /**
1325  * pcs_free_resources() - free memory used by this driver
1326  * @pcs: pcs driver instance
1327  */
1328 static void pcs_free_resources(struct pcs_device *pcs)
1329 {
1330 	pcs_irq_free(pcs);
1331 	pinctrl_unregister(pcs->pctl);
1332 
1333 #if IS_BUILTIN(CONFIG_PINCTRL_SINGLE)
1334 	if (pcs->missing_nr_pinctrl_cells)
1335 		of_remove_property(pcs->np, pcs->missing_nr_pinctrl_cells);
1336 #endif
1337 }
1338 
1339 static int pcs_add_gpio_func(struct device_node *node, struct pcs_device *pcs)
1340 {
1341 	const char *propname = "pinctrl-single,gpio-range";
1342 	const char *cellname = "#pinctrl-single,gpio-range-cells";
1343 	struct of_phandle_args gpiospec;
1344 	struct pcs_gpiofunc_range *range;
1345 	int ret, i;
1346 
1347 	for (i = 0; ; i++) {
1348 		ret = of_parse_phandle_with_args(node, propname, cellname,
1349 						 i, &gpiospec);
1350 		/* Do not treat it as error. Only treat it as end condition. */
1351 		if (ret) {
1352 			ret = 0;
1353 			break;
1354 		}
1355 		range = devm_kzalloc(pcs->dev, sizeof(*range), GFP_KERNEL);
1356 		if (!range) {
1357 			ret = -ENOMEM;
1358 			break;
1359 		}
1360 		range->offset = gpiospec.args[0];
1361 		range->npins = gpiospec.args[1];
1362 		range->gpiofunc = gpiospec.args[2];
1363 		mutex_lock(&pcs->mutex);
1364 		list_add_tail(&range->node, &pcs->gpiofuncs);
1365 		mutex_unlock(&pcs->mutex);
1366 	}
1367 	return ret;
1368 }
1369 
1370 /**
1371  * struct pcs_interrupt
1372  * @reg:	virtual address of interrupt register
1373  * @hwirq:	hardware irq number
1374  * @irq:	virtual irq number
1375  * @node:	list node
1376  */
1377 struct pcs_interrupt {
1378 	void __iomem *reg;
1379 	irq_hw_number_t hwirq;
1380 	unsigned int irq;
1381 	struct list_head node;
1382 };
1383 
1384 /**
1385  * pcs_irq_set() - enables or disables an interrupt
1386  * @pcs_soc: SoC specific settings
1387  * @irq: interrupt
1388  * @enable: enable or disable the interrupt
1389  *
1390  * Note that this currently assumes one interrupt per pinctrl
1391  * register that is typically used for wake-up events.
1392  */
1393 static inline void pcs_irq_set(struct pcs_soc_data *pcs_soc,
1394 			       int irq, const bool enable)
1395 {
1396 	struct pcs_device *pcs;
1397 	struct list_head *pos;
1398 	unsigned mask;
1399 
1400 	pcs = container_of(pcs_soc, struct pcs_device, socdata);
1401 	list_for_each(pos, &pcs->irqs) {
1402 		struct pcs_interrupt *pcswi;
1403 		unsigned soc_mask;
1404 
1405 		pcswi = list_entry(pos, struct pcs_interrupt, node);
1406 		if (irq != pcswi->irq)
1407 			continue;
1408 
1409 		soc_mask = pcs_soc->irq_enable_mask;
1410 		raw_spin_lock(&pcs->lock);
1411 		mask = pcs->read(pcswi->reg);
1412 		if (enable)
1413 			mask |= soc_mask;
1414 		else
1415 			mask &= ~soc_mask;
1416 		pcs->write(mask, pcswi->reg);
1417 
1418 		/* flush posted write */
1419 		mask = pcs->read(pcswi->reg);
1420 		raw_spin_unlock(&pcs->lock);
1421 	}
1422 
1423 	if (pcs_soc->rearm)
1424 		pcs_soc->rearm();
1425 }
1426 
1427 /**
1428  * pcs_irq_mask() - mask pinctrl interrupt
1429  * @d: interrupt data
1430  */
1431 static void pcs_irq_mask(struct irq_data *d)
1432 {
1433 	struct pcs_soc_data *pcs_soc = irq_data_get_irq_chip_data(d);
1434 
1435 	pcs_irq_set(pcs_soc, d->irq, false);
1436 }
1437 
1438 /**
1439  * pcs_irq_unmask() - unmask pinctrl interrupt
1440  * @d: interrupt data
1441  */
1442 static void pcs_irq_unmask(struct irq_data *d)
1443 {
1444 	struct pcs_soc_data *pcs_soc = irq_data_get_irq_chip_data(d);
1445 
1446 	pcs_irq_set(pcs_soc, d->irq, true);
1447 }
1448 
1449 /**
1450  * pcs_irq_set_wake() - toggle the suspend and resume wake up
1451  * @d: interrupt data
1452  * @state: wake-up state
1453  *
1454  * Note that this should be called only for suspend and resume.
1455  * For runtime PM, the wake-up events should be enabled by default.
1456  */
1457 static int pcs_irq_set_wake(struct irq_data *d, unsigned int state)
1458 {
1459 	if (state)
1460 		pcs_irq_unmask(d);
1461 	else
1462 		pcs_irq_mask(d);
1463 
1464 	return 0;
1465 }
1466 
1467 /**
1468  * pcs_irq_handle() - common interrupt handler
1469  * @pcs_soc: SoC specific settings
1470  *
1471  * Note that this currently assumes we have one interrupt bit per
1472  * mux register. This interrupt is typically used for wake-up events.
1473  * For more complex interrupts different handlers can be specified.
1474  */
1475 static int pcs_irq_handle(struct pcs_soc_data *pcs_soc)
1476 {
1477 	struct pcs_device *pcs;
1478 	struct list_head *pos;
1479 	int count = 0;
1480 
1481 	pcs = container_of(pcs_soc, struct pcs_device, socdata);
1482 	list_for_each(pos, &pcs->irqs) {
1483 		struct pcs_interrupt *pcswi;
1484 		unsigned mask;
1485 
1486 		pcswi = list_entry(pos, struct pcs_interrupt, node);
1487 		raw_spin_lock(&pcs->lock);
1488 		mask = pcs->read(pcswi->reg);
1489 		raw_spin_unlock(&pcs->lock);
1490 		if (mask & pcs_soc->irq_status_mask) {
1491 			generic_handle_domain_irq(pcs->domain,
1492 						  pcswi->hwirq);
1493 			count++;
1494 		}
1495 	}
1496 
1497 	return count;
1498 }
1499 
1500 /**
1501  * pcs_irq_handler() - handler for the shared interrupt case
1502  * @irq: interrupt
1503  * @d: data
1504  *
1505  * Use this for cases where multiple instances of
1506  * pinctrl-single share a single interrupt like on omaps.
1507  */
1508 static irqreturn_t pcs_irq_handler(int irq, void *d)
1509 {
1510 	struct pcs_soc_data *pcs_soc = d;
1511 
1512 	return pcs_irq_handle(pcs_soc) ? IRQ_HANDLED : IRQ_NONE;
1513 }
1514 
1515 /**
1516  * pcs_irq_chain_handler() - handler for the dedicated chained interrupt case
1517  * @desc: interrupt descriptor
1518  *
1519  * Use this if you have a separate interrupt for each
1520  * pinctrl-single instance.
1521  */
1522 static void pcs_irq_chain_handler(struct irq_desc *desc)
1523 {
1524 	struct pcs_soc_data *pcs_soc = irq_desc_get_handler_data(desc);
1525 	struct irq_chip *chip;
1526 
1527 	chip = irq_desc_get_chip(desc);
1528 	chained_irq_enter(chip, desc);
1529 	pcs_irq_handle(pcs_soc);
1530 	/* REVISIT: export and add handle_bad_irq(irq, desc)? */
1531 	chained_irq_exit(chip, desc);
1532 }
1533 
1534 static int pcs_irqdomain_map(struct irq_domain *d, unsigned int irq,
1535 			     irq_hw_number_t hwirq)
1536 {
1537 	struct pcs_soc_data *pcs_soc = d->host_data;
1538 	struct pcs_device *pcs;
1539 	struct pcs_interrupt *pcswi;
1540 
1541 	pcs = container_of(pcs_soc, struct pcs_device, socdata);
1542 	pcswi = devm_kzalloc(pcs->dev, sizeof(*pcswi), GFP_KERNEL);
1543 	if (!pcswi)
1544 		return -ENOMEM;
1545 
1546 	pcswi->reg = pcs->base + hwirq;
1547 	pcswi->hwirq = hwirq;
1548 	pcswi->irq = irq;
1549 
1550 	mutex_lock(&pcs->mutex);
1551 	list_add_tail(&pcswi->node, &pcs->irqs);
1552 	mutex_unlock(&pcs->mutex);
1553 
1554 	irq_set_chip_data(irq, pcs_soc);
1555 	irq_set_chip_and_handler(irq, &pcs->chip,
1556 				 handle_level_irq);
1557 	irq_set_lockdep_class(irq, &pcs_lock_class, &pcs_request_class);
1558 	irq_set_noprobe(irq);
1559 
1560 	return 0;
1561 }
1562 
1563 static const struct irq_domain_ops pcs_irqdomain_ops = {
1564 	.map = pcs_irqdomain_map,
1565 	.xlate = irq_domain_xlate_onecell,
1566 };
1567 
1568 /**
1569  * pcs_irq_init_chained_handler() - set up a chained interrupt handler
1570  * @pcs: pcs driver instance
1571  * @np: device node pointer
1572  */
1573 static int pcs_irq_init_chained_handler(struct pcs_device *pcs,
1574 					struct device_node *np)
1575 {
1576 	struct pcs_soc_data *pcs_soc = &pcs->socdata;
1577 	const char *name = "pinctrl";
1578 	int num_irqs;
1579 
1580 	if (!pcs_soc->irq_enable_mask ||
1581 	    !pcs_soc->irq_status_mask) {
1582 		pcs_soc->irq = -1;
1583 		return -EINVAL;
1584 	}
1585 
1586 	INIT_LIST_HEAD(&pcs->irqs);
1587 	pcs->chip.name = name;
1588 	pcs->chip.irq_ack = pcs_irq_mask;
1589 	pcs->chip.irq_mask = pcs_irq_mask;
1590 	pcs->chip.irq_unmask = pcs_irq_unmask;
1591 	pcs->chip.irq_set_wake = pcs_irq_set_wake;
1592 
1593 	if (PCS_QUIRK_HAS_SHARED_IRQ) {
1594 		int res;
1595 
1596 		res = request_irq(pcs_soc->irq, pcs_irq_handler,
1597 				  IRQF_SHARED | IRQF_NO_SUSPEND |
1598 				  IRQF_NO_THREAD,
1599 				  name, pcs_soc);
1600 		if (res) {
1601 			pcs_soc->irq = -1;
1602 			return res;
1603 		}
1604 	} else {
1605 		irq_set_chained_handler_and_data(pcs_soc->irq,
1606 						 pcs_irq_chain_handler,
1607 						 pcs_soc);
1608 	}
1609 
1610 	/*
1611 	 * We can use the register offset as the hardirq
1612 	 * number as irq_domain_add_simple maps them lazily.
1613 	 * This way we can easily support more than one
1614 	 * interrupt per function if needed.
1615 	 */
1616 	num_irqs = pcs->size;
1617 
1618 	pcs->domain = irq_domain_add_simple(np, num_irqs, 0,
1619 					    &pcs_irqdomain_ops,
1620 					    pcs_soc);
1621 	if (!pcs->domain) {
1622 		irq_set_chained_handler(pcs_soc->irq, NULL);
1623 		return -EINVAL;
1624 	}
1625 
1626 	return 0;
1627 }
1628 
1629 #ifdef CONFIG_PM
1630 static int pcs_save_context(struct pcs_device *pcs)
1631 {
1632 	int i, mux_bytes;
1633 	u64 *regsl;
1634 	u32 *regsw;
1635 	u16 *regshw;
1636 
1637 	mux_bytes = pcs->width / BITS_PER_BYTE;
1638 
1639 	if (!pcs->saved_vals) {
1640 		pcs->saved_vals = devm_kzalloc(pcs->dev, pcs->size, GFP_ATOMIC);
1641 		if (!pcs->saved_vals)
1642 			return -ENOMEM;
1643 	}
1644 
1645 	switch (pcs->width) {
1646 	case 64:
1647 		regsl = pcs->saved_vals;
1648 		for (i = 0; i < pcs->size; i += mux_bytes)
1649 			*regsl++ = pcs->read(pcs->base + i);
1650 		break;
1651 	case 32:
1652 		regsw = pcs->saved_vals;
1653 		for (i = 0; i < pcs->size; i += mux_bytes)
1654 			*regsw++ = pcs->read(pcs->base + i);
1655 		break;
1656 	case 16:
1657 		regshw = pcs->saved_vals;
1658 		for (i = 0; i < pcs->size; i += mux_bytes)
1659 			*regshw++ = pcs->read(pcs->base + i);
1660 		break;
1661 	}
1662 
1663 	return 0;
1664 }
1665 
1666 static void pcs_restore_context(struct pcs_device *pcs)
1667 {
1668 	int i, mux_bytes;
1669 	u64 *regsl;
1670 	u32 *regsw;
1671 	u16 *regshw;
1672 
1673 	mux_bytes = pcs->width / BITS_PER_BYTE;
1674 
1675 	switch (pcs->width) {
1676 	case 64:
1677 		regsl = pcs->saved_vals;
1678 		for (i = 0; i < pcs->size; i += mux_bytes)
1679 			pcs->write(*regsl++, pcs->base + i);
1680 		break;
1681 	case 32:
1682 		regsw = pcs->saved_vals;
1683 		for (i = 0; i < pcs->size; i += mux_bytes)
1684 			pcs->write(*regsw++, pcs->base + i);
1685 		break;
1686 	case 16:
1687 		regshw = pcs->saved_vals;
1688 		for (i = 0; i < pcs->size; i += mux_bytes)
1689 			pcs->write(*regshw++, pcs->base + i);
1690 		break;
1691 	}
1692 }
1693 
1694 static int pinctrl_single_suspend(struct platform_device *pdev,
1695 					pm_message_t state)
1696 {
1697 	struct pcs_device *pcs;
1698 
1699 	pcs = platform_get_drvdata(pdev);
1700 	if (!pcs)
1701 		return -EINVAL;
1702 
1703 	if (pcs->flags & PCS_CONTEXT_LOSS_OFF) {
1704 		int ret;
1705 
1706 		ret = pcs_save_context(pcs);
1707 		if (ret < 0)
1708 			return ret;
1709 	}
1710 
1711 	return pinctrl_force_sleep(pcs->pctl);
1712 }
1713 
1714 static int pinctrl_single_resume(struct platform_device *pdev)
1715 {
1716 	struct pcs_device *pcs;
1717 
1718 	pcs = platform_get_drvdata(pdev);
1719 	if (!pcs)
1720 		return -EINVAL;
1721 
1722 	if (pcs->flags & PCS_CONTEXT_LOSS_OFF)
1723 		pcs_restore_context(pcs);
1724 
1725 	return pinctrl_force_default(pcs->pctl);
1726 }
1727 #endif
1728 
1729 /**
1730  * pcs_quirk_missing_pinctrl_cells - handle legacy binding
1731  * @pcs: pinctrl driver instance
1732  * @np: device tree node
1733  * @cells: number of cells
1734  *
1735  * Handle legacy binding with no #pinctrl-cells. This should be
1736  * always two pinctrl-single,bit-per-mux and one for others.
1737  * At some point we may want to consider removing this.
1738  */
1739 static int pcs_quirk_missing_pinctrl_cells(struct pcs_device *pcs,
1740 					   struct device_node *np,
1741 					   int cells)
1742 {
1743 	struct property *p;
1744 	const char *name = "#pinctrl-cells";
1745 	int error;
1746 	u32 val;
1747 
1748 	error = of_property_read_u32(np, name, &val);
1749 	if (!error)
1750 		return 0;
1751 
1752 	dev_warn(pcs->dev, "please update dts to use %s = <%i>\n",
1753 		 name, cells);
1754 
1755 	p = devm_kzalloc(pcs->dev, sizeof(*p), GFP_KERNEL);
1756 	if (!p)
1757 		return -ENOMEM;
1758 
1759 	p->length = sizeof(__be32);
1760 	p->value = devm_kzalloc(pcs->dev, sizeof(__be32), GFP_KERNEL);
1761 	if (!p->value)
1762 		return -ENOMEM;
1763 	*(__be32 *)p->value = cpu_to_be32(cells);
1764 
1765 	p->name = devm_kstrdup(pcs->dev, name, GFP_KERNEL);
1766 	if (!p->name)
1767 		return -ENOMEM;
1768 
1769 	pcs->missing_nr_pinctrl_cells = p;
1770 
1771 #if IS_BUILTIN(CONFIG_PINCTRL_SINGLE)
1772 	error = of_add_property(np, pcs->missing_nr_pinctrl_cells);
1773 #endif
1774 
1775 	return error;
1776 }
1777 
1778 static int pcs_probe(struct platform_device *pdev)
1779 {
1780 	struct device_node *np = pdev->dev.of_node;
1781 	struct pcs_pdata *pdata;
1782 	struct resource *res;
1783 	struct pcs_device *pcs;
1784 	const struct pcs_soc_data *soc;
1785 	int ret;
1786 
1787 	soc = of_device_get_match_data(&pdev->dev);
1788 	if (WARN_ON(!soc))
1789 		return -EINVAL;
1790 
1791 	pcs = devm_kzalloc(&pdev->dev, sizeof(*pcs), GFP_KERNEL);
1792 	if (!pcs)
1793 		return -ENOMEM;
1794 
1795 	pcs->dev = &pdev->dev;
1796 	pcs->np = np;
1797 	raw_spin_lock_init(&pcs->lock);
1798 	mutex_init(&pcs->mutex);
1799 	INIT_LIST_HEAD(&pcs->gpiofuncs);
1800 	pcs->flags = soc->flags;
1801 	memcpy(&pcs->socdata, soc, sizeof(*soc));
1802 
1803 	ret = of_property_read_u32(np, "pinctrl-single,register-width",
1804 				   &pcs->width);
1805 	if (ret) {
1806 		dev_err(pcs->dev, "register width not specified\n");
1807 
1808 		return ret;
1809 	}
1810 
1811 	ret = of_property_read_u32(np, "pinctrl-single,function-mask",
1812 				   &pcs->fmask);
1813 	if (!ret) {
1814 		pcs->fshift = __ffs(pcs->fmask);
1815 		pcs->fmax = pcs->fmask >> pcs->fshift;
1816 	} else {
1817 		/* If mask property doesn't exist, function mux is invalid. */
1818 		pcs->fmask = 0;
1819 		pcs->fshift = 0;
1820 		pcs->fmax = 0;
1821 	}
1822 
1823 	ret = of_property_read_u32(np, "pinctrl-single,function-off",
1824 					&pcs->foff);
1825 	if (ret)
1826 		pcs->foff = PCS_OFF_DISABLED;
1827 
1828 	pcs->bits_per_mux = of_property_read_bool(np,
1829 						  "pinctrl-single,bit-per-mux");
1830 	ret = pcs_quirk_missing_pinctrl_cells(pcs, np,
1831 					      pcs->bits_per_mux ? 2 : 1);
1832 	if (ret) {
1833 		dev_err(&pdev->dev, "unable to patch #pinctrl-cells\n");
1834 
1835 		return ret;
1836 	}
1837 
1838 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1839 	if (!res) {
1840 		dev_err(pcs->dev, "could not get resource\n");
1841 		return -ENODEV;
1842 	}
1843 
1844 	pcs->res = devm_request_mem_region(pcs->dev, res->start,
1845 			resource_size(res), DRIVER_NAME);
1846 	if (!pcs->res) {
1847 		dev_err(pcs->dev, "could not get mem_region\n");
1848 		return -EBUSY;
1849 	}
1850 
1851 	pcs->size = resource_size(pcs->res);
1852 	pcs->base = devm_ioremap(pcs->dev, pcs->res->start, pcs->size);
1853 	if (!pcs->base) {
1854 		dev_err(pcs->dev, "could not ioremap\n");
1855 		return -ENODEV;
1856 	}
1857 
1858 	platform_set_drvdata(pdev, pcs);
1859 
1860 	switch (pcs->width) {
1861 	case 8:
1862 		pcs->read = pcs_readb;
1863 		pcs->write = pcs_writeb;
1864 		break;
1865 	case 16:
1866 		pcs->read = pcs_readw;
1867 		pcs->write = pcs_writew;
1868 		break;
1869 	case 32:
1870 		pcs->read = pcs_readl;
1871 		pcs->write = pcs_writel;
1872 		break;
1873 	default:
1874 		break;
1875 	}
1876 
1877 	pcs->desc.name = DRIVER_NAME;
1878 	pcs->desc.pctlops = &pcs_pinctrl_ops;
1879 	pcs->desc.pmxops = &pcs_pinmux_ops;
1880 	if (PCS_HAS_PINCONF)
1881 		pcs->desc.confops = &pcs_pinconf_ops;
1882 	pcs->desc.owner = THIS_MODULE;
1883 
1884 	ret = pcs_allocate_pin_table(pcs);
1885 	if (ret < 0)
1886 		goto free;
1887 
1888 	ret = pinctrl_register_and_init(&pcs->desc, pcs->dev, pcs, &pcs->pctl);
1889 	if (ret) {
1890 		dev_err(pcs->dev, "could not register single pinctrl driver\n");
1891 		goto free;
1892 	}
1893 
1894 	ret = pcs_add_gpio_func(np, pcs);
1895 	if (ret < 0)
1896 		goto free;
1897 
1898 	pcs->socdata.irq = irq_of_parse_and_map(np, 0);
1899 	if (pcs->socdata.irq)
1900 		pcs->flags |= PCS_FEAT_IRQ;
1901 
1902 	/* We still need auxdata for some omaps for PRM interrupts */
1903 	pdata = dev_get_platdata(&pdev->dev);
1904 	if (pdata) {
1905 		if (pdata->rearm)
1906 			pcs->socdata.rearm = pdata->rearm;
1907 		if (pdata->irq) {
1908 			pcs->socdata.irq = pdata->irq;
1909 			pcs->flags |= PCS_FEAT_IRQ;
1910 		}
1911 	}
1912 
1913 	if (PCS_HAS_IRQ) {
1914 		ret = pcs_irq_init_chained_handler(pcs, np);
1915 		if (ret < 0)
1916 			dev_warn(pcs->dev, "initialized with no interrupts\n");
1917 	}
1918 
1919 	dev_info(pcs->dev, "%i pins, size %u\n", pcs->desc.npins, pcs->size);
1920 
1921 	return pinctrl_enable(pcs->pctl);
1922 
1923 free:
1924 	pcs_free_resources(pcs);
1925 
1926 	return ret;
1927 }
1928 
1929 static int pcs_remove(struct platform_device *pdev)
1930 {
1931 	struct pcs_device *pcs = platform_get_drvdata(pdev);
1932 
1933 	if (!pcs)
1934 		return 0;
1935 
1936 	pcs_free_resources(pcs);
1937 
1938 	return 0;
1939 }
1940 
1941 static const struct pcs_soc_data pinctrl_single_omap_wkup = {
1942 	.flags = PCS_QUIRK_SHARED_IRQ,
1943 	.irq_enable_mask = (1 << 14),	/* OMAP_WAKEUP_EN */
1944 	.irq_status_mask = (1 << 15),	/* OMAP_WAKEUP_EVENT */
1945 };
1946 
1947 static const struct pcs_soc_data pinctrl_single_dra7 = {
1948 	.irq_enable_mask = (1 << 24),	/* WAKEUPENABLE */
1949 	.irq_status_mask = (1 << 25),	/* WAKEUPEVENT */
1950 };
1951 
1952 static const struct pcs_soc_data pinctrl_single_am437x = {
1953 	.flags = PCS_QUIRK_SHARED_IRQ | PCS_CONTEXT_LOSS_OFF,
1954 	.irq_enable_mask = (1 << 29),   /* OMAP_WAKEUP_EN */
1955 	.irq_status_mask = (1 << 30),   /* OMAP_WAKEUP_EVENT */
1956 };
1957 
1958 static const struct pcs_soc_data pinctrl_single = {
1959 };
1960 
1961 static const struct pcs_soc_data pinconf_single = {
1962 	.flags = PCS_FEAT_PINCONF,
1963 };
1964 
1965 static const struct of_device_id pcs_of_match[] = {
1966 	{ .compatible = "ti,omap3-padconf", .data = &pinctrl_single_omap_wkup },
1967 	{ .compatible = "ti,omap4-padconf", .data = &pinctrl_single_omap_wkup },
1968 	{ .compatible = "ti,omap5-padconf", .data = &pinctrl_single_omap_wkup },
1969 	{ .compatible = "ti,dra7-padconf", .data = &pinctrl_single_dra7 },
1970 	{ .compatible = "ti,am437-padconf", .data = &pinctrl_single_am437x },
1971 	{ .compatible = "pinctrl-single", .data = &pinctrl_single },
1972 	{ .compatible = "pinconf-single", .data = &pinconf_single },
1973 	{ },
1974 };
1975 MODULE_DEVICE_TABLE(of, pcs_of_match);
1976 
1977 static struct platform_driver pcs_driver = {
1978 	.probe		= pcs_probe,
1979 	.remove		= pcs_remove,
1980 	.driver = {
1981 		.name		= DRIVER_NAME,
1982 		.of_match_table	= pcs_of_match,
1983 	},
1984 #ifdef CONFIG_PM
1985 	.suspend = pinctrl_single_suspend,
1986 	.resume = pinctrl_single_resume,
1987 #endif
1988 };
1989 
1990 module_platform_driver(pcs_driver);
1991 
1992 MODULE_AUTHOR("Tony Lindgren <tony@atomide.com>");
1993 MODULE_DESCRIPTION("One-register-per-pin type device tree based pinctrl driver");
1994 MODULE_LICENSE("GPL v2");
1995