1 /* 2 * Generic device tree based pinctrl driver for one register per pin 3 * type pinmux controllers 4 * 5 * Copyright (C) 2012 Texas Instruments, Inc. 6 * 7 * This file is licensed under the terms of the GNU General Public 8 * License version 2. This program is licensed "as is" without any 9 * warranty of any kind, whether express or implied. 10 */ 11 12 #include <linux/init.h> 13 #include <linux/module.h> 14 #include <linux/io.h> 15 #include <linux/slab.h> 16 #include <linux/err.h> 17 #include <linux/list.h> 18 #include <linux/interrupt.h> 19 20 #include <linux/irqchip/chained_irq.h> 21 22 #include <linux/of.h> 23 #include <linux/of_device.h> 24 #include <linux/of_address.h> 25 #include <linux/of_irq.h> 26 27 #include <linux/pinctrl/pinctrl.h> 28 #include <linux/pinctrl/pinmux.h> 29 #include <linux/pinctrl/pinconf-generic.h> 30 31 #include <linux/platform_data/pinctrl-single.h> 32 33 #include "core.h" 34 #include "devicetree.h" 35 #include "pinconf.h" 36 #include "pinmux.h" 37 38 #define DRIVER_NAME "pinctrl-single" 39 #define PCS_OFF_DISABLED ~0U 40 41 /** 42 * struct pcs_func_vals - mux function register offset and value pair 43 * @reg: register virtual address 44 * @val: register value 45 * @mask: mask 46 */ 47 struct pcs_func_vals { 48 void __iomem *reg; 49 unsigned val; 50 unsigned mask; 51 }; 52 53 /** 54 * struct pcs_conf_vals - pinconf parameter, pinconf register offset 55 * and value, enable, disable, mask 56 * @param: config parameter 57 * @val: user input bits in the pinconf register 58 * @enable: enable bits in the pinconf register 59 * @disable: disable bits in the pinconf register 60 * @mask: mask bits in the register value 61 */ 62 struct pcs_conf_vals { 63 enum pin_config_param param; 64 unsigned val; 65 unsigned enable; 66 unsigned disable; 67 unsigned mask; 68 }; 69 70 /** 71 * struct pcs_conf_type - pinconf property name, pinconf param pair 72 * @name: property name in DTS file 73 * @param: config parameter 74 */ 75 struct pcs_conf_type { 76 const char *name; 77 enum pin_config_param param; 78 }; 79 80 /** 81 * struct pcs_function - pinctrl function 82 * @name: pinctrl function name 83 * @vals: register and vals array 84 * @nvals: number of entries in vals array 85 * @pgnames: array of pingroup names the function uses 86 * @npgnames: number of pingroup names the function uses 87 * @conf: array of pin configurations 88 * @nconfs: number of pin configurations available 89 * @node: list node 90 */ 91 struct pcs_function { 92 const char *name; 93 struct pcs_func_vals *vals; 94 unsigned nvals; 95 const char **pgnames; 96 int npgnames; 97 struct pcs_conf_vals *conf; 98 int nconfs; 99 struct list_head node; 100 }; 101 102 /** 103 * struct pcs_gpiofunc_range - pin ranges with same mux value of gpio function 104 * @offset: offset base of pins 105 * @npins: number pins with the same mux value of gpio function 106 * @gpiofunc: mux value of gpio function 107 * @node: list node 108 */ 109 struct pcs_gpiofunc_range { 110 unsigned offset; 111 unsigned npins; 112 unsigned gpiofunc; 113 struct list_head node; 114 }; 115 116 /** 117 * struct pcs_data - wrapper for data needed by pinctrl framework 118 * @pa: pindesc array 119 * @cur: index to current element 120 * 121 * REVISIT: We should be able to drop this eventually by adding 122 * support for registering pins individually in the pinctrl 123 * framework for those drivers that don't need a static array. 124 */ 125 struct pcs_data { 126 struct pinctrl_pin_desc *pa; 127 int cur; 128 }; 129 130 /** 131 * struct pcs_soc_data - SoC specific settings 132 * @flags: initial SoC specific PCS_FEAT_xxx values 133 * @irq: optional interrupt for the controller 134 * @irq_enable_mask: optional SoC specific interrupt enable mask 135 * @irq_status_mask: optional SoC specific interrupt status mask 136 * @rearm: optional SoC specific wake-up rearm function 137 */ 138 struct pcs_soc_data { 139 unsigned flags; 140 int irq; 141 unsigned irq_enable_mask; 142 unsigned irq_status_mask; 143 void (*rearm)(void); 144 }; 145 146 /** 147 * struct pcs_device - pinctrl device instance 148 * @res: resources 149 * @base: virtual address of the controller 150 * @saved_vals: saved values for the controller 151 * @size: size of the ioremapped area 152 * @dev: device entry 153 * @np: device tree node 154 * @pctl: pin controller device 155 * @flags: mask of PCS_FEAT_xxx values 156 * @missing_nr_pinctrl_cells: for legacy binding, may go away 157 * @socdata: soc specific data 158 * @lock: spinlock for register access 159 * @mutex: mutex protecting the lists 160 * @width: bits per mux register 161 * @fmask: function register mask 162 * @fshift: function register shift 163 * @foff: value to turn mux off 164 * @fmax: max number of functions in fmask 165 * @bits_per_mux: number of bits per mux 166 * @bits_per_pin: number of bits per pin 167 * @pins: physical pins on the SoC 168 * @gpiofuncs: list of gpio functions 169 * @irqs: list of interrupt registers 170 * @chip: chip container for this instance 171 * @domain: IRQ domain for this instance 172 * @desc: pin controller descriptor 173 * @read: register read function to use 174 * @write: register write function to use 175 */ 176 struct pcs_device { 177 struct resource *res; 178 void __iomem *base; 179 void *saved_vals; 180 unsigned size; 181 struct device *dev; 182 struct device_node *np; 183 struct pinctrl_dev *pctl; 184 unsigned flags; 185 #define PCS_CONTEXT_LOSS_OFF (1 << 3) 186 #define PCS_QUIRK_SHARED_IRQ (1 << 2) 187 #define PCS_FEAT_IRQ (1 << 1) 188 #define PCS_FEAT_PINCONF (1 << 0) 189 struct property *missing_nr_pinctrl_cells; 190 struct pcs_soc_data socdata; 191 raw_spinlock_t lock; 192 struct mutex mutex; 193 unsigned width; 194 unsigned fmask; 195 unsigned fshift; 196 unsigned foff; 197 unsigned fmax; 198 bool bits_per_mux; 199 unsigned bits_per_pin; 200 struct pcs_data pins; 201 struct list_head gpiofuncs; 202 struct list_head irqs; 203 struct irq_chip chip; 204 struct irq_domain *domain; 205 struct pinctrl_desc desc; 206 unsigned (*read)(void __iomem *reg); 207 void (*write)(unsigned val, void __iomem *reg); 208 }; 209 210 #define PCS_QUIRK_HAS_SHARED_IRQ (pcs->flags & PCS_QUIRK_SHARED_IRQ) 211 #define PCS_HAS_IRQ (pcs->flags & PCS_FEAT_IRQ) 212 #define PCS_HAS_PINCONF (pcs->flags & PCS_FEAT_PINCONF) 213 214 static int pcs_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin, 215 unsigned long *config); 216 static int pcs_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin, 217 unsigned long *configs, unsigned num_configs); 218 219 static enum pin_config_param pcs_bias[] = { 220 PIN_CONFIG_BIAS_PULL_DOWN, 221 PIN_CONFIG_BIAS_PULL_UP, 222 }; 223 224 /* 225 * This lock class tells lockdep that irqchip core that this single 226 * pinctrl can be in a different category than its parents, so it won't 227 * report false recursion. 228 */ 229 static struct lock_class_key pcs_lock_class; 230 231 /* Class for the IRQ request mutex */ 232 static struct lock_class_key pcs_request_class; 233 234 /* 235 * REVISIT: Reads and writes could eventually use regmap or something 236 * generic. But at least on omaps, some mux registers are performance 237 * critical as they may need to be remuxed every time before and after 238 * idle. Adding tests for register access width for every read and 239 * write like regmap is doing is not desired, and caching the registers 240 * does not help in this case. 241 */ 242 243 static unsigned __maybe_unused pcs_readb(void __iomem *reg) 244 { 245 return readb(reg); 246 } 247 248 static unsigned __maybe_unused pcs_readw(void __iomem *reg) 249 { 250 return readw(reg); 251 } 252 253 static unsigned __maybe_unused pcs_readl(void __iomem *reg) 254 { 255 return readl(reg); 256 } 257 258 static void __maybe_unused pcs_writeb(unsigned val, void __iomem *reg) 259 { 260 writeb(val, reg); 261 } 262 263 static void __maybe_unused pcs_writew(unsigned val, void __iomem *reg) 264 { 265 writew(val, reg); 266 } 267 268 static void __maybe_unused pcs_writel(unsigned val, void __iomem *reg) 269 { 270 writel(val, reg); 271 } 272 273 static unsigned int pcs_pin_reg_offset_get(struct pcs_device *pcs, 274 unsigned int pin) 275 { 276 unsigned int mux_bytes = pcs->width / BITS_PER_BYTE; 277 278 if (pcs->bits_per_mux) { 279 unsigned int pin_offset_bytes; 280 281 pin_offset_bytes = (pcs->bits_per_pin * pin) / BITS_PER_BYTE; 282 return (pin_offset_bytes / mux_bytes) * mux_bytes; 283 } 284 285 return pin * mux_bytes; 286 } 287 288 static unsigned int pcs_pin_shift_reg_get(struct pcs_device *pcs, 289 unsigned int pin) 290 { 291 return (pin % (pcs->width / pcs->bits_per_pin)) * pcs->bits_per_pin; 292 } 293 294 static void pcs_pin_dbg_show(struct pinctrl_dev *pctldev, 295 struct seq_file *s, 296 unsigned pin) 297 { 298 struct pcs_device *pcs; 299 unsigned int val; 300 unsigned long offset; 301 size_t pa; 302 303 pcs = pinctrl_dev_get_drvdata(pctldev); 304 305 offset = pcs_pin_reg_offset_get(pcs, pin); 306 val = pcs->read(pcs->base + offset); 307 308 if (pcs->bits_per_mux) 309 val &= pcs->fmask << pcs_pin_shift_reg_get(pcs, pin); 310 311 pa = pcs->res->start + offset; 312 313 seq_printf(s, "%zx %08x %s ", pa, val, DRIVER_NAME); 314 } 315 316 static void pcs_dt_free_map(struct pinctrl_dev *pctldev, 317 struct pinctrl_map *map, unsigned num_maps) 318 { 319 struct pcs_device *pcs; 320 321 pcs = pinctrl_dev_get_drvdata(pctldev); 322 devm_kfree(pcs->dev, map); 323 } 324 325 static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev, 326 struct device_node *np_config, 327 struct pinctrl_map **map, unsigned *num_maps); 328 329 static const struct pinctrl_ops pcs_pinctrl_ops = { 330 .get_groups_count = pinctrl_generic_get_group_count, 331 .get_group_name = pinctrl_generic_get_group_name, 332 .get_group_pins = pinctrl_generic_get_group_pins, 333 .pin_dbg_show = pcs_pin_dbg_show, 334 .dt_node_to_map = pcs_dt_node_to_map, 335 .dt_free_map = pcs_dt_free_map, 336 }; 337 338 static int pcs_get_function(struct pinctrl_dev *pctldev, unsigned pin, 339 struct pcs_function **func) 340 { 341 struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev); 342 struct pin_desc *pdesc = pin_desc_get(pctldev, pin); 343 const struct pinctrl_setting_mux *setting; 344 struct function_desc *function; 345 unsigned fselector; 346 347 /* If pin is not described in DTS & enabled, mux_setting is NULL. */ 348 setting = pdesc->mux_setting; 349 if (!setting) 350 return -ENOTSUPP; 351 fselector = setting->func; 352 function = pinmux_generic_get_function(pctldev, fselector); 353 *func = function->data; 354 if (!(*func)) { 355 dev_err(pcs->dev, "%s could not find function%i\n", 356 __func__, fselector); 357 return -ENOTSUPP; 358 } 359 return 0; 360 } 361 362 static int pcs_set_mux(struct pinctrl_dev *pctldev, unsigned fselector, 363 unsigned group) 364 { 365 struct pcs_device *pcs; 366 struct function_desc *function; 367 struct pcs_function *func; 368 int i; 369 370 pcs = pinctrl_dev_get_drvdata(pctldev); 371 /* If function mask is null, needn't enable it. */ 372 if (!pcs->fmask) 373 return 0; 374 function = pinmux_generic_get_function(pctldev, fselector); 375 func = function->data; 376 if (!func) 377 return -EINVAL; 378 379 dev_dbg(pcs->dev, "enabling %s function%i\n", 380 func->name, fselector); 381 382 for (i = 0; i < func->nvals; i++) { 383 struct pcs_func_vals *vals; 384 unsigned long flags; 385 unsigned val, mask; 386 387 vals = &func->vals[i]; 388 raw_spin_lock_irqsave(&pcs->lock, flags); 389 val = pcs->read(vals->reg); 390 391 if (pcs->bits_per_mux) 392 mask = vals->mask; 393 else 394 mask = pcs->fmask; 395 396 val &= ~mask; 397 val |= (vals->val & mask); 398 pcs->write(val, vals->reg); 399 raw_spin_unlock_irqrestore(&pcs->lock, flags); 400 } 401 402 return 0; 403 } 404 405 static int pcs_request_gpio(struct pinctrl_dev *pctldev, 406 struct pinctrl_gpio_range *range, unsigned pin) 407 { 408 struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev); 409 struct pcs_gpiofunc_range *frange = NULL; 410 struct list_head *pos, *tmp; 411 unsigned data; 412 413 /* If function mask is null, return directly. */ 414 if (!pcs->fmask) 415 return -ENOTSUPP; 416 417 list_for_each_safe(pos, tmp, &pcs->gpiofuncs) { 418 u32 offset; 419 420 frange = list_entry(pos, struct pcs_gpiofunc_range, node); 421 if (pin >= frange->offset + frange->npins 422 || pin < frange->offset) 423 continue; 424 425 offset = pcs_pin_reg_offset_get(pcs, pin); 426 427 if (pcs->bits_per_mux) { 428 int pin_shift = pcs_pin_shift_reg_get(pcs, pin); 429 430 data = pcs->read(pcs->base + offset); 431 data &= ~(pcs->fmask << pin_shift); 432 data |= frange->gpiofunc << pin_shift; 433 pcs->write(data, pcs->base + offset); 434 } else { 435 data = pcs->read(pcs->base + offset); 436 data &= ~pcs->fmask; 437 data |= frange->gpiofunc; 438 pcs->write(data, pcs->base + offset); 439 } 440 break; 441 } 442 return 0; 443 } 444 445 static const struct pinmux_ops pcs_pinmux_ops = { 446 .get_functions_count = pinmux_generic_get_function_count, 447 .get_function_name = pinmux_generic_get_function_name, 448 .get_function_groups = pinmux_generic_get_function_groups, 449 .set_mux = pcs_set_mux, 450 .gpio_request_enable = pcs_request_gpio, 451 }; 452 453 /* Clear BIAS value */ 454 static void pcs_pinconf_clear_bias(struct pinctrl_dev *pctldev, unsigned pin) 455 { 456 unsigned long config; 457 int i; 458 for (i = 0; i < ARRAY_SIZE(pcs_bias); i++) { 459 config = pinconf_to_config_packed(pcs_bias[i], 0); 460 pcs_pinconf_set(pctldev, pin, &config, 1); 461 } 462 } 463 464 /* 465 * Check whether PIN_CONFIG_BIAS_DISABLE is valid. 466 * It's depend on that PULL_DOWN & PULL_UP configs are all invalid. 467 */ 468 static bool pcs_pinconf_bias_disable(struct pinctrl_dev *pctldev, unsigned pin) 469 { 470 unsigned long config; 471 int i; 472 473 for (i = 0; i < ARRAY_SIZE(pcs_bias); i++) { 474 config = pinconf_to_config_packed(pcs_bias[i], 0); 475 if (!pcs_pinconf_get(pctldev, pin, &config)) 476 goto out; 477 } 478 return true; 479 out: 480 return false; 481 } 482 483 static int pcs_pinconf_get(struct pinctrl_dev *pctldev, 484 unsigned pin, unsigned long *config) 485 { 486 struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev); 487 struct pcs_function *func; 488 enum pin_config_param param; 489 unsigned offset = 0, data = 0, i, j, ret; 490 491 ret = pcs_get_function(pctldev, pin, &func); 492 if (ret) 493 return ret; 494 495 for (i = 0; i < func->nconfs; i++) { 496 param = pinconf_to_config_param(*config); 497 if (param == PIN_CONFIG_BIAS_DISABLE) { 498 if (pcs_pinconf_bias_disable(pctldev, pin)) { 499 *config = 0; 500 return 0; 501 } else { 502 return -ENOTSUPP; 503 } 504 } else if (param != func->conf[i].param) { 505 continue; 506 } 507 508 offset = pin * (pcs->width / BITS_PER_BYTE); 509 data = pcs->read(pcs->base + offset) & func->conf[i].mask; 510 switch (func->conf[i].param) { 511 /* 4 parameters */ 512 case PIN_CONFIG_BIAS_PULL_DOWN: 513 case PIN_CONFIG_BIAS_PULL_UP: 514 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 515 if ((data != func->conf[i].enable) || 516 (data == func->conf[i].disable)) 517 return -ENOTSUPP; 518 *config = 0; 519 break; 520 /* 2 parameters */ 521 case PIN_CONFIG_INPUT_SCHMITT: 522 for (j = 0; j < func->nconfs; j++) { 523 switch (func->conf[j].param) { 524 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 525 if (data != func->conf[j].enable) 526 return -ENOTSUPP; 527 break; 528 default: 529 break; 530 } 531 } 532 *config = data; 533 break; 534 case PIN_CONFIG_DRIVE_STRENGTH: 535 case PIN_CONFIG_SLEW_RATE: 536 case PIN_CONFIG_MODE_LOW_POWER: 537 case PIN_CONFIG_INPUT_ENABLE: 538 default: 539 *config = data; 540 break; 541 } 542 return 0; 543 } 544 return -ENOTSUPP; 545 } 546 547 static int pcs_pinconf_set(struct pinctrl_dev *pctldev, 548 unsigned pin, unsigned long *configs, 549 unsigned num_configs) 550 { 551 struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev); 552 struct pcs_function *func; 553 unsigned offset = 0, shift = 0, i, data, ret; 554 u32 arg; 555 int j; 556 557 ret = pcs_get_function(pctldev, pin, &func); 558 if (ret) 559 return ret; 560 561 for (j = 0; j < num_configs; j++) { 562 for (i = 0; i < func->nconfs; i++) { 563 if (pinconf_to_config_param(configs[j]) 564 != func->conf[i].param) 565 continue; 566 567 offset = pin * (pcs->width / BITS_PER_BYTE); 568 data = pcs->read(pcs->base + offset); 569 arg = pinconf_to_config_argument(configs[j]); 570 switch (func->conf[i].param) { 571 /* 2 parameters */ 572 case PIN_CONFIG_INPUT_SCHMITT: 573 case PIN_CONFIG_DRIVE_STRENGTH: 574 case PIN_CONFIG_SLEW_RATE: 575 case PIN_CONFIG_MODE_LOW_POWER: 576 case PIN_CONFIG_INPUT_ENABLE: 577 shift = ffs(func->conf[i].mask) - 1; 578 data &= ~func->conf[i].mask; 579 data |= (arg << shift) & func->conf[i].mask; 580 break; 581 /* 4 parameters */ 582 case PIN_CONFIG_BIAS_DISABLE: 583 pcs_pinconf_clear_bias(pctldev, pin); 584 break; 585 case PIN_CONFIG_BIAS_PULL_DOWN: 586 case PIN_CONFIG_BIAS_PULL_UP: 587 if (arg) 588 pcs_pinconf_clear_bias(pctldev, pin); 589 fallthrough; 590 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 591 data &= ~func->conf[i].mask; 592 if (arg) 593 data |= func->conf[i].enable; 594 else 595 data |= func->conf[i].disable; 596 break; 597 default: 598 return -ENOTSUPP; 599 } 600 pcs->write(data, pcs->base + offset); 601 602 break; 603 } 604 if (i >= func->nconfs) 605 return -ENOTSUPP; 606 } /* for each config */ 607 608 return 0; 609 } 610 611 static int pcs_pinconf_group_get(struct pinctrl_dev *pctldev, 612 unsigned group, unsigned long *config) 613 { 614 const unsigned *pins; 615 unsigned npins, old = 0; 616 int i, ret; 617 618 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); 619 if (ret) 620 return ret; 621 for (i = 0; i < npins; i++) { 622 if (pcs_pinconf_get(pctldev, pins[i], config)) 623 return -ENOTSUPP; 624 /* configs do not match between two pins */ 625 if (i && (old != *config)) 626 return -ENOTSUPP; 627 old = *config; 628 } 629 return 0; 630 } 631 632 static int pcs_pinconf_group_set(struct pinctrl_dev *pctldev, 633 unsigned group, unsigned long *configs, 634 unsigned num_configs) 635 { 636 const unsigned *pins; 637 unsigned npins; 638 int i, ret; 639 640 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); 641 if (ret) 642 return ret; 643 for (i = 0; i < npins; i++) { 644 if (pcs_pinconf_set(pctldev, pins[i], configs, num_configs)) 645 return -ENOTSUPP; 646 } 647 return 0; 648 } 649 650 static void pcs_pinconf_dbg_show(struct pinctrl_dev *pctldev, 651 struct seq_file *s, unsigned pin) 652 { 653 } 654 655 static void pcs_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, 656 struct seq_file *s, unsigned selector) 657 { 658 } 659 660 static void pcs_pinconf_config_dbg_show(struct pinctrl_dev *pctldev, 661 struct seq_file *s, 662 unsigned long config) 663 { 664 pinconf_generic_dump_config(pctldev, s, config); 665 } 666 667 static const struct pinconf_ops pcs_pinconf_ops = { 668 .pin_config_get = pcs_pinconf_get, 669 .pin_config_set = pcs_pinconf_set, 670 .pin_config_group_get = pcs_pinconf_group_get, 671 .pin_config_group_set = pcs_pinconf_group_set, 672 .pin_config_dbg_show = pcs_pinconf_dbg_show, 673 .pin_config_group_dbg_show = pcs_pinconf_group_dbg_show, 674 .pin_config_config_dbg_show = pcs_pinconf_config_dbg_show, 675 .is_generic = true, 676 }; 677 678 /** 679 * pcs_add_pin() - add a pin to the static per controller pin array 680 * @pcs: pcs driver instance 681 * @offset: register offset from base 682 */ 683 static int pcs_add_pin(struct pcs_device *pcs, unsigned int offset) 684 { 685 struct pcs_soc_data *pcs_soc = &pcs->socdata; 686 struct pinctrl_pin_desc *pin; 687 int i; 688 689 i = pcs->pins.cur; 690 if (i >= pcs->desc.npins) { 691 dev_err(pcs->dev, "too many pins, max %i\n", 692 pcs->desc.npins); 693 return -ENOMEM; 694 } 695 696 if (pcs_soc->irq_enable_mask) { 697 unsigned val; 698 699 val = pcs->read(pcs->base + offset); 700 if (val & pcs_soc->irq_enable_mask) { 701 dev_dbg(pcs->dev, "irq enabled at boot for pin at %lx (%x), clearing\n", 702 (unsigned long)pcs->res->start + offset, val); 703 val &= ~pcs_soc->irq_enable_mask; 704 pcs->write(val, pcs->base + offset); 705 } 706 } 707 708 pin = &pcs->pins.pa[i]; 709 pin->number = i; 710 pcs->pins.cur++; 711 712 return i; 713 } 714 715 /** 716 * pcs_allocate_pin_table() - adds all the pins for the pinctrl driver 717 * @pcs: pcs driver instance 718 * 719 * In case of errors, resources are freed in pcs_free_resources. 720 * 721 * If your hardware needs holes in the address space, then just set 722 * up multiple driver instances. 723 */ 724 static int pcs_allocate_pin_table(struct pcs_device *pcs) 725 { 726 int mux_bytes, nr_pins, i; 727 728 mux_bytes = pcs->width / BITS_PER_BYTE; 729 730 if (pcs->bits_per_mux) { 731 pcs->bits_per_pin = fls(pcs->fmask); 732 nr_pins = (pcs->size * BITS_PER_BYTE) / pcs->bits_per_pin; 733 } else { 734 nr_pins = pcs->size / mux_bytes; 735 } 736 737 dev_dbg(pcs->dev, "allocating %i pins\n", nr_pins); 738 pcs->pins.pa = devm_kcalloc(pcs->dev, 739 nr_pins, sizeof(*pcs->pins.pa), 740 GFP_KERNEL); 741 if (!pcs->pins.pa) 742 return -ENOMEM; 743 744 pcs->desc.pins = pcs->pins.pa; 745 pcs->desc.npins = nr_pins; 746 747 for (i = 0; i < pcs->desc.npins; i++) { 748 unsigned offset; 749 int res; 750 751 offset = pcs_pin_reg_offset_get(pcs, i); 752 res = pcs_add_pin(pcs, offset); 753 if (res < 0) { 754 dev_err(pcs->dev, "error adding pins: %i\n", res); 755 return res; 756 } 757 } 758 759 return 0; 760 } 761 762 /** 763 * pcs_add_function() - adds a new function to the function list 764 * @pcs: pcs driver instance 765 * @fcn: new function allocated 766 * @name: name of the function 767 * @vals: array of mux register value pairs used by the function 768 * @nvals: number of mux register value pairs 769 * @pgnames: array of pingroup names for the function 770 * @npgnames: number of pingroup names 771 * 772 * Caller must take care of locking. 773 */ 774 static int pcs_add_function(struct pcs_device *pcs, 775 struct pcs_function **fcn, 776 const char *name, 777 struct pcs_func_vals *vals, 778 unsigned int nvals, 779 const char **pgnames, 780 unsigned int npgnames) 781 { 782 struct pcs_function *function; 783 int selector; 784 785 function = devm_kzalloc(pcs->dev, sizeof(*function), GFP_KERNEL); 786 if (!function) 787 return -ENOMEM; 788 789 function->vals = vals; 790 function->nvals = nvals; 791 function->name = name; 792 793 selector = pinmux_generic_add_function(pcs->pctl, name, 794 pgnames, npgnames, 795 function); 796 if (selector < 0) { 797 devm_kfree(pcs->dev, function); 798 *fcn = NULL; 799 } else { 800 *fcn = function; 801 } 802 803 return selector; 804 } 805 806 /** 807 * pcs_get_pin_by_offset() - get a pin index based on the register offset 808 * @pcs: pcs driver instance 809 * @offset: register offset from the base 810 * 811 * Note that this is OK as long as the pins are in a static array. 812 */ 813 static int pcs_get_pin_by_offset(struct pcs_device *pcs, unsigned offset) 814 { 815 unsigned index; 816 817 if (offset >= pcs->size) { 818 dev_err(pcs->dev, "mux offset out of range: 0x%x (0x%x)\n", 819 offset, pcs->size); 820 return -EINVAL; 821 } 822 823 if (pcs->bits_per_mux) 824 index = (offset * BITS_PER_BYTE) / pcs->bits_per_pin; 825 else 826 index = offset / (pcs->width / BITS_PER_BYTE); 827 828 return index; 829 } 830 831 /* 832 * check whether data matches enable bits or disable bits 833 * Return value: 1 for matching enable bits, 0 for matching disable bits, 834 * and negative value for matching failure. 835 */ 836 static int pcs_config_match(unsigned data, unsigned enable, unsigned disable) 837 { 838 int ret = -EINVAL; 839 840 if (data == enable) 841 ret = 1; 842 else if (data == disable) 843 ret = 0; 844 return ret; 845 } 846 847 static void add_config(struct pcs_conf_vals **conf, enum pin_config_param param, 848 unsigned value, unsigned enable, unsigned disable, 849 unsigned mask) 850 { 851 (*conf)->param = param; 852 (*conf)->val = value; 853 (*conf)->enable = enable; 854 (*conf)->disable = disable; 855 (*conf)->mask = mask; 856 (*conf)++; 857 } 858 859 static void add_setting(unsigned long **setting, enum pin_config_param param, 860 unsigned arg) 861 { 862 **setting = pinconf_to_config_packed(param, arg); 863 (*setting)++; 864 } 865 866 /* add pinconf setting with 2 parameters */ 867 static void pcs_add_conf2(struct pcs_device *pcs, struct device_node *np, 868 const char *name, enum pin_config_param param, 869 struct pcs_conf_vals **conf, unsigned long **settings) 870 { 871 unsigned value[2], shift; 872 int ret; 873 874 ret = of_property_read_u32_array(np, name, value, 2); 875 if (ret) 876 return; 877 /* set value & mask */ 878 value[0] &= value[1]; 879 shift = ffs(value[1]) - 1; 880 /* skip enable & disable */ 881 add_config(conf, param, value[0], 0, 0, value[1]); 882 add_setting(settings, param, value[0] >> shift); 883 } 884 885 /* add pinconf setting with 4 parameters */ 886 static void pcs_add_conf4(struct pcs_device *pcs, struct device_node *np, 887 const char *name, enum pin_config_param param, 888 struct pcs_conf_vals **conf, unsigned long **settings) 889 { 890 unsigned value[4]; 891 int ret; 892 893 /* value to set, enable, disable, mask */ 894 ret = of_property_read_u32_array(np, name, value, 4); 895 if (ret) 896 return; 897 if (!value[3]) { 898 dev_err(pcs->dev, "mask field of the property can't be 0\n"); 899 return; 900 } 901 value[0] &= value[3]; 902 value[1] &= value[3]; 903 value[2] &= value[3]; 904 ret = pcs_config_match(value[0], value[1], value[2]); 905 if (ret < 0) 906 dev_dbg(pcs->dev, "failed to match enable or disable bits\n"); 907 add_config(conf, param, value[0], value[1], value[2], value[3]); 908 add_setting(settings, param, ret); 909 } 910 911 static int pcs_parse_pinconf(struct pcs_device *pcs, struct device_node *np, 912 struct pcs_function *func, 913 struct pinctrl_map **map) 914 915 { 916 struct pinctrl_map *m = *map; 917 int i = 0, nconfs = 0; 918 unsigned long *settings = NULL, *s = NULL; 919 struct pcs_conf_vals *conf = NULL; 920 static const struct pcs_conf_type prop2[] = { 921 { "pinctrl-single,drive-strength", PIN_CONFIG_DRIVE_STRENGTH, }, 922 { "pinctrl-single,slew-rate", PIN_CONFIG_SLEW_RATE, }, 923 { "pinctrl-single,input-enable", PIN_CONFIG_INPUT_ENABLE, }, 924 { "pinctrl-single,input-schmitt", PIN_CONFIG_INPUT_SCHMITT, }, 925 { "pinctrl-single,low-power-mode", PIN_CONFIG_MODE_LOW_POWER, }, 926 }; 927 static const struct pcs_conf_type prop4[] = { 928 { "pinctrl-single,bias-pullup", PIN_CONFIG_BIAS_PULL_UP, }, 929 { "pinctrl-single,bias-pulldown", PIN_CONFIG_BIAS_PULL_DOWN, }, 930 { "pinctrl-single,input-schmitt-enable", 931 PIN_CONFIG_INPUT_SCHMITT_ENABLE, }, 932 }; 933 934 /* If pinconf isn't supported, don't parse properties in below. */ 935 if (!PCS_HAS_PINCONF) 936 return -ENOTSUPP; 937 938 /* cacluate how much properties are supported in current node */ 939 for (i = 0; i < ARRAY_SIZE(prop2); i++) { 940 if (of_find_property(np, prop2[i].name, NULL)) 941 nconfs++; 942 } 943 for (i = 0; i < ARRAY_SIZE(prop4); i++) { 944 if (of_find_property(np, prop4[i].name, NULL)) 945 nconfs++; 946 } 947 if (!nconfs) 948 return -ENOTSUPP; 949 950 func->conf = devm_kcalloc(pcs->dev, 951 nconfs, sizeof(struct pcs_conf_vals), 952 GFP_KERNEL); 953 if (!func->conf) 954 return -ENOMEM; 955 func->nconfs = nconfs; 956 conf = &(func->conf[0]); 957 m++; 958 settings = devm_kcalloc(pcs->dev, nconfs, sizeof(unsigned long), 959 GFP_KERNEL); 960 if (!settings) 961 return -ENOMEM; 962 s = &settings[0]; 963 964 for (i = 0; i < ARRAY_SIZE(prop2); i++) 965 pcs_add_conf2(pcs, np, prop2[i].name, prop2[i].param, 966 &conf, &s); 967 for (i = 0; i < ARRAY_SIZE(prop4); i++) 968 pcs_add_conf4(pcs, np, prop4[i].name, prop4[i].param, 969 &conf, &s); 970 m->type = PIN_MAP_TYPE_CONFIGS_GROUP; 971 m->data.configs.group_or_pin = np->name; 972 m->data.configs.configs = settings; 973 m->data.configs.num_configs = nconfs; 974 return 0; 975 } 976 977 /** 978 * pcs_parse_one_pinctrl_entry() - parses a device tree mux entry 979 * @pcs: pinctrl driver instance 980 * @np: device node of the mux entry 981 * @map: map entry 982 * @num_maps: number of map 983 * @pgnames: pingroup names 984 * 985 * Note that this binding currently supports only sets of one register + value. 986 * 987 * Also note that this driver tries to avoid understanding pin and function 988 * names because of the extra bloat they would cause especially in the case of 989 * a large number of pins. This driver just sets what is specified for the board 990 * in the .dts file. Further user space debugging tools can be developed to 991 * decipher the pin and function names using debugfs. 992 * 993 * If you are concerned about the boot time, set up the static pins in 994 * the bootloader, and only set up selected pins as device tree entries. 995 */ 996 static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs, 997 struct device_node *np, 998 struct pinctrl_map **map, 999 unsigned *num_maps, 1000 const char **pgnames) 1001 { 1002 const char *name = "pinctrl-single,pins"; 1003 struct pcs_func_vals *vals; 1004 int rows, *pins, found = 0, res = -ENOMEM, i, fsel, gsel; 1005 struct pcs_function *function = NULL; 1006 1007 rows = pinctrl_count_index_with_args(np, name); 1008 if (rows <= 0) { 1009 dev_err(pcs->dev, "Invalid number of rows: %d\n", rows); 1010 return -EINVAL; 1011 } 1012 1013 vals = devm_kcalloc(pcs->dev, rows, sizeof(*vals), GFP_KERNEL); 1014 if (!vals) 1015 return -ENOMEM; 1016 1017 pins = devm_kcalloc(pcs->dev, rows, sizeof(*pins), GFP_KERNEL); 1018 if (!pins) 1019 goto free_vals; 1020 1021 for (i = 0; i < rows; i++) { 1022 struct of_phandle_args pinctrl_spec; 1023 unsigned int offset; 1024 int pin; 1025 1026 res = pinctrl_parse_index_with_args(np, name, i, &pinctrl_spec); 1027 if (res) 1028 return res; 1029 1030 if (pinctrl_spec.args_count < 2 || pinctrl_spec.args_count > 3) { 1031 dev_err(pcs->dev, "invalid args_count for spec: %i\n", 1032 pinctrl_spec.args_count); 1033 break; 1034 } 1035 1036 offset = pinctrl_spec.args[0]; 1037 vals[found].reg = pcs->base + offset; 1038 1039 switch (pinctrl_spec.args_count) { 1040 case 2: 1041 vals[found].val = pinctrl_spec.args[1]; 1042 break; 1043 case 3: 1044 vals[found].val = (pinctrl_spec.args[1] | pinctrl_spec.args[2]); 1045 break; 1046 } 1047 1048 dev_dbg(pcs->dev, "%pOFn index: 0x%x value: 0x%x\n", 1049 pinctrl_spec.np, offset, vals[found].val); 1050 1051 pin = pcs_get_pin_by_offset(pcs, offset); 1052 if (pin < 0) { 1053 dev_err(pcs->dev, 1054 "could not add functions for %pOFn %ux\n", 1055 np, offset); 1056 break; 1057 } 1058 pins[found++] = pin; 1059 } 1060 1061 pgnames[0] = np->name; 1062 mutex_lock(&pcs->mutex); 1063 fsel = pcs_add_function(pcs, &function, np->name, vals, found, 1064 pgnames, 1); 1065 if (fsel < 0) { 1066 res = fsel; 1067 goto free_pins; 1068 } 1069 1070 gsel = pinctrl_generic_add_group(pcs->pctl, np->name, pins, found, pcs); 1071 if (gsel < 0) { 1072 res = gsel; 1073 goto free_function; 1074 } 1075 1076 (*map)->type = PIN_MAP_TYPE_MUX_GROUP; 1077 (*map)->data.mux.group = np->name; 1078 (*map)->data.mux.function = np->name; 1079 1080 if (PCS_HAS_PINCONF && function) { 1081 res = pcs_parse_pinconf(pcs, np, function, map); 1082 if (res == 0) 1083 *num_maps = 2; 1084 else if (res == -ENOTSUPP) 1085 *num_maps = 1; 1086 else 1087 goto free_pingroups; 1088 } else { 1089 *num_maps = 1; 1090 } 1091 mutex_unlock(&pcs->mutex); 1092 1093 return 0; 1094 1095 free_pingroups: 1096 pinctrl_generic_remove_group(pcs->pctl, gsel); 1097 *num_maps = 1; 1098 free_function: 1099 pinmux_generic_remove_function(pcs->pctl, fsel); 1100 free_pins: 1101 mutex_unlock(&pcs->mutex); 1102 devm_kfree(pcs->dev, pins); 1103 1104 free_vals: 1105 devm_kfree(pcs->dev, vals); 1106 1107 return res; 1108 } 1109 1110 static int pcs_parse_bits_in_pinctrl_entry(struct pcs_device *pcs, 1111 struct device_node *np, 1112 struct pinctrl_map **map, 1113 unsigned *num_maps, 1114 const char **pgnames) 1115 { 1116 const char *name = "pinctrl-single,bits"; 1117 struct pcs_func_vals *vals; 1118 int rows, *pins, found = 0, res = -ENOMEM, i, fsel, gsel; 1119 int npins_in_row; 1120 struct pcs_function *function = NULL; 1121 1122 rows = pinctrl_count_index_with_args(np, name); 1123 if (rows <= 0) { 1124 dev_err(pcs->dev, "Invalid number of rows: %d\n", rows); 1125 return -EINVAL; 1126 } 1127 1128 npins_in_row = pcs->width / pcs->bits_per_pin; 1129 1130 vals = devm_kzalloc(pcs->dev, 1131 array3_size(rows, npins_in_row, sizeof(*vals)), 1132 GFP_KERNEL); 1133 if (!vals) 1134 return -ENOMEM; 1135 1136 pins = devm_kzalloc(pcs->dev, 1137 array3_size(rows, npins_in_row, sizeof(*pins)), 1138 GFP_KERNEL); 1139 if (!pins) 1140 goto free_vals; 1141 1142 for (i = 0; i < rows; i++) { 1143 struct of_phandle_args pinctrl_spec; 1144 unsigned offset, val; 1145 unsigned mask, bit_pos, val_pos, mask_pos, submask; 1146 unsigned pin_num_from_lsb; 1147 int pin; 1148 1149 res = pinctrl_parse_index_with_args(np, name, i, &pinctrl_spec); 1150 if (res) 1151 return res; 1152 1153 if (pinctrl_spec.args_count < 3) { 1154 dev_err(pcs->dev, "invalid args_count for spec: %i\n", 1155 pinctrl_spec.args_count); 1156 break; 1157 } 1158 1159 /* Index plus two value cells */ 1160 offset = pinctrl_spec.args[0]; 1161 val = pinctrl_spec.args[1]; 1162 mask = pinctrl_spec.args[2]; 1163 1164 dev_dbg(pcs->dev, "%pOFn index: 0x%x value: 0x%x mask: 0x%x\n", 1165 pinctrl_spec.np, offset, val, mask); 1166 1167 /* Parse pins in each row from LSB */ 1168 while (mask) { 1169 bit_pos = __ffs(mask); 1170 pin_num_from_lsb = bit_pos / pcs->bits_per_pin; 1171 mask_pos = ((pcs->fmask) << bit_pos); 1172 val_pos = val & mask_pos; 1173 submask = mask & mask_pos; 1174 1175 if ((mask & mask_pos) == 0) { 1176 dev_err(pcs->dev, 1177 "Invalid mask for %pOFn at 0x%x\n", 1178 np, offset); 1179 break; 1180 } 1181 1182 mask &= ~mask_pos; 1183 1184 if (submask != mask_pos) { 1185 dev_warn(pcs->dev, 1186 "Invalid submask 0x%x for %pOFn at 0x%x\n", 1187 submask, np, offset); 1188 continue; 1189 } 1190 1191 vals[found].mask = submask; 1192 vals[found].reg = pcs->base + offset; 1193 vals[found].val = val_pos; 1194 1195 pin = pcs_get_pin_by_offset(pcs, offset); 1196 if (pin < 0) { 1197 dev_err(pcs->dev, 1198 "could not add functions for %pOFn %ux\n", 1199 np, offset); 1200 break; 1201 } 1202 pins[found++] = pin + pin_num_from_lsb; 1203 } 1204 } 1205 1206 pgnames[0] = np->name; 1207 mutex_lock(&pcs->mutex); 1208 fsel = pcs_add_function(pcs, &function, np->name, vals, found, 1209 pgnames, 1); 1210 if (fsel < 0) { 1211 res = fsel; 1212 goto free_pins; 1213 } 1214 1215 gsel = pinctrl_generic_add_group(pcs->pctl, np->name, pins, found, pcs); 1216 if (gsel < 0) { 1217 res = gsel; 1218 goto free_function; 1219 } 1220 1221 (*map)->type = PIN_MAP_TYPE_MUX_GROUP; 1222 (*map)->data.mux.group = np->name; 1223 (*map)->data.mux.function = np->name; 1224 1225 if (PCS_HAS_PINCONF) { 1226 dev_err(pcs->dev, "pinconf not supported\n"); 1227 res = -ENOTSUPP; 1228 goto free_pingroups; 1229 } 1230 1231 *num_maps = 1; 1232 mutex_unlock(&pcs->mutex); 1233 1234 return 0; 1235 1236 free_pingroups: 1237 pinctrl_generic_remove_group(pcs->pctl, gsel); 1238 *num_maps = 1; 1239 free_function: 1240 pinmux_generic_remove_function(pcs->pctl, fsel); 1241 free_pins: 1242 mutex_unlock(&pcs->mutex); 1243 devm_kfree(pcs->dev, pins); 1244 1245 free_vals: 1246 devm_kfree(pcs->dev, vals); 1247 1248 return res; 1249 } 1250 /** 1251 * pcs_dt_node_to_map() - allocates and parses pinctrl maps 1252 * @pctldev: pinctrl instance 1253 * @np_config: device tree pinmux entry 1254 * @map: array of map entries 1255 * @num_maps: number of maps 1256 */ 1257 static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev, 1258 struct device_node *np_config, 1259 struct pinctrl_map **map, unsigned *num_maps) 1260 { 1261 struct pcs_device *pcs; 1262 const char **pgnames; 1263 int ret; 1264 1265 pcs = pinctrl_dev_get_drvdata(pctldev); 1266 1267 /* create 2 maps. One is for pinmux, and the other is for pinconf. */ 1268 *map = devm_kcalloc(pcs->dev, 2, sizeof(**map), GFP_KERNEL); 1269 if (!*map) 1270 return -ENOMEM; 1271 1272 *num_maps = 0; 1273 1274 pgnames = devm_kzalloc(pcs->dev, sizeof(*pgnames), GFP_KERNEL); 1275 if (!pgnames) { 1276 ret = -ENOMEM; 1277 goto free_map; 1278 } 1279 1280 if (pcs->bits_per_mux) { 1281 ret = pcs_parse_bits_in_pinctrl_entry(pcs, np_config, map, 1282 num_maps, pgnames); 1283 if (ret < 0) { 1284 dev_err(pcs->dev, "no pins entries for %pOFn\n", 1285 np_config); 1286 goto free_pgnames; 1287 } 1288 } else { 1289 ret = pcs_parse_one_pinctrl_entry(pcs, np_config, map, 1290 num_maps, pgnames); 1291 if (ret < 0) { 1292 dev_err(pcs->dev, "no pins entries for %pOFn\n", 1293 np_config); 1294 goto free_pgnames; 1295 } 1296 } 1297 1298 return 0; 1299 1300 free_pgnames: 1301 devm_kfree(pcs->dev, pgnames); 1302 free_map: 1303 devm_kfree(pcs->dev, *map); 1304 1305 return ret; 1306 } 1307 1308 /** 1309 * pcs_irq_free() - free interrupt 1310 * @pcs: pcs driver instance 1311 */ 1312 static void pcs_irq_free(struct pcs_device *pcs) 1313 { 1314 struct pcs_soc_data *pcs_soc = &pcs->socdata; 1315 1316 if (pcs_soc->irq < 0) 1317 return; 1318 1319 if (pcs->domain) 1320 irq_domain_remove(pcs->domain); 1321 1322 if (PCS_QUIRK_HAS_SHARED_IRQ) 1323 free_irq(pcs_soc->irq, pcs_soc); 1324 else 1325 irq_set_chained_handler(pcs_soc->irq, NULL); 1326 } 1327 1328 /** 1329 * pcs_free_resources() - free memory used by this driver 1330 * @pcs: pcs driver instance 1331 */ 1332 static void pcs_free_resources(struct pcs_device *pcs) 1333 { 1334 pcs_irq_free(pcs); 1335 pinctrl_unregister(pcs->pctl); 1336 1337 #if IS_BUILTIN(CONFIG_PINCTRL_SINGLE) 1338 if (pcs->missing_nr_pinctrl_cells) 1339 of_remove_property(pcs->np, pcs->missing_nr_pinctrl_cells); 1340 #endif 1341 } 1342 1343 static int pcs_add_gpio_func(struct device_node *node, struct pcs_device *pcs) 1344 { 1345 const char *propname = "pinctrl-single,gpio-range"; 1346 const char *cellname = "#pinctrl-single,gpio-range-cells"; 1347 struct of_phandle_args gpiospec; 1348 struct pcs_gpiofunc_range *range; 1349 int ret, i; 1350 1351 for (i = 0; ; i++) { 1352 ret = of_parse_phandle_with_args(node, propname, cellname, 1353 i, &gpiospec); 1354 /* Do not treat it as error. Only treat it as end condition. */ 1355 if (ret) { 1356 ret = 0; 1357 break; 1358 } 1359 range = devm_kzalloc(pcs->dev, sizeof(*range), GFP_KERNEL); 1360 if (!range) { 1361 ret = -ENOMEM; 1362 break; 1363 } 1364 range->offset = gpiospec.args[0]; 1365 range->npins = gpiospec.args[1]; 1366 range->gpiofunc = gpiospec.args[2]; 1367 mutex_lock(&pcs->mutex); 1368 list_add_tail(&range->node, &pcs->gpiofuncs); 1369 mutex_unlock(&pcs->mutex); 1370 } 1371 return ret; 1372 } 1373 1374 /** 1375 * struct pcs_interrupt 1376 * @reg: virtual address of interrupt register 1377 * @hwirq: hardware irq number 1378 * @irq: virtual irq number 1379 * @node: list node 1380 */ 1381 struct pcs_interrupt { 1382 void __iomem *reg; 1383 irq_hw_number_t hwirq; 1384 unsigned int irq; 1385 struct list_head node; 1386 }; 1387 1388 /** 1389 * pcs_irq_set() - enables or disables an interrupt 1390 * @pcs_soc: SoC specific settings 1391 * @irq: interrupt 1392 * @enable: enable or disable the interrupt 1393 * 1394 * Note that this currently assumes one interrupt per pinctrl 1395 * register that is typically used for wake-up events. 1396 */ 1397 static inline void pcs_irq_set(struct pcs_soc_data *pcs_soc, 1398 int irq, const bool enable) 1399 { 1400 struct pcs_device *pcs; 1401 struct list_head *pos; 1402 unsigned mask; 1403 1404 pcs = container_of(pcs_soc, struct pcs_device, socdata); 1405 list_for_each(pos, &pcs->irqs) { 1406 struct pcs_interrupt *pcswi; 1407 unsigned soc_mask; 1408 1409 pcswi = list_entry(pos, struct pcs_interrupt, node); 1410 if (irq != pcswi->irq) 1411 continue; 1412 1413 soc_mask = pcs_soc->irq_enable_mask; 1414 raw_spin_lock(&pcs->lock); 1415 mask = pcs->read(pcswi->reg); 1416 if (enable) 1417 mask |= soc_mask; 1418 else 1419 mask &= ~soc_mask; 1420 pcs->write(mask, pcswi->reg); 1421 1422 /* flush posted write */ 1423 mask = pcs->read(pcswi->reg); 1424 raw_spin_unlock(&pcs->lock); 1425 } 1426 1427 if (pcs_soc->rearm) 1428 pcs_soc->rearm(); 1429 } 1430 1431 /** 1432 * pcs_irq_mask() - mask pinctrl interrupt 1433 * @d: interrupt data 1434 */ 1435 static void pcs_irq_mask(struct irq_data *d) 1436 { 1437 struct pcs_soc_data *pcs_soc = irq_data_get_irq_chip_data(d); 1438 1439 pcs_irq_set(pcs_soc, d->irq, false); 1440 } 1441 1442 /** 1443 * pcs_irq_unmask() - unmask pinctrl interrupt 1444 * @d: interrupt data 1445 */ 1446 static void pcs_irq_unmask(struct irq_data *d) 1447 { 1448 struct pcs_soc_data *pcs_soc = irq_data_get_irq_chip_data(d); 1449 1450 pcs_irq_set(pcs_soc, d->irq, true); 1451 } 1452 1453 /** 1454 * pcs_irq_set_wake() - toggle the suspend and resume wake up 1455 * @d: interrupt data 1456 * @state: wake-up state 1457 * 1458 * Note that this should be called only for suspend and resume. 1459 * For runtime PM, the wake-up events should be enabled by default. 1460 */ 1461 static int pcs_irq_set_wake(struct irq_data *d, unsigned int state) 1462 { 1463 if (state) 1464 pcs_irq_unmask(d); 1465 else 1466 pcs_irq_mask(d); 1467 1468 return 0; 1469 } 1470 1471 /** 1472 * pcs_irq_handle() - common interrupt handler 1473 * @pcs_soc: SoC specific settings 1474 * 1475 * Note that this currently assumes we have one interrupt bit per 1476 * mux register. This interrupt is typically used for wake-up events. 1477 * For more complex interrupts different handlers can be specified. 1478 */ 1479 static int pcs_irq_handle(struct pcs_soc_data *pcs_soc) 1480 { 1481 struct pcs_device *pcs; 1482 struct list_head *pos; 1483 int count = 0; 1484 1485 pcs = container_of(pcs_soc, struct pcs_device, socdata); 1486 list_for_each(pos, &pcs->irqs) { 1487 struct pcs_interrupt *pcswi; 1488 unsigned mask; 1489 1490 pcswi = list_entry(pos, struct pcs_interrupt, node); 1491 raw_spin_lock(&pcs->lock); 1492 mask = pcs->read(pcswi->reg); 1493 raw_spin_unlock(&pcs->lock); 1494 if (mask & pcs_soc->irq_status_mask) { 1495 generic_handle_irq(irq_find_mapping(pcs->domain, 1496 pcswi->hwirq)); 1497 count++; 1498 } 1499 } 1500 1501 return count; 1502 } 1503 1504 /** 1505 * pcs_irq_handler() - handler for the shared interrupt case 1506 * @irq: interrupt 1507 * @d: data 1508 * 1509 * Use this for cases where multiple instances of 1510 * pinctrl-single share a single interrupt like on omaps. 1511 */ 1512 static irqreturn_t pcs_irq_handler(int irq, void *d) 1513 { 1514 struct pcs_soc_data *pcs_soc = d; 1515 1516 return pcs_irq_handle(pcs_soc) ? IRQ_HANDLED : IRQ_NONE; 1517 } 1518 1519 /** 1520 * pcs_irq_chain_handler() - handler for the dedicated chained interrupt case 1521 * @desc: interrupt descriptor 1522 * 1523 * Use this if you have a separate interrupt for each 1524 * pinctrl-single instance. 1525 */ 1526 static void pcs_irq_chain_handler(struct irq_desc *desc) 1527 { 1528 struct pcs_soc_data *pcs_soc = irq_desc_get_handler_data(desc); 1529 struct irq_chip *chip; 1530 1531 chip = irq_desc_get_chip(desc); 1532 chained_irq_enter(chip, desc); 1533 pcs_irq_handle(pcs_soc); 1534 /* REVISIT: export and add handle_bad_irq(irq, desc)? */ 1535 chained_irq_exit(chip, desc); 1536 } 1537 1538 static int pcs_irqdomain_map(struct irq_domain *d, unsigned int irq, 1539 irq_hw_number_t hwirq) 1540 { 1541 struct pcs_soc_data *pcs_soc = d->host_data; 1542 struct pcs_device *pcs; 1543 struct pcs_interrupt *pcswi; 1544 1545 pcs = container_of(pcs_soc, struct pcs_device, socdata); 1546 pcswi = devm_kzalloc(pcs->dev, sizeof(*pcswi), GFP_KERNEL); 1547 if (!pcswi) 1548 return -ENOMEM; 1549 1550 pcswi->reg = pcs->base + hwirq; 1551 pcswi->hwirq = hwirq; 1552 pcswi->irq = irq; 1553 1554 mutex_lock(&pcs->mutex); 1555 list_add_tail(&pcswi->node, &pcs->irqs); 1556 mutex_unlock(&pcs->mutex); 1557 1558 irq_set_chip_data(irq, pcs_soc); 1559 irq_set_chip_and_handler(irq, &pcs->chip, 1560 handle_level_irq); 1561 irq_set_lockdep_class(irq, &pcs_lock_class, &pcs_request_class); 1562 irq_set_noprobe(irq); 1563 1564 return 0; 1565 } 1566 1567 static const struct irq_domain_ops pcs_irqdomain_ops = { 1568 .map = pcs_irqdomain_map, 1569 .xlate = irq_domain_xlate_onecell, 1570 }; 1571 1572 /** 1573 * pcs_irq_init_chained_handler() - set up a chained interrupt handler 1574 * @pcs: pcs driver instance 1575 * @np: device node pointer 1576 */ 1577 static int pcs_irq_init_chained_handler(struct pcs_device *pcs, 1578 struct device_node *np) 1579 { 1580 struct pcs_soc_data *pcs_soc = &pcs->socdata; 1581 const char *name = "pinctrl"; 1582 int num_irqs; 1583 1584 if (!pcs_soc->irq_enable_mask || 1585 !pcs_soc->irq_status_mask) { 1586 pcs_soc->irq = -1; 1587 return -EINVAL; 1588 } 1589 1590 INIT_LIST_HEAD(&pcs->irqs); 1591 pcs->chip.name = name; 1592 pcs->chip.irq_ack = pcs_irq_mask; 1593 pcs->chip.irq_mask = pcs_irq_mask; 1594 pcs->chip.irq_unmask = pcs_irq_unmask; 1595 pcs->chip.irq_set_wake = pcs_irq_set_wake; 1596 1597 if (PCS_QUIRK_HAS_SHARED_IRQ) { 1598 int res; 1599 1600 res = request_irq(pcs_soc->irq, pcs_irq_handler, 1601 IRQF_SHARED | IRQF_NO_SUSPEND | 1602 IRQF_NO_THREAD, 1603 name, pcs_soc); 1604 if (res) { 1605 pcs_soc->irq = -1; 1606 return res; 1607 } 1608 } else { 1609 irq_set_chained_handler_and_data(pcs_soc->irq, 1610 pcs_irq_chain_handler, 1611 pcs_soc); 1612 } 1613 1614 /* 1615 * We can use the register offset as the hardirq 1616 * number as irq_domain_add_simple maps them lazily. 1617 * This way we can easily support more than one 1618 * interrupt per function if needed. 1619 */ 1620 num_irqs = pcs->size; 1621 1622 pcs->domain = irq_domain_add_simple(np, num_irqs, 0, 1623 &pcs_irqdomain_ops, 1624 pcs_soc); 1625 if (!pcs->domain) { 1626 irq_set_chained_handler(pcs_soc->irq, NULL); 1627 return -EINVAL; 1628 } 1629 1630 return 0; 1631 } 1632 1633 #ifdef CONFIG_PM 1634 static int pcs_save_context(struct pcs_device *pcs) 1635 { 1636 int i, mux_bytes; 1637 u64 *regsl; 1638 u32 *regsw; 1639 u16 *regshw; 1640 1641 mux_bytes = pcs->width / BITS_PER_BYTE; 1642 1643 if (!pcs->saved_vals) { 1644 pcs->saved_vals = devm_kzalloc(pcs->dev, pcs->size, GFP_ATOMIC); 1645 if (!pcs->saved_vals) 1646 return -ENOMEM; 1647 } 1648 1649 switch (pcs->width) { 1650 case 64: 1651 regsl = pcs->saved_vals; 1652 for (i = 0; i < pcs->size; i += mux_bytes) 1653 *regsl++ = pcs->read(pcs->base + i); 1654 break; 1655 case 32: 1656 regsw = pcs->saved_vals; 1657 for (i = 0; i < pcs->size; i += mux_bytes) 1658 *regsw++ = pcs->read(pcs->base + i); 1659 break; 1660 case 16: 1661 regshw = pcs->saved_vals; 1662 for (i = 0; i < pcs->size; i += mux_bytes) 1663 *regshw++ = pcs->read(pcs->base + i); 1664 break; 1665 } 1666 1667 return 0; 1668 } 1669 1670 static void pcs_restore_context(struct pcs_device *pcs) 1671 { 1672 int i, mux_bytes; 1673 u64 *regsl; 1674 u32 *regsw; 1675 u16 *regshw; 1676 1677 mux_bytes = pcs->width / BITS_PER_BYTE; 1678 1679 switch (pcs->width) { 1680 case 64: 1681 regsl = pcs->saved_vals; 1682 for (i = 0; i < pcs->size; i += mux_bytes) 1683 pcs->write(*regsl++, pcs->base + i); 1684 break; 1685 case 32: 1686 regsw = pcs->saved_vals; 1687 for (i = 0; i < pcs->size; i += mux_bytes) 1688 pcs->write(*regsw++, pcs->base + i); 1689 break; 1690 case 16: 1691 regshw = pcs->saved_vals; 1692 for (i = 0; i < pcs->size; i += mux_bytes) 1693 pcs->write(*regshw++, pcs->base + i); 1694 break; 1695 } 1696 } 1697 1698 static int pinctrl_single_suspend(struct platform_device *pdev, 1699 pm_message_t state) 1700 { 1701 struct pcs_device *pcs; 1702 1703 pcs = platform_get_drvdata(pdev); 1704 if (!pcs) 1705 return -EINVAL; 1706 1707 if (pcs->flags & PCS_CONTEXT_LOSS_OFF) { 1708 int ret; 1709 1710 ret = pcs_save_context(pcs); 1711 if (ret < 0) 1712 return ret; 1713 } 1714 1715 return pinctrl_force_sleep(pcs->pctl); 1716 } 1717 1718 static int pinctrl_single_resume(struct platform_device *pdev) 1719 { 1720 struct pcs_device *pcs; 1721 1722 pcs = platform_get_drvdata(pdev); 1723 if (!pcs) 1724 return -EINVAL; 1725 1726 if (pcs->flags & PCS_CONTEXT_LOSS_OFF) 1727 pcs_restore_context(pcs); 1728 1729 return pinctrl_force_default(pcs->pctl); 1730 } 1731 #endif 1732 1733 /** 1734 * pcs_quirk_missing_pinctrl_cells - handle legacy binding 1735 * @pcs: pinctrl driver instance 1736 * @np: device tree node 1737 * @cells: number of cells 1738 * 1739 * Handle legacy binding with no #pinctrl-cells. This should be 1740 * always two pinctrl-single,bit-per-mux and one for others. 1741 * At some point we may want to consider removing this. 1742 */ 1743 static int pcs_quirk_missing_pinctrl_cells(struct pcs_device *pcs, 1744 struct device_node *np, 1745 int cells) 1746 { 1747 struct property *p; 1748 const char *name = "#pinctrl-cells"; 1749 int error; 1750 u32 val; 1751 1752 error = of_property_read_u32(np, name, &val); 1753 if (!error) 1754 return 0; 1755 1756 dev_warn(pcs->dev, "please update dts to use %s = <%i>\n", 1757 name, cells); 1758 1759 p = devm_kzalloc(pcs->dev, sizeof(*p), GFP_KERNEL); 1760 if (!p) 1761 return -ENOMEM; 1762 1763 p->length = sizeof(__be32); 1764 p->value = devm_kzalloc(pcs->dev, sizeof(__be32), GFP_KERNEL); 1765 if (!p->value) 1766 return -ENOMEM; 1767 *(__be32 *)p->value = cpu_to_be32(cells); 1768 1769 p->name = devm_kstrdup(pcs->dev, name, GFP_KERNEL); 1770 if (!p->name) 1771 return -ENOMEM; 1772 1773 pcs->missing_nr_pinctrl_cells = p; 1774 1775 #if IS_BUILTIN(CONFIG_PINCTRL_SINGLE) 1776 error = of_add_property(np, pcs->missing_nr_pinctrl_cells); 1777 #endif 1778 1779 return error; 1780 } 1781 1782 static int pcs_probe(struct platform_device *pdev) 1783 { 1784 struct device_node *np = pdev->dev.of_node; 1785 struct pcs_pdata *pdata; 1786 struct resource *res; 1787 struct pcs_device *pcs; 1788 const struct pcs_soc_data *soc; 1789 int ret; 1790 1791 soc = of_device_get_match_data(&pdev->dev); 1792 if (WARN_ON(!soc)) 1793 return -EINVAL; 1794 1795 pcs = devm_kzalloc(&pdev->dev, sizeof(*pcs), GFP_KERNEL); 1796 if (!pcs) 1797 return -ENOMEM; 1798 1799 pcs->dev = &pdev->dev; 1800 pcs->np = np; 1801 raw_spin_lock_init(&pcs->lock); 1802 mutex_init(&pcs->mutex); 1803 INIT_LIST_HEAD(&pcs->gpiofuncs); 1804 pcs->flags = soc->flags; 1805 memcpy(&pcs->socdata, soc, sizeof(*soc)); 1806 1807 ret = of_property_read_u32(np, "pinctrl-single,register-width", 1808 &pcs->width); 1809 if (ret) { 1810 dev_err(pcs->dev, "register width not specified\n"); 1811 1812 return ret; 1813 } 1814 1815 ret = of_property_read_u32(np, "pinctrl-single,function-mask", 1816 &pcs->fmask); 1817 if (!ret) { 1818 pcs->fshift = __ffs(pcs->fmask); 1819 pcs->fmax = pcs->fmask >> pcs->fshift; 1820 } else { 1821 /* If mask property doesn't exist, function mux is invalid. */ 1822 pcs->fmask = 0; 1823 pcs->fshift = 0; 1824 pcs->fmax = 0; 1825 } 1826 1827 ret = of_property_read_u32(np, "pinctrl-single,function-off", 1828 &pcs->foff); 1829 if (ret) 1830 pcs->foff = PCS_OFF_DISABLED; 1831 1832 pcs->bits_per_mux = of_property_read_bool(np, 1833 "pinctrl-single,bit-per-mux"); 1834 ret = pcs_quirk_missing_pinctrl_cells(pcs, np, 1835 pcs->bits_per_mux ? 2 : 1); 1836 if (ret) { 1837 dev_err(&pdev->dev, "unable to patch #pinctrl-cells\n"); 1838 1839 return ret; 1840 } 1841 1842 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1843 if (!res) { 1844 dev_err(pcs->dev, "could not get resource\n"); 1845 return -ENODEV; 1846 } 1847 1848 pcs->res = devm_request_mem_region(pcs->dev, res->start, 1849 resource_size(res), DRIVER_NAME); 1850 if (!pcs->res) { 1851 dev_err(pcs->dev, "could not get mem_region\n"); 1852 return -EBUSY; 1853 } 1854 1855 pcs->size = resource_size(pcs->res); 1856 pcs->base = devm_ioremap(pcs->dev, pcs->res->start, pcs->size); 1857 if (!pcs->base) { 1858 dev_err(pcs->dev, "could not ioremap\n"); 1859 return -ENODEV; 1860 } 1861 1862 platform_set_drvdata(pdev, pcs); 1863 1864 switch (pcs->width) { 1865 case 8: 1866 pcs->read = pcs_readb; 1867 pcs->write = pcs_writeb; 1868 break; 1869 case 16: 1870 pcs->read = pcs_readw; 1871 pcs->write = pcs_writew; 1872 break; 1873 case 32: 1874 pcs->read = pcs_readl; 1875 pcs->write = pcs_writel; 1876 break; 1877 default: 1878 break; 1879 } 1880 1881 pcs->desc.name = DRIVER_NAME; 1882 pcs->desc.pctlops = &pcs_pinctrl_ops; 1883 pcs->desc.pmxops = &pcs_pinmux_ops; 1884 if (PCS_HAS_PINCONF) 1885 pcs->desc.confops = &pcs_pinconf_ops; 1886 pcs->desc.owner = THIS_MODULE; 1887 1888 ret = pcs_allocate_pin_table(pcs); 1889 if (ret < 0) 1890 goto free; 1891 1892 ret = pinctrl_register_and_init(&pcs->desc, pcs->dev, pcs, &pcs->pctl); 1893 if (ret) { 1894 dev_err(pcs->dev, "could not register single pinctrl driver\n"); 1895 goto free; 1896 } 1897 1898 ret = pcs_add_gpio_func(np, pcs); 1899 if (ret < 0) 1900 goto free; 1901 1902 pcs->socdata.irq = irq_of_parse_and_map(np, 0); 1903 if (pcs->socdata.irq) 1904 pcs->flags |= PCS_FEAT_IRQ; 1905 1906 /* We still need auxdata for some omaps for PRM interrupts */ 1907 pdata = dev_get_platdata(&pdev->dev); 1908 if (pdata) { 1909 if (pdata->rearm) 1910 pcs->socdata.rearm = pdata->rearm; 1911 if (pdata->irq) { 1912 pcs->socdata.irq = pdata->irq; 1913 pcs->flags |= PCS_FEAT_IRQ; 1914 } 1915 } 1916 1917 if (PCS_HAS_IRQ) { 1918 ret = pcs_irq_init_chained_handler(pcs, np); 1919 if (ret < 0) 1920 dev_warn(pcs->dev, "initialized with no interrupts\n"); 1921 } 1922 1923 dev_info(pcs->dev, "%i pins, size %u\n", pcs->desc.npins, pcs->size); 1924 1925 return pinctrl_enable(pcs->pctl); 1926 1927 free: 1928 pcs_free_resources(pcs); 1929 1930 return ret; 1931 } 1932 1933 static int pcs_remove(struct platform_device *pdev) 1934 { 1935 struct pcs_device *pcs = platform_get_drvdata(pdev); 1936 1937 if (!pcs) 1938 return 0; 1939 1940 pcs_free_resources(pcs); 1941 1942 return 0; 1943 } 1944 1945 static const struct pcs_soc_data pinctrl_single_omap_wkup = { 1946 .flags = PCS_QUIRK_SHARED_IRQ, 1947 .irq_enable_mask = (1 << 14), /* OMAP_WAKEUP_EN */ 1948 .irq_status_mask = (1 << 15), /* OMAP_WAKEUP_EVENT */ 1949 }; 1950 1951 static const struct pcs_soc_data pinctrl_single_dra7 = { 1952 .irq_enable_mask = (1 << 24), /* WAKEUPENABLE */ 1953 .irq_status_mask = (1 << 25), /* WAKEUPEVENT */ 1954 }; 1955 1956 static const struct pcs_soc_data pinctrl_single_am437x = { 1957 .flags = PCS_QUIRK_SHARED_IRQ | PCS_CONTEXT_LOSS_OFF, 1958 .irq_enable_mask = (1 << 29), /* OMAP_WAKEUP_EN */ 1959 .irq_status_mask = (1 << 30), /* OMAP_WAKEUP_EVENT */ 1960 }; 1961 1962 static const struct pcs_soc_data pinctrl_single = { 1963 }; 1964 1965 static const struct pcs_soc_data pinconf_single = { 1966 .flags = PCS_FEAT_PINCONF, 1967 }; 1968 1969 static const struct of_device_id pcs_of_match[] = { 1970 { .compatible = "ti,omap3-padconf", .data = &pinctrl_single_omap_wkup }, 1971 { .compatible = "ti,omap4-padconf", .data = &pinctrl_single_omap_wkup }, 1972 { .compatible = "ti,omap5-padconf", .data = &pinctrl_single_omap_wkup }, 1973 { .compatible = "ti,dra7-padconf", .data = &pinctrl_single_dra7 }, 1974 { .compatible = "ti,am437-padconf", .data = &pinctrl_single_am437x }, 1975 { .compatible = "pinctrl-single", .data = &pinctrl_single }, 1976 { .compatible = "pinconf-single", .data = &pinconf_single }, 1977 { }, 1978 }; 1979 MODULE_DEVICE_TABLE(of, pcs_of_match); 1980 1981 static struct platform_driver pcs_driver = { 1982 .probe = pcs_probe, 1983 .remove = pcs_remove, 1984 .driver = { 1985 .name = DRIVER_NAME, 1986 .of_match_table = pcs_of_match, 1987 }, 1988 #ifdef CONFIG_PM 1989 .suspend = pinctrl_single_suspend, 1990 .resume = pinctrl_single_resume, 1991 #endif 1992 }; 1993 1994 module_platform_driver(pcs_driver); 1995 1996 MODULE_AUTHOR("Tony Lindgren <tony@atomide.com>"); 1997 MODULE_DESCRIPTION("One-register-per-pin type device tree based pinctrl driver"); 1998 MODULE_LICENSE("GPL v2"); 1999