1 /* 2 * Generic device tree based pinctrl driver for one register per pin 3 * type pinmux controllers 4 * 5 * Copyright (C) 2012 Texas Instruments, Inc. 6 * 7 * This file is licensed under the terms of the GNU General Public 8 * License version 2. This program is licensed "as is" without any 9 * warranty of any kind, whether express or implied. 10 */ 11 12 #include <linux/init.h> 13 #include <linux/module.h> 14 #include <linux/io.h> 15 #include <linux/slab.h> 16 #include <linux/err.h> 17 #include <linux/list.h> 18 #include <linux/interrupt.h> 19 20 #include <linux/irqchip/chained_irq.h> 21 22 #include <linux/of.h> 23 #include <linux/of_device.h> 24 #include <linux/of_address.h> 25 #include <linux/of_irq.h> 26 27 #include <linux/pinctrl/pinctrl.h> 28 #include <linux/pinctrl/pinmux.h> 29 #include <linux/pinctrl/pinconf-generic.h> 30 31 #include <linux/platform_data/pinctrl-single.h> 32 33 #include "core.h" 34 #include "pinconf.h" 35 36 #define DRIVER_NAME "pinctrl-single" 37 #define PCS_MUX_PINS_NAME "pinctrl-single,pins" 38 #define PCS_MUX_BITS_NAME "pinctrl-single,bits" 39 #define PCS_OFF_DISABLED ~0U 40 41 /** 42 * struct pcs_pingroup - pingroups for a function 43 * @np: pingroup device node pointer 44 * @name: pingroup name 45 * @gpins: array of the pins in the group 46 * @ngpins: number of pins in the group 47 * @node: list node 48 */ 49 struct pcs_pingroup { 50 struct device_node *np; 51 const char *name; 52 int *gpins; 53 int ngpins; 54 struct list_head node; 55 }; 56 57 /** 58 * struct pcs_func_vals - mux function register offset and value pair 59 * @reg: register virtual address 60 * @val: register value 61 */ 62 struct pcs_func_vals { 63 void __iomem *reg; 64 unsigned val; 65 unsigned mask; 66 }; 67 68 /** 69 * struct pcs_conf_vals - pinconf parameter, pinconf register offset 70 * and value, enable, disable, mask 71 * @param: config parameter 72 * @val: user input bits in the pinconf register 73 * @enable: enable bits in the pinconf register 74 * @disable: disable bits in the pinconf register 75 * @mask: mask bits in the register value 76 */ 77 struct pcs_conf_vals { 78 enum pin_config_param param; 79 unsigned val; 80 unsigned enable; 81 unsigned disable; 82 unsigned mask; 83 }; 84 85 /** 86 * struct pcs_conf_type - pinconf property name, pinconf param pair 87 * @name: property name in DTS file 88 * @param: config parameter 89 */ 90 struct pcs_conf_type { 91 const char *name; 92 enum pin_config_param param; 93 }; 94 95 /** 96 * struct pcs_function - pinctrl function 97 * @name: pinctrl function name 98 * @vals: register and vals array 99 * @nvals: number of entries in vals array 100 * @pgnames: array of pingroup names the function uses 101 * @npgnames: number of pingroup names the function uses 102 * @node: list node 103 */ 104 struct pcs_function { 105 const char *name; 106 struct pcs_func_vals *vals; 107 unsigned nvals; 108 const char **pgnames; 109 int npgnames; 110 struct pcs_conf_vals *conf; 111 int nconfs; 112 struct list_head node; 113 }; 114 115 /** 116 * struct pcs_gpiofunc_range - pin ranges with same mux value of gpio function 117 * @offset: offset base of pins 118 * @npins: number pins with the same mux value of gpio function 119 * @gpiofunc: mux value of gpio function 120 * @node: list node 121 */ 122 struct pcs_gpiofunc_range { 123 unsigned offset; 124 unsigned npins; 125 unsigned gpiofunc; 126 struct list_head node; 127 }; 128 129 /** 130 * struct pcs_data - wrapper for data needed by pinctrl framework 131 * @pa: pindesc array 132 * @cur: index to current element 133 * 134 * REVISIT: We should be able to drop this eventually by adding 135 * support for registering pins individually in the pinctrl 136 * framework for those drivers that don't need a static array. 137 */ 138 struct pcs_data { 139 struct pinctrl_pin_desc *pa; 140 int cur; 141 }; 142 143 /** 144 * struct pcs_soc_data - SoC specific settings 145 * @flags: initial SoC specific PCS_FEAT_xxx values 146 * @irq: optional interrupt for the controller 147 * @irq_enable_mask: optional SoC specific interrupt enable mask 148 * @irq_status_mask: optional SoC specific interrupt status mask 149 * @rearm: optional SoC specific wake-up rearm function 150 */ 151 struct pcs_soc_data { 152 unsigned flags; 153 int irq; 154 unsigned irq_enable_mask; 155 unsigned irq_status_mask; 156 void (*rearm)(void); 157 }; 158 159 /** 160 * struct pcs_device - pinctrl device instance 161 * @res: resources 162 * @base: virtual address of the controller 163 * @size: size of the ioremapped area 164 * @dev: device entry 165 * @pctl: pin controller device 166 * @flags: mask of PCS_FEAT_xxx values 167 * @lock: spinlock for register access 168 * @mutex: mutex protecting the lists 169 * @width: bits per mux register 170 * @fmask: function register mask 171 * @fshift: function register shift 172 * @foff: value to turn mux off 173 * @fmax: max number of functions in fmask 174 * @bits_per_pin:number of bits per pin 175 * @pins: physical pins on the SoC 176 * @pgtree: pingroup index radix tree 177 * @ftree: function index radix tree 178 * @pingroups: list of pingroups 179 * @functions: list of functions 180 * @gpiofuncs: list of gpio functions 181 * @irqs: list of interrupt registers 182 * @chip: chip container for this instance 183 * @domain: IRQ domain for this instance 184 * @ngroups: number of pingroups 185 * @nfuncs: number of functions 186 * @desc: pin controller descriptor 187 * @read: register read function to use 188 * @write: register write function to use 189 */ 190 struct pcs_device { 191 struct resource *res; 192 void __iomem *base; 193 unsigned size; 194 struct device *dev; 195 struct pinctrl_dev *pctl; 196 unsigned flags; 197 #define PCS_QUIRK_SHARED_IRQ (1 << 2) 198 #define PCS_FEAT_IRQ (1 << 1) 199 #define PCS_FEAT_PINCONF (1 << 0) 200 struct pcs_soc_data socdata; 201 raw_spinlock_t lock; 202 struct mutex mutex; 203 unsigned width; 204 unsigned fmask; 205 unsigned fshift; 206 unsigned foff; 207 unsigned fmax; 208 bool bits_per_mux; 209 unsigned bits_per_pin; 210 struct pcs_data pins; 211 struct radix_tree_root pgtree; 212 struct radix_tree_root ftree; 213 struct list_head pingroups; 214 struct list_head functions; 215 struct list_head gpiofuncs; 216 struct list_head irqs; 217 struct irq_chip chip; 218 struct irq_domain *domain; 219 unsigned ngroups; 220 unsigned nfuncs; 221 struct pinctrl_desc desc; 222 unsigned (*read)(void __iomem *reg); 223 void (*write)(unsigned val, void __iomem *reg); 224 }; 225 226 #define PCS_QUIRK_HAS_SHARED_IRQ (pcs->flags & PCS_QUIRK_SHARED_IRQ) 227 #define PCS_HAS_IRQ (pcs->flags & PCS_FEAT_IRQ) 228 #define PCS_HAS_PINCONF (pcs->flags & PCS_FEAT_PINCONF) 229 230 static int pcs_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin, 231 unsigned long *config); 232 static int pcs_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin, 233 unsigned long *configs, unsigned num_configs); 234 235 static enum pin_config_param pcs_bias[] = { 236 PIN_CONFIG_BIAS_PULL_DOWN, 237 PIN_CONFIG_BIAS_PULL_UP, 238 }; 239 240 /* 241 * This lock class tells lockdep that irqchip core that this single 242 * pinctrl can be in a different category than its parents, so it won't 243 * report false recursion. 244 */ 245 static struct lock_class_key pcs_lock_class; 246 247 /* 248 * REVISIT: Reads and writes could eventually use regmap or something 249 * generic. But at least on omaps, some mux registers are performance 250 * critical as they may need to be remuxed every time before and after 251 * idle. Adding tests for register access width for every read and 252 * write like regmap is doing is not desired, and caching the registers 253 * does not help in this case. 254 */ 255 256 static unsigned __maybe_unused pcs_readb(void __iomem *reg) 257 { 258 return readb(reg); 259 } 260 261 static unsigned __maybe_unused pcs_readw(void __iomem *reg) 262 { 263 return readw(reg); 264 } 265 266 static unsigned __maybe_unused pcs_readl(void __iomem *reg) 267 { 268 return readl(reg); 269 } 270 271 static void __maybe_unused pcs_writeb(unsigned val, void __iomem *reg) 272 { 273 writeb(val, reg); 274 } 275 276 static void __maybe_unused pcs_writew(unsigned val, void __iomem *reg) 277 { 278 writew(val, reg); 279 } 280 281 static void __maybe_unused pcs_writel(unsigned val, void __iomem *reg) 282 { 283 writel(val, reg); 284 } 285 286 static int pcs_get_groups_count(struct pinctrl_dev *pctldev) 287 { 288 struct pcs_device *pcs; 289 290 pcs = pinctrl_dev_get_drvdata(pctldev); 291 292 return pcs->ngroups; 293 } 294 295 static const char *pcs_get_group_name(struct pinctrl_dev *pctldev, 296 unsigned gselector) 297 { 298 struct pcs_device *pcs; 299 struct pcs_pingroup *group; 300 301 pcs = pinctrl_dev_get_drvdata(pctldev); 302 group = radix_tree_lookup(&pcs->pgtree, gselector); 303 if (!group) { 304 dev_err(pcs->dev, "%s could not find pingroup%i\n", 305 __func__, gselector); 306 return NULL; 307 } 308 309 return group->name; 310 } 311 312 static int pcs_get_group_pins(struct pinctrl_dev *pctldev, 313 unsigned gselector, 314 const unsigned **pins, 315 unsigned *npins) 316 { 317 struct pcs_device *pcs; 318 struct pcs_pingroup *group; 319 320 pcs = pinctrl_dev_get_drvdata(pctldev); 321 group = radix_tree_lookup(&pcs->pgtree, gselector); 322 if (!group) { 323 dev_err(pcs->dev, "%s could not find pingroup%i\n", 324 __func__, gselector); 325 return -EINVAL; 326 } 327 328 *pins = group->gpins; 329 *npins = group->ngpins; 330 331 return 0; 332 } 333 334 static void pcs_pin_dbg_show(struct pinctrl_dev *pctldev, 335 struct seq_file *s, 336 unsigned pin) 337 { 338 struct pcs_device *pcs; 339 unsigned val, mux_bytes; 340 unsigned long offset; 341 size_t pa; 342 343 pcs = pinctrl_dev_get_drvdata(pctldev); 344 345 mux_bytes = pcs->width / BITS_PER_BYTE; 346 offset = pin * mux_bytes; 347 val = pcs->read(pcs->base + offset); 348 pa = pcs->res->start + offset; 349 350 seq_printf(s, "%zx %08x %s ", pa, val, DRIVER_NAME); 351 } 352 353 static void pcs_dt_free_map(struct pinctrl_dev *pctldev, 354 struct pinctrl_map *map, unsigned num_maps) 355 { 356 struct pcs_device *pcs; 357 358 pcs = pinctrl_dev_get_drvdata(pctldev); 359 devm_kfree(pcs->dev, map); 360 } 361 362 static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev, 363 struct device_node *np_config, 364 struct pinctrl_map **map, unsigned *num_maps); 365 366 static const struct pinctrl_ops pcs_pinctrl_ops = { 367 .get_groups_count = pcs_get_groups_count, 368 .get_group_name = pcs_get_group_name, 369 .get_group_pins = pcs_get_group_pins, 370 .pin_dbg_show = pcs_pin_dbg_show, 371 .dt_node_to_map = pcs_dt_node_to_map, 372 .dt_free_map = pcs_dt_free_map, 373 }; 374 375 static int pcs_get_functions_count(struct pinctrl_dev *pctldev) 376 { 377 struct pcs_device *pcs; 378 379 pcs = pinctrl_dev_get_drvdata(pctldev); 380 381 return pcs->nfuncs; 382 } 383 384 static const char *pcs_get_function_name(struct pinctrl_dev *pctldev, 385 unsigned fselector) 386 { 387 struct pcs_device *pcs; 388 struct pcs_function *func; 389 390 pcs = pinctrl_dev_get_drvdata(pctldev); 391 func = radix_tree_lookup(&pcs->ftree, fselector); 392 if (!func) { 393 dev_err(pcs->dev, "%s could not find function%i\n", 394 __func__, fselector); 395 return NULL; 396 } 397 398 return func->name; 399 } 400 401 static int pcs_get_function_groups(struct pinctrl_dev *pctldev, 402 unsigned fselector, 403 const char * const **groups, 404 unsigned * const ngroups) 405 { 406 struct pcs_device *pcs; 407 struct pcs_function *func; 408 409 pcs = pinctrl_dev_get_drvdata(pctldev); 410 func = radix_tree_lookup(&pcs->ftree, fselector); 411 if (!func) { 412 dev_err(pcs->dev, "%s could not find function%i\n", 413 __func__, fselector); 414 return -EINVAL; 415 } 416 *groups = func->pgnames; 417 *ngroups = func->npgnames; 418 419 return 0; 420 } 421 422 static int pcs_get_function(struct pinctrl_dev *pctldev, unsigned pin, 423 struct pcs_function **func) 424 { 425 struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev); 426 struct pin_desc *pdesc = pin_desc_get(pctldev, pin); 427 const struct pinctrl_setting_mux *setting; 428 unsigned fselector; 429 430 /* If pin is not described in DTS & enabled, mux_setting is NULL. */ 431 setting = pdesc->mux_setting; 432 if (!setting) 433 return -ENOTSUPP; 434 fselector = setting->func; 435 *func = radix_tree_lookup(&pcs->ftree, fselector); 436 if (!(*func)) { 437 dev_err(pcs->dev, "%s could not find function%i\n", 438 __func__, fselector); 439 return -ENOTSUPP; 440 } 441 return 0; 442 } 443 444 static int pcs_set_mux(struct pinctrl_dev *pctldev, unsigned fselector, 445 unsigned group) 446 { 447 struct pcs_device *pcs; 448 struct pcs_function *func; 449 int i; 450 451 pcs = pinctrl_dev_get_drvdata(pctldev); 452 /* If function mask is null, needn't enable it. */ 453 if (!pcs->fmask) 454 return 0; 455 func = radix_tree_lookup(&pcs->ftree, fselector); 456 if (!func) 457 return -EINVAL; 458 459 dev_dbg(pcs->dev, "enabling %s function%i\n", 460 func->name, fselector); 461 462 for (i = 0; i < func->nvals; i++) { 463 struct pcs_func_vals *vals; 464 unsigned long flags; 465 unsigned val, mask; 466 467 vals = &func->vals[i]; 468 raw_spin_lock_irqsave(&pcs->lock, flags); 469 val = pcs->read(vals->reg); 470 471 if (pcs->bits_per_mux) 472 mask = vals->mask; 473 else 474 mask = pcs->fmask; 475 476 val &= ~mask; 477 val |= (vals->val & mask); 478 pcs->write(val, vals->reg); 479 raw_spin_unlock_irqrestore(&pcs->lock, flags); 480 } 481 482 return 0; 483 } 484 485 static int pcs_request_gpio(struct pinctrl_dev *pctldev, 486 struct pinctrl_gpio_range *range, unsigned pin) 487 { 488 struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev); 489 struct pcs_gpiofunc_range *frange = NULL; 490 struct list_head *pos, *tmp; 491 int mux_bytes = 0; 492 unsigned data; 493 494 /* If function mask is null, return directly. */ 495 if (!pcs->fmask) 496 return -ENOTSUPP; 497 498 list_for_each_safe(pos, tmp, &pcs->gpiofuncs) { 499 frange = list_entry(pos, struct pcs_gpiofunc_range, node); 500 if (pin >= frange->offset + frange->npins 501 || pin < frange->offset) 502 continue; 503 mux_bytes = pcs->width / BITS_PER_BYTE; 504 data = pcs->read(pcs->base + pin * mux_bytes) & ~pcs->fmask; 505 data |= frange->gpiofunc; 506 pcs->write(data, pcs->base + pin * mux_bytes); 507 break; 508 } 509 return 0; 510 } 511 512 static const struct pinmux_ops pcs_pinmux_ops = { 513 .get_functions_count = pcs_get_functions_count, 514 .get_function_name = pcs_get_function_name, 515 .get_function_groups = pcs_get_function_groups, 516 .set_mux = pcs_set_mux, 517 .gpio_request_enable = pcs_request_gpio, 518 }; 519 520 /* Clear BIAS value */ 521 static void pcs_pinconf_clear_bias(struct pinctrl_dev *pctldev, unsigned pin) 522 { 523 unsigned long config; 524 int i; 525 for (i = 0; i < ARRAY_SIZE(pcs_bias); i++) { 526 config = pinconf_to_config_packed(pcs_bias[i], 0); 527 pcs_pinconf_set(pctldev, pin, &config, 1); 528 } 529 } 530 531 /* 532 * Check whether PIN_CONFIG_BIAS_DISABLE is valid. 533 * It's depend on that PULL_DOWN & PULL_UP configs are all invalid. 534 */ 535 static bool pcs_pinconf_bias_disable(struct pinctrl_dev *pctldev, unsigned pin) 536 { 537 unsigned long config; 538 int i; 539 540 for (i = 0; i < ARRAY_SIZE(pcs_bias); i++) { 541 config = pinconf_to_config_packed(pcs_bias[i], 0); 542 if (!pcs_pinconf_get(pctldev, pin, &config)) 543 goto out; 544 } 545 return true; 546 out: 547 return false; 548 } 549 550 static int pcs_pinconf_get(struct pinctrl_dev *pctldev, 551 unsigned pin, unsigned long *config) 552 { 553 struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev); 554 struct pcs_function *func; 555 enum pin_config_param param; 556 unsigned offset = 0, data = 0, i, j, ret; 557 558 ret = pcs_get_function(pctldev, pin, &func); 559 if (ret) 560 return ret; 561 562 for (i = 0; i < func->nconfs; i++) { 563 param = pinconf_to_config_param(*config); 564 if (param == PIN_CONFIG_BIAS_DISABLE) { 565 if (pcs_pinconf_bias_disable(pctldev, pin)) { 566 *config = 0; 567 return 0; 568 } else { 569 return -ENOTSUPP; 570 } 571 } else if (param != func->conf[i].param) { 572 continue; 573 } 574 575 offset = pin * (pcs->width / BITS_PER_BYTE); 576 data = pcs->read(pcs->base + offset) & func->conf[i].mask; 577 switch (func->conf[i].param) { 578 /* 4 parameters */ 579 case PIN_CONFIG_BIAS_PULL_DOWN: 580 case PIN_CONFIG_BIAS_PULL_UP: 581 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 582 if ((data != func->conf[i].enable) || 583 (data == func->conf[i].disable)) 584 return -ENOTSUPP; 585 *config = 0; 586 break; 587 /* 2 parameters */ 588 case PIN_CONFIG_INPUT_SCHMITT: 589 for (j = 0; j < func->nconfs; j++) { 590 switch (func->conf[j].param) { 591 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 592 if (data != func->conf[j].enable) 593 return -ENOTSUPP; 594 break; 595 default: 596 break; 597 } 598 } 599 *config = data; 600 break; 601 case PIN_CONFIG_DRIVE_STRENGTH: 602 case PIN_CONFIG_SLEW_RATE: 603 case PIN_CONFIG_LOW_POWER_MODE: 604 default: 605 *config = data; 606 break; 607 } 608 return 0; 609 } 610 return -ENOTSUPP; 611 } 612 613 static int pcs_pinconf_set(struct pinctrl_dev *pctldev, 614 unsigned pin, unsigned long *configs, 615 unsigned num_configs) 616 { 617 struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev); 618 struct pcs_function *func; 619 unsigned offset = 0, shift = 0, i, data, ret; 620 u16 arg; 621 int j; 622 623 ret = pcs_get_function(pctldev, pin, &func); 624 if (ret) 625 return ret; 626 627 for (j = 0; j < num_configs; j++) { 628 for (i = 0; i < func->nconfs; i++) { 629 if (pinconf_to_config_param(configs[j]) 630 != func->conf[i].param) 631 continue; 632 633 offset = pin * (pcs->width / BITS_PER_BYTE); 634 data = pcs->read(pcs->base + offset); 635 arg = pinconf_to_config_argument(configs[j]); 636 switch (func->conf[i].param) { 637 /* 2 parameters */ 638 case PIN_CONFIG_INPUT_SCHMITT: 639 case PIN_CONFIG_DRIVE_STRENGTH: 640 case PIN_CONFIG_SLEW_RATE: 641 case PIN_CONFIG_LOW_POWER_MODE: 642 shift = ffs(func->conf[i].mask) - 1; 643 data &= ~func->conf[i].mask; 644 data |= (arg << shift) & func->conf[i].mask; 645 break; 646 /* 4 parameters */ 647 case PIN_CONFIG_BIAS_DISABLE: 648 pcs_pinconf_clear_bias(pctldev, pin); 649 break; 650 case PIN_CONFIG_BIAS_PULL_DOWN: 651 case PIN_CONFIG_BIAS_PULL_UP: 652 if (arg) 653 pcs_pinconf_clear_bias(pctldev, pin); 654 /* fall through */ 655 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 656 data &= ~func->conf[i].mask; 657 if (arg) 658 data |= func->conf[i].enable; 659 else 660 data |= func->conf[i].disable; 661 break; 662 default: 663 return -ENOTSUPP; 664 } 665 pcs->write(data, pcs->base + offset); 666 667 break; 668 } 669 if (i >= func->nconfs) 670 return -ENOTSUPP; 671 } /* for each config */ 672 673 return 0; 674 } 675 676 static int pcs_pinconf_group_get(struct pinctrl_dev *pctldev, 677 unsigned group, unsigned long *config) 678 { 679 const unsigned *pins; 680 unsigned npins, old = 0; 681 int i, ret; 682 683 ret = pcs_get_group_pins(pctldev, group, &pins, &npins); 684 if (ret) 685 return ret; 686 for (i = 0; i < npins; i++) { 687 if (pcs_pinconf_get(pctldev, pins[i], config)) 688 return -ENOTSUPP; 689 /* configs do not match between two pins */ 690 if (i && (old != *config)) 691 return -ENOTSUPP; 692 old = *config; 693 } 694 return 0; 695 } 696 697 static int pcs_pinconf_group_set(struct pinctrl_dev *pctldev, 698 unsigned group, unsigned long *configs, 699 unsigned num_configs) 700 { 701 const unsigned *pins; 702 unsigned npins; 703 int i, ret; 704 705 ret = pcs_get_group_pins(pctldev, group, &pins, &npins); 706 if (ret) 707 return ret; 708 for (i = 0; i < npins; i++) { 709 if (pcs_pinconf_set(pctldev, pins[i], configs, num_configs)) 710 return -ENOTSUPP; 711 } 712 return 0; 713 } 714 715 static void pcs_pinconf_dbg_show(struct pinctrl_dev *pctldev, 716 struct seq_file *s, unsigned pin) 717 { 718 } 719 720 static void pcs_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, 721 struct seq_file *s, unsigned selector) 722 { 723 } 724 725 static void pcs_pinconf_config_dbg_show(struct pinctrl_dev *pctldev, 726 struct seq_file *s, 727 unsigned long config) 728 { 729 pinconf_generic_dump_config(pctldev, s, config); 730 } 731 732 static const struct pinconf_ops pcs_pinconf_ops = { 733 .pin_config_get = pcs_pinconf_get, 734 .pin_config_set = pcs_pinconf_set, 735 .pin_config_group_get = pcs_pinconf_group_get, 736 .pin_config_group_set = pcs_pinconf_group_set, 737 .pin_config_dbg_show = pcs_pinconf_dbg_show, 738 .pin_config_group_dbg_show = pcs_pinconf_group_dbg_show, 739 .pin_config_config_dbg_show = pcs_pinconf_config_dbg_show, 740 .is_generic = true, 741 }; 742 743 /** 744 * pcs_add_pin() - add a pin to the static per controller pin array 745 * @pcs: pcs driver instance 746 * @offset: register offset from base 747 */ 748 static int pcs_add_pin(struct pcs_device *pcs, unsigned offset, 749 unsigned pin_pos) 750 { 751 struct pcs_soc_data *pcs_soc = &pcs->socdata; 752 struct pinctrl_pin_desc *pin; 753 int i; 754 755 i = pcs->pins.cur; 756 if (i >= pcs->desc.npins) { 757 dev_err(pcs->dev, "too many pins, max %i\n", 758 pcs->desc.npins); 759 return -ENOMEM; 760 } 761 762 if (pcs_soc->irq_enable_mask) { 763 unsigned val; 764 765 val = pcs->read(pcs->base + offset); 766 if (val & pcs_soc->irq_enable_mask) { 767 dev_dbg(pcs->dev, "irq enabled at boot for pin at %lx (%x), clearing\n", 768 (unsigned long)pcs->res->start + offset, val); 769 val &= ~pcs_soc->irq_enable_mask; 770 pcs->write(val, pcs->base + offset); 771 } 772 } 773 774 pin = &pcs->pins.pa[i]; 775 pin->number = i; 776 pcs->pins.cur++; 777 778 return i; 779 } 780 781 /** 782 * pcs_allocate_pin_table() - adds all the pins for the pinctrl driver 783 * @pcs: pcs driver instance 784 * 785 * In case of errors, resources are freed in pcs_free_resources. 786 * 787 * If your hardware needs holes in the address space, then just set 788 * up multiple driver instances. 789 */ 790 static int pcs_allocate_pin_table(struct pcs_device *pcs) 791 { 792 int mux_bytes, nr_pins, i; 793 int num_pins_in_register = 0; 794 795 mux_bytes = pcs->width / BITS_PER_BYTE; 796 797 if (pcs->bits_per_mux) { 798 pcs->bits_per_pin = fls(pcs->fmask); 799 nr_pins = (pcs->size * BITS_PER_BYTE) / pcs->bits_per_pin; 800 num_pins_in_register = pcs->width / pcs->bits_per_pin; 801 } else { 802 nr_pins = pcs->size / mux_bytes; 803 } 804 805 dev_dbg(pcs->dev, "allocating %i pins\n", nr_pins); 806 pcs->pins.pa = devm_kzalloc(pcs->dev, 807 sizeof(*pcs->pins.pa) * nr_pins, 808 GFP_KERNEL); 809 if (!pcs->pins.pa) 810 return -ENOMEM; 811 812 pcs->desc.pins = pcs->pins.pa; 813 pcs->desc.npins = nr_pins; 814 815 for (i = 0; i < pcs->desc.npins; i++) { 816 unsigned offset; 817 int res; 818 int byte_num; 819 int pin_pos = 0; 820 821 if (pcs->bits_per_mux) { 822 byte_num = (pcs->bits_per_pin * i) / BITS_PER_BYTE; 823 offset = (byte_num / mux_bytes) * mux_bytes; 824 pin_pos = i % num_pins_in_register; 825 } else { 826 offset = i * mux_bytes; 827 } 828 res = pcs_add_pin(pcs, offset, pin_pos); 829 if (res < 0) { 830 dev_err(pcs->dev, "error adding pins: %i\n", res); 831 return res; 832 } 833 } 834 835 return 0; 836 } 837 838 /** 839 * pcs_add_function() - adds a new function to the function list 840 * @pcs: pcs driver instance 841 * @np: device node of the mux entry 842 * @name: name of the function 843 * @vals: array of mux register value pairs used by the function 844 * @nvals: number of mux register value pairs 845 * @pgnames: array of pingroup names for the function 846 * @npgnames: number of pingroup names 847 */ 848 static struct pcs_function *pcs_add_function(struct pcs_device *pcs, 849 struct device_node *np, 850 const char *name, 851 struct pcs_func_vals *vals, 852 unsigned nvals, 853 const char **pgnames, 854 unsigned npgnames) 855 { 856 struct pcs_function *function; 857 858 function = devm_kzalloc(pcs->dev, sizeof(*function), GFP_KERNEL); 859 if (!function) 860 return NULL; 861 862 function->name = name; 863 function->vals = vals; 864 function->nvals = nvals; 865 function->pgnames = pgnames; 866 function->npgnames = npgnames; 867 868 mutex_lock(&pcs->mutex); 869 list_add_tail(&function->node, &pcs->functions); 870 radix_tree_insert(&pcs->ftree, pcs->nfuncs, function); 871 pcs->nfuncs++; 872 mutex_unlock(&pcs->mutex); 873 874 return function; 875 } 876 877 static void pcs_remove_function(struct pcs_device *pcs, 878 struct pcs_function *function) 879 { 880 int i; 881 882 mutex_lock(&pcs->mutex); 883 for (i = 0; i < pcs->nfuncs; i++) { 884 struct pcs_function *found; 885 886 found = radix_tree_lookup(&pcs->ftree, i); 887 if (found == function) 888 radix_tree_delete(&pcs->ftree, i); 889 } 890 list_del(&function->node); 891 mutex_unlock(&pcs->mutex); 892 } 893 894 /** 895 * pcs_add_pingroup() - add a pingroup to the pingroup list 896 * @pcs: pcs driver instance 897 * @np: device node of the mux entry 898 * @name: name of the pingroup 899 * @gpins: array of the pins that belong to the group 900 * @ngpins: number of pins in the group 901 */ 902 static int pcs_add_pingroup(struct pcs_device *pcs, 903 struct device_node *np, 904 const char *name, 905 int *gpins, 906 int ngpins) 907 { 908 struct pcs_pingroup *pingroup; 909 910 pingroup = devm_kzalloc(pcs->dev, sizeof(*pingroup), GFP_KERNEL); 911 if (!pingroup) 912 return -ENOMEM; 913 914 pingroup->name = name; 915 pingroup->np = np; 916 pingroup->gpins = gpins; 917 pingroup->ngpins = ngpins; 918 919 mutex_lock(&pcs->mutex); 920 list_add_tail(&pingroup->node, &pcs->pingroups); 921 radix_tree_insert(&pcs->pgtree, pcs->ngroups, pingroup); 922 pcs->ngroups++; 923 mutex_unlock(&pcs->mutex); 924 925 return 0; 926 } 927 928 /** 929 * pcs_get_pin_by_offset() - get a pin index based on the register offset 930 * @pcs: pcs driver instance 931 * @offset: register offset from the base 932 * 933 * Note that this is OK as long as the pins are in a static array. 934 */ 935 static int pcs_get_pin_by_offset(struct pcs_device *pcs, unsigned offset) 936 { 937 unsigned index; 938 939 if (offset >= pcs->size) { 940 dev_err(pcs->dev, "mux offset out of range: 0x%x (0x%x)\n", 941 offset, pcs->size); 942 return -EINVAL; 943 } 944 945 if (pcs->bits_per_mux) 946 index = (offset * BITS_PER_BYTE) / pcs->bits_per_pin; 947 else 948 index = offset / (pcs->width / BITS_PER_BYTE); 949 950 return index; 951 } 952 953 /* 954 * check whether data matches enable bits or disable bits 955 * Return value: 1 for matching enable bits, 0 for matching disable bits, 956 * and negative value for matching failure. 957 */ 958 static int pcs_config_match(unsigned data, unsigned enable, unsigned disable) 959 { 960 int ret = -EINVAL; 961 962 if (data == enable) 963 ret = 1; 964 else if (data == disable) 965 ret = 0; 966 return ret; 967 } 968 969 static void add_config(struct pcs_conf_vals **conf, enum pin_config_param param, 970 unsigned value, unsigned enable, unsigned disable, 971 unsigned mask) 972 { 973 (*conf)->param = param; 974 (*conf)->val = value; 975 (*conf)->enable = enable; 976 (*conf)->disable = disable; 977 (*conf)->mask = mask; 978 (*conf)++; 979 } 980 981 static void add_setting(unsigned long **setting, enum pin_config_param param, 982 unsigned arg) 983 { 984 **setting = pinconf_to_config_packed(param, arg); 985 (*setting)++; 986 } 987 988 /* add pinconf setting with 2 parameters */ 989 static void pcs_add_conf2(struct pcs_device *pcs, struct device_node *np, 990 const char *name, enum pin_config_param param, 991 struct pcs_conf_vals **conf, unsigned long **settings) 992 { 993 unsigned value[2], shift; 994 int ret; 995 996 ret = of_property_read_u32_array(np, name, value, 2); 997 if (ret) 998 return; 999 /* set value & mask */ 1000 value[0] &= value[1]; 1001 shift = ffs(value[1]) - 1; 1002 /* skip enable & disable */ 1003 add_config(conf, param, value[0], 0, 0, value[1]); 1004 add_setting(settings, param, value[0] >> shift); 1005 } 1006 1007 /* add pinconf setting with 4 parameters */ 1008 static void pcs_add_conf4(struct pcs_device *pcs, struct device_node *np, 1009 const char *name, enum pin_config_param param, 1010 struct pcs_conf_vals **conf, unsigned long **settings) 1011 { 1012 unsigned value[4]; 1013 int ret; 1014 1015 /* value to set, enable, disable, mask */ 1016 ret = of_property_read_u32_array(np, name, value, 4); 1017 if (ret) 1018 return; 1019 if (!value[3]) { 1020 dev_err(pcs->dev, "mask field of the property can't be 0\n"); 1021 return; 1022 } 1023 value[0] &= value[3]; 1024 value[1] &= value[3]; 1025 value[2] &= value[3]; 1026 ret = pcs_config_match(value[0], value[1], value[2]); 1027 if (ret < 0) 1028 dev_dbg(pcs->dev, "failed to match enable or disable bits\n"); 1029 add_config(conf, param, value[0], value[1], value[2], value[3]); 1030 add_setting(settings, param, ret); 1031 } 1032 1033 static int pcs_parse_pinconf(struct pcs_device *pcs, struct device_node *np, 1034 struct pcs_function *func, 1035 struct pinctrl_map **map) 1036 1037 { 1038 struct pinctrl_map *m = *map; 1039 int i = 0, nconfs = 0; 1040 unsigned long *settings = NULL, *s = NULL; 1041 struct pcs_conf_vals *conf = NULL; 1042 struct pcs_conf_type prop2[] = { 1043 { "pinctrl-single,drive-strength", PIN_CONFIG_DRIVE_STRENGTH, }, 1044 { "pinctrl-single,slew-rate", PIN_CONFIG_SLEW_RATE, }, 1045 { "pinctrl-single,input-schmitt", PIN_CONFIG_INPUT_SCHMITT, }, 1046 { "pinctrl-single,low-power-mode", PIN_CONFIG_LOW_POWER_MODE, }, 1047 }; 1048 struct pcs_conf_type prop4[] = { 1049 { "pinctrl-single,bias-pullup", PIN_CONFIG_BIAS_PULL_UP, }, 1050 { "pinctrl-single,bias-pulldown", PIN_CONFIG_BIAS_PULL_DOWN, }, 1051 { "pinctrl-single,input-schmitt-enable", 1052 PIN_CONFIG_INPUT_SCHMITT_ENABLE, }, 1053 }; 1054 1055 /* If pinconf isn't supported, don't parse properties in below. */ 1056 if (!PCS_HAS_PINCONF) 1057 return 0; 1058 1059 /* cacluate how much properties are supported in current node */ 1060 for (i = 0; i < ARRAY_SIZE(prop2); i++) { 1061 if (of_find_property(np, prop2[i].name, NULL)) 1062 nconfs++; 1063 } 1064 for (i = 0; i < ARRAY_SIZE(prop4); i++) { 1065 if (of_find_property(np, prop4[i].name, NULL)) 1066 nconfs++; 1067 } 1068 if (!nconfs) 1069 return 0; 1070 1071 func->conf = devm_kzalloc(pcs->dev, 1072 sizeof(struct pcs_conf_vals) * nconfs, 1073 GFP_KERNEL); 1074 if (!func->conf) 1075 return -ENOMEM; 1076 func->nconfs = nconfs; 1077 conf = &(func->conf[0]); 1078 m++; 1079 settings = devm_kzalloc(pcs->dev, sizeof(unsigned long) * nconfs, 1080 GFP_KERNEL); 1081 if (!settings) 1082 return -ENOMEM; 1083 s = &settings[0]; 1084 1085 for (i = 0; i < ARRAY_SIZE(prop2); i++) 1086 pcs_add_conf2(pcs, np, prop2[i].name, prop2[i].param, 1087 &conf, &s); 1088 for (i = 0; i < ARRAY_SIZE(prop4); i++) 1089 pcs_add_conf4(pcs, np, prop4[i].name, prop4[i].param, 1090 &conf, &s); 1091 m->type = PIN_MAP_TYPE_CONFIGS_GROUP; 1092 m->data.configs.group_or_pin = np->name; 1093 m->data.configs.configs = settings; 1094 m->data.configs.num_configs = nconfs; 1095 return 0; 1096 } 1097 1098 static void pcs_free_pingroups(struct pcs_device *pcs); 1099 1100 /** 1101 * smux_parse_one_pinctrl_entry() - parses a device tree mux entry 1102 * @pcs: pinctrl driver instance 1103 * @np: device node of the mux entry 1104 * @map: map entry 1105 * @num_maps: number of map 1106 * @pgnames: pingroup names 1107 * 1108 * Note that this binding currently supports only sets of one register + value. 1109 * 1110 * Also note that this driver tries to avoid understanding pin and function 1111 * names because of the extra bloat they would cause especially in the case of 1112 * a large number of pins. This driver just sets what is specified for the board 1113 * in the .dts file. Further user space debugging tools can be developed to 1114 * decipher the pin and function names using debugfs. 1115 * 1116 * If you are concerned about the boot time, set up the static pins in 1117 * the bootloader, and only set up selected pins as device tree entries. 1118 */ 1119 static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs, 1120 struct device_node *np, 1121 struct pinctrl_map **map, 1122 unsigned *num_maps, 1123 const char **pgnames) 1124 { 1125 struct pcs_func_vals *vals; 1126 const __be32 *mux; 1127 int size, rows, *pins, index = 0, found = 0, res = -ENOMEM; 1128 struct pcs_function *function; 1129 1130 mux = of_get_property(np, PCS_MUX_PINS_NAME, &size); 1131 if ((!mux) || (size < sizeof(*mux) * 2)) { 1132 dev_err(pcs->dev, "bad data for mux %s\n", 1133 np->name); 1134 return -EINVAL; 1135 } 1136 1137 size /= sizeof(*mux); /* Number of elements in array */ 1138 rows = size / 2; 1139 1140 vals = devm_kzalloc(pcs->dev, sizeof(*vals) * rows, GFP_KERNEL); 1141 if (!vals) 1142 return -ENOMEM; 1143 1144 pins = devm_kzalloc(pcs->dev, sizeof(*pins) * rows, GFP_KERNEL); 1145 if (!pins) 1146 goto free_vals; 1147 1148 while (index < size) { 1149 unsigned offset, val; 1150 int pin; 1151 1152 offset = be32_to_cpup(mux + index++); 1153 val = be32_to_cpup(mux + index++); 1154 vals[found].reg = pcs->base + offset; 1155 vals[found].val = val; 1156 1157 pin = pcs_get_pin_by_offset(pcs, offset); 1158 if (pin < 0) { 1159 dev_err(pcs->dev, 1160 "could not add functions for %s %ux\n", 1161 np->name, offset); 1162 break; 1163 } 1164 pins[found++] = pin; 1165 } 1166 1167 pgnames[0] = np->name; 1168 function = pcs_add_function(pcs, np, np->name, vals, found, pgnames, 1); 1169 if (!function) 1170 goto free_pins; 1171 1172 res = pcs_add_pingroup(pcs, np, np->name, pins, found); 1173 if (res < 0) 1174 goto free_function; 1175 1176 (*map)->type = PIN_MAP_TYPE_MUX_GROUP; 1177 (*map)->data.mux.group = np->name; 1178 (*map)->data.mux.function = np->name; 1179 1180 if (PCS_HAS_PINCONF) { 1181 res = pcs_parse_pinconf(pcs, np, function, map); 1182 if (res) 1183 goto free_pingroups; 1184 *num_maps = 2; 1185 } else { 1186 *num_maps = 1; 1187 } 1188 return 0; 1189 1190 free_pingroups: 1191 pcs_free_pingroups(pcs); 1192 *num_maps = 1; 1193 free_function: 1194 pcs_remove_function(pcs, function); 1195 1196 free_pins: 1197 devm_kfree(pcs->dev, pins); 1198 1199 free_vals: 1200 devm_kfree(pcs->dev, vals); 1201 1202 return res; 1203 } 1204 1205 #define PARAMS_FOR_BITS_PER_MUX 3 1206 1207 static int pcs_parse_bits_in_pinctrl_entry(struct pcs_device *pcs, 1208 struct device_node *np, 1209 struct pinctrl_map **map, 1210 unsigned *num_maps, 1211 const char **pgnames) 1212 { 1213 struct pcs_func_vals *vals; 1214 const __be32 *mux; 1215 int size, rows, *pins, index = 0, found = 0, res = -ENOMEM; 1216 int npins_in_row; 1217 struct pcs_function *function; 1218 1219 mux = of_get_property(np, PCS_MUX_BITS_NAME, &size); 1220 1221 if (!mux) { 1222 dev_err(pcs->dev, "no valid property for %s\n", np->name); 1223 return -EINVAL; 1224 } 1225 1226 if (size < (sizeof(*mux) * PARAMS_FOR_BITS_PER_MUX)) { 1227 dev_err(pcs->dev, "bad data for %s\n", np->name); 1228 return -EINVAL; 1229 } 1230 1231 /* Number of elements in array */ 1232 size /= sizeof(*mux); 1233 1234 rows = size / PARAMS_FOR_BITS_PER_MUX; 1235 npins_in_row = pcs->width / pcs->bits_per_pin; 1236 1237 vals = devm_kzalloc(pcs->dev, sizeof(*vals) * rows * npins_in_row, 1238 GFP_KERNEL); 1239 if (!vals) 1240 return -ENOMEM; 1241 1242 pins = devm_kzalloc(pcs->dev, sizeof(*pins) * rows * npins_in_row, 1243 GFP_KERNEL); 1244 if (!pins) 1245 goto free_vals; 1246 1247 while (index < size) { 1248 unsigned offset, val; 1249 unsigned mask, bit_pos, val_pos, mask_pos, submask; 1250 unsigned pin_num_from_lsb; 1251 int pin; 1252 1253 offset = be32_to_cpup(mux + index++); 1254 val = be32_to_cpup(mux + index++); 1255 mask = be32_to_cpup(mux + index++); 1256 1257 /* Parse pins in each row from LSB */ 1258 while (mask) { 1259 bit_pos = __ffs(mask); 1260 pin_num_from_lsb = bit_pos / pcs->bits_per_pin; 1261 mask_pos = ((pcs->fmask) << bit_pos); 1262 val_pos = val & mask_pos; 1263 submask = mask & mask_pos; 1264 1265 if ((mask & mask_pos) == 0) { 1266 dev_err(pcs->dev, 1267 "Invalid mask for %s at 0x%x\n", 1268 np->name, offset); 1269 break; 1270 } 1271 1272 mask &= ~mask_pos; 1273 1274 if (submask != mask_pos) { 1275 dev_warn(pcs->dev, 1276 "Invalid submask 0x%x for %s at 0x%x\n", 1277 submask, np->name, offset); 1278 continue; 1279 } 1280 1281 vals[found].mask = submask; 1282 vals[found].reg = pcs->base + offset; 1283 vals[found].val = val_pos; 1284 1285 pin = pcs_get_pin_by_offset(pcs, offset); 1286 if (pin < 0) { 1287 dev_err(pcs->dev, 1288 "could not add functions for %s %ux\n", 1289 np->name, offset); 1290 break; 1291 } 1292 pins[found++] = pin + pin_num_from_lsb; 1293 } 1294 } 1295 1296 pgnames[0] = np->name; 1297 function = pcs_add_function(pcs, np, np->name, vals, found, pgnames, 1); 1298 if (!function) 1299 goto free_pins; 1300 1301 res = pcs_add_pingroup(pcs, np, np->name, pins, found); 1302 if (res < 0) 1303 goto free_function; 1304 1305 (*map)->type = PIN_MAP_TYPE_MUX_GROUP; 1306 (*map)->data.mux.group = np->name; 1307 (*map)->data.mux.function = np->name; 1308 1309 if (PCS_HAS_PINCONF) { 1310 dev_err(pcs->dev, "pinconf not supported\n"); 1311 goto free_pingroups; 1312 } 1313 1314 *num_maps = 1; 1315 return 0; 1316 1317 free_pingroups: 1318 pcs_free_pingroups(pcs); 1319 *num_maps = 1; 1320 free_function: 1321 pcs_remove_function(pcs, function); 1322 1323 free_pins: 1324 devm_kfree(pcs->dev, pins); 1325 1326 free_vals: 1327 devm_kfree(pcs->dev, vals); 1328 1329 return res; 1330 } 1331 /** 1332 * pcs_dt_node_to_map() - allocates and parses pinctrl maps 1333 * @pctldev: pinctrl instance 1334 * @np_config: device tree pinmux entry 1335 * @map: array of map entries 1336 * @num_maps: number of maps 1337 */ 1338 static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev, 1339 struct device_node *np_config, 1340 struct pinctrl_map **map, unsigned *num_maps) 1341 { 1342 struct pcs_device *pcs; 1343 const char **pgnames; 1344 int ret; 1345 1346 pcs = pinctrl_dev_get_drvdata(pctldev); 1347 1348 /* create 2 maps. One is for pinmux, and the other is for pinconf. */ 1349 *map = devm_kzalloc(pcs->dev, sizeof(**map) * 2, GFP_KERNEL); 1350 if (!*map) 1351 return -ENOMEM; 1352 1353 *num_maps = 0; 1354 1355 pgnames = devm_kzalloc(pcs->dev, sizeof(*pgnames), GFP_KERNEL); 1356 if (!pgnames) { 1357 ret = -ENOMEM; 1358 goto free_map; 1359 } 1360 1361 if (pcs->bits_per_mux) { 1362 ret = pcs_parse_bits_in_pinctrl_entry(pcs, np_config, map, 1363 num_maps, pgnames); 1364 if (ret < 0) { 1365 dev_err(pcs->dev, "no pins entries for %s\n", 1366 np_config->name); 1367 goto free_pgnames; 1368 } 1369 } else { 1370 ret = pcs_parse_one_pinctrl_entry(pcs, np_config, map, 1371 num_maps, pgnames); 1372 if (ret < 0) { 1373 dev_err(pcs->dev, "no pins entries for %s\n", 1374 np_config->name); 1375 goto free_pgnames; 1376 } 1377 } 1378 1379 return 0; 1380 1381 free_pgnames: 1382 devm_kfree(pcs->dev, pgnames); 1383 free_map: 1384 devm_kfree(pcs->dev, *map); 1385 1386 return ret; 1387 } 1388 1389 /** 1390 * pcs_free_funcs() - free memory used by functions 1391 * @pcs: pcs driver instance 1392 */ 1393 static void pcs_free_funcs(struct pcs_device *pcs) 1394 { 1395 struct list_head *pos, *tmp; 1396 int i; 1397 1398 mutex_lock(&pcs->mutex); 1399 for (i = 0; i < pcs->nfuncs; i++) { 1400 struct pcs_function *func; 1401 1402 func = radix_tree_lookup(&pcs->ftree, i); 1403 if (!func) 1404 continue; 1405 radix_tree_delete(&pcs->ftree, i); 1406 } 1407 list_for_each_safe(pos, tmp, &pcs->functions) { 1408 struct pcs_function *function; 1409 1410 function = list_entry(pos, struct pcs_function, node); 1411 list_del(&function->node); 1412 } 1413 mutex_unlock(&pcs->mutex); 1414 } 1415 1416 /** 1417 * pcs_free_pingroups() - free memory used by pingroups 1418 * @pcs: pcs driver instance 1419 */ 1420 static void pcs_free_pingroups(struct pcs_device *pcs) 1421 { 1422 struct list_head *pos, *tmp; 1423 int i; 1424 1425 mutex_lock(&pcs->mutex); 1426 for (i = 0; i < pcs->ngroups; i++) { 1427 struct pcs_pingroup *pingroup; 1428 1429 pingroup = radix_tree_lookup(&pcs->pgtree, i); 1430 if (!pingroup) 1431 continue; 1432 radix_tree_delete(&pcs->pgtree, i); 1433 } 1434 list_for_each_safe(pos, tmp, &pcs->pingroups) { 1435 struct pcs_pingroup *pingroup; 1436 1437 pingroup = list_entry(pos, struct pcs_pingroup, node); 1438 list_del(&pingroup->node); 1439 } 1440 mutex_unlock(&pcs->mutex); 1441 } 1442 1443 /** 1444 * pcs_irq_free() - free interrupt 1445 * @pcs: pcs driver instance 1446 */ 1447 static void pcs_irq_free(struct pcs_device *pcs) 1448 { 1449 struct pcs_soc_data *pcs_soc = &pcs->socdata; 1450 1451 if (pcs_soc->irq < 0) 1452 return; 1453 1454 if (pcs->domain) 1455 irq_domain_remove(pcs->domain); 1456 1457 if (PCS_QUIRK_HAS_SHARED_IRQ) 1458 free_irq(pcs_soc->irq, pcs_soc); 1459 else 1460 irq_set_chained_handler(pcs_soc->irq, NULL); 1461 } 1462 1463 /** 1464 * pcs_free_resources() - free memory used by this driver 1465 * @pcs: pcs driver instance 1466 */ 1467 static void pcs_free_resources(struct pcs_device *pcs) 1468 { 1469 pcs_irq_free(pcs); 1470 pinctrl_unregister(pcs->pctl); 1471 pcs_free_funcs(pcs); 1472 pcs_free_pingroups(pcs); 1473 } 1474 1475 static const struct of_device_id pcs_of_match[]; 1476 1477 static int pcs_add_gpio_func(struct device_node *node, struct pcs_device *pcs) 1478 { 1479 const char *propname = "pinctrl-single,gpio-range"; 1480 const char *cellname = "#pinctrl-single,gpio-range-cells"; 1481 struct of_phandle_args gpiospec; 1482 struct pcs_gpiofunc_range *range; 1483 int ret, i; 1484 1485 for (i = 0; ; i++) { 1486 ret = of_parse_phandle_with_args(node, propname, cellname, 1487 i, &gpiospec); 1488 /* Do not treat it as error. Only treat it as end condition. */ 1489 if (ret) { 1490 ret = 0; 1491 break; 1492 } 1493 range = devm_kzalloc(pcs->dev, sizeof(*range), GFP_KERNEL); 1494 if (!range) { 1495 ret = -ENOMEM; 1496 break; 1497 } 1498 range->offset = gpiospec.args[0]; 1499 range->npins = gpiospec.args[1]; 1500 range->gpiofunc = gpiospec.args[2]; 1501 mutex_lock(&pcs->mutex); 1502 list_add_tail(&range->node, &pcs->gpiofuncs); 1503 mutex_unlock(&pcs->mutex); 1504 } 1505 return ret; 1506 } 1507 /** 1508 * @reg: virtual address of interrupt register 1509 * @hwirq: hardware irq number 1510 * @irq: virtual irq number 1511 * @node: list node 1512 */ 1513 struct pcs_interrupt { 1514 void __iomem *reg; 1515 irq_hw_number_t hwirq; 1516 unsigned int irq; 1517 struct list_head node; 1518 }; 1519 1520 /** 1521 * pcs_irq_set() - enables or disables an interrupt 1522 * 1523 * Note that this currently assumes one interrupt per pinctrl 1524 * register that is typically used for wake-up events. 1525 */ 1526 static inline void pcs_irq_set(struct pcs_soc_data *pcs_soc, 1527 int irq, const bool enable) 1528 { 1529 struct pcs_device *pcs; 1530 struct list_head *pos; 1531 unsigned mask; 1532 1533 pcs = container_of(pcs_soc, struct pcs_device, socdata); 1534 list_for_each(pos, &pcs->irqs) { 1535 struct pcs_interrupt *pcswi; 1536 unsigned soc_mask; 1537 1538 pcswi = list_entry(pos, struct pcs_interrupt, node); 1539 if (irq != pcswi->irq) 1540 continue; 1541 1542 soc_mask = pcs_soc->irq_enable_mask; 1543 raw_spin_lock(&pcs->lock); 1544 mask = pcs->read(pcswi->reg); 1545 if (enable) 1546 mask |= soc_mask; 1547 else 1548 mask &= ~soc_mask; 1549 pcs->write(mask, pcswi->reg); 1550 1551 /* flush posted write */ 1552 mask = pcs->read(pcswi->reg); 1553 raw_spin_unlock(&pcs->lock); 1554 } 1555 1556 if (pcs_soc->rearm) 1557 pcs_soc->rearm(); 1558 } 1559 1560 /** 1561 * pcs_irq_mask() - mask pinctrl interrupt 1562 * @d: interrupt data 1563 */ 1564 static void pcs_irq_mask(struct irq_data *d) 1565 { 1566 struct pcs_soc_data *pcs_soc = irq_data_get_irq_chip_data(d); 1567 1568 pcs_irq_set(pcs_soc, d->irq, false); 1569 } 1570 1571 /** 1572 * pcs_irq_unmask() - unmask pinctrl interrupt 1573 * @d: interrupt data 1574 */ 1575 static void pcs_irq_unmask(struct irq_data *d) 1576 { 1577 struct pcs_soc_data *pcs_soc = irq_data_get_irq_chip_data(d); 1578 1579 pcs_irq_set(pcs_soc, d->irq, true); 1580 } 1581 1582 /** 1583 * pcs_irq_set_wake() - toggle the suspend and resume wake up 1584 * @d: interrupt data 1585 * @state: wake-up state 1586 * 1587 * Note that this should be called only for suspend and resume. 1588 * For runtime PM, the wake-up events should be enabled by default. 1589 */ 1590 static int pcs_irq_set_wake(struct irq_data *d, unsigned int state) 1591 { 1592 if (state) 1593 pcs_irq_unmask(d); 1594 else 1595 pcs_irq_mask(d); 1596 1597 return 0; 1598 } 1599 1600 /** 1601 * pcs_irq_handle() - common interrupt handler 1602 * @pcs_irq: interrupt data 1603 * 1604 * Note that this currently assumes we have one interrupt bit per 1605 * mux register. This interrupt is typically used for wake-up events. 1606 * For more complex interrupts different handlers can be specified. 1607 */ 1608 static int pcs_irq_handle(struct pcs_soc_data *pcs_soc) 1609 { 1610 struct pcs_device *pcs; 1611 struct list_head *pos; 1612 int count = 0; 1613 1614 pcs = container_of(pcs_soc, struct pcs_device, socdata); 1615 list_for_each(pos, &pcs->irqs) { 1616 struct pcs_interrupt *pcswi; 1617 unsigned mask; 1618 1619 pcswi = list_entry(pos, struct pcs_interrupt, node); 1620 raw_spin_lock(&pcs->lock); 1621 mask = pcs->read(pcswi->reg); 1622 raw_spin_unlock(&pcs->lock); 1623 if (mask & pcs_soc->irq_status_mask) { 1624 generic_handle_irq(irq_find_mapping(pcs->domain, 1625 pcswi->hwirq)); 1626 count++; 1627 } 1628 } 1629 1630 return count; 1631 } 1632 1633 /** 1634 * pcs_irq_handler() - handler for the shared interrupt case 1635 * @irq: interrupt 1636 * @d: data 1637 * 1638 * Use this for cases where multiple instances of 1639 * pinctrl-single share a single interrupt like on omaps. 1640 */ 1641 static irqreturn_t pcs_irq_handler(int irq, void *d) 1642 { 1643 struct pcs_soc_data *pcs_soc = d; 1644 1645 return pcs_irq_handle(pcs_soc) ? IRQ_HANDLED : IRQ_NONE; 1646 } 1647 1648 /** 1649 * pcs_irq_handle() - handler for the dedicated chained interrupt case 1650 * @irq: interrupt 1651 * @desc: interrupt descriptor 1652 * 1653 * Use this if you have a separate interrupt for each 1654 * pinctrl-single instance. 1655 */ 1656 static void pcs_irq_chain_handler(struct irq_desc *desc) 1657 { 1658 struct pcs_soc_data *pcs_soc = irq_desc_get_handler_data(desc); 1659 struct irq_chip *chip; 1660 1661 chip = irq_desc_get_chip(desc); 1662 chained_irq_enter(chip, desc); 1663 pcs_irq_handle(pcs_soc); 1664 /* REVISIT: export and add handle_bad_irq(irq, desc)? */ 1665 chained_irq_exit(chip, desc); 1666 1667 return; 1668 } 1669 1670 static int pcs_irqdomain_map(struct irq_domain *d, unsigned int irq, 1671 irq_hw_number_t hwirq) 1672 { 1673 struct pcs_soc_data *pcs_soc = d->host_data; 1674 struct pcs_device *pcs; 1675 struct pcs_interrupt *pcswi; 1676 1677 pcs = container_of(pcs_soc, struct pcs_device, socdata); 1678 pcswi = devm_kzalloc(pcs->dev, sizeof(*pcswi), GFP_KERNEL); 1679 if (!pcswi) 1680 return -ENOMEM; 1681 1682 pcswi->reg = pcs->base + hwirq; 1683 pcswi->hwirq = hwirq; 1684 pcswi->irq = irq; 1685 1686 mutex_lock(&pcs->mutex); 1687 list_add_tail(&pcswi->node, &pcs->irqs); 1688 mutex_unlock(&pcs->mutex); 1689 1690 irq_set_chip_data(irq, pcs_soc); 1691 irq_set_chip_and_handler(irq, &pcs->chip, 1692 handle_level_irq); 1693 irq_set_lockdep_class(irq, &pcs_lock_class); 1694 irq_set_noprobe(irq); 1695 1696 return 0; 1697 } 1698 1699 static const struct irq_domain_ops pcs_irqdomain_ops = { 1700 .map = pcs_irqdomain_map, 1701 .xlate = irq_domain_xlate_onecell, 1702 }; 1703 1704 /** 1705 * pcs_irq_init_chained_handler() - set up a chained interrupt handler 1706 * @pcs: pcs driver instance 1707 * @np: device node pointer 1708 */ 1709 static int pcs_irq_init_chained_handler(struct pcs_device *pcs, 1710 struct device_node *np) 1711 { 1712 struct pcs_soc_data *pcs_soc = &pcs->socdata; 1713 const char *name = "pinctrl"; 1714 int num_irqs; 1715 1716 if (!pcs_soc->irq_enable_mask || 1717 !pcs_soc->irq_status_mask) { 1718 pcs_soc->irq = -1; 1719 return -EINVAL; 1720 } 1721 1722 INIT_LIST_HEAD(&pcs->irqs); 1723 pcs->chip.name = name; 1724 pcs->chip.irq_ack = pcs_irq_mask; 1725 pcs->chip.irq_mask = pcs_irq_mask; 1726 pcs->chip.irq_unmask = pcs_irq_unmask; 1727 pcs->chip.irq_set_wake = pcs_irq_set_wake; 1728 1729 if (PCS_QUIRK_HAS_SHARED_IRQ) { 1730 int res; 1731 1732 res = request_irq(pcs_soc->irq, pcs_irq_handler, 1733 IRQF_SHARED | IRQF_NO_SUSPEND | 1734 IRQF_NO_THREAD, 1735 name, pcs_soc); 1736 if (res) { 1737 pcs_soc->irq = -1; 1738 return res; 1739 } 1740 } else { 1741 irq_set_chained_handler_and_data(pcs_soc->irq, 1742 pcs_irq_chain_handler, 1743 pcs_soc); 1744 } 1745 1746 /* 1747 * We can use the register offset as the hardirq 1748 * number as irq_domain_add_simple maps them lazily. 1749 * This way we can easily support more than one 1750 * interrupt per function if needed. 1751 */ 1752 num_irqs = pcs->size; 1753 1754 pcs->domain = irq_domain_add_simple(np, num_irqs, 0, 1755 &pcs_irqdomain_ops, 1756 pcs_soc); 1757 if (!pcs->domain) { 1758 irq_set_chained_handler(pcs_soc->irq, NULL); 1759 return -EINVAL; 1760 } 1761 1762 return 0; 1763 } 1764 1765 #ifdef CONFIG_PM 1766 static int pinctrl_single_suspend(struct platform_device *pdev, 1767 pm_message_t state) 1768 { 1769 struct pcs_device *pcs; 1770 1771 pcs = platform_get_drvdata(pdev); 1772 if (!pcs) 1773 return -EINVAL; 1774 1775 return pinctrl_force_sleep(pcs->pctl); 1776 } 1777 1778 static int pinctrl_single_resume(struct platform_device *pdev) 1779 { 1780 struct pcs_device *pcs; 1781 1782 pcs = platform_get_drvdata(pdev); 1783 if (!pcs) 1784 return -EINVAL; 1785 1786 return pinctrl_force_default(pcs->pctl); 1787 } 1788 #endif 1789 1790 static int pcs_probe(struct platform_device *pdev) 1791 { 1792 struct device_node *np = pdev->dev.of_node; 1793 const struct of_device_id *match; 1794 struct pcs_pdata *pdata; 1795 struct resource *res; 1796 struct pcs_device *pcs; 1797 const struct pcs_soc_data *soc; 1798 int ret; 1799 1800 match = of_match_device(pcs_of_match, &pdev->dev); 1801 if (!match) 1802 return -EINVAL; 1803 1804 pcs = devm_kzalloc(&pdev->dev, sizeof(*pcs), GFP_KERNEL); 1805 if (!pcs) { 1806 dev_err(&pdev->dev, "could not allocate\n"); 1807 return -ENOMEM; 1808 } 1809 pcs->dev = &pdev->dev; 1810 raw_spin_lock_init(&pcs->lock); 1811 mutex_init(&pcs->mutex); 1812 INIT_LIST_HEAD(&pcs->pingroups); 1813 INIT_LIST_HEAD(&pcs->functions); 1814 INIT_LIST_HEAD(&pcs->gpiofuncs); 1815 soc = match->data; 1816 pcs->flags = soc->flags; 1817 memcpy(&pcs->socdata, soc, sizeof(*soc)); 1818 1819 ret = of_property_read_u32(np, "pinctrl-single,register-width", 1820 &pcs->width); 1821 if (ret) { 1822 dev_err(pcs->dev, "register width not specified\n"); 1823 1824 return ret; 1825 } 1826 1827 ret = of_property_read_u32(np, "pinctrl-single,function-mask", 1828 &pcs->fmask); 1829 if (!ret) { 1830 pcs->fshift = __ffs(pcs->fmask); 1831 pcs->fmax = pcs->fmask >> pcs->fshift; 1832 } else { 1833 /* If mask property doesn't exist, function mux is invalid. */ 1834 pcs->fmask = 0; 1835 pcs->fshift = 0; 1836 pcs->fmax = 0; 1837 } 1838 1839 ret = of_property_read_u32(np, "pinctrl-single,function-off", 1840 &pcs->foff); 1841 if (ret) 1842 pcs->foff = PCS_OFF_DISABLED; 1843 1844 pcs->bits_per_mux = of_property_read_bool(np, 1845 "pinctrl-single,bit-per-mux"); 1846 1847 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1848 if (!res) { 1849 dev_err(pcs->dev, "could not get resource\n"); 1850 return -ENODEV; 1851 } 1852 1853 pcs->res = devm_request_mem_region(pcs->dev, res->start, 1854 resource_size(res), DRIVER_NAME); 1855 if (!pcs->res) { 1856 dev_err(pcs->dev, "could not get mem_region\n"); 1857 return -EBUSY; 1858 } 1859 1860 pcs->size = resource_size(pcs->res); 1861 pcs->base = devm_ioremap(pcs->dev, pcs->res->start, pcs->size); 1862 if (!pcs->base) { 1863 dev_err(pcs->dev, "could not ioremap\n"); 1864 return -ENODEV; 1865 } 1866 1867 INIT_RADIX_TREE(&pcs->pgtree, GFP_KERNEL); 1868 INIT_RADIX_TREE(&pcs->ftree, GFP_KERNEL); 1869 platform_set_drvdata(pdev, pcs); 1870 1871 switch (pcs->width) { 1872 case 8: 1873 pcs->read = pcs_readb; 1874 pcs->write = pcs_writeb; 1875 break; 1876 case 16: 1877 pcs->read = pcs_readw; 1878 pcs->write = pcs_writew; 1879 break; 1880 case 32: 1881 pcs->read = pcs_readl; 1882 pcs->write = pcs_writel; 1883 break; 1884 default: 1885 break; 1886 } 1887 1888 pcs->desc.name = DRIVER_NAME; 1889 pcs->desc.pctlops = &pcs_pinctrl_ops; 1890 pcs->desc.pmxops = &pcs_pinmux_ops; 1891 if (PCS_HAS_PINCONF) 1892 pcs->desc.confops = &pcs_pinconf_ops; 1893 pcs->desc.owner = THIS_MODULE; 1894 1895 ret = pcs_allocate_pin_table(pcs); 1896 if (ret < 0) 1897 goto free; 1898 1899 pcs->pctl = pinctrl_register(&pcs->desc, pcs->dev, pcs); 1900 if (IS_ERR(pcs->pctl)) { 1901 dev_err(pcs->dev, "could not register single pinctrl driver\n"); 1902 ret = PTR_ERR(pcs->pctl); 1903 goto free; 1904 } 1905 1906 ret = pcs_add_gpio_func(np, pcs); 1907 if (ret < 0) 1908 goto free; 1909 1910 pcs->socdata.irq = irq_of_parse_and_map(np, 0); 1911 if (pcs->socdata.irq) 1912 pcs->flags |= PCS_FEAT_IRQ; 1913 1914 /* We still need auxdata for some omaps for PRM interrupts */ 1915 pdata = dev_get_platdata(&pdev->dev); 1916 if (pdata) { 1917 if (pdata->rearm) 1918 pcs->socdata.rearm = pdata->rearm; 1919 if (pdata->irq) { 1920 pcs->socdata.irq = pdata->irq; 1921 pcs->flags |= PCS_FEAT_IRQ; 1922 } 1923 } 1924 1925 if (PCS_HAS_IRQ) { 1926 ret = pcs_irq_init_chained_handler(pcs, np); 1927 if (ret < 0) 1928 dev_warn(pcs->dev, "initialized with no interrupts\n"); 1929 } 1930 1931 dev_info(pcs->dev, "%i pins at pa %p size %u\n", 1932 pcs->desc.npins, pcs->base, pcs->size); 1933 1934 return 0; 1935 1936 free: 1937 pcs_free_resources(pcs); 1938 1939 return ret; 1940 } 1941 1942 static int pcs_remove(struct platform_device *pdev) 1943 { 1944 struct pcs_device *pcs = platform_get_drvdata(pdev); 1945 1946 if (!pcs) 1947 return 0; 1948 1949 pcs_free_resources(pcs); 1950 1951 return 0; 1952 } 1953 1954 static const struct pcs_soc_data pinctrl_single_omap_wkup = { 1955 .flags = PCS_QUIRK_SHARED_IRQ, 1956 .irq_enable_mask = (1 << 14), /* OMAP_WAKEUP_EN */ 1957 .irq_status_mask = (1 << 15), /* OMAP_WAKEUP_EVENT */ 1958 }; 1959 1960 static const struct pcs_soc_data pinctrl_single_dra7 = { 1961 .irq_enable_mask = (1 << 24), /* WAKEUPENABLE */ 1962 .irq_status_mask = (1 << 25), /* WAKEUPEVENT */ 1963 }; 1964 1965 static const struct pcs_soc_data pinctrl_single_am437x = { 1966 .flags = PCS_QUIRK_SHARED_IRQ, 1967 .irq_enable_mask = (1 << 29), /* OMAP_WAKEUP_EN */ 1968 .irq_status_mask = (1 << 30), /* OMAP_WAKEUP_EVENT */ 1969 }; 1970 1971 static const struct pcs_soc_data pinctrl_single = { 1972 }; 1973 1974 static const struct pcs_soc_data pinconf_single = { 1975 .flags = PCS_FEAT_PINCONF, 1976 }; 1977 1978 static const struct of_device_id pcs_of_match[] = { 1979 { .compatible = "ti,omap3-padconf", .data = &pinctrl_single_omap_wkup }, 1980 { .compatible = "ti,omap4-padconf", .data = &pinctrl_single_omap_wkup }, 1981 { .compatible = "ti,omap5-padconf", .data = &pinctrl_single_omap_wkup }, 1982 { .compatible = "ti,dra7-padconf", .data = &pinctrl_single_dra7 }, 1983 { .compatible = "ti,am437-padconf", .data = &pinctrl_single_am437x }, 1984 { .compatible = "pinctrl-single", .data = &pinctrl_single }, 1985 { .compatible = "pinconf-single", .data = &pinconf_single }, 1986 { }, 1987 }; 1988 MODULE_DEVICE_TABLE(of, pcs_of_match); 1989 1990 static struct platform_driver pcs_driver = { 1991 .probe = pcs_probe, 1992 .remove = pcs_remove, 1993 .driver = { 1994 .name = DRIVER_NAME, 1995 .of_match_table = pcs_of_match, 1996 }, 1997 #ifdef CONFIG_PM 1998 .suspend = pinctrl_single_suspend, 1999 .resume = pinctrl_single_resume, 2000 #endif 2001 }; 2002 2003 module_platform_driver(pcs_driver); 2004 2005 MODULE_AUTHOR("Tony Lindgren <tony@atomide.com>"); 2006 MODULE_DESCRIPTION("One-register-per-pin type device tree based pinctrl driver"); 2007 MODULE_LICENSE("GPL v2"); 2008