1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2020-2021 Rockchip Electronics Co. Ltd. 4 * 5 * Copyright (c) 2013 MundoReader S.L. 6 * Author: Heiko Stuebner <heiko@sntech.de> 7 * 8 * With some ideas taken from pinctrl-samsung: 9 * Copyright (c) 2012 Samsung Electronics Co., Ltd. 10 * http://www.samsung.com 11 * Copyright (c) 2012 Linaro Ltd 12 * https://www.linaro.org 13 * 14 * and pinctrl-at91: 15 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> 16 */ 17 18 #ifndef _PINCTRL_ROCKCHIP_H 19 #define _PINCTRL_ROCKCHIP_H 20 21 enum rockchip_pinctrl_type { 22 PX30, 23 RV1108, 24 RK2928, 25 RK3066B, 26 RK3128, 27 RK3188, 28 RK3288, 29 RK3308, 30 RK3368, 31 RK3399, 32 RK3568, 33 }; 34 35 /** 36 * struct rockchip_gpio_regs 37 * @port_dr: data register 38 * @port_ddr: data direction register 39 * @int_en: interrupt enable 40 * @int_mask: interrupt mask 41 * @int_type: interrupt trigger type, such as high, low, edge trriger type. 42 * @int_polarity: interrupt polarity enable register 43 * @int_bothedge: interrupt bothedge enable register 44 * @int_status: interrupt status register 45 * @int_rawstatus: int_status = int_rawstatus & int_mask 46 * @debounce: enable debounce for interrupt signal 47 * @dbclk_div_en: enable divider for debounce clock 48 * @dbclk_div_con: setting for divider of debounce clock 49 * @port_eoi: end of interrupt of the port 50 * @ext_port: port data from external 51 * @version_id: controller version register 52 */ 53 struct rockchip_gpio_regs { 54 u32 port_dr; 55 u32 port_ddr; 56 u32 int_en; 57 u32 int_mask; 58 u32 int_type; 59 u32 int_polarity; 60 u32 int_bothedge; 61 u32 int_status; 62 u32 int_rawstatus; 63 u32 debounce; 64 u32 dbclk_div_en; 65 u32 dbclk_div_con; 66 u32 port_eoi; 67 u32 ext_port; 68 u32 version_id; 69 }; 70 71 /** 72 * struct rockchip_iomux 73 * @type: iomux variant using IOMUX_* constants 74 * @offset: if initialized to -1 it will be autocalculated, by specifying 75 * an initial offset value the relevant source offset can be reset 76 * to a new value for autocalculating the following iomux registers. 77 */ 78 struct rockchip_iomux { 79 int type; 80 int offset; 81 }; 82 83 /* 84 * enum type index corresponding to rockchip_perpin_drv_list arrays index. 85 */ 86 enum rockchip_pin_drv_type { 87 DRV_TYPE_IO_DEFAULT = 0, 88 DRV_TYPE_IO_1V8_OR_3V0, 89 DRV_TYPE_IO_1V8_ONLY, 90 DRV_TYPE_IO_1V8_3V0_AUTO, 91 DRV_TYPE_IO_3V3_ONLY, 92 DRV_TYPE_MAX 93 }; 94 95 /* 96 * enum type index corresponding to rockchip_pull_list arrays index. 97 */ 98 enum rockchip_pin_pull_type { 99 PULL_TYPE_IO_DEFAULT = 0, 100 PULL_TYPE_IO_1V8_ONLY, 101 PULL_TYPE_MAX 102 }; 103 104 /** 105 * struct rockchip_drv 106 * @drv_type: drive strength variant using rockchip_perpin_drv_type 107 * @offset: if initialized to -1 it will be autocalculated, by specifying 108 * an initial offset value the relevant source offset can be reset 109 * to a new value for autocalculating the following drive strength 110 * registers. if used chips own cal_drv func instead to calculate 111 * registers offset, the variant could be ignored. 112 */ 113 struct rockchip_drv { 114 enum rockchip_pin_drv_type drv_type; 115 int offset; 116 }; 117 118 /** 119 * struct rockchip_pin_bank 120 * @dev: the pinctrl device bind to the bank 121 * @reg_base: register base of the gpio bank 122 * @regmap_pull: optional separate register for additional pull settings 123 * @clk: clock of the gpio bank 124 * @db_clk: clock of the gpio debounce 125 * @irq: interrupt of the gpio bank 126 * @saved_masks: Saved content of GPIO_INTEN at suspend time. 127 * @pin_base: first pin number 128 * @nr_pins: number of pins in this bank 129 * @name: name of the bank 130 * @bank_num: number of the bank, to account for holes 131 * @iomux: array describing the 4 iomux sources of the bank 132 * @drv: array describing the 4 drive strength sources of the bank 133 * @pull_type: array describing the 4 pull type sources of the bank 134 * @valid: is all necessary information present 135 * @of_node: dt node of this bank 136 * @drvdata: common pinctrl basedata 137 * @domain: irqdomain of the gpio bank 138 * @gpio_chip: gpiolib chip 139 * @grange: gpio range 140 * @slock: spinlock for the gpio bank 141 * @toggle_edge_mode: bit mask to toggle (falling/rising) edge mode 142 * @recalced_mask: bit mask to indicate a need to recalulate the mask 143 * @route_mask: bits describing the routing pins of per bank 144 */ 145 struct rockchip_pin_bank { 146 struct device *dev; 147 void __iomem *reg_base; 148 struct regmap *regmap_pull; 149 struct clk *clk; 150 struct clk *db_clk; 151 int irq; 152 u32 saved_masks; 153 u32 pin_base; 154 u8 nr_pins; 155 char *name; 156 u8 bank_num; 157 struct rockchip_iomux iomux[4]; 158 struct rockchip_drv drv[4]; 159 enum rockchip_pin_pull_type pull_type[4]; 160 bool valid; 161 struct device_node *of_node; 162 struct rockchip_pinctrl *drvdata; 163 struct irq_domain *domain; 164 struct gpio_chip gpio_chip; 165 struct pinctrl_gpio_range grange; 166 raw_spinlock_t slock; 167 const struct rockchip_gpio_regs *gpio_regs; 168 u32 gpio_type; 169 u32 toggle_edge_mode; 170 u32 recalced_mask; 171 u32 route_mask; 172 }; 173 174 /** 175 * struct rockchip_mux_recalced_data: represent a pin iomux data. 176 * @num: bank number. 177 * @pin: pin number. 178 * @bit: index at register. 179 * @reg: register offset. 180 * @mask: mask bit 181 */ 182 struct rockchip_mux_recalced_data { 183 u8 num; 184 u8 pin; 185 u32 reg; 186 u8 bit; 187 u8 mask; 188 }; 189 190 enum rockchip_mux_route_location { 191 ROCKCHIP_ROUTE_SAME = 0, 192 ROCKCHIP_ROUTE_PMU, 193 ROCKCHIP_ROUTE_GRF, 194 }; 195 196 /** 197 * struct rockchip_mux_recalced_data: represent a pin iomux data. 198 * @bank_num: bank number. 199 * @pin: index at register or used to calc index. 200 * @func: the min pin. 201 * @route_location: the mux route location (same, pmu, grf). 202 * @route_offset: the max pin. 203 * @route_val: the register offset. 204 */ 205 struct rockchip_mux_route_data { 206 u8 bank_num; 207 u8 pin; 208 u8 func; 209 enum rockchip_mux_route_location route_location; 210 u32 route_offset; 211 u32 route_val; 212 }; 213 214 struct rockchip_pin_ctrl { 215 struct rockchip_pin_bank *pin_banks; 216 u32 nr_banks; 217 u32 nr_pins; 218 char *label; 219 enum rockchip_pinctrl_type type; 220 int grf_mux_offset; 221 int pmu_mux_offset; 222 int grf_drv_offset; 223 int pmu_drv_offset; 224 struct rockchip_mux_recalced_data *iomux_recalced; 225 u32 niomux_recalced; 226 struct rockchip_mux_route_data *iomux_routes; 227 u32 niomux_routes; 228 229 void (*pull_calc_reg)(struct rockchip_pin_bank *bank, 230 int pin_num, struct regmap **regmap, 231 int *reg, u8 *bit); 232 void (*drv_calc_reg)(struct rockchip_pin_bank *bank, 233 int pin_num, struct regmap **regmap, 234 int *reg, u8 *bit); 235 int (*schmitt_calc_reg)(struct rockchip_pin_bank *bank, 236 int pin_num, struct regmap **regmap, 237 int *reg, u8 *bit); 238 }; 239 240 struct rockchip_pin_config { 241 unsigned int func; 242 unsigned long *configs; 243 unsigned int nconfigs; 244 }; 245 246 /** 247 * struct rockchip_pin_group: represent group of pins of a pinmux function. 248 * @name: name of the pin group, used to lookup the group. 249 * @pins: the pins included in this group. 250 * @npins: number of pins included in this group. 251 * @data: local pin configuration 252 */ 253 struct rockchip_pin_group { 254 const char *name; 255 unsigned int npins; 256 unsigned int *pins; 257 struct rockchip_pin_config *data; 258 }; 259 260 /** 261 * struct rockchip_pmx_func: represent a pin function. 262 * @name: name of the pin function, used to lookup the function. 263 * @groups: one or more names of pin groups that provide this function. 264 * @ngroups: number of groups included in @groups. 265 */ 266 struct rockchip_pmx_func { 267 const char *name; 268 const char **groups; 269 u8 ngroups; 270 }; 271 272 struct rockchip_pinctrl { 273 struct regmap *regmap_base; 274 int reg_size; 275 struct regmap *regmap_pull; 276 struct regmap *regmap_pmu; 277 struct device *dev; 278 struct rockchip_pin_ctrl *ctrl; 279 struct pinctrl_desc pctl; 280 struct pinctrl_dev *pctl_dev; 281 struct rockchip_pin_group *groups; 282 unsigned int ngroups; 283 struct rockchip_pmx_func *functions; 284 unsigned int nfunctions; 285 }; 286 287 #endif 288