1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Pinctrl driver for Rockchip SoCs
4  *
5  * Copyright (c) 2013 MundoReader S.L.
6  * Author: Heiko Stuebner <heiko@sntech.de>
7  *
8  * With some ideas taken from pinctrl-samsung:
9  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
10  *		http://www.samsung.com
11  * Copyright (c) 2012 Linaro Ltd
12  *		http://www.linaro.org
13  *
14  * and pinctrl-at91:
15  * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
16  */
17 
18 #include <linux/init.h>
19 #include <linux/platform_device.h>
20 #include <linux/io.h>
21 #include <linux/bitops.h>
22 #include <linux/gpio/driver.h>
23 #include <linux/of_address.h>
24 #include <linux/of_irq.h>
25 #include <linux/pinctrl/machine.h>
26 #include <linux/pinctrl/pinconf.h>
27 #include <linux/pinctrl/pinctrl.h>
28 #include <linux/pinctrl/pinmux.h>
29 #include <linux/pinctrl/pinconf-generic.h>
30 #include <linux/irqchip/chained_irq.h>
31 #include <linux/clk.h>
32 #include <linux/regmap.h>
33 #include <linux/mfd/syscon.h>
34 #include <dt-bindings/pinctrl/rockchip.h>
35 
36 #include "core.h"
37 #include "pinconf.h"
38 
39 /* GPIO control registers */
40 #define GPIO_SWPORT_DR		0x00
41 #define GPIO_SWPORT_DDR		0x04
42 #define GPIO_INTEN		0x30
43 #define GPIO_INTMASK		0x34
44 #define GPIO_INTTYPE_LEVEL	0x38
45 #define GPIO_INT_POLARITY	0x3c
46 #define GPIO_INT_STATUS		0x40
47 #define GPIO_INT_RAWSTATUS	0x44
48 #define GPIO_DEBOUNCE		0x48
49 #define GPIO_PORTS_EOI		0x4c
50 #define GPIO_EXT_PORT		0x50
51 #define GPIO_LS_SYNC		0x60
52 
53 enum rockchip_pinctrl_type {
54 	PX30,
55 	RV1108,
56 	RK2928,
57 	RK3066B,
58 	RK3128,
59 	RK3188,
60 	RK3288,
61 	RK3308,
62 	RK3368,
63 	RK3399,
64 };
65 
66 /**
67  * Encode variants of iomux registers into a type variable
68  */
69 #define IOMUX_GPIO_ONLY		BIT(0)
70 #define IOMUX_WIDTH_4BIT	BIT(1)
71 #define IOMUX_SOURCE_PMU	BIT(2)
72 #define IOMUX_UNROUTED		BIT(3)
73 #define IOMUX_WIDTH_3BIT	BIT(4)
74 #define IOMUX_WIDTH_2BIT	BIT(5)
75 
76 /**
77  * @type: iomux variant using IOMUX_* constants
78  * @offset: if initialized to -1 it will be autocalculated, by specifying
79  *	    an initial offset value the relevant source offset can be reset
80  *	    to a new value for autocalculating the following iomux registers.
81  */
82 struct rockchip_iomux {
83 	int				type;
84 	int				offset;
85 };
86 
87 /**
88  * enum type index corresponding to rockchip_perpin_drv_list arrays index.
89  */
90 enum rockchip_pin_drv_type {
91 	DRV_TYPE_IO_DEFAULT = 0,
92 	DRV_TYPE_IO_1V8_OR_3V0,
93 	DRV_TYPE_IO_1V8_ONLY,
94 	DRV_TYPE_IO_1V8_3V0_AUTO,
95 	DRV_TYPE_IO_3V3_ONLY,
96 	DRV_TYPE_MAX
97 };
98 
99 /**
100  * enum type index corresponding to rockchip_pull_list arrays index.
101  */
102 enum rockchip_pin_pull_type {
103 	PULL_TYPE_IO_DEFAULT = 0,
104 	PULL_TYPE_IO_1V8_ONLY,
105 	PULL_TYPE_MAX
106 };
107 
108 /**
109  * @drv_type: drive strength variant using rockchip_perpin_drv_type
110  * @offset: if initialized to -1 it will be autocalculated, by specifying
111  *	    an initial offset value the relevant source offset can be reset
112  *	    to a new value for autocalculating the following drive strength
113  *	    registers. if used chips own cal_drv func instead to calculate
114  *	    registers offset, the variant could be ignored.
115  */
116 struct rockchip_drv {
117 	enum rockchip_pin_drv_type	drv_type;
118 	int				offset;
119 };
120 
121 /**
122  * @reg_base: register base of the gpio bank
123  * @reg_pull: optional separate register for additional pull settings
124  * @clk: clock of the gpio bank
125  * @irq: interrupt of the gpio bank
126  * @saved_masks: Saved content of GPIO_INTEN at suspend time.
127  * @pin_base: first pin number
128  * @nr_pins: number of pins in this bank
129  * @name: name of the bank
130  * @bank_num: number of the bank, to account for holes
131  * @iomux: array describing the 4 iomux sources of the bank
132  * @drv: array describing the 4 drive strength sources of the bank
133  * @pull_type: array describing the 4 pull type sources of the bank
134  * @valid: is all necessary information present
135  * @of_node: dt node of this bank
136  * @drvdata: common pinctrl basedata
137  * @domain: irqdomain of the gpio bank
138  * @gpio_chip: gpiolib chip
139  * @grange: gpio range
140  * @slock: spinlock for the gpio bank
141  * @route_mask: bits describing the routing pins of per bank
142  */
143 struct rockchip_pin_bank {
144 	void __iomem			*reg_base;
145 	struct regmap			*regmap_pull;
146 	struct clk			*clk;
147 	int				irq;
148 	u32				saved_masks;
149 	u32				pin_base;
150 	u8				nr_pins;
151 	char				*name;
152 	u8				bank_num;
153 	struct rockchip_iomux		iomux[4];
154 	struct rockchip_drv		drv[4];
155 	enum rockchip_pin_pull_type	pull_type[4];
156 	bool				valid;
157 	struct device_node		*of_node;
158 	struct rockchip_pinctrl		*drvdata;
159 	struct irq_domain		*domain;
160 	struct gpio_chip		gpio_chip;
161 	struct pinctrl_gpio_range	grange;
162 	raw_spinlock_t			slock;
163 	u32				toggle_edge_mode;
164 	u32				recalced_mask;
165 	u32				route_mask;
166 };
167 
168 #define PIN_BANK(id, pins, label)			\
169 	{						\
170 		.bank_num	= id,			\
171 		.nr_pins	= pins,			\
172 		.name		= label,		\
173 		.iomux		= {			\
174 			{ .offset = -1 },		\
175 			{ .offset = -1 },		\
176 			{ .offset = -1 },		\
177 			{ .offset = -1 },		\
178 		},					\
179 	}
180 
181 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3)	\
182 	{								\
183 		.bank_num	= id,					\
184 		.nr_pins	= pins,					\
185 		.name		= label,				\
186 		.iomux		= {					\
187 			{ .type = iom0, .offset = -1 },			\
188 			{ .type = iom1, .offset = -1 },			\
189 			{ .type = iom2, .offset = -1 },			\
190 			{ .type = iom3, .offset = -1 },			\
191 		},							\
192 	}
193 
194 #define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \
195 	{								\
196 		.bank_num	= id,					\
197 		.nr_pins	= pins,					\
198 		.name		= label,				\
199 		.iomux		= {					\
200 			{ .offset = -1 },				\
201 			{ .offset = -1 },				\
202 			{ .offset = -1 },				\
203 			{ .offset = -1 },				\
204 		},							\
205 		.drv		= {					\
206 			{ .drv_type = type0, .offset = -1 },		\
207 			{ .drv_type = type1, .offset = -1 },		\
208 			{ .drv_type = type2, .offset = -1 },		\
209 			{ .drv_type = type3, .offset = -1 },		\
210 		},							\
211 	}
212 
213 #define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1,	\
214 				      drv2, drv3, pull0, pull1,		\
215 				      pull2, pull3)			\
216 	{								\
217 		.bank_num	= id,					\
218 		.nr_pins	= pins,					\
219 		.name		= label,				\
220 		.iomux		= {					\
221 			{ .offset = -1 },				\
222 			{ .offset = -1 },				\
223 			{ .offset = -1 },				\
224 			{ .offset = -1 },				\
225 		},							\
226 		.drv		= {					\
227 			{ .drv_type = drv0, .offset = -1 },		\
228 			{ .drv_type = drv1, .offset = -1 },		\
229 			{ .drv_type = drv2, .offset = -1 },		\
230 			{ .drv_type = drv3, .offset = -1 },		\
231 		},							\
232 		.pull_type[0] = pull0,					\
233 		.pull_type[1] = pull1,					\
234 		.pull_type[2] = pull2,					\
235 		.pull_type[3] = pull3,					\
236 	}
237 
238 #define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1,	\
239 					iom2, iom3, drv0, drv1, drv2,	\
240 					drv3, offset0, offset1,		\
241 					offset2, offset3)		\
242 	{								\
243 		.bank_num	= id,					\
244 		.nr_pins	= pins,					\
245 		.name		= label,				\
246 		.iomux		= {					\
247 			{ .type = iom0, .offset = -1 },			\
248 			{ .type = iom1, .offset = -1 },			\
249 			{ .type = iom2, .offset = -1 },			\
250 			{ .type = iom3, .offset = -1 },			\
251 		},							\
252 		.drv		= {					\
253 			{ .drv_type = drv0, .offset = offset0 },	\
254 			{ .drv_type = drv1, .offset = offset1 },	\
255 			{ .drv_type = drv2, .offset = offset2 },	\
256 			{ .drv_type = drv3, .offset = offset3 },	\
257 		},							\
258 	}
259 
260 #define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins,	\
261 					      label, iom0, iom1, iom2,  \
262 					      iom3, drv0, drv1, drv2,   \
263 					      drv3, offset0, offset1,   \
264 					      offset2, offset3, pull0,  \
265 					      pull1, pull2, pull3)	\
266 	{								\
267 		.bank_num	= id,					\
268 		.nr_pins	= pins,					\
269 		.name		= label,				\
270 		.iomux		= {					\
271 			{ .type = iom0, .offset = -1 },			\
272 			{ .type = iom1, .offset = -1 },			\
273 			{ .type = iom2, .offset = -1 },			\
274 			{ .type = iom3, .offset = -1 },			\
275 		},							\
276 		.drv		= {					\
277 			{ .drv_type = drv0, .offset = offset0 },	\
278 			{ .drv_type = drv1, .offset = offset1 },	\
279 			{ .drv_type = drv2, .offset = offset2 },	\
280 			{ .drv_type = drv3, .offset = offset3 },	\
281 		},							\
282 		.pull_type[0] = pull0,					\
283 		.pull_type[1] = pull1,					\
284 		.pull_type[2] = pull2,					\
285 		.pull_type[3] = pull3,					\
286 	}
287 
288 /**
289  * struct rockchip_mux_recalced_data: represent a pin iomux data.
290  * @num: bank number.
291  * @pin: pin number.
292  * @bit: index at register.
293  * @reg: register offset.
294  * @mask: mask bit
295  */
296 struct rockchip_mux_recalced_data {
297 	u8 num;
298 	u8 pin;
299 	u32 reg;
300 	u8 bit;
301 	u8 mask;
302 };
303 
304 enum rockchip_mux_route_location {
305 	ROCKCHIP_ROUTE_SAME = 0,
306 	ROCKCHIP_ROUTE_PMU,
307 	ROCKCHIP_ROUTE_GRF,
308 };
309 
310 /**
311  * struct rockchip_mux_recalced_data: represent a pin iomux data.
312  * @bank_num: bank number.
313  * @pin: index at register or used to calc index.
314  * @func: the min pin.
315  * @route_offset: the max pin.
316  * @route_val: the register offset.
317  */
318 struct rockchip_mux_route_data {
319 	u8 bank_num;
320 	u8 pin;
321 	u8 func;
322 	enum rockchip_mux_route_location route_location;
323 	u32 route_offset;
324 	u32 route_val;
325 };
326 
327 /**
328  */
329 struct rockchip_pin_ctrl {
330 	struct rockchip_pin_bank	*pin_banks;
331 	u32				nr_banks;
332 	u32				nr_pins;
333 	char				*label;
334 	enum rockchip_pinctrl_type	type;
335 	int				grf_mux_offset;
336 	int				pmu_mux_offset;
337 	int				grf_drv_offset;
338 	int				pmu_drv_offset;
339 	struct rockchip_mux_recalced_data *iomux_recalced;
340 	u32				niomux_recalced;
341 	struct rockchip_mux_route_data *iomux_routes;
342 	u32				niomux_routes;
343 
344 	void	(*pull_calc_reg)(struct rockchip_pin_bank *bank,
345 				    int pin_num, struct regmap **regmap,
346 				    int *reg, u8 *bit);
347 	void	(*drv_calc_reg)(struct rockchip_pin_bank *bank,
348 				    int pin_num, struct regmap **regmap,
349 				    int *reg, u8 *bit);
350 	int	(*schmitt_calc_reg)(struct rockchip_pin_bank *bank,
351 				    int pin_num, struct regmap **regmap,
352 				    int *reg, u8 *bit);
353 };
354 
355 struct rockchip_pin_config {
356 	unsigned int		func;
357 	unsigned long		*configs;
358 	unsigned int		nconfigs;
359 };
360 
361 /**
362  * struct rockchip_pin_group: represent group of pins of a pinmux function.
363  * @name: name of the pin group, used to lookup the group.
364  * @pins: the pins included in this group.
365  * @npins: number of pins included in this group.
366  * @func: the mux function number to be programmed when selected.
367  * @configs: the config values to be set for each pin
368  * @nconfigs: number of configs for each pin
369  */
370 struct rockchip_pin_group {
371 	const char			*name;
372 	unsigned int			npins;
373 	unsigned int			*pins;
374 	struct rockchip_pin_config	*data;
375 };
376 
377 /**
378  * struct rockchip_pmx_func: represent a pin function.
379  * @name: name of the pin function, used to lookup the function.
380  * @groups: one or more names of pin groups that provide this function.
381  * @num_groups: number of groups included in @groups.
382  */
383 struct rockchip_pmx_func {
384 	const char		*name;
385 	const char		**groups;
386 	u8			ngroups;
387 };
388 
389 struct rockchip_pinctrl {
390 	struct regmap			*regmap_base;
391 	int				reg_size;
392 	struct regmap			*regmap_pull;
393 	struct regmap			*regmap_pmu;
394 	struct device			*dev;
395 	struct rockchip_pin_ctrl	*ctrl;
396 	struct pinctrl_desc		pctl;
397 	struct pinctrl_dev		*pctl_dev;
398 	struct rockchip_pin_group	*groups;
399 	unsigned int			ngroups;
400 	struct rockchip_pmx_func	*functions;
401 	unsigned int			nfunctions;
402 };
403 
404 static struct regmap_config rockchip_regmap_config = {
405 	.reg_bits = 32,
406 	.val_bits = 32,
407 	.reg_stride = 4,
408 };
409 
410 static inline const struct rockchip_pin_group *pinctrl_name_to_group(
411 					const struct rockchip_pinctrl *info,
412 					const char *name)
413 {
414 	int i;
415 
416 	for (i = 0; i < info->ngroups; i++) {
417 		if (!strcmp(info->groups[i].name, name))
418 			return &info->groups[i];
419 	}
420 
421 	return NULL;
422 }
423 
424 /*
425  * given a pin number that is local to a pin controller, find out the pin bank
426  * and the register base of the pin bank.
427  */
428 static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info,
429 								unsigned pin)
430 {
431 	struct rockchip_pin_bank *b = info->ctrl->pin_banks;
432 
433 	while (pin >= (b->pin_base + b->nr_pins))
434 		b++;
435 
436 	return b;
437 }
438 
439 static struct rockchip_pin_bank *bank_num_to_bank(
440 					struct rockchip_pinctrl *info,
441 					unsigned num)
442 {
443 	struct rockchip_pin_bank *b = info->ctrl->pin_banks;
444 	int i;
445 
446 	for (i = 0; i < info->ctrl->nr_banks; i++, b++) {
447 		if (b->bank_num == num)
448 			return b;
449 	}
450 
451 	return ERR_PTR(-EINVAL);
452 }
453 
454 /*
455  * Pinctrl_ops handling
456  */
457 
458 static int rockchip_get_groups_count(struct pinctrl_dev *pctldev)
459 {
460 	struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
461 
462 	return info->ngroups;
463 }
464 
465 static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev,
466 							unsigned selector)
467 {
468 	struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
469 
470 	return info->groups[selector].name;
471 }
472 
473 static int rockchip_get_group_pins(struct pinctrl_dev *pctldev,
474 				      unsigned selector, const unsigned **pins,
475 				      unsigned *npins)
476 {
477 	struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
478 
479 	if (selector >= info->ngroups)
480 		return -EINVAL;
481 
482 	*pins = info->groups[selector].pins;
483 	*npins = info->groups[selector].npins;
484 
485 	return 0;
486 }
487 
488 static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev,
489 				 struct device_node *np,
490 				 struct pinctrl_map **map, unsigned *num_maps)
491 {
492 	struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
493 	const struct rockchip_pin_group *grp;
494 	struct pinctrl_map *new_map;
495 	struct device_node *parent;
496 	int map_num = 1;
497 	int i;
498 
499 	/*
500 	 * first find the group of this node and check if we need to create
501 	 * config maps for pins
502 	 */
503 	grp = pinctrl_name_to_group(info, np->name);
504 	if (!grp) {
505 		dev_err(info->dev, "unable to find group for node %pOFn\n",
506 			np);
507 		return -EINVAL;
508 	}
509 
510 	map_num += grp->npins;
511 
512 	new_map = kcalloc(map_num, sizeof(*new_map), GFP_KERNEL);
513 	if (!new_map)
514 		return -ENOMEM;
515 
516 	*map = new_map;
517 	*num_maps = map_num;
518 
519 	/* create mux map */
520 	parent = of_get_parent(np);
521 	if (!parent) {
522 		kfree(new_map);
523 		return -EINVAL;
524 	}
525 	new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
526 	new_map[0].data.mux.function = parent->name;
527 	new_map[0].data.mux.group = np->name;
528 	of_node_put(parent);
529 
530 	/* create config map */
531 	new_map++;
532 	for (i = 0; i < grp->npins; i++) {
533 		new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
534 		new_map[i].data.configs.group_or_pin =
535 				pin_get_name(pctldev, grp->pins[i]);
536 		new_map[i].data.configs.configs = grp->data[i].configs;
537 		new_map[i].data.configs.num_configs = grp->data[i].nconfigs;
538 	}
539 
540 	dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
541 		(*map)->data.mux.function, (*map)->data.mux.group, map_num);
542 
543 	return 0;
544 }
545 
546 static void rockchip_dt_free_map(struct pinctrl_dev *pctldev,
547 				    struct pinctrl_map *map, unsigned num_maps)
548 {
549 	kfree(map);
550 }
551 
552 static const struct pinctrl_ops rockchip_pctrl_ops = {
553 	.get_groups_count	= rockchip_get_groups_count,
554 	.get_group_name		= rockchip_get_group_name,
555 	.get_group_pins		= rockchip_get_group_pins,
556 	.dt_node_to_map		= rockchip_dt_node_to_map,
557 	.dt_free_map		= rockchip_dt_free_map,
558 };
559 
560 /*
561  * Hardware access
562  */
563 
564 static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = {
565 	{
566 		.num = 1,
567 		.pin = 0,
568 		.reg = 0x418,
569 		.bit = 0,
570 		.mask = 0x3
571 	}, {
572 		.num = 1,
573 		.pin = 1,
574 		.reg = 0x418,
575 		.bit = 2,
576 		.mask = 0x3
577 	}, {
578 		.num = 1,
579 		.pin = 2,
580 		.reg = 0x418,
581 		.bit = 4,
582 		.mask = 0x3
583 	}, {
584 		.num = 1,
585 		.pin = 3,
586 		.reg = 0x418,
587 		.bit = 6,
588 		.mask = 0x3
589 	}, {
590 		.num = 1,
591 		.pin = 4,
592 		.reg = 0x418,
593 		.bit = 8,
594 		.mask = 0x3
595 	}, {
596 		.num = 1,
597 		.pin = 5,
598 		.reg = 0x418,
599 		.bit = 10,
600 		.mask = 0x3
601 	}, {
602 		.num = 1,
603 		.pin = 6,
604 		.reg = 0x418,
605 		.bit = 12,
606 		.mask = 0x3
607 	}, {
608 		.num = 1,
609 		.pin = 7,
610 		.reg = 0x418,
611 		.bit = 14,
612 		.mask = 0x3
613 	}, {
614 		.num = 1,
615 		.pin = 8,
616 		.reg = 0x41c,
617 		.bit = 0,
618 		.mask = 0x3
619 	}, {
620 		.num = 1,
621 		.pin = 9,
622 		.reg = 0x41c,
623 		.bit = 2,
624 		.mask = 0x3
625 	},
626 };
627 
628 static  struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = {
629 	{
630 		.num = 2,
631 		.pin = 20,
632 		.reg = 0xe8,
633 		.bit = 0,
634 		.mask = 0x7
635 	}, {
636 		.num = 2,
637 		.pin = 21,
638 		.reg = 0xe8,
639 		.bit = 4,
640 		.mask = 0x7
641 	}, {
642 		.num = 2,
643 		.pin = 22,
644 		.reg = 0xe8,
645 		.bit = 8,
646 		.mask = 0x7
647 	}, {
648 		.num = 2,
649 		.pin = 23,
650 		.reg = 0xe8,
651 		.bit = 12,
652 		.mask = 0x7
653 	}, {
654 		.num = 2,
655 		.pin = 24,
656 		.reg = 0xd4,
657 		.bit = 12,
658 		.mask = 0x7
659 	},
660 };
661 
662 static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = {
663 	{
664 		.num = 1,
665 		.pin = 14,
666 		.reg = 0x28,
667 		.bit = 12,
668 		.mask = 0xf
669 	}, {
670 		.num = 1,
671 		.pin = 15,
672 		.reg = 0x2c,
673 		.bit = 0,
674 		.mask = 0x3
675 	}, {
676 		.num = 1,
677 		.pin = 18,
678 		.reg = 0x30,
679 		.bit = 4,
680 		.mask = 0xf
681 	}, {
682 		.num = 1,
683 		.pin = 19,
684 		.reg = 0x30,
685 		.bit = 8,
686 		.mask = 0xf
687 	}, {
688 		.num = 1,
689 		.pin = 20,
690 		.reg = 0x30,
691 		.bit = 12,
692 		.mask = 0xf
693 	}, {
694 		.num = 1,
695 		.pin = 21,
696 		.reg = 0x34,
697 		.bit = 0,
698 		.mask = 0xf
699 	}, {
700 		.num = 1,
701 		.pin = 22,
702 		.reg = 0x34,
703 		.bit = 4,
704 		.mask = 0xf
705 	}, {
706 		.num = 1,
707 		.pin = 23,
708 		.reg = 0x34,
709 		.bit = 8,
710 		.mask = 0xf
711 	}, {
712 		.num = 3,
713 		.pin = 12,
714 		.reg = 0x68,
715 		.bit = 8,
716 		.mask = 0xf
717 	}, {
718 		.num = 3,
719 		.pin = 13,
720 		.reg = 0x68,
721 		.bit = 12,
722 		.mask = 0xf
723 	}, {
724 		.num = 2,
725 		.pin = 2,
726 		.reg = 0x608,
727 		.bit = 0,
728 		.mask = 0x7
729 	}, {
730 		.num = 2,
731 		.pin = 3,
732 		.reg = 0x608,
733 		.bit = 4,
734 		.mask = 0x7
735 	}, {
736 		.num = 2,
737 		.pin = 16,
738 		.reg = 0x610,
739 		.bit = 8,
740 		.mask = 0x7
741 	}, {
742 		.num = 3,
743 		.pin = 10,
744 		.reg = 0x610,
745 		.bit = 0,
746 		.mask = 0x7
747 	}, {
748 		.num = 3,
749 		.pin = 11,
750 		.reg = 0x610,
751 		.bit = 4,
752 		.mask = 0x7
753 	},
754 };
755 
756 static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = {
757 	{
758 		.num = 2,
759 		.pin = 12,
760 		.reg = 0x24,
761 		.bit = 8,
762 		.mask = 0x3
763 	}, {
764 		.num = 2,
765 		.pin = 15,
766 		.reg = 0x28,
767 		.bit = 0,
768 		.mask = 0x7
769 	}, {
770 		.num = 2,
771 		.pin = 23,
772 		.reg = 0x30,
773 		.bit = 14,
774 		.mask = 0x3
775 	},
776 };
777 
778 static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin,
779 				      int *reg, u8 *bit, int *mask)
780 {
781 	struct rockchip_pinctrl *info = bank->drvdata;
782 	struct rockchip_pin_ctrl *ctrl = info->ctrl;
783 	struct rockchip_mux_recalced_data *data;
784 	int i;
785 
786 	for (i = 0; i < ctrl->niomux_recalced; i++) {
787 		data = &ctrl->iomux_recalced[i];
788 		if (data->num == bank->bank_num &&
789 		    data->pin == pin)
790 			break;
791 	}
792 
793 	if (i >= ctrl->niomux_recalced)
794 		return;
795 
796 	*reg = data->reg;
797 	*mask = data->mask;
798 	*bit = data->bit;
799 }
800 
801 static struct rockchip_mux_route_data px30_mux_route_data[] = {
802 	{
803 		/* cif-d2m0 */
804 		.bank_num = 2,
805 		.pin = 0,
806 		.func = 1,
807 		.route_offset = 0x184,
808 		.route_val = BIT(16 + 7),
809 	}, {
810 		/* cif-d2m1 */
811 		.bank_num = 3,
812 		.pin = 3,
813 		.func = 3,
814 		.route_offset = 0x184,
815 		.route_val = BIT(16 + 7) | BIT(7),
816 	}, {
817 		/* pdm-m0 */
818 		.bank_num = 3,
819 		.pin = 22,
820 		.func = 2,
821 		.route_offset = 0x184,
822 		.route_val = BIT(16 + 8),
823 	}, {
824 		/* pdm-m1 */
825 		.bank_num = 2,
826 		.pin = 22,
827 		.func = 1,
828 		.route_offset = 0x184,
829 		.route_val = BIT(16 + 8) | BIT(8),
830 	}, {
831 		/* uart2-rxm0 */
832 		.bank_num = 1,
833 		.pin = 27,
834 		.func = 2,
835 		.route_offset = 0x184,
836 		.route_val = BIT(16 + 10),
837 	}, {
838 		/* uart2-rxm1 */
839 		.bank_num = 2,
840 		.pin = 14,
841 		.func = 2,
842 		.route_offset = 0x184,
843 		.route_val = BIT(16 + 10) | BIT(10),
844 	}, {
845 		/* uart3-rxm0 */
846 		.bank_num = 0,
847 		.pin = 17,
848 		.func = 2,
849 		.route_offset = 0x184,
850 		.route_val = BIT(16 + 9),
851 	}, {
852 		/* uart3-rxm1 */
853 		.bank_num = 1,
854 		.pin = 15,
855 		.func = 2,
856 		.route_offset = 0x184,
857 		.route_val = BIT(16 + 9) | BIT(9),
858 	},
859 };
860 
861 static struct rockchip_mux_route_data rk3128_mux_route_data[] = {
862 	{
863 		/* spi-0 */
864 		.bank_num = 1,
865 		.pin = 10,
866 		.func = 1,
867 		.route_offset = 0x144,
868 		.route_val = BIT(16 + 3) | BIT(16 + 4),
869 	}, {
870 		/* spi-1 */
871 		.bank_num = 1,
872 		.pin = 27,
873 		.func = 3,
874 		.route_offset = 0x144,
875 		.route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(3),
876 	}, {
877 		/* spi-2 */
878 		.bank_num = 0,
879 		.pin = 13,
880 		.func = 2,
881 		.route_offset = 0x144,
882 		.route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(4),
883 	}, {
884 		/* i2s-0 */
885 		.bank_num = 1,
886 		.pin = 5,
887 		.func = 1,
888 		.route_offset = 0x144,
889 		.route_val = BIT(16 + 5),
890 	}, {
891 		/* i2s-1 */
892 		.bank_num = 0,
893 		.pin = 14,
894 		.func = 1,
895 		.route_offset = 0x144,
896 		.route_val = BIT(16 + 5) | BIT(5),
897 	}, {
898 		/* emmc-0 */
899 		.bank_num = 1,
900 		.pin = 22,
901 		.func = 2,
902 		.route_offset = 0x144,
903 		.route_val = BIT(16 + 6),
904 	}, {
905 		/* emmc-1 */
906 		.bank_num = 2,
907 		.pin = 4,
908 		.func = 2,
909 		.route_offset = 0x144,
910 		.route_val = BIT(16 + 6) | BIT(6),
911 	},
912 };
913 
914 static struct rockchip_mux_route_data rk3188_mux_route_data[] = {
915 	{
916 		/* non-iomuxed emmc/flash pins on flash-dqs */
917 		.bank_num = 0,
918 		.pin = 24,
919 		.func = 1,
920 		.route_location = ROCKCHIP_ROUTE_GRF,
921 		.route_offset = 0xa0,
922 		.route_val = BIT(16 + 11),
923 	}, {
924 		/* non-iomuxed emmc/flash pins on emmc-clk */
925 		.bank_num = 0,
926 		.pin = 24,
927 		.func = 2,
928 		.route_location = ROCKCHIP_ROUTE_GRF,
929 		.route_offset = 0xa0,
930 		.route_val = BIT(16 + 11) | BIT(11),
931 	},
932 };
933 
934 static struct rockchip_mux_route_data rk3228_mux_route_data[] = {
935 	{
936 		/* pwm0-0 */
937 		.bank_num = 0,
938 		.pin = 26,
939 		.func = 1,
940 		.route_offset = 0x50,
941 		.route_val = BIT(16),
942 	}, {
943 		/* pwm0-1 */
944 		.bank_num = 3,
945 		.pin = 21,
946 		.func = 1,
947 		.route_offset = 0x50,
948 		.route_val = BIT(16) | BIT(0),
949 	}, {
950 		/* pwm1-0 */
951 		.bank_num = 0,
952 		.pin = 27,
953 		.func = 1,
954 		.route_offset = 0x50,
955 		.route_val = BIT(16 + 1),
956 	}, {
957 		/* pwm1-1 */
958 		.bank_num = 0,
959 		.pin = 30,
960 		.func = 2,
961 		.route_offset = 0x50,
962 		.route_val = BIT(16 + 1) | BIT(1),
963 	}, {
964 		/* pwm2-0 */
965 		.bank_num = 0,
966 		.pin = 28,
967 		.func = 1,
968 		.route_offset = 0x50,
969 		.route_val = BIT(16 + 2),
970 	}, {
971 		/* pwm2-1 */
972 		.bank_num = 1,
973 		.pin = 12,
974 		.func = 2,
975 		.route_offset = 0x50,
976 		.route_val = BIT(16 + 2) | BIT(2),
977 	}, {
978 		/* pwm3-0 */
979 		.bank_num = 3,
980 		.pin = 26,
981 		.func = 1,
982 		.route_offset = 0x50,
983 		.route_val = BIT(16 + 3),
984 	}, {
985 		/* pwm3-1 */
986 		.bank_num = 1,
987 		.pin = 11,
988 		.func = 2,
989 		.route_offset = 0x50,
990 		.route_val = BIT(16 + 3) | BIT(3),
991 	}, {
992 		/* sdio-0_d0 */
993 		.bank_num = 1,
994 		.pin = 1,
995 		.func = 1,
996 		.route_offset = 0x50,
997 		.route_val = BIT(16 + 4),
998 	}, {
999 		/* sdio-1_d0 */
1000 		.bank_num = 3,
1001 		.pin = 2,
1002 		.func = 1,
1003 		.route_offset = 0x50,
1004 		.route_val = BIT(16 + 4) | BIT(4),
1005 	}, {
1006 		/* spi-0_rx */
1007 		.bank_num = 0,
1008 		.pin = 13,
1009 		.func = 2,
1010 		.route_offset = 0x50,
1011 		.route_val = BIT(16 + 5),
1012 	}, {
1013 		/* spi-1_rx */
1014 		.bank_num = 2,
1015 		.pin = 0,
1016 		.func = 2,
1017 		.route_offset = 0x50,
1018 		.route_val = BIT(16 + 5) | BIT(5),
1019 	}, {
1020 		/* emmc-0_cmd */
1021 		.bank_num = 1,
1022 		.pin = 22,
1023 		.func = 2,
1024 		.route_offset = 0x50,
1025 		.route_val = BIT(16 + 7),
1026 	}, {
1027 		/* emmc-1_cmd */
1028 		.bank_num = 2,
1029 		.pin = 4,
1030 		.func = 2,
1031 		.route_offset = 0x50,
1032 		.route_val = BIT(16 + 7) | BIT(7),
1033 	}, {
1034 		/* uart2-0_rx */
1035 		.bank_num = 1,
1036 		.pin = 19,
1037 		.func = 2,
1038 		.route_offset = 0x50,
1039 		.route_val = BIT(16 + 8),
1040 	}, {
1041 		/* uart2-1_rx */
1042 		.bank_num = 1,
1043 		.pin = 10,
1044 		.func = 2,
1045 		.route_offset = 0x50,
1046 		.route_val = BIT(16 + 8) | BIT(8),
1047 	}, {
1048 		/* uart1-0_rx */
1049 		.bank_num = 1,
1050 		.pin = 10,
1051 		.func = 1,
1052 		.route_offset = 0x50,
1053 		.route_val = BIT(16 + 11),
1054 	}, {
1055 		/* uart1-1_rx */
1056 		.bank_num = 3,
1057 		.pin = 13,
1058 		.func = 1,
1059 		.route_offset = 0x50,
1060 		.route_val = BIT(16 + 11) | BIT(11),
1061 	},
1062 };
1063 
1064 static struct rockchip_mux_route_data rk3288_mux_route_data[] = {
1065 	{
1066 		/* edphdmi_cecinoutt1 */
1067 		.bank_num = 7,
1068 		.pin = 16,
1069 		.func = 2,
1070 		.route_offset = 0x264,
1071 		.route_val = BIT(16 + 12) | BIT(12),
1072 	}, {
1073 		/* edphdmi_cecinout */
1074 		.bank_num = 7,
1075 		.pin = 23,
1076 		.func = 4,
1077 		.route_offset = 0x264,
1078 		.route_val = BIT(16 + 12),
1079 	},
1080 };
1081 
1082 static struct rockchip_mux_route_data rk3308_mux_route_data[] = {
1083 	{
1084 		/* rtc_clk */
1085 		.bank_num = 0,
1086 		.pin = 19,
1087 		.func = 1,
1088 		.route_offset = 0x314,
1089 		.route_val = BIT(16 + 0) | BIT(0),
1090 	}, {
1091 		/* uart2_rxm0 */
1092 		.bank_num = 1,
1093 		.pin = 22,
1094 		.func = 2,
1095 		.route_offset = 0x314,
1096 		.route_val = BIT(16 + 2) | BIT(16 + 3),
1097 	}, {
1098 		/* uart2_rxm1 */
1099 		.bank_num = 4,
1100 		.pin = 26,
1101 		.func = 2,
1102 		.route_offset = 0x314,
1103 		.route_val = BIT(16 + 2) | BIT(16 + 3) | BIT(2),
1104 	}, {
1105 		/* i2c3_sdam0 */
1106 		.bank_num = 0,
1107 		.pin = 15,
1108 		.func = 2,
1109 		.route_offset = 0x608,
1110 		.route_val = BIT(16 + 8) | BIT(16 + 9),
1111 	}, {
1112 		/* i2c3_sdam1 */
1113 		.bank_num = 3,
1114 		.pin = 12,
1115 		.func = 2,
1116 		.route_offset = 0x608,
1117 		.route_val = BIT(16 + 8) | BIT(16 + 9) | BIT(8),
1118 	}, {
1119 		/* i2c3_sdam2 */
1120 		.bank_num = 2,
1121 		.pin = 0,
1122 		.func = 3,
1123 		.route_offset = 0x608,
1124 		.route_val = BIT(16 + 8) | BIT(16 + 9) | BIT(9),
1125 	}, {
1126 		/* i2s-8ch-1-sclktxm0 */
1127 		.bank_num = 1,
1128 		.pin = 3,
1129 		.func = 2,
1130 		.route_offset = 0x308,
1131 		.route_val = BIT(16 + 3),
1132 	}, {
1133 		/* i2s-8ch-1-sclkrxm0 */
1134 		.bank_num = 1,
1135 		.pin = 4,
1136 		.func = 2,
1137 		.route_offset = 0x308,
1138 		.route_val = BIT(16 + 3),
1139 	}, {
1140 		/* i2s-8ch-1-sclktxm1 */
1141 		.bank_num = 1,
1142 		.pin = 13,
1143 		.func = 2,
1144 		.route_offset = 0x308,
1145 		.route_val = BIT(16 + 3) | BIT(3),
1146 	}, {
1147 		/* i2s-8ch-1-sclkrxm1 */
1148 		.bank_num = 1,
1149 		.pin = 14,
1150 		.func = 2,
1151 		.route_offset = 0x308,
1152 		.route_val = BIT(16 + 3) | BIT(3),
1153 	}, {
1154 		/* pdm-clkm0 */
1155 		.bank_num = 1,
1156 		.pin = 4,
1157 		.func = 3,
1158 		.route_offset = 0x308,
1159 		.route_val =  BIT(16 + 12) | BIT(16 + 13),
1160 	}, {
1161 		/* pdm-clkm1 */
1162 		.bank_num = 1,
1163 		.pin = 14,
1164 		.func = 4,
1165 		.route_offset = 0x308,
1166 		.route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(12),
1167 	}, {
1168 		/* pdm-clkm2 */
1169 		.bank_num = 2,
1170 		.pin = 6,
1171 		.func = 2,
1172 		.route_offset = 0x308,
1173 		.route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(13),
1174 	}, {
1175 		/* pdm-clkm-m2 */
1176 		.bank_num = 2,
1177 		.pin = 4,
1178 		.func = 3,
1179 		.route_offset = 0x600,
1180 		.route_val = BIT(16 + 2) | BIT(2),
1181 	}, {
1182 		/* spi1_miso */
1183 		.bank_num = 3,
1184 		.pin = 10,
1185 		.func = 3,
1186 		.route_offset = 0x314,
1187 		.route_val = BIT(16 + 9),
1188 	}, {
1189 		/* spi1_miso_m1 */
1190 		.bank_num = 2,
1191 		.pin = 4,
1192 		.func = 2,
1193 		.route_offset = 0x314,
1194 		.route_val = BIT(16 + 9) | BIT(9),
1195 	}, {
1196 		/* owire_m0 */
1197 		.bank_num = 0,
1198 		.pin = 11,
1199 		.func = 3,
1200 		.route_offset = 0x314,
1201 		.route_val = BIT(16 + 10) | BIT(16 + 11),
1202 	}, {
1203 		/* owire_m1 */
1204 		.bank_num = 1,
1205 		.pin = 22,
1206 		.func = 7,
1207 		.route_offset = 0x314,
1208 		.route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10),
1209 	}, {
1210 		/* owire_m2 */
1211 		.bank_num = 2,
1212 		.pin = 2,
1213 		.func = 5,
1214 		.route_offset = 0x314,
1215 		.route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11),
1216 	}, {
1217 		/* can_rxd_m0 */
1218 		.bank_num = 0,
1219 		.pin = 11,
1220 		.func = 2,
1221 		.route_offset = 0x314,
1222 		.route_val = BIT(16 + 12) | BIT(16 + 13),
1223 	}, {
1224 		/* can_rxd_m1 */
1225 		.bank_num = 1,
1226 		.pin = 22,
1227 		.func = 5,
1228 		.route_offset = 0x314,
1229 		.route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(12),
1230 	}, {
1231 		/* can_rxd_m2 */
1232 		.bank_num = 2,
1233 		.pin = 2,
1234 		.func = 4,
1235 		.route_offset = 0x314,
1236 		.route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(13),
1237 	}, {
1238 		/* mac_rxd0_m0 */
1239 		.bank_num = 1,
1240 		.pin = 20,
1241 		.func = 3,
1242 		.route_offset = 0x314,
1243 		.route_val = BIT(16 + 14),
1244 	}, {
1245 		/* mac_rxd0_m1 */
1246 		.bank_num = 4,
1247 		.pin = 2,
1248 		.func = 2,
1249 		.route_offset = 0x314,
1250 		.route_val = BIT(16 + 14) | BIT(14),
1251 	}, {
1252 		/* uart3_rx */
1253 		.bank_num = 3,
1254 		.pin = 12,
1255 		.func = 4,
1256 		.route_offset = 0x314,
1257 		.route_val = BIT(16 + 15),
1258 	}, {
1259 		/* uart3_rx_m1 */
1260 		.bank_num = 0,
1261 		.pin = 17,
1262 		.func = 3,
1263 		.route_offset = 0x314,
1264 		.route_val = BIT(16 + 15) | BIT(15),
1265 	},
1266 };
1267 
1268 static struct rockchip_mux_route_data rk3328_mux_route_data[] = {
1269 	{
1270 		/* uart2dbg_rxm0 */
1271 		.bank_num = 1,
1272 		.pin = 1,
1273 		.func = 2,
1274 		.route_offset = 0x50,
1275 		.route_val = BIT(16) | BIT(16 + 1),
1276 	}, {
1277 		/* uart2dbg_rxm1 */
1278 		.bank_num = 2,
1279 		.pin = 1,
1280 		.func = 1,
1281 		.route_offset = 0x50,
1282 		.route_val = BIT(16) | BIT(16 + 1) | BIT(0),
1283 	}, {
1284 		/* gmac-m1_rxd0 */
1285 		.bank_num = 1,
1286 		.pin = 11,
1287 		.func = 2,
1288 		.route_offset = 0x50,
1289 		.route_val = BIT(16 + 2) | BIT(2),
1290 	}, {
1291 		/* gmac-m1-optimized_rxd3 */
1292 		.bank_num = 1,
1293 		.pin = 14,
1294 		.func = 2,
1295 		.route_offset = 0x50,
1296 		.route_val = BIT(16 + 10) | BIT(10),
1297 	}, {
1298 		/* pdm_sdi0m0 */
1299 		.bank_num = 2,
1300 		.pin = 19,
1301 		.func = 2,
1302 		.route_offset = 0x50,
1303 		.route_val = BIT(16 + 3),
1304 	}, {
1305 		/* pdm_sdi0m1 */
1306 		.bank_num = 1,
1307 		.pin = 23,
1308 		.func = 3,
1309 		.route_offset = 0x50,
1310 		.route_val =  BIT(16 + 3) | BIT(3),
1311 	}, {
1312 		/* spi_rxdm2 */
1313 		.bank_num = 3,
1314 		.pin = 2,
1315 		.func = 4,
1316 		.route_offset = 0x50,
1317 		.route_val =  BIT(16 + 4) | BIT(16 + 5) | BIT(5),
1318 	}, {
1319 		/* i2s2_sdim0 */
1320 		.bank_num = 1,
1321 		.pin = 24,
1322 		.func = 1,
1323 		.route_offset = 0x50,
1324 		.route_val = BIT(16 + 6),
1325 	}, {
1326 		/* i2s2_sdim1 */
1327 		.bank_num = 3,
1328 		.pin = 2,
1329 		.func = 6,
1330 		.route_offset = 0x50,
1331 		.route_val =  BIT(16 + 6) | BIT(6),
1332 	}, {
1333 		/* card_iom1 */
1334 		.bank_num = 2,
1335 		.pin = 22,
1336 		.func = 3,
1337 		.route_offset = 0x50,
1338 		.route_val =  BIT(16 + 7) | BIT(7),
1339 	}, {
1340 		/* tsp_d5m1 */
1341 		.bank_num = 2,
1342 		.pin = 16,
1343 		.func = 3,
1344 		.route_offset = 0x50,
1345 		.route_val =  BIT(16 + 8) | BIT(8),
1346 	}, {
1347 		/* cif_data5m1 */
1348 		.bank_num = 2,
1349 		.pin = 16,
1350 		.func = 4,
1351 		.route_offset = 0x50,
1352 		.route_val =  BIT(16 + 9) | BIT(9),
1353 	},
1354 };
1355 
1356 static struct rockchip_mux_route_data rk3399_mux_route_data[] = {
1357 	{
1358 		/* uart2dbga_rx */
1359 		.bank_num = 4,
1360 		.pin = 8,
1361 		.func = 2,
1362 		.route_offset = 0xe21c,
1363 		.route_val = BIT(16 + 10) | BIT(16 + 11),
1364 	}, {
1365 		/* uart2dbgb_rx */
1366 		.bank_num = 4,
1367 		.pin = 16,
1368 		.func = 2,
1369 		.route_offset = 0xe21c,
1370 		.route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10),
1371 	}, {
1372 		/* uart2dbgc_rx */
1373 		.bank_num = 4,
1374 		.pin = 19,
1375 		.func = 1,
1376 		.route_offset = 0xe21c,
1377 		.route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11),
1378 	}, {
1379 		/* pcie_clkreqn */
1380 		.bank_num = 2,
1381 		.pin = 26,
1382 		.func = 2,
1383 		.route_offset = 0xe21c,
1384 		.route_val = BIT(16 + 14),
1385 	}, {
1386 		/* pcie_clkreqnb */
1387 		.bank_num = 4,
1388 		.pin = 24,
1389 		.func = 1,
1390 		.route_offset = 0xe21c,
1391 		.route_val = BIT(16 + 14) | BIT(14),
1392 	},
1393 };
1394 
1395 static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin,
1396 				   int mux, u32 *loc, u32 *reg, u32 *value)
1397 {
1398 	struct rockchip_pinctrl *info = bank->drvdata;
1399 	struct rockchip_pin_ctrl *ctrl = info->ctrl;
1400 	struct rockchip_mux_route_data *data;
1401 	int i;
1402 
1403 	for (i = 0; i < ctrl->niomux_routes; i++) {
1404 		data = &ctrl->iomux_routes[i];
1405 		if ((data->bank_num == bank->bank_num) &&
1406 		    (data->pin == pin) && (data->func == mux))
1407 			break;
1408 	}
1409 
1410 	if (i >= ctrl->niomux_routes)
1411 		return false;
1412 
1413 	*loc = data->route_location;
1414 	*reg = data->route_offset;
1415 	*value = data->route_val;
1416 
1417 	return true;
1418 }
1419 
1420 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
1421 {
1422 	struct rockchip_pinctrl *info = bank->drvdata;
1423 	int iomux_num = (pin / 8);
1424 	struct regmap *regmap;
1425 	unsigned int val;
1426 	int reg, ret, mask, mux_type;
1427 	u8 bit;
1428 
1429 	if (iomux_num > 3)
1430 		return -EINVAL;
1431 
1432 	if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
1433 		dev_err(info->dev, "pin %d is unrouted\n", pin);
1434 		return -EINVAL;
1435 	}
1436 
1437 	if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
1438 		return RK_FUNC_GPIO;
1439 
1440 	regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
1441 				? info->regmap_pmu : info->regmap_base;
1442 
1443 	/* get basic quadrupel of mux registers and the correct reg inside */
1444 	mux_type = bank->iomux[iomux_num].type;
1445 	reg = bank->iomux[iomux_num].offset;
1446 	if (mux_type & IOMUX_WIDTH_4BIT) {
1447 		if ((pin % 8) >= 4)
1448 			reg += 0x4;
1449 		bit = (pin % 4) * 4;
1450 		mask = 0xf;
1451 	} else if (mux_type & IOMUX_WIDTH_3BIT) {
1452 		if ((pin % 8) >= 5)
1453 			reg += 0x4;
1454 		bit = (pin % 8 % 5) * 3;
1455 		mask = 0x7;
1456 	} else {
1457 		bit = (pin % 8) * 2;
1458 		mask = 0x3;
1459 	}
1460 
1461 	if (bank->recalced_mask & BIT(pin))
1462 		rockchip_get_recalced_mux(bank, pin, &reg, &bit, &mask);
1463 
1464 	ret = regmap_read(regmap, reg, &val);
1465 	if (ret)
1466 		return ret;
1467 
1468 	return ((val >> bit) & mask);
1469 }
1470 
1471 static int rockchip_verify_mux(struct rockchip_pin_bank *bank,
1472 			       int pin, int mux)
1473 {
1474 	struct rockchip_pinctrl *info = bank->drvdata;
1475 	int iomux_num = (pin / 8);
1476 
1477 	if (iomux_num > 3)
1478 		return -EINVAL;
1479 
1480 	if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
1481 		dev_err(info->dev, "pin %d is unrouted\n", pin);
1482 		return -EINVAL;
1483 	}
1484 
1485 	if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) {
1486 		if (mux != RK_FUNC_GPIO) {
1487 			dev_err(info->dev,
1488 				"pin %d only supports a gpio mux\n", pin);
1489 			return -ENOTSUPP;
1490 		}
1491 	}
1492 
1493 	return 0;
1494 }
1495 
1496 /*
1497  * Set a new mux function for a pin.
1498  *
1499  * The register is divided into the upper and lower 16 bit. When changing
1500  * a value, the previous register value is not read and changed. Instead
1501  * it seems the changed bits are marked in the upper 16 bit, while the
1502  * changed value gets set in the same offset in the lower 16 bit.
1503  * All pin settings seem to be 2 bit wide in both the upper and lower
1504  * parts.
1505  * @bank: pin bank to change
1506  * @pin: pin to change
1507  * @mux: new mux function to set
1508  */
1509 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
1510 {
1511 	struct rockchip_pinctrl *info = bank->drvdata;
1512 	int iomux_num = (pin / 8);
1513 	struct regmap *regmap;
1514 	int reg, ret, mask, mux_type;
1515 	u8 bit;
1516 	u32 data, rmask, route_location, route_reg, route_val;
1517 
1518 	ret = rockchip_verify_mux(bank, pin, mux);
1519 	if (ret < 0)
1520 		return ret;
1521 
1522 	if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
1523 		return 0;
1524 
1525 	dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n",
1526 						bank->bank_num, pin, mux);
1527 
1528 	regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
1529 				? info->regmap_pmu : info->regmap_base;
1530 
1531 	/* get basic quadrupel of mux registers and the correct reg inside */
1532 	mux_type = bank->iomux[iomux_num].type;
1533 	reg = bank->iomux[iomux_num].offset;
1534 	if (mux_type & IOMUX_WIDTH_4BIT) {
1535 		if ((pin % 8) >= 4)
1536 			reg += 0x4;
1537 		bit = (pin % 4) * 4;
1538 		mask = 0xf;
1539 	} else if (mux_type & IOMUX_WIDTH_3BIT) {
1540 		if ((pin % 8) >= 5)
1541 			reg += 0x4;
1542 		bit = (pin % 8 % 5) * 3;
1543 		mask = 0x7;
1544 	} else {
1545 		bit = (pin % 8) * 2;
1546 		mask = 0x3;
1547 	}
1548 
1549 	if (bank->recalced_mask & BIT(pin))
1550 		rockchip_get_recalced_mux(bank, pin, &reg, &bit, &mask);
1551 
1552 	if (bank->route_mask & BIT(pin)) {
1553 		if (rockchip_get_mux_route(bank, pin, mux, &route_location,
1554 					   &route_reg, &route_val)) {
1555 			struct regmap *route_regmap = regmap;
1556 
1557 			/* handle special locations */
1558 			switch (route_location) {
1559 			case ROCKCHIP_ROUTE_PMU:
1560 				route_regmap = info->regmap_pmu;
1561 				break;
1562 			case ROCKCHIP_ROUTE_GRF:
1563 				route_regmap = info->regmap_base;
1564 				break;
1565 			}
1566 
1567 			ret = regmap_write(route_regmap, route_reg, route_val);
1568 			if (ret)
1569 				return ret;
1570 		}
1571 	}
1572 
1573 	data = (mask << (bit + 16));
1574 	rmask = data | (data >> 16);
1575 	data |= (mux & mask) << bit;
1576 	ret = regmap_update_bits(regmap, reg, rmask, data);
1577 
1578 	return ret;
1579 }
1580 
1581 #define PX30_PULL_PMU_OFFSET		0x10
1582 #define PX30_PULL_GRF_OFFSET		0x60
1583 #define PX30_PULL_BITS_PER_PIN		2
1584 #define PX30_PULL_PINS_PER_REG		8
1585 #define PX30_PULL_BANK_STRIDE		16
1586 
1587 static void px30_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1588 				       int pin_num, struct regmap **regmap,
1589 				       int *reg, u8 *bit)
1590 {
1591 	struct rockchip_pinctrl *info = bank->drvdata;
1592 
1593 	/* The first 32 pins of the first bank are located in PMU */
1594 	if (bank->bank_num == 0) {
1595 		*regmap = info->regmap_pmu;
1596 		*reg = PX30_PULL_PMU_OFFSET;
1597 	} else {
1598 		*regmap = info->regmap_base;
1599 		*reg = PX30_PULL_GRF_OFFSET;
1600 
1601 		/* correct the offset, as we're starting with the 2nd bank */
1602 		*reg -= 0x10;
1603 		*reg += bank->bank_num * PX30_PULL_BANK_STRIDE;
1604 	}
1605 
1606 	*reg += ((pin_num / PX30_PULL_PINS_PER_REG) * 4);
1607 	*bit = (pin_num % PX30_PULL_PINS_PER_REG);
1608 	*bit *= PX30_PULL_BITS_PER_PIN;
1609 }
1610 
1611 #define PX30_DRV_PMU_OFFSET		0x20
1612 #define PX30_DRV_GRF_OFFSET		0xf0
1613 #define PX30_DRV_BITS_PER_PIN		2
1614 #define PX30_DRV_PINS_PER_REG		8
1615 #define PX30_DRV_BANK_STRIDE		16
1616 
1617 static void px30_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1618 				      int pin_num, struct regmap **regmap,
1619 				      int *reg, u8 *bit)
1620 {
1621 	struct rockchip_pinctrl *info = bank->drvdata;
1622 
1623 	/* The first 32 pins of the first bank are located in PMU */
1624 	if (bank->bank_num == 0) {
1625 		*regmap = info->regmap_pmu;
1626 		*reg = PX30_DRV_PMU_OFFSET;
1627 	} else {
1628 		*regmap = info->regmap_base;
1629 		*reg = PX30_DRV_GRF_OFFSET;
1630 
1631 		/* correct the offset, as we're starting with the 2nd bank */
1632 		*reg -= 0x10;
1633 		*reg += bank->bank_num * PX30_DRV_BANK_STRIDE;
1634 	}
1635 
1636 	*reg += ((pin_num / PX30_DRV_PINS_PER_REG) * 4);
1637 	*bit = (pin_num % PX30_DRV_PINS_PER_REG);
1638 	*bit *= PX30_DRV_BITS_PER_PIN;
1639 }
1640 
1641 #define PX30_SCHMITT_PMU_OFFSET			0x38
1642 #define PX30_SCHMITT_GRF_OFFSET			0xc0
1643 #define PX30_SCHMITT_PINS_PER_PMU_REG		16
1644 #define PX30_SCHMITT_BANK_STRIDE		16
1645 #define PX30_SCHMITT_PINS_PER_GRF_REG		8
1646 
1647 static int px30_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1648 					 int pin_num,
1649 					 struct regmap **regmap,
1650 					 int *reg, u8 *bit)
1651 {
1652 	struct rockchip_pinctrl *info = bank->drvdata;
1653 	int pins_per_reg;
1654 
1655 	if (bank->bank_num == 0) {
1656 		*regmap = info->regmap_pmu;
1657 		*reg = PX30_SCHMITT_PMU_OFFSET;
1658 		pins_per_reg = PX30_SCHMITT_PINS_PER_PMU_REG;
1659 	} else {
1660 		*regmap = info->regmap_base;
1661 		*reg = PX30_SCHMITT_GRF_OFFSET;
1662 		pins_per_reg = PX30_SCHMITT_PINS_PER_GRF_REG;
1663 		*reg += (bank->bank_num  - 1) * PX30_SCHMITT_BANK_STRIDE;
1664 	}
1665 
1666 	*reg += ((pin_num / pins_per_reg) * 4);
1667 	*bit = pin_num % pins_per_reg;
1668 
1669 	return 0;
1670 }
1671 
1672 #define RV1108_PULL_PMU_OFFSET		0x10
1673 #define RV1108_PULL_OFFSET		0x110
1674 #define RV1108_PULL_PINS_PER_REG	8
1675 #define RV1108_PULL_BITS_PER_PIN	2
1676 #define RV1108_PULL_BANK_STRIDE		16
1677 
1678 static void rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1679 					 int pin_num, struct regmap **regmap,
1680 					 int *reg, u8 *bit)
1681 {
1682 	struct rockchip_pinctrl *info = bank->drvdata;
1683 
1684 	/* The first 24 pins of the first bank are located in PMU */
1685 	if (bank->bank_num == 0) {
1686 		*regmap = info->regmap_pmu;
1687 		*reg = RV1108_PULL_PMU_OFFSET;
1688 	} else {
1689 		*reg = RV1108_PULL_OFFSET;
1690 		*regmap = info->regmap_base;
1691 		/* correct the offset, as we're starting with the 2nd bank */
1692 		*reg -= 0x10;
1693 		*reg += bank->bank_num * RV1108_PULL_BANK_STRIDE;
1694 	}
1695 
1696 	*reg += ((pin_num / RV1108_PULL_PINS_PER_REG) * 4);
1697 	*bit = (pin_num % RV1108_PULL_PINS_PER_REG);
1698 	*bit *= RV1108_PULL_BITS_PER_PIN;
1699 }
1700 
1701 #define RV1108_DRV_PMU_OFFSET		0x20
1702 #define RV1108_DRV_GRF_OFFSET		0x210
1703 #define RV1108_DRV_BITS_PER_PIN		2
1704 #define RV1108_DRV_PINS_PER_REG		8
1705 #define RV1108_DRV_BANK_STRIDE		16
1706 
1707 static void rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1708 					int pin_num, struct regmap **regmap,
1709 					int *reg, u8 *bit)
1710 {
1711 	struct rockchip_pinctrl *info = bank->drvdata;
1712 
1713 	/* The first 24 pins of the first bank are located in PMU */
1714 	if (bank->bank_num == 0) {
1715 		*regmap = info->regmap_pmu;
1716 		*reg = RV1108_DRV_PMU_OFFSET;
1717 	} else {
1718 		*regmap = info->regmap_base;
1719 		*reg = RV1108_DRV_GRF_OFFSET;
1720 
1721 		/* correct the offset, as we're starting with the 2nd bank */
1722 		*reg -= 0x10;
1723 		*reg += bank->bank_num * RV1108_DRV_BANK_STRIDE;
1724 	}
1725 
1726 	*reg += ((pin_num / RV1108_DRV_PINS_PER_REG) * 4);
1727 	*bit = pin_num % RV1108_DRV_PINS_PER_REG;
1728 	*bit *= RV1108_DRV_BITS_PER_PIN;
1729 }
1730 
1731 #define RV1108_SCHMITT_PMU_OFFSET		0x30
1732 #define RV1108_SCHMITT_GRF_OFFSET		0x388
1733 #define RV1108_SCHMITT_BANK_STRIDE		8
1734 #define RV1108_SCHMITT_PINS_PER_GRF_REG		16
1735 #define RV1108_SCHMITT_PINS_PER_PMU_REG		8
1736 
1737 static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1738 					   int pin_num,
1739 					   struct regmap **regmap,
1740 					   int *reg, u8 *bit)
1741 {
1742 	struct rockchip_pinctrl *info = bank->drvdata;
1743 	int pins_per_reg;
1744 
1745 	if (bank->bank_num == 0) {
1746 		*regmap = info->regmap_pmu;
1747 		*reg = RV1108_SCHMITT_PMU_OFFSET;
1748 		pins_per_reg = RV1108_SCHMITT_PINS_PER_PMU_REG;
1749 	} else {
1750 		*regmap = info->regmap_base;
1751 		*reg = RV1108_SCHMITT_GRF_OFFSET;
1752 		pins_per_reg = RV1108_SCHMITT_PINS_PER_GRF_REG;
1753 		*reg += (bank->bank_num  - 1) * RV1108_SCHMITT_BANK_STRIDE;
1754 	}
1755 	*reg += ((pin_num / pins_per_reg) * 4);
1756 	*bit = pin_num % pins_per_reg;
1757 
1758 	return 0;
1759 }
1760 
1761 #define RK3308_SCHMITT_PINS_PER_REG		8
1762 #define RK3308_SCHMITT_BANK_STRIDE		16
1763 #define RK3308_SCHMITT_GRF_OFFSET		0x1a0
1764 
1765 static int rk3308_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1766 				    int pin_num, struct regmap **regmap,
1767 				    int *reg, u8 *bit)
1768 {
1769 	struct rockchip_pinctrl *info = bank->drvdata;
1770 
1771 	*regmap = info->regmap_base;
1772 	*reg = RK3308_SCHMITT_GRF_OFFSET;
1773 
1774 	*reg += bank->bank_num * RK3308_SCHMITT_BANK_STRIDE;
1775 	*reg += ((pin_num / RK3308_SCHMITT_PINS_PER_REG) * 4);
1776 	*bit = pin_num % RK3308_SCHMITT_PINS_PER_REG;
1777 
1778 	return 0;
1779 }
1780 
1781 #define RK2928_PULL_OFFSET		0x118
1782 #define RK2928_PULL_PINS_PER_REG	16
1783 #define RK2928_PULL_BANK_STRIDE		8
1784 
1785 static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1786 				    int pin_num, struct regmap **regmap,
1787 				    int *reg, u8 *bit)
1788 {
1789 	struct rockchip_pinctrl *info = bank->drvdata;
1790 
1791 	*regmap = info->regmap_base;
1792 	*reg = RK2928_PULL_OFFSET;
1793 	*reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
1794 	*reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4;
1795 
1796 	*bit = pin_num % RK2928_PULL_PINS_PER_REG;
1797 };
1798 
1799 #define RK3128_PULL_OFFSET	0x118
1800 
1801 static void rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1802 					 int pin_num, struct regmap **regmap,
1803 					 int *reg, u8 *bit)
1804 {
1805 	struct rockchip_pinctrl *info = bank->drvdata;
1806 
1807 	*regmap = info->regmap_base;
1808 	*reg = RK3128_PULL_OFFSET;
1809 	*reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
1810 	*reg += ((pin_num / RK2928_PULL_PINS_PER_REG) * 4);
1811 
1812 	*bit = pin_num % RK2928_PULL_PINS_PER_REG;
1813 }
1814 
1815 #define RK3188_PULL_OFFSET		0x164
1816 #define RK3188_PULL_BITS_PER_PIN	2
1817 #define RK3188_PULL_PINS_PER_REG	8
1818 #define RK3188_PULL_BANK_STRIDE		16
1819 #define RK3188_PULL_PMU_OFFSET		0x64
1820 
1821 static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1822 				    int pin_num, struct regmap **regmap,
1823 				    int *reg, u8 *bit)
1824 {
1825 	struct rockchip_pinctrl *info = bank->drvdata;
1826 
1827 	/* The first 12 pins of the first bank are located elsewhere */
1828 	if (bank->bank_num == 0 && pin_num < 12) {
1829 		*regmap = info->regmap_pmu ? info->regmap_pmu
1830 					   : bank->regmap_pull;
1831 		*reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0;
1832 		*reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1833 		*bit = pin_num % RK3188_PULL_PINS_PER_REG;
1834 		*bit *= RK3188_PULL_BITS_PER_PIN;
1835 	} else {
1836 		*regmap = info->regmap_pull ? info->regmap_pull
1837 					    : info->regmap_base;
1838 		*reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET;
1839 
1840 		/* correct the offset, as it is the 2nd pull register */
1841 		*reg -= 4;
1842 		*reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1843 		*reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1844 
1845 		/*
1846 		 * The bits in these registers have an inverse ordering
1847 		 * with the lowest pin being in bits 15:14 and the highest
1848 		 * pin in bits 1:0
1849 		 */
1850 		*bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG);
1851 		*bit *= RK3188_PULL_BITS_PER_PIN;
1852 	}
1853 }
1854 
1855 #define RK3288_PULL_OFFSET		0x140
1856 static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1857 				    int pin_num, struct regmap **regmap,
1858 				    int *reg, u8 *bit)
1859 {
1860 	struct rockchip_pinctrl *info = bank->drvdata;
1861 
1862 	/* The first 24 pins of the first bank are located in PMU */
1863 	if (bank->bank_num == 0) {
1864 		*regmap = info->regmap_pmu;
1865 		*reg = RK3188_PULL_PMU_OFFSET;
1866 
1867 		*reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1868 		*bit = pin_num % RK3188_PULL_PINS_PER_REG;
1869 		*bit *= RK3188_PULL_BITS_PER_PIN;
1870 	} else {
1871 		*regmap = info->regmap_base;
1872 		*reg = RK3288_PULL_OFFSET;
1873 
1874 		/* correct the offset, as we're starting with the 2nd bank */
1875 		*reg -= 0x10;
1876 		*reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1877 		*reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1878 
1879 		*bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1880 		*bit *= RK3188_PULL_BITS_PER_PIN;
1881 	}
1882 }
1883 
1884 #define RK3288_DRV_PMU_OFFSET		0x70
1885 #define RK3288_DRV_GRF_OFFSET		0x1c0
1886 #define RK3288_DRV_BITS_PER_PIN		2
1887 #define RK3288_DRV_PINS_PER_REG		8
1888 #define RK3288_DRV_BANK_STRIDE		16
1889 
1890 static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1891 				    int pin_num, struct regmap **regmap,
1892 				    int *reg, u8 *bit)
1893 {
1894 	struct rockchip_pinctrl *info = bank->drvdata;
1895 
1896 	/* The first 24 pins of the first bank are located in PMU */
1897 	if (bank->bank_num == 0) {
1898 		*regmap = info->regmap_pmu;
1899 		*reg = RK3288_DRV_PMU_OFFSET;
1900 
1901 		*reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1902 		*bit = pin_num % RK3288_DRV_PINS_PER_REG;
1903 		*bit *= RK3288_DRV_BITS_PER_PIN;
1904 	} else {
1905 		*regmap = info->regmap_base;
1906 		*reg = RK3288_DRV_GRF_OFFSET;
1907 
1908 		/* correct the offset, as we're starting with the 2nd bank */
1909 		*reg -= 0x10;
1910 		*reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1911 		*reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1912 
1913 		*bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1914 		*bit *= RK3288_DRV_BITS_PER_PIN;
1915 	}
1916 }
1917 
1918 #define RK3228_PULL_OFFSET		0x100
1919 
1920 static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1921 				    int pin_num, struct regmap **regmap,
1922 				    int *reg, u8 *bit)
1923 {
1924 	struct rockchip_pinctrl *info = bank->drvdata;
1925 
1926 	*regmap = info->regmap_base;
1927 	*reg = RK3228_PULL_OFFSET;
1928 	*reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1929 	*reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1930 
1931 	*bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1932 	*bit *= RK3188_PULL_BITS_PER_PIN;
1933 }
1934 
1935 #define RK3228_DRV_GRF_OFFSET		0x200
1936 
1937 static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1938 				    int pin_num, struct regmap **regmap,
1939 				    int *reg, u8 *bit)
1940 {
1941 	struct rockchip_pinctrl *info = bank->drvdata;
1942 
1943 	*regmap = info->regmap_base;
1944 	*reg = RK3228_DRV_GRF_OFFSET;
1945 	*reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1946 	*reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1947 
1948 	*bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1949 	*bit *= RK3288_DRV_BITS_PER_PIN;
1950 }
1951 
1952 #define RK3308_PULL_OFFSET		0xa0
1953 
1954 static void rk3308_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1955 				    int pin_num, struct regmap **regmap,
1956 				    int *reg, u8 *bit)
1957 {
1958 	struct rockchip_pinctrl *info = bank->drvdata;
1959 
1960 	*regmap = info->regmap_base;
1961 	*reg = RK3308_PULL_OFFSET;
1962 	*reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1963 	*reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1964 
1965 	*bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1966 	*bit *= RK3188_PULL_BITS_PER_PIN;
1967 }
1968 
1969 #define RK3308_DRV_GRF_OFFSET		0x100
1970 
1971 static void rk3308_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1972 				    int pin_num, struct regmap **regmap,
1973 				    int *reg, u8 *bit)
1974 {
1975 	struct rockchip_pinctrl *info = bank->drvdata;
1976 
1977 	*regmap = info->regmap_base;
1978 	*reg = RK3308_DRV_GRF_OFFSET;
1979 	*reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1980 	*reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1981 
1982 	*bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1983 	*bit *= RK3288_DRV_BITS_PER_PIN;
1984 }
1985 
1986 #define RK3368_PULL_GRF_OFFSET		0x100
1987 #define RK3368_PULL_PMU_OFFSET		0x10
1988 
1989 static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1990 				    int pin_num, struct regmap **regmap,
1991 				    int *reg, u8 *bit)
1992 {
1993 	struct rockchip_pinctrl *info = bank->drvdata;
1994 
1995 	/* The first 32 pins of the first bank are located in PMU */
1996 	if (bank->bank_num == 0) {
1997 		*regmap = info->regmap_pmu;
1998 		*reg = RK3368_PULL_PMU_OFFSET;
1999 
2000 		*reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
2001 		*bit = pin_num % RK3188_PULL_PINS_PER_REG;
2002 		*bit *= RK3188_PULL_BITS_PER_PIN;
2003 	} else {
2004 		*regmap = info->regmap_base;
2005 		*reg = RK3368_PULL_GRF_OFFSET;
2006 
2007 		/* correct the offset, as we're starting with the 2nd bank */
2008 		*reg -= 0x10;
2009 		*reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
2010 		*reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
2011 
2012 		*bit = (pin_num % RK3188_PULL_PINS_PER_REG);
2013 		*bit *= RK3188_PULL_BITS_PER_PIN;
2014 	}
2015 }
2016 
2017 #define RK3368_DRV_PMU_OFFSET		0x20
2018 #define RK3368_DRV_GRF_OFFSET		0x200
2019 
2020 static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
2021 				    int pin_num, struct regmap **regmap,
2022 				    int *reg, u8 *bit)
2023 {
2024 	struct rockchip_pinctrl *info = bank->drvdata;
2025 
2026 	/* The first 32 pins of the first bank are located in PMU */
2027 	if (bank->bank_num == 0) {
2028 		*regmap = info->regmap_pmu;
2029 		*reg = RK3368_DRV_PMU_OFFSET;
2030 
2031 		*reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
2032 		*bit = pin_num % RK3288_DRV_PINS_PER_REG;
2033 		*bit *= RK3288_DRV_BITS_PER_PIN;
2034 	} else {
2035 		*regmap = info->regmap_base;
2036 		*reg = RK3368_DRV_GRF_OFFSET;
2037 
2038 		/* correct the offset, as we're starting with the 2nd bank */
2039 		*reg -= 0x10;
2040 		*reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
2041 		*reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
2042 
2043 		*bit = (pin_num % RK3288_DRV_PINS_PER_REG);
2044 		*bit *= RK3288_DRV_BITS_PER_PIN;
2045 	}
2046 }
2047 
2048 #define RK3399_PULL_GRF_OFFSET		0xe040
2049 #define RK3399_PULL_PMU_OFFSET		0x40
2050 #define RK3399_DRV_3BITS_PER_PIN	3
2051 
2052 static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
2053 					 int pin_num, struct regmap **regmap,
2054 					 int *reg, u8 *bit)
2055 {
2056 	struct rockchip_pinctrl *info = bank->drvdata;
2057 
2058 	/* The bank0:16 and bank1:32 pins are located in PMU */
2059 	if ((bank->bank_num == 0) || (bank->bank_num == 1)) {
2060 		*regmap = info->regmap_pmu;
2061 		*reg = RK3399_PULL_PMU_OFFSET;
2062 
2063 		*reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
2064 
2065 		*reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
2066 		*bit = pin_num % RK3188_PULL_PINS_PER_REG;
2067 		*bit *= RK3188_PULL_BITS_PER_PIN;
2068 	} else {
2069 		*regmap = info->regmap_base;
2070 		*reg = RK3399_PULL_GRF_OFFSET;
2071 
2072 		/* correct the offset, as we're starting with the 3rd bank */
2073 		*reg -= 0x20;
2074 		*reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
2075 		*reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
2076 
2077 		*bit = (pin_num % RK3188_PULL_PINS_PER_REG);
2078 		*bit *= RK3188_PULL_BITS_PER_PIN;
2079 	}
2080 }
2081 
2082 static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
2083 					int pin_num, struct regmap **regmap,
2084 					int *reg, u8 *bit)
2085 {
2086 	struct rockchip_pinctrl *info = bank->drvdata;
2087 	int drv_num = (pin_num / 8);
2088 
2089 	/*  The bank0:16 and bank1:32 pins are located in PMU */
2090 	if ((bank->bank_num == 0) || (bank->bank_num == 1))
2091 		*regmap = info->regmap_pmu;
2092 	else
2093 		*regmap = info->regmap_base;
2094 
2095 	*reg = bank->drv[drv_num].offset;
2096 	if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
2097 	    (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY))
2098 		*bit = (pin_num % 8) * 3;
2099 	else
2100 		*bit = (pin_num % 8) * 2;
2101 }
2102 
2103 static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = {
2104 	{ 2, 4, 8, 12, -1, -1, -1, -1 },
2105 	{ 3, 6, 9, 12, -1, -1, -1, -1 },
2106 	{ 5, 10, 15, 20, -1, -1, -1, -1 },
2107 	{ 4, 6, 8, 10, 12, 14, 16, 18 },
2108 	{ 4, 7, 10, 13, 16, 19, 22, 26 }
2109 };
2110 
2111 static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank,
2112 				     int pin_num)
2113 {
2114 	struct rockchip_pinctrl *info = bank->drvdata;
2115 	struct rockchip_pin_ctrl *ctrl = info->ctrl;
2116 	struct regmap *regmap;
2117 	int reg, ret;
2118 	u32 data, temp, rmask_bits;
2119 	u8 bit;
2120 	int drv_type = bank->drv[pin_num / 8].drv_type;
2121 
2122 	ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
2123 
2124 	switch (drv_type) {
2125 	case DRV_TYPE_IO_1V8_3V0_AUTO:
2126 	case DRV_TYPE_IO_3V3_ONLY:
2127 		rmask_bits = RK3399_DRV_3BITS_PER_PIN;
2128 		switch (bit) {
2129 		case 0 ... 12:
2130 			/* regular case, nothing to do */
2131 			break;
2132 		case 15:
2133 			/*
2134 			 * drive-strength offset is special, as it is
2135 			 * spread over 2 registers
2136 			 */
2137 			ret = regmap_read(regmap, reg, &data);
2138 			if (ret)
2139 				return ret;
2140 
2141 			ret = regmap_read(regmap, reg + 0x4, &temp);
2142 			if (ret)
2143 				return ret;
2144 
2145 			/*
2146 			 * the bit data[15] contains bit 0 of the value
2147 			 * while temp[1:0] contains bits 2 and 1
2148 			 */
2149 			data >>= 15;
2150 			temp &= 0x3;
2151 			temp <<= 1;
2152 			data |= temp;
2153 
2154 			return rockchip_perpin_drv_list[drv_type][data];
2155 		case 18 ... 21:
2156 			/* setting fully enclosed in the second register */
2157 			reg += 4;
2158 			bit -= 16;
2159 			break;
2160 		default:
2161 			dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n",
2162 				bit, drv_type);
2163 			return -EINVAL;
2164 		}
2165 
2166 		break;
2167 	case DRV_TYPE_IO_DEFAULT:
2168 	case DRV_TYPE_IO_1V8_OR_3V0:
2169 	case DRV_TYPE_IO_1V8_ONLY:
2170 		rmask_bits = RK3288_DRV_BITS_PER_PIN;
2171 		break;
2172 	default:
2173 		dev_err(info->dev, "unsupported pinctrl drive type: %d\n",
2174 			drv_type);
2175 		return -EINVAL;
2176 	}
2177 
2178 	ret = regmap_read(regmap, reg, &data);
2179 	if (ret)
2180 		return ret;
2181 
2182 	data >>= bit;
2183 	data &= (1 << rmask_bits) - 1;
2184 
2185 	return rockchip_perpin_drv_list[drv_type][data];
2186 }
2187 
2188 static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
2189 				     int pin_num, int strength)
2190 {
2191 	struct rockchip_pinctrl *info = bank->drvdata;
2192 	struct rockchip_pin_ctrl *ctrl = info->ctrl;
2193 	struct regmap *regmap;
2194 	int reg, ret, i;
2195 	u32 data, rmask, rmask_bits, temp;
2196 	u8 bit;
2197 	int drv_type = bank->drv[pin_num / 8].drv_type;
2198 
2199 	dev_dbg(info->dev, "setting drive of GPIO%d-%d to %d\n",
2200 		bank->bank_num, pin_num, strength);
2201 
2202 	ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
2203 
2204 	ret = -EINVAL;
2205 	for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) {
2206 		if (rockchip_perpin_drv_list[drv_type][i] == strength) {
2207 			ret = i;
2208 			break;
2209 		} else if (rockchip_perpin_drv_list[drv_type][i] < 0) {
2210 			ret = rockchip_perpin_drv_list[drv_type][i];
2211 			break;
2212 		}
2213 	}
2214 
2215 	if (ret < 0) {
2216 		dev_err(info->dev, "unsupported driver strength %d\n",
2217 			strength);
2218 		return ret;
2219 	}
2220 
2221 	switch (drv_type) {
2222 	case DRV_TYPE_IO_1V8_3V0_AUTO:
2223 	case DRV_TYPE_IO_3V3_ONLY:
2224 		rmask_bits = RK3399_DRV_3BITS_PER_PIN;
2225 		switch (bit) {
2226 		case 0 ... 12:
2227 			/* regular case, nothing to do */
2228 			break;
2229 		case 15:
2230 			/*
2231 			 * drive-strength offset is special, as it is spread
2232 			 * over 2 registers, the bit data[15] contains bit 0
2233 			 * of the value while temp[1:0] contains bits 2 and 1
2234 			 */
2235 			data = (ret & 0x1) << 15;
2236 			temp = (ret >> 0x1) & 0x3;
2237 
2238 			rmask = BIT(15) | BIT(31);
2239 			data |= BIT(31);
2240 			ret = regmap_update_bits(regmap, reg, rmask, data);
2241 			if (ret)
2242 				return ret;
2243 
2244 			rmask = 0x3 | (0x3 << 16);
2245 			temp |= (0x3 << 16);
2246 			reg += 0x4;
2247 			ret = regmap_update_bits(regmap, reg, rmask, temp);
2248 
2249 			return ret;
2250 		case 18 ... 21:
2251 			/* setting fully enclosed in the second register */
2252 			reg += 4;
2253 			bit -= 16;
2254 			break;
2255 		default:
2256 			dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n",
2257 				bit, drv_type);
2258 			return -EINVAL;
2259 		}
2260 		break;
2261 	case DRV_TYPE_IO_DEFAULT:
2262 	case DRV_TYPE_IO_1V8_OR_3V0:
2263 	case DRV_TYPE_IO_1V8_ONLY:
2264 		rmask_bits = RK3288_DRV_BITS_PER_PIN;
2265 		break;
2266 	default:
2267 		dev_err(info->dev, "unsupported pinctrl drive type: %d\n",
2268 			drv_type);
2269 		return -EINVAL;
2270 	}
2271 
2272 	/* enable the write to the equivalent lower bits */
2273 	data = ((1 << rmask_bits) - 1) << (bit + 16);
2274 	rmask = data | (data >> 16);
2275 	data |= (ret << bit);
2276 
2277 	ret = regmap_update_bits(regmap, reg, rmask, data);
2278 
2279 	return ret;
2280 }
2281 
2282 static int rockchip_pull_list[PULL_TYPE_MAX][4] = {
2283 	{
2284 		PIN_CONFIG_BIAS_DISABLE,
2285 		PIN_CONFIG_BIAS_PULL_UP,
2286 		PIN_CONFIG_BIAS_PULL_DOWN,
2287 		PIN_CONFIG_BIAS_BUS_HOLD
2288 	},
2289 	{
2290 		PIN_CONFIG_BIAS_DISABLE,
2291 		PIN_CONFIG_BIAS_PULL_DOWN,
2292 		PIN_CONFIG_BIAS_DISABLE,
2293 		PIN_CONFIG_BIAS_PULL_UP
2294 	},
2295 };
2296 
2297 static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
2298 {
2299 	struct rockchip_pinctrl *info = bank->drvdata;
2300 	struct rockchip_pin_ctrl *ctrl = info->ctrl;
2301 	struct regmap *regmap;
2302 	int reg, ret, pull_type;
2303 	u8 bit;
2304 	u32 data;
2305 
2306 	/* rk3066b does support any pulls */
2307 	if (ctrl->type == RK3066B)
2308 		return PIN_CONFIG_BIAS_DISABLE;
2309 
2310 	ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
2311 
2312 	ret = regmap_read(regmap, reg, &data);
2313 	if (ret)
2314 		return ret;
2315 
2316 	switch (ctrl->type) {
2317 	case RK2928:
2318 	case RK3128:
2319 		return !(data & BIT(bit))
2320 				? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
2321 				: PIN_CONFIG_BIAS_DISABLE;
2322 	case PX30:
2323 	case RV1108:
2324 	case RK3188:
2325 	case RK3288:
2326 	case RK3308:
2327 	case RK3368:
2328 	case RK3399:
2329 		pull_type = bank->pull_type[pin_num / 8];
2330 		data >>= bit;
2331 		data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;
2332 
2333 		return rockchip_pull_list[pull_type][data];
2334 	default:
2335 		dev_err(info->dev, "unsupported pinctrl type\n");
2336 		return -EINVAL;
2337 	};
2338 }
2339 
2340 static int rockchip_set_pull(struct rockchip_pin_bank *bank,
2341 					int pin_num, int pull)
2342 {
2343 	struct rockchip_pinctrl *info = bank->drvdata;
2344 	struct rockchip_pin_ctrl *ctrl = info->ctrl;
2345 	struct regmap *regmap;
2346 	int reg, ret, i, pull_type;
2347 	u8 bit;
2348 	u32 data, rmask;
2349 
2350 	dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n",
2351 		 bank->bank_num, pin_num, pull);
2352 
2353 	/* rk3066b does support any pulls */
2354 	if (ctrl->type == RK3066B)
2355 		return pull ? -EINVAL : 0;
2356 
2357 	ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
2358 
2359 	switch (ctrl->type) {
2360 	case RK2928:
2361 	case RK3128:
2362 		data = BIT(bit + 16);
2363 		if (pull == PIN_CONFIG_BIAS_DISABLE)
2364 			data |= BIT(bit);
2365 		ret = regmap_write(regmap, reg, data);
2366 		break;
2367 	case PX30:
2368 	case RV1108:
2369 	case RK3188:
2370 	case RK3288:
2371 	case RK3308:
2372 	case RK3368:
2373 	case RK3399:
2374 		pull_type = bank->pull_type[pin_num / 8];
2375 		ret = -EINVAL;
2376 		for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]);
2377 			i++) {
2378 			if (rockchip_pull_list[pull_type][i] == pull) {
2379 				ret = i;
2380 				break;
2381 			}
2382 		}
2383 
2384 		if (ret < 0) {
2385 			dev_err(info->dev, "unsupported pull setting %d\n",
2386 				pull);
2387 			return ret;
2388 		}
2389 
2390 		/* enable the write to the equivalent lower bits */
2391 		data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16);
2392 		rmask = data | (data >> 16);
2393 		data |= (ret << bit);
2394 
2395 		ret = regmap_update_bits(regmap, reg, rmask, data);
2396 		break;
2397 	default:
2398 		dev_err(info->dev, "unsupported pinctrl type\n");
2399 		return -EINVAL;
2400 	}
2401 
2402 	return ret;
2403 }
2404 
2405 #define RK3328_SCHMITT_BITS_PER_PIN		1
2406 #define RK3328_SCHMITT_PINS_PER_REG		16
2407 #define RK3328_SCHMITT_BANK_STRIDE		8
2408 #define RK3328_SCHMITT_GRF_OFFSET		0x380
2409 
2410 static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
2411 					   int pin_num,
2412 					   struct regmap **regmap,
2413 					   int *reg, u8 *bit)
2414 {
2415 	struct rockchip_pinctrl *info = bank->drvdata;
2416 
2417 	*regmap = info->regmap_base;
2418 	*reg = RK3328_SCHMITT_GRF_OFFSET;
2419 
2420 	*reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE;
2421 	*reg += ((pin_num / RK3328_SCHMITT_PINS_PER_REG) * 4);
2422 	*bit = pin_num % RK3328_SCHMITT_PINS_PER_REG;
2423 
2424 	return 0;
2425 }
2426 
2427 static int rockchip_get_schmitt(struct rockchip_pin_bank *bank, int pin_num)
2428 {
2429 	struct rockchip_pinctrl *info = bank->drvdata;
2430 	struct rockchip_pin_ctrl *ctrl = info->ctrl;
2431 	struct regmap *regmap;
2432 	int reg, ret;
2433 	u8 bit;
2434 	u32 data;
2435 
2436 	ret = ctrl->schmitt_calc_reg(bank, pin_num, &regmap, &reg, &bit);
2437 	if (ret)
2438 		return ret;
2439 
2440 	ret = regmap_read(regmap, reg, &data);
2441 	if (ret)
2442 		return ret;
2443 
2444 	data >>= bit;
2445 	return data & 0x1;
2446 }
2447 
2448 static int rockchip_set_schmitt(struct rockchip_pin_bank *bank,
2449 				int pin_num, int enable)
2450 {
2451 	struct rockchip_pinctrl *info = bank->drvdata;
2452 	struct rockchip_pin_ctrl *ctrl = info->ctrl;
2453 	struct regmap *regmap;
2454 	int reg, ret;
2455 	u8 bit;
2456 	u32 data, rmask;
2457 
2458 	dev_dbg(info->dev, "setting input schmitt of GPIO%d-%d to %d\n",
2459 		bank->bank_num, pin_num, enable);
2460 
2461 	ret = ctrl->schmitt_calc_reg(bank, pin_num, &regmap, &reg, &bit);
2462 	if (ret)
2463 		return ret;
2464 
2465 	/* enable the write to the equivalent lower bits */
2466 	data = BIT(bit + 16) | (enable << bit);
2467 	rmask = BIT(bit + 16) | BIT(bit);
2468 
2469 	return regmap_update_bits(regmap, reg, rmask, data);
2470 }
2471 
2472 /*
2473  * Pinmux_ops handling
2474  */
2475 
2476 static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
2477 {
2478 	struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2479 
2480 	return info->nfunctions;
2481 }
2482 
2483 static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev,
2484 					  unsigned selector)
2485 {
2486 	struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2487 
2488 	return info->functions[selector].name;
2489 }
2490 
2491 static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev,
2492 				unsigned selector, const char * const **groups,
2493 				unsigned * const num_groups)
2494 {
2495 	struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2496 
2497 	*groups = info->functions[selector].groups;
2498 	*num_groups = info->functions[selector].ngroups;
2499 
2500 	return 0;
2501 }
2502 
2503 static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
2504 			    unsigned group)
2505 {
2506 	struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2507 	const unsigned int *pins = info->groups[group].pins;
2508 	const struct rockchip_pin_config *data = info->groups[group].data;
2509 	struct rockchip_pin_bank *bank;
2510 	int cnt, ret = 0;
2511 
2512 	dev_dbg(info->dev, "enable function %s group %s\n",
2513 		info->functions[selector].name, info->groups[group].name);
2514 
2515 	/*
2516 	 * for each pin in the pin group selected, program the corresponding
2517 	 * pin function number in the config register.
2518 	 */
2519 	for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
2520 		bank = pin_to_bank(info, pins[cnt]);
2521 		ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base,
2522 				       data[cnt].func);
2523 		if (ret)
2524 			break;
2525 	}
2526 
2527 	if (ret) {
2528 		/* revert the already done pin settings */
2529 		for (cnt--; cnt >= 0; cnt--)
2530 			rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
2531 
2532 		return ret;
2533 	}
2534 
2535 	return 0;
2536 }
2537 
2538 static int rockchip_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
2539 {
2540 	struct rockchip_pin_bank *bank = gpiochip_get_data(chip);
2541 	u32 data;
2542 	int ret;
2543 
2544 	ret = clk_enable(bank->clk);
2545 	if (ret < 0) {
2546 		dev_err(bank->drvdata->dev,
2547 			"failed to enable clock for bank %s\n", bank->name);
2548 		return ret;
2549 	}
2550 	data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
2551 	clk_disable(bank->clk);
2552 
2553 	if (data & BIT(offset))
2554 		return GPIO_LINE_DIRECTION_OUT;
2555 
2556 	return GPIO_LINE_DIRECTION_IN;
2557 }
2558 
2559 /*
2560  * The calls to gpio_direction_output() and gpio_direction_input()
2561  * leads to this function call (via the pinctrl_gpio_direction_{input|output}()
2562  * function called from the gpiolib interface).
2563  */
2564 static int _rockchip_pmx_gpio_set_direction(struct gpio_chip *chip,
2565 					    int pin, bool input)
2566 {
2567 	struct rockchip_pin_bank *bank;
2568 	int ret;
2569 	unsigned long flags;
2570 	u32 data;
2571 
2572 	bank = gpiochip_get_data(chip);
2573 
2574 	ret = rockchip_set_mux(bank, pin, RK_FUNC_GPIO);
2575 	if (ret < 0)
2576 		return ret;
2577 
2578 	clk_enable(bank->clk);
2579 	raw_spin_lock_irqsave(&bank->slock, flags);
2580 
2581 	data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
2582 	/* set bit to 1 for output, 0 for input */
2583 	if (!input)
2584 		data |= BIT(pin);
2585 	else
2586 		data &= ~BIT(pin);
2587 	writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
2588 
2589 	raw_spin_unlock_irqrestore(&bank->slock, flags);
2590 	clk_disable(bank->clk);
2591 
2592 	return 0;
2593 }
2594 
2595 static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
2596 					      struct pinctrl_gpio_range *range,
2597 					      unsigned offset, bool input)
2598 {
2599 	struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2600 	struct gpio_chip *chip;
2601 	int pin;
2602 
2603 	chip = range->gc;
2604 	pin = offset - chip->base;
2605 	dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n",
2606 		 offset, range->name, pin, input ? "input" : "output");
2607 
2608 	return _rockchip_pmx_gpio_set_direction(chip, offset - chip->base,
2609 						input);
2610 }
2611 
2612 static const struct pinmux_ops rockchip_pmx_ops = {
2613 	.get_functions_count	= rockchip_pmx_get_funcs_count,
2614 	.get_function_name	= rockchip_pmx_get_func_name,
2615 	.get_function_groups	= rockchip_pmx_get_groups,
2616 	.set_mux		= rockchip_pmx_set,
2617 	.gpio_set_direction	= rockchip_pmx_gpio_set_direction,
2618 };
2619 
2620 /*
2621  * Pinconf_ops handling
2622  */
2623 
2624 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
2625 					enum pin_config_param pull)
2626 {
2627 	switch (ctrl->type) {
2628 	case RK2928:
2629 	case RK3128:
2630 		return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT ||
2631 					pull == PIN_CONFIG_BIAS_DISABLE);
2632 	case RK3066B:
2633 		return pull ? false : true;
2634 	case PX30:
2635 	case RV1108:
2636 	case RK3188:
2637 	case RK3288:
2638 	case RK3308:
2639 	case RK3368:
2640 	case RK3399:
2641 		return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
2642 	}
2643 
2644 	return false;
2645 }
2646 
2647 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value);
2648 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset);
2649 
2650 /* set the pin config settings for a specified pin */
2651 static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
2652 				unsigned long *configs, unsigned num_configs)
2653 {
2654 	struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2655 	struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
2656 	enum pin_config_param param;
2657 	u32 arg;
2658 	int i;
2659 	int rc;
2660 
2661 	for (i = 0; i < num_configs; i++) {
2662 		param = pinconf_to_config_param(configs[i]);
2663 		arg = pinconf_to_config_argument(configs[i]);
2664 
2665 		switch (param) {
2666 		case PIN_CONFIG_BIAS_DISABLE:
2667 			rc =  rockchip_set_pull(bank, pin - bank->pin_base,
2668 				param);
2669 			if (rc)
2670 				return rc;
2671 			break;
2672 		case PIN_CONFIG_BIAS_PULL_UP:
2673 		case PIN_CONFIG_BIAS_PULL_DOWN:
2674 		case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
2675 		case PIN_CONFIG_BIAS_BUS_HOLD:
2676 			if (!rockchip_pinconf_pull_valid(info->ctrl, param))
2677 				return -ENOTSUPP;
2678 
2679 			if (!arg)
2680 				return -EINVAL;
2681 
2682 			rc = rockchip_set_pull(bank, pin - bank->pin_base,
2683 				param);
2684 			if (rc)
2685 				return rc;
2686 			break;
2687 		case PIN_CONFIG_OUTPUT:
2688 			rockchip_gpio_set(&bank->gpio_chip,
2689 					  pin - bank->pin_base, arg);
2690 			rc = _rockchip_pmx_gpio_set_direction(&bank->gpio_chip,
2691 					  pin - bank->pin_base, false);
2692 			if (rc)
2693 				return rc;
2694 			break;
2695 		case PIN_CONFIG_DRIVE_STRENGTH:
2696 			/* rk3288 is the first with per-pin drive-strength */
2697 			if (!info->ctrl->drv_calc_reg)
2698 				return -ENOTSUPP;
2699 
2700 			rc = rockchip_set_drive_perpin(bank,
2701 						pin - bank->pin_base, arg);
2702 			if (rc < 0)
2703 				return rc;
2704 			break;
2705 		case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
2706 			if (!info->ctrl->schmitt_calc_reg)
2707 				return -ENOTSUPP;
2708 
2709 			rc = rockchip_set_schmitt(bank,
2710 						  pin - bank->pin_base, arg);
2711 			if (rc < 0)
2712 				return rc;
2713 			break;
2714 		default:
2715 			return -ENOTSUPP;
2716 			break;
2717 		}
2718 	} /* for each config */
2719 
2720 	return 0;
2721 }
2722 
2723 /* get the pin config settings for a specified pin */
2724 static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
2725 							unsigned long *config)
2726 {
2727 	struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2728 	struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
2729 	enum pin_config_param param = pinconf_to_config_param(*config);
2730 	u16 arg;
2731 	int rc;
2732 
2733 	switch (param) {
2734 	case PIN_CONFIG_BIAS_DISABLE:
2735 		if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
2736 			return -EINVAL;
2737 
2738 		arg = 0;
2739 		break;
2740 	case PIN_CONFIG_BIAS_PULL_UP:
2741 	case PIN_CONFIG_BIAS_PULL_DOWN:
2742 	case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
2743 	case PIN_CONFIG_BIAS_BUS_HOLD:
2744 		if (!rockchip_pinconf_pull_valid(info->ctrl, param))
2745 			return -ENOTSUPP;
2746 
2747 		if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
2748 			return -EINVAL;
2749 
2750 		arg = 1;
2751 		break;
2752 	case PIN_CONFIG_OUTPUT:
2753 		rc = rockchip_get_mux(bank, pin - bank->pin_base);
2754 		if (rc != RK_FUNC_GPIO)
2755 			return -EINVAL;
2756 
2757 		rc = rockchip_gpio_get(&bank->gpio_chip, pin - bank->pin_base);
2758 		if (rc < 0)
2759 			return rc;
2760 
2761 		arg = rc ? 1 : 0;
2762 		break;
2763 	case PIN_CONFIG_DRIVE_STRENGTH:
2764 		/* rk3288 is the first with per-pin drive-strength */
2765 		if (!info->ctrl->drv_calc_reg)
2766 			return -ENOTSUPP;
2767 
2768 		rc = rockchip_get_drive_perpin(bank, pin - bank->pin_base);
2769 		if (rc < 0)
2770 			return rc;
2771 
2772 		arg = rc;
2773 		break;
2774 	case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
2775 		if (!info->ctrl->schmitt_calc_reg)
2776 			return -ENOTSUPP;
2777 
2778 		rc = rockchip_get_schmitt(bank, pin - bank->pin_base);
2779 		if (rc < 0)
2780 			return rc;
2781 
2782 		arg = rc;
2783 		break;
2784 	default:
2785 		return -ENOTSUPP;
2786 		break;
2787 	}
2788 
2789 	*config = pinconf_to_config_packed(param, arg);
2790 
2791 	return 0;
2792 }
2793 
2794 static const struct pinconf_ops rockchip_pinconf_ops = {
2795 	.pin_config_get			= rockchip_pinconf_get,
2796 	.pin_config_set			= rockchip_pinconf_set,
2797 	.is_generic			= true,
2798 };
2799 
2800 static const struct of_device_id rockchip_bank_match[] = {
2801 	{ .compatible = "rockchip,gpio-bank" },
2802 	{ .compatible = "rockchip,rk3188-gpio-bank0" },
2803 	{},
2804 };
2805 
2806 static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info,
2807 						struct device_node *np)
2808 {
2809 	struct device_node *child;
2810 
2811 	for_each_child_of_node(np, child) {
2812 		if (of_match_node(rockchip_bank_match, child))
2813 			continue;
2814 
2815 		info->nfunctions++;
2816 		info->ngroups += of_get_child_count(child);
2817 	}
2818 }
2819 
2820 static int rockchip_pinctrl_parse_groups(struct device_node *np,
2821 					      struct rockchip_pin_group *grp,
2822 					      struct rockchip_pinctrl *info,
2823 					      u32 index)
2824 {
2825 	struct rockchip_pin_bank *bank;
2826 	int size;
2827 	const __be32 *list;
2828 	int num;
2829 	int i, j;
2830 	int ret;
2831 
2832 	dev_dbg(info->dev, "group(%d): %pOFn\n", index, np);
2833 
2834 	/* Initialise group */
2835 	grp->name = np->name;
2836 
2837 	/*
2838 	 * the binding format is rockchip,pins = <bank pin mux CONFIG>,
2839 	 * do sanity check and calculate pins number
2840 	 */
2841 	list = of_get_property(np, "rockchip,pins", &size);
2842 	/* we do not check return since it's safe node passed down */
2843 	size /= sizeof(*list);
2844 	if (!size || size % 4) {
2845 		dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
2846 		return -EINVAL;
2847 	}
2848 
2849 	grp->npins = size / 4;
2850 
2851 	grp->pins = devm_kcalloc(info->dev, grp->npins, sizeof(unsigned int),
2852 						GFP_KERNEL);
2853 	grp->data = devm_kcalloc(info->dev,
2854 					grp->npins,
2855 					sizeof(struct rockchip_pin_config),
2856 					GFP_KERNEL);
2857 	if (!grp->pins || !grp->data)
2858 		return -ENOMEM;
2859 
2860 	for (i = 0, j = 0; i < size; i += 4, j++) {
2861 		const __be32 *phandle;
2862 		struct device_node *np_config;
2863 
2864 		num = be32_to_cpu(*list++);
2865 		bank = bank_num_to_bank(info, num);
2866 		if (IS_ERR(bank))
2867 			return PTR_ERR(bank);
2868 
2869 		grp->pins[j] = bank->pin_base + be32_to_cpu(*list++);
2870 		grp->data[j].func = be32_to_cpu(*list++);
2871 
2872 		phandle = list++;
2873 		if (!phandle)
2874 			return -EINVAL;
2875 
2876 		np_config = of_find_node_by_phandle(be32_to_cpup(phandle));
2877 		ret = pinconf_generic_parse_dt_config(np_config, NULL,
2878 				&grp->data[j].configs, &grp->data[j].nconfigs);
2879 		if (ret)
2880 			return ret;
2881 	}
2882 
2883 	return 0;
2884 }
2885 
2886 static int rockchip_pinctrl_parse_functions(struct device_node *np,
2887 						struct rockchip_pinctrl *info,
2888 						u32 index)
2889 {
2890 	struct device_node *child;
2891 	struct rockchip_pmx_func *func;
2892 	struct rockchip_pin_group *grp;
2893 	int ret;
2894 	static u32 grp_index;
2895 	u32 i = 0;
2896 
2897 	dev_dbg(info->dev, "parse function(%d): %pOFn\n", index, np);
2898 
2899 	func = &info->functions[index];
2900 
2901 	/* Initialise function */
2902 	func->name = np->name;
2903 	func->ngroups = of_get_child_count(np);
2904 	if (func->ngroups <= 0)
2905 		return 0;
2906 
2907 	func->groups = devm_kcalloc(info->dev,
2908 			func->ngroups, sizeof(char *), GFP_KERNEL);
2909 	if (!func->groups)
2910 		return -ENOMEM;
2911 
2912 	for_each_child_of_node(np, child) {
2913 		func->groups[i] = child->name;
2914 		grp = &info->groups[grp_index++];
2915 		ret = rockchip_pinctrl_parse_groups(child, grp, info, i++);
2916 		if (ret) {
2917 			of_node_put(child);
2918 			return ret;
2919 		}
2920 	}
2921 
2922 	return 0;
2923 }
2924 
2925 static int rockchip_pinctrl_parse_dt(struct platform_device *pdev,
2926 					      struct rockchip_pinctrl *info)
2927 {
2928 	struct device *dev = &pdev->dev;
2929 	struct device_node *np = dev->of_node;
2930 	struct device_node *child;
2931 	int ret;
2932 	int i;
2933 
2934 	rockchip_pinctrl_child_count(info, np);
2935 
2936 	dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
2937 	dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
2938 
2939 	info->functions = devm_kcalloc(dev,
2940 					      info->nfunctions,
2941 					      sizeof(struct rockchip_pmx_func),
2942 					      GFP_KERNEL);
2943 	if (!info->functions)
2944 		return -ENOMEM;
2945 
2946 	info->groups = devm_kcalloc(dev,
2947 					    info->ngroups,
2948 					    sizeof(struct rockchip_pin_group),
2949 					    GFP_KERNEL);
2950 	if (!info->groups)
2951 		return -ENOMEM;
2952 
2953 	i = 0;
2954 
2955 	for_each_child_of_node(np, child) {
2956 		if (of_match_node(rockchip_bank_match, child))
2957 			continue;
2958 
2959 		ret = rockchip_pinctrl_parse_functions(child, info, i++);
2960 		if (ret) {
2961 			dev_err(&pdev->dev, "failed to parse function\n");
2962 			of_node_put(child);
2963 			return ret;
2964 		}
2965 	}
2966 
2967 	return 0;
2968 }
2969 
2970 static int rockchip_pinctrl_register(struct platform_device *pdev,
2971 					struct rockchip_pinctrl *info)
2972 {
2973 	struct pinctrl_desc *ctrldesc = &info->pctl;
2974 	struct pinctrl_pin_desc *pindesc, *pdesc;
2975 	struct rockchip_pin_bank *pin_bank;
2976 	int pin, bank, ret;
2977 	int k;
2978 
2979 	ctrldesc->name = "rockchip-pinctrl";
2980 	ctrldesc->owner = THIS_MODULE;
2981 	ctrldesc->pctlops = &rockchip_pctrl_ops;
2982 	ctrldesc->pmxops = &rockchip_pmx_ops;
2983 	ctrldesc->confops = &rockchip_pinconf_ops;
2984 
2985 	pindesc = devm_kcalloc(&pdev->dev,
2986 			       info->ctrl->nr_pins, sizeof(*pindesc),
2987 			       GFP_KERNEL);
2988 	if (!pindesc)
2989 		return -ENOMEM;
2990 
2991 	ctrldesc->pins = pindesc;
2992 	ctrldesc->npins = info->ctrl->nr_pins;
2993 
2994 	pdesc = pindesc;
2995 	for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) {
2996 		pin_bank = &info->ctrl->pin_banks[bank];
2997 		for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) {
2998 			pdesc->number = k;
2999 			pdesc->name = kasprintf(GFP_KERNEL, "%s-%d",
3000 						pin_bank->name, pin);
3001 			pdesc++;
3002 		}
3003 	}
3004 
3005 	ret = rockchip_pinctrl_parse_dt(pdev, info);
3006 	if (ret)
3007 		return ret;
3008 
3009 	info->pctl_dev = devm_pinctrl_register(&pdev->dev, ctrldesc, info);
3010 	if (IS_ERR(info->pctl_dev)) {
3011 		dev_err(&pdev->dev, "could not register pinctrl driver\n");
3012 		return PTR_ERR(info->pctl_dev);
3013 	}
3014 
3015 	for (bank = 0; bank < info->ctrl->nr_banks; ++bank) {
3016 		pin_bank = &info->ctrl->pin_banks[bank];
3017 		pin_bank->grange.name = pin_bank->name;
3018 		pin_bank->grange.id = bank;
3019 		pin_bank->grange.pin_base = pin_bank->pin_base;
3020 		pin_bank->grange.base = pin_bank->gpio_chip.base;
3021 		pin_bank->grange.npins = pin_bank->gpio_chip.ngpio;
3022 		pin_bank->grange.gc = &pin_bank->gpio_chip;
3023 		pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange);
3024 	}
3025 
3026 	return 0;
3027 }
3028 
3029 /*
3030  * GPIO handling
3031  */
3032 
3033 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
3034 {
3035 	struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
3036 	void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR;
3037 	unsigned long flags;
3038 	u32 data;
3039 
3040 	clk_enable(bank->clk);
3041 	raw_spin_lock_irqsave(&bank->slock, flags);
3042 
3043 	data = readl(reg);
3044 	data &= ~BIT(offset);
3045 	if (value)
3046 		data |= BIT(offset);
3047 	writel(data, reg);
3048 
3049 	raw_spin_unlock_irqrestore(&bank->slock, flags);
3050 	clk_disable(bank->clk);
3051 }
3052 
3053 /*
3054  * Returns the level of the pin for input direction and setting of the DR
3055  * register for output gpios.
3056  */
3057 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset)
3058 {
3059 	struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
3060 	u32 data;
3061 
3062 	clk_enable(bank->clk);
3063 	data = readl(bank->reg_base + GPIO_EXT_PORT);
3064 	clk_disable(bank->clk);
3065 	data >>= offset;
3066 	data &= 1;
3067 	return data;
3068 }
3069 
3070 /*
3071  * gpiolib gpio_direction_input callback function. The setting of the pin
3072  * mux function as 'gpio input' will be handled by the pinctrl subsystem
3073  * interface.
3074  */
3075 static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
3076 {
3077 	return pinctrl_gpio_direction_input(gc->base + offset);
3078 }
3079 
3080 /*
3081  * gpiolib gpio_direction_output callback function. The setting of the pin
3082  * mux function as 'gpio output' will be handled by the pinctrl subsystem
3083  * interface.
3084  */
3085 static int rockchip_gpio_direction_output(struct gpio_chip *gc,
3086 					  unsigned offset, int value)
3087 {
3088 	rockchip_gpio_set(gc, offset, value);
3089 	return pinctrl_gpio_direction_output(gc->base + offset);
3090 }
3091 
3092 static void rockchip_gpio_set_debounce(struct gpio_chip *gc,
3093 				       unsigned int offset, bool enable)
3094 {
3095 	struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
3096 	void __iomem *reg = bank->reg_base + GPIO_DEBOUNCE;
3097 	unsigned long flags;
3098 	u32 data;
3099 
3100 	clk_enable(bank->clk);
3101 	raw_spin_lock_irqsave(&bank->slock, flags);
3102 
3103 	data = readl(reg);
3104 	if (enable)
3105 		data |= BIT(offset);
3106 	else
3107 		data &= ~BIT(offset);
3108 	writel(data, reg);
3109 
3110 	raw_spin_unlock_irqrestore(&bank->slock, flags);
3111 	clk_disable(bank->clk);
3112 }
3113 
3114 /*
3115  * gpiolib set_config callback function. The setting of the pin
3116  * mux function as 'gpio output' will be handled by the pinctrl subsystem
3117  * interface.
3118  */
3119 static int rockchip_gpio_set_config(struct gpio_chip *gc, unsigned int offset,
3120 				  unsigned long config)
3121 {
3122 	enum pin_config_param param = pinconf_to_config_param(config);
3123 
3124 	switch (param) {
3125 	case PIN_CONFIG_INPUT_DEBOUNCE:
3126 		rockchip_gpio_set_debounce(gc, offset, true);
3127 		/*
3128 		 * Rockchip's gpio could only support up to one period
3129 		 * of the debounce clock(pclk), which is far away from
3130 		 * satisftying the requirement, as pclk is usually near
3131 		 * 100MHz shared by all peripherals. So the fact is it
3132 		 * has crippled debounce capability could only be useful
3133 		 * to prevent any spurious glitches from waking up the system
3134 		 * if the gpio is conguired as wakeup interrupt source. Let's
3135 		 * still return -ENOTSUPP as before, to make sure the caller
3136 		 * of gpiod_set_debounce won't change its behaviour.
3137 		 */
3138 		return -ENOTSUPP;
3139 	default:
3140 		return -ENOTSUPP;
3141 	}
3142 }
3143 
3144 /*
3145  * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin
3146  * and a virtual IRQ, if not already present.
3147  */
3148 static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
3149 {
3150 	struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
3151 	unsigned int virq;
3152 
3153 	if (!bank->domain)
3154 		return -ENXIO;
3155 
3156 	virq = irq_create_mapping(bank->domain, offset);
3157 
3158 	return (virq) ? : -ENXIO;
3159 }
3160 
3161 static const struct gpio_chip rockchip_gpiolib_chip = {
3162 	.request = gpiochip_generic_request,
3163 	.free = gpiochip_generic_free,
3164 	.set = rockchip_gpio_set,
3165 	.get = rockchip_gpio_get,
3166 	.get_direction	= rockchip_gpio_get_direction,
3167 	.direction_input = rockchip_gpio_direction_input,
3168 	.direction_output = rockchip_gpio_direction_output,
3169 	.set_config = rockchip_gpio_set_config,
3170 	.to_irq = rockchip_gpio_to_irq,
3171 	.owner = THIS_MODULE,
3172 };
3173 
3174 /*
3175  * Interrupt handling
3176  */
3177 
3178 static void rockchip_irq_demux(struct irq_desc *desc)
3179 {
3180 	struct irq_chip *chip = irq_desc_get_chip(desc);
3181 	struct rockchip_pin_bank *bank = irq_desc_get_handler_data(desc);
3182 	u32 pend;
3183 
3184 	dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name);
3185 
3186 	chained_irq_enter(chip, desc);
3187 
3188 	pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS);
3189 
3190 	while (pend) {
3191 		unsigned int irq, virq;
3192 
3193 		irq = __ffs(pend);
3194 		pend &= ~BIT(irq);
3195 		virq = irq_linear_revmap(bank->domain, irq);
3196 
3197 		if (!virq) {
3198 			dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq);
3199 			continue;
3200 		}
3201 
3202 		dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq);
3203 
3204 		/*
3205 		 * Triggering IRQ on both rising and falling edge
3206 		 * needs manual intervention.
3207 		 */
3208 		if (bank->toggle_edge_mode & BIT(irq)) {
3209 			u32 data, data_old, polarity;
3210 			unsigned long flags;
3211 
3212 			data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT);
3213 			do {
3214 				raw_spin_lock_irqsave(&bank->slock, flags);
3215 
3216 				polarity = readl_relaxed(bank->reg_base +
3217 							 GPIO_INT_POLARITY);
3218 				if (data & BIT(irq))
3219 					polarity &= ~BIT(irq);
3220 				else
3221 					polarity |= BIT(irq);
3222 				writel(polarity,
3223 				       bank->reg_base + GPIO_INT_POLARITY);
3224 
3225 				raw_spin_unlock_irqrestore(&bank->slock, flags);
3226 
3227 				data_old = data;
3228 				data = readl_relaxed(bank->reg_base +
3229 						     GPIO_EXT_PORT);
3230 			} while ((data & BIT(irq)) != (data_old & BIT(irq)));
3231 		}
3232 
3233 		generic_handle_irq(virq);
3234 	}
3235 
3236 	chained_irq_exit(chip, desc);
3237 }
3238 
3239 static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
3240 {
3241 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
3242 	struct rockchip_pin_bank *bank = gc->private;
3243 	u32 mask = BIT(d->hwirq);
3244 	u32 polarity;
3245 	u32 level;
3246 	u32 data;
3247 	unsigned long flags;
3248 	int ret;
3249 
3250 	/* make sure the pin is configured as gpio input */
3251 	ret = rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO);
3252 	if (ret < 0)
3253 		return ret;
3254 
3255 	clk_enable(bank->clk);
3256 	raw_spin_lock_irqsave(&bank->slock, flags);
3257 
3258 	data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
3259 	data &= ~mask;
3260 	writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
3261 
3262 	raw_spin_unlock_irqrestore(&bank->slock, flags);
3263 
3264 	if (type & IRQ_TYPE_EDGE_BOTH)
3265 		irq_set_handler_locked(d, handle_edge_irq);
3266 	else
3267 		irq_set_handler_locked(d, handle_level_irq);
3268 
3269 	raw_spin_lock_irqsave(&bank->slock, flags);
3270 	irq_gc_lock(gc);
3271 
3272 	level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL);
3273 	polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY);
3274 
3275 	switch (type) {
3276 	case IRQ_TYPE_EDGE_BOTH:
3277 		bank->toggle_edge_mode |= mask;
3278 		level |= mask;
3279 
3280 		/*
3281 		 * Determine gpio state. If 1 next interrupt should be falling
3282 		 * otherwise rising.
3283 		 */
3284 		data = readl(bank->reg_base + GPIO_EXT_PORT);
3285 		if (data & mask)
3286 			polarity &= ~mask;
3287 		else
3288 			polarity |= mask;
3289 		break;
3290 	case IRQ_TYPE_EDGE_RISING:
3291 		bank->toggle_edge_mode &= ~mask;
3292 		level |= mask;
3293 		polarity |= mask;
3294 		break;
3295 	case IRQ_TYPE_EDGE_FALLING:
3296 		bank->toggle_edge_mode &= ~mask;
3297 		level |= mask;
3298 		polarity &= ~mask;
3299 		break;
3300 	case IRQ_TYPE_LEVEL_HIGH:
3301 		bank->toggle_edge_mode &= ~mask;
3302 		level &= ~mask;
3303 		polarity |= mask;
3304 		break;
3305 	case IRQ_TYPE_LEVEL_LOW:
3306 		bank->toggle_edge_mode &= ~mask;
3307 		level &= ~mask;
3308 		polarity &= ~mask;
3309 		break;
3310 	default:
3311 		irq_gc_unlock(gc);
3312 		raw_spin_unlock_irqrestore(&bank->slock, flags);
3313 		clk_disable(bank->clk);
3314 		return -EINVAL;
3315 	}
3316 
3317 	writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL);
3318 	writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY);
3319 
3320 	irq_gc_unlock(gc);
3321 	raw_spin_unlock_irqrestore(&bank->slock, flags);
3322 	clk_disable(bank->clk);
3323 
3324 	return 0;
3325 }
3326 
3327 static void rockchip_irq_suspend(struct irq_data *d)
3328 {
3329 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
3330 	struct rockchip_pin_bank *bank = gc->private;
3331 
3332 	clk_enable(bank->clk);
3333 	bank->saved_masks = irq_reg_readl(gc, GPIO_INTMASK);
3334 	irq_reg_writel(gc, ~gc->wake_active, GPIO_INTMASK);
3335 	clk_disable(bank->clk);
3336 }
3337 
3338 static void rockchip_irq_resume(struct irq_data *d)
3339 {
3340 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
3341 	struct rockchip_pin_bank *bank = gc->private;
3342 
3343 	clk_enable(bank->clk);
3344 	irq_reg_writel(gc, bank->saved_masks, GPIO_INTMASK);
3345 	clk_disable(bank->clk);
3346 }
3347 
3348 static void rockchip_irq_enable(struct irq_data *d)
3349 {
3350 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
3351 	struct rockchip_pin_bank *bank = gc->private;
3352 
3353 	clk_enable(bank->clk);
3354 	irq_gc_mask_clr_bit(d);
3355 }
3356 
3357 static void rockchip_irq_disable(struct irq_data *d)
3358 {
3359 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
3360 	struct rockchip_pin_bank *bank = gc->private;
3361 
3362 	irq_gc_mask_set_bit(d);
3363 	clk_disable(bank->clk);
3364 }
3365 
3366 static int rockchip_interrupts_register(struct platform_device *pdev,
3367 						struct rockchip_pinctrl *info)
3368 {
3369 	struct rockchip_pin_ctrl *ctrl = info->ctrl;
3370 	struct rockchip_pin_bank *bank = ctrl->pin_banks;
3371 	unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
3372 	struct irq_chip_generic *gc;
3373 	int ret;
3374 	int i, j;
3375 
3376 	for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3377 		if (!bank->valid) {
3378 			dev_warn(&pdev->dev, "bank %s is not valid\n",
3379 				 bank->name);
3380 			continue;
3381 		}
3382 
3383 		ret = clk_enable(bank->clk);
3384 		if (ret) {
3385 			dev_err(&pdev->dev, "failed to enable clock for bank %s\n",
3386 				bank->name);
3387 			continue;
3388 		}
3389 
3390 		bank->domain = irq_domain_add_linear(bank->of_node, 32,
3391 						&irq_generic_chip_ops, NULL);
3392 		if (!bank->domain) {
3393 			dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n",
3394 				 bank->name);
3395 			clk_disable(bank->clk);
3396 			continue;
3397 		}
3398 
3399 		ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1,
3400 					 "rockchip_gpio_irq", handle_level_irq,
3401 					 clr, 0, IRQ_GC_INIT_MASK_CACHE);
3402 		if (ret) {
3403 			dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n",
3404 				bank->name);
3405 			irq_domain_remove(bank->domain);
3406 			clk_disable(bank->clk);
3407 			continue;
3408 		}
3409 
3410 		/*
3411 		 * Linux assumes that all interrupts start out disabled/masked.
3412 		 * Our driver only uses the concept of masked and always keeps
3413 		 * things enabled, so for us that's all masked and all enabled.
3414 		 */
3415 		writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTMASK);
3416 		writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTEN);
3417 
3418 		gc = irq_get_domain_generic_chip(bank->domain, 0);
3419 		gc->reg_base = bank->reg_base;
3420 		gc->private = bank;
3421 		gc->chip_types[0].regs.mask = GPIO_INTMASK;
3422 		gc->chip_types[0].regs.ack = GPIO_PORTS_EOI;
3423 		gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
3424 		gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit;
3425 		gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit;
3426 		gc->chip_types[0].chip.irq_enable = rockchip_irq_enable;
3427 		gc->chip_types[0].chip.irq_disable = rockchip_irq_disable;
3428 		gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
3429 		gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend;
3430 		gc->chip_types[0].chip.irq_resume = rockchip_irq_resume;
3431 		gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type;
3432 		gc->wake_enabled = IRQ_MSK(bank->nr_pins);
3433 
3434 		irq_set_chained_handler_and_data(bank->irq,
3435 						 rockchip_irq_demux, bank);
3436 
3437 		/* map the gpio irqs here, when the clock is still running */
3438 		for (j = 0 ; j < 32 ; j++)
3439 			irq_create_mapping(bank->domain, j);
3440 
3441 		clk_disable(bank->clk);
3442 	}
3443 
3444 	return 0;
3445 }
3446 
3447 static int rockchip_gpiolib_register(struct platform_device *pdev,
3448 						struct rockchip_pinctrl *info)
3449 {
3450 	struct rockchip_pin_ctrl *ctrl = info->ctrl;
3451 	struct rockchip_pin_bank *bank = ctrl->pin_banks;
3452 	struct gpio_chip *gc;
3453 	int ret;
3454 	int i;
3455 
3456 	for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3457 		if (!bank->valid) {
3458 			dev_warn(&pdev->dev, "bank %s is not valid\n",
3459 				 bank->name);
3460 			continue;
3461 		}
3462 
3463 		bank->gpio_chip = rockchip_gpiolib_chip;
3464 
3465 		gc = &bank->gpio_chip;
3466 		gc->base = bank->pin_base;
3467 		gc->ngpio = bank->nr_pins;
3468 		gc->parent = &pdev->dev;
3469 		gc->of_node = bank->of_node;
3470 		gc->label = bank->name;
3471 
3472 		ret = gpiochip_add_data(gc, bank);
3473 		if (ret) {
3474 			dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n",
3475 							gc->label, ret);
3476 			goto fail;
3477 		}
3478 	}
3479 
3480 	rockchip_interrupts_register(pdev, info);
3481 
3482 	return 0;
3483 
3484 fail:
3485 	for (--i, --bank; i >= 0; --i, --bank) {
3486 		if (!bank->valid)
3487 			continue;
3488 		gpiochip_remove(&bank->gpio_chip);
3489 	}
3490 	return ret;
3491 }
3492 
3493 static int rockchip_gpiolib_unregister(struct platform_device *pdev,
3494 						struct rockchip_pinctrl *info)
3495 {
3496 	struct rockchip_pin_ctrl *ctrl = info->ctrl;
3497 	struct rockchip_pin_bank *bank = ctrl->pin_banks;
3498 	int i;
3499 
3500 	for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3501 		if (!bank->valid)
3502 			continue;
3503 		gpiochip_remove(&bank->gpio_chip);
3504 	}
3505 
3506 	return 0;
3507 }
3508 
3509 static int rockchip_get_bank_data(struct rockchip_pin_bank *bank,
3510 				  struct rockchip_pinctrl *info)
3511 {
3512 	struct resource res;
3513 	void __iomem *base;
3514 
3515 	if (of_address_to_resource(bank->of_node, 0, &res)) {
3516 		dev_err(info->dev, "cannot find IO resource for bank\n");
3517 		return -ENOENT;
3518 	}
3519 
3520 	bank->reg_base = devm_ioremap_resource(info->dev, &res);
3521 	if (IS_ERR(bank->reg_base))
3522 		return PTR_ERR(bank->reg_base);
3523 
3524 	/*
3525 	 * special case, where parts of the pull setting-registers are
3526 	 * part of the PMU register space
3527 	 */
3528 	if (of_device_is_compatible(bank->of_node,
3529 				    "rockchip,rk3188-gpio-bank0")) {
3530 		struct device_node *node;
3531 
3532 		node = of_parse_phandle(bank->of_node->parent,
3533 					"rockchip,pmu", 0);
3534 		if (!node) {
3535 			if (of_address_to_resource(bank->of_node, 1, &res)) {
3536 				dev_err(info->dev, "cannot find IO resource for bank\n");
3537 				return -ENOENT;
3538 			}
3539 
3540 			base = devm_ioremap_resource(info->dev, &res);
3541 			if (IS_ERR(base))
3542 				return PTR_ERR(base);
3543 			rockchip_regmap_config.max_register =
3544 						    resource_size(&res) - 4;
3545 			rockchip_regmap_config.name =
3546 					    "rockchip,rk3188-gpio-bank0-pull";
3547 			bank->regmap_pull = devm_regmap_init_mmio(info->dev,
3548 						    base,
3549 						    &rockchip_regmap_config);
3550 		}
3551 		of_node_put(node);
3552 	}
3553 
3554 	bank->irq = irq_of_parse_and_map(bank->of_node, 0);
3555 
3556 	bank->clk = of_clk_get(bank->of_node, 0);
3557 	if (IS_ERR(bank->clk))
3558 		return PTR_ERR(bank->clk);
3559 
3560 	return clk_prepare(bank->clk);
3561 }
3562 
3563 static const struct of_device_id rockchip_pinctrl_dt_match[];
3564 
3565 /* retrieve the soc specific data */
3566 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
3567 						struct rockchip_pinctrl *d,
3568 						struct platform_device *pdev)
3569 {
3570 	const struct of_device_id *match;
3571 	struct device_node *node = pdev->dev.of_node;
3572 	struct device_node *np;
3573 	struct rockchip_pin_ctrl *ctrl;
3574 	struct rockchip_pin_bank *bank;
3575 	int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j;
3576 
3577 	match = of_match_node(rockchip_pinctrl_dt_match, node);
3578 	ctrl = (struct rockchip_pin_ctrl *)match->data;
3579 
3580 	for_each_child_of_node(node, np) {
3581 		if (!of_find_property(np, "gpio-controller", NULL))
3582 			continue;
3583 
3584 		bank = ctrl->pin_banks;
3585 		for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3586 			if (!strcmp(bank->name, np->name)) {
3587 				bank->of_node = np;
3588 
3589 				if (!rockchip_get_bank_data(bank, d))
3590 					bank->valid = true;
3591 
3592 				break;
3593 			}
3594 		}
3595 	}
3596 
3597 	grf_offs = ctrl->grf_mux_offset;
3598 	pmu_offs = ctrl->pmu_mux_offset;
3599 	drv_pmu_offs = ctrl->pmu_drv_offset;
3600 	drv_grf_offs = ctrl->grf_drv_offset;
3601 	bank = ctrl->pin_banks;
3602 	for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3603 		int bank_pins = 0;
3604 
3605 		raw_spin_lock_init(&bank->slock);
3606 		bank->drvdata = d;
3607 		bank->pin_base = ctrl->nr_pins;
3608 		ctrl->nr_pins += bank->nr_pins;
3609 
3610 		/* calculate iomux and drv offsets */
3611 		for (j = 0; j < 4; j++) {
3612 			struct rockchip_iomux *iom = &bank->iomux[j];
3613 			struct rockchip_drv *drv = &bank->drv[j];
3614 			int inc;
3615 
3616 			if (bank_pins >= bank->nr_pins)
3617 				break;
3618 
3619 			/* preset iomux offset value, set new start value */
3620 			if (iom->offset >= 0) {
3621 				if (iom->type & IOMUX_SOURCE_PMU)
3622 					pmu_offs = iom->offset;
3623 				else
3624 					grf_offs = iom->offset;
3625 			} else { /* set current iomux offset */
3626 				iom->offset = (iom->type & IOMUX_SOURCE_PMU) ?
3627 							pmu_offs : grf_offs;
3628 			}
3629 
3630 			/* preset drv offset value, set new start value */
3631 			if (drv->offset >= 0) {
3632 				if (iom->type & IOMUX_SOURCE_PMU)
3633 					drv_pmu_offs = drv->offset;
3634 				else
3635 					drv_grf_offs = drv->offset;
3636 			} else { /* set current drv offset */
3637 				drv->offset = (iom->type & IOMUX_SOURCE_PMU) ?
3638 						drv_pmu_offs : drv_grf_offs;
3639 			}
3640 
3641 			dev_dbg(d->dev, "bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n",
3642 				i, j, iom->offset, drv->offset);
3643 
3644 			/*
3645 			 * Increase offset according to iomux width.
3646 			 * 4bit iomux'es are spread over two registers.
3647 			 */
3648 			inc = (iom->type & (IOMUX_WIDTH_4BIT |
3649 					    IOMUX_WIDTH_3BIT |
3650 					    IOMUX_WIDTH_2BIT)) ? 8 : 4;
3651 			if (iom->type & IOMUX_SOURCE_PMU)
3652 				pmu_offs += inc;
3653 			else
3654 				grf_offs += inc;
3655 
3656 			/*
3657 			 * Increase offset according to drv width.
3658 			 * 3bit drive-strenth'es are spread over two registers.
3659 			 */
3660 			if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
3661 			    (drv->drv_type == DRV_TYPE_IO_3V3_ONLY))
3662 				inc = 8;
3663 			else
3664 				inc = 4;
3665 
3666 			if (iom->type & IOMUX_SOURCE_PMU)
3667 				drv_pmu_offs += inc;
3668 			else
3669 				drv_grf_offs += inc;
3670 
3671 			bank_pins += 8;
3672 		}
3673 
3674 		/* calculate the per-bank recalced_mask */
3675 		for (j = 0; j < ctrl->niomux_recalced; j++) {
3676 			int pin = 0;
3677 
3678 			if (ctrl->iomux_recalced[j].num == bank->bank_num) {
3679 				pin = ctrl->iomux_recalced[j].pin;
3680 				bank->recalced_mask |= BIT(pin);
3681 			}
3682 		}
3683 
3684 		/* calculate the per-bank route_mask */
3685 		for (j = 0; j < ctrl->niomux_routes; j++) {
3686 			int pin = 0;
3687 
3688 			if (ctrl->iomux_routes[j].bank_num == bank->bank_num) {
3689 				pin = ctrl->iomux_routes[j].pin;
3690 				bank->route_mask |= BIT(pin);
3691 			}
3692 		}
3693 	}
3694 
3695 	return ctrl;
3696 }
3697 
3698 #define RK3288_GRF_GPIO6C_IOMUX		0x64
3699 #define GPIO6C6_SEL_WRITE_ENABLE	BIT(28)
3700 
3701 static u32 rk3288_grf_gpio6c_iomux;
3702 
3703 static int __maybe_unused rockchip_pinctrl_suspend(struct device *dev)
3704 {
3705 	struct rockchip_pinctrl *info = dev_get_drvdata(dev);
3706 	int ret = pinctrl_force_sleep(info->pctl_dev);
3707 
3708 	if (ret)
3709 		return ret;
3710 
3711 	/*
3712 	 * RK3288 GPIO6_C6 mux would be modified by Maskrom when resume, so save
3713 	 * the setting here, and restore it at resume.
3714 	 */
3715 	if (info->ctrl->type == RK3288) {
3716 		ret = regmap_read(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
3717 				  &rk3288_grf_gpio6c_iomux);
3718 		if (ret) {
3719 			pinctrl_force_default(info->pctl_dev);
3720 			return ret;
3721 		}
3722 	}
3723 
3724 	return 0;
3725 }
3726 
3727 static int __maybe_unused rockchip_pinctrl_resume(struct device *dev)
3728 {
3729 	struct rockchip_pinctrl *info = dev_get_drvdata(dev);
3730 	int ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
3731 			       rk3288_grf_gpio6c_iomux |
3732 			       GPIO6C6_SEL_WRITE_ENABLE);
3733 
3734 	if (ret)
3735 		return ret;
3736 
3737 	return pinctrl_force_default(info->pctl_dev);
3738 }
3739 
3740 static SIMPLE_DEV_PM_OPS(rockchip_pinctrl_dev_pm_ops, rockchip_pinctrl_suspend,
3741 			 rockchip_pinctrl_resume);
3742 
3743 static int rockchip_pinctrl_probe(struct platform_device *pdev)
3744 {
3745 	struct rockchip_pinctrl *info;
3746 	struct device *dev = &pdev->dev;
3747 	struct rockchip_pin_ctrl *ctrl;
3748 	struct device_node *np = pdev->dev.of_node, *node;
3749 	struct resource *res;
3750 	void __iomem *base;
3751 	int ret;
3752 
3753 	if (!dev->of_node) {
3754 		dev_err(dev, "device tree node not found\n");
3755 		return -ENODEV;
3756 	}
3757 
3758 	info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
3759 	if (!info)
3760 		return -ENOMEM;
3761 
3762 	info->dev = dev;
3763 
3764 	ctrl = rockchip_pinctrl_get_soc_data(info, pdev);
3765 	if (!ctrl) {
3766 		dev_err(dev, "driver data not available\n");
3767 		return -EINVAL;
3768 	}
3769 	info->ctrl = ctrl;
3770 
3771 	node = of_parse_phandle(np, "rockchip,grf", 0);
3772 	if (node) {
3773 		info->regmap_base = syscon_node_to_regmap(node);
3774 		if (IS_ERR(info->regmap_base))
3775 			return PTR_ERR(info->regmap_base);
3776 	} else {
3777 		res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3778 		base = devm_ioremap_resource(&pdev->dev, res);
3779 		if (IS_ERR(base))
3780 			return PTR_ERR(base);
3781 
3782 		rockchip_regmap_config.max_register = resource_size(res) - 4;
3783 		rockchip_regmap_config.name = "rockchip,pinctrl";
3784 		info->regmap_base = devm_regmap_init_mmio(&pdev->dev, base,
3785 						    &rockchip_regmap_config);
3786 
3787 		/* to check for the old dt-bindings */
3788 		info->reg_size = resource_size(res);
3789 
3790 		/* Honor the old binding, with pull registers as 2nd resource */
3791 		if (ctrl->type == RK3188 && info->reg_size < 0x200) {
3792 			res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
3793 			base = devm_ioremap_resource(&pdev->dev, res);
3794 			if (IS_ERR(base))
3795 				return PTR_ERR(base);
3796 
3797 			rockchip_regmap_config.max_register =
3798 							resource_size(res) - 4;
3799 			rockchip_regmap_config.name = "rockchip,pinctrl-pull";
3800 			info->regmap_pull = devm_regmap_init_mmio(&pdev->dev,
3801 						    base,
3802 						    &rockchip_regmap_config);
3803 		}
3804 	}
3805 
3806 	/* try to find the optional reference to the pmu syscon */
3807 	node = of_parse_phandle(np, "rockchip,pmu", 0);
3808 	if (node) {
3809 		info->regmap_pmu = syscon_node_to_regmap(node);
3810 		if (IS_ERR(info->regmap_pmu))
3811 			return PTR_ERR(info->regmap_pmu);
3812 	}
3813 
3814 	ret = rockchip_gpiolib_register(pdev, info);
3815 	if (ret)
3816 		return ret;
3817 
3818 	ret = rockchip_pinctrl_register(pdev, info);
3819 	if (ret) {
3820 		rockchip_gpiolib_unregister(pdev, info);
3821 		return ret;
3822 	}
3823 
3824 	platform_set_drvdata(pdev, info);
3825 
3826 	return 0;
3827 }
3828 
3829 static struct rockchip_pin_bank px30_pin_banks[] = {
3830 	PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
3831 					     IOMUX_SOURCE_PMU,
3832 					     IOMUX_SOURCE_PMU,
3833 					     IOMUX_SOURCE_PMU
3834 			    ),
3835 	PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT,
3836 					     IOMUX_WIDTH_4BIT,
3837 					     IOMUX_WIDTH_4BIT,
3838 					     IOMUX_WIDTH_4BIT
3839 			    ),
3840 	PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT,
3841 					     IOMUX_WIDTH_4BIT,
3842 					     IOMUX_WIDTH_4BIT,
3843 					     IOMUX_WIDTH_4BIT
3844 			    ),
3845 	PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT,
3846 					     IOMUX_WIDTH_4BIT,
3847 					     IOMUX_WIDTH_4BIT,
3848 					     IOMUX_WIDTH_4BIT
3849 			    ),
3850 };
3851 
3852 static struct rockchip_pin_ctrl px30_pin_ctrl = {
3853 		.pin_banks		= px30_pin_banks,
3854 		.nr_banks		= ARRAY_SIZE(px30_pin_banks),
3855 		.label			= "PX30-GPIO",
3856 		.type			= PX30,
3857 		.grf_mux_offset		= 0x0,
3858 		.pmu_mux_offset		= 0x0,
3859 		.iomux_routes		= px30_mux_route_data,
3860 		.niomux_routes		= ARRAY_SIZE(px30_mux_route_data),
3861 		.pull_calc_reg		= px30_calc_pull_reg_and_bit,
3862 		.drv_calc_reg		= px30_calc_drv_reg_and_bit,
3863 		.schmitt_calc_reg	= px30_calc_schmitt_reg_and_bit,
3864 };
3865 
3866 static struct rockchip_pin_bank rv1108_pin_banks[] = {
3867 	PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
3868 					     IOMUX_SOURCE_PMU,
3869 					     IOMUX_SOURCE_PMU,
3870 					     IOMUX_SOURCE_PMU),
3871 	PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
3872 	PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0),
3873 	PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0),
3874 };
3875 
3876 static struct rockchip_pin_ctrl rv1108_pin_ctrl = {
3877 	.pin_banks		= rv1108_pin_banks,
3878 	.nr_banks		= ARRAY_SIZE(rv1108_pin_banks),
3879 	.label			= "RV1108-GPIO",
3880 	.type			= RV1108,
3881 	.grf_mux_offset		= 0x10,
3882 	.pmu_mux_offset		= 0x0,
3883 	.iomux_recalced		= rv1108_mux_recalced_data,
3884 	.niomux_recalced	= ARRAY_SIZE(rv1108_mux_recalced_data),
3885 	.pull_calc_reg		= rv1108_calc_pull_reg_and_bit,
3886 	.drv_calc_reg		= rv1108_calc_drv_reg_and_bit,
3887 	.schmitt_calc_reg	= rv1108_calc_schmitt_reg_and_bit,
3888 };
3889 
3890 static struct rockchip_pin_bank rk2928_pin_banks[] = {
3891 	PIN_BANK(0, 32, "gpio0"),
3892 	PIN_BANK(1, 32, "gpio1"),
3893 	PIN_BANK(2, 32, "gpio2"),
3894 	PIN_BANK(3, 32, "gpio3"),
3895 };
3896 
3897 static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
3898 		.pin_banks		= rk2928_pin_banks,
3899 		.nr_banks		= ARRAY_SIZE(rk2928_pin_banks),
3900 		.label			= "RK2928-GPIO",
3901 		.type			= RK2928,
3902 		.grf_mux_offset		= 0xa8,
3903 		.pull_calc_reg		= rk2928_calc_pull_reg_and_bit,
3904 };
3905 
3906 static struct rockchip_pin_bank rk3036_pin_banks[] = {
3907 	PIN_BANK(0, 32, "gpio0"),
3908 	PIN_BANK(1, 32, "gpio1"),
3909 	PIN_BANK(2, 32, "gpio2"),
3910 };
3911 
3912 static struct rockchip_pin_ctrl rk3036_pin_ctrl = {
3913 		.pin_banks		= rk3036_pin_banks,
3914 		.nr_banks		= ARRAY_SIZE(rk3036_pin_banks),
3915 		.label			= "RK3036-GPIO",
3916 		.type			= RK2928,
3917 		.grf_mux_offset		= 0xa8,
3918 		.pull_calc_reg		= rk2928_calc_pull_reg_and_bit,
3919 };
3920 
3921 static struct rockchip_pin_bank rk3066a_pin_banks[] = {
3922 	PIN_BANK(0, 32, "gpio0"),
3923 	PIN_BANK(1, 32, "gpio1"),
3924 	PIN_BANK(2, 32, "gpio2"),
3925 	PIN_BANK(3, 32, "gpio3"),
3926 	PIN_BANK(4, 32, "gpio4"),
3927 	PIN_BANK(6, 16, "gpio6"),
3928 };
3929 
3930 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
3931 		.pin_banks		= rk3066a_pin_banks,
3932 		.nr_banks		= ARRAY_SIZE(rk3066a_pin_banks),
3933 		.label			= "RK3066a-GPIO",
3934 		.type			= RK2928,
3935 		.grf_mux_offset		= 0xa8,
3936 		.pull_calc_reg		= rk2928_calc_pull_reg_and_bit,
3937 };
3938 
3939 static struct rockchip_pin_bank rk3066b_pin_banks[] = {
3940 	PIN_BANK(0, 32, "gpio0"),
3941 	PIN_BANK(1, 32, "gpio1"),
3942 	PIN_BANK(2, 32, "gpio2"),
3943 	PIN_BANK(3, 32, "gpio3"),
3944 };
3945 
3946 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
3947 		.pin_banks	= rk3066b_pin_banks,
3948 		.nr_banks	= ARRAY_SIZE(rk3066b_pin_banks),
3949 		.label		= "RK3066b-GPIO",
3950 		.type		= RK3066B,
3951 		.grf_mux_offset	= 0x60,
3952 };
3953 
3954 static struct rockchip_pin_bank rk3128_pin_banks[] = {
3955 	PIN_BANK(0, 32, "gpio0"),
3956 	PIN_BANK(1, 32, "gpio1"),
3957 	PIN_BANK(2, 32, "gpio2"),
3958 	PIN_BANK(3, 32, "gpio3"),
3959 };
3960 
3961 static struct rockchip_pin_ctrl rk3128_pin_ctrl = {
3962 		.pin_banks		= rk3128_pin_banks,
3963 		.nr_banks		= ARRAY_SIZE(rk3128_pin_banks),
3964 		.label			= "RK3128-GPIO",
3965 		.type			= RK3128,
3966 		.grf_mux_offset		= 0xa8,
3967 		.iomux_recalced		= rk3128_mux_recalced_data,
3968 		.niomux_recalced	= ARRAY_SIZE(rk3128_mux_recalced_data),
3969 		.iomux_routes		= rk3128_mux_route_data,
3970 		.niomux_routes		= ARRAY_SIZE(rk3128_mux_route_data),
3971 		.pull_calc_reg		= rk3128_calc_pull_reg_and_bit,
3972 };
3973 
3974 static struct rockchip_pin_bank rk3188_pin_banks[] = {
3975 	PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0),
3976 	PIN_BANK(1, 32, "gpio1"),
3977 	PIN_BANK(2, 32, "gpio2"),
3978 	PIN_BANK(3, 32, "gpio3"),
3979 };
3980 
3981 static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
3982 		.pin_banks		= rk3188_pin_banks,
3983 		.nr_banks		= ARRAY_SIZE(rk3188_pin_banks),
3984 		.label			= "RK3188-GPIO",
3985 		.type			= RK3188,
3986 		.grf_mux_offset		= 0x60,
3987 		.iomux_routes		= rk3188_mux_route_data,
3988 		.niomux_routes		= ARRAY_SIZE(rk3188_mux_route_data),
3989 		.pull_calc_reg		= rk3188_calc_pull_reg_and_bit,
3990 };
3991 
3992 static struct rockchip_pin_bank rk3228_pin_banks[] = {
3993 	PIN_BANK(0, 32, "gpio0"),
3994 	PIN_BANK(1, 32, "gpio1"),
3995 	PIN_BANK(2, 32, "gpio2"),
3996 	PIN_BANK(3, 32, "gpio3"),
3997 };
3998 
3999 static struct rockchip_pin_ctrl rk3228_pin_ctrl = {
4000 		.pin_banks		= rk3228_pin_banks,
4001 		.nr_banks		= ARRAY_SIZE(rk3228_pin_banks),
4002 		.label			= "RK3228-GPIO",
4003 		.type			= RK3288,
4004 		.grf_mux_offset		= 0x0,
4005 		.iomux_routes		= rk3228_mux_route_data,
4006 		.niomux_routes		= ARRAY_SIZE(rk3228_mux_route_data),
4007 		.pull_calc_reg		= rk3228_calc_pull_reg_and_bit,
4008 		.drv_calc_reg		= rk3228_calc_drv_reg_and_bit,
4009 };
4010 
4011 static struct rockchip_pin_bank rk3288_pin_banks[] = {
4012 	PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU,
4013 					     IOMUX_SOURCE_PMU,
4014 					     IOMUX_SOURCE_PMU,
4015 					     IOMUX_UNROUTED
4016 			    ),
4017 	PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED,
4018 					     IOMUX_UNROUTED,
4019 					     IOMUX_UNROUTED,
4020 					     0
4021 			    ),
4022 	PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED),
4023 	PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT),
4024 	PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
4025 					     IOMUX_WIDTH_4BIT,
4026 					     0,
4027 					     0
4028 			    ),
4029 	PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED,
4030 					     0,
4031 					     0,
4032 					     IOMUX_UNROUTED
4033 			    ),
4034 	PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED),
4035 	PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0,
4036 					     0,
4037 					     IOMUX_WIDTH_4BIT,
4038 					     IOMUX_UNROUTED
4039 			    ),
4040 	PIN_BANK(8, 16, "gpio8"),
4041 };
4042 
4043 static struct rockchip_pin_ctrl rk3288_pin_ctrl = {
4044 		.pin_banks		= rk3288_pin_banks,
4045 		.nr_banks		= ARRAY_SIZE(rk3288_pin_banks),
4046 		.label			= "RK3288-GPIO",
4047 		.type			= RK3288,
4048 		.grf_mux_offset		= 0x0,
4049 		.pmu_mux_offset		= 0x84,
4050 		.iomux_routes		= rk3288_mux_route_data,
4051 		.niomux_routes		= ARRAY_SIZE(rk3288_mux_route_data),
4052 		.pull_calc_reg		= rk3288_calc_pull_reg_and_bit,
4053 		.drv_calc_reg		= rk3288_calc_drv_reg_and_bit,
4054 };
4055 
4056 static struct rockchip_pin_bank rk3308_pin_banks[] = {
4057 	PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_WIDTH_2BIT,
4058 					     IOMUX_WIDTH_2BIT,
4059 					     IOMUX_WIDTH_2BIT,
4060 					     IOMUX_WIDTH_2BIT),
4061 	PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_2BIT,
4062 					     IOMUX_WIDTH_2BIT,
4063 					     IOMUX_WIDTH_2BIT,
4064 					     IOMUX_WIDTH_2BIT),
4065 	PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_2BIT,
4066 					     IOMUX_WIDTH_2BIT,
4067 					     IOMUX_WIDTH_2BIT,
4068 					     IOMUX_WIDTH_2BIT),
4069 	PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_2BIT,
4070 					     IOMUX_WIDTH_2BIT,
4071 					     IOMUX_WIDTH_2BIT,
4072 					     IOMUX_WIDTH_2BIT),
4073 	PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_2BIT,
4074 					     IOMUX_WIDTH_2BIT,
4075 					     IOMUX_WIDTH_2BIT,
4076 					     IOMUX_WIDTH_2BIT),
4077 };
4078 
4079 static struct rockchip_pin_ctrl rk3308_pin_ctrl = {
4080 		.pin_banks		= rk3308_pin_banks,
4081 		.nr_banks		= ARRAY_SIZE(rk3308_pin_banks),
4082 		.label			= "RK3308-GPIO",
4083 		.type			= RK3308,
4084 		.grf_mux_offset		= 0x0,
4085 		.iomux_recalced		= rk3308_mux_recalced_data,
4086 		.niomux_recalced	= ARRAY_SIZE(rk3308_mux_recalced_data),
4087 		.iomux_routes		= rk3308_mux_route_data,
4088 		.niomux_routes		= ARRAY_SIZE(rk3308_mux_route_data),
4089 		.pull_calc_reg		= rk3308_calc_pull_reg_and_bit,
4090 		.drv_calc_reg		= rk3308_calc_drv_reg_and_bit,
4091 		.schmitt_calc_reg	= rk3308_calc_schmitt_reg_and_bit,
4092 };
4093 
4094 static struct rockchip_pin_bank rk3328_pin_banks[] = {
4095 	PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0),
4096 	PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
4097 	PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0,
4098 			     IOMUX_WIDTH_3BIT,
4099 			     IOMUX_WIDTH_3BIT,
4100 			     0),
4101 	PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3",
4102 			     IOMUX_WIDTH_3BIT,
4103 			     IOMUX_WIDTH_3BIT,
4104 			     0,
4105 			     0),
4106 };
4107 
4108 static struct rockchip_pin_ctrl rk3328_pin_ctrl = {
4109 		.pin_banks		= rk3328_pin_banks,
4110 		.nr_banks		= ARRAY_SIZE(rk3328_pin_banks),
4111 		.label			= "RK3328-GPIO",
4112 		.type			= RK3288,
4113 		.grf_mux_offset		= 0x0,
4114 		.iomux_recalced		= rk3328_mux_recalced_data,
4115 		.niomux_recalced	= ARRAY_SIZE(rk3328_mux_recalced_data),
4116 		.iomux_routes		= rk3328_mux_route_data,
4117 		.niomux_routes		= ARRAY_SIZE(rk3328_mux_route_data),
4118 		.pull_calc_reg		= rk3228_calc_pull_reg_and_bit,
4119 		.drv_calc_reg		= rk3228_calc_drv_reg_and_bit,
4120 		.schmitt_calc_reg	= rk3328_calc_schmitt_reg_and_bit,
4121 };
4122 
4123 static struct rockchip_pin_bank rk3368_pin_banks[] = {
4124 	PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
4125 					     IOMUX_SOURCE_PMU,
4126 					     IOMUX_SOURCE_PMU,
4127 					     IOMUX_SOURCE_PMU
4128 			    ),
4129 	PIN_BANK(1, 32, "gpio1"),
4130 	PIN_BANK(2, 32, "gpio2"),
4131 	PIN_BANK(3, 32, "gpio3"),
4132 };
4133 
4134 static struct rockchip_pin_ctrl rk3368_pin_ctrl = {
4135 		.pin_banks		= rk3368_pin_banks,
4136 		.nr_banks		= ARRAY_SIZE(rk3368_pin_banks),
4137 		.label			= "RK3368-GPIO",
4138 		.type			= RK3368,
4139 		.grf_mux_offset		= 0x0,
4140 		.pmu_mux_offset		= 0x0,
4141 		.pull_calc_reg		= rk3368_calc_pull_reg_and_bit,
4142 		.drv_calc_reg		= rk3368_calc_drv_reg_and_bit,
4143 };
4144 
4145 static struct rockchip_pin_bank rk3399_pin_banks[] = {
4146 	PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0",
4147 							 IOMUX_SOURCE_PMU,
4148 							 IOMUX_SOURCE_PMU,
4149 							 IOMUX_SOURCE_PMU,
4150 							 IOMUX_SOURCE_PMU,
4151 							 DRV_TYPE_IO_1V8_ONLY,
4152 							 DRV_TYPE_IO_1V8_ONLY,
4153 							 DRV_TYPE_IO_DEFAULT,
4154 							 DRV_TYPE_IO_DEFAULT,
4155 							 0x80,
4156 							 0x88,
4157 							 -1,
4158 							 -1,
4159 							 PULL_TYPE_IO_1V8_ONLY,
4160 							 PULL_TYPE_IO_1V8_ONLY,
4161 							 PULL_TYPE_IO_DEFAULT,
4162 							 PULL_TYPE_IO_DEFAULT
4163 							),
4164 	PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU,
4165 					IOMUX_SOURCE_PMU,
4166 					IOMUX_SOURCE_PMU,
4167 					IOMUX_SOURCE_PMU,
4168 					DRV_TYPE_IO_1V8_OR_3V0,
4169 					DRV_TYPE_IO_1V8_OR_3V0,
4170 					DRV_TYPE_IO_1V8_OR_3V0,
4171 					DRV_TYPE_IO_1V8_OR_3V0,
4172 					0xa0,
4173 					0xa8,
4174 					0xb0,
4175 					0xb8
4176 					),
4177 	PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0,
4178 				      DRV_TYPE_IO_1V8_OR_3V0,
4179 				      DRV_TYPE_IO_1V8_ONLY,
4180 				      DRV_TYPE_IO_1V8_ONLY,
4181 				      PULL_TYPE_IO_DEFAULT,
4182 				      PULL_TYPE_IO_DEFAULT,
4183 				      PULL_TYPE_IO_1V8_ONLY,
4184 				      PULL_TYPE_IO_1V8_ONLY
4185 				      ),
4186 	PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY,
4187 			   DRV_TYPE_IO_3V3_ONLY,
4188 			   DRV_TYPE_IO_3V3_ONLY,
4189 			   DRV_TYPE_IO_1V8_OR_3V0
4190 			   ),
4191 	PIN_BANK_DRV_FLAGS(4, 32, "gpio4", DRV_TYPE_IO_1V8_OR_3V0,
4192 			   DRV_TYPE_IO_1V8_3V0_AUTO,
4193 			   DRV_TYPE_IO_1V8_OR_3V0,
4194 			   DRV_TYPE_IO_1V8_OR_3V0
4195 			   ),
4196 };
4197 
4198 static struct rockchip_pin_ctrl rk3399_pin_ctrl = {
4199 		.pin_banks		= rk3399_pin_banks,
4200 		.nr_banks		= ARRAY_SIZE(rk3399_pin_banks),
4201 		.label			= "RK3399-GPIO",
4202 		.type			= RK3399,
4203 		.grf_mux_offset		= 0xe000,
4204 		.pmu_mux_offset		= 0x0,
4205 		.grf_drv_offset		= 0xe100,
4206 		.pmu_drv_offset		= 0x80,
4207 		.iomux_routes		= rk3399_mux_route_data,
4208 		.niomux_routes		= ARRAY_SIZE(rk3399_mux_route_data),
4209 		.pull_calc_reg		= rk3399_calc_pull_reg_and_bit,
4210 		.drv_calc_reg		= rk3399_calc_drv_reg_and_bit,
4211 };
4212 
4213 static const struct of_device_id rockchip_pinctrl_dt_match[] = {
4214 	{ .compatible = "rockchip,px30-pinctrl",
4215 		.data = &px30_pin_ctrl },
4216 	{ .compatible = "rockchip,rv1108-pinctrl",
4217 		.data = &rv1108_pin_ctrl },
4218 	{ .compatible = "rockchip,rk2928-pinctrl",
4219 		.data = &rk2928_pin_ctrl },
4220 	{ .compatible = "rockchip,rk3036-pinctrl",
4221 		.data = &rk3036_pin_ctrl },
4222 	{ .compatible = "rockchip,rk3066a-pinctrl",
4223 		.data = &rk3066a_pin_ctrl },
4224 	{ .compatible = "rockchip,rk3066b-pinctrl",
4225 		.data = &rk3066b_pin_ctrl },
4226 	{ .compatible = "rockchip,rk3128-pinctrl",
4227 		.data = (void *)&rk3128_pin_ctrl },
4228 	{ .compatible = "rockchip,rk3188-pinctrl",
4229 		.data = &rk3188_pin_ctrl },
4230 	{ .compatible = "rockchip,rk3228-pinctrl",
4231 		.data = &rk3228_pin_ctrl },
4232 	{ .compatible = "rockchip,rk3288-pinctrl",
4233 		.data = &rk3288_pin_ctrl },
4234 	{ .compatible = "rockchip,rk3308-pinctrl",
4235 		.data = &rk3308_pin_ctrl },
4236 	{ .compatible = "rockchip,rk3328-pinctrl",
4237 		.data = &rk3328_pin_ctrl },
4238 	{ .compatible = "rockchip,rk3368-pinctrl",
4239 		.data = &rk3368_pin_ctrl },
4240 	{ .compatible = "rockchip,rk3399-pinctrl",
4241 		.data = &rk3399_pin_ctrl },
4242 	{},
4243 };
4244 
4245 static struct platform_driver rockchip_pinctrl_driver = {
4246 	.probe		= rockchip_pinctrl_probe,
4247 	.driver = {
4248 		.name	= "rockchip-pinctrl",
4249 		.pm = &rockchip_pinctrl_dev_pm_ops,
4250 		.of_match_table = rockchip_pinctrl_dt_match,
4251 	},
4252 };
4253 
4254 static int __init rockchip_pinctrl_drv_register(void)
4255 {
4256 	return platform_driver_register(&rockchip_pinctrl_driver);
4257 }
4258 postcore_initcall(rockchip_pinctrl_drv_register);
4259