1 /* 2 * Pinctrl driver for Rockchip SoCs 3 * 4 * Copyright (c) 2013 MundoReader S.L. 5 * Author: Heiko Stuebner <heiko@sntech.de> 6 * 7 * With some ideas taken from pinctrl-samsung: 8 * Copyright (c) 2012 Samsung Electronics Co., Ltd. 9 * http://www.samsung.com 10 * Copyright (c) 2012 Linaro Ltd 11 * http://www.linaro.org 12 * 13 * and pinctrl-at91: 14 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> 15 * 16 * This program is free software; you can redistribute it and/or modify 17 * it under the terms of the GNU General Public License version 2 as published 18 * by the Free Software Foundation. 19 * 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 */ 25 26 #include <linux/init.h> 27 #include <linux/platform_device.h> 28 #include <linux/io.h> 29 #include <linux/bitops.h> 30 #include <linux/gpio/driver.h> 31 #include <linux/of_address.h> 32 #include <linux/of_irq.h> 33 #include <linux/pinctrl/machine.h> 34 #include <linux/pinctrl/pinconf.h> 35 #include <linux/pinctrl/pinctrl.h> 36 #include <linux/pinctrl/pinmux.h> 37 #include <linux/pinctrl/pinconf-generic.h> 38 #include <linux/irqchip/chained_irq.h> 39 #include <linux/clk.h> 40 #include <linux/regmap.h> 41 #include <linux/mfd/syscon.h> 42 #include <dt-bindings/pinctrl/rockchip.h> 43 44 #include "core.h" 45 #include "pinconf.h" 46 47 /* GPIO control registers */ 48 #define GPIO_SWPORT_DR 0x00 49 #define GPIO_SWPORT_DDR 0x04 50 #define GPIO_INTEN 0x30 51 #define GPIO_INTMASK 0x34 52 #define GPIO_INTTYPE_LEVEL 0x38 53 #define GPIO_INT_POLARITY 0x3c 54 #define GPIO_INT_STATUS 0x40 55 #define GPIO_INT_RAWSTATUS 0x44 56 #define GPIO_DEBOUNCE 0x48 57 #define GPIO_PORTS_EOI 0x4c 58 #define GPIO_EXT_PORT 0x50 59 #define GPIO_LS_SYNC 0x60 60 61 enum rockchip_pinctrl_type { 62 PX30, 63 RV1108, 64 RK2928, 65 RK3066B, 66 RK3128, 67 RK3188, 68 RK3288, 69 RK3368, 70 RK3399, 71 }; 72 73 /** 74 * Encode variants of iomux registers into a type variable 75 */ 76 #define IOMUX_GPIO_ONLY BIT(0) 77 #define IOMUX_WIDTH_4BIT BIT(1) 78 #define IOMUX_SOURCE_PMU BIT(2) 79 #define IOMUX_UNROUTED BIT(3) 80 #define IOMUX_WIDTH_3BIT BIT(4) 81 82 /** 83 * @type: iomux variant using IOMUX_* constants 84 * @offset: if initialized to -1 it will be autocalculated, by specifying 85 * an initial offset value the relevant source offset can be reset 86 * to a new value for autocalculating the following iomux registers. 87 */ 88 struct rockchip_iomux { 89 int type; 90 int offset; 91 }; 92 93 /** 94 * enum type index corresponding to rockchip_perpin_drv_list arrays index. 95 */ 96 enum rockchip_pin_drv_type { 97 DRV_TYPE_IO_DEFAULT = 0, 98 DRV_TYPE_IO_1V8_OR_3V0, 99 DRV_TYPE_IO_1V8_ONLY, 100 DRV_TYPE_IO_1V8_3V0_AUTO, 101 DRV_TYPE_IO_3V3_ONLY, 102 DRV_TYPE_MAX 103 }; 104 105 /** 106 * enum type index corresponding to rockchip_pull_list arrays index. 107 */ 108 enum rockchip_pin_pull_type { 109 PULL_TYPE_IO_DEFAULT = 0, 110 PULL_TYPE_IO_1V8_ONLY, 111 PULL_TYPE_MAX 112 }; 113 114 /** 115 * @drv_type: drive strength variant using rockchip_perpin_drv_type 116 * @offset: if initialized to -1 it will be autocalculated, by specifying 117 * an initial offset value the relevant source offset can be reset 118 * to a new value for autocalculating the following drive strength 119 * registers. if used chips own cal_drv func instead to calculate 120 * registers offset, the variant could be ignored. 121 */ 122 struct rockchip_drv { 123 enum rockchip_pin_drv_type drv_type; 124 int offset; 125 }; 126 127 /** 128 * @reg_base: register base of the gpio bank 129 * @reg_pull: optional separate register for additional pull settings 130 * @clk: clock of the gpio bank 131 * @irq: interrupt of the gpio bank 132 * @saved_masks: Saved content of GPIO_INTEN at suspend time. 133 * @pin_base: first pin number 134 * @nr_pins: number of pins in this bank 135 * @name: name of the bank 136 * @bank_num: number of the bank, to account for holes 137 * @iomux: array describing the 4 iomux sources of the bank 138 * @drv: array describing the 4 drive strength sources of the bank 139 * @pull_type: array describing the 4 pull type sources of the bank 140 * @valid: is all necessary information present 141 * @of_node: dt node of this bank 142 * @drvdata: common pinctrl basedata 143 * @domain: irqdomain of the gpio bank 144 * @gpio_chip: gpiolib chip 145 * @grange: gpio range 146 * @slock: spinlock for the gpio bank 147 * @route_mask: bits describing the routing pins of per bank 148 */ 149 struct rockchip_pin_bank { 150 void __iomem *reg_base; 151 struct regmap *regmap_pull; 152 struct clk *clk; 153 int irq; 154 u32 saved_masks; 155 u32 pin_base; 156 u8 nr_pins; 157 char *name; 158 u8 bank_num; 159 struct rockchip_iomux iomux[4]; 160 struct rockchip_drv drv[4]; 161 enum rockchip_pin_pull_type pull_type[4]; 162 bool valid; 163 struct device_node *of_node; 164 struct rockchip_pinctrl *drvdata; 165 struct irq_domain *domain; 166 struct gpio_chip gpio_chip; 167 struct pinctrl_gpio_range grange; 168 raw_spinlock_t slock; 169 u32 toggle_edge_mode; 170 u32 recalced_mask; 171 u32 route_mask; 172 }; 173 174 #define PIN_BANK(id, pins, label) \ 175 { \ 176 .bank_num = id, \ 177 .nr_pins = pins, \ 178 .name = label, \ 179 .iomux = { \ 180 { .offset = -1 }, \ 181 { .offset = -1 }, \ 182 { .offset = -1 }, \ 183 { .offset = -1 }, \ 184 }, \ 185 } 186 187 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \ 188 { \ 189 .bank_num = id, \ 190 .nr_pins = pins, \ 191 .name = label, \ 192 .iomux = { \ 193 { .type = iom0, .offset = -1 }, \ 194 { .type = iom1, .offset = -1 }, \ 195 { .type = iom2, .offset = -1 }, \ 196 { .type = iom3, .offset = -1 }, \ 197 }, \ 198 } 199 200 #define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \ 201 { \ 202 .bank_num = id, \ 203 .nr_pins = pins, \ 204 .name = label, \ 205 .iomux = { \ 206 { .offset = -1 }, \ 207 { .offset = -1 }, \ 208 { .offset = -1 }, \ 209 { .offset = -1 }, \ 210 }, \ 211 .drv = { \ 212 { .drv_type = type0, .offset = -1 }, \ 213 { .drv_type = type1, .offset = -1 }, \ 214 { .drv_type = type2, .offset = -1 }, \ 215 { .drv_type = type3, .offset = -1 }, \ 216 }, \ 217 } 218 219 #define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1, \ 220 drv2, drv3, pull0, pull1, \ 221 pull2, pull3) \ 222 { \ 223 .bank_num = id, \ 224 .nr_pins = pins, \ 225 .name = label, \ 226 .iomux = { \ 227 { .offset = -1 }, \ 228 { .offset = -1 }, \ 229 { .offset = -1 }, \ 230 { .offset = -1 }, \ 231 }, \ 232 .drv = { \ 233 { .drv_type = drv0, .offset = -1 }, \ 234 { .drv_type = drv1, .offset = -1 }, \ 235 { .drv_type = drv2, .offset = -1 }, \ 236 { .drv_type = drv3, .offset = -1 }, \ 237 }, \ 238 .pull_type[0] = pull0, \ 239 .pull_type[1] = pull1, \ 240 .pull_type[2] = pull2, \ 241 .pull_type[3] = pull3, \ 242 } 243 244 #define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1, \ 245 iom2, iom3, drv0, drv1, drv2, \ 246 drv3, offset0, offset1, \ 247 offset2, offset3) \ 248 { \ 249 .bank_num = id, \ 250 .nr_pins = pins, \ 251 .name = label, \ 252 .iomux = { \ 253 { .type = iom0, .offset = -1 }, \ 254 { .type = iom1, .offset = -1 }, \ 255 { .type = iom2, .offset = -1 }, \ 256 { .type = iom3, .offset = -1 }, \ 257 }, \ 258 .drv = { \ 259 { .drv_type = drv0, .offset = offset0 }, \ 260 { .drv_type = drv1, .offset = offset1 }, \ 261 { .drv_type = drv2, .offset = offset2 }, \ 262 { .drv_type = drv3, .offset = offset3 }, \ 263 }, \ 264 } 265 266 #define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins, \ 267 label, iom0, iom1, iom2, \ 268 iom3, drv0, drv1, drv2, \ 269 drv3, offset0, offset1, \ 270 offset2, offset3, pull0, \ 271 pull1, pull2, pull3) \ 272 { \ 273 .bank_num = id, \ 274 .nr_pins = pins, \ 275 .name = label, \ 276 .iomux = { \ 277 { .type = iom0, .offset = -1 }, \ 278 { .type = iom1, .offset = -1 }, \ 279 { .type = iom2, .offset = -1 }, \ 280 { .type = iom3, .offset = -1 }, \ 281 }, \ 282 .drv = { \ 283 { .drv_type = drv0, .offset = offset0 }, \ 284 { .drv_type = drv1, .offset = offset1 }, \ 285 { .drv_type = drv2, .offset = offset2 }, \ 286 { .drv_type = drv3, .offset = offset3 }, \ 287 }, \ 288 .pull_type[0] = pull0, \ 289 .pull_type[1] = pull1, \ 290 .pull_type[2] = pull2, \ 291 .pull_type[3] = pull3, \ 292 } 293 294 /** 295 * struct rockchip_mux_recalced_data: represent a pin iomux data. 296 * @num: bank number. 297 * @pin: pin number. 298 * @bit: index at register. 299 * @reg: register offset. 300 * @mask: mask bit 301 */ 302 struct rockchip_mux_recalced_data { 303 u8 num; 304 u8 pin; 305 u32 reg; 306 u8 bit; 307 u8 mask; 308 }; 309 310 enum rockchip_mux_route_location { 311 ROCKCHIP_ROUTE_SAME = 0, 312 ROCKCHIP_ROUTE_PMU, 313 ROCKCHIP_ROUTE_GRF, 314 }; 315 316 /** 317 * struct rockchip_mux_recalced_data: represent a pin iomux data. 318 * @bank_num: bank number. 319 * @pin: index at register or used to calc index. 320 * @func: the min pin. 321 * @route_offset: the max pin. 322 * @route_val: the register offset. 323 */ 324 struct rockchip_mux_route_data { 325 u8 bank_num; 326 u8 pin; 327 u8 func; 328 enum rockchip_mux_route_location route_location; 329 u32 route_offset; 330 u32 route_val; 331 }; 332 333 /** 334 */ 335 struct rockchip_pin_ctrl { 336 struct rockchip_pin_bank *pin_banks; 337 u32 nr_banks; 338 u32 nr_pins; 339 char *label; 340 enum rockchip_pinctrl_type type; 341 int grf_mux_offset; 342 int pmu_mux_offset; 343 int grf_drv_offset; 344 int pmu_drv_offset; 345 struct rockchip_mux_recalced_data *iomux_recalced; 346 u32 niomux_recalced; 347 struct rockchip_mux_route_data *iomux_routes; 348 u32 niomux_routes; 349 350 void (*pull_calc_reg)(struct rockchip_pin_bank *bank, 351 int pin_num, struct regmap **regmap, 352 int *reg, u8 *bit); 353 void (*drv_calc_reg)(struct rockchip_pin_bank *bank, 354 int pin_num, struct regmap **regmap, 355 int *reg, u8 *bit); 356 int (*schmitt_calc_reg)(struct rockchip_pin_bank *bank, 357 int pin_num, struct regmap **regmap, 358 int *reg, u8 *bit); 359 }; 360 361 struct rockchip_pin_config { 362 unsigned int func; 363 unsigned long *configs; 364 unsigned int nconfigs; 365 }; 366 367 /** 368 * struct rockchip_pin_group: represent group of pins of a pinmux function. 369 * @name: name of the pin group, used to lookup the group. 370 * @pins: the pins included in this group. 371 * @npins: number of pins included in this group. 372 * @func: the mux function number to be programmed when selected. 373 * @configs: the config values to be set for each pin 374 * @nconfigs: number of configs for each pin 375 */ 376 struct rockchip_pin_group { 377 const char *name; 378 unsigned int npins; 379 unsigned int *pins; 380 struct rockchip_pin_config *data; 381 }; 382 383 /** 384 * struct rockchip_pmx_func: represent a pin function. 385 * @name: name of the pin function, used to lookup the function. 386 * @groups: one or more names of pin groups that provide this function. 387 * @num_groups: number of groups included in @groups. 388 */ 389 struct rockchip_pmx_func { 390 const char *name; 391 const char **groups; 392 u8 ngroups; 393 }; 394 395 struct rockchip_pinctrl { 396 struct regmap *regmap_base; 397 int reg_size; 398 struct regmap *regmap_pull; 399 struct regmap *regmap_pmu; 400 struct device *dev; 401 struct rockchip_pin_ctrl *ctrl; 402 struct pinctrl_desc pctl; 403 struct pinctrl_dev *pctl_dev; 404 struct rockchip_pin_group *groups; 405 unsigned int ngroups; 406 struct rockchip_pmx_func *functions; 407 unsigned int nfunctions; 408 }; 409 410 static struct regmap_config rockchip_regmap_config = { 411 .reg_bits = 32, 412 .val_bits = 32, 413 .reg_stride = 4, 414 }; 415 416 static inline const struct rockchip_pin_group *pinctrl_name_to_group( 417 const struct rockchip_pinctrl *info, 418 const char *name) 419 { 420 int i; 421 422 for (i = 0; i < info->ngroups; i++) { 423 if (!strcmp(info->groups[i].name, name)) 424 return &info->groups[i]; 425 } 426 427 return NULL; 428 } 429 430 /* 431 * given a pin number that is local to a pin controller, find out the pin bank 432 * and the register base of the pin bank. 433 */ 434 static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info, 435 unsigned pin) 436 { 437 struct rockchip_pin_bank *b = info->ctrl->pin_banks; 438 439 while (pin >= (b->pin_base + b->nr_pins)) 440 b++; 441 442 return b; 443 } 444 445 static struct rockchip_pin_bank *bank_num_to_bank( 446 struct rockchip_pinctrl *info, 447 unsigned num) 448 { 449 struct rockchip_pin_bank *b = info->ctrl->pin_banks; 450 int i; 451 452 for (i = 0; i < info->ctrl->nr_banks; i++, b++) { 453 if (b->bank_num == num) 454 return b; 455 } 456 457 return ERR_PTR(-EINVAL); 458 } 459 460 /* 461 * Pinctrl_ops handling 462 */ 463 464 static int rockchip_get_groups_count(struct pinctrl_dev *pctldev) 465 { 466 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 467 468 return info->ngroups; 469 } 470 471 static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev, 472 unsigned selector) 473 { 474 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 475 476 return info->groups[selector].name; 477 } 478 479 static int rockchip_get_group_pins(struct pinctrl_dev *pctldev, 480 unsigned selector, const unsigned **pins, 481 unsigned *npins) 482 { 483 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 484 485 if (selector >= info->ngroups) 486 return -EINVAL; 487 488 *pins = info->groups[selector].pins; 489 *npins = info->groups[selector].npins; 490 491 return 0; 492 } 493 494 static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev, 495 struct device_node *np, 496 struct pinctrl_map **map, unsigned *num_maps) 497 { 498 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 499 const struct rockchip_pin_group *grp; 500 struct pinctrl_map *new_map; 501 struct device_node *parent; 502 int map_num = 1; 503 int i; 504 505 /* 506 * first find the group of this node and check if we need to create 507 * config maps for pins 508 */ 509 grp = pinctrl_name_to_group(info, np->name); 510 if (!grp) { 511 dev_err(info->dev, "unable to find group for node %pOFn\n", 512 np); 513 return -EINVAL; 514 } 515 516 map_num += grp->npins; 517 new_map = devm_kcalloc(pctldev->dev, map_num, sizeof(*new_map), 518 GFP_KERNEL); 519 if (!new_map) 520 return -ENOMEM; 521 522 *map = new_map; 523 *num_maps = map_num; 524 525 /* create mux map */ 526 parent = of_get_parent(np); 527 if (!parent) { 528 devm_kfree(pctldev->dev, new_map); 529 return -EINVAL; 530 } 531 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP; 532 new_map[0].data.mux.function = parent->name; 533 new_map[0].data.mux.group = np->name; 534 of_node_put(parent); 535 536 /* create config map */ 537 new_map++; 538 for (i = 0; i < grp->npins; i++) { 539 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN; 540 new_map[i].data.configs.group_or_pin = 541 pin_get_name(pctldev, grp->pins[i]); 542 new_map[i].data.configs.configs = grp->data[i].configs; 543 new_map[i].data.configs.num_configs = grp->data[i].nconfigs; 544 } 545 546 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n", 547 (*map)->data.mux.function, (*map)->data.mux.group, map_num); 548 549 return 0; 550 } 551 552 static void rockchip_dt_free_map(struct pinctrl_dev *pctldev, 553 struct pinctrl_map *map, unsigned num_maps) 554 { 555 } 556 557 static const struct pinctrl_ops rockchip_pctrl_ops = { 558 .get_groups_count = rockchip_get_groups_count, 559 .get_group_name = rockchip_get_group_name, 560 .get_group_pins = rockchip_get_group_pins, 561 .dt_node_to_map = rockchip_dt_node_to_map, 562 .dt_free_map = rockchip_dt_free_map, 563 }; 564 565 /* 566 * Hardware access 567 */ 568 569 static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = { 570 { 571 .num = 1, 572 .pin = 0, 573 .reg = 0x418, 574 .bit = 0, 575 .mask = 0x3 576 }, { 577 .num = 1, 578 .pin = 1, 579 .reg = 0x418, 580 .bit = 2, 581 .mask = 0x3 582 }, { 583 .num = 1, 584 .pin = 2, 585 .reg = 0x418, 586 .bit = 4, 587 .mask = 0x3 588 }, { 589 .num = 1, 590 .pin = 3, 591 .reg = 0x418, 592 .bit = 6, 593 .mask = 0x3 594 }, { 595 .num = 1, 596 .pin = 4, 597 .reg = 0x418, 598 .bit = 8, 599 .mask = 0x3 600 }, { 601 .num = 1, 602 .pin = 5, 603 .reg = 0x418, 604 .bit = 10, 605 .mask = 0x3 606 }, { 607 .num = 1, 608 .pin = 6, 609 .reg = 0x418, 610 .bit = 12, 611 .mask = 0x3 612 }, { 613 .num = 1, 614 .pin = 7, 615 .reg = 0x418, 616 .bit = 14, 617 .mask = 0x3 618 }, { 619 .num = 1, 620 .pin = 8, 621 .reg = 0x41c, 622 .bit = 0, 623 .mask = 0x3 624 }, { 625 .num = 1, 626 .pin = 9, 627 .reg = 0x41c, 628 .bit = 2, 629 .mask = 0x3 630 }, 631 }; 632 633 static struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = { 634 { 635 .num = 2, 636 .pin = 20, 637 .reg = 0xe8, 638 .bit = 0, 639 .mask = 0x7 640 }, { 641 .num = 2, 642 .pin = 21, 643 .reg = 0xe8, 644 .bit = 4, 645 .mask = 0x7 646 }, { 647 .num = 2, 648 .pin = 22, 649 .reg = 0xe8, 650 .bit = 8, 651 .mask = 0x7 652 }, { 653 .num = 2, 654 .pin = 23, 655 .reg = 0xe8, 656 .bit = 12, 657 .mask = 0x7 658 }, { 659 .num = 2, 660 .pin = 24, 661 .reg = 0xd4, 662 .bit = 12, 663 .mask = 0x7 664 }, 665 }; 666 667 static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = { 668 { 669 .num = 2, 670 .pin = 12, 671 .reg = 0x24, 672 .bit = 8, 673 .mask = 0x3 674 }, { 675 .num = 2, 676 .pin = 15, 677 .reg = 0x28, 678 .bit = 0, 679 .mask = 0x7 680 }, { 681 .num = 2, 682 .pin = 23, 683 .reg = 0x30, 684 .bit = 14, 685 .mask = 0x3 686 }, 687 }; 688 689 static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin, 690 int *reg, u8 *bit, int *mask) 691 { 692 struct rockchip_pinctrl *info = bank->drvdata; 693 struct rockchip_pin_ctrl *ctrl = info->ctrl; 694 struct rockchip_mux_recalced_data *data; 695 int i; 696 697 for (i = 0; i < ctrl->niomux_recalced; i++) { 698 data = &ctrl->iomux_recalced[i]; 699 if (data->num == bank->bank_num && 700 data->pin == pin) 701 break; 702 } 703 704 if (i >= ctrl->niomux_recalced) 705 return; 706 707 *reg = data->reg; 708 *mask = data->mask; 709 *bit = data->bit; 710 } 711 712 static struct rockchip_mux_route_data px30_mux_route_data[] = { 713 { 714 /* cif-d2m0 */ 715 .bank_num = 2, 716 .pin = 0, 717 .func = 1, 718 .route_offset = 0x184, 719 .route_val = BIT(16 + 7), 720 }, { 721 /* cif-d2m1 */ 722 .bank_num = 3, 723 .pin = 3, 724 .func = 3, 725 .route_offset = 0x184, 726 .route_val = BIT(16 + 7) | BIT(7), 727 }, { 728 /* pdm-m0 */ 729 .bank_num = 3, 730 .pin = 22, 731 .func = 2, 732 .route_offset = 0x184, 733 .route_val = BIT(16 + 8), 734 }, { 735 /* pdm-m1 */ 736 .bank_num = 2, 737 .pin = 22, 738 .func = 1, 739 .route_offset = 0x184, 740 .route_val = BIT(16 + 8) | BIT(8), 741 }, { 742 /* uart2-rxm0 */ 743 .bank_num = 1, 744 .pin = 27, 745 .func = 2, 746 .route_offset = 0x184, 747 .route_val = BIT(16 + 10), 748 }, { 749 /* uart2-rxm1 */ 750 .bank_num = 2, 751 .pin = 14, 752 .func = 2, 753 .route_offset = 0x184, 754 .route_val = BIT(16 + 10) | BIT(10), 755 }, { 756 /* uart3-rxm0 */ 757 .bank_num = 0, 758 .pin = 17, 759 .func = 2, 760 .route_offset = 0x184, 761 .route_val = BIT(16 + 9), 762 }, { 763 /* uart3-rxm1 */ 764 .bank_num = 1, 765 .pin = 15, 766 .func = 2, 767 .route_offset = 0x184, 768 .route_val = BIT(16 + 9) | BIT(9), 769 }, 770 }; 771 772 static struct rockchip_mux_route_data rk3128_mux_route_data[] = { 773 { 774 /* spi-0 */ 775 .bank_num = 1, 776 .pin = 10, 777 .func = 1, 778 .route_offset = 0x144, 779 .route_val = BIT(16 + 3) | BIT(16 + 4), 780 }, { 781 /* spi-1 */ 782 .bank_num = 1, 783 .pin = 27, 784 .func = 3, 785 .route_offset = 0x144, 786 .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(3), 787 }, { 788 /* spi-2 */ 789 .bank_num = 0, 790 .pin = 13, 791 .func = 2, 792 .route_offset = 0x144, 793 .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(4), 794 }, { 795 /* i2s-0 */ 796 .bank_num = 1, 797 .pin = 5, 798 .func = 1, 799 .route_offset = 0x144, 800 .route_val = BIT(16 + 5), 801 }, { 802 /* i2s-1 */ 803 .bank_num = 0, 804 .pin = 14, 805 .func = 1, 806 .route_offset = 0x144, 807 .route_val = BIT(16 + 5) | BIT(5), 808 }, { 809 /* emmc-0 */ 810 .bank_num = 1, 811 .pin = 22, 812 .func = 2, 813 .route_offset = 0x144, 814 .route_val = BIT(16 + 6), 815 }, { 816 /* emmc-1 */ 817 .bank_num = 2, 818 .pin = 4, 819 .func = 2, 820 .route_offset = 0x144, 821 .route_val = BIT(16 + 6) | BIT(6), 822 }, 823 }; 824 825 static struct rockchip_mux_route_data rk3188_mux_route_data[] = { 826 { 827 /* non-iomuxed emmc/flash pins on flash-dqs */ 828 .bank_num = 0, 829 .pin = 24, 830 .func = 1, 831 .route_location = ROCKCHIP_ROUTE_GRF, 832 .route_offset = 0xa0, 833 .route_val = BIT(16 + 11), 834 }, { 835 /* non-iomuxed emmc/flash pins on emmc-clk */ 836 .bank_num = 0, 837 .pin = 24, 838 .func = 2, 839 .route_location = ROCKCHIP_ROUTE_GRF, 840 .route_offset = 0xa0, 841 .route_val = BIT(16 + 11) | BIT(11), 842 }, 843 }; 844 845 static struct rockchip_mux_route_data rk3228_mux_route_data[] = { 846 { 847 /* pwm0-0 */ 848 .bank_num = 0, 849 .pin = 26, 850 .func = 1, 851 .route_offset = 0x50, 852 .route_val = BIT(16), 853 }, { 854 /* pwm0-1 */ 855 .bank_num = 3, 856 .pin = 21, 857 .func = 1, 858 .route_offset = 0x50, 859 .route_val = BIT(16) | BIT(0), 860 }, { 861 /* pwm1-0 */ 862 .bank_num = 0, 863 .pin = 27, 864 .func = 1, 865 .route_offset = 0x50, 866 .route_val = BIT(16 + 1), 867 }, { 868 /* pwm1-1 */ 869 .bank_num = 0, 870 .pin = 30, 871 .func = 2, 872 .route_offset = 0x50, 873 .route_val = BIT(16 + 1) | BIT(1), 874 }, { 875 /* pwm2-0 */ 876 .bank_num = 0, 877 .pin = 28, 878 .func = 1, 879 .route_offset = 0x50, 880 .route_val = BIT(16 + 2), 881 }, { 882 /* pwm2-1 */ 883 .bank_num = 1, 884 .pin = 12, 885 .func = 2, 886 .route_offset = 0x50, 887 .route_val = BIT(16 + 2) | BIT(2), 888 }, { 889 /* pwm3-0 */ 890 .bank_num = 3, 891 .pin = 26, 892 .func = 1, 893 .route_offset = 0x50, 894 .route_val = BIT(16 + 3), 895 }, { 896 /* pwm3-1 */ 897 .bank_num = 1, 898 .pin = 11, 899 .func = 2, 900 .route_offset = 0x50, 901 .route_val = BIT(16 + 3) | BIT(3), 902 }, { 903 /* sdio-0_d0 */ 904 .bank_num = 1, 905 .pin = 1, 906 .func = 1, 907 .route_offset = 0x50, 908 .route_val = BIT(16 + 4), 909 }, { 910 /* sdio-1_d0 */ 911 .bank_num = 3, 912 .pin = 2, 913 .func = 1, 914 .route_offset = 0x50, 915 .route_val = BIT(16 + 4) | BIT(4), 916 }, { 917 /* spi-0_rx */ 918 .bank_num = 0, 919 .pin = 13, 920 .func = 2, 921 .route_offset = 0x50, 922 .route_val = BIT(16 + 5), 923 }, { 924 /* spi-1_rx */ 925 .bank_num = 2, 926 .pin = 0, 927 .func = 2, 928 .route_offset = 0x50, 929 .route_val = BIT(16 + 5) | BIT(5), 930 }, { 931 /* emmc-0_cmd */ 932 .bank_num = 1, 933 .pin = 22, 934 .func = 2, 935 .route_offset = 0x50, 936 .route_val = BIT(16 + 7), 937 }, { 938 /* emmc-1_cmd */ 939 .bank_num = 2, 940 .pin = 4, 941 .func = 2, 942 .route_offset = 0x50, 943 .route_val = BIT(16 + 7) | BIT(7), 944 }, { 945 /* uart2-0_rx */ 946 .bank_num = 1, 947 .pin = 19, 948 .func = 2, 949 .route_offset = 0x50, 950 .route_val = BIT(16 + 8), 951 }, { 952 /* uart2-1_rx */ 953 .bank_num = 1, 954 .pin = 10, 955 .func = 2, 956 .route_offset = 0x50, 957 .route_val = BIT(16 + 8) | BIT(8), 958 }, { 959 /* uart1-0_rx */ 960 .bank_num = 1, 961 .pin = 10, 962 .func = 1, 963 .route_offset = 0x50, 964 .route_val = BIT(16 + 11), 965 }, { 966 /* uart1-1_rx */ 967 .bank_num = 3, 968 .pin = 13, 969 .func = 1, 970 .route_offset = 0x50, 971 .route_val = BIT(16 + 11) | BIT(11), 972 }, 973 }; 974 975 static struct rockchip_mux_route_data rk3288_mux_route_data[] = { 976 { 977 /* edphdmi_cecinoutt1 */ 978 .bank_num = 7, 979 .pin = 16, 980 .func = 2, 981 .route_offset = 0x264, 982 .route_val = BIT(16 + 12) | BIT(12), 983 }, { 984 /* edphdmi_cecinout */ 985 .bank_num = 7, 986 .pin = 23, 987 .func = 4, 988 .route_offset = 0x264, 989 .route_val = BIT(16 + 12), 990 }, 991 }; 992 993 static struct rockchip_mux_route_data rk3328_mux_route_data[] = { 994 { 995 /* uart2dbg_rxm0 */ 996 .bank_num = 1, 997 .pin = 1, 998 .func = 2, 999 .route_offset = 0x50, 1000 .route_val = BIT(16) | BIT(16 + 1), 1001 }, { 1002 /* uart2dbg_rxm1 */ 1003 .bank_num = 2, 1004 .pin = 1, 1005 .func = 1, 1006 .route_offset = 0x50, 1007 .route_val = BIT(16) | BIT(16 + 1) | BIT(0), 1008 }, { 1009 /* gmac-m1_rxd0 */ 1010 .bank_num = 1, 1011 .pin = 11, 1012 .func = 2, 1013 .route_offset = 0x50, 1014 .route_val = BIT(16 + 2) | BIT(2), 1015 }, { 1016 /* gmac-m1-optimized_rxd3 */ 1017 .bank_num = 1, 1018 .pin = 14, 1019 .func = 2, 1020 .route_offset = 0x50, 1021 .route_val = BIT(16 + 10) | BIT(10), 1022 }, { 1023 /* pdm_sdi0m0 */ 1024 .bank_num = 2, 1025 .pin = 19, 1026 .func = 2, 1027 .route_offset = 0x50, 1028 .route_val = BIT(16 + 3), 1029 }, { 1030 /* pdm_sdi0m1 */ 1031 .bank_num = 1, 1032 .pin = 23, 1033 .func = 3, 1034 .route_offset = 0x50, 1035 .route_val = BIT(16 + 3) | BIT(3), 1036 }, { 1037 /* spi_rxdm2 */ 1038 .bank_num = 3, 1039 .pin = 2, 1040 .func = 4, 1041 .route_offset = 0x50, 1042 .route_val = BIT(16 + 4) | BIT(16 + 5) | BIT(5), 1043 }, { 1044 /* i2s2_sdim0 */ 1045 .bank_num = 1, 1046 .pin = 24, 1047 .func = 1, 1048 .route_offset = 0x50, 1049 .route_val = BIT(16 + 6), 1050 }, { 1051 /* i2s2_sdim1 */ 1052 .bank_num = 3, 1053 .pin = 2, 1054 .func = 6, 1055 .route_offset = 0x50, 1056 .route_val = BIT(16 + 6) | BIT(6), 1057 }, { 1058 /* card_iom1 */ 1059 .bank_num = 2, 1060 .pin = 22, 1061 .func = 3, 1062 .route_offset = 0x50, 1063 .route_val = BIT(16 + 7) | BIT(7), 1064 }, { 1065 /* tsp_d5m1 */ 1066 .bank_num = 2, 1067 .pin = 16, 1068 .func = 3, 1069 .route_offset = 0x50, 1070 .route_val = BIT(16 + 8) | BIT(8), 1071 }, { 1072 /* cif_data5m1 */ 1073 .bank_num = 2, 1074 .pin = 16, 1075 .func = 4, 1076 .route_offset = 0x50, 1077 .route_val = BIT(16 + 9) | BIT(9), 1078 }, 1079 }; 1080 1081 static struct rockchip_mux_route_data rk3399_mux_route_data[] = { 1082 { 1083 /* uart2dbga_rx */ 1084 .bank_num = 4, 1085 .pin = 8, 1086 .func = 2, 1087 .route_offset = 0xe21c, 1088 .route_val = BIT(16 + 10) | BIT(16 + 11), 1089 }, { 1090 /* uart2dbgb_rx */ 1091 .bank_num = 4, 1092 .pin = 16, 1093 .func = 2, 1094 .route_offset = 0xe21c, 1095 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10), 1096 }, { 1097 /* uart2dbgc_rx */ 1098 .bank_num = 4, 1099 .pin = 19, 1100 .func = 1, 1101 .route_offset = 0xe21c, 1102 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11), 1103 }, { 1104 /* pcie_clkreqn */ 1105 .bank_num = 2, 1106 .pin = 26, 1107 .func = 2, 1108 .route_offset = 0xe21c, 1109 .route_val = BIT(16 + 14), 1110 }, { 1111 /* pcie_clkreqnb */ 1112 .bank_num = 4, 1113 .pin = 24, 1114 .func = 1, 1115 .route_offset = 0xe21c, 1116 .route_val = BIT(16 + 14) | BIT(14), 1117 }, 1118 }; 1119 1120 static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin, 1121 int mux, u32 *loc, u32 *reg, u32 *value) 1122 { 1123 struct rockchip_pinctrl *info = bank->drvdata; 1124 struct rockchip_pin_ctrl *ctrl = info->ctrl; 1125 struct rockchip_mux_route_data *data; 1126 int i; 1127 1128 for (i = 0; i < ctrl->niomux_routes; i++) { 1129 data = &ctrl->iomux_routes[i]; 1130 if ((data->bank_num == bank->bank_num) && 1131 (data->pin == pin) && (data->func == mux)) 1132 break; 1133 } 1134 1135 if (i >= ctrl->niomux_routes) 1136 return false; 1137 1138 *loc = data->route_location; 1139 *reg = data->route_offset; 1140 *value = data->route_val; 1141 1142 return true; 1143 } 1144 1145 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) 1146 { 1147 struct rockchip_pinctrl *info = bank->drvdata; 1148 int iomux_num = (pin / 8); 1149 struct regmap *regmap; 1150 unsigned int val; 1151 int reg, ret, mask, mux_type; 1152 u8 bit; 1153 1154 if (iomux_num > 3) 1155 return -EINVAL; 1156 1157 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { 1158 dev_err(info->dev, "pin %d is unrouted\n", pin); 1159 return -EINVAL; 1160 } 1161 1162 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) 1163 return RK_FUNC_GPIO; 1164 1165 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) 1166 ? info->regmap_pmu : info->regmap_base; 1167 1168 /* get basic quadrupel of mux registers and the correct reg inside */ 1169 mux_type = bank->iomux[iomux_num].type; 1170 reg = bank->iomux[iomux_num].offset; 1171 if (mux_type & IOMUX_WIDTH_4BIT) { 1172 if ((pin % 8) >= 4) 1173 reg += 0x4; 1174 bit = (pin % 4) * 4; 1175 mask = 0xf; 1176 } else if (mux_type & IOMUX_WIDTH_3BIT) { 1177 if ((pin % 8) >= 5) 1178 reg += 0x4; 1179 bit = (pin % 8 % 5) * 3; 1180 mask = 0x7; 1181 } else { 1182 bit = (pin % 8) * 2; 1183 mask = 0x3; 1184 } 1185 1186 if (bank->recalced_mask & BIT(pin)) 1187 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); 1188 1189 ret = regmap_read(regmap, reg, &val); 1190 if (ret) 1191 return ret; 1192 1193 return ((val >> bit) & mask); 1194 } 1195 1196 static int rockchip_verify_mux(struct rockchip_pin_bank *bank, 1197 int pin, int mux) 1198 { 1199 struct rockchip_pinctrl *info = bank->drvdata; 1200 int iomux_num = (pin / 8); 1201 1202 if (iomux_num > 3) 1203 return -EINVAL; 1204 1205 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { 1206 dev_err(info->dev, "pin %d is unrouted\n", pin); 1207 return -EINVAL; 1208 } 1209 1210 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) { 1211 if (mux != RK_FUNC_GPIO) { 1212 dev_err(info->dev, 1213 "pin %d only supports a gpio mux\n", pin); 1214 return -ENOTSUPP; 1215 } 1216 } 1217 1218 return 0; 1219 } 1220 1221 /* 1222 * Set a new mux function for a pin. 1223 * 1224 * The register is divided into the upper and lower 16 bit. When changing 1225 * a value, the previous register value is not read and changed. Instead 1226 * it seems the changed bits are marked in the upper 16 bit, while the 1227 * changed value gets set in the same offset in the lower 16 bit. 1228 * All pin settings seem to be 2 bit wide in both the upper and lower 1229 * parts. 1230 * @bank: pin bank to change 1231 * @pin: pin to change 1232 * @mux: new mux function to set 1233 */ 1234 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) 1235 { 1236 struct rockchip_pinctrl *info = bank->drvdata; 1237 int iomux_num = (pin / 8); 1238 struct regmap *regmap; 1239 int reg, ret, mask, mux_type; 1240 u8 bit; 1241 u32 data, rmask, route_location, route_reg, route_val; 1242 1243 ret = rockchip_verify_mux(bank, pin, mux); 1244 if (ret < 0) 1245 return ret; 1246 1247 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) 1248 return 0; 1249 1250 dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n", 1251 bank->bank_num, pin, mux); 1252 1253 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) 1254 ? info->regmap_pmu : info->regmap_base; 1255 1256 /* get basic quadrupel of mux registers and the correct reg inside */ 1257 mux_type = bank->iomux[iomux_num].type; 1258 reg = bank->iomux[iomux_num].offset; 1259 if (mux_type & IOMUX_WIDTH_4BIT) { 1260 if ((pin % 8) >= 4) 1261 reg += 0x4; 1262 bit = (pin % 4) * 4; 1263 mask = 0xf; 1264 } else if (mux_type & IOMUX_WIDTH_3BIT) { 1265 if ((pin % 8) >= 5) 1266 reg += 0x4; 1267 bit = (pin % 8 % 5) * 3; 1268 mask = 0x7; 1269 } else { 1270 bit = (pin % 8) * 2; 1271 mask = 0x3; 1272 } 1273 1274 if (bank->recalced_mask & BIT(pin)) 1275 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); 1276 1277 if (bank->route_mask & BIT(pin)) { 1278 if (rockchip_get_mux_route(bank, pin, mux, &route_location, 1279 &route_reg, &route_val)) { 1280 struct regmap *route_regmap = regmap; 1281 1282 /* handle special locations */ 1283 switch (route_location) { 1284 case ROCKCHIP_ROUTE_PMU: 1285 route_regmap = info->regmap_pmu; 1286 break; 1287 case ROCKCHIP_ROUTE_GRF: 1288 route_regmap = info->regmap_base; 1289 break; 1290 } 1291 1292 ret = regmap_write(route_regmap, route_reg, route_val); 1293 if (ret) 1294 return ret; 1295 } 1296 } 1297 1298 data = (mask << (bit + 16)); 1299 rmask = data | (data >> 16); 1300 data |= (mux & mask) << bit; 1301 ret = regmap_update_bits(regmap, reg, rmask, data); 1302 1303 return ret; 1304 } 1305 1306 #define PX30_PULL_PMU_OFFSET 0x10 1307 #define PX30_PULL_GRF_OFFSET 0x60 1308 #define PX30_PULL_BITS_PER_PIN 2 1309 #define PX30_PULL_PINS_PER_REG 8 1310 #define PX30_PULL_BANK_STRIDE 16 1311 1312 static void px30_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1313 int pin_num, struct regmap **regmap, 1314 int *reg, u8 *bit) 1315 { 1316 struct rockchip_pinctrl *info = bank->drvdata; 1317 1318 /* The first 32 pins of the first bank are located in PMU */ 1319 if (bank->bank_num == 0) { 1320 *regmap = info->regmap_pmu; 1321 *reg = PX30_PULL_PMU_OFFSET; 1322 } else { 1323 *regmap = info->regmap_base; 1324 *reg = PX30_PULL_GRF_OFFSET; 1325 1326 /* correct the offset, as we're starting with the 2nd bank */ 1327 *reg -= 0x10; 1328 *reg += bank->bank_num * PX30_PULL_BANK_STRIDE; 1329 } 1330 1331 *reg += ((pin_num / PX30_PULL_PINS_PER_REG) * 4); 1332 *bit = (pin_num % PX30_PULL_PINS_PER_REG); 1333 *bit *= PX30_PULL_BITS_PER_PIN; 1334 } 1335 1336 #define PX30_DRV_PMU_OFFSET 0x20 1337 #define PX30_DRV_GRF_OFFSET 0xf0 1338 #define PX30_DRV_BITS_PER_PIN 2 1339 #define PX30_DRV_PINS_PER_REG 8 1340 #define PX30_DRV_BANK_STRIDE 16 1341 1342 static void px30_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1343 int pin_num, struct regmap **regmap, 1344 int *reg, u8 *bit) 1345 { 1346 struct rockchip_pinctrl *info = bank->drvdata; 1347 1348 /* The first 32 pins of the first bank are located in PMU */ 1349 if (bank->bank_num == 0) { 1350 *regmap = info->regmap_pmu; 1351 *reg = PX30_DRV_PMU_OFFSET; 1352 } else { 1353 *regmap = info->regmap_base; 1354 *reg = PX30_DRV_GRF_OFFSET; 1355 1356 /* correct the offset, as we're starting with the 2nd bank */ 1357 *reg -= 0x10; 1358 *reg += bank->bank_num * PX30_DRV_BANK_STRIDE; 1359 } 1360 1361 *reg += ((pin_num / PX30_DRV_PINS_PER_REG) * 4); 1362 *bit = (pin_num % PX30_DRV_PINS_PER_REG); 1363 *bit *= PX30_DRV_BITS_PER_PIN; 1364 } 1365 1366 #define PX30_SCHMITT_PMU_OFFSET 0x38 1367 #define PX30_SCHMITT_GRF_OFFSET 0xc0 1368 #define PX30_SCHMITT_PINS_PER_PMU_REG 16 1369 #define PX30_SCHMITT_BANK_STRIDE 16 1370 #define PX30_SCHMITT_PINS_PER_GRF_REG 8 1371 1372 static int px30_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1373 int pin_num, 1374 struct regmap **regmap, 1375 int *reg, u8 *bit) 1376 { 1377 struct rockchip_pinctrl *info = bank->drvdata; 1378 int pins_per_reg; 1379 1380 if (bank->bank_num == 0) { 1381 *regmap = info->regmap_pmu; 1382 *reg = PX30_SCHMITT_PMU_OFFSET; 1383 pins_per_reg = PX30_SCHMITT_PINS_PER_PMU_REG; 1384 } else { 1385 *regmap = info->regmap_base; 1386 *reg = PX30_SCHMITT_GRF_OFFSET; 1387 pins_per_reg = PX30_SCHMITT_PINS_PER_GRF_REG; 1388 *reg += (bank->bank_num - 1) * PX30_SCHMITT_BANK_STRIDE; 1389 } 1390 1391 *reg += ((pin_num / pins_per_reg) * 4); 1392 *bit = pin_num % pins_per_reg; 1393 1394 return 0; 1395 } 1396 1397 #define RV1108_PULL_PMU_OFFSET 0x10 1398 #define RV1108_PULL_OFFSET 0x110 1399 #define RV1108_PULL_PINS_PER_REG 8 1400 #define RV1108_PULL_BITS_PER_PIN 2 1401 #define RV1108_PULL_BANK_STRIDE 16 1402 1403 static void rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1404 int pin_num, struct regmap **regmap, 1405 int *reg, u8 *bit) 1406 { 1407 struct rockchip_pinctrl *info = bank->drvdata; 1408 1409 /* The first 24 pins of the first bank are located in PMU */ 1410 if (bank->bank_num == 0) { 1411 *regmap = info->regmap_pmu; 1412 *reg = RV1108_PULL_PMU_OFFSET; 1413 } else { 1414 *reg = RV1108_PULL_OFFSET; 1415 *regmap = info->regmap_base; 1416 /* correct the offset, as we're starting with the 2nd bank */ 1417 *reg -= 0x10; 1418 *reg += bank->bank_num * RV1108_PULL_BANK_STRIDE; 1419 } 1420 1421 *reg += ((pin_num / RV1108_PULL_PINS_PER_REG) * 4); 1422 *bit = (pin_num % RV1108_PULL_PINS_PER_REG); 1423 *bit *= RV1108_PULL_BITS_PER_PIN; 1424 } 1425 1426 #define RV1108_DRV_PMU_OFFSET 0x20 1427 #define RV1108_DRV_GRF_OFFSET 0x210 1428 #define RV1108_DRV_BITS_PER_PIN 2 1429 #define RV1108_DRV_PINS_PER_REG 8 1430 #define RV1108_DRV_BANK_STRIDE 16 1431 1432 static void rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1433 int pin_num, struct regmap **regmap, 1434 int *reg, u8 *bit) 1435 { 1436 struct rockchip_pinctrl *info = bank->drvdata; 1437 1438 /* The first 24 pins of the first bank are located in PMU */ 1439 if (bank->bank_num == 0) { 1440 *regmap = info->regmap_pmu; 1441 *reg = RV1108_DRV_PMU_OFFSET; 1442 } else { 1443 *regmap = info->regmap_base; 1444 *reg = RV1108_DRV_GRF_OFFSET; 1445 1446 /* correct the offset, as we're starting with the 2nd bank */ 1447 *reg -= 0x10; 1448 *reg += bank->bank_num * RV1108_DRV_BANK_STRIDE; 1449 } 1450 1451 *reg += ((pin_num / RV1108_DRV_PINS_PER_REG) * 4); 1452 *bit = pin_num % RV1108_DRV_PINS_PER_REG; 1453 *bit *= RV1108_DRV_BITS_PER_PIN; 1454 } 1455 1456 #define RV1108_SCHMITT_PMU_OFFSET 0x30 1457 #define RV1108_SCHMITT_GRF_OFFSET 0x388 1458 #define RV1108_SCHMITT_BANK_STRIDE 8 1459 #define RV1108_SCHMITT_PINS_PER_GRF_REG 16 1460 #define RV1108_SCHMITT_PINS_PER_PMU_REG 8 1461 1462 static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1463 int pin_num, 1464 struct regmap **regmap, 1465 int *reg, u8 *bit) 1466 { 1467 struct rockchip_pinctrl *info = bank->drvdata; 1468 int pins_per_reg; 1469 1470 if (bank->bank_num == 0) { 1471 *regmap = info->regmap_pmu; 1472 *reg = RV1108_SCHMITT_PMU_OFFSET; 1473 pins_per_reg = RV1108_SCHMITT_PINS_PER_PMU_REG; 1474 } else { 1475 *regmap = info->regmap_base; 1476 *reg = RV1108_SCHMITT_GRF_OFFSET; 1477 pins_per_reg = RV1108_SCHMITT_PINS_PER_GRF_REG; 1478 *reg += (bank->bank_num - 1) * RV1108_SCHMITT_BANK_STRIDE; 1479 } 1480 *reg += ((pin_num / pins_per_reg) * 4); 1481 *bit = pin_num % pins_per_reg; 1482 1483 return 0; 1484 } 1485 1486 #define RK2928_PULL_OFFSET 0x118 1487 #define RK2928_PULL_PINS_PER_REG 16 1488 #define RK2928_PULL_BANK_STRIDE 8 1489 1490 static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1491 int pin_num, struct regmap **regmap, 1492 int *reg, u8 *bit) 1493 { 1494 struct rockchip_pinctrl *info = bank->drvdata; 1495 1496 *regmap = info->regmap_base; 1497 *reg = RK2928_PULL_OFFSET; 1498 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; 1499 *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4; 1500 1501 *bit = pin_num % RK2928_PULL_PINS_PER_REG; 1502 }; 1503 1504 #define RK3128_PULL_OFFSET 0x118 1505 1506 static void rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1507 int pin_num, struct regmap **regmap, 1508 int *reg, u8 *bit) 1509 { 1510 struct rockchip_pinctrl *info = bank->drvdata; 1511 1512 *regmap = info->regmap_base; 1513 *reg = RK3128_PULL_OFFSET; 1514 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; 1515 *reg += ((pin_num / RK2928_PULL_PINS_PER_REG) * 4); 1516 1517 *bit = pin_num % RK2928_PULL_PINS_PER_REG; 1518 } 1519 1520 #define RK3188_PULL_OFFSET 0x164 1521 #define RK3188_PULL_BITS_PER_PIN 2 1522 #define RK3188_PULL_PINS_PER_REG 8 1523 #define RK3188_PULL_BANK_STRIDE 16 1524 #define RK3188_PULL_PMU_OFFSET 0x64 1525 1526 static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1527 int pin_num, struct regmap **regmap, 1528 int *reg, u8 *bit) 1529 { 1530 struct rockchip_pinctrl *info = bank->drvdata; 1531 1532 /* The first 12 pins of the first bank are located elsewhere */ 1533 if (bank->bank_num == 0 && pin_num < 12) { 1534 *regmap = info->regmap_pmu ? info->regmap_pmu 1535 : bank->regmap_pull; 1536 *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0; 1537 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1538 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 1539 *bit *= RK3188_PULL_BITS_PER_PIN; 1540 } else { 1541 *regmap = info->regmap_pull ? info->regmap_pull 1542 : info->regmap_base; 1543 *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET; 1544 1545 /* correct the offset, as it is the 2nd pull register */ 1546 *reg -= 4; 1547 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1548 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1549 1550 /* 1551 * The bits in these registers have an inverse ordering 1552 * with the lowest pin being in bits 15:14 and the highest 1553 * pin in bits 1:0 1554 */ 1555 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG); 1556 *bit *= RK3188_PULL_BITS_PER_PIN; 1557 } 1558 } 1559 1560 #define RK3288_PULL_OFFSET 0x140 1561 static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1562 int pin_num, struct regmap **regmap, 1563 int *reg, u8 *bit) 1564 { 1565 struct rockchip_pinctrl *info = bank->drvdata; 1566 1567 /* The first 24 pins of the first bank are located in PMU */ 1568 if (bank->bank_num == 0) { 1569 *regmap = info->regmap_pmu; 1570 *reg = RK3188_PULL_PMU_OFFSET; 1571 1572 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1573 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 1574 *bit *= RK3188_PULL_BITS_PER_PIN; 1575 } else { 1576 *regmap = info->regmap_base; 1577 *reg = RK3288_PULL_OFFSET; 1578 1579 /* correct the offset, as we're starting with the 2nd bank */ 1580 *reg -= 0x10; 1581 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1582 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1583 1584 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1585 *bit *= RK3188_PULL_BITS_PER_PIN; 1586 } 1587 } 1588 1589 #define RK3288_DRV_PMU_OFFSET 0x70 1590 #define RK3288_DRV_GRF_OFFSET 0x1c0 1591 #define RK3288_DRV_BITS_PER_PIN 2 1592 #define RK3288_DRV_PINS_PER_REG 8 1593 #define RK3288_DRV_BANK_STRIDE 16 1594 1595 static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1596 int pin_num, struct regmap **regmap, 1597 int *reg, u8 *bit) 1598 { 1599 struct rockchip_pinctrl *info = bank->drvdata; 1600 1601 /* The first 24 pins of the first bank are located in PMU */ 1602 if (bank->bank_num == 0) { 1603 *regmap = info->regmap_pmu; 1604 *reg = RK3288_DRV_PMU_OFFSET; 1605 1606 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1607 *bit = pin_num % RK3288_DRV_PINS_PER_REG; 1608 *bit *= RK3288_DRV_BITS_PER_PIN; 1609 } else { 1610 *regmap = info->regmap_base; 1611 *reg = RK3288_DRV_GRF_OFFSET; 1612 1613 /* correct the offset, as we're starting with the 2nd bank */ 1614 *reg -= 0x10; 1615 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 1616 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1617 1618 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 1619 *bit *= RK3288_DRV_BITS_PER_PIN; 1620 } 1621 } 1622 1623 #define RK3228_PULL_OFFSET 0x100 1624 1625 static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1626 int pin_num, struct regmap **regmap, 1627 int *reg, u8 *bit) 1628 { 1629 struct rockchip_pinctrl *info = bank->drvdata; 1630 1631 *regmap = info->regmap_base; 1632 *reg = RK3228_PULL_OFFSET; 1633 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1634 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1635 1636 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1637 *bit *= RK3188_PULL_BITS_PER_PIN; 1638 } 1639 1640 #define RK3228_DRV_GRF_OFFSET 0x200 1641 1642 static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1643 int pin_num, struct regmap **regmap, 1644 int *reg, u8 *bit) 1645 { 1646 struct rockchip_pinctrl *info = bank->drvdata; 1647 1648 *regmap = info->regmap_base; 1649 *reg = RK3228_DRV_GRF_OFFSET; 1650 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 1651 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1652 1653 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 1654 *bit *= RK3288_DRV_BITS_PER_PIN; 1655 } 1656 1657 #define RK3368_PULL_GRF_OFFSET 0x100 1658 #define RK3368_PULL_PMU_OFFSET 0x10 1659 1660 static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1661 int pin_num, struct regmap **regmap, 1662 int *reg, u8 *bit) 1663 { 1664 struct rockchip_pinctrl *info = bank->drvdata; 1665 1666 /* The first 32 pins of the first bank are located in PMU */ 1667 if (bank->bank_num == 0) { 1668 *regmap = info->regmap_pmu; 1669 *reg = RK3368_PULL_PMU_OFFSET; 1670 1671 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1672 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 1673 *bit *= RK3188_PULL_BITS_PER_PIN; 1674 } else { 1675 *regmap = info->regmap_base; 1676 *reg = RK3368_PULL_GRF_OFFSET; 1677 1678 /* correct the offset, as we're starting with the 2nd bank */ 1679 *reg -= 0x10; 1680 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1681 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1682 1683 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1684 *bit *= RK3188_PULL_BITS_PER_PIN; 1685 } 1686 } 1687 1688 #define RK3368_DRV_PMU_OFFSET 0x20 1689 #define RK3368_DRV_GRF_OFFSET 0x200 1690 1691 static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1692 int pin_num, struct regmap **regmap, 1693 int *reg, u8 *bit) 1694 { 1695 struct rockchip_pinctrl *info = bank->drvdata; 1696 1697 /* The first 32 pins of the first bank are located in PMU */ 1698 if (bank->bank_num == 0) { 1699 *regmap = info->regmap_pmu; 1700 *reg = RK3368_DRV_PMU_OFFSET; 1701 1702 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1703 *bit = pin_num % RK3288_DRV_PINS_PER_REG; 1704 *bit *= RK3288_DRV_BITS_PER_PIN; 1705 } else { 1706 *regmap = info->regmap_base; 1707 *reg = RK3368_DRV_GRF_OFFSET; 1708 1709 /* correct the offset, as we're starting with the 2nd bank */ 1710 *reg -= 0x10; 1711 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 1712 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1713 1714 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 1715 *bit *= RK3288_DRV_BITS_PER_PIN; 1716 } 1717 } 1718 1719 #define RK3399_PULL_GRF_OFFSET 0xe040 1720 #define RK3399_PULL_PMU_OFFSET 0x40 1721 #define RK3399_DRV_3BITS_PER_PIN 3 1722 1723 static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1724 int pin_num, struct regmap **regmap, 1725 int *reg, u8 *bit) 1726 { 1727 struct rockchip_pinctrl *info = bank->drvdata; 1728 1729 /* The bank0:16 and bank1:32 pins are located in PMU */ 1730 if ((bank->bank_num == 0) || (bank->bank_num == 1)) { 1731 *regmap = info->regmap_pmu; 1732 *reg = RK3399_PULL_PMU_OFFSET; 1733 1734 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1735 1736 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1737 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 1738 *bit *= RK3188_PULL_BITS_PER_PIN; 1739 } else { 1740 *regmap = info->regmap_base; 1741 *reg = RK3399_PULL_GRF_OFFSET; 1742 1743 /* correct the offset, as we're starting with the 3rd bank */ 1744 *reg -= 0x20; 1745 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1746 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1747 1748 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1749 *bit *= RK3188_PULL_BITS_PER_PIN; 1750 } 1751 } 1752 1753 static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1754 int pin_num, struct regmap **regmap, 1755 int *reg, u8 *bit) 1756 { 1757 struct rockchip_pinctrl *info = bank->drvdata; 1758 int drv_num = (pin_num / 8); 1759 1760 /* The bank0:16 and bank1:32 pins are located in PMU */ 1761 if ((bank->bank_num == 0) || (bank->bank_num == 1)) 1762 *regmap = info->regmap_pmu; 1763 else 1764 *regmap = info->regmap_base; 1765 1766 *reg = bank->drv[drv_num].offset; 1767 if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) || 1768 (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY)) 1769 *bit = (pin_num % 8) * 3; 1770 else 1771 *bit = (pin_num % 8) * 2; 1772 } 1773 1774 static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = { 1775 { 2, 4, 8, 12, -1, -1, -1, -1 }, 1776 { 3, 6, 9, 12, -1, -1, -1, -1 }, 1777 { 5, 10, 15, 20, -1, -1, -1, -1 }, 1778 { 4, 6, 8, 10, 12, 14, 16, 18 }, 1779 { 4, 7, 10, 13, 16, 19, 22, 26 } 1780 }; 1781 1782 static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank, 1783 int pin_num) 1784 { 1785 struct rockchip_pinctrl *info = bank->drvdata; 1786 struct rockchip_pin_ctrl *ctrl = info->ctrl; 1787 struct regmap *regmap; 1788 int reg, ret; 1789 u32 data, temp, rmask_bits; 1790 u8 bit; 1791 int drv_type = bank->drv[pin_num / 8].drv_type; 1792 1793 ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); 1794 1795 switch (drv_type) { 1796 case DRV_TYPE_IO_1V8_3V0_AUTO: 1797 case DRV_TYPE_IO_3V3_ONLY: 1798 rmask_bits = RK3399_DRV_3BITS_PER_PIN; 1799 switch (bit) { 1800 case 0 ... 12: 1801 /* regular case, nothing to do */ 1802 break; 1803 case 15: 1804 /* 1805 * drive-strength offset is special, as it is 1806 * spread over 2 registers 1807 */ 1808 ret = regmap_read(regmap, reg, &data); 1809 if (ret) 1810 return ret; 1811 1812 ret = regmap_read(regmap, reg + 0x4, &temp); 1813 if (ret) 1814 return ret; 1815 1816 /* 1817 * the bit data[15] contains bit 0 of the value 1818 * while temp[1:0] contains bits 2 and 1 1819 */ 1820 data >>= 15; 1821 temp &= 0x3; 1822 temp <<= 1; 1823 data |= temp; 1824 1825 return rockchip_perpin_drv_list[drv_type][data]; 1826 case 18 ... 21: 1827 /* setting fully enclosed in the second register */ 1828 reg += 4; 1829 bit -= 16; 1830 break; 1831 default: 1832 dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n", 1833 bit, drv_type); 1834 return -EINVAL; 1835 } 1836 1837 break; 1838 case DRV_TYPE_IO_DEFAULT: 1839 case DRV_TYPE_IO_1V8_OR_3V0: 1840 case DRV_TYPE_IO_1V8_ONLY: 1841 rmask_bits = RK3288_DRV_BITS_PER_PIN; 1842 break; 1843 default: 1844 dev_err(info->dev, "unsupported pinctrl drive type: %d\n", 1845 drv_type); 1846 return -EINVAL; 1847 } 1848 1849 ret = regmap_read(regmap, reg, &data); 1850 if (ret) 1851 return ret; 1852 1853 data >>= bit; 1854 data &= (1 << rmask_bits) - 1; 1855 1856 return rockchip_perpin_drv_list[drv_type][data]; 1857 } 1858 1859 static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank, 1860 int pin_num, int strength) 1861 { 1862 struct rockchip_pinctrl *info = bank->drvdata; 1863 struct rockchip_pin_ctrl *ctrl = info->ctrl; 1864 struct regmap *regmap; 1865 int reg, ret, i; 1866 u32 data, rmask, rmask_bits, temp; 1867 u8 bit; 1868 int drv_type = bank->drv[pin_num / 8].drv_type; 1869 1870 dev_dbg(info->dev, "setting drive of GPIO%d-%d to %d\n", 1871 bank->bank_num, pin_num, strength); 1872 1873 ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); 1874 1875 ret = -EINVAL; 1876 for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) { 1877 if (rockchip_perpin_drv_list[drv_type][i] == strength) { 1878 ret = i; 1879 break; 1880 } else if (rockchip_perpin_drv_list[drv_type][i] < 0) { 1881 ret = rockchip_perpin_drv_list[drv_type][i]; 1882 break; 1883 } 1884 } 1885 1886 if (ret < 0) { 1887 dev_err(info->dev, "unsupported driver strength %d\n", 1888 strength); 1889 return ret; 1890 } 1891 1892 switch (drv_type) { 1893 case DRV_TYPE_IO_1V8_3V0_AUTO: 1894 case DRV_TYPE_IO_3V3_ONLY: 1895 rmask_bits = RK3399_DRV_3BITS_PER_PIN; 1896 switch (bit) { 1897 case 0 ... 12: 1898 /* regular case, nothing to do */ 1899 break; 1900 case 15: 1901 /* 1902 * drive-strength offset is special, as it is spread 1903 * over 2 registers, the bit data[15] contains bit 0 1904 * of the value while temp[1:0] contains bits 2 and 1 1905 */ 1906 data = (ret & 0x1) << 15; 1907 temp = (ret >> 0x1) & 0x3; 1908 1909 rmask = BIT(15) | BIT(31); 1910 data |= BIT(31); 1911 ret = regmap_update_bits(regmap, reg, rmask, data); 1912 if (ret) 1913 return ret; 1914 1915 rmask = 0x3 | (0x3 << 16); 1916 temp |= (0x3 << 16); 1917 reg += 0x4; 1918 ret = regmap_update_bits(regmap, reg, rmask, temp); 1919 1920 return ret; 1921 case 18 ... 21: 1922 /* setting fully enclosed in the second register */ 1923 reg += 4; 1924 bit -= 16; 1925 break; 1926 default: 1927 dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n", 1928 bit, drv_type); 1929 return -EINVAL; 1930 } 1931 break; 1932 case DRV_TYPE_IO_DEFAULT: 1933 case DRV_TYPE_IO_1V8_OR_3V0: 1934 case DRV_TYPE_IO_1V8_ONLY: 1935 rmask_bits = RK3288_DRV_BITS_PER_PIN; 1936 break; 1937 default: 1938 dev_err(info->dev, "unsupported pinctrl drive type: %d\n", 1939 drv_type); 1940 return -EINVAL; 1941 } 1942 1943 /* enable the write to the equivalent lower bits */ 1944 data = ((1 << rmask_bits) - 1) << (bit + 16); 1945 rmask = data | (data >> 16); 1946 data |= (ret << bit); 1947 1948 ret = regmap_update_bits(regmap, reg, rmask, data); 1949 1950 return ret; 1951 } 1952 1953 static int rockchip_pull_list[PULL_TYPE_MAX][4] = { 1954 { 1955 PIN_CONFIG_BIAS_DISABLE, 1956 PIN_CONFIG_BIAS_PULL_UP, 1957 PIN_CONFIG_BIAS_PULL_DOWN, 1958 PIN_CONFIG_BIAS_BUS_HOLD 1959 }, 1960 { 1961 PIN_CONFIG_BIAS_DISABLE, 1962 PIN_CONFIG_BIAS_PULL_DOWN, 1963 PIN_CONFIG_BIAS_DISABLE, 1964 PIN_CONFIG_BIAS_PULL_UP 1965 }, 1966 }; 1967 1968 static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num) 1969 { 1970 struct rockchip_pinctrl *info = bank->drvdata; 1971 struct rockchip_pin_ctrl *ctrl = info->ctrl; 1972 struct regmap *regmap; 1973 int reg, ret, pull_type; 1974 u8 bit; 1975 u32 data; 1976 1977 /* rk3066b does support any pulls */ 1978 if (ctrl->type == RK3066B) 1979 return PIN_CONFIG_BIAS_DISABLE; 1980 1981 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); 1982 1983 ret = regmap_read(regmap, reg, &data); 1984 if (ret) 1985 return ret; 1986 1987 switch (ctrl->type) { 1988 case RK2928: 1989 case RK3128: 1990 return !(data & BIT(bit)) 1991 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT 1992 : PIN_CONFIG_BIAS_DISABLE; 1993 case PX30: 1994 case RV1108: 1995 case RK3188: 1996 case RK3288: 1997 case RK3368: 1998 case RK3399: 1999 pull_type = bank->pull_type[pin_num / 8]; 2000 data >>= bit; 2001 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1; 2002 2003 return rockchip_pull_list[pull_type][data]; 2004 default: 2005 dev_err(info->dev, "unsupported pinctrl type\n"); 2006 return -EINVAL; 2007 }; 2008 } 2009 2010 static int rockchip_set_pull(struct rockchip_pin_bank *bank, 2011 int pin_num, int pull) 2012 { 2013 struct rockchip_pinctrl *info = bank->drvdata; 2014 struct rockchip_pin_ctrl *ctrl = info->ctrl; 2015 struct regmap *regmap; 2016 int reg, ret, i, pull_type; 2017 u8 bit; 2018 u32 data, rmask; 2019 2020 dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n", 2021 bank->bank_num, pin_num, pull); 2022 2023 /* rk3066b does support any pulls */ 2024 if (ctrl->type == RK3066B) 2025 return pull ? -EINVAL : 0; 2026 2027 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); 2028 2029 switch (ctrl->type) { 2030 case RK2928: 2031 case RK3128: 2032 data = BIT(bit + 16); 2033 if (pull == PIN_CONFIG_BIAS_DISABLE) 2034 data |= BIT(bit); 2035 ret = regmap_write(regmap, reg, data); 2036 break; 2037 case PX30: 2038 case RV1108: 2039 case RK3188: 2040 case RK3288: 2041 case RK3368: 2042 case RK3399: 2043 pull_type = bank->pull_type[pin_num / 8]; 2044 ret = -EINVAL; 2045 for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]); 2046 i++) { 2047 if (rockchip_pull_list[pull_type][i] == pull) { 2048 ret = i; 2049 break; 2050 } 2051 } 2052 2053 if (ret < 0) { 2054 dev_err(info->dev, "unsupported pull setting %d\n", 2055 pull); 2056 return ret; 2057 } 2058 2059 /* enable the write to the equivalent lower bits */ 2060 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16); 2061 rmask = data | (data >> 16); 2062 data |= (ret << bit); 2063 2064 ret = regmap_update_bits(regmap, reg, rmask, data); 2065 break; 2066 default: 2067 dev_err(info->dev, "unsupported pinctrl type\n"); 2068 return -EINVAL; 2069 } 2070 2071 return ret; 2072 } 2073 2074 #define RK3328_SCHMITT_BITS_PER_PIN 1 2075 #define RK3328_SCHMITT_PINS_PER_REG 16 2076 #define RK3328_SCHMITT_BANK_STRIDE 8 2077 #define RK3328_SCHMITT_GRF_OFFSET 0x380 2078 2079 static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 2080 int pin_num, 2081 struct regmap **regmap, 2082 int *reg, u8 *bit) 2083 { 2084 struct rockchip_pinctrl *info = bank->drvdata; 2085 2086 *regmap = info->regmap_base; 2087 *reg = RK3328_SCHMITT_GRF_OFFSET; 2088 2089 *reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE; 2090 *reg += ((pin_num / RK3328_SCHMITT_PINS_PER_REG) * 4); 2091 *bit = pin_num % RK3328_SCHMITT_PINS_PER_REG; 2092 2093 return 0; 2094 } 2095 2096 static int rockchip_get_schmitt(struct rockchip_pin_bank *bank, int pin_num) 2097 { 2098 struct rockchip_pinctrl *info = bank->drvdata; 2099 struct rockchip_pin_ctrl *ctrl = info->ctrl; 2100 struct regmap *regmap; 2101 int reg, ret; 2102 u8 bit; 2103 u32 data; 2104 2105 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit); 2106 if (ret) 2107 return ret; 2108 2109 ret = regmap_read(regmap, reg, &data); 2110 if (ret) 2111 return ret; 2112 2113 data >>= bit; 2114 return data & 0x1; 2115 } 2116 2117 static int rockchip_set_schmitt(struct rockchip_pin_bank *bank, 2118 int pin_num, int enable) 2119 { 2120 struct rockchip_pinctrl *info = bank->drvdata; 2121 struct rockchip_pin_ctrl *ctrl = info->ctrl; 2122 struct regmap *regmap; 2123 int reg, ret; 2124 u8 bit; 2125 u32 data, rmask; 2126 2127 dev_dbg(info->dev, "setting input schmitt of GPIO%d-%d to %d\n", 2128 bank->bank_num, pin_num, enable); 2129 2130 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit); 2131 if (ret) 2132 return ret; 2133 2134 /* enable the write to the equivalent lower bits */ 2135 data = BIT(bit + 16) | (enable << bit); 2136 rmask = BIT(bit + 16) | BIT(bit); 2137 2138 return regmap_update_bits(regmap, reg, rmask, data); 2139 } 2140 2141 /* 2142 * Pinmux_ops handling 2143 */ 2144 2145 static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev) 2146 { 2147 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 2148 2149 return info->nfunctions; 2150 } 2151 2152 static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev, 2153 unsigned selector) 2154 { 2155 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 2156 2157 return info->functions[selector].name; 2158 } 2159 2160 static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev, 2161 unsigned selector, const char * const **groups, 2162 unsigned * const num_groups) 2163 { 2164 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 2165 2166 *groups = info->functions[selector].groups; 2167 *num_groups = info->functions[selector].ngroups; 2168 2169 return 0; 2170 } 2171 2172 static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector, 2173 unsigned group) 2174 { 2175 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 2176 const unsigned int *pins = info->groups[group].pins; 2177 const struct rockchip_pin_config *data = info->groups[group].data; 2178 struct rockchip_pin_bank *bank; 2179 int cnt, ret = 0; 2180 2181 dev_dbg(info->dev, "enable function %s group %s\n", 2182 info->functions[selector].name, info->groups[group].name); 2183 2184 /* 2185 * for each pin in the pin group selected, program the corresponding 2186 * pin function number in the config register. 2187 */ 2188 for (cnt = 0; cnt < info->groups[group].npins; cnt++) { 2189 bank = pin_to_bank(info, pins[cnt]); 2190 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 2191 data[cnt].func); 2192 if (ret) 2193 break; 2194 } 2195 2196 if (ret) { 2197 /* revert the already done pin settings */ 2198 for (cnt--; cnt >= 0; cnt--) 2199 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0); 2200 2201 return ret; 2202 } 2203 2204 return 0; 2205 } 2206 2207 static int rockchip_gpio_get_direction(struct gpio_chip *chip, unsigned offset) 2208 { 2209 struct rockchip_pin_bank *bank = gpiochip_get_data(chip); 2210 u32 data; 2211 int ret; 2212 2213 ret = clk_enable(bank->clk); 2214 if (ret < 0) { 2215 dev_err(bank->drvdata->dev, 2216 "failed to enable clock for bank %s\n", bank->name); 2217 return ret; 2218 } 2219 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); 2220 clk_disable(bank->clk); 2221 2222 return !(data & BIT(offset)); 2223 } 2224 2225 /* 2226 * The calls to gpio_direction_output() and gpio_direction_input() 2227 * leads to this function call (via the pinctrl_gpio_direction_{input|output}() 2228 * function called from the gpiolib interface). 2229 */ 2230 static int _rockchip_pmx_gpio_set_direction(struct gpio_chip *chip, 2231 int pin, bool input) 2232 { 2233 struct rockchip_pin_bank *bank; 2234 int ret; 2235 unsigned long flags; 2236 u32 data; 2237 2238 bank = gpiochip_get_data(chip); 2239 2240 ret = rockchip_set_mux(bank, pin, RK_FUNC_GPIO); 2241 if (ret < 0) 2242 return ret; 2243 2244 clk_enable(bank->clk); 2245 raw_spin_lock_irqsave(&bank->slock, flags); 2246 2247 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); 2248 /* set bit to 1 for output, 0 for input */ 2249 if (!input) 2250 data |= BIT(pin); 2251 else 2252 data &= ~BIT(pin); 2253 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR); 2254 2255 raw_spin_unlock_irqrestore(&bank->slock, flags); 2256 clk_disable(bank->clk); 2257 2258 return 0; 2259 } 2260 2261 static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, 2262 struct pinctrl_gpio_range *range, 2263 unsigned offset, bool input) 2264 { 2265 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 2266 struct gpio_chip *chip; 2267 int pin; 2268 2269 chip = range->gc; 2270 pin = offset - chip->base; 2271 dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n", 2272 offset, range->name, pin, input ? "input" : "output"); 2273 2274 return _rockchip_pmx_gpio_set_direction(chip, offset - chip->base, 2275 input); 2276 } 2277 2278 static const struct pinmux_ops rockchip_pmx_ops = { 2279 .get_functions_count = rockchip_pmx_get_funcs_count, 2280 .get_function_name = rockchip_pmx_get_func_name, 2281 .get_function_groups = rockchip_pmx_get_groups, 2282 .set_mux = rockchip_pmx_set, 2283 .gpio_set_direction = rockchip_pmx_gpio_set_direction, 2284 }; 2285 2286 /* 2287 * Pinconf_ops handling 2288 */ 2289 2290 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl, 2291 enum pin_config_param pull) 2292 { 2293 switch (ctrl->type) { 2294 case RK2928: 2295 case RK3128: 2296 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT || 2297 pull == PIN_CONFIG_BIAS_DISABLE); 2298 case RK3066B: 2299 return pull ? false : true; 2300 case PX30: 2301 case RV1108: 2302 case RK3188: 2303 case RK3288: 2304 case RK3368: 2305 case RK3399: 2306 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT); 2307 } 2308 2309 return false; 2310 } 2311 2312 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value); 2313 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset); 2314 2315 /* set the pin config settings for a specified pin */ 2316 static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 2317 unsigned long *configs, unsigned num_configs) 2318 { 2319 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 2320 struct rockchip_pin_bank *bank = pin_to_bank(info, pin); 2321 enum pin_config_param param; 2322 u32 arg; 2323 int i; 2324 int rc; 2325 2326 for (i = 0; i < num_configs; i++) { 2327 param = pinconf_to_config_param(configs[i]); 2328 arg = pinconf_to_config_argument(configs[i]); 2329 2330 switch (param) { 2331 case PIN_CONFIG_BIAS_DISABLE: 2332 rc = rockchip_set_pull(bank, pin - bank->pin_base, 2333 param); 2334 if (rc) 2335 return rc; 2336 break; 2337 case PIN_CONFIG_BIAS_PULL_UP: 2338 case PIN_CONFIG_BIAS_PULL_DOWN: 2339 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: 2340 case PIN_CONFIG_BIAS_BUS_HOLD: 2341 if (!rockchip_pinconf_pull_valid(info->ctrl, param)) 2342 return -ENOTSUPP; 2343 2344 if (!arg) 2345 return -EINVAL; 2346 2347 rc = rockchip_set_pull(bank, pin - bank->pin_base, 2348 param); 2349 if (rc) 2350 return rc; 2351 break; 2352 case PIN_CONFIG_OUTPUT: 2353 rockchip_gpio_set(&bank->gpio_chip, 2354 pin - bank->pin_base, arg); 2355 rc = _rockchip_pmx_gpio_set_direction(&bank->gpio_chip, 2356 pin - bank->pin_base, false); 2357 if (rc) 2358 return rc; 2359 break; 2360 case PIN_CONFIG_DRIVE_STRENGTH: 2361 /* rk3288 is the first with per-pin drive-strength */ 2362 if (!info->ctrl->drv_calc_reg) 2363 return -ENOTSUPP; 2364 2365 rc = rockchip_set_drive_perpin(bank, 2366 pin - bank->pin_base, arg); 2367 if (rc < 0) 2368 return rc; 2369 break; 2370 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 2371 if (!info->ctrl->schmitt_calc_reg) 2372 return -ENOTSUPP; 2373 2374 rc = rockchip_set_schmitt(bank, 2375 pin - bank->pin_base, arg); 2376 if (rc < 0) 2377 return rc; 2378 break; 2379 default: 2380 return -ENOTSUPP; 2381 break; 2382 } 2383 } /* for each config */ 2384 2385 return 0; 2386 } 2387 2388 /* get the pin config settings for a specified pin */ 2389 static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, 2390 unsigned long *config) 2391 { 2392 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 2393 struct rockchip_pin_bank *bank = pin_to_bank(info, pin); 2394 enum pin_config_param param = pinconf_to_config_param(*config); 2395 u16 arg; 2396 int rc; 2397 2398 switch (param) { 2399 case PIN_CONFIG_BIAS_DISABLE: 2400 if (rockchip_get_pull(bank, pin - bank->pin_base) != param) 2401 return -EINVAL; 2402 2403 arg = 0; 2404 break; 2405 case PIN_CONFIG_BIAS_PULL_UP: 2406 case PIN_CONFIG_BIAS_PULL_DOWN: 2407 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: 2408 case PIN_CONFIG_BIAS_BUS_HOLD: 2409 if (!rockchip_pinconf_pull_valid(info->ctrl, param)) 2410 return -ENOTSUPP; 2411 2412 if (rockchip_get_pull(bank, pin - bank->pin_base) != param) 2413 return -EINVAL; 2414 2415 arg = 1; 2416 break; 2417 case PIN_CONFIG_OUTPUT: 2418 rc = rockchip_get_mux(bank, pin - bank->pin_base); 2419 if (rc != RK_FUNC_GPIO) 2420 return -EINVAL; 2421 2422 rc = rockchip_gpio_get(&bank->gpio_chip, pin - bank->pin_base); 2423 if (rc < 0) 2424 return rc; 2425 2426 arg = rc ? 1 : 0; 2427 break; 2428 case PIN_CONFIG_DRIVE_STRENGTH: 2429 /* rk3288 is the first with per-pin drive-strength */ 2430 if (!info->ctrl->drv_calc_reg) 2431 return -ENOTSUPP; 2432 2433 rc = rockchip_get_drive_perpin(bank, pin - bank->pin_base); 2434 if (rc < 0) 2435 return rc; 2436 2437 arg = rc; 2438 break; 2439 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 2440 if (!info->ctrl->schmitt_calc_reg) 2441 return -ENOTSUPP; 2442 2443 rc = rockchip_get_schmitt(bank, pin - bank->pin_base); 2444 if (rc < 0) 2445 return rc; 2446 2447 arg = rc; 2448 break; 2449 default: 2450 return -ENOTSUPP; 2451 break; 2452 } 2453 2454 *config = pinconf_to_config_packed(param, arg); 2455 2456 return 0; 2457 } 2458 2459 static const struct pinconf_ops rockchip_pinconf_ops = { 2460 .pin_config_get = rockchip_pinconf_get, 2461 .pin_config_set = rockchip_pinconf_set, 2462 .is_generic = true, 2463 }; 2464 2465 static const struct of_device_id rockchip_bank_match[] = { 2466 { .compatible = "rockchip,gpio-bank" }, 2467 { .compatible = "rockchip,rk3188-gpio-bank0" }, 2468 {}, 2469 }; 2470 2471 static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info, 2472 struct device_node *np) 2473 { 2474 struct device_node *child; 2475 2476 for_each_child_of_node(np, child) { 2477 if (of_match_node(rockchip_bank_match, child)) 2478 continue; 2479 2480 info->nfunctions++; 2481 info->ngroups += of_get_child_count(child); 2482 } 2483 } 2484 2485 static int rockchip_pinctrl_parse_groups(struct device_node *np, 2486 struct rockchip_pin_group *grp, 2487 struct rockchip_pinctrl *info, 2488 u32 index) 2489 { 2490 struct rockchip_pin_bank *bank; 2491 int size; 2492 const __be32 *list; 2493 int num; 2494 int i, j; 2495 int ret; 2496 2497 dev_dbg(info->dev, "group(%d): %pOFn\n", index, np); 2498 2499 /* Initialise group */ 2500 grp->name = np->name; 2501 2502 /* 2503 * the binding format is rockchip,pins = <bank pin mux CONFIG>, 2504 * do sanity check and calculate pins number 2505 */ 2506 list = of_get_property(np, "rockchip,pins", &size); 2507 /* we do not check return since it's safe node passed down */ 2508 size /= sizeof(*list); 2509 if (!size || size % 4) { 2510 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n"); 2511 return -EINVAL; 2512 } 2513 2514 grp->npins = size / 4; 2515 2516 grp->pins = devm_kcalloc(info->dev, grp->npins, sizeof(unsigned int), 2517 GFP_KERNEL); 2518 grp->data = devm_kcalloc(info->dev, 2519 grp->npins, 2520 sizeof(struct rockchip_pin_config), 2521 GFP_KERNEL); 2522 if (!grp->pins || !grp->data) 2523 return -ENOMEM; 2524 2525 for (i = 0, j = 0; i < size; i += 4, j++) { 2526 const __be32 *phandle; 2527 struct device_node *np_config; 2528 2529 num = be32_to_cpu(*list++); 2530 bank = bank_num_to_bank(info, num); 2531 if (IS_ERR(bank)) 2532 return PTR_ERR(bank); 2533 2534 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++); 2535 grp->data[j].func = be32_to_cpu(*list++); 2536 2537 phandle = list++; 2538 if (!phandle) 2539 return -EINVAL; 2540 2541 np_config = of_find_node_by_phandle(be32_to_cpup(phandle)); 2542 ret = pinconf_generic_parse_dt_config(np_config, NULL, 2543 &grp->data[j].configs, &grp->data[j].nconfigs); 2544 if (ret) 2545 return ret; 2546 } 2547 2548 return 0; 2549 } 2550 2551 static int rockchip_pinctrl_parse_functions(struct device_node *np, 2552 struct rockchip_pinctrl *info, 2553 u32 index) 2554 { 2555 struct device_node *child; 2556 struct rockchip_pmx_func *func; 2557 struct rockchip_pin_group *grp; 2558 int ret; 2559 static u32 grp_index; 2560 u32 i = 0; 2561 2562 dev_dbg(info->dev, "parse function(%d): %pOFn\n", index, np); 2563 2564 func = &info->functions[index]; 2565 2566 /* Initialise function */ 2567 func->name = np->name; 2568 func->ngroups = of_get_child_count(np); 2569 if (func->ngroups <= 0) 2570 return 0; 2571 2572 func->groups = devm_kcalloc(info->dev, 2573 func->ngroups, sizeof(char *), GFP_KERNEL); 2574 if (!func->groups) 2575 return -ENOMEM; 2576 2577 for_each_child_of_node(np, child) { 2578 func->groups[i] = child->name; 2579 grp = &info->groups[grp_index++]; 2580 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++); 2581 if (ret) { 2582 of_node_put(child); 2583 return ret; 2584 } 2585 } 2586 2587 return 0; 2588 } 2589 2590 static int rockchip_pinctrl_parse_dt(struct platform_device *pdev, 2591 struct rockchip_pinctrl *info) 2592 { 2593 struct device *dev = &pdev->dev; 2594 struct device_node *np = dev->of_node; 2595 struct device_node *child; 2596 int ret; 2597 int i; 2598 2599 rockchip_pinctrl_child_count(info, np); 2600 2601 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions); 2602 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups); 2603 2604 info->functions = devm_kcalloc(dev, 2605 info->nfunctions, 2606 sizeof(struct rockchip_pmx_func), 2607 GFP_KERNEL); 2608 if (!info->functions) 2609 return -EINVAL; 2610 2611 info->groups = devm_kcalloc(dev, 2612 info->ngroups, 2613 sizeof(struct rockchip_pin_group), 2614 GFP_KERNEL); 2615 if (!info->groups) 2616 return -EINVAL; 2617 2618 i = 0; 2619 2620 for_each_child_of_node(np, child) { 2621 if (of_match_node(rockchip_bank_match, child)) 2622 continue; 2623 2624 ret = rockchip_pinctrl_parse_functions(child, info, i++); 2625 if (ret) { 2626 dev_err(&pdev->dev, "failed to parse function\n"); 2627 of_node_put(child); 2628 return ret; 2629 } 2630 } 2631 2632 return 0; 2633 } 2634 2635 static int rockchip_pinctrl_register(struct platform_device *pdev, 2636 struct rockchip_pinctrl *info) 2637 { 2638 struct pinctrl_desc *ctrldesc = &info->pctl; 2639 struct pinctrl_pin_desc *pindesc, *pdesc; 2640 struct rockchip_pin_bank *pin_bank; 2641 int pin, bank, ret; 2642 int k; 2643 2644 ctrldesc->name = "rockchip-pinctrl"; 2645 ctrldesc->owner = THIS_MODULE; 2646 ctrldesc->pctlops = &rockchip_pctrl_ops; 2647 ctrldesc->pmxops = &rockchip_pmx_ops; 2648 ctrldesc->confops = &rockchip_pinconf_ops; 2649 2650 pindesc = devm_kcalloc(&pdev->dev, 2651 info->ctrl->nr_pins, sizeof(*pindesc), 2652 GFP_KERNEL); 2653 if (!pindesc) 2654 return -ENOMEM; 2655 2656 ctrldesc->pins = pindesc; 2657 ctrldesc->npins = info->ctrl->nr_pins; 2658 2659 pdesc = pindesc; 2660 for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) { 2661 pin_bank = &info->ctrl->pin_banks[bank]; 2662 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) { 2663 pdesc->number = k; 2664 pdesc->name = kasprintf(GFP_KERNEL, "%s-%d", 2665 pin_bank->name, pin); 2666 pdesc++; 2667 } 2668 } 2669 2670 ret = rockchip_pinctrl_parse_dt(pdev, info); 2671 if (ret) 2672 return ret; 2673 2674 info->pctl_dev = devm_pinctrl_register(&pdev->dev, ctrldesc, info); 2675 if (IS_ERR(info->pctl_dev)) { 2676 dev_err(&pdev->dev, "could not register pinctrl driver\n"); 2677 return PTR_ERR(info->pctl_dev); 2678 } 2679 2680 for (bank = 0; bank < info->ctrl->nr_banks; ++bank) { 2681 pin_bank = &info->ctrl->pin_banks[bank]; 2682 pin_bank->grange.name = pin_bank->name; 2683 pin_bank->grange.id = bank; 2684 pin_bank->grange.pin_base = pin_bank->pin_base; 2685 pin_bank->grange.base = pin_bank->gpio_chip.base; 2686 pin_bank->grange.npins = pin_bank->gpio_chip.ngpio; 2687 pin_bank->grange.gc = &pin_bank->gpio_chip; 2688 pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange); 2689 } 2690 2691 return 0; 2692 } 2693 2694 /* 2695 * GPIO handling 2696 */ 2697 2698 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value) 2699 { 2700 struct rockchip_pin_bank *bank = gpiochip_get_data(gc); 2701 void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR; 2702 unsigned long flags; 2703 u32 data; 2704 2705 clk_enable(bank->clk); 2706 raw_spin_lock_irqsave(&bank->slock, flags); 2707 2708 data = readl(reg); 2709 data &= ~BIT(offset); 2710 if (value) 2711 data |= BIT(offset); 2712 writel(data, reg); 2713 2714 raw_spin_unlock_irqrestore(&bank->slock, flags); 2715 clk_disable(bank->clk); 2716 } 2717 2718 /* 2719 * Returns the level of the pin for input direction and setting of the DR 2720 * register for output gpios. 2721 */ 2722 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset) 2723 { 2724 struct rockchip_pin_bank *bank = gpiochip_get_data(gc); 2725 u32 data; 2726 2727 clk_enable(bank->clk); 2728 data = readl(bank->reg_base + GPIO_EXT_PORT); 2729 clk_disable(bank->clk); 2730 data >>= offset; 2731 data &= 1; 2732 return data; 2733 } 2734 2735 /* 2736 * gpiolib gpio_direction_input callback function. The setting of the pin 2737 * mux function as 'gpio input' will be handled by the pinctrl subsystem 2738 * interface. 2739 */ 2740 static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset) 2741 { 2742 return pinctrl_gpio_direction_input(gc->base + offset); 2743 } 2744 2745 /* 2746 * gpiolib gpio_direction_output callback function. The setting of the pin 2747 * mux function as 'gpio output' will be handled by the pinctrl subsystem 2748 * interface. 2749 */ 2750 static int rockchip_gpio_direction_output(struct gpio_chip *gc, 2751 unsigned offset, int value) 2752 { 2753 rockchip_gpio_set(gc, offset, value); 2754 return pinctrl_gpio_direction_output(gc->base + offset); 2755 } 2756 2757 static void rockchip_gpio_set_debounce(struct gpio_chip *gc, 2758 unsigned int offset, bool enable) 2759 { 2760 struct rockchip_pin_bank *bank = gpiochip_get_data(gc); 2761 void __iomem *reg = bank->reg_base + GPIO_DEBOUNCE; 2762 unsigned long flags; 2763 u32 data; 2764 2765 clk_enable(bank->clk); 2766 raw_spin_lock_irqsave(&bank->slock, flags); 2767 2768 data = readl(reg); 2769 if (enable) 2770 data |= BIT(offset); 2771 else 2772 data &= ~BIT(offset); 2773 writel(data, reg); 2774 2775 raw_spin_unlock_irqrestore(&bank->slock, flags); 2776 clk_disable(bank->clk); 2777 } 2778 2779 /* 2780 * gpiolib set_config callback function. The setting of the pin 2781 * mux function as 'gpio output' will be handled by the pinctrl subsystem 2782 * interface. 2783 */ 2784 static int rockchip_gpio_set_config(struct gpio_chip *gc, unsigned int offset, 2785 unsigned long config) 2786 { 2787 enum pin_config_param param = pinconf_to_config_param(config); 2788 2789 switch (param) { 2790 case PIN_CONFIG_INPUT_DEBOUNCE: 2791 rockchip_gpio_set_debounce(gc, offset, true); 2792 /* 2793 * Rockchip's gpio could only support up to one period 2794 * of the debounce clock(pclk), which is far away from 2795 * satisftying the requirement, as pclk is usually near 2796 * 100MHz shared by all peripherals. So the fact is it 2797 * has crippled debounce capability could only be useful 2798 * to prevent any spurious glitches from waking up the system 2799 * if the gpio is conguired as wakeup interrupt source. Let's 2800 * still return -ENOTSUPP as before, to make sure the caller 2801 * of gpiod_set_debounce won't change its behaviour. 2802 */ 2803 default: 2804 return -ENOTSUPP; 2805 } 2806 } 2807 2808 /* 2809 * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin 2810 * and a virtual IRQ, if not already present. 2811 */ 2812 static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset) 2813 { 2814 struct rockchip_pin_bank *bank = gpiochip_get_data(gc); 2815 unsigned int virq; 2816 2817 if (!bank->domain) 2818 return -ENXIO; 2819 2820 virq = irq_create_mapping(bank->domain, offset); 2821 2822 return (virq) ? : -ENXIO; 2823 } 2824 2825 static const struct gpio_chip rockchip_gpiolib_chip = { 2826 .request = gpiochip_generic_request, 2827 .free = gpiochip_generic_free, 2828 .set = rockchip_gpio_set, 2829 .get = rockchip_gpio_get, 2830 .get_direction = rockchip_gpio_get_direction, 2831 .direction_input = rockchip_gpio_direction_input, 2832 .direction_output = rockchip_gpio_direction_output, 2833 .set_config = rockchip_gpio_set_config, 2834 .to_irq = rockchip_gpio_to_irq, 2835 .owner = THIS_MODULE, 2836 }; 2837 2838 /* 2839 * Interrupt handling 2840 */ 2841 2842 static void rockchip_irq_demux(struct irq_desc *desc) 2843 { 2844 struct irq_chip *chip = irq_desc_get_chip(desc); 2845 struct rockchip_pin_bank *bank = irq_desc_get_handler_data(desc); 2846 u32 pend; 2847 2848 dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name); 2849 2850 chained_irq_enter(chip, desc); 2851 2852 pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS); 2853 2854 while (pend) { 2855 unsigned int irq, virq; 2856 2857 irq = __ffs(pend); 2858 pend &= ~BIT(irq); 2859 virq = irq_linear_revmap(bank->domain, irq); 2860 2861 if (!virq) { 2862 dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq); 2863 continue; 2864 } 2865 2866 dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq); 2867 2868 /* 2869 * Triggering IRQ on both rising and falling edge 2870 * needs manual intervention. 2871 */ 2872 if (bank->toggle_edge_mode & BIT(irq)) { 2873 u32 data, data_old, polarity; 2874 unsigned long flags; 2875 2876 data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT); 2877 do { 2878 raw_spin_lock_irqsave(&bank->slock, flags); 2879 2880 polarity = readl_relaxed(bank->reg_base + 2881 GPIO_INT_POLARITY); 2882 if (data & BIT(irq)) 2883 polarity &= ~BIT(irq); 2884 else 2885 polarity |= BIT(irq); 2886 writel(polarity, 2887 bank->reg_base + GPIO_INT_POLARITY); 2888 2889 raw_spin_unlock_irqrestore(&bank->slock, flags); 2890 2891 data_old = data; 2892 data = readl_relaxed(bank->reg_base + 2893 GPIO_EXT_PORT); 2894 } while ((data & BIT(irq)) != (data_old & BIT(irq))); 2895 } 2896 2897 generic_handle_irq(virq); 2898 } 2899 2900 chained_irq_exit(chip, desc); 2901 } 2902 2903 static int rockchip_irq_set_type(struct irq_data *d, unsigned int type) 2904 { 2905 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 2906 struct rockchip_pin_bank *bank = gc->private; 2907 u32 mask = BIT(d->hwirq); 2908 u32 polarity; 2909 u32 level; 2910 u32 data; 2911 unsigned long flags; 2912 int ret; 2913 2914 /* make sure the pin is configured as gpio input */ 2915 ret = rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO); 2916 if (ret < 0) 2917 return ret; 2918 2919 clk_enable(bank->clk); 2920 raw_spin_lock_irqsave(&bank->slock, flags); 2921 2922 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); 2923 data &= ~mask; 2924 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR); 2925 2926 raw_spin_unlock_irqrestore(&bank->slock, flags); 2927 2928 if (type & IRQ_TYPE_EDGE_BOTH) 2929 irq_set_handler_locked(d, handle_edge_irq); 2930 else 2931 irq_set_handler_locked(d, handle_level_irq); 2932 2933 raw_spin_lock_irqsave(&bank->slock, flags); 2934 irq_gc_lock(gc); 2935 2936 level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL); 2937 polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY); 2938 2939 switch (type) { 2940 case IRQ_TYPE_EDGE_BOTH: 2941 bank->toggle_edge_mode |= mask; 2942 level |= mask; 2943 2944 /* 2945 * Determine gpio state. If 1 next interrupt should be falling 2946 * otherwise rising. 2947 */ 2948 data = readl(bank->reg_base + GPIO_EXT_PORT); 2949 if (data & mask) 2950 polarity &= ~mask; 2951 else 2952 polarity |= mask; 2953 break; 2954 case IRQ_TYPE_EDGE_RISING: 2955 bank->toggle_edge_mode &= ~mask; 2956 level |= mask; 2957 polarity |= mask; 2958 break; 2959 case IRQ_TYPE_EDGE_FALLING: 2960 bank->toggle_edge_mode &= ~mask; 2961 level |= mask; 2962 polarity &= ~mask; 2963 break; 2964 case IRQ_TYPE_LEVEL_HIGH: 2965 bank->toggle_edge_mode &= ~mask; 2966 level &= ~mask; 2967 polarity |= mask; 2968 break; 2969 case IRQ_TYPE_LEVEL_LOW: 2970 bank->toggle_edge_mode &= ~mask; 2971 level &= ~mask; 2972 polarity &= ~mask; 2973 break; 2974 default: 2975 irq_gc_unlock(gc); 2976 raw_spin_unlock_irqrestore(&bank->slock, flags); 2977 clk_disable(bank->clk); 2978 return -EINVAL; 2979 } 2980 2981 writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL); 2982 writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY); 2983 2984 irq_gc_unlock(gc); 2985 raw_spin_unlock_irqrestore(&bank->slock, flags); 2986 clk_disable(bank->clk); 2987 2988 return 0; 2989 } 2990 2991 static void rockchip_irq_suspend(struct irq_data *d) 2992 { 2993 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 2994 struct rockchip_pin_bank *bank = gc->private; 2995 2996 clk_enable(bank->clk); 2997 bank->saved_masks = irq_reg_readl(gc, GPIO_INTMASK); 2998 irq_reg_writel(gc, ~gc->wake_active, GPIO_INTMASK); 2999 clk_disable(bank->clk); 3000 } 3001 3002 static void rockchip_irq_resume(struct irq_data *d) 3003 { 3004 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 3005 struct rockchip_pin_bank *bank = gc->private; 3006 3007 clk_enable(bank->clk); 3008 irq_reg_writel(gc, bank->saved_masks, GPIO_INTMASK); 3009 clk_disable(bank->clk); 3010 } 3011 3012 static void rockchip_irq_enable(struct irq_data *d) 3013 { 3014 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 3015 struct rockchip_pin_bank *bank = gc->private; 3016 3017 clk_enable(bank->clk); 3018 irq_gc_mask_clr_bit(d); 3019 } 3020 3021 static void rockchip_irq_disable(struct irq_data *d) 3022 { 3023 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 3024 struct rockchip_pin_bank *bank = gc->private; 3025 3026 irq_gc_mask_set_bit(d); 3027 clk_disable(bank->clk); 3028 } 3029 3030 static int rockchip_interrupts_register(struct platform_device *pdev, 3031 struct rockchip_pinctrl *info) 3032 { 3033 struct rockchip_pin_ctrl *ctrl = info->ctrl; 3034 struct rockchip_pin_bank *bank = ctrl->pin_banks; 3035 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; 3036 struct irq_chip_generic *gc; 3037 int ret; 3038 int i, j; 3039 3040 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 3041 if (!bank->valid) { 3042 dev_warn(&pdev->dev, "bank %s is not valid\n", 3043 bank->name); 3044 continue; 3045 } 3046 3047 ret = clk_enable(bank->clk); 3048 if (ret) { 3049 dev_err(&pdev->dev, "failed to enable clock for bank %s\n", 3050 bank->name); 3051 continue; 3052 } 3053 3054 bank->domain = irq_domain_add_linear(bank->of_node, 32, 3055 &irq_generic_chip_ops, NULL); 3056 if (!bank->domain) { 3057 dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n", 3058 bank->name); 3059 clk_disable(bank->clk); 3060 continue; 3061 } 3062 3063 ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1, 3064 "rockchip_gpio_irq", handle_level_irq, 3065 clr, 0, IRQ_GC_INIT_MASK_CACHE); 3066 if (ret) { 3067 dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n", 3068 bank->name); 3069 irq_domain_remove(bank->domain); 3070 clk_disable(bank->clk); 3071 continue; 3072 } 3073 3074 /* 3075 * Linux assumes that all interrupts start out disabled/masked. 3076 * Our driver only uses the concept of masked and always keeps 3077 * things enabled, so for us that's all masked and all enabled. 3078 */ 3079 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTMASK); 3080 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTEN); 3081 3082 gc = irq_get_domain_generic_chip(bank->domain, 0); 3083 gc->reg_base = bank->reg_base; 3084 gc->private = bank; 3085 gc->chip_types[0].regs.mask = GPIO_INTMASK; 3086 gc->chip_types[0].regs.ack = GPIO_PORTS_EOI; 3087 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit; 3088 gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit; 3089 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit; 3090 gc->chip_types[0].chip.irq_enable = rockchip_irq_enable; 3091 gc->chip_types[0].chip.irq_disable = rockchip_irq_disable; 3092 gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake; 3093 gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend; 3094 gc->chip_types[0].chip.irq_resume = rockchip_irq_resume; 3095 gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type; 3096 gc->wake_enabled = IRQ_MSK(bank->nr_pins); 3097 3098 irq_set_chained_handler_and_data(bank->irq, 3099 rockchip_irq_demux, bank); 3100 3101 /* map the gpio irqs here, when the clock is still running */ 3102 for (j = 0 ; j < 32 ; j++) 3103 irq_create_mapping(bank->domain, j); 3104 3105 clk_disable(bank->clk); 3106 } 3107 3108 return 0; 3109 } 3110 3111 static int rockchip_gpiolib_register(struct platform_device *pdev, 3112 struct rockchip_pinctrl *info) 3113 { 3114 struct rockchip_pin_ctrl *ctrl = info->ctrl; 3115 struct rockchip_pin_bank *bank = ctrl->pin_banks; 3116 struct gpio_chip *gc; 3117 int ret; 3118 int i; 3119 3120 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 3121 if (!bank->valid) { 3122 dev_warn(&pdev->dev, "bank %s is not valid\n", 3123 bank->name); 3124 continue; 3125 } 3126 3127 bank->gpio_chip = rockchip_gpiolib_chip; 3128 3129 gc = &bank->gpio_chip; 3130 gc->base = bank->pin_base; 3131 gc->ngpio = bank->nr_pins; 3132 gc->parent = &pdev->dev; 3133 gc->of_node = bank->of_node; 3134 gc->label = bank->name; 3135 3136 ret = gpiochip_add_data(gc, bank); 3137 if (ret) { 3138 dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n", 3139 gc->label, ret); 3140 goto fail; 3141 } 3142 } 3143 3144 rockchip_interrupts_register(pdev, info); 3145 3146 return 0; 3147 3148 fail: 3149 for (--i, --bank; i >= 0; --i, --bank) { 3150 if (!bank->valid) 3151 continue; 3152 gpiochip_remove(&bank->gpio_chip); 3153 } 3154 return ret; 3155 } 3156 3157 static int rockchip_gpiolib_unregister(struct platform_device *pdev, 3158 struct rockchip_pinctrl *info) 3159 { 3160 struct rockchip_pin_ctrl *ctrl = info->ctrl; 3161 struct rockchip_pin_bank *bank = ctrl->pin_banks; 3162 int i; 3163 3164 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 3165 if (!bank->valid) 3166 continue; 3167 gpiochip_remove(&bank->gpio_chip); 3168 } 3169 3170 return 0; 3171 } 3172 3173 static int rockchip_get_bank_data(struct rockchip_pin_bank *bank, 3174 struct rockchip_pinctrl *info) 3175 { 3176 struct resource res; 3177 void __iomem *base; 3178 3179 if (of_address_to_resource(bank->of_node, 0, &res)) { 3180 dev_err(info->dev, "cannot find IO resource for bank\n"); 3181 return -ENOENT; 3182 } 3183 3184 bank->reg_base = devm_ioremap_resource(info->dev, &res); 3185 if (IS_ERR(bank->reg_base)) 3186 return PTR_ERR(bank->reg_base); 3187 3188 /* 3189 * special case, where parts of the pull setting-registers are 3190 * part of the PMU register space 3191 */ 3192 if (of_device_is_compatible(bank->of_node, 3193 "rockchip,rk3188-gpio-bank0")) { 3194 struct device_node *node; 3195 3196 node = of_parse_phandle(bank->of_node->parent, 3197 "rockchip,pmu", 0); 3198 if (!node) { 3199 if (of_address_to_resource(bank->of_node, 1, &res)) { 3200 dev_err(info->dev, "cannot find IO resource for bank\n"); 3201 return -ENOENT; 3202 } 3203 3204 base = devm_ioremap_resource(info->dev, &res); 3205 if (IS_ERR(base)) 3206 return PTR_ERR(base); 3207 rockchip_regmap_config.max_register = 3208 resource_size(&res) - 4; 3209 rockchip_regmap_config.name = 3210 "rockchip,rk3188-gpio-bank0-pull"; 3211 bank->regmap_pull = devm_regmap_init_mmio(info->dev, 3212 base, 3213 &rockchip_regmap_config); 3214 } 3215 } 3216 3217 bank->irq = irq_of_parse_and_map(bank->of_node, 0); 3218 3219 bank->clk = of_clk_get(bank->of_node, 0); 3220 if (IS_ERR(bank->clk)) 3221 return PTR_ERR(bank->clk); 3222 3223 return clk_prepare(bank->clk); 3224 } 3225 3226 static const struct of_device_id rockchip_pinctrl_dt_match[]; 3227 3228 /* retrieve the soc specific data */ 3229 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data( 3230 struct rockchip_pinctrl *d, 3231 struct platform_device *pdev) 3232 { 3233 const struct of_device_id *match; 3234 struct device_node *node = pdev->dev.of_node; 3235 struct device_node *np; 3236 struct rockchip_pin_ctrl *ctrl; 3237 struct rockchip_pin_bank *bank; 3238 int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j; 3239 3240 match = of_match_node(rockchip_pinctrl_dt_match, node); 3241 ctrl = (struct rockchip_pin_ctrl *)match->data; 3242 3243 for_each_child_of_node(node, np) { 3244 if (!of_find_property(np, "gpio-controller", NULL)) 3245 continue; 3246 3247 bank = ctrl->pin_banks; 3248 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 3249 if (!strcmp(bank->name, np->name)) { 3250 bank->of_node = np; 3251 3252 if (!rockchip_get_bank_data(bank, d)) 3253 bank->valid = true; 3254 3255 break; 3256 } 3257 } 3258 } 3259 3260 grf_offs = ctrl->grf_mux_offset; 3261 pmu_offs = ctrl->pmu_mux_offset; 3262 drv_pmu_offs = ctrl->pmu_drv_offset; 3263 drv_grf_offs = ctrl->grf_drv_offset; 3264 bank = ctrl->pin_banks; 3265 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 3266 int bank_pins = 0; 3267 3268 raw_spin_lock_init(&bank->slock); 3269 bank->drvdata = d; 3270 bank->pin_base = ctrl->nr_pins; 3271 ctrl->nr_pins += bank->nr_pins; 3272 3273 /* calculate iomux and drv offsets */ 3274 for (j = 0; j < 4; j++) { 3275 struct rockchip_iomux *iom = &bank->iomux[j]; 3276 struct rockchip_drv *drv = &bank->drv[j]; 3277 int inc; 3278 3279 if (bank_pins >= bank->nr_pins) 3280 break; 3281 3282 /* preset iomux offset value, set new start value */ 3283 if (iom->offset >= 0) { 3284 if (iom->type & IOMUX_SOURCE_PMU) 3285 pmu_offs = iom->offset; 3286 else 3287 grf_offs = iom->offset; 3288 } else { /* set current iomux offset */ 3289 iom->offset = (iom->type & IOMUX_SOURCE_PMU) ? 3290 pmu_offs : grf_offs; 3291 } 3292 3293 /* preset drv offset value, set new start value */ 3294 if (drv->offset >= 0) { 3295 if (iom->type & IOMUX_SOURCE_PMU) 3296 drv_pmu_offs = drv->offset; 3297 else 3298 drv_grf_offs = drv->offset; 3299 } else { /* set current drv offset */ 3300 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ? 3301 drv_pmu_offs : drv_grf_offs; 3302 } 3303 3304 dev_dbg(d->dev, "bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n", 3305 i, j, iom->offset, drv->offset); 3306 3307 /* 3308 * Increase offset according to iomux width. 3309 * 4bit iomux'es are spread over two registers. 3310 */ 3311 inc = (iom->type & (IOMUX_WIDTH_4BIT | 3312 IOMUX_WIDTH_3BIT)) ? 8 : 4; 3313 if (iom->type & IOMUX_SOURCE_PMU) 3314 pmu_offs += inc; 3315 else 3316 grf_offs += inc; 3317 3318 /* 3319 * Increase offset according to drv width. 3320 * 3bit drive-strenth'es are spread over two registers. 3321 */ 3322 if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) || 3323 (drv->drv_type == DRV_TYPE_IO_3V3_ONLY)) 3324 inc = 8; 3325 else 3326 inc = 4; 3327 3328 if (iom->type & IOMUX_SOURCE_PMU) 3329 drv_pmu_offs += inc; 3330 else 3331 drv_grf_offs += inc; 3332 3333 bank_pins += 8; 3334 } 3335 3336 /* calculate the per-bank recalced_mask */ 3337 for (j = 0; j < ctrl->niomux_recalced; j++) { 3338 int pin = 0; 3339 3340 if (ctrl->iomux_recalced[j].num == bank->bank_num) { 3341 pin = ctrl->iomux_recalced[j].pin; 3342 bank->recalced_mask |= BIT(pin); 3343 } 3344 } 3345 3346 /* calculate the per-bank route_mask */ 3347 for (j = 0; j < ctrl->niomux_routes; j++) { 3348 int pin = 0; 3349 3350 if (ctrl->iomux_routes[j].bank_num == bank->bank_num) { 3351 pin = ctrl->iomux_routes[j].pin; 3352 bank->route_mask |= BIT(pin); 3353 } 3354 } 3355 } 3356 3357 return ctrl; 3358 } 3359 3360 #define RK3288_GRF_GPIO6C_IOMUX 0x64 3361 #define GPIO6C6_SEL_WRITE_ENABLE BIT(28) 3362 3363 static u32 rk3288_grf_gpio6c_iomux; 3364 3365 static int __maybe_unused rockchip_pinctrl_suspend(struct device *dev) 3366 { 3367 struct rockchip_pinctrl *info = dev_get_drvdata(dev); 3368 int ret = pinctrl_force_sleep(info->pctl_dev); 3369 3370 if (ret) 3371 return ret; 3372 3373 /* 3374 * RK3288 GPIO6_C6 mux would be modified by Maskrom when resume, so save 3375 * the setting here, and restore it at resume. 3376 */ 3377 if (info->ctrl->type == RK3288) { 3378 ret = regmap_read(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX, 3379 &rk3288_grf_gpio6c_iomux); 3380 if (ret) { 3381 pinctrl_force_default(info->pctl_dev); 3382 return ret; 3383 } 3384 } 3385 3386 return 0; 3387 } 3388 3389 static int __maybe_unused rockchip_pinctrl_resume(struct device *dev) 3390 { 3391 struct rockchip_pinctrl *info = dev_get_drvdata(dev); 3392 int ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX, 3393 rk3288_grf_gpio6c_iomux | 3394 GPIO6C6_SEL_WRITE_ENABLE); 3395 3396 if (ret) 3397 return ret; 3398 3399 return pinctrl_force_default(info->pctl_dev); 3400 } 3401 3402 static SIMPLE_DEV_PM_OPS(rockchip_pinctrl_dev_pm_ops, rockchip_pinctrl_suspend, 3403 rockchip_pinctrl_resume); 3404 3405 static int rockchip_pinctrl_probe(struct platform_device *pdev) 3406 { 3407 struct rockchip_pinctrl *info; 3408 struct device *dev = &pdev->dev; 3409 struct rockchip_pin_ctrl *ctrl; 3410 struct device_node *np = pdev->dev.of_node, *node; 3411 struct resource *res; 3412 void __iomem *base; 3413 int ret; 3414 3415 if (!dev->of_node) { 3416 dev_err(dev, "device tree node not found\n"); 3417 return -ENODEV; 3418 } 3419 3420 info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL); 3421 if (!info) 3422 return -ENOMEM; 3423 3424 info->dev = dev; 3425 3426 ctrl = rockchip_pinctrl_get_soc_data(info, pdev); 3427 if (!ctrl) { 3428 dev_err(dev, "driver data not available\n"); 3429 return -EINVAL; 3430 } 3431 info->ctrl = ctrl; 3432 3433 node = of_parse_phandle(np, "rockchip,grf", 0); 3434 if (node) { 3435 info->regmap_base = syscon_node_to_regmap(node); 3436 if (IS_ERR(info->regmap_base)) 3437 return PTR_ERR(info->regmap_base); 3438 } else { 3439 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 3440 base = devm_ioremap_resource(&pdev->dev, res); 3441 if (IS_ERR(base)) 3442 return PTR_ERR(base); 3443 3444 rockchip_regmap_config.max_register = resource_size(res) - 4; 3445 rockchip_regmap_config.name = "rockchip,pinctrl"; 3446 info->regmap_base = devm_regmap_init_mmio(&pdev->dev, base, 3447 &rockchip_regmap_config); 3448 3449 /* to check for the old dt-bindings */ 3450 info->reg_size = resource_size(res); 3451 3452 /* Honor the old binding, with pull registers as 2nd resource */ 3453 if (ctrl->type == RK3188 && info->reg_size < 0x200) { 3454 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 3455 base = devm_ioremap_resource(&pdev->dev, res); 3456 if (IS_ERR(base)) 3457 return PTR_ERR(base); 3458 3459 rockchip_regmap_config.max_register = 3460 resource_size(res) - 4; 3461 rockchip_regmap_config.name = "rockchip,pinctrl-pull"; 3462 info->regmap_pull = devm_regmap_init_mmio(&pdev->dev, 3463 base, 3464 &rockchip_regmap_config); 3465 } 3466 } 3467 3468 /* try to find the optional reference to the pmu syscon */ 3469 node = of_parse_phandle(np, "rockchip,pmu", 0); 3470 if (node) { 3471 info->regmap_pmu = syscon_node_to_regmap(node); 3472 if (IS_ERR(info->regmap_pmu)) 3473 return PTR_ERR(info->regmap_pmu); 3474 } 3475 3476 ret = rockchip_gpiolib_register(pdev, info); 3477 if (ret) 3478 return ret; 3479 3480 ret = rockchip_pinctrl_register(pdev, info); 3481 if (ret) { 3482 rockchip_gpiolib_unregister(pdev, info); 3483 return ret; 3484 } 3485 3486 platform_set_drvdata(pdev, info); 3487 3488 return 0; 3489 } 3490 3491 static struct rockchip_pin_bank px30_pin_banks[] = { 3492 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, 3493 IOMUX_SOURCE_PMU, 3494 IOMUX_SOURCE_PMU, 3495 IOMUX_SOURCE_PMU 3496 ), 3497 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT, 3498 IOMUX_WIDTH_4BIT, 3499 IOMUX_WIDTH_4BIT, 3500 IOMUX_WIDTH_4BIT 3501 ), 3502 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT, 3503 IOMUX_WIDTH_4BIT, 3504 IOMUX_WIDTH_4BIT, 3505 IOMUX_WIDTH_4BIT 3506 ), 3507 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT, 3508 IOMUX_WIDTH_4BIT, 3509 IOMUX_WIDTH_4BIT, 3510 IOMUX_WIDTH_4BIT 3511 ), 3512 }; 3513 3514 static struct rockchip_pin_ctrl px30_pin_ctrl = { 3515 .pin_banks = px30_pin_banks, 3516 .nr_banks = ARRAY_SIZE(px30_pin_banks), 3517 .label = "PX30-GPIO", 3518 .type = PX30, 3519 .grf_mux_offset = 0x0, 3520 .pmu_mux_offset = 0x0, 3521 .iomux_routes = px30_mux_route_data, 3522 .niomux_routes = ARRAY_SIZE(px30_mux_route_data), 3523 .pull_calc_reg = px30_calc_pull_reg_and_bit, 3524 .drv_calc_reg = px30_calc_drv_reg_and_bit, 3525 .schmitt_calc_reg = px30_calc_schmitt_reg_and_bit, 3526 }; 3527 3528 static struct rockchip_pin_bank rv1108_pin_banks[] = { 3529 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, 3530 IOMUX_SOURCE_PMU, 3531 IOMUX_SOURCE_PMU, 3532 IOMUX_SOURCE_PMU), 3533 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0), 3534 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0), 3535 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0), 3536 }; 3537 3538 static struct rockchip_pin_ctrl rv1108_pin_ctrl = { 3539 .pin_banks = rv1108_pin_banks, 3540 .nr_banks = ARRAY_SIZE(rv1108_pin_banks), 3541 .label = "RV1108-GPIO", 3542 .type = RV1108, 3543 .grf_mux_offset = 0x10, 3544 .pmu_mux_offset = 0x0, 3545 .iomux_recalced = rv1108_mux_recalced_data, 3546 .niomux_recalced = ARRAY_SIZE(rv1108_mux_recalced_data), 3547 .pull_calc_reg = rv1108_calc_pull_reg_and_bit, 3548 .drv_calc_reg = rv1108_calc_drv_reg_and_bit, 3549 .schmitt_calc_reg = rv1108_calc_schmitt_reg_and_bit, 3550 }; 3551 3552 static struct rockchip_pin_bank rk2928_pin_banks[] = { 3553 PIN_BANK(0, 32, "gpio0"), 3554 PIN_BANK(1, 32, "gpio1"), 3555 PIN_BANK(2, 32, "gpio2"), 3556 PIN_BANK(3, 32, "gpio3"), 3557 }; 3558 3559 static struct rockchip_pin_ctrl rk2928_pin_ctrl = { 3560 .pin_banks = rk2928_pin_banks, 3561 .nr_banks = ARRAY_SIZE(rk2928_pin_banks), 3562 .label = "RK2928-GPIO", 3563 .type = RK2928, 3564 .grf_mux_offset = 0xa8, 3565 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 3566 }; 3567 3568 static struct rockchip_pin_bank rk3036_pin_banks[] = { 3569 PIN_BANK(0, 32, "gpio0"), 3570 PIN_BANK(1, 32, "gpio1"), 3571 PIN_BANK(2, 32, "gpio2"), 3572 }; 3573 3574 static struct rockchip_pin_ctrl rk3036_pin_ctrl = { 3575 .pin_banks = rk3036_pin_banks, 3576 .nr_banks = ARRAY_SIZE(rk3036_pin_banks), 3577 .label = "RK3036-GPIO", 3578 .type = RK2928, 3579 .grf_mux_offset = 0xa8, 3580 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 3581 }; 3582 3583 static struct rockchip_pin_bank rk3066a_pin_banks[] = { 3584 PIN_BANK(0, 32, "gpio0"), 3585 PIN_BANK(1, 32, "gpio1"), 3586 PIN_BANK(2, 32, "gpio2"), 3587 PIN_BANK(3, 32, "gpio3"), 3588 PIN_BANK(4, 32, "gpio4"), 3589 PIN_BANK(6, 16, "gpio6"), 3590 }; 3591 3592 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = { 3593 .pin_banks = rk3066a_pin_banks, 3594 .nr_banks = ARRAY_SIZE(rk3066a_pin_banks), 3595 .label = "RK3066a-GPIO", 3596 .type = RK2928, 3597 .grf_mux_offset = 0xa8, 3598 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 3599 }; 3600 3601 static struct rockchip_pin_bank rk3066b_pin_banks[] = { 3602 PIN_BANK(0, 32, "gpio0"), 3603 PIN_BANK(1, 32, "gpio1"), 3604 PIN_BANK(2, 32, "gpio2"), 3605 PIN_BANK(3, 32, "gpio3"), 3606 }; 3607 3608 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = { 3609 .pin_banks = rk3066b_pin_banks, 3610 .nr_banks = ARRAY_SIZE(rk3066b_pin_banks), 3611 .label = "RK3066b-GPIO", 3612 .type = RK3066B, 3613 .grf_mux_offset = 0x60, 3614 }; 3615 3616 static struct rockchip_pin_bank rk3128_pin_banks[] = { 3617 PIN_BANK(0, 32, "gpio0"), 3618 PIN_BANK(1, 32, "gpio1"), 3619 PIN_BANK(2, 32, "gpio2"), 3620 PIN_BANK(3, 32, "gpio3"), 3621 }; 3622 3623 static struct rockchip_pin_ctrl rk3128_pin_ctrl = { 3624 .pin_banks = rk3128_pin_banks, 3625 .nr_banks = ARRAY_SIZE(rk3128_pin_banks), 3626 .label = "RK3128-GPIO", 3627 .type = RK3128, 3628 .grf_mux_offset = 0xa8, 3629 .iomux_recalced = rk3128_mux_recalced_data, 3630 .niomux_recalced = ARRAY_SIZE(rk3128_mux_recalced_data), 3631 .iomux_routes = rk3128_mux_route_data, 3632 .niomux_routes = ARRAY_SIZE(rk3128_mux_route_data), 3633 .pull_calc_reg = rk3128_calc_pull_reg_and_bit, 3634 }; 3635 3636 static struct rockchip_pin_bank rk3188_pin_banks[] = { 3637 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0), 3638 PIN_BANK(1, 32, "gpio1"), 3639 PIN_BANK(2, 32, "gpio2"), 3640 PIN_BANK(3, 32, "gpio3"), 3641 }; 3642 3643 static struct rockchip_pin_ctrl rk3188_pin_ctrl = { 3644 .pin_banks = rk3188_pin_banks, 3645 .nr_banks = ARRAY_SIZE(rk3188_pin_banks), 3646 .label = "RK3188-GPIO", 3647 .type = RK3188, 3648 .grf_mux_offset = 0x60, 3649 .iomux_routes = rk3188_mux_route_data, 3650 .niomux_routes = ARRAY_SIZE(rk3188_mux_route_data), 3651 .pull_calc_reg = rk3188_calc_pull_reg_and_bit, 3652 }; 3653 3654 static struct rockchip_pin_bank rk3228_pin_banks[] = { 3655 PIN_BANK(0, 32, "gpio0"), 3656 PIN_BANK(1, 32, "gpio1"), 3657 PIN_BANK(2, 32, "gpio2"), 3658 PIN_BANK(3, 32, "gpio3"), 3659 }; 3660 3661 static struct rockchip_pin_ctrl rk3228_pin_ctrl = { 3662 .pin_banks = rk3228_pin_banks, 3663 .nr_banks = ARRAY_SIZE(rk3228_pin_banks), 3664 .label = "RK3228-GPIO", 3665 .type = RK3288, 3666 .grf_mux_offset = 0x0, 3667 .iomux_routes = rk3228_mux_route_data, 3668 .niomux_routes = ARRAY_SIZE(rk3228_mux_route_data), 3669 .pull_calc_reg = rk3228_calc_pull_reg_and_bit, 3670 .drv_calc_reg = rk3228_calc_drv_reg_and_bit, 3671 }; 3672 3673 static struct rockchip_pin_bank rk3288_pin_banks[] = { 3674 PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU, 3675 IOMUX_SOURCE_PMU, 3676 IOMUX_SOURCE_PMU, 3677 IOMUX_UNROUTED 3678 ), 3679 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED, 3680 IOMUX_UNROUTED, 3681 IOMUX_UNROUTED, 3682 0 3683 ), 3684 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED), 3685 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT), 3686 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT, 3687 IOMUX_WIDTH_4BIT, 3688 0, 3689 0 3690 ), 3691 PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED, 3692 0, 3693 0, 3694 IOMUX_UNROUTED 3695 ), 3696 PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED), 3697 PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0, 3698 0, 3699 IOMUX_WIDTH_4BIT, 3700 IOMUX_UNROUTED 3701 ), 3702 PIN_BANK(8, 16, "gpio8"), 3703 }; 3704 3705 static struct rockchip_pin_ctrl rk3288_pin_ctrl = { 3706 .pin_banks = rk3288_pin_banks, 3707 .nr_banks = ARRAY_SIZE(rk3288_pin_banks), 3708 .label = "RK3288-GPIO", 3709 .type = RK3288, 3710 .grf_mux_offset = 0x0, 3711 .pmu_mux_offset = 0x84, 3712 .iomux_routes = rk3288_mux_route_data, 3713 .niomux_routes = ARRAY_SIZE(rk3288_mux_route_data), 3714 .pull_calc_reg = rk3288_calc_pull_reg_and_bit, 3715 .drv_calc_reg = rk3288_calc_drv_reg_and_bit, 3716 }; 3717 3718 static struct rockchip_pin_bank rk3328_pin_banks[] = { 3719 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0), 3720 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0), 3721 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 3722 IOMUX_WIDTH_3BIT, 3723 IOMUX_WIDTH_3BIT, 3724 0), 3725 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 3726 IOMUX_WIDTH_3BIT, 3727 IOMUX_WIDTH_3BIT, 3728 0, 3729 0), 3730 }; 3731 3732 static struct rockchip_pin_ctrl rk3328_pin_ctrl = { 3733 .pin_banks = rk3328_pin_banks, 3734 .nr_banks = ARRAY_SIZE(rk3328_pin_banks), 3735 .label = "RK3328-GPIO", 3736 .type = RK3288, 3737 .grf_mux_offset = 0x0, 3738 .iomux_recalced = rk3328_mux_recalced_data, 3739 .niomux_recalced = ARRAY_SIZE(rk3328_mux_recalced_data), 3740 .iomux_routes = rk3328_mux_route_data, 3741 .niomux_routes = ARRAY_SIZE(rk3328_mux_route_data), 3742 .pull_calc_reg = rk3228_calc_pull_reg_and_bit, 3743 .drv_calc_reg = rk3228_calc_drv_reg_and_bit, 3744 .schmitt_calc_reg = rk3328_calc_schmitt_reg_and_bit, 3745 }; 3746 3747 static struct rockchip_pin_bank rk3368_pin_banks[] = { 3748 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, 3749 IOMUX_SOURCE_PMU, 3750 IOMUX_SOURCE_PMU, 3751 IOMUX_SOURCE_PMU 3752 ), 3753 PIN_BANK(1, 32, "gpio1"), 3754 PIN_BANK(2, 32, "gpio2"), 3755 PIN_BANK(3, 32, "gpio3"), 3756 }; 3757 3758 static struct rockchip_pin_ctrl rk3368_pin_ctrl = { 3759 .pin_banks = rk3368_pin_banks, 3760 .nr_banks = ARRAY_SIZE(rk3368_pin_banks), 3761 .label = "RK3368-GPIO", 3762 .type = RK3368, 3763 .grf_mux_offset = 0x0, 3764 .pmu_mux_offset = 0x0, 3765 .pull_calc_reg = rk3368_calc_pull_reg_and_bit, 3766 .drv_calc_reg = rk3368_calc_drv_reg_and_bit, 3767 }; 3768 3769 static struct rockchip_pin_bank rk3399_pin_banks[] = { 3770 PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0", 3771 IOMUX_SOURCE_PMU, 3772 IOMUX_SOURCE_PMU, 3773 IOMUX_SOURCE_PMU, 3774 IOMUX_SOURCE_PMU, 3775 DRV_TYPE_IO_1V8_ONLY, 3776 DRV_TYPE_IO_1V8_ONLY, 3777 DRV_TYPE_IO_DEFAULT, 3778 DRV_TYPE_IO_DEFAULT, 3779 0x80, 3780 0x88, 3781 -1, 3782 -1, 3783 PULL_TYPE_IO_1V8_ONLY, 3784 PULL_TYPE_IO_1V8_ONLY, 3785 PULL_TYPE_IO_DEFAULT, 3786 PULL_TYPE_IO_DEFAULT 3787 ), 3788 PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU, 3789 IOMUX_SOURCE_PMU, 3790 IOMUX_SOURCE_PMU, 3791 IOMUX_SOURCE_PMU, 3792 DRV_TYPE_IO_1V8_OR_3V0, 3793 DRV_TYPE_IO_1V8_OR_3V0, 3794 DRV_TYPE_IO_1V8_OR_3V0, 3795 DRV_TYPE_IO_1V8_OR_3V0, 3796 0xa0, 3797 0xa8, 3798 0xb0, 3799 0xb8 3800 ), 3801 PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0, 3802 DRV_TYPE_IO_1V8_OR_3V0, 3803 DRV_TYPE_IO_1V8_ONLY, 3804 DRV_TYPE_IO_1V8_ONLY, 3805 PULL_TYPE_IO_DEFAULT, 3806 PULL_TYPE_IO_DEFAULT, 3807 PULL_TYPE_IO_1V8_ONLY, 3808 PULL_TYPE_IO_1V8_ONLY 3809 ), 3810 PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY, 3811 DRV_TYPE_IO_3V3_ONLY, 3812 DRV_TYPE_IO_3V3_ONLY, 3813 DRV_TYPE_IO_1V8_OR_3V0 3814 ), 3815 PIN_BANK_DRV_FLAGS(4, 32, "gpio4", DRV_TYPE_IO_1V8_OR_3V0, 3816 DRV_TYPE_IO_1V8_3V0_AUTO, 3817 DRV_TYPE_IO_1V8_OR_3V0, 3818 DRV_TYPE_IO_1V8_OR_3V0 3819 ), 3820 }; 3821 3822 static struct rockchip_pin_ctrl rk3399_pin_ctrl = { 3823 .pin_banks = rk3399_pin_banks, 3824 .nr_banks = ARRAY_SIZE(rk3399_pin_banks), 3825 .label = "RK3399-GPIO", 3826 .type = RK3399, 3827 .grf_mux_offset = 0xe000, 3828 .pmu_mux_offset = 0x0, 3829 .grf_drv_offset = 0xe100, 3830 .pmu_drv_offset = 0x80, 3831 .iomux_routes = rk3399_mux_route_data, 3832 .niomux_routes = ARRAY_SIZE(rk3399_mux_route_data), 3833 .pull_calc_reg = rk3399_calc_pull_reg_and_bit, 3834 .drv_calc_reg = rk3399_calc_drv_reg_and_bit, 3835 }; 3836 3837 static const struct of_device_id rockchip_pinctrl_dt_match[] = { 3838 { .compatible = "rockchip,px30-pinctrl", 3839 .data = &px30_pin_ctrl }, 3840 { .compatible = "rockchip,rv1108-pinctrl", 3841 .data = &rv1108_pin_ctrl }, 3842 { .compatible = "rockchip,rk2928-pinctrl", 3843 .data = &rk2928_pin_ctrl }, 3844 { .compatible = "rockchip,rk3036-pinctrl", 3845 .data = &rk3036_pin_ctrl }, 3846 { .compatible = "rockchip,rk3066a-pinctrl", 3847 .data = &rk3066a_pin_ctrl }, 3848 { .compatible = "rockchip,rk3066b-pinctrl", 3849 .data = &rk3066b_pin_ctrl }, 3850 { .compatible = "rockchip,rk3128-pinctrl", 3851 .data = (void *)&rk3128_pin_ctrl }, 3852 { .compatible = "rockchip,rk3188-pinctrl", 3853 .data = &rk3188_pin_ctrl }, 3854 { .compatible = "rockchip,rk3228-pinctrl", 3855 .data = &rk3228_pin_ctrl }, 3856 { .compatible = "rockchip,rk3288-pinctrl", 3857 .data = &rk3288_pin_ctrl }, 3858 { .compatible = "rockchip,rk3328-pinctrl", 3859 .data = &rk3328_pin_ctrl }, 3860 { .compatible = "rockchip,rk3368-pinctrl", 3861 .data = &rk3368_pin_ctrl }, 3862 { .compatible = "rockchip,rk3399-pinctrl", 3863 .data = &rk3399_pin_ctrl }, 3864 {}, 3865 }; 3866 3867 static struct platform_driver rockchip_pinctrl_driver = { 3868 .probe = rockchip_pinctrl_probe, 3869 .driver = { 3870 .name = "rockchip-pinctrl", 3871 .pm = &rockchip_pinctrl_dev_pm_ops, 3872 .of_match_table = rockchip_pinctrl_dt_match, 3873 }, 3874 }; 3875 3876 static int __init rockchip_pinctrl_drv_register(void) 3877 { 3878 return platform_driver_register(&rockchip_pinctrl_driver); 3879 } 3880 postcore_initcall(rockchip_pinctrl_drv_register); 3881