1 /* 2 * Pinctrl driver for Rockchip SoCs 3 * 4 * Copyright (c) 2013 MundoReader S.L. 5 * Author: Heiko Stuebner <heiko@sntech.de> 6 * 7 * With some ideas taken from pinctrl-samsung: 8 * Copyright (c) 2012 Samsung Electronics Co., Ltd. 9 * http://www.samsung.com 10 * Copyright (c) 2012 Linaro Ltd 11 * http://www.linaro.org 12 * 13 * and pinctrl-at91: 14 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> 15 * 16 * This program is free software; you can redistribute it and/or modify 17 * it under the terms of the GNU General Public License version 2 as published 18 * by the Free Software Foundation. 19 * 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 */ 25 26 #include <linux/module.h> 27 #include <linux/platform_device.h> 28 #include <linux/io.h> 29 #include <linux/bitops.h> 30 #include <linux/gpio.h> 31 #include <linux/of_address.h> 32 #include <linux/of_irq.h> 33 #include <linux/pinctrl/machine.h> 34 #include <linux/pinctrl/pinconf.h> 35 #include <linux/pinctrl/pinctrl.h> 36 #include <linux/pinctrl/pinmux.h> 37 #include <linux/pinctrl/pinconf-generic.h> 38 #include <linux/irqchip/chained_irq.h> 39 #include <linux/clk.h> 40 #include <linux/regmap.h> 41 #include <linux/mfd/syscon.h> 42 #include <dt-bindings/pinctrl/rockchip.h> 43 44 #include "core.h" 45 #include "pinconf.h" 46 47 /* GPIO control registers */ 48 #define GPIO_SWPORT_DR 0x00 49 #define GPIO_SWPORT_DDR 0x04 50 #define GPIO_INTEN 0x30 51 #define GPIO_INTMASK 0x34 52 #define GPIO_INTTYPE_LEVEL 0x38 53 #define GPIO_INT_POLARITY 0x3c 54 #define GPIO_INT_STATUS 0x40 55 #define GPIO_INT_RAWSTATUS 0x44 56 #define GPIO_DEBOUNCE 0x48 57 #define GPIO_PORTS_EOI 0x4c 58 #define GPIO_EXT_PORT 0x50 59 #define GPIO_LS_SYNC 0x60 60 61 enum rockchip_pinctrl_type { 62 RK2928, 63 RK3066B, 64 RK3188, 65 RK3288, 66 RK3368, 67 }; 68 69 /** 70 * Encode variants of iomux registers into a type variable 71 */ 72 #define IOMUX_GPIO_ONLY BIT(0) 73 #define IOMUX_WIDTH_4BIT BIT(1) 74 #define IOMUX_SOURCE_PMU BIT(2) 75 #define IOMUX_UNROUTED BIT(3) 76 77 /** 78 * @type: iomux variant using IOMUX_* constants 79 * @offset: if initialized to -1 it will be autocalculated, by specifying 80 * an initial offset value the relevant source offset can be reset 81 * to a new value for autocalculating the following iomux registers. 82 */ 83 struct rockchip_iomux { 84 int type; 85 int offset; 86 }; 87 88 /** 89 * @reg_base: register base of the gpio bank 90 * @reg_pull: optional separate register for additional pull settings 91 * @clk: clock of the gpio bank 92 * @irq: interrupt of the gpio bank 93 * @saved_masks: Saved content of GPIO_INTEN at suspend time. 94 * @pin_base: first pin number 95 * @nr_pins: number of pins in this bank 96 * @name: name of the bank 97 * @bank_num: number of the bank, to account for holes 98 * @iomux: array describing the 4 iomux sources of the bank 99 * @valid: are all necessary informations present 100 * @of_node: dt node of this bank 101 * @drvdata: common pinctrl basedata 102 * @domain: irqdomain of the gpio bank 103 * @gpio_chip: gpiolib chip 104 * @grange: gpio range 105 * @slock: spinlock for the gpio bank 106 */ 107 struct rockchip_pin_bank { 108 void __iomem *reg_base; 109 struct regmap *regmap_pull; 110 struct clk *clk; 111 int irq; 112 u32 saved_masks; 113 u32 pin_base; 114 u8 nr_pins; 115 char *name; 116 u8 bank_num; 117 struct rockchip_iomux iomux[4]; 118 bool valid; 119 struct device_node *of_node; 120 struct rockchip_pinctrl *drvdata; 121 struct irq_domain *domain; 122 struct gpio_chip gpio_chip; 123 struct pinctrl_gpio_range grange; 124 spinlock_t slock; 125 u32 toggle_edge_mode; 126 }; 127 128 #define PIN_BANK(id, pins, label) \ 129 { \ 130 .bank_num = id, \ 131 .nr_pins = pins, \ 132 .name = label, \ 133 .iomux = { \ 134 { .offset = -1 }, \ 135 { .offset = -1 }, \ 136 { .offset = -1 }, \ 137 { .offset = -1 }, \ 138 }, \ 139 } 140 141 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \ 142 { \ 143 .bank_num = id, \ 144 .nr_pins = pins, \ 145 .name = label, \ 146 .iomux = { \ 147 { .type = iom0, .offset = -1 }, \ 148 { .type = iom1, .offset = -1 }, \ 149 { .type = iom2, .offset = -1 }, \ 150 { .type = iom3, .offset = -1 }, \ 151 }, \ 152 } 153 154 /** 155 */ 156 struct rockchip_pin_ctrl { 157 struct rockchip_pin_bank *pin_banks; 158 u32 nr_banks; 159 u32 nr_pins; 160 char *label; 161 enum rockchip_pinctrl_type type; 162 int grf_mux_offset; 163 int pmu_mux_offset; 164 void (*pull_calc_reg)(struct rockchip_pin_bank *bank, 165 int pin_num, struct regmap **regmap, 166 int *reg, u8 *bit); 167 void (*drv_calc_reg)(struct rockchip_pin_bank *bank, 168 int pin_num, struct regmap **regmap, 169 int *reg, u8 *bit); 170 }; 171 172 struct rockchip_pin_config { 173 unsigned int func; 174 unsigned long *configs; 175 unsigned int nconfigs; 176 }; 177 178 /** 179 * struct rockchip_pin_group: represent group of pins of a pinmux function. 180 * @name: name of the pin group, used to lookup the group. 181 * @pins: the pins included in this group. 182 * @npins: number of pins included in this group. 183 * @func: the mux function number to be programmed when selected. 184 * @configs: the config values to be set for each pin 185 * @nconfigs: number of configs for each pin 186 */ 187 struct rockchip_pin_group { 188 const char *name; 189 unsigned int npins; 190 unsigned int *pins; 191 struct rockchip_pin_config *data; 192 }; 193 194 /** 195 * struct rockchip_pmx_func: represent a pin function. 196 * @name: name of the pin function, used to lookup the function. 197 * @groups: one or more names of pin groups that provide this function. 198 * @num_groups: number of groups included in @groups. 199 */ 200 struct rockchip_pmx_func { 201 const char *name; 202 const char **groups; 203 u8 ngroups; 204 }; 205 206 struct rockchip_pinctrl { 207 struct regmap *regmap_base; 208 int reg_size; 209 struct regmap *regmap_pull; 210 struct regmap *regmap_pmu; 211 struct device *dev; 212 struct rockchip_pin_ctrl *ctrl; 213 struct pinctrl_desc pctl; 214 struct pinctrl_dev *pctl_dev; 215 struct rockchip_pin_group *groups; 216 unsigned int ngroups; 217 struct rockchip_pmx_func *functions; 218 unsigned int nfunctions; 219 }; 220 221 static struct regmap_config rockchip_regmap_config = { 222 .reg_bits = 32, 223 .val_bits = 32, 224 .reg_stride = 4, 225 }; 226 227 static inline struct rockchip_pin_bank *gc_to_pin_bank(struct gpio_chip *gc) 228 { 229 return container_of(gc, struct rockchip_pin_bank, gpio_chip); 230 } 231 232 static const inline struct rockchip_pin_group *pinctrl_name_to_group( 233 const struct rockchip_pinctrl *info, 234 const char *name) 235 { 236 int i; 237 238 for (i = 0; i < info->ngroups; i++) { 239 if (!strcmp(info->groups[i].name, name)) 240 return &info->groups[i]; 241 } 242 243 return NULL; 244 } 245 246 /* 247 * given a pin number that is local to a pin controller, find out the pin bank 248 * and the register base of the pin bank. 249 */ 250 static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info, 251 unsigned pin) 252 { 253 struct rockchip_pin_bank *b = info->ctrl->pin_banks; 254 255 while (pin >= (b->pin_base + b->nr_pins)) 256 b++; 257 258 return b; 259 } 260 261 static struct rockchip_pin_bank *bank_num_to_bank( 262 struct rockchip_pinctrl *info, 263 unsigned num) 264 { 265 struct rockchip_pin_bank *b = info->ctrl->pin_banks; 266 int i; 267 268 for (i = 0; i < info->ctrl->nr_banks; i++, b++) { 269 if (b->bank_num == num) 270 return b; 271 } 272 273 return ERR_PTR(-EINVAL); 274 } 275 276 /* 277 * Pinctrl_ops handling 278 */ 279 280 static int rockchip_get_groups_count(struct pinctrl_dev *pctldev) 281 { 282 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 283 284 return info->ngroups; 285 } 286 287 static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev, 288 unsigned selector) 289 { 290 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 291 292 return info->groups[selector].name; 293 } 294 295 static int rockchip_get_group_pins(struct pinctrl_dev *pctldev, 296 unsigned selector, const unsigned **pins, 297 unsigned *npins) 298 { 299 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 300 301 if (selector >= info->ngroups) 302 return -EINVAL; 303 304 *pins = info->groups[selector].pins; 305 *npins = info->groups[selector].npins; 306 307 return 0; 308 } 309 310 static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev, 311 struct device_node *np, 312 struct pinctrl_map **map, unsigned *num_maps) 313 { 314 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 315 const struct rockchip_pin_group *grp; 316 struct pinctrl_map *new_map; 317 struct device_node *parent; 318 int map_num = 1; 319 int i; 320 321 /* 322 * first find the group of this node and check if we need to create 323 * config maps for pins 324 */ 325 grp = pinctrl_name_to_group(info, np->name); 326 if (!grp) { 327 dev_err(info->dev, "unable to find group for node %s\n", 328 np->name); 329 return -EINVAL; 330 } 331 332 map_num += grp->npins; 333 new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num, 334 GFP_KERNEL); 335 if (!new_map) 336 return -ENOMEM; 337 338 *map = new_map; 339 *num_maps = map_num; 340 341 /* create mux map */ 342 parent = of_get_parent(np); 343 if (!parent) { 344 devm_kfree(pctldev->dev, new_map); 345 return -EINVAL; 346 } 347 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP; 348 new_map[0].data.mux.function = parent->name; 349 new_map[0].data.mux.group = np->name; 350 of_node_put(parent); 351 352 /* create config map */ 353 new_map++; 354 for (i = 0; i < grp->npins; i++) { 355 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN; 356 new_map[i].data.configs.group_or_pin = 357 pin_get_name(pctldev, grp->pins[i]); 358 new_map[i].data.configs.configs = grp->data[i].configs; 359 new_map[i].data.configs.num_configs = grp->data[i].nconfigs; 360 } 361 362 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n", 363 (*map)->data.mux.function, (*map)->data.mux.group, map_num); 364 365 return 0; 366 } 367 368 static void rockchip_dt_free_map(struct pinctrl_dev *pctldev, 369 struct pinctrl_map *map, unsigned num_maps) 370 { 371 } 372 373 static const struct pinctrl_ops rockchip_pctrl_ops = { 374 .get_groups_count = rockchip_get_groups_count, 375 .get_group_name = rockchip_get_group_name, 376 .get_group_pins = rockchip_get_group_pins, 377 .dt_node_to_map = rockchip_dt_node_to_map, 378 .dt_free_map = rockchip_dt_free_map, 379 }; 380 381 /* 382 * Hardware access 383 */ 384 385 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) 386 { 387 struct rockchip_pinctrl *info = bank->drvdata; 388 int iomux_num = (pin / 8); 389 struct regmap *regmap; 390 unsigned int val; 391 int reg, ret, mask; 392 u8 bit; 393 394 if (iomux_num > 3) 395 return -EINVAL; 396 397 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { 398 dev_err(info->dev, "pin %d is unrouted\n", pin); 399 return -EINVAL; 400 } 401 402 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) 403 return RK_FUNC_GPIO; 404 405 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) 406 ? info->regmap_pmu : info->regmap_base; 407 408 /* get basic quadrupel of mux registers and the correct reg inside */ 409 mask = (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) ? 0xf : 0x3; 410 reg = bank->iomux[iomux_num].offset; 411 if (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) { 412 if ((pin % 8) >= 4) 413 reg += 0x4; 414 bit = (pin % 4) * 4; 415 } else { 416 bit = (pin % 8) * 2; 417 } 418 419 ret = regmap_read(regmap, reg, &val); 420 if (ret) 421 return ret; 422 423 return ((val >> bit) & mask); 424 } 425 426 /* 427 * Set a new mux function for a pin. 428 * 429 * The register is divided into the upper and lower 16 bit. When changing 430 * a value, the previous register value is not read and changed. Instead 431 * it seems the changed bits are marked in the upper 16 bit, while the 432 * changed value gets set in the same offset in the lower 16 bit. 433 * All pin settings seem to be 2 bit wide in both the upper and lower 434 * parts. 435 * @bank: pin bank to change 436 * @pin: pin to change 437 * @mux: new mux function to set 438 */ 439 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) 440 { 441 struct rockchip_pinctrl *info = bank->drvdata; 442 int iomux_num = (pin / 8); 443 struct regmap *regmap; 444 int reg, ret, mask; 445 unsigned long flags; 446 u8 bit; 447 u32 data, rmask; 448 449 if (iomux_num > 3) 450 return -EINVAL; 451 452 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { 453 dev_err(info->dev, "pin %d is unrouted\n", pin); 454 return -EINVAL; 455 } 456 457 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) { 458 if (mux != RK_FUNC_GPIO) { 459 dev_err(info->dev, 460 "pin %d only supports a gpio mux\n", pin); 461 return -ENOTSUPP; 462 } else { 463 return 0; 464 } 465 } 466 467 dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n", 468 bank->bank_num, pin, mux); 469 470 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) 471 ? info->regmap_pmu : info->regmap_base; 472 473 /* get basic quadrupel of mux registers and the correct reg inside */ 474 mask = (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) ? 0xf : 0x3; 475 reg = bank->iomux[iomux_num].offset; 476 if (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) { 477 if ((pin % 8) >= 4) 478 reg += 0x4; 479 bit = (pin % 4) * 4; 480 } else { 481 bit = (pin % 8) * 2; 482 } 483 484 spin_lock_irqsave(&bank->slock, flags); 485 486 data = (mask << (bit + 16)); 487 rmask = data | (data >> 16); 488 data |= (mux & mask) << bit; 489 ret = regmap_update_bits(regmap, reg, rmask, data); 490 491 spin_unlock_irqrestore(&bank->slock, flags); 492 493 return ret; 494 } 495 496 #define RK2928_PULL_OFFSET 0x118 497 #define RK2928_PULL_PINS_PER_REG 16 498 #define RK2928_PULL_BANK_STRIDE 8 499 500 static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 501 int pin_num, struct regmap **regmap, 502 int *reg, u8 *bit) 503 { 504 struct rockchip_pinctrl *info = bank->drvdata; 505 506 *regmap = info->regmap_base; 507 *reg = RK2928_PULL_OFFSET; 508 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; 509 *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4; 510 511 *bit = pin_num % RK2928_PULL_PINS_PER_REG; 512 }; 513 514 #define RK3188_PULL_OFFSET 0x164 515 #define RK3188_PULL_BITS_PER_PIN 2 516 #define RK3188_PULL_PINS_PER_REG 8 517 #define RK3188_PULL_BANK_STRIDE 16 518 #define RK3188_PULL_PMU_OFFSET 0x64 519 520 static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 521 int pin_num, struct regmap **regmap, 522 int *reg, u8 *bit) 523 { 524 struct rockchip_pinctrl *info = bank->drvdata; 525 526 /* The first 12 pins of the first bank are located elsewhere */ 527 if (bank->bank_num == 0 && pin_num < 12) { 528 *regmap = info->regmap_pmu ? info->regmap_pmu 529 : bank->regmap_pull; 530 *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0; 531 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 532 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 533 *bit *= RK3188_PULL_BITS_PER_PIN; 534 } else { 535 *regmap = info->regmap_pull ? info->regmap_pull 536 : info->regmap_base; 537 *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET; 538 539 /* correct the offset, as it is the 2nd pull register */ 540 *reg -= 4; 541 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 542 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 543 544 /* 545 * The bits in these registers have an inverse ordering 546 * with the lowest pin being in bits 15:14 and the highest 547 * pin in bits 1:0 548 */ 549 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG); 550 *bit *= RK3188_PULL_BITS_PER_PIN; 551 } 552 } 553 554 #define RK3288_PULL_OFFSET 0x140 555 static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 556 int pin_num, struct regmap **regmap, 557 int *reg, u8 *bit) 558 { 559 struct rockchip_pinctrl *info = bank->drvdata; 560 561 /* The first 24 pins of the first bank are located in PMU */ 562 if (bank->bank_num == 0) { 563 *regmap = info->regmap_pmu; 564 *reg = RK3188_PULL_PMU_OFFSET; 565 566 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 567 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 568 *bit *= RK3188_PULL_BITS_PER_PIN; 569 } else { 570 *regmap = info->regmap_base; 571 *reg = RK3288_PULL_OFFSET; 572 573 /* correct the offset, as we're starting with the 2nd bank */ 574 *reg -= 0x10; 575 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 576 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 577 578 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 579 *bit *= RK3188_PULL_BITS_PER_PIN; 580 } 581 } 582 583 #define RK3288_DRV_PMU_OFFSET 0x70 584 #define RK3288_DRV_GRF_OFFSET 0x1c0 585 #define RK3288_DRV_BITS_PER_PIN 2 586 #define RK3288_DRV_PINS_PER_REG 8 587 #define RK3288_DRV_BANK_STRIDE 16 588 589 static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 590 int pin_num, struct regmap **regmap, 591 int *reg, u8 *bit) 592 { 593 struct rockchip_pinctrl *info = bank->drvdata; 594 595 /* The first 24 pins of the first bank are located in PMU */ 596 if (bank->bank_num == 0) { 597 *regmap = info->regmap_pmu; 598 *reg = RK3288_DRV_PMU_OFFSET; 599 600 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 601 *bit = pin_num % RK3288_DRV_PINS_PER_REG; 602 *bit *= RK3288_DRV_BITS_PER_PIN; 603 } else { 604 *regmap = info->regmap_base; 605 *reg = RK3288_DRV_GRF_OFFSET; 606 607 /* correct the offset, as we're starting with the 2nd bank */ 608 *reg -= 0x10; 609 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 610 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 611 612 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 613 *bit *= RK3288_DRV_BITS_PER_PIN; 614 } 615 } 616 617 #define RK3368_PULL_GRF_OFFSET 0x100 618 #define RK3368_PULL_PMU_OFFSET 0x10 619 620 static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 621 int pin_num, struct regmap **regmap, 622 int *reg, u8 *bit) 623 { 624 struct rockchip_pinctrl *info = bank->drvdata; 625 626 /* The first 32 pins of the first bank are located in PMU */ 627 if (bank->bank_num == 0) { 628 *regmap = info->regmap_pmu; 629 *reg = RK3368_PULL_PMU_OFFSET; 630 631 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 632 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 633 *bit *= RK3188_PULL_BITS_PER_PIN; 634 } else { 635 *regmap = info->regmap_base; 636 *reg = RK3368_PULL_GRF_OFFSET; 637 638 /* correct the offset, as we're starting with the 2nd bank */ 639 *reg -= 0x10; 640 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 641 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 642 643 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 644 *bit *= RK3188_PULL_BITS_PER_PIN; 645 } 646 } 647 648 #define RK3368_DRV_PMU_OFFSET 0x20 649 #define RK3368_DRV_GRF_OFFSET 0x200 650 651 static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 652 int pin_num, struct regmap **regmap, 653 int *reg, u8 *bit) 654 { 655 struct rockchip_pinctrl *info = bank->drvdata; 656 657 /* The first 32 pins of the first bank are located in PMU */ 658 if (bank->bank_num == 0) { 659 *regmap = info->regmap_pmu; 660 *reg = RK3368_DRV_PMU_OFFSET; 661 662 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 663 *bit = pin_num % RK3288_DRV_PINS_PER_REG; 664 *bit *= RK3288_DRV_BITS_PER_PIN; 665 } else { 666 *regmap = info->regmap_base; 667 *reg = RK3368_DRV_GRF_OFFSET; 668 669 /* correct the offset, as we're starting with the 2nd bank */ 670 *reg -= 0x10; 671 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 672 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 673 674 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 675 *bit *= RK3288_DRV_BITS_PER_PIN; 676 } 677 } 678 679 static int rockchip_perpin_drv_list[] = { 2, 4, 8, 12 }; 680 681 static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank, 682 int pin_num) 683 { 684 struct rockchip_pinctrl *info = bank->drvdata; 685 struct rockchip_pin_ctrl *ctrl = info->ctrl; 686 struct regmap *regmap; 687 int reg, ret; 688 u32 data; 689 u8 bit; 690 691 ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); 692 693 ret = regmap_read(regmap, reg, &data); 694 if (ret) 695 return ret; 696 697 data >>= bit; 698 data &= (1 << RK3288_DRV_BITS_PER_PIN) - 1; 699 700 return rockchip_perpin_drv_list[data]; 701 } 702 703 static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank, 704 int pin_num, int strength) 705 { 706 struct rockchip_pinctrl *info = bank->drvdata; 707 struct rockchip_pin_ctrl *ctrl = info->ctrl; 708 struct regmap *regmap; 709 unsigned long flags; 710 int reg, ret, i; 711 u32 data, rmask; 712 u8 bit; 713 714 ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); 715 716 ret = -EINVAL; 717 for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list); i++) { 718 if (rockchip_perpin_drv_list[i] == strength) { 719 ret = i; 720 break; 721 } 722 } 723 724 if (ret < 0) { 725 dev_err(info->dev, "unsupported driver strength %d\n", 726 strength); 727 return ret; 728 } 729 730 spin_lock_irqsave(&bank->slock, flags); 731 732 /* enable the write to the equivalent lower bits */ 733 data = ((1 << RK3288_DRV_BITS_PER_PIN) - 1) << (bit + 16); 734 rmask = data | (data >> 16); 735 data |= (ret << bit); 736 737 ret = regmap_update_bits(regmap, reg, rmask, data); 738 spin_unlock_irqrestore(&bank->slock, flags); 739 740 return ret; 741 } 742 743 static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num) 744 { 745 struct rockchip_pinctrl *info = bank->drvdata; 746 struct rockchip_pin_ctrl *ctrl = info->ctrl; 747 struct regmap *regmap; 748 int reg, ret; 749 u8 bit; 750 u32 data; 751 752 /* rk3066b does support any pulls */ 753 if (ctrl->type == RK3066B) 754 return PIN_CONFIG_BIAS_DISABLE; 755 756 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); 757 758 ret = regmap_read(regmap, reg, &data); 759 if (ret) 760 return ret; 761 762 switch (ctrl->type) { 763 case RK2928: 764 return !(data & BIT(bit)) 765 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT 766 : PIN_CONFIG_BIAS_DISABLE; 767 case RK3188: 768 case RK3288: 769 case RK3368: 770 data >>= bit; 771 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1; 772 773 switch (data) { 774 case 0: 775 return PIN_CONFIG_BIAS_DISABLE; 776 case 1: 777 return PIN_CONFIG_BIAS_PULL_UP; 778 case 2: 779 return PIN_CONFIG_BIAS_PULL_DOWN; 780 case 3: 781 return PIN_CONFIG_BIAS_BUS_HOLD; 782 } 783 784 dev_err(info->dev, "unknown pull setting\n"); 785 return -EIO; 786 default: 787 dev_err(info->dev, "unsupported pinctrl type\n"); 788 return -EINVAL; 789 }; 790 } 791 792 static int rockchip_set_pull(struct rockchip_pin_bank *bank, 793 int pin_num, int pull) 794 { 795 struct rockchip_pinctrl *info = bank->drvdata; 796 struct rockchip_pin_ctrl *ctrl = info->ctrl; 797 struct regmap *regmap; 798 int reg, ret; 799 unsigned long flags; 800 u8 bit; 801 u32 data, rmask; 802 803 dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n", 804 bank->bank_num, pin_num, pull); 805 806 /* rk3066b does support any pulls */ 807 if (ctrl->type == RK3066B) 808 return pull ? -EINVAL : 0; 809 810 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); 811 812 switch (ctrl->type) { 813 case RK2928: 814 spin_lock_irqsave(&bank->slock, flags); 815 816 data = BIT(bit + 16); 817 if (pull == PIN_CONFIG_BIAS_DISABLE) 818 data |= BIT(bit); 819 ret = regmap_write(regmap, reg, data); 820 821 spin_unlock_irqrestore(&bank->slock, flags); 822 break; 823 case RK3188: 824 case RK3288: 825 case RK3368: 826 spin_lock_irqsave(&bank->slock, flags); 827 828 /* enable the write to the equivalent lower bits */ 829 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16); 830 rmask = data | (data >> 16); 831 832 switch (pull) { 833 case PIN_CONFIG_BIAS_DISABLE: 834 break; 835 case PIN_CONFIG_BIAS_PULL_UP: 836 data |= (1 << bit); 837 break; 838 case PIN_CONFIG_BIAS_PULL_DOWN: 839 data |= (2 << bit); 840 break; 841 case PIN_CONFIG_BIAS_BUS_HOLD: 842 data |= (3 << bit); 843 break; 844 default: 845 spin_unlock_irqrestore(&bank->slock, flags); 846 dev_err(info->dev, "unsupported pull setting %d\n", 847 pull); 848 return -EINVAL; 849 } 850 851 ret = regmap_update_bits(regmap, reg, rmask, data); 852 853 spin_unlock_irqrestore(&bank->slock, flags); 854 break; 855 default: 856 dev_err(info->dev, "unsupported pinctrl type\n"); 857 return -EINVAL; 858 } 859 860 return ret; 861 } 862 863 /* 864 * Pinmux_ops handling 865 */ 866 867 static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev) 868 { 869 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 870 871 return info->nfunctions; 872 } 873 874 static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev, 875 unsigned selector) 876 { 877 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 878 879 return info->functions[selector].name; 880 } 881 882 static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev, 883 unsigned selector, const char * const **groups, 884 unsigned * const num_groups) 885 { 886 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 887 888 *groups = info->functions[selector].groups; 889 *num_groups = info->functions[selector].ngroups; 890 891 return 0; 892 } 893 894 static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector, 895 unsigned group) 896 { 897 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 898 const unsigned int *pins = info->groups[group].pins; 899 const struct rockchip_pin_config *data = info->groups[group].data; 900 struct rockchip_pin_bank *bank; 901 int cnt, ret = 0; 902 903 dev_dbg(info->dev, "enable function %s group %s\n", 904 info->functions[selector].name, info->groups[group].name); 905 906 /* 907 * for each pin in the pin group selected, program the correspoding pin 908 * pin function number in the config register. 909 */ 910 for (cnt = 0; cnt < info->groups[group].npins; cnt++) { 911 bank = pin_to_bank(info, pins[cnt]); 912 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 913 data[cnt].func); 914 if (ret) 915 break; 916 } 917 918 if (ret) { 919 /* revert the already done pin settings */ 920 for (cnt--; cnt >= 0; cnt--) 921 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0); 922 923 return ret; 924 } 925 926 return 0; 927 } 928 929 /* 930 * The calls to gpio_direction_output() and gpio_direction_input() 931 * leads to this function call (via the pinctrl_gpio_direction_{input|output}() 932 * function called from the gpiolib interface). 933 */ 934 static int _rockchip_pmx_gpio_set_direction(struct gpio_chip *chip, 935 int pin, bool input) 936 { 937 struct rockchip_pin_bank *bank; 938 int ret; 939 unsigned long flags; 940 u32 data; 941 942 bank = gc_to_pin_bank(chip); 943 944 ret = rockchip_set_mux(bank, pin, RK_FUNC_GPIO); 945 if (ret < 0) 946 return ret; 947 948 spin_lock_irqsave(&bank->slock, flags); 949 950 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); 951 /* set bit to 1 for output, 0 for input */ 952 if (!input) 953 data |= BIT(pin); 954 else 955 data &= ~BIT(pin); 956 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR); 957 958 spin_unlock_irqrestore(&bank->slock, flags); 959 960 return 0; 961 } 962 963 static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, 964 struct pinctrl_gpio_range *range, 965 unsigned offset, bool input) 966 { 967 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 968 struct gpio_chip *chip; 969 int pin; 970 971 chip = range->gc; 972 pin = offset - chip->base; 973 dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n", 974 offset, range->name, pin, input ? "input" : "output"); 975 976 return _rockchip_pmx_gpio_set_direction(chip, offset - chip->base, 977 input); 978 } 979 980 static const struct pinmux_ops rockchip_pmx_ops = { 981 .get_functions_count = rockchip_pmx_get_funcs_count, 982 .get_function_name = rockchip_pmx_get_func_name, 983 .get_function_groups = rockchip_pmx_get_groups, 984 .set_mux = rockchip_pmx_set, 985 .gpio_set_direction = rockchip_pmx_gpio_set_direction, 986 }; 987 988 /* 989 * Pinconf_ops handling 990 */ 991 992 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl, 993 enum pin_config_param pull) 994 { 995 switch (ctrl->type) { 996 case RK2928: 997 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT || 998 pull == PIN_CONFIG_BIAS_DISABLE); 999 case RK3066B: 1000 return pull ? false : true; 1001 case RK3188: 1002 case RK3288: 1003 case RK3368: 1004 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT); 1005 } 1006 1007 return false; 1008 } 1009 1010 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value); 1011 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset); 1012 1013 /* set the pin config settings for a specified pin */ 1014 static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 1015 unsigned long *configs, unsigned num_configs) 1016 { 1017 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1018 struct rockchip_pin_bank *bank = pin_to_bank(info, pin); 1019 enum pin_config_param param; 1020 u16 arg; 1021 int i; 1022 int rc; 1023 1024 for (i = 0; i < num_configs; i++) { 1025 param = pinconf_to_config_param(configs[i]); 1026 arg = pinconf_to_config_argument(configs[i]); 1027 1028 switch (param) { 1029 case PIN_CONFIG_BIAS_DISABLE: 1030 rc = rockchip_set_pull(bank, pin - bank->pin_base, 1031 param); 1032 if (rc) 1033 return rc; 1034 break; 1035 case PIN_CONFIG_BIAS_PULL_UP: 1036 case PIN_CONFIG_BIAS_PULL_DOWN: 1037 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: 1038 case PIN_CONFIG_BIAS_BUS_HOLD: 1039 if (!rockchip_pinconf_pull_valid(info->ctrl, param)) 1040 return -ENOTSUPP; 1041 1042 if (!arg) 1043 return -EINVAL; 1044 1045 rc = rockchip_set_pull(bank, pin - bank->pin_base, 1046 param); 1047 if (rc) 1048 return rc; 1049 break; 1050 case PIN_CONFIG_OUTPUT: 1051 rockchip_gpio_set(&bank->gpio_chip, 1052 pin - bank->pin_base, arg); 1053 rc = _rockchip_pmx_gpio_set_direction(&bank->gpio_chip, 1054 pin - bank->pin_base, false); 1055 if (rc) 1056 return rc; 1057 break; 1058 case PIN_CONFIG_DRIVE_STRENGTH: 1059 /* rk3288 is the first with per-pin drive-strength */ 1060 if (!info->ctrl->drv_calc_reg) 1061 return -ENOTSUPP; 1062 1063 rc = rockchip_set_drive_perpin(bank, 1064 pin - bank->pin_base, arg); 1065 if (rc < 0) 1066 return rc; 1067 break; 1068 default: 1069 return -ENOTSUPP; 1070 break; 1071 } 1072 } /* for each config */ 1073 1074 return 0; 1075 } 1076 1077 /* get the pin config settings for a specified pin */ 1078 static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, 1079 unsigned long *config) 1080 { 1081 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1082 struct rockchip_pin_bank *bank = pin_to_bank(info, pin); 1083 enum pin_config_param param = pinconf_to_config_param(*config); 1084 u16 arg; 1085 int rc; 1086 1087 switch (param) { 1088 case PIN_CONFIG_BIAS_DISABLE: 1089 if (rockchip_get_pull(bank, pin - bank->pin_base) != param) 1090 return -EINVAL; 1091 1092 arg = 0; 1093 break; 1094 case PIN_CONFIG_BIAS_PULL_UP: 1095 case PIN_CONFIG_BIAS_PULL_DOWN: 1096 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: 1097 case PIN_CONFIG_BIAS_BUS_HOLD: 1098 if (!rockchip_pinconf_pull_valid(info->ctrl, param)) 1099 return -ENOTSUPP; 1100 1101 if (rockchip_get_pull(bank, pin - bank->pin_base) != param) 1102 return -EINVAL; 1103 1104 arg = 1; 1105 break; 1106 case PIN_CONFIG_OUTPUT: 1107 rc = rockchip_get_mux(bank, pin - bank->pin_base); 1108 if (rc != RK_FUNC_GPIO) 1109 return -EINVAL; 1110 1111 rc = rockchip_gpio_get(&bank->gpio_chip, pin - bank->pin_base); 1112 if (rc < 0) 1113 return rc; 1114 1115 arg = rc ? 1 : 0; 1116 break; 1117 case PIN_CONFIG_DRIVE_STRENGTH: 1118 /* rk3288 is the first with per-pin drive-strength */ 1119 if (!info->ctrl->drv_calc_reg) 1120 return -ENOTSUPP; 1121 1122 rc = rockchip_get_drive_perpin(bank, pin - bank->pin_base); 1123 if (rc < 0) 1124 return rc; 1125 1126 arg = rc; 1127 break; 1128 default: 1129 return -ENOTSUPP; 1130 break; 1131 } 1132 1133 *config = pinconf_to_config_packed(param, arg); 1134 1135 return 0; 1136 } 1137 1138 static const struct pinconf_ops rockchip_pinconf_ops = { 1139 .pin_config_get = rockchip_pinconf_get, 1140 .pin_config_set = rockchip_pinconf_set, 1141 .is_generic = true, 1142 }; 1143 1144 static const struct of_device_id rockchip_bank_match[] = { 1145 { .compatible = "rockchip,gpio-bank" }, 1146 { .compatible = "rockchip,rk3188-gpio-bank0" }, 1147 {}, 1148 }; 1149 1150 static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info, 1151 struct device_node *np) 1152 { 1153 struct device_node *child; 1154 1155 for_each_child_of_node(np, child) { 1156 if (of_match_node(rockchip_bank_match, child)) 1157 continue; 1158 1159 info->nfunctions++; 1160 info->ngroups += of_get_child_count(child); 1161 } 1162 } 1163 1164 static int rockchip_pinctrl_parse_groups(struct device_node *np, 1165 struct rockchip_pin_group *grp, 1166 struct rockchip_pinctrl *info, 1167 u32 index) 1168 { 1169 struct rockchip_pin_bank *bank; 1170 int size; 1171 const __be32 *list; 1172 int num; 1173 int i, j; 1174 int ret; 1175 1176 dev_dbg(info->dev, "group(%d): %s\n", index, np->name); 1177 1178 /* Initialise group */ 1179 grp->name = np->name; 1180 1181 /* 1182 * the binding format is rockchip,pins = <bank pin mux CONFIG>, 1183 * do sanity check and calculate pins number 1184 */ 1185 list = of_get_property(np, "rockchip,pins", &size); 1186 /* we do not check return since it's safe node passed down */ 1187 size /= sizeof(*list); 1188 if (!size || size % 4) { 1189 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n"); 1190 return -EINVAL; 1191 } 1192 1193 grp->npins = size / 4; 1194 1195 grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int), 1196 GFP_KERNEL); 1197 grp->data = devm_kzalloc(info->dev, grp->npins * 1198 sizeof(struct rockchip_pin_config), 1199 GFP_KERNEL); 1200 if (!grp->pins || !grp->data) 1201 return -ENOMEM; 1202 1203 for (i = 0, j = 0; i < size; i += 4, j++) { 1204 const __be32 *phandle; 1205 struct device_node *np_config; 1206 1207 num = be32_to_cpu(*list++); 1208 bank = bank_num_to_bank(info, num); 1209 if (IS_ERR(bank)) 1210 return PTR_ERR(bank); 1211 1212 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++); 1213 grp->data[j].func = be32_to_cpu(*list++); 1214 1215 phandle = list++; 1216 if (!phandle) 1217 return -EINVAL; 1218 1219 np_config = of_find_node_by_phandle(be32_to_cpup(phandle)); 1220 ret = pinconf_generic_parse_dt_config(np_config, NULL, 1221 &grp->data[j].configs, &grp->data[j].nconfigs); 1222 if (ret) 1223 return ret; 1224 } 1225 1226 return 0; 1227 } 1228 1229 static int rockchip_pinctrl_parse_functions(struct device_node *np, 1230 struct rockchip_pinctrl *info, 1231 u32 index) 1232 { 1233 struct device_node *child; 1234 struct rockchip_pmx_func *func; 1235 struct rockchip_pin_group *grp; 1236 int ret; 1237 static u32 grp_index; 1238 u32 i = 0; 1239 1240 dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name); 1241 1242 func = &info->functions[index]; 1243 1244 /* Initialise function */ 1245 func->name = np->name; 1246 func->ngroups = of_get_child_count(np); 1247 if (func->ngroups <= 0) 1248 return 0; 1249 1250 func->groups = devm_kzalloc(info->dev, 1251 func->ngroups * sizeof(char *), GFP_KERNEL); 1252 if (!func->groups) 1253 return -ENOMEM; 1254 1255 for_each_child_of_node(np, child) { 1256 func->groups[i] = child->name; 1257 grp = &info->groups[grp_index++]; 1258 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++); 1259 if (ret) 1260 return ret; 1261 } 1262 1263 return 0; 1264 } 1265 1266 static int rockchip_pinctrl_parse_dt(struct platform_device *pdev, 1267 struct rockchip_pinctrl *info) 1268 { 1269 struct device *dev = &pdev->dev; 1270 struct device_node *np = dev->of_node; 1271 struct device_node *child; 1272 int ret; 1273 int i; 1274 1275 rockchip_pinctrl_child_count(info, np); 1276 1277 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions); 1278 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups); 1279 1280 info->functions = devm_kzalloc(dev, info->nfunctions * 1281 sizeof(struct rockchip_pmx_func), 1282 GFP_KERNEL); 1283 if (!info->functions) { 1284 dev_err(dev, "failed to allocate memory for function list\n"); 1285 return -EINVAL; 1286 } 1287 1288 info->groups = devm_kzalloc(dev, info->ngroups * 1289 sizeof(struct rockchip_pin_group), 1290 GFP_KERNEL); 1291 if (!info->groups) { 1292 dev_err(dev, "failed allocate memory for ping group list\n"); 1293 return -EINVAL; 1294 } 1295 1296 i = 0; 1297 1298 for_each_child_of_node(np, child) { 1299 if (of_match_node(rockchip_bank_match, child)) 1300 continue; 1301 1302 ret = rockchip_pinctrl_parse_functions(child, info, i++); 1303 if (ret) { 1304 dev_err(&pdev->dev, "failed to parse function\n"); 1305 return ret; 1306 } 1307 } 1308 1309 return 0; 1310 } 1311 1312 static int rockchip_pinctrl_register(struct platform_device *pdev, 1313 struct rockchip_pinctrl *info) 1314 { 1315 struct pinctrl_desc *ctrldesc = &info->pctl; 1316 struct pinctrl_pin_desc *pindesc, *pdesc; 1317 struct rockchip_pin_bank *pin_bank; 1318 int pin, bank, ret; 1319 int k; 1320 1321 ctrldesc->name = "rockchip-pinctrl"; 1322 ctrldesc->owner = THIS_MODULE; 1323 ctrldesc->pctlops = &rockchip_pctrl_ops; 1324 ctrldesc->pmxops = &rockchip_pmx_ops; 1325 ctrldesc->confops = &rockchip_pinconf_ops; 1326 1327 pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) * 1328 info->ctrl->nr_pins, GFP_KERNEL); 1329 if (!pindesc) { 1330 dev_err(&pdev->dev, "mem alloc for pin descriptors failed\n"); 1331 return -ENOMEM; 1332 } 1333 ctrldesc->pins = pindesc; 1334 ctrldesc->npins = info->ctrl->nr_pins; 1335 1336 pdesc = pindesc; 1337 for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) { 1338 pin_bank = &info->ctrl->pin_banks[bank]; 1339 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) { 1340 pdesc->number = k; 1341 pdesc->name = kasprintf(GFP_KERNEL, "%s-%d", 1342 pin_bank->name, pin); 1343 pdesc++; 1344 } 1345 } 1346 1347 ret = rockchip_pinctrl_parse_dt(pdev, info); 1348 if (ret) 1349 return ret; 1350 1351 info->pctl_dev = pinctrl_register(ctrldesc, &pdev->dev, info); 1352 if (IS_ERR(info->pctl_dev)) { 1353 dev_err(&pdev->dev, "could not register pinctrl driver\n"); 1354 return PTR_ERR(info->pctl_dev); 1355 } 1356 1357 for (bank = 0; bank < info->ctrl->nr_banks; ++bank) { 1358 pin_bank = &info->ctrl->pin_banks[bank]; 1359 pin_bank->grange.name = pin_bank->name; 1360 pin_bank->grange.id = bank; 1361 pin_bank->grange.pin_base = pin_bank->pin_base; 1362 pin_bank->grange.base = pin_bank->gpio_chip.base; 1363 pin_bank->grange.npins = pin_bank->gpio_chip.ngpio; 1364 pin_bank->grange.gc = &pin_bank->gpio_chip; 1365 pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange); 1366 } 1367 1368 return 0; 1369 } 1370 1371 /* 1372 * GPIO handling 1373 */ 1374 1375 static int rockchip_gpio_request(struct gpio_chip *chip, unsigned offset) 1376 { 1377 return pinctrl_request_gpio(chip->base + offset); 1378 } 1379 1380 static void rockchip_gpio_free(struct gpio_chip *chip, unsigned offset) 1381 { 1382 pinctrl_free_gpio(chip->base + offset); 1383 } 1384 1385 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value) 1386 { 1387 struct rockchip_pin_bank *bank = gc_to_pin_bank(gc); 1388 void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR; 1389 unsigned long flags; 1390 u32 data; 1391 1392 spin_lock_irqsave(&bank->slock, flags); 1393 1394 data = readl(reg); 1395 data &= ~BIT(offset); 1396 if (value) 1397 data |= BIT(offset); 1398 writel(data, reg); 1399 1400 spin_unlock_irqrestore(&bank->slock, flags); 1401 } 1402 1403 /* 1404 * Returns the level of the pin for input direction and setting of the DR 1405 * register for output gpios. 1406 */ 1407 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset) 1408 { 1409 struct rockchip_pin_bank *bank = gc_to_pin_bank(gc); 1410 u32 data; 1411 1412 data = readl(bank->reg_base + GPIO_EXT_PORT); 1413 data >>= offset; 1414 data &= 1; 1415 return data; 1416 } 1417 1418 /* 1419 * gpiolib gpio_direction_input callback function. The setting of the pin 1420 * mux function as 'gpio input' will be handled by the pinctrl susbsystem 1421 * interface. 1422 */ 1423 static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset) 1424 { 1425 return pinctrl_gpio_direction_input(gc->base + offset); 1426 } 1427 1428 /* 1429 * gpiolib gpio_direction_output callback function. The setting of the pin 1430 * mux function as 'gpio output' will be handled by the pinctrl susbsystem 1431 * interface. 1432 */ 1433 static int rockchip_gpio_direction_output(struct gpio_chip *gc, 1434 unsigned offset, int value) 1435 { 1436 rockchip_gpio_set(gc, offset, value); 1437 return pinctrl_gpio_direction_output(gc->base + offset); 1438 } 1439 1440 /* 1441 * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin 1442 * and a virtual IRQ, if not already present. 1443 */ 1444 static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset) 1445 { 1446 struct rockchip_pin_bank *bank = gc_to_pin_bank(gc); 1447 unsigned int virq; 1448 1449 if (!bank->domain) 1450 return -ENXIO; 1451 1452 virq = irq_create_mapping(bank->domain, offset); 1453 1454 return (virq) ? : -ENXIO; 1455 } 1456 1457 static const struct gpio_chip rockchip_gpiolib_chip = { 1458 .request = rockchip_gpio_request, 1459 .free = rockchip_gpio_free, 1460 .set = rockchip_gpio_set, 1461 .get = rockchip_gpio_get, 1462 .direction_input = rockchip_gpio_direction_input, 1463 .direction_output = rockchip_gpio_direction_output, 1464 .to_irq = rockchip_gpio_to_irq, 1465 .owner = THIS_MODULE, 1466 }; 1467 1468 /* 1469 * Interrupt handling 1470 */ 1471 1472 static void rockchip_irq_demux(unsigned int irq, struct irq_desc *desc) 1473 { 1474 struct irq_chip *chip = irq_get_chip(irq); 1475 struct rockchip_pin_bank *bank = irq_get_handler_data(irq); 1476 u32 pend; 1477 1478 dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name); 1479 1480 chained_irq_enter(chip, desc); 1481 1482 pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS); 1483 1484 while (pend) { 1485 unsigned int virq; 1486 1487 irq = __ffs(pend); 1488 pend &= ~BIT(irq); 1489 virq = irq_linear_revmap(bank->domain, irq); 1490 1491 if (!virq) { 1492 dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq); 1493 continue; 1494 } 1495 1496 dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq); 1497 1498 /* 1499 * Triggering IRQ on both rising and falling edge 1500 * needs manual intervention. 1501 */ 1502 if (bank->toggle_edge_mode & BIT(irq)) { 1503 u32 data, data_old, polarity; 1504 unsigned long flags; 1505 1506 data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT); 1507 do { 1508 spin_lock_irqsave(&bank->slock, flags); 1509 1510 polarity = readl_relaxed(bank->reg_base + 1511 GPIO_INT_POLARITY); 1512 if (data & BIT(irq)) 1513 polarity &= ~BIT(irq); 1514 else 1515 polarity |= BIT(irq); 1516 writel(polarity, 1517 bank->reg_base + GPIO_INT_POLARITY); 1518 1519 spin_unlock_irqrestore(&bank->slock, flags); 1520 1521 data_old = data; 1522 data = readl_relaxed(bank->reg_base + 1523 GPIO_EXT_PORT); 1524 } while ((data & BIT(irq)) != (data_old & BIT(irq))); 1525 } 1526 1527 generic_handle_irq(virq); 1528 } 1529 1530 chained_irq_exit(chip, desc); 1531 } 1532 1533 static int rockchip_irq_set_type(struct irq_data *d, unsigned int type) 1534 { 1535 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 1536 struct rockchip_pin_bank *bank = gc->private; 1537 u32 mask = BIT(d->hwirq); 1538 u32 polarity; 1539 u32 level; 1540 u32 data; 1541 unsigned long flags; 1542 int ret; 1543 1544 /* make sure the pin is configured as gpio input */ 1545 ret = rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO); 1546 if (ret < 0) 1547 return ret; 1548 1549 spin_lock_irqsave(&bank->slock, flags); 1550 1551 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); 1552 data &= ~mask; 1553 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR); 1554 1555 spin_unlock_irqrestore(&bank->slock, flags); 1556 1557 if (type & IRQ_TYPE_EDGE_BOTH) 1558 __irq_set_handler_locked(d->irq, handle_edge_irq); 1559 else 1560 __irq_set_handler_locked(d->irq, handle_level_irq); 1561 1562 spin_lock_irqsave(&bank->slock, flags); 1563 irq_gc_lock(gc); 1564 1565 level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL); 1566 polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY); 1567 1568 switch (type) { 1569 case IRQ_TYPE_EDGE_BOTH: 1570 bank->toggle_edge_mode |= mask; 1571 level |= mask; 1572 1573 /* 1574 * Determine gpio state. If 1 next interrupt should be falling 1575 * otherwise rising. 1576 */ 1577 data = readl(bank->reg_base + GPIO_EXT_PORT); 1578 if (data & mask) 1579 polarity &= ~mask; 1580 else 1581 polarity |= mask; 1582 break; 1583 case IRQ_TYPE_EDGE_RISING: 1584 bank->toggle_edge_mode &= ~mask; 1585 level |= mask; 1586 polarity |= mask; 1587 break; 1588 case IRQ_TYPE_EDGE_FALLING: 1589 bank->toggle_edge_mode &= ~mask; 1590 level |= mask; 1591 polarity &= ~mask; 1592 break; 1593 case IRQ_TYPE_LEVEL_HIGH: 1594 bank->toggle_edge_mode &= ~mask; 1595 level &= ~mask; 1596 polarity |= mask; 1597 break; 1598 case IRQ_TYPE_LEVEL_LOW: 1599 bank->toggle_edge_mode &= ~mask; 1600 level &= ~mask; 1601 polarity &= ~mask; 1602 break; 1603 default: 1604 irq_gc_unlock(gc); 1605 spin_unlock_irqrestore(&bank->slock, flags); 1606 return -EINVAL; 1607 } 1608 1609 writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL); 1610 writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY); 1611 1612 irq_gc_unlock(gc); 1613 spin_unlock_irqrestore(&bank->slock, flags); 1614 1615 return 0; 1616 } 1617 1618 static void rockchip_irq_suspend(struct irq_data *d) 1619 { 1620 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 1621 struct rockchip_pin_bank *bank = gc->private; 1622 1623 bank->saved_masks = irq_reg_readl(gc, GPIO_INTMASK); 1624 irq_reg_writel(gc, ~gc->wake_active, GPIO_INTMASK); 1625 } 1626 1627 static void rockchip_irq_resume(struct irq_data *d) 1628 { 1629 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 1630 struct rockchip_pin_bank *bank = gc->private; 1631 1632 irq_reg_writel(gc, bank->saved_masks, GPIO_INTMASK); 1633 } 1634 1635 static int rockchip_interrupts_register(struct platform_device *pdev, 1636 struct rockchip_pinctrl *info) 1637 { 1638 struct rockchip_pin_ctrl *ctrl = info->ctrl; 1639 struct rockchip_pin_bank *bank = ctrl->pin_banks; 1640 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; 1641 struct irq_chip_generic *gc; 1642 int ret; 1643 int i; 1644 1645 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 1646 if (!bank->valid) { 1647 dev_warn(&pdev->dev, "bank %s is not valid\n", 1648 bank->name); 1649 continue; 1650 } 1651 1652 bank->domain = irq_domain_add_linear(bank->of_node, 32, 1653 &irq_generic_chip_ops, NULL); 1654 if (!bank->domain) { 1655 dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n", 1656 bank->name); 1657 continue; 1658 } 1659 1660 ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1, 1661 "rockchip_gpio_irq", handle_level_irq, 1662 clr, 0, IRQ_GC_INIT_MASK_CACHE); 1663 if (ret) { 1664 dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n", 1665 bank->name); 1666 irq_domain_remove(bank->domain); 1667 continue; 1668 } 1669 1670 /* 1671 * Linux assumes that all interrupts start out disabled/masked. 1672 * Our driver only uses the concept of masked and always keeps 1673 * things enabled, so for us that's all masked and all enabled. 1674 */ 1675 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTMASK); 1676 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTEN); 1677 1678 gc = irq_get_domain_generic_chip(bank->domain, 0); 1679 gc->reg_base = bank->reg_base; 1680 gc->private = bank; 1681 gc->chip_types[0].regs.mask = GPIO_INTMASK; 1682 gc->chip_types[0].regs.ack = GPIO_PORTS_EOI; 1683 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit; 1684 gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit; 1685 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit; 1686 gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake; 1687 gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend; 1688 gc->chip_types[0].chip.irq_resume = rockchip_irq_resume; 1689 gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type; 1690 gc->wake_enabled = IRQ_MSK(bank->nr_pins); 1691 1692 irq_set_handler_data(bank->irq, bank); 1693 irq_set_chained_handler(bank->irq, rockchip_irq_demux); 1694 } 1695 1696 return 0; 1697 } 1698 1699 static int rockchip_gpiolib_register(struct platform_device *pdev, 1700 struct rockchip_pinctrl *info) 1701 { 1702 struct rockchip_pin_ctrl *ctrl = info->ctrl; 1703 struct rockchip_pin_bank *bank = ctrl->pin_banks; 1704 struct gpio_chip *gc; 1705 int ret; 1706 int i; 1707 1708 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 1709 if (!bank->valid) { 1710 dev_warn(&pdev->dev, "bank %s is not valid\n", 1711 bank->name); 1712 continue; 1713 } 1714 1715 bank->gpio_chip = rockchip_gpiolib_chip; 1716 1717 gc = &bank->gpio_chip; 1718 gc->base = bank->pin_base; 1719 gc->ngpio = bank->nr_pins; 1720 gc->dev = &pdev->dev; 1721 gc->of_node = bank->of_node; 1722 gc->label = bank->name; 1723 1724 ret = gpiochip_add(gc); 1725 if (ret) { 1726 dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n", 1727 gc->label, ret); 1728 goto fail; 1729 } 1730 } 1731 1732 rockchip_interrupts_register(pdev, info); 1733 1734 return 0; 1735 1736 fail: 1737 for (--i, --bank; i >= 0; --i, --bank) { 1738 if (!bank->valid) 1739 continue; 1740 gpiochip_remove(&bank->gpio_chip); 1741 } 1742 return ret; 1743 } 1744 1745 static int rockchip_gpiolib_unregister(struct platform_device *pdev, 1746 struct rockchip_pinctrl *info) 1747 { 1748 struct rockchip_pin_ctrl *ctrl = info->ctrl; 1749 struct rockchip_pin_bank *bank = ctrl->pin_banks; 1750 int i; 1751 1752 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 1753 if (!bank->valid) 1754 continue; 1755 gpiochip_remove(&bank->gpio_chip); 1756 } 1757 1758 return 0; 1759 } 1760 1761 static int rockchip_get_bank_data(struct rockchip_pin_bank *bank, 1762 struct rockchip_pinctrl *info) 1763 { 1764 struct resource res; 1765 void __iomem *base; 1766 1767 if (of_address_to_resource(bank->of_node, 0, &res)) { 1768 dev_err(info->dev, "cannot find IO resource for bank\n"); 1769 return -ENOENT; 1770 } 1771 1772 bank->reg_base = devm_ioremap_resource(info->dev, &res); 1773 if (IS_ERR(bank->reg_base)) 1774 return PTR_ERR(bank->reg_base); 1775 1776 /* 1777 * special case, where parts of the pull setting-registers are 1778 * part of the PMU register space 1779 */ 1780 if (of_device_is_compatible(bank->of_node, 1781 "rockchip,rk3188-gpio-bank0")) { 1782 struct device_node *node; 1783 1784 node = of_parse_phandle(bank->of_node->parent, 1785 "rockchip,pmu", 0); 1786 if (!node) { 1787 if (of_address_to_resource(bank->of_node, 1, &res)) { 1788 dev_err(info->dev, "cannot find IO resource for bank\n"); 1789 return -ENOENT; 1790 } 1791 1792 base = devm_ioremap_resource(info->dev, &res); 1793 if (IS_ERR(base)) 1794 return PTR_ERR(base); 1795 rockchip_regmap_config.max_register = 1796 resource_size(&res) - 4; 1797 rockchip_regmap_config.name = 1798 "rockchip,rk3188-gpio-bank0-pull"; 1799 bank->regmap_pull = devm_regmap_init_mmio(info->dev, 1800 base, 1801 &rockchip_regmap_config); 1802 } 1803 } 1804 1805 bank->irq = irq_of_parse_and_map(bank->of_node, 0); 1806 1807 bank->clk = of_clk_get(bank->of_node, 0); 1808 if (IS_ERR(bank->clk)) 1809 return PTR_ERR(bank->clk); 1810 1811 return clk_prepare_enable(bank->clk); 1812 } 1813 1814 static const struct of_device_id rockchip_pinctrl_dt_match[]; 1815 1816 /* retrieve the soc specific data */ 1817 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data( 1818 struct rockchip_pinctrl *d, 1819 struct platform_device *pdev) 1820 { 1821 const struct of_device_id *match; 1822 struct device_node *node = pdev->dev.of_node; 1823 struct device_node *np; 1824 struct rockchip_pin_ctrl *ctrl; 1825 struct rockchip_pin_bank *bank; 1826 int grf_offs, pmu_offs, i, j; 1827 1828 match = of_match_node(rockchip_pinctrl_dt_match, node); 1829 ctrl = (struct rockchip_pin_ctrl *)match->data; 1830 1831 for_each_child_of_node(node, np) { 1832 if (!of_find_property(np, "gpio-controller", NULL)) 1833 continue; 1834 1835 bank = ctrl->pin_banks; 1836 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 1837 if (!strcmp(bank->name, np->name)) { 1838 bank->of_node = np; 1839 1840 if (!rockchip_get_bank_data(bank, d)) 1841 bank->valid = true; 1842 1843 break; 1844 } 1845 } 1846 } 1847 1848 grf_offs = ctrl->grf_mux_offset; 1849 pmu_offs = ctrl->pmu_mux_offset; 1850 bank = ctrl->pin_banks; 1851 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 1852 int bank_pins = 0; 1853 1854 spin_lock_init(&bank->slock); 1855 bank->drvdata = d; 1856 bank->pin_base = ctrl->nr_pins; 1857 ctrl->nr_pins += bank->nr_pins; 1858 1859 /* calculate iomux offsets */ 1860 for (j = 0; j < 4; j++) { 1861 struct rockchip_iomux *iom = &bank->iomux[j]; 1862 int inc; 1863 1864 if (bank_pins >= bank->nr_pins) 1865 break; 1866 1867 /* preset offset value, set new start value */ 1868 if (iom->offset >= 0) { 1869 if (iom->type & IOMUX_SOURCE_PMU) 1870 pmu_offs = iom->offset; 1871 else 1872 grf_offs = iom->offset; 1873 } else { /* set current offset */ 1874 iom->offset = (iom->type & IOMUX_SOURCE_PMU) ? 1875 pmu_offs : grf_offs; 1876 } 1877 1878 dev_dbg(d->dev, "bank %d, iomux %d has offset 0x%x\n", 1879 i, j, iom->offset); 1880 1881 /* 1882 * Increase offset according to iomux width. 1883 * 4bit iomux'es are spread over two registers. 1884 */ 1885 inc = (iom->type & IOMUX_WIDTH_4BIT) ? 8 : 4; 1886 if (iom->type & IOMUX_SOURCE_PMU) 1887 pmu_offs += inc; 1888 else 1889 grf_offs += inc; 1890 1891 bank_pins += 8; 1892 } 1893 } 1894 1895 return ctrl; 1896 } 1897 1898 #define RK3288_GRF_GPIO6C_IOMUX 0x64 1899 #define GPIO6C6_SEL_WRITE_ENABLE BIT(28) 1900 1901 static u32 rk3288_grf_gpio6c_iomux; 1902 1903 static int __maybe_unused rockchip_pinctrl_suspend(struct device *dev) 1904 { 1905 struct rockchip_pinctrl *info = dev_get_drvdata(dev); 1906 int ret = pinctrl_force_sleep(info->pctl_dev); 1907 1908 if (ret) 1909 return ret; 1910 1911 /* 1912 * RK3288 GPIO6_C6 mux would be modified by Maskrom when resume, so save 1913 * the setting here, and restore it at resume. 1914 */ 1915 if (info->ctrl->type == RK3288) { 1916 ret = regmap_read(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX, 1917 &rk3288_grf_gpio6c_iomux); 1918 if (ret) { 1919 pinctrl_force_default(info->pctl_dev); 1920 return ret; 1921 } 1922 } 1923 1924 return 0; 1925 } 1926 1927 static int __maybe_unused rockchip_pinctrl_resume(struct device *dev) 1928 { 1929 struct rockchip_pinctrl *info = dev_get_drvdata(dev); 1930 int ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX, 1931 rk3288_grf_gpio6c_iomux | 1932 GPIO6C6_SEL_WRITE_ENABLE); 1933 1934 if (ret) 1935 return ret; 1936 1937 return pinctrl_force_default(info->pctl_dev); 1938 } 1939 1940 static SIMPLE_DEV_PM_OPS(rockchip_pinctrl_dev_pm_ops, rockchip_pinctrl_suspend, 1941 rockchip_pinctrl_resume); 1942 1943 static int rockchip_pinctrl_probe(struct platform_device *pdev) 1944 { 1945 struct rockchip_pinctrl *info; 1946 struct device *dev = &pdev->dev; 1947 struct rockchip_pin_ctrl *ctrl; 1948 struct device_node *np = pdev->dev.of_node, *node; 1949 struct resource *res; 1950 void __iomem *base; 1951 int ret; 1952 1953 if (!dev->of_node) { 1954 dev_err(dev, "device tree node not found\n"); 1955 return -ENODEV; 1956 } 1957 1958 info = devm_kzalloc(dev, sizeof(struct rockchip_pinctrl), GFP_KERNEL); 1959 if (!info) 1960 return -ENOMEM; 1961 1962 info->dev = dev; 1963 1964 ctrl = rockchip_pinctrl_get_soc_data(info, pdev); 1965 if (!ctrl) { 1966 dev_err(dev, "driver data not available\n"); 1967 return -EINVAL; 1968 } 1969 info->ctrl = ctrl; 1970 1971 node = of_parse_phandle(np, "rockchip,grf", 0); 1972 if (node) { 1973 info->regmap_base = syscon_node_to_regmap(node); 1974 if (IS_ERR(info->regmap_base)) 1975 return PTR_ERR(info->regmap_base); 1976 } else { 1977 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1978 base = devm_ioremap_resource(&pdev->dev, res); 1979 if (IS_ERR(base)) 1980 return PTR_ERR(base); 1981 1982 rockchip_regmap_config.max_register = resource_size(res) - 4; 1983 rockchip_regmap_config.name = "rockchip,pinctrl"; 1984 info->regmap_base = devm_regmap_init_mmio(&pdev->dev, base, 1985 &rockchip_regmap_config); 1986 1987 /* to check for the old dt-bindings */ 1988 info->reg_size = resource_size(res); 1989 1990 /* Honor the old binding, with pull registers as 2nd resource */ 1991 if (ctrl->type == RK3188 && info->reg_size < 0x200) { 1992 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 1993 base = devm_ioremap_resource(&pdev->dev, res); 1994 if (IS_ERR(base)) 1995 return PTR_ERR(base); 1996 1997 rockchip_regmap_config.max_register = 1998 resource_size(res) - 4; 1999 rockchip_regmap_config.name = "rockchip,pinctrl-pull"; 2000 info->regmap_pull = devm_regmap_init_mmio(&pdev->dev, 2001 base, 2002 &rockchip_regmap_config); 2003 } 2004 } 2005 2006 /* try to find the optional reference to the pmu syscon */ 2007 node = of_parse_phandle(np, "rockchip,pmu", 0); 2008 if (node) { 2009 info->regmap_pmu = syscon_node_to_regmap(node); 2010 if (IS_ERR(info->regmap_pmu)) 2011 return PTR_ERR(info->regmap_pmu); 2012 } 2013 2014 ret = rockchip_gpiolib_register(pdev, info); 2015 if (ret) 2016 return ret; 2017 2018 ret = rockchip_pinctrl_register(pdev, info); 2019 if (ret) { 2020 rockchip_gpiolib_unregister(pdev, info); 2021 return ret; 2022 } 2023 2024 platform_set_drvdata(pdev, info); 2025 2026 return 0; 2027 } 2028 2029 static struct rockchip_pin_bank rk2928_pin_banks[] = { 2030 PIN_BANK(0, 32, "gpio0"), 2031 PIN_BANK(1, 32, "gpio1"), 2032 PIN_BANK(2, 32, "gpio2"), 2033 PIN_BANK(3, 32, "gpio3"), 2034 }; 2035 2036 static struct rockchip_pin_ctrl rk2928_pin_ctrl = { 2037 .pin_banks = rk2928_pin_banks, 2038 .nr_banks = ARRAY_SIZE(rk2928_pin_banks), 2039 .label = "RK2928-GPIO", 2040 .type = RK2928, 2041 .grf_mux_offset = 0xa8, 2042 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 2043 }; 2044 2045 static struct rockchip_pin_bank rk3066a_pin_banks[] = { 2046 PIN_BANK(0, 32, "gpio0"), 2047 PIN_BANK(1, 32, "gpio1"), 2048 PIN_BANK(2, 32, "gpio2"), 2049 PIN_BANK(3, 32, "gpio3"), 2050 PIN_BANK(4, 32, "gpio4"), 2051 PIN_BANK(6, 16, "gpio6"), 2052 }; 2053 2054 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = { 2055 .pin_banks = rk3066a_pin_banks, 2056 .nr_banks = ARRAY_SIZE(rk3066a_pin_banks), 2057 .label = "RK3066a-GPIO", 2058 .type = RK2928, 2059 .grf_mux_offset = 0xa8, 2060 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 2061 }; 2062 2063 static struct rockchip_pin_bank rk3066b_pin_banks[] = { 2064 PIN_BANK(0, 32, "gpio0"), 2065 PIN_BANK(1, 32, "gpio1"), 2066 PIN_BANK(2, 32, "gpio2"), 2067 PIN_BANK(3, 32, "gpio3"), 2068 }; 2069 2070 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = { 2071 .pin_banks = rk3066b_pin_banks, 2072 .nr_banks = ARRAY_SIZE(rk3066b_pin_banks), 2073 .label = "RK3066b-GPIO", 2074 .type = RK3066B, 2075 .grf_mux_offset = 0x60, 2076 }; 2077 2078 static struct rockchip_pin_bank rk3188_pin_banks[] = { 2079 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0), 2080 PIN_BANK(1, 32, "gpio1"), 2081 PIN_BANK(2, 32, "gpio2"), 2082 PIN_BANK(3, 32, "gpio3"), 2083 }; 2084 2085 static struct rockchip_pin_ctrl rk3188_pin_ctrl = { 2086 .pin_banks = rk3188_pin_banks, 2087 .nr_banks = ARRAY_SIZE(rk3188_pin_banks), 2088 .label = "RK3188-GPIO", 2089 .type = RK3188, 2090 .grf_mux_offset = 0x60, 2091 .pull_calc_reg = rk3188_calc_pull_reg_and_bit, 2092 }; 2093 2094 static struct rockchip_pin_bank rk3288_pin_banks[] = { 2095 PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU, 2096 IOMUX_SOURCE_PMU, 2097 IOMUX_SOURCE_PMU, 2098 IOMUX_UNROUTED 2099 ), 2100 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED, 2101 IOMUX_UNROUTED, 2102 IOMUX_UNROUTED, 2103 0 2104 ), 2105 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED), 2106 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT), 2107 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT, 2108 IOMUX_WIDTH_4BIT, 2109 0, 2110 0 2111 ), 2112 PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED, 2113 0, 2114 0, 2115 IOMUX_UNROUTED 2116 ), 2117 PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED), 2118 PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0, 2119 0, 2120 IOMUX_WIDTH_4BIT, 2121 IOMUX_UNROUTED 2122 ), 2123 PIN_BANK(8, 16, "gpio8"), 2124 }; 2125 2126 static struct rockchip_pin_ctrl rk3288_pin_ctrl = { 2127 .pin_banks = rk3288_pin_banks, 2128 .nr_banks = ARRAY_SIZE(rk3288_pin_banks), 2129 .label = "RK3288-GPIO", 2130 .type = RK3288, 2131 .grf_mux_offset = 0x0, 2132 .pmu_mux_offset = 0x84, 2133 .pull_calc_reg = rk3288_calc_pull_reg_and_bit, 2134 .drv_calc_reg = rk3288_calc_drv_reg_and_bit, 2135 }; 2136 2137 static struct rockchip_pin_bank rk3368_pin_banks[] = { 2138 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, 2139 IOMUX_SOURCE_PMU, 2140 IOMUX_SOURCE_PMU, 2141 IOMUX_SOURCE_PMU 2142 ), 2143 PIN_BANK(1, 32, "gpio1"), 2144 PIN_BANK(2, 32, "gpio2"), 2145 PIN_BANK(3, 32, "gpio3"), 2146 }; 2147 2148 static struct rockchip_pin_ctrl rk3368_pin_ctrl = { 2149 .pin_banks = rk3368_pin_banks, 2150 .nr_banks = ARRAY_SIZE(rk3368_pin_banks), 2151 .label = "RK3368-GPIO", 2152 .type = RK3368, 2153 .grf_mux_offset = 0x0, 2154 .pmu_mux_offset = 0x0, 2155 .pull_calc_reg = rk3368_calc_pull_reg_and_bit, 2156 .drv_calc_reg = rk3368_calc_drv_reg_and_bit, 2157 }; 2158 2159 2160 static const struct of_device_id rockchip_pinctrl_dt_match[] = { 2161 { .compatible = "rockchip,rk2928-pinctrl", 2162 .data = (void *)&rk2928_pin_ctrl }, 2163 { .compatible = "rockchip,rk3066a-pinctrl", 2164 .data = (void *)&rk3066a_pin_ctrl }, 2165 { .compatible = "rockchip,rk3066b-pinctrl", 2166 .data = (void *)&rk3066b_pin_ctrl }, 2167 { .compatible = "rockchip,rk3188-pinctrl", 2168 .data = (void *)&rk3188_pin_ctrl }, 2169 { .compatible = "rockchip,rk3288-pinctrl", 2170 .data = (void *)&rk3288_pin_ctrl }, 2171 { .compatible = "rockchip,rk3368-pinctrl", 2172 .data = (void *)&rk3368_pin_ctrl }, 2173 {}, 2174 }; 2175 MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match); 2176 2177 static struct platform_driver rockchip_pinctrl_driver = { 2178 .probe = rockchip_pinctrl_probe, 2179 .driver = { 2180 .name = "rockchip-pinctrl", 2181 .pm = &rockchip_pinctrl_dev_pm_ops, 2182 .of_match_table = rockchip_pinctrl_dt_match, 2183 }, 2184 }; 2185 2186 static int __init rockchip_pinctrl_drv_register(void) 2187 { 2188 return platform_driver_register(&rockchip_pinctrl_driver); 2189 } 2190 postcore_initcall(rockchip_pinctrl_drv_register); 2191 2192 MODULE_AUTHOR("Heiko Stuebner <heiko@sntech.de>"); 2193 MODULE_DESCRIPTION("Rockchip pinctrl driver"); 2194 MODULE_LICENSE("GPL v2"); 2195