1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Pinctrl driver for Rockchip SoCs 4 * 5 * Copyright (c) 2013 MundoReader S.L. 6 * Author: Heiko Stuebner <heiko@sntech.de> 7 * 8 * With some ideas taken from pinctrl-samsung: 9 * Copyright (c) 2012 Samsung Electronics Co., Ltd. 10 * http://www.samsung.com 11 * Copyright (c) 2012 Linaro Ltd 12 * https://www.linaro.org 13 * 14 * and pinctrl-at91: 15 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> 16 */ 17 18 #include <linux/init.h> 19 #include <linux/module.h> 20 #include <linux/platform_device.h> 21 #include <linux/io.h> 22 #include <linux/bitops.h> 23 #include <linux/gpio/driver.h> 24 #include <linux/of_address.h> 25 #include <linux/of_device.h> 26 #include <linux/of_irq.h> 27 #include <linux/pinctrl/machine.h> 28 #include <linux/pinctrl/pinconf.h> 29 #include <linux/pinctrl/pinctrl.h> 30 #include <linux/pinctrl/pinmux.h> 31 #include <linux/pinctrl/pinconf-generic.h> 32 #include <linux/irqchip/chained_irq.h> 33 #include <linux/clk.h> 34 #include <linux/regmap.h> 35 #include <linux/mfd/syscon.h> 36 #include <linux/string_helpers.h> 37 38 #include <dt-bindings/pinctrl/rockchip.h> 39 40 #include "core.h" 41 #include "pinconf.h" 42 #include "pinctrl-rockchip.h" 43 44 /* 45 * Generate a bitmask for setting a value (v) with a write mask bit in hiword 46 * register 31:16 area. 47 */ 48 #define WRITE_MASK_VAL(h, l, v) \ 49 (GENMASK(((h) + 16), ((l) + 16)) | (((v) << (l)) & GENMASK((h), (l)))) 50 51 /* 52 * Encode variants of iomux registers into a type variable 53 */ 54 #define IOMUX_GPIO_ONLY BIT(0) 55 #define IOMUX_WIDTH_4BIT BIT(1) 56 #define IOMUX_SOURCE_PMU BIT(2) 57 #define IOMUX_UNROUTED BIT(3) 58 #define IOMUX_WIDTH_3BIT BIT(4) 59 #define IOMUX_WIDTH_2BIT BIT(5) 60 61 #define PIN_BANK(id, pins, label) \ 62 { \ 63 .bank_num = id, \ 64 .nr_pins = pins, \ 65 .name = label, \ 66 .iomux = { \ 67 { .offset = -1 }, \ 68 { .offset = -1 }, \ 69 { .offset = -1 }, \ 70 { .offset = -1 }, \ 71 }, \ 72 } 73 74 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \ 75 { \ 76 .bank_num = id, \ 77 .nr_pins = pins, \ 78 .name = label, \ 79 .iomux = { \ 80 { .type = iom0, .offset = -1 }, \ 81 { .type = iom1, .offset = -1 }, \ 82 { .type = iom2, .offset = -1 }, \ 83 { .type = iom3, .offset = -1 }, \ 84 }, \ 85 } 86 87 #define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \ 88 { \ 89 .bank_num = id, \ 90 .nr_pins = pins, \ 91 .name = label, \ 92 .iomux = { \ 93 { .offset = -1 }, \ 94 { .offset = -1 }, \ 95 { .offset = -1 }, \ 96 { .offset = -1 }, \ 97 }, \ 98 .drv = { \ 99 { .drv_type = type0, .offset = -1 }, \ 100 { .drv_type = type1, .offset = -1 }, \ 101 { .drv_type = type2, .offset = -1 }, \ 102 { .drv_type = type3, .offset = -1 }, \ 103 }, \ 104 } 105 106 #define PIN_BANK_IOMUX_FLAGS_PULL_FLAGS(id, pins, label, iom0, iom1, \ 107 iom2, iom3, pull0, pull1, \ 108 pull2, pull3) \ 109 { \ 110 .bank_num = id, \ 111 .nr_pins = pins, \ 112 .name = label, \ 113 .iomux = { \ 114 { .type = iom0, .offset = -1 }, \ 115 { .type = iom1, .offset = -1 }, \ 116 { .type = iom2, .offset = -1 }, \ 117 { .type = iom3, .offset = -1 }, \ 118 }, \ 119 .pull_type[0] = pull0, \ 120 .pull_type[1] = pull1, \ 121 .pull_type[2] = pull2, \ 122 .pull_type[3] = pull3, \ 123 } 124 125 #define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1, \ 126 drv2, drv3, pull0, pull1, \ 127 pull2, pull3) \ 128 { \ 129 .bank_num = id, \ 130 .nr_pins = pins, \ 131 .name = label, \ 132 .iomux = { \ 133 { .offset = -1 }, \ 134 { .offset = -1 }, \ 135 { .offset = -1 }, \ 136 { .offset = -1 }, \ 137 }, \ 138 .drv = { \ 139 { .drv_type = drv0, .offset = -1 }, \ 140 { .drv_type = drv1, .offset = -1 }, \ 141 { .drv_type = drv2, .offset = -1 }, \ 142 { .drv_type = drv3, .offset = -1 }, \ 143 }, \ 144 .pull_type[0] = pull0, \ 145 .pull_type[1] = pull1, \ 146 .pull_type[2] = pull2, \ 147 .pull_type[3] = pull3, \ 148 } 149 150 #define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1, \ 151 iom2, iom3, drv0, drv1, drv2, \ 152 drv3, offset0, offset1, \ 153 offset2, offset3) \ 154 { \ 155 .bank_num = id, \ 156 .nr_pins = pins, \ 157 .name = label, \ 158 .iomux = { \ 159 { .type = iom0, .offset = -1 }, \ 160 { .type = iom1, .offset = -1 }, \ 161 { .type = iom2, .offset = -1 }, \ 162 { .type = iom3, .offset = -1 }, \ 163 }, \ 164 .drv = { \ 165 { .drv_type = drv0, .offset = offset0 }, \ 166 { .drv_type = drv1, .offset = offset1 }, \ 167 { .drv_type = drv2, .offset = offset2 }, \ 168 { .drv_type = drv3, .offset = offset3 }, \ 169 }, \ 170 } 171 172 #define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins, \ 173 label, iom0, iom1, iom2, \ 174 iom3, drv0, drv1, drv2, \ 175 drv3, offset0, offset1, \ 176 offset2, offset3, pull0, \ 177 pull1, pull2, pull3) \ 178 { \ 179 .bank_num = id, \ 180 .nr_pins = pins, \ 181 .name = label, \ 182 .iomux = { \ 183 { .type = iom0, .offset = -1 }, \ 184 { .type = iom1, .offset = -1 }, \ 185 { .type = iom2, .offset = -1 }, \ 186 { .type = iom3, .offset = -1 }, \ 187 }, \ 188 .drv = { \ 189 { .drv_type = drv0, .offset = offset0 }, \ 190 { .drv_type = drv1, .offset = offset1 }, \ 191 { .drv_type = drv2, .offset = offset2 }, \ 192 { .drv_type = drv3, .offset = offset3 }, \ 193 }, \ 194 .pull_type[0] = pull0, \ 195 .pull_type[1] = pull1, \ 196 .pull_type[2] = pull2, \ 197 .pull_type[3] = pull3, \ 198 } 199 200 #define PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, FLAG) \ 201 { \ 202 .bank_num = ID, \ 203 .pin = PIN, \ 204 .func = FUNC, \ 205 .route_offset = REG, \ 206 .route_val = VAL, \ 207 .route_location = FLAG, \ 208 } 209 210 #define RK_MUXROUTE_SAME(ID, PIN, FUNC, REG, VAL) \ 211 PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_SAME) 212 213 #define RK_MUXROUTE_GRF(ID, PIN, FUNC, REG, VAL) \ 214 PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_GRF) 215 216 #define RK_MUXROUTE_PMU(ID, PIN, FUNC, REG, VAL) \ 217 PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_PMU) 218 219 #define RK3588_PIN_BANK_FLAGS(ID, PIN, LABEL, M, P) \ 220 PIN_BANK_IOMUX_FLAGS_PULL_FLAGS(ID, PIN, LABEL, M, M, M, M, P, P, P, P) 221 222 static struct regmap_config rockchip_regmap_config = { 223 .reg_bits = 32, 224 .val_bits = 32, 225 .reg_stride = 4, 226 }; 227 228 static inline const struct rockchip_pin_group *pinctrl_name_to_group( 229 const struct rockchip_pinctrl *info, 230 const char *name) 231 { 232 int i; 233 234 for (i = 0; i < info->ngroups; i++) { 235 if (!strcmp(info->groups[i].name, name)) 236 return &info->groups[i]; 237 } 238 239 return NULL; 240 } 241 242 /* 243 * given a pin number that is local to a pin controller, find out the pin bank 244 * and the register base of the pin bank. 245 */ 246 static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info, 247 unsigned pin) 248 { 249 struct rockchip_pin_bank *b = info->ctrl->pin_banks; 250 251 while (pin >= (b->pin_base + b->nr_pins)) 252 b++; 253 254 return b; 255 } 256 257 static struct rockchip_pin_bank *bank_num_to_bank( 258 struct rockchip_pinctrl *info, 259 unsigned num) 260 { 261 struct rockchip_pin_bank *b = info->ctrl->pin_banks; 262 int i; 263 264 for (i = 0; i < info->ctrl->nr_banks; i++, b++) { 265 if (b->bank_num == num) 266 return b; 267 } 268 269 return ERR_PTR(-EINVAL); 270 } 271 272 /* 273 * Pinctrl_ops handling 274 */ 275 276 static int rockchip_get_groups_count(struct pinctrl_dev *pctldev) 277 { 278 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 279 280 return info->ngroups; 281 } 282 283 static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev, 284 unsigned selector) 285 { 286 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 287 288 return info->groups[selector].name; 289 } 290 291 static int rockchip_get_group_pins(struct pinctrl_dev *pctldev, 292 unsigned selector, const unsigned **pins, 293 unsigned *npins) 294 { 295 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 296 297 if (selector >= info->ngroups) 298 return -EINVAL; 299 300 *pins = info->groups[selector].pins; 301 *npins = info->groups[selector].npins; 302 303 return 0; 304 } 305 306 static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev, 307 struct device_node *np, 308 struct pinctrl_map **map, unsigned *num_maps) 309 { 310 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 311 const struct rockchip_pin_group *grp; 312 struct device *dev = info->dev; 313 struct pinctrl_map *new_map; 314 struct device_node *parent; 315 int map_num = 1; 316 int i; 317 318 /* 319 * first find the group of this node and check if we need to create 320 * config maps for pins 321 */ 322 grp = pinctrl_name_to_group(info, np->name); 323 if (!grp) { 324 dev_err(dev, "unable to find group for node %pOFn\n", np); 325 return -EINVAL; 326 } 327 328 map_num += grp->npins; 329 330 new_map = kcalloc(map_num, sizeof(*new_map), GFP_KERNEL); 331 if (!new_map) 332 return -ENOMEM; 333 334 *map = new_map; 335 *num_maps = map_num; 336 337 /* create mux map */ 338 parent = of_get_parent(np); 339 if (!parent) { 340 kfree(new_map); 341 return -EINVAL; 342 } 343 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP; 344 new_map[0].data.mux.function = parent->name; 345 new_map[0].data.mux.group = np->name; 346 of_node_put(parent); 347 348 /* create config map */ 349 new_map++; 350 for (i = 0; i < grp->npins; i++) { 351 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN; 352 new_map[i].data.configs.group_or_pin = 353 pin_get_name(pctldev, grp->pins[i]); 354 new_map[i].data.configs.configs = grp->data[i].configs; 355 new_map[i].data.configs.num_configs = grp->data[i].nconfigs; 356 } 357 358 dev_dbg(dev, "maps: function %s group %s num %d\n", 359 (*map)->data.mux.function, (*map)->data.mux.group, map_num); 360 361 return 0; 362 } 363 364 static void rockchip_dt_free_map(struct pinctrl_dev *pctldev, 365 struct pinctrl_map *map, unsigned num_maps) 366 { 367 kfree(map); 368 } 369 370 static const struct pinctrl_ops rockchip_pctrl_ops = { 371 .get_groups_count = rockchip_get_groups_count, 372 .get_group_name = rockchip_get_group_name, 373 .get_group_pins = rockchip_get_group_pins, 374 .dt_node_to_map = rockchip_dt_node_to_map, 375 .dt_free_map = rockchip_dt_free_map, 376 }; 377 378 /* 379 * Hardware access 380 */ 381 382 static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = { 383 { 384 .num = 1, 385 .pin = 0, 386 .reg = 0x418, 387 .bit = 0, 388 .mask = 0x3 389 }, { 390 .num = 1, 391 .pin = 1, 392 .reg = 0x418, 393 .bit = 2, 394 .mask = 0x3 395 }, { 396 .num = 1, 397 .pin = 2, 398 .reg = 0x418, 399 .bit = 4, 400 .mask = 0x3 401 }, { 402 .num = 1, 403 .pin = 3, 404 .reg = 0x418, 405 .bit = 6, 406 .mask = 0x3 407 }, { 408 .num = 1, 409 .pin = 4, 410 .reg = 0x418, 411 .bit = 8, 412 .mask = 0x3 413 }, { 414 .num = 1, 415 .pin = 5, 416 .reg = 0x418, 417 .bit = 10, 418 .mask = 0x3 419 }, { 420 .num = 1, 421 .pin = 6, 422 .reg = 0x418, 423 .bit = 12, 424 .mask = 0x3 425 }, { 426 .num = 1, 427 .pin = 7, 428 .reg = 0x418, 429 .bit = 14, 430 .mask = 0x3 431 }, { 432 .num = 1, 433 .pin = 8, 434 .reg = 0x41c, 435 .bit = 0, 436 .mask = 0x3 437 }, { 438 .num = 1, 439 .pin = 9, 440 .reg = 0x41c, 441 .bit = 2, 442 .mask = 0x3 443 }, 444 }; 445 446 static struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = { 447 { 448 .num = 2, 449 .pin = 20, 450 .reg = 0xe8, 451 .bit = 0, 452 .mask = 0x7 453 }, { 454 .num = 2, 455 .pin = 21, 456 .reg = 0xe8, 457 .bit = 4, 458 .mask = 0x7 459 }, { 460 .num = 2, 461 .pin = 22, 462 .reg = 0xe8, 463 .bit = 8, 464 .mask = 0x7 465 }, { 466 .num = 2, 467 .pin = 23, 468 .reg = 0xe8, 469 .bit = 12, 470 .mask = 0x7 471 }, { 472 .num = 2, 473 .pin = 24, 474 .reg = 0xd4, 475 .bit = 12, 476 .mask = 0x7 477 }, 478 }; 479 480 static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = { 481 { 482 /* gpio1b6_sel */ 483 .num = 1, 484 .pin = 14, 485 .reg = 0x28, 486 .bit = 12, 487 .mask = 0xf 488 }, { 489 /* gpio1b7_sel */ 490 .num = 1, 491 .pin = 15, 492 .reg = 0x2c, 493 .bit = 0, 494 .mask = 0x3 495 }, { 496 /* gpio1c2_sel */ 497 .num = 1, 498 .pin = 18, 499 .reg = 0x30, 500 .bit = 4, 501 .mask = 0xf 502 }, { 503 /* gpio1c3_sel */ 504 .num = 1, 505 .pin = 19, 506 .reg = 0x30, 507 .bit = 8, 508 .mask = 0xf 509 }, { 510 /* gpio1c4_sel */ 511 .num = 1, 512 .pin = 20, 513 .reg = 0x30, 514 .bit = 12, 515 .mask = 0xf 516 }, { 517 /* gpio1c5_sel */ 518 .num = 1, 519 .pin = 21, 520 .reg = 0x34, 521 .bit = 0, 522 .mask = 0xf 523 }, { 524 /* gpio1c6_sel */ 525 .num = 1, 526 .pin = 22, 527 .reg = 0x34, 528 .bit = 4, 529 .mask = 0xf 530 }, { 531 /* gpio1c7_sel */ 532 .num = 1, 533 .pin = 23, 534 .reg = 0x34, 535 .bit = 8, 536 .mask = 0xf 537 }, { 538 /* gpio2a2_sel */ 539 .num = 2, 540 .pin = 2, 541 .reg = 0x40, 542 .bit = 4, 543 .mask = 0x3 544 }, { 545 /* gpio2a3_sel */ 546 .num = 2, 547 .pin = 3, 548 .reg = 0x40, 549 .bit = 6, 550 .mask = 0x3 551 }, { 552 /* gpio2c0_sel */ 553 .num = 2, 554 .pin = 16, 555 .reg = 0x50, 556 .bit = 0, 557 .mask = 0x3 558 }, { 559 /* gpio3b2_sel */ 560 .num = 3, 561 .pin = 10, 562 .reg = 0x68, 563 .bit = 4, 564 .mask = 0x3 565 }, { 566 /* gpio3b3_sel */ 567 .num = 3, 568 .pin = 11, 569 .reg = 0x68, 570 .bit = 6, 571 .mask = 0x3 572 }, { 573 /* gpio3b4_sel */ 574 .num = 3, 575 .pin = 12, 576 .reg = 0x68, 577 .bit = 8, 578 .mask = 0xf 579 }, { 580 /* gpio3b5_sel */ 581 .num = 3, 582 .pin = 13, 583 .reg = 0x68, 584 .bit = 12, 585 .mask = 0xf 586 }, 587 }; 588 589 static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = { 590 { 591 .num = 2, 592 .pin = 12, 593 .reg = 0x24, 594 .bit = 8, 595 .mask = 0x3 596 }, { 597 .num = 2, 598 .pin = 15, 599 .reg = 0x28, 600 .bit = 0, 601 .mask = 0x7 602 }, { 603 .num = 2, 604 .pin = 23, 605 .reg = 0x30, 606 .bit = 14, 607 .mask = 0x3 608 }, 609 }; 610 611 static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin, 612 int *reg, u8 *bit, int *mask) 613 { 614 struct rockchip_pinctrl *info = bank->drvdata; 615 struct rockchip_pin_ctrl *ctrl = info->ctrl; 616 struct rockchip_mux_recalced_data *data; 617 int i; 618 619 for (i = 0; i < ctrl->niomux_recalced; i++) { 620 data = &ctrl->iomux_recalced[i]; 621 if (data->num == bank->bank_num && 622 data->pin == pin) 623 break; 624 } 625 626 if (i >= ctrl->niomux_recalced) 627 return; 628 629 *reg = data->reg; 630 *mask = data->mask; 631 *bit = data->bit; 632 } 633 634 static struct rockchip_mux_route_data px30_mux_route_data[] = { 635 RK_MUXROUTE_SAME(2, RK_PA0, 1, 0x184, BIT(16 + 7)), /* cif-d2m0 */ 636 RK_MUXROUTE_SAME(3, RK_PA3, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d2m1 */ 637 RK_MUXROUTE_SAME(3, RK_PC6, 2, 0x184, BIT(16 + 8)), /* pdm-m0 */ 638 RK_MUXROUTE_SAME(2, RK_PC6, 1, 0x184, BIT(16 + 8) | BIT(8)), /* pdm-m1 */ 639 RK_MUXROUTE_SAME(1, RK_PD3, 2, 0x184, BIT(16 + 10)), /* uart2-rxm0 */ 640 RK_MUXROUTE_SAME(2, RK_PB6, 2, 0x184, BIT(16 + 10) | BIT(10)), /* uart2-rxm1 */ 641 RK_MUXROUTE_SAME(0, RK_PC1, 2, 0x184, BIT(16 + 9)), /* uart3-rxm0 */ 642 RK_MUXROUTE_SAME(1, RK_PB7, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-rxm1 */ 643 }; 644 645 static struct rockchip_mux_route_data rk3128_mux_route_data[] = { 646 RK_MUXROUTE_SAME(1, RK_PB2, 1, 0x144, BIT(16 + 3) | BIT(16 + 4)), /* spi-0 */ 647 RK_MUXROUTE_SAME(1, RK_PD3, 3, 0x144, BIT(16 + 3) | BIT(16 + 4) | BIT(3)), /* spi-1 */ 648 RK_MUXROUTE_SAME(0, RK_PB5, 2, 0x144, BIT(16 + 3) | BIT(16 + 4) | BIT(4)), /* spi-2 */ 649 RK_MUXROUTE_SAME(1, RK_PA5, 1, 0x144, BIT(16 + 5)), /* i2s-0 */ 650 RK_MUXROUTE_SAME(0, RK_PB6, 1, 0x144, BIT(16 + 5) | BIT(5)), /* i2s-1 */ 651 RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x144, BIT(16 + 6)), /* emmc-0 */ 652 RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x144, BIT(16 + 6) | BIT(6)), /* emmc-1 */ 653 }; 654 655 static struct rockchip_mux_route_data rk3188_mux_route_data[] = { 656 RK_MUXROUTE_SAME(0, RK_PD0, 1, 0xa0, BIT(16 + 11)), /* non-iomuxed emmc/flash pins on flash-dqs */ 657 RK_MUXROUTE_SAME(0, RK_PD0, 2, 0xa0, BIT(16 + 11) | BIT(11)), /* non-iomuxed emmc/flash pins on emmc-clk */ 658 }; 659 660 static struct rockchip_mux_route_data rk3228_mux_route_data[] = { 661 RK_MUXROUTE_SAME(0, RK_PD2, 1, 0x50, BIT(16)), /* pwm0-0 */ 662 RK_MUXROUTE_SAME(3, RK_PC5, 1, 0x50, BIT(16) | BIT(0)), /* pwm0-1 */ 663 RK_MUXROUTE_SAME(0, RK_PD3, 1, 0x50, BIT(16 + 1)), /* pwm1-0 */ 664 RK_MUXROUTE_SAME(0, RK_PD6, 2, 0x50, BIT(16 + 1) | BIT(1)), /* pwm1-1 */ 665 RK_MUXROUTE_SAME(0, RK_PD4, 1, 0x50, BIT(16 + 2)), /* pwm2-0 */ 666 RK_MUXROUTE_SAME(1, RK_PB4, 2, 0x50, BIT(16 + 2) | BIT(2)), /* pwm2-1 */ 667 RK_MUXROUTE_SAME(3, RK_PD2, 1, 0x50, BIT(16 + 3)), /* pwm3-0 */ 668 RK_MUXROUTE_SAME(1, RK_PB3, 2, 0x50, BIT(16 + 3) | BIT(3)), /* pwm3-1 */ 669 RK_MUXROUTE_SAME(1, RK_PA1, 1, 0x50, BIT(16 + 4)), /* sdio-0_d0 */ 670 RK_MUXROUTE_SAME(3, RK_PA2, 1, 0x50, BIT(16 + 4) | BIT(4)), /* sdio-1_d0 */ 671 RK_MUXROUTE_SAME(0, RK_PB5, 2, 0x50, BIT(16 + 5)), /* spi-0_rx */ 672 RK_MUXROUTE_SAME(2, RK_PA0, 2, 0x50, BIT(16 + 5) | BIT(5)), /* spi-1_rx */ 673 RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x50, BIT(16 + 7)), /* emmc-0_cmd */ 674 RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x50, BIT(16 + 7) | BIT(7)), /* emmc-1_cmd */ 675 RK_MUXROUTE_SAME(1, RK_PC3, 2, 0x50, BIT(16 + 8)), /* uart2-0_rx */ 676 RK_MUXROUTE_SAME(1, RK_PB2, 2, 0x50, BIT(16 + 8) | BIT(8)), /* uart2-1_rx */ 677 RK_MUXROUTE_SAME(1, RK_PB2, 1, 0x50, BIT(16 + 11)), /* uart1-0_rx */ 678 RK_MUXROUTE_SAME(3, RK_PB5, 1, 0x50, BIT(16 + 11) | BIT(11)), /* uart1-1_rx */ 679 }; 680 681 static struct rockchip_mux_route_data rk3288_mux_route_data[] = { 682 RK_MUXROUTE_SAME(7, RK_PC0, 2, 0x264, BIT(16 + 12) | BIT(12)), /* edphdmi_cecinoutt1 */ 683 RK_MUXROUTE_SAME(7, RK_PC7, 4, 0x264, BIT(16 + 12)), /* edphdmi_cecinout */ 684 }; 685 686 static struct rockchip_mux_route_data rk3308_mux_route_data[] = { 687 RK_MUXROUTE_SAME(0, RK_PC3, 1, 0x314, BIT(16 + 0) | BIT(0)), /* rtc_clk */ 688 RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x314, BIT(16 + 2) | BIT(16 + 3)), /* uart2_rxm0 */ 689 RK_MUXROUTE_SAME(4, RK_PD2, 2, 0x314, BIT(16 + 2) | BIT(16 + 3) | BIT(2)), /* uart2_rxm1 */ 690 RK_MUXROUTE_SAME(0, RK_PB7, 2, 0x608, BIT(16 + 8) | BIT(16 + 9)), /* i2c3_sdam0 */ 691 RK_MUXROUTE_SAME(3, RK_PB4, 2, 0x608, BIT(16 + 8) | BIT(16 + 9) | BIT(8)), /* i2c3_sdam1 */ 692 RK_MUXROUTE_SAME(2, RK_PA0, 3, 0x608, BIT(16 + 8) | BIT(16 + 9) | BIT(9)), /* i2c3_sdam2 */ 693 RK_MUXROUTE_SAME(1, RK_PA3, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclktxm0 */ 694 RK_MUXROUTE_SAME(1, RK_PA4, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclkrxm0 */ 695 RK_MUXROUTE_SAME(1, RK_PB5, 2, 0x308, BIT(16 + 3) | BIT(3)), /* i2s-8ch-1-sclktxm1 */ 696 RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x308, BIT(16 + 3) | BIT(3)), /* i2s-8ch-1-sclkrxm1 */ 697 RK_MUXROUTE_SAME(1, RK_PA4, 3, 0x308, BIT(16 + 12) | BIT(16 + 13)), /* pdm-clkm0 */ 698 RK_MUXROUTE_SAME(1, RK_PB6, 4, 0x308, BIT(16 + 12) | BIT(16 + 13) | BIT(12)), /* pdm-clkm1 */ 699 RK_MUXROUTE_SAME(2, RK_PA6, 2, 0x308, BIT(16 + 12) | BIT(16 + 13) | BIT(13)), /* pdm-clkm2 */ 700 RK_MUXROUTE_SAME(2, RK_PA4, 3, 0x600, BIT(16 + 2) | BIT(2)), /* pdm-clkm-m2 */ 701 RK_MUXROUTE_SAME(3, RK_PB2, 3, 0x314, BIT(16 + 9)), /* spi1_miso */ 702 RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x314, BIT(16 + 9) | BIT(9)), /* spi1_miso_m1 */ 703 RK_MUXROUTE_SAME(0, RK_PB3, 3, 0x314, BIT(16 + 10) | BIT(16 + 11)), /* owire_m0 */ 704 RK_MUXROUTE_SAME(1, RK_PC6, 7, 0x314, BIT(16 + 10) | BIT(16 + 11) | BIT(10)), /* owire_m1 */ 705 RK_MUXROUTE_SAME(2, RK_PA2, 5, 0x314, BIT(16 + 10) | BIT(16 + 11) | BIT(11)), /* owire_m2 */ 706 RK_MUXROUTE_SAME(0, RK_PB3, 2, 0x314, BIT(16 + 12) | BIT(16 + 13)), /* can_rxd_m0 */ 707 RK_MUXROUTE_SAME(1, RK_PC6, 5, 0x314, BIT(16 + 12) | BIT(16 + 13) | BIT(12)), /* can_rxd_m1 */ 708 RK_MUXROUTE_SAME(2, RK_PA2, 4, 0x314, BIT(16 + 12) | BIT(16 + 13) | BIT(13)), /* can_rxd_m2 */ 709 RK_MUXROUTE_SAME(1, RK_PC4, 3, 0x314, BIT(16 + 14)), /* mac_rxd0_m0 */ 710 RK_MUXROUTE_SAME(4, RK_PA2, 2, 0x314, BIT(16 + 14) | BIT(14)), /* mac_rxd0_m1 */ 711 RK_MUXROUTE_SAME(3, RK_PB4, 4, 0x314, BIT(16 + 15)), /* uart3_rx */ 712 RK_MUXROUTE_SAME(0, RK_PC1, 3, 0x314, BIT(16 + 15) | BIT(15)), /* uart3_rx_m1 */ 713 }; 714 715 static struct rockchip_mux_route_data rk3328_mux_route_data[] = { 716 RK_MUXROUTE_SAME(1, RK_PA1, 2, 0x50, BIT(16) | BIT(16 + 1)), /* uart2dbg_rxm0 */ 717 RK_MUXROUTE_SAME(2, RK_PA1, 1, 0x50, BIT(16) | BIT(16 + 1) | BIT(0)), /* uart2dbg_rxm1 */ 718 RK_MUXROUTE_SAME(1, RK_PB3, 2, 0x50, BIT(16 + 2) | BIT(2)), /* gmac-m1_rxd0 */ 719 RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x50, BIT(16 + 10) | BIT(10)), /* gmac-m1-optimized_rxd3 */ 720 RK_MUXROUTE_SAME(2, RK_PC3, 2, 0x50, BIT(16 + 3)), /* pdm_sdi0m0 */ 721 RK_MUXROUTE_SAME(1, RK_PC7, 3, 0x50, BIT(16 + 3) | BIT(3)), /* pdm_sdi0m1 */ 722 RK_MUXROUTE_SAME(3, RK_PA2, 4, 0x50, BIT(16 + 4) | BIT(16 + 5) | BIT(5)), /* spi_rxdm2 */ 723 RK_MUXROUTE_SAME(1, RK_PD0, 1, 0x50, BIT(16 + 6)), /* i2s2_sdim0 */ 724 RK_MUXROUTE_SAME(3, RK_PA2, 6, 0x50, BIT(16 + 6) | BIT(6)), /* i2s2_sdim1 */ 725 RK_MUXROUTE_SAME(2, RK_PC6, 3, 0x50, BIT(16 + 7) | BIT(7)), /* card_iom1 */ 726 RK_MUXROUTE_SAME(2, RK_PC0, 3, 0x50, BIT(16 + 8) | BIT(8)), /* tsp_d5m1 */ 727 RK_MUXROUTE_SAME(2, RK_PC0, 4, 0x50, BIT(16 + 9) | BIT(9)), /* cif_data5m1 */ 728 }; 729 730 static struct rockchip_mux_route_data rk3399_mux_route_data[] = { 731 RK_MUXROUTE_SAME(4, RK_PB0, 2, 0xe21c, BIT(16 + 10) | BIT(16 + 11)), /* uart2dbga_rx */ 732 RK_MUXROUTE_SAME(4, RK_PC0, 2, 0xe21c, BIT(16 + 10) | BIT(16 + 11) | BIT(10)), /* uart2dbgb_rx */ 733 RK_MUXROUTE_SAME(4, RK_PC3, 1, 0xe21c, BIT(16 + 10) | BIT(16 + 11) | BIT(11)), /* uart2dbgc_rx */ 734 RK_MUXROUTE_SAME(2, RK_PD2, 2, 0xe21c, BIT(16 + 14)), /* pcie_clkreqn */ 735 RK_MUXROUTE_SAME(4, RK_PD0, 1, 0xe21c, BIT(16 + 14) | BIT(14)), /* pcie_clkreqnb */ 736 }; 737 738 static struct rockchip_mux_route_data rk3568_mux_route_data[] = { 739 RK_MUXROUTE_PMU(0, RK_PB7, 1, 0x0110, WRITE_MASK_VAL(1, 0, 0)), /* PWM0 IO mux M0 */ 740 RK_MUXROUTE_PMU(0, RK_PC7, 2, 0x0110, WRITE_MASK_VAL(1, 0, 1)), /* PWM0 IO mux M1 */ 741 RK_MUXROUTE_PMU(0, RK_PC0, 1, 0x0110, WRITE_MASK_VAL(3, 2, 0)), /* PWM1 IO mux M0 */ 742 RK_MUXROUTE_PMU(0, RK_PB5, 4, 0x0110, WRITE_MASK_VAL(3, 2, 1)), /* PWM1 IO mux M1 */ 743 RK_MUXROUTE_PMU(0, RK_PC1, 1, 0x0110, WRITE_MASK_VAL(5, 4, 0)), /* PWM2 IO mux M0 */ 744 RK_MUXROUTE_PMU(0, RK_PB6, 4, 0x0110, WRITE_MASK_VAL(5, 4, 1)), /* PWM2 IO mux M1 */ 745 RK_MUXROUTE_PMU(0, RK_PB3, 2, 0x0300, WRITE_MASK_VAL(0, 0, 0)), /* CAN0 IO mux M0 */ 746 RK_MUXROUTE_GRF(2, RK_PA1, 4, 0x0300, WRITE_MASK_VAL(0, 0, 1)), /* CAN0 IO mux M1 */ 747 RK_MUXROUTE_GRF(1, RK_PA1, 3, 0x0300, WRITE_MASK_VAL(2, 2, 0)), /* CAN1 IO mux M0 */ 748 RK_MUXROUTE_GRF(4, RK_PC3, 3, 0x0300, WRITE_MASK_VAL(2, 2, 1)), /* CAN1 IO mux M1 */ 749 RK_MUXROUTE_GRF(4, RK_PB5, 3, 0x0300, WRITE_MASK_VAL(4, 4, 0)), /* CAN2 IO mux M0 */ 750 RK_MUXROUTE_GRF(2, RK_PB2, 4, 0x0300, WRITE_MASK_VAL(4, 4, 1)), /* CAN2 IO mux M1 */ 751 RK_MUXROUTE_GRF(4, RK_PC4, 1, 0x0300, WRITE_MASK_VAL(6, 6, 0)), /* HPDIN IO mux M0 */ 752 RK_MUXROUTE_PMU(0, RK_PC2, 2, 0x0300, WRITE_MASK_VAL(6, 6, 1)), /* HPDIN IO mux M1 */ 753 RK_MUXROUTE_GRF(3, RK_PB1, 3, 0x0300, WRITE_MASK_VAL(8, 8, 0)), /* GMAC1 IO mux M0 */ 754 RK_MUXROUTE_GRF(4, RK_PA7, 3, 0x0300, WRITE_MASK_VAL(8, 8, 1)), /* GMAC1 IO mux M1 */ 755 RK_MUXROUTE_GRF(4, RK_PD1, 1, 0x0300, WRITE_MASK_VAL(10, 10, 0)), /* HDMITX IO mux M0 */ 756 RK_MUXROUTE_PMU(0, RK_PC7, 1, 0x0300, WRITE_MASK_VAL(10, 10, 1)), /* HDMITX IO mux M1 */ 757 RK_MUXROUTE_PMU(0, RK_PB6, 1, 0x0300, WRITE_MASK_VAL(14, 14, 0)), /* I2C2 IO mux M0 */ 758 RK_MUXROUTE_GRF(4, RK_PB4, 1, 0x0300, WRITE_MASK_VAL(14, 14, 1)), /* I2C2 IO mux M1 */ 759 RK_MUXROUTE_GRF(1, RK_PA0, 1, 0x0304, WRITE_MASK_VAL(0, 0, 0)), /* I2C3 IO mux M0 */ 760 RK_MUXROUTE_GRF(3, RK_PB6, 4, 0x0304, WRITE_MASK_VAL(0, 0, 1)), /* I2C3 IO mux M1 */ 761 RK_MUXROUTE_GRF(4, RK_PB2, 1, 0x0304, WRITE_MASK_VAL(2, 2, 0)), /* I2C4 IO mux M0 */ 762 RK_MUXROUTE_GRF(2, RK_PB1, 2, 0x0304, WRITE_MASK_VAL(2, 2, 1)), /* I2C4 IO mux M1 */ 763 RK_MUXROUTE_GRF(3, RK_PB4, 4, 0x0304, WRITE_MASK_VAL(4, 4, 0)), /* I2C5 IO mux M0 */ 764 RK_MUXROUTE_GRF(4, RK_PD0, 2, 0x0304, WRITE_MASK_VAL(4, 4, 1)), /* I2C5 IO mux M1 */ 765 RK_MUXROUTE_GRF(3, RK_PB1, 5, 0x0304, WRITE_MASK_VAL(14, 14, 0)), /* PWM8 IO mux M0 */ 766 RK_MUXROUTE_GRF(1, RK_PD5, 4, 0x0304, WRITE_MASK_VAL(14, 14, 1)), /* PWM8 IO mux M1 */ 767 RK_MUXROUTE_GRF(3, RK_PB2, 5, 0x0308, WRITE_MASK_VAL(0, 0, 0)), /* PWM9 IO mux M0 */ 768 RK_MUXROUTE_GRF(1, RK_PD6, 4, 0x0308, WRITE_MASK_VAL(0, 0, 1)), /* PWM9 IO mux M1 */ 769 RK_MUXROUTE_GRF(3, RK_PB5, 5, 0x0308, WRITE_MASK_VAL(2, 2, 0)), /* PWM10 IO mux M0 */ 770 RK_MUXROUTE_GRF(2, RK_PA1, 2, 0x0308, WRITE_MASK_VAL(2, 2, 1)), /* PWM10 IO mux M1 */ 771 RK_MUXROUTE_GRF(3, RK_PB6, 5, 0x0308, WRITE_MASK_VAL(4, 4, 0)), /* PWM11 IO mux M0 */ 772 RK_MUXROUTE_GRF(4, RK_PC0, 3, 0x0308, WRITE_MASK_VAL(4, 4, 1)), /* PWM11 IO mux M1 */ 773 RK_MUXROUTE_GRF(3, RK_PB7, 2, 0x0308, WRITE_MASK_VAL(6, 6, 0)), /* PWM12 IO mux M0 */ 774 RK_MUXROUTE_GRF(4, RK_PC5, 1, 0x0308, WRITE_MASK_VAL(6, 6, 1)), /* PWM12 IO mux M1 */ 775 RK_MUXROUTE_GRF(3, RK_PC0, 2, 0x0308, WRITE_MASK_VAL(8, 8, 0)), /* PWM13 IO mux M0 */ 776 RK_MUXROUTE_GRF(4, RK_PC6, 1, 0x0308, WRITE_MASK_VAL(8, 8, 1)), /* PWM13 IO mux M1 */ 777 RK_MUXROUTE_GRF(3, RK_PC4, 1, 0x0308, WRITE_MASK_VAL(10, 10, 0)), /* PWM14 IO mux M0 */ 778 RK_MUXROUTE_GRF(4, RK_PC2, 1, 0x0308, WRITE_MASK_VAL(10, 10, 1)), /* PWM14 IO mux M1 */ 779 RK_MUXROUTE_GRF(3, RK_PC5, 1, 0x0308, WRITE_MASK_VAL(12, 12, 0)), /* PWM15 IO mux M0 */ 780 RK_MUXROUTE_GRF(4, RK_PC3, 1, 0x0308, WRITE_MASK_VAL(12, 12, 1)), /* PWM15 IO mux M1 */ 781 RK_MUXROUTE_GRF(3, RK_PD2, 3, 0x0308, WRITE_MASK_VAL(14, 14, 0)), /* SDMMC2 IO mux M0 */ 782 RK_MUXROUTE_GRF(3, RK_PA5, 5, 0x0308, WRITE_MASK_VAL(14, 14, 1)), /* SDMMC2 IO mux M1 */ 783 RK_MUXROUTE_PMU(0, RK_PB5, 2, 0x030c, WRITE_MASK_VAL(0, 0, 0)), /* SPI0 IO mux M0 */ 784 RK_MUXROUTE_GRF(2, RK_PD3, 3, 0x030c, WRITE_MASK_VAL(0, 0, 1)), /* SPI0 IO mux M1 */ 785 RK_MUXROUTE_GRF(2, RK_PB5, 3, 0x030c, WRITE_MASK_VAL(2, 2, 0)), /* SPI1 IO mux M0 */ 786 RK_MUXROUTE_GRF(3, RK_PC3, 3, 0x030c, WRITE_MASK_VAL(2, 2, 1)), /* SPI1 IO mux M1 */ 787 RK_MUXROUTE_GRF(2, RK_PC1, 4, 0x030c, WRITE_MASK_VAL(4, 4, 0)), /* SPI2 IO mux M0 */ 788 RK_MUXROUTE_GRF(3, RK_PA0, 3, 0x030c, WRITE_MASK_VAL(4, 4, 1)), /* SPI2 IO mux M1 */ 789 RK_MUXROUTE_GRF(4, RK_PB3, 4, 0x030c, WRITE_MASK_VAL(6, 6, 0)), /* SPI3 IO mux M0 */ 790 RK_MUXROUTE_GRF(4, RK_PC2, 2, 0x030c, WRITE_MASK_VAL(6, 6, 1)), /* SPI3 IO mux M1 */ 791 RK_MUXROUTE_GRF(2, RK_PB4, 2, 0x030c, WRITE_MASK_VAL(8, 8, 0)), /* UART1 IO mux M0 */ 792 RK_MUXROUTE_PMU(0, RK_PD1, 1, 0x030c, WRITE_MASK_VAL(8, 8, 1)), /* UART1 IO mux M1 */ 793 RK_MUXROUTE_PMU(0, RK_PD1, 1, 0x030c, WRITE_MASK_VAL(10, 10, 0)), /* UART2 IO mux M0 */ 794 RK_MUXROUTE_GRF(1, RK_PD5, 2, 0x030c, WRITE_MASK_VAL(10, 10, 1)), /* UART2 IO mux M1 */ 795 RK_MUXROUTE_GRF(1, RK_PA1, 2, 0x030c, WRITE_MASK_VAL(12, 12, 0)), /* UART3 IO mux M0 */ 796 RK_MUXROUTE_GRF(3, RK_PB7, 4, 0x030c, WRITE_MASK_VAL(12, 12, 1)), /* UART3 IO mux M1 */ 797 RK_MUXROUTE_GRF(1, RK_PA6, 2, 0x030c, WRITE_MASK_VAL(14, 14, 0)), /* UART4 IO mux M0 */ 798 RK_MUXROUTE_GRF(3, RK_PB2, 4, 0x030c, WRITE_MASK_VAL(14, 14, 1)), /* UART4 IO mux M1 */ 799 RK_MUXROUTE_GRF(2, RK_PA2, 3, 0x0310, WRITE_MASK_VAL(0, 0, 0)), /* UART5 IO mux M0 */ 800 RK_MUXROUTE_GRF(3, RK_PC2, 4, 0x0310, WRITE_MASK_VAL(0, 0, 1)), /* UART5 IO mux M1 */ 801 RK_MUXROUTE_GRF(2, RK_PA4, 3, 0x0310, WRITE_MASK_VAL(2, 2, 0)), /* UART6 IO mux M0 */ 802 RK_MUXROUTE_GRF(1, RK_PD5, 3, 0x0310, WRITE_MASK_VAL(2, 2, 1)), /* UART6 IO mux M1 */ 803 RK_MUXROUTE_GRF(2, RK_PA6, 3, 0x0310, WRITE_MASK_VAL(5, 4, 0)), /* UART7 IO mux M0 */ 804 RK_MUXROUTE_GRF(3, RK_PC4, 4, 0x0310, WRITE_MASK_VAL(5, 4, 1)), /* UART7 IO mux M1 */ 805 RK_MUXROUTE_GRF(4, RK_PA2, 4, 0x0310, WRITE_MASK_VAL(5, 4, 2)), /* UART7 IO mux M2 */ 806 RK_MUXROUTE_GRF(2, RK_PC5, 3, 0x0310, WRITE_MASK_VAL(6, 6, 0)), /* UART8 IO mux M0 */ 807 RK_MUXROUTE_GRF(2, RK_PD7, 4, 0x0310, WRITE_MASK_VAL(6, 6, 1)), /* UART8 IO mux M1 */ 808 RK_MUXROUTE_GRF(2, RK_PB0, 3, 0x0310, WRITE_MASK_VAL(9, 8, 0)), /* UART9 IO mux M0 */ 809 RK_MUXROUTE_GRF(4, RK_PC5, 4, 0x0310, WRITE_MASK_VAL(9, 8, 1)), /* UART9 IO mux M1 */ 810 RK_MUXROUTE_GRF(4, RK_PA4, 4, 0x0310, WRITE_MASK_VAL(9, 8, 2)), /* UART9 IO mux M2 */ 811 RK_MUXROUTE_GRF(1, RK_PA2, 1, 0x0310, WRITE_MASK_VAL(11, 10, 0)), /* I2S1 IO mux M0 */ 812 RK_MUXROUTE_GRF(3, RK_PC6, 4, 0x0310, WRITE_MASK_VAL(11, 10, 1)), /* I2S1 IO mux M1 */ 813 RK_MUXROUTE_GRF(2, RK_PD0, 5, 0x0310, WRITE_MASK_VAL(11, 10, 2)), /* I2S1 IO mux M2 */ 814 RK_MUXROUTE_GRF(2, RK_PC1, 1, 0x0310, WRITE_MASK_VAL(12, 12, 0)), /* I2S2 IO mux M0 */ 815 RK_MUXROUTE_GRF(4, RK_PB6, 5, 0x0310, WRITE_MASK_VAL(12, 12, 1)), /* I2S2 IO mux M1 */ 816 RK_MUXROUTE_GRF(3, RK_PA2, 4, 0x0310, WRITE_MASK_VAL(14, 14, 0)), /* I2S3 IO mux M0 */ 817 RK_MUXROUTE_GRF(4, RK_PC2, 5, 0x0310, WRITE_MASK_VAL(14, 14, 1)), /* I2S3 IO mux M1 */ 818 RK_MUXROUTE_GRF(1, RK_PA4, 3, 0x0314, WRITE_MASK_VAL(1, 0, 0)), /* PDM IO mux M0 */ 819 RK_MUXROUTE_GRF(1, RK_PA6, 3, 0x0314, WRITE_MASK_VAL(1, 0, 0)), /* PDM IO mux M0 */ 820 RK_MUXROUTE_GRF(3, RK_PD6, 5, 0x0314, WRITE_MASK_VAL(1, 0, 1)), /* PDM IO mux M1 */ 821 RK_MUXROUTE_GRF(4, RK_PA0, 4, 0x0314, WRITE_MASK_VAL(1, 0, 1)), /* PDM IO mux M1 */ 822 RK_MUXROUTE_GRF(3, RK_PC4, 5, 0x0314, WRITE_MASK_VAL(1, 0, 2)), /* PDM IO mux M2 */ 823 RK_MUXROUTE_PMU(0, RK_PA5, 3, 0x0314, WRITE_MASK_VAL(3, 2, 0)), /* PCIE20 IO mux M0 */ 824 RK_MUXROUTE_GRF(2, RK_PD0, 4, 0x0314, WRITE_MASK_VAL(3, 2, 1)), /* PCIE20 IO mux M1 */ 825 RK_MUXROUTE_GRF(1, RK_PB0, 4, 0x0314, WRITE_MASK_VAL(3, 2, 2)), /* PCIE20 IO mux M2 */ 826 RK_MUXROUTE_PMU(0, RK_PA4, 3, 0x0314, WRITE_MASK_VAL(5, 4, 0)), /* PCIE30X1 IO mux M0 */ 827 RK_MUXROUTE_GRF(2, RK_PD2, 4, 0x0314, WRITE_MASK_VAL(5, 4, 1)), /* PCIE30X1 IO mux M1 */ 828 RK_MUXROUTE_GRF(1, RK_PA5, 4, 0x0314, WRITE_MASK_VAL(5, 4, 2)), /* PCIE30X1 IO mux M2 */ 829 RK_MUXROUTE_PMU(0, RK_PA6, 2, 0x0314, WRITE_MASK_VAL(7, 6, 0)), /* PCIE30X2 IO mux M0 */ 830 RK_MUXROUTE_GRF(2, RK_PD4, 4, 0x0314, WRITE_MASK_VAL(7, 6, 1)), /* PCIE30X2 IO mux M1 */ 831 RK_MUXROUTE_GRF(4, RK_PC2, 4, 0x0314, WRITE_MASK_VAL(7, 6, 2)), /* PCIE30X2 IO mux M2 */ 832 }; 833 834 static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin, 835 int mux, u32 *loc, u32 *reg, u32 *value) 836 { 837 struct rockchip_pinctrl *info = bank->drvdata; 838 struct rockchip_pin_ctrl *ctrl = info->ctrl; 839 struct rockchip_mux_route_data *data; 840 int i; 841 842 for (i = 0; i < ctrl->niomux_routes; i++) { 843 data = &ctrl->iomux_routes[i]; 844 if ((data->bank_num == bank->bank_num) && 845 (data->pin == pin) && (data->func == mux)) 846 break; 847 } 848 849 if (i >= ctrl->niomux_routes) 850 return false; 851 852 *loc = data->route_location; 853 *reg = data->route_offset; 854 *value = data->route_val; 855 856 return true; 857 } 858 859 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) 860 { 861 struct rockchip_pinctrl *info = bank->drvdata; 862 struct rockchip_pin_ctrl *ctrl = info->ctrl; 863 int iomux_num = (pin / 8); 864 struct regmap *regmap; 865 unsigned int val; 866 int reg, ret, mask, mux_type; 867 u8 bit; 868 869 if (iomux_num > 3) 870 return -EINVAL; 871 872 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { 873 dev_err(info->dev, "pin %d is unrouted\n", pin); 874 return -EINVAL; 875 } 876 877 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) 878 return RK_FUNC_GPIO; 879 880 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) 881 ? info->regmap_pmu : info->regmap_base; 882 883 /* get basic quadrupel of mux registers and the correct reg inside */ 884 mux_type = bank->iomux[iomux_num].type; 885 reg = bank->iomux[iomux_num].offset; 886 if (mux_type & IOMUX_WIDTH_4BIT) { 887 if ((pin % 8) >= 4) 888 reg += 0x4; 889 bit = (pin % 4) * 4; 890 mask = 0xf; 891 } else if (mux_type & IOMUX_WIDTH_3BIT) { 892 if ((pin % 8) >= 5) 893 reg += 0x4; 894 bit = (pin % 8 % 5) * 3; 895 mask = 0x7; 896 } else { 897 bit = (pin % 8) * 2; 898 mask = 0x3; 899 } 900 901 if (bank->recalced_mask & BIT(pin)) 902 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); 903 904 if (ctrl->type == RK3588) { 905 if (bank->bank_num == 0) { 906 if ((pin >= RK_PB4) && (pin <= RK_PD7)) { 907 u32 reg0 = 0; 908 909 reg0 = reg + 0x4000 - 0xC; /* PMU2_IOC_BASE */ 910 ret = regmap_read(regmap, reg0, &val); 911 if (ret) 912 return ret; 913 914 if (!(val & BIT(8))) 915 return ((val >> bit) & mask); 916 917 reg = reg + 0x8000; /* BUS_IOC_BASE */ 918 regmap = info->regmap_base; 919 } 920 } else if (bank->bank_num > 0) { 921 reg += 0x8000; /* BUS_IOC_BASE */ 922 } 923 } 924 925 ret = regmap_read(regmap, reg, &val); 926 if (ret) 927 return ret; 928 929 return ((val >> bit) & mask); 930 } 931 932 static int rockchip_verify_mux(struct rockchip_pin_bank *bank, 933 int pin, int mux) 934 { 935 struct rockchip_pinctrl *info = bank->drvdata; 936 struct device *dev = info->dev; 937 int iomux_num = (pin / 8); 938 939 if (iomux_num > 3) 940 return -EINVAL; 941 942 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { 943 dev_err(dev, "pin %d is unrouted\n", pin); 944 return -EINVAL; 945 } 946 947 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) { 948 if (mux != RK_FUNC_GPIO) { 949 dev_err(dev, "pin %d only supports a gpio mux\n", pin); 950 return -ENOTSUPP; 951 } 952 } 953 954 return 0; 955 } 956 957 /* 958 * Set a new mux function for a pin. 959 * 960 * The register is divided into the upper and lower 16 bit. When changing 961 * a value, the previous register value is not read and changed. Instead 962 * it seems the changed bits are marked in the upper 16 bit, while the 963 * changed value gets set in the same offset in the lower 16 bit. 964 * All pin settings seem to be 2 bit wide in both the upper and lower 965 * parts. 966 * @bank: pin bank to change 967 * @pin: pin to change 968 * @mux: new mux function to set 969 */ 970 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) 971 { 972 struct rockchip_pinctrl *info = bank->drvdata; 973 struct rockchip_pin_ctrl *ctrl = info->ctrl; 974 struct device *dev = info->dev; 975 int iomux_num = (pin / 8); 976 struct regmap *regmap; 977 int reg, ret, mask, mux_type; 978 u8 bit; 979 u32 data, rmask, route_location, route_reg, route_val; 980 981 ret = rockchip_verify_mux(bank, pin, mux); 982 if (ret < 0) 983 return ret; 984 985 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) 986 return 0; 987 988 dev_dbg(dev, "setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux); 989 990 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) 991 ? info->regmap_pmu : info->regmap_base; 992 993 /* get basic quadrupel of mux registers and the correct reg inside */ 994 mux_type = bank->iomux[iomux_num].type; 995 reg = bank->iomux[iomux_num].offset; 996 if (mux_type & IOMUX_WIDTH_4BIT) { 997 if ((pin % 8) >= 4) 998 reg += 0x4; 999 bit = (pin % 4) * 4; 1000 mask = 0xf; 1001 } else if (mux_type & IOMUX_WIDTH_3BIT) { 1002 if ((pin % 8) >= 5) 1003 reg += 0x4; 1004 bit = (pin % 8 % 5) * 3; 1005 mask = 0x7; 1006 } else { 1007 bit = (pin % 8) * 2; 1008 mask = 0x3; 1009 } 1010 1011 if (bank->recalced_mask & BIT(pin)) 1012 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); 1013 1014 if (ctrl->type == RK3588) { 1015 if (bank->bank_num == 0) { 1016 if ((pin >= RK_PB4) && (pin <= RK_PD7)) { 1017 if (mux < 8) { 1018 reg += 0x4000 - 0xC; /* PMU2_IOC_BASE */ 1019 data = (mask << (bit + 16)); 1020 rmask = data | (data >> 16); 1021 data |= (mux & mask) << bit; 1022 ret = regmap_update_bits(regmap, reg, rmask, data); 1023 } else { 1024 u32 reg0 = 0; 1025 1026 reg0 = reg + 0x4000 - 0xC; /* PMU2_IOC_BASE */ 1027 data = (mask << (bit + 16)); 1028 rmask = data | (data >> 16); 1029 data |= 8 << bit; 1030 ret = regmap_update_bits(regmap, reg0, rmask, data); 1031 1032 reg0 = reg + 0x8000; /* BUS_IOC_BASE */ 1033 data = (mask << (bit + 16)); 1034 rmask = data | (data >> 16); 1035 data |= mux << bit; 1036 regmap = info->regmap_base; 1037 ret |= regmap_update_bits(regmap, reg0, rmask, data); 1038 } 1039 } else { 1040 data = (mask << (bit + 16)); 1041 rmask = data | (data >> 16); 1042 data |= (mux & mask) << bit; 1043 ret = regmap_update_bits(regmap, reg, rmask, data); 1044 } 1045 return ret; 1046 } else if (bank->bank_num > 0) { 1047 reg += 0x8000; /* BUS_IOC_BASE */ 1048 } 1049 } 1050 1051 if (mux > mask) 1052 return -EINVAL; 1053 1054 if (bank->route_mask & BIT(pin)) { 1055 if (rockchip_get_mux_route(bank, pin, mux, &route_location, 1056 &route_reg, &route_val)) { 1057 struct regmap *route_regmap = regmap; 1058 1059 /* handle special locations */ 1060 switch (route_location) { 1061 case ROCKCHIP_ROUTE_PMU: 1062 route_regmap = info->regmap_pmu; 1063 break; 1064 case ROCKCHIP_ROUTE_GRF: 1065 route_regmap = info->regmap_base; 1066 break; 1067 } 1068 1069 ret = regmap_write(route_regmap, route_reg, route_val); 1070 if (ret) 1071 return ret; 1072 } 1073 } 1074 1075 data = (mask << (bit + 16)); 1076 rmask = data | (data >> 16); 1077 data |= (mux & mask) << bit; 1078 ret = regmap_update_bits(regmap, reg, rmask, data); 1079 1080 return ret; 1081 } 1082 1083 #define PX30_PULL_PMU_OFFSET 0x10 1084 #define PX30_PULL_GRF_OFFSET 0x60 1085 #define PX30_PULL_BITS_PER_PIN 2 1086 #define PX30_PULL_PINS_PER_REG 8 1087 #define PX30_PULL_BANK_STRIDE 16 1088 1089 static int px30_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1090 int pin_num, struct regmap **regmap, 1091 int *reg, u8 *bit) 1092 { 1093 struct rockchip_pinctrl *info = bank->drvdata; 1094 1095 /* The first 32 pins of the first bank are located in PMU */ 1096 if (bank->bank_num == 0) { 1097 *regmap = info->regmap_pmu; 1098 *reg = PX30_PULL_PMU_OFFSET; 1099 } else { 1100 *regmap = info->regmap_base; 1101 *reg = PX30_PULL_GRF_OFFSET; 1102 1103 /* correct the offset, as we're starting with the 2nd bank */ 1104 *reg -= 0x10; 1105 *reg += bank->bank_num * PX30_PULL_BANK_STRIDE; 1106 } 1107 1108 *reg += ((pin_num / PX30_PULL_PINS_PER_REG) * 4); 1109 *bit = (pin_num % PX30_PULL_PINS_PER_REG); 1110 *bit *= PX30_PULL_BITS_PER_PIN; 1111 1112 return 0; 1113 } 1114 1115 #define PX30_DRV_PMU_OFFSET 0x20 1116 #define PX30_DRV_GRF_OFFSET 0xf0 1117 #define PX30_DRV_BITS_PER_PIN 2 1118 #define PX30_DRV_PINS_PER_REG 8 1119 #define PX30_DRV_BANK_STRIDE 16 1120 1121 static int px30_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1122 int pin_num, struct regmap **regmap, 1123 int *reg, u8 *bit) 1124 { 1125 struct rockchip_pinctrl *info = bank->drvdata; 1126 1127 /* The first 32 pins of the first bank are located in PMU */ 1128 if (bank->bank_num == 0) { 1129 *regmap = info->regmap_pmu; 1130 *reg = PX30_DRV_PMU_OFFSET; 1131 } else { 1132 *regmap = info->regmap_base; 1133 *reg = PX30_DRV_GRF_OFFSET; 1134 1135 /* correct the offset, as we're starting with the 2nd bank */ 1136 *reg -= 0x10; 1137 *reg += bank->bank_num * PX30_DRV_BANK_STRIDE; 1138 } 1139 1140 *reg += ((pin_num / PX30_DRV_PINS_PER_REG) * 4); 1141 *bit = (pin_num % PX30_DRV_PINS_PER_REG); 1142 *bit *= PX30_DRV_BITS_PER_PIN; 1143 1144 return 0; 1145 } 1146 1147 #define PX30_SCHMITT_PMU_OFFSET 0x38 1148 #define PX30_SCHMITT_GRF_OFFSET 0xc0 1149 #define PX30_SCHMITT_PINS_PER_PMU_REG 16 1150 #define PX30_SCHMITT_BANK_STRIDE 16 1151 #define PX30_SCHMITT_PINS_PER_GRF_REG 8 1152 1153 static int px30_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1154 int pin_num, 1155 struct regmap **regmap, 1156 int *reg, u8 *bit) 1157 { 1158 struct rockchip_pinctrl *info = bank->drvdata; 1159 int pins_per_reg; 1160 1161 if (bank->bank_num == 0) { 1162 *regmap = info->regmap_pmu; 1163 *reg = PX30_SCHMITT_PMU_OFFSET; 1164 pins_per_reg = PX30_SCHMITT_PINS_PER_PMU_REG; 1165 } else { 1166 *regmap = info->regmap_base; 1167 *reg = PX30_SCHMITT_GRF_OFFSET; 1168 pins_per_reg = PX30_SCHMITT_PINS_PER_GRF_REG; 1169 *reg += (bank->bank_num - 1) * PX30_SCHMITT_BANK_STRIDE; 1170 } 1171 1172 *reg += ((pin_num / pins_per_reg) * 4); 1173 *bit = pin_num % pins_per_reg; 1174 1175 return 0; 1176 } 1177 1178 #define RV1108_PULL_PMU_OFFSET 0x10 1179 #define RV1108_PULL_OFFSET 0x110 1180 #define RV1108_PULL_PINS_PER_REG 8 1181 #define RV1108_PULL_BITS_PER_PIN 2 1182 #define RV1108_PULL_BANK_STRIDE 16 1183 1184 static int rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1185 int pin_num, struct regmap **regmap, 1186 int *reg, u8 *bit) 1187 { 1188 struct rockchip_pinctrl *info = bank->drvdata; 1189 1190 /* The first 24 pins of the first bank are located in PMU */ 1191 if (bank->bank_num == 0) { 1192 *regmap = info->regmap_pmu; 1193 *reg = RV1108_PULL_PMU_OFFSET; 1194 } else { 1195 *reg = RV1108_PULL_OFFSET; 1196 *regmap = info->regmap_base; 1197 /* correct the offset, as we're starting with the 2nd bank */ 1198 *reg -= 0x10; 1199 *reg += bank->bank_num * RV1108_PULL_BANK_STRIDE; 1200 } 1201 1202 *reg += ((pin_num / RV1108_PULL_PINS_PER_REG) * 4); 1203 *bit = (pin_num % RV1108_PULL_PINS_PER_REG); 1204 *bit *= RV1108_PULL_BITS_PER_PIN; 1205 1206 return 0; 1207 } 1208 1209 #define RV1108_DRV_PMU_OFFSET 0x20 1210 #define RV1108_DRV_GRF_OFFSET 0x210 1211 #define RV1108_DRV_BITS_PER_PIN 2 1212 #define RV1108_DRV_PINS_PER_REG 8 1213 #define RV1108_DRV_BANK_STRIDE 16 1214 1215 static int rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1216 int pin_num, struct regmap **regmap, 1217 int *reg, u8 *bit) 1218 { 1219 struct rockchip_pinctrl *info = bank->drvdata; 1220 1221 /* The first 24 pins of the first bank are located in PMU */ 1222 if (bank->bank_num == 0) { 1223 *regmap = info->regmap_pmu; 1224 *reg = RV1108_DRV_PMU_OFFSET; 1225 } else { 1226 *regmap = info->regmap_base; 1227 *reg = RV1108_DRV_GRF_OFFSET; 1228 1229 /* correct the offset, as we're starting with the 2nd bank */ 1230 *reg -= 0x10; 1231 *reg += bank->bank_num * RV1108_DRV_BANK_STRIDE; 1232 } 1233 1234 *reg += ((pin_num / RV1108_DRV_PINS_PER_REG) * 4); 1235 *bit = pin_num % RV1108_DRV_PINS_PER_REG; 1236 *bit *= RV1108_DRV_BITS_PER_PIN; 1237 1238 return 0; 1239 } 1240 1241 #define RV1108_SCHMITT_PMU_OFFSET 0x30 1242 #define RV1108_SCHMITT_GRF_OFFSET 0x388 1243 #define RV1108_SCHMITT_BANK_STRIDE 8 1244 #define RV1108_SCHMITT_PINS_PER_GRF_REG 16 1245 #define RV1108_SCHMITT_PINS_PER_PMU_REG 8 1246 1247 static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1248 int pin_num, 1249 struct regmap **regmap, 1250 int *reg, u8 *bit) 1251 { 1252 struct rockchip_pinctrl *info = bank->drvdata; 1253 int pins_per_reg; 1254 1255 if (bank->bank_num == 0) { 1256 *regmap = info->regmap_pmu; 1257 *reg = RV1108_SCHMITT_PMU_OFFSET; 1258 pins_per_reg = RV1108_SCHMITT_PINS_PER_PMU_REG; 1259 } else { 1260 *regmap = info->regmap_base; 1261 *reg = RV1108_SCHMITT_GRF_OFFSET; 1262 pins_per_reg = RV1108_SCHMITT_PINS_PER_GRF_REG; 1263 *reg += (bank->bank_num - 1) * RV1108_SCHMITT_BANK_STRIDE; 1264 } 1265 *reg += ((pin_num / pins_per_reg) * 4); 1266 *bit = pin_num % pins_per_reg; 1267 1268 return 0; 1269 } 1270 1271 #define RK3308_SCHMITT_PINS_PER_REG 8 1272 #define RK3308_SCHMITT_BANK_STRIDE 16 1273 #define RK3308_SCHMITT_GRF_OFFSET 0x1a0 1274 1275 static int rk3308_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1276 int pin_num, struct regmap **regmap, 1277 int *reg, u8 *bit) 1278 { 1279 struct rockchip_pinctrl *info = bank->drvdata; 1280 1281 *regmap = info->regmap_base; 1282 *reg = RK3308_SCHMITT_GRF_OFFSET; 1283 1284 *reg += bank->bank_num * RK3308_SCHMITT_BANK_STRIDE; 1285 *reg += ((pin_num / RK3308_SCHMITT_PINS_PER_REG) * 4); 1286 *bit = pin_num % RK3308_SCHMITT_PINS_PER_REG; 1287 1288 return 0; 1289 } 1290 1291 #define RK2928_PULL_OFFSET 0x118 1292 #define RK2928_PULL_PINS_PER_REG 16 1293 #define RK2928_PULL_BANK_STRIDE 8 1294 1295 static int rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1296 int pin_num, struct regmap **regmap, 1297 int *reg, u8 *bit) 1298 { 1299 struct rockchip_pinctrl *info = bank->drvdata; 1300 1301 *regmap = info->regmap_base; 1302 *reg = RK2928_PULL_OFFSET; 1303 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; 1304 *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4; 1305 1306 *bit = pin_num % RK2928_PULL_PINS_PER_REG; 1307 1308 return 0; 1309 }; 1310 1311 #define RK3128_PULL_OFFSET 0x118 1312 1313 static int rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1314 int pin_num, struct regmap **regmap, 1315 int *reg, u8 *bit) 1316 { 1317 struct rockchip_pinctrl *info = bank->drvdata; 1318 1319 *regmap = info->regmap_base; 1320 *reg = RK3128_PULL_OFFSET; 1321 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; 1322 *reg += ((pin_num / RK2928_PULL_PINS_PER_REG) * 4); 1323 1324 *bit = pin_num % RK2928_PULL_PINS_PER_REG; 1325 1326 return 0; 1327 } 1328 1329 #define RK3188_PULL_OFFSET 0x164 1330 #define RK3188_PULL_BITS_PER_PIN 2 1331 #define RK3188_PULL_PINS_PER_REG 8 1332 #define RK3188_PULL_BANK_STRIDE 16 1333 #define RK3188_PULL_PMU_OFFSET 0x64 1334 1335 static int rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1336 int pin_num, struct regmap **regmap, 1337 int *reg, u8 *bit) 1338 { 1339 struct rockchip_pinctrl *info = bank->drvdata; 1340 1341 /* The first 12 pins of the first bank are located elsewhere */ 1342 if (bank->bank_num == 0 && pin_num < 12) { 1343 *regmap = info->regmap_pmu ? info->regmap_pmu 1344 : bank->regmap_pull; 1345 *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0; 1346 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1347 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 1348 *bit *= RK3188_PULL_BITS_PER_PIN; 1349 } else { 1350 *regmap = info->regmap_pull ? info->regmap_pull 1351 : info->regmap_base; 1352 *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET; 1353 1354 /* correct the offset, as it is the 2nd pull register */ 1355 *reg -= 4; 1356 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1357 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1358 1359 /* 1360 * The bits in these registers have an inverse ordering 1361 * with the lowest pin being in bits 15:14 and the highest 1362 * pin in bits 1:0 1363 */ 1364 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG); 1365 *bit *= RK3188_PULL_BITS_PER_PIN; 1366 } 1367 1368 return 0; 1369 } 1370 1371 #define RK3288_PULL_OFFSET 0x140 1372 static int rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1373 int pin_num, struct regmap **regmap, 1374 int *reg, u8 *bit) 1375 { 1376 struct rockchip_pinctrl *info = bank->drvdata; 1377 1378 /* The first 24 pins of the first bank are located in PMU */ 1379 if (bank->bank_num == 0) { 1380 *regmap = info->regmap_pmu; 1381 *reg = RK3188_PULL_PMU_OFFSET; 1382 1383 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1384 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 1385 *bit *= RK3188_PULL_BITS_PER_PIN; 1386 } else { 1387 *regmap = info->regmap_base; 1388 *reg = RK3288_PULL_OFFSET; 1389 1390 /* correct the offset, as we're starting with the 2nd bank */ 1391 *reg -= 0x10; 1392 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1393 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1394 1395 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1396 *bit *= RK3188_PULL_BITS_PER_PIN; 1397 } 1398 1399 return 0; 1400 } 1401 1402 #define RK3288_DRV_PMU_OFFSET 0x70 1403 #define RK3288_DRV_GRF_OFFSET 0x1c0 1404 #define RK3288_DRV_BITS_PER_PIN 2 1405 #define RK3288_DRV_PINS_PER_REG 8 1406 #define RK3288_DRV_BANK_STRIDE 16 1407 1408 static int rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1409 int pin_num, struct regmap **regmap, 1410 int *reg, u8 *bit) 1411 { 1412 struct rockchip_pinctrl *info = bank->drvdata; 1413 1414 /* The first 24 pins of the first bank are located in PMU */ 1415 if (bank->bank_num == 0) { 1416 *regmap = info->regmap_pmu; 1417 *reg = RK3288_DRV_PMU_OFFSET; 1418 1419 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1420 *bit = pin_num % RK3288_DRV_PINS_PER_REG; 1421 *bit *= RK3288_DRV_BITS_PER_PIN; 1422 } else { 1423 *regmap = info->regmap_base; 1424 *reg = RK3288_DRV_GRF_OFFSET; 1425 1426 /* correct the offset, as we're starting with the 2nd bank */ 1427 *reg -= 0x10; 1428 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 1429 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1430 1431 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 1432 *bit *= RK3288_DRV_BITS_PER_PIN; 1433 } 1434 1435 return 0; 1436 } 1437 1438 #define RK3228_PULL_OFFSET 0x100 1439 1440 static int rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1441 int pin_num, struct regmap **regmap, 1442 int *reg, u8 *bit) 1443 { 1444 struct rockchip_pinctrl *info = bank->drvdata; 1445 1446 *regmap = info->regmap_base; 1447 *reg = RK3228_PULL_OFFSET; 1448 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1449 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1450 1451 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1452 *bit *= RK3188_PULL_BITS_PER_PIN; 1453 1454 return 0; 1455 } 1456 1457 #define RK3228_DRV_GRF_OFFSET 0x200 1458 1459 static int rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1460 int pin_num, struct regmap **regmap, 1461 int *reg, u8 *bit) 1462 { 1463 struct rockchip_pinctrl *info = bank->drvdata; 1464 1465 *regmap = info->regmap_base; 1466 *reg = RK3228_DRV_GRF_OFFSET; 1467 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 1468 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1469 1470 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 1471 *bit *= RK3288_DRV_BITS_PER_PIN; 1472 1473 return 0; 1474 } 1475 1476 #define RK3308_PULL_OFFSET 0xa0 1477 1478 static int rk3308_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1479 int pin_num, struct regmap **regmap, 1480 int *reg, u8 *bit) 1481 { 1482 struct rockchip_pinctrl *info = bank->drvdata; 1483 1484 *regmap = info->regmap_base; 1485 *reg = RK3308_PULL_OFFSET; 1486 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1487 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1488 1489 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1490 *bit *= RK3188_PULL_BITS_PER_PIN; 1491 1492 return 0; 1493 } 1494 1495 #define RK3308_DRV_GRF_OFFSET 0x100 1496 1497 static int rk3308_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1498 int pin_num, struct regmap **regmap, 1499 int *reg, u8 *bit) 1500 { 1501 struct rockchip_pinctrl *info = bank->drvdata; 1502 1503 *regmap = info->regmap_base; 1504 *reg = RK3308_DRV_GRF_OFFSET; 1505 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 1506 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1507 1508 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 1509 *bit *= RK3288_DRV_BITS_PER_PIN; 1510 1511 return 0; 1512 } 1513 1514 #define RK3368_PULL_GRF_OFFSET 0x100 1515 #define RK3368_PULL_PMU_OFFSET 0x10 1516 1517 static int rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1518 int pin_num, struct regmap **regmap, 1519 int *reg, u8 *bit) 1520 { 1521 struct rockchip_pinctrl *info = bank->drvdata; 1522 1523 /* The first 32 pins of the first bank are located in PMU */ 1524 if (bank->bank_num == 0) { 1525 *regmap = info->regmap_pmu; 1526 *reg = RK3368_PULL_PMU_OFFSET; 1527 1528 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1529 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 1530 *bit *= RK3188_PULL_BITS_PER_PIN; 1531 } else { 1532 *regmap = info->regmap_base; 1533 *reg = RK3368_PULL_GRF_OFFSET; 1534 1535 /* correct the offset, as we're starting with the 2nd bank */ 1536 *reg -= 0x10; 1537 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1538 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1539 1540 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1541 *bit *= RK3188_PULL_BITS_PER_PIN; 1542 } 1543 1544 return 0; 1545 } 1546 1547 #define RK3368_DRV_PMU_OFFSET 0x20 1548 #define RK3368_DRV_GRF_OFFSET 0x200 1549 1550 static int rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1551 int pin_num, struct regmap **regmap, 1552 int *reg, u8 *bit) 1553 { 1554 struct rockchip_pinctrl *info = bank->drvdata; 1555 1556 /* The first 32 pins of the first bank are located in PMU */ 1557 if (bank->bank_num == 0) { 1558 *regmap = info->regmap_pmu; 1559 *reg = RK3368_DRV_PMU_OFFSET; 1560 1561 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1562 *bit = pin_num % RK3288_DRV_PINS_PER_REG; 1563 *bit *= RK3288_DRV_BITS_PER_PIN; 1564 } else { 1565 *regmap = info->regmap_base; 1566 *reg = RK3368_DRV_GRF_OFFSET; 1567 1568 /* correct the offset, as we're starting with the 2nd bank */ 1569 *reg -= 0x10; 1570 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 1571 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1572 1573 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 1574 *bit *= RK3288_DRV_BITS_PER_PIN; 1575 } 1576 1577 return 0; 1578 } 1579 1580 #define RK3399_PULL_GRF_OFFSET 0xe040 1581 #define RK3399_PULL_PMU_OFFSET 0x40 1582 #define RK3399_DRV_3BITS_PER_PIN 3 1583 1584 static int rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1585 int pin_num, struct regmap **regmap, 1586 int *reg, u8 *bit) 1587 { 1588 struct rockchip_pinctrl *info = bank->drvdata; 1589 1590 /* The bank0:16 and bank1:32 pins are located in PMU */ 1591 if ((bank->bank_num == 0) || (bank->bank_num == 1)) { 1592 *regmap = info->regmap_pmu; 1593 *reg = RK3399_PULL_PMU_OFFSET; 1594 1595 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1596 1597 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1598 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 1599 *bit *= RK3188_PULL_BITS_PER_PIN; 1600 } else { 1601 *regmap = info->regmap_base; 1602 *reg = RK3399_PULL_GRF_OFFSET; 1603 1604 /* correct the offset, as we're starting with the 3rd bank */ 1605 *reg -= 0x20; 1606 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1607 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1608 1609 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1610 *bit *= RK3188_PULL_BITS_PER_PIN; 1611 } 1612 1613 return 0; 1614 } 1615 1616 static int rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1617 int pin_num, struct regmap **regmap, 1618 int *reg, u8 *bit) 1619 { 1620 struct rockchip_pinctrl *info = bank->drvdata; 1621 int drv_num = (pin_num / 8); 1622 1623 /* The bank0:16 and bank1:32 pins are located in PMU */ 1624 if ((bank->bank_num == 0) || (bank->bank_num == 1)) 1625 *regmap = info->regmap_pmu; 1626 else 1627 *regmap = info->regmap_base; 1628 1629 *reg = bank->drv[drv_num].offset; 1630 if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) || 1631 (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY)) 1632 *bit = (pin_num % 8) * 3; 1633 else 1634 *bit = (pin_num % 8) * 2; 1635 1636 return 0; 1637 } 1638 1639 #define RK3568_PULL_PMU_OFFSET 0x20 1640 #define RK3568_PULL_GRF_OFFSET 0x80 1641 #define RK3568_PULL_BITS_PER_PIN 2 1642 #define RK3568_PULL_PINS_PER_REG 8 1643 #define RK3568_PULL_BANK_STRIDE 0x10 1644 1645 static int rk3568_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1646 int pin_num, struct regmap **regmap, 1647 int *reg, u8 *bit) 1648 { 1649 struct rockchip_pinctrl *info = bank->drvdata; 1650 1651 if (bank->bank_num == 0) { 1652 *regmap = info->regmap_pmu; 1653 *reg = RK3568_PULL_PMU_OFFSET; 1654 *reg += bank->bank_num * RK3568_PULL_BANK_STRIDE; 1655 *reg += ((pin_num / RK3568_PULL_PINS_PER_REG) * 4); 1656 1657 *bit = pin_num % RK3568_PULL_PINS_PER_REG; 1658 *bit *= RK3568_PULL_BITS_PER_PIN; 1659 } else { 1660 *regmap = info->regmap_base; 1661 *reg = RK3568_PULL_GRF_OFFSET; 1662 *reg += (bank->bank_num - 1) * RK3568_PULL_BANK_STRIDE; 1663 *reg += ((pin_num / RK3568_PULL_PINS_PER_REG) * 4); 1664 1665 *bit = (pin_num % RK3568_PULL_PINS_PER_REG); 1666 *bit *= RK3568_PULL_BITS_PER_PIN; 1667 } 1668 1669 return 0; 1670 } 1671 1672 #define RK3568_DRV_PMU_OFFSET 0x70 1673 #define RK3568_DRV_GRF_OFFSET 0x200 1674 #define RK3568_DRV_BITS_PER_PIN 8 1675 #define RK3568_DRV_PINS_PER_REG 2 1676 #define RK3568_DRV_BANK_STRIDE 0x40 1677 1678 static int rk3568_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1679 int pin_num, struct regmap **regmap, 1680 int *reg, u8 *bit) 1681 { 1682 struct rockchip_pinctrl *info = bank->drvdata; 1683 1684 /* The first 32 pins of the first bank are located in PMU */ 1685 if (bank->bank_num == 0) { 1686 *regmap = info->regmap_pmu; 1687 *reg = RK3568_DRV_PMU_OFFSET; 1688 *reg += ((pin_num / RK3568_DRV_PINS_PER_REG) * 4); 1689 1690 *bit = pin_num % RK3568_DRV_PINS_PER_REG; 1691 *bit *= RK3568_DRV_BITS_PER_PIN; 1692 } else { 1693 *regmap = info->regmap_base; 1694 *reg = RK3568_DRV_GRF_OFFSET; 1695 *reg += (bank->bank_num - 1) * RK3568_DRV_BANK_STRIDE; 1696 *reg += ((pin_num / RK3568_DRV_PINS_PER_REG) * 4); 1697 1698 *bit = (pin_num % RK3568_DRV_PINS_PER_REG); 1699 *bit *= RK3568_DRV_BITS_PER_PIN; 1700 } 1701 1702 return 0; 1703 } 1704 1705 #define RK3588_PMU1_IOC_REG (0x0000) 1706 #define RK3588_PMU2_IOC_REG (0x4000) 1707 #define RK3588_BUS_IOC_REG (0x8000) 1708 #define RK3588_VCCIO1_4_IOC_REG (0x9000) 1709 #define RK3588_VCCIO3_5_IOC_REG (0xA000) 1710 #define RK3588_VCCIO2_IOC_REG (0xB000) 1711 #define RK3588_VCCIO6_IOC_REG (0xC000) 1712 #define RK3588_EMMC_IOC_REG (0xD000) 1713 1714 static const u32 rk3588_ds_regs[][2] = { 1715 {RK_GPIO0_A0, RK3588_PMU1_IOC_REG + 0x0010}, 1716 {RK_GPIO0_A4, RK3588_PMU1_IOC_REG + 0x0014}, 1717 {RK_GPIO0_B0, RK3588_PMU1_IOC_REG + 0x0018}, 1718 {RK_GPIO0_B4, RK3588_PMU2_IOC_REG + 0x0014}, 1719 {RK_GPIO0_C0, RK3588_PMU2_IOC_REG + 0x0018}, 1720 {RK_GPIO0_C4, RK3588_PMU2_IOC_REG + 0x001C}, 1721 {RK_GPIO0_D0, RK3588_PMU2_IOC_REG + 0x0020}, 1722 {RK_GPIO0_D4, RK3588_PMU2_IOC_REG + 0x0024}, 1723 {RK_GPIO1_A0, RK3588_VCCIO1_4_IOC_REG + 0x0020}, 1724 {RK_GPIO1_A4, RK3588_VCCIO1_4_IOC_REG + 0x0024}, 1725 {RK_GPIO1_B0, RK3588_VCCIO1_4_IOC_REG + 0x0028}, 1726 {RK_GPIO1_B4, RK3588_VCCIO1_4_IOC_REG + 0x002C}, 1727 {RK_GPIO1_C0, RK3588_VCCIO1_4_IOC_REG + 0x0030}, 1728 {RK_GPIO1_C4, RK3588_VCCIO1_4_IOC_REG + 0x0034}, 1729 {RK_GPIO1_D0, RK3588_VCCIO1_4_IOC_REG + 0x0038}, 1730 {RK_GPIO1_D4, RK3588_VCCIO1_4_IOC_REG + 0x003C}, 1731 {RK_GPIO2_A0, RK3588_EMMC_IOC_REG + 0x0040}, 1732 {RK_GPIO2_A4, RK3588_VCCIO3_5_IOC_REG + 0x0044}, 1733 {RK_GPIO2_B0, RK3588_VCCIO3_5_IOC_REG + 0x0048}, 1734 {RK_GPIO2_B4, RK3588_VCCIO3_5_IOC_REG + 0x004C}, 1735 {RK_GPIO2_C0, RK3588_VCCIO3_5_IOC_REG + 0x0050}, 1736 {RK_GPIO2_C4, RK3588_VCCIO3_5_IOC_REG + 0x0054}, 1737 {RK_GPIO2_D0, RK3588_EMMC_IOC_REG + 0x0058}, 1738 {RK_GPIO2_D4, RK3588_EMMC_IOC_REG + 0x005C}, 1739 {RK_GPIO3_A0, RK3588_VCCIO3_5_IOC_REG + 0x0060}, 1740 {RK_GPIO3_A4, RK3588_VCCIO3_5_IOC_REG + 0x0064}, 1741 {RK_GPIO3_B0, RK3588_VCCIO3_5_IOC_REG + 0x0068}, 1742 {RK_GPIO3_B4, RK3588_VCCIO3_5_IOC_REG + 0x006C}, 1743 {RK_GPIO3_C0, RK3588_VCCIO3_5_IOC_REG + 0x0070}, 1744 {RK_GPIO3_C4, RK3588_VCCIO3_5_IOC_REG + 0x0074}, 1745 {RK_GPIO3_D0, RK3588_VCCIO3_5_IOC_REG + 0x0078}, 1746 {RK_GPIO3_D4, RK3588_VCCIO3_5_IOC_REG + 0x007C}, 1747 {RK_GPIO4_A0, RK3588_VCCIO6_IOC_REG + 0x0080}, 1748 {RK_GPIO4_A4, RK3588_VCCIO6_IOC_REG + 0x0084}, 1749 {RK_GPIO4_B0, RK3588_VCCIO6_IOC_REG + 0x0088}, 1750 {RK_GPIO4_B4, RK3588_VCCIO6_IOC_REG + 0x008C}, 1751 {RK_GPIO4_C0, RK3588_VCCIO6_IOC_REG + 0x0090}, 1752 {RK_GPIO4_C2, RK3588_VCCIO3_5_IOC_REG + 0x0090}, 1753 {RK_GPIO4_C4, RK3588_VCCIO3_5_IOC_REG + 0x0094}, 1754 {RK_GPIO4_D0, RK3588_VCCIO2_IOC_REG + 0x0098}, 1755 {RK_GPIO4_D4, RK3588_VCCIO2_IOC_REG + 0x009C}, 1756 }; 1757 1758 static const u32 rk3588_p_regs[][2] = { 1759 {RK_GPIO0_A0, RK3588_PMU1_IOC_REG + 0x0020}, 1760 {RK_GPIO0_B0, RK3588_PMU1_IOC_REG + 0x0024}, 1761 {RK_GPIO0_B5, RK3588_PMU2_IOC_REG + 0x0028}, 1762 {RK_GPIO0_C0, RK3588_PMU2_IOC_REG + 0x002C}, 1763 {RK_GPIO0_D0, RK3588_PMU2_IOC_REG + 0x0030}, 1764 {RK_GPIO1_A0, RK3588_VCCIO1_4_IOC_REG + 0x0110}, 1765 {RK_GPIO1_B0, RK3588_VCCIO1_4_IOC_REG + 0x0114}, 1766 {RK_GPIO1_C0, RK3588_VCCIO1_4_IOC_REG + 0x0118}, 1767 {RK_GPIO1_D0, RK3588_VCCIO1_4_IOC_REG + 0x011C}, 1768 {RK_GPIO2_A0, RK3588_EMMC_IOC_REG + 0x0120}, 1769 {RK_GPIO2_A6, RK3588_VCCIO3_5_IOC_REG + 0x0120}, 1770 {RK_GPIO2_B0, RK3588_VCCIO3_5_IOC_REG + 0x0124}, 1771 {RK_GPIO2_C0, RK3588_VCCIO3_5_IOC_REG + 0x0128}, 1772 {RK_GPIO2_D0, RK3588_EMMC_IOC_REG + 0x012C}, 1773 {RK_GPIO3_A0, RK3588_VCCIO3_5_IOC_REG + 0x0130}, 1774 {RK_GPIO3_B0, RK3588_VCCIO3_5_IOC_REG + 0x0134}, 1775 {RK_GPIO3_C0, RK3588_VCCIO3_5_IOC_REG + 0x0138}, 1776 {RK_GPIO3_D0, RK3588_VCCIO3_5_IOC_REG + 0x013C}, 1777 {RK_GPIO4_A0, RK3588_VCCIO6_IOC_REG + 0x0140}, 1778 {RK_GPIO4_B0, RK3588_VCCIO6_IOC_REG + 0x0144}, 1779 {RK_GPIO4_C0, RK3588_VCCIO6_IOC_REG + 0x0148}, 1780 {RK_GPIO4_C2, RK3588_VCCIO3_5_IOC_REG + 0x0148}, 1781 {RK_GPIO4_D0, RK3588_VCCIO2_IOC_REG + 0x014C}, 1782 }; 1783 1784 static const u32 rk3588_smt_regs[][2] = { 1785 {RK_GPIO0_A0, RK3588_PMU1_IOC_REG + 0x0030}, 1786 {RK_GPIO0_B0, RK3588_PMU1_IOC_REG + 0x0034}, 1787 {RK_GPIO0_B5, RK3588_PMU2_IOC_REG + 0x0040}, 1788 {RK_GPIO0_C0, RK3588_PMU2_IOC_REG + 0x0044}, 1789 {RK_GPIO0_D0, RK3588_PMU2_IOC_REG + 0x0048}, 1790 {RK_GPIO1_A0, RK3588_VCCIO1_4_IOC_REG + 0x0210}, 1791 {RK_GPIO1_B0, RK3588_VCCIO1_4_IOC_REG + 0x0214}, 1792 {RK_GPIO1_C0, RK3588_VCCIO1_4_IOC_REG + 0x0218}, 1793 {RK_GPIO1_D0, RK3588_VCCIO1_4_IOC_REG + 0x021C}, 1794 {RK_GPIO2_A0, RK3588_EMMC_IOC_REG + 0x0220}, 1795 {RK_GPIO2_A6, RK3588_VCCIO3_5_IOC_REG + 0x0220}, 1796 {RK_GPIO2_B0, RK3588_VCCIO3_5_IOC_REG + 0x0224}, 1797 {RK_GPIO2_C0, RK3588_VCCIO3_5_IOC_REG + 0x0228}, 1798 {RK_GPIO2_D0, RK3588_EMMC_IOC_REG + 0x022C}, 1799 {RK_GPIO3_A0, RK3588_VCCIO3_5_IOC_REG + 0x0230}, 1800 {RK_GPIO3_B0, RK3588_VCCIO3_5_IOC_REG + 0x0234}, 1801 {RK_GPIO3_C0, RK3588_VCCIO3_5_IOC_REG + 0x0238}, 1802 {RK_GPIO3_D0, RK3588_VCCIO3_5_IOC_REG + 0x023C}, 1803 {RK_GPIO4_A0, RK3588_VCCIO6_IOC_REG + 0x0240}, 1804 {RK_GPIO4_B0, RK3588_VCCIO6_IOC_REG + 0x0244}, 1805 {RK_GPIO4_C0, RK3588_VCCIO6_IOC_REG + 0x0248}, 1806 {RK_GPIO4_C2, RK3588_VCCIO3_5_IOC_REG + 0x0248}, 1807 {RK_GPIO4_D0, RK3588_VCCIO2_IOC_REG + 0x024C}, 1808 }; 1809 1810 #define RK3588_PULL_BITS_PER_PIN 2 1811 #define RK3588_PULL_PINS_PER_REG 8 1812 1813 static int rk3588_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1814 int pin_num, struct regmap **regmap, 1815 int *reg, u8 *bit) 1816 { 1817 struct rockchip_pinctrl *info = bank->drvdata; 1818 u8 bank_num = bank->bank_num; 1819 u32 pin = bank_num * 32 + pin_num; 1820 int i; 1821 1822 for (i = ARRAY_SIZE(rk3588_p_regs) - 1; i >= 0; i--) { 1823 if (pin >= rk3588_p_regs[i][0]) { 1824 *reg = rk3588_p_regs[i][1]; 1825 *regmap = info->regmap_base; 1826 *bit = pin_num % RK3588_PULL_PINS_PER_REG; 1827 *bit *= RK3588_PULL_BITS_PER_PIN; 1828 return 0; 1829 } 1830 } 1831 1832 return -EINVAL; 1833 } 1834 1835 #define RK3588_DRV_BITS_PER_PIN 4 1836 #define RK3588_DRV_PINS_PER_REG 4 1837 1838 static int rk3588_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1839 int pin_num, struct regmap **regmap, 1840 int *reg, u8 *bit) 1841 { 1842 struct rockchip_pinctrl *info = bank->drvdata; 1843 u8 bank_num = bank->bank_num; 1844 u32 pin = bank_num * 32 + pin_num; 1845 int i; 1846 1847 for (i = ARRAY_SIZE(rk3588_ds_regs) - 1; i >= 0; i--) { 1848 if (pin >= rk3588_ds_regs[i][0]) { 1849 *reg = rk3588_ds_regs[i][1]; 1850 *regmap = info->regmap_base; 1851 *bit = pin_num % RK3588_DRV_PINS_PER_REG; 1852 *bit *= RK3588_DRV_BITS_PER_PIN; 1853 return 0; 1854 } 1855 } 1856 1857 return -EINVAL; 1858 } 1859 1860 #define RK3588_SMT_BITS_PER_PIN 1 1861 #define RK3588_SMT_PINS_PER_REG 8 1862 1863 static int rk3588_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1864 int pin_num, 1865 struct regmap **regmap, 1866 int *reg, u8 *bit) 1867 { 1868 struct rockchip_pinctrl *info = bank->drvdata; 1869 u8 bank_num = bank->bank_num; 1870 u32 pin = bank_num * 32 + pin_num; 1871 int i; 1872 1873 for (i = ARRAY_SIZE(rk3588_smt_regs) - 1; i >= 0; i--) { 1874 if (pin >= rk3588_smt_regs[i][0]) { 1875 *reg = rk3588_smt_regs[i][1]; 1876 *regmap = info->regmap_base; 1877 *bit = pin_num % RK3588_SMT_PINS_PER_REG; 1878 *bit *= RK3588_SMT_BITS_PER_PIN; 1879 return 0; 1880 } 1881 } 1882 1883 return -EINVAL; 1884 } 1885 1886 static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = { 1887 { 2, 4, 8, 12, -1, -1, -1, -1 }, 1888 { 3, 6, 9, 12, -1, -1, -1, -1 }, 1889 { 5, 10, 15, 20, -1, -1, -1, -1 }, 1890 { 4, 6, 8, 10, 12, 14, 16, 18 }, 1891 { 4, 7, 10, 13, 16, 19, 22, 26 } 1892 }; 1893 1894 static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank, 1895 int pin_num) 1896 { 1897 struct rockchip_pinctrl *info = bank->drvdata; 1898 struct rockchip_pin_ctrl *ctrl = info->ctrl; 1899 struct device *dev = info->dev; 1900 struct regmap *regmap; 1901 int reg, ret; 1902 u32 data, temp, rmask_bits; 1903 u8 bit; 1904 int drv_type = bank->drv[pin_num / 8].drv_type; 1905 1906 ret = ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); 1907 if (ret) 1908 return ret; 1909 1910 switch (drv_type) { 1911 case DRV_TYPE_IO_1V8_3V0_AUTO: 1912 case DRV_TYPE_IO_3V3_ONLY: 1913 rmask_bits = RK3399_DRV_3BITS_PER_PIN; 1914 switch (bit) { 1915 case 0 ... 12: 1916 /* regular case, nothing to do */ 1917 break; 1918 case 15: 1919 /* 1920 * drive-strength offset is special, as it is 1921 * spread over 2 registers 1922 */ 1923 ret = regmap_read(regmap, reg, &data); 1924 if (ret) 1925 return ret; 1926 1927 ret = regmap_read(regmap, reg + 0x4, &temp); 1928 if (ret) 1929 return ret; 1930 1931 /* 1932 * the bit data[15] contains bit 0 of the value 1933 * while temp[1:0] contains bits 2 and 1 1934 */ 1935 data >>= 15; 1936 temp &= 0x3; 1937 temp <<= 1; 1938 data |= temp; 1939 1940 return rockchip_perpin_drv_list[drv_type][data]; 1941 case 18 ... 21: 1942 /* setting fully enclosed in the second register */ 1943 reg += 4; 1944 bit -= 16; 1945 break; 1946 default: 1947 dev_err(dev, "unsupported bit: %d for pinctrl drive type: %d\n", 1948 bit, drv_type); 1949 return -EINVAL; 1950 } 1951 1952 break; 1953 case DRV_TYPE_IO_DEFAULT: 1954 case DRV_TYPE_IO_1V8_OR_3V0: 1955 case DRV_TYPE_IO_1V8_ONLY: 1956 rmask_bits = RK3288_DRV_BITS_PER_PIN; 1957 break; 1958 default: 1959 dev_err(dev, "unsupported pinctrl drive type: %d\n", drv_type); 1960 return -EINVAL; 1961 } 1962 1963 ret = regmap_read(regmap, reg, &data); 1964 if (ret) 1965 return ret; 1966 1967 data >>= bit; 1968 data &= (1 << rmask_bits) - 1; 1969 1970 return rockchip_perpin_drv_list[drv_type][data]; 1971 } 1972 1973 static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank, 1974 int pin_num, int strength) 1975 { 1976 struct rockchip_pinctrl *info = bank->drvdata; 1977 struct rockchip_pin_ctrl *ctrl = info->ctrl; 1978 struct device *dev = info->dev; 1979 struct regmap *regmap; 1980 int reg, ret, i; 1981 u32 data, rmask, rmask_bits, temp; 1982 u8 bit; 1983 int drv_type = bank->drv[pin_num / 8].drv_type; 1984 1985 dev_dbg(dev, "setting drive of GPIO%d-%d to %d\n", 1986 bank->bank_num, pin_num, strength); 1987 1988 ret = ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); 1989 if (ret) 1990 return ret; 1991 if (ctrl->type == RK3588) { 1992 rmask_bits = RK3588_DRV_BITS_PER_PIN; 1993 ret = strength; 1994 goto config; 1995 } else if (ctrl->type == RK3568) { 1996 rmask_bits = RK3568_DRV_BITS_PER_PIN; 1997 ret = (1 << (strength + 1)) - 1; 1998 goto config; 1999 } 2000 2001 ret = -EINVAL; 2002 for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) { 2003 if (rockchip_perpin_drv_list[drv_type][i] == strength) { 2004 ret = i; 2005 break; 2006 } else if (rockchip_perpin_drv_list[drv_type][i] < 0) { 2007 ret = rockchip_perpin_drv_list[drv_type][i]; 2008 break; 2009 } 2010 } 2011 2012 if (ret < 0) { 2013 dev_err(dev, "unsupported driver strength %d\n", strength); 2014 return ret; 2015 } 2016 2017 switch (drv_type) { 2018 case DRV_TYPE_IO_1V8_3V0_AUTO: 2019 case DRV_TYPE_IO_3V3_ONLY: 2020 rmask_bits = RK3399_DRV_3BITS_PER_PIN; 2021 switch (bit) { 2022 case 0 ... 12: 2023 /* regular case, nothing to do */ 2024 break; 2025 case 15: 2026 /* 2027 * drive-strength offset is special, as it is spread 2028 * over 2 registers, the bit data[15] contains bit 0 2029 * of the value while temp[1:0] contains bits 2 and 1 2030 */ 2031 data = (ret & 0x1) << 15; 2032 temp = (ret >> 0x1) & 0x3; 2033 2034 rmask = BIT(15) | BIT(31); 2035 data |= BIT(31); 2036 ret = regmap_update_bits(regmap, reg, rmask, data); 2037 if (ret) 2038 return ret; 2039 2040 rmask = 0x3 | (0x3 << 16); 2041 temp |= (0x3 << 16); 2042 reg += 0x4; 2043 ret = regmap_update_bits(regmap, reg, rmask, temp); 2044 2045 return ret; 2046 case 18 ... 21: 2047 /* setting fully enclosed in the second register */ 2048 reg += 4; 2049 bit -= 16; 2050 break; 2051 default: 2052 dev_err(dev, "unsupported bit: %d for pinctrl drive type: %d\n", 2053 bit, drv_type); 2054 return -EINVAL; 2055 } 2056 break; 2057 case DRV_TYPE_IO_DEFAULT: 2058 case DRV_TYPE_IO_1V8_OR_3V0: 2059 case DRV_TYPE_IO_1V8_ONLY: 2060 rmask_bits = RK3288_DRV_BITS_PER_PIN; 2061 break; 2062 default: 2063 dev_err(dev, "unsupported pinctrl drive type: %d\n", drv_type); 2064 return -EINVAL; 2065 } 2066 2067 config: 2068 /* enable the write to the equivalent lower bits */ 2069 data = ((1 << rmask_bits) - 1) << (bit + 16); 2070 rmask = data | (data >> 16); 2071 data |= (ret << bit); 2072 2073 ret = regmap_update_bits(regmap, reg, rmask, data); 2074 2075 return ret; 2076 } 2077 2078 static int rockchip_pull_list[PULL_TYPE_MAX][4] = { 2079 { 2080 PIN_CONFIG_BIAS_DISABLE, 2081 PIN_CONFIG_BIAS_PULL_UP, 2082 PIN_CONFIG_BIAS_PULL_DOWN, 2083 PIN_CONFIG_BIAS_BUS_HOLD 2084 }, 2085 { 2086 PIN_CONFIG_BIAS_DISABLE, 2087 PIN_CONFIG_BIAS_PULL_DOWN, 2088 PIN_CONFIG_BIAS_DISABLE, 2089 PIN_CONFIG_BIAS_PULL_UP 2090 }, 2091 }; 2092 2093 static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num) 2094 { 2095 struct rockchip_pinctrl *info = bank->drvdata; 2096 struct rockchip_pin_ctrl *ctrl = info->ctrl; 2097 struct device *dev = info->dev; 2098 struct regmap *regmap; 2099 int reg, ret, pull_type; 2100 u8 bit; 2101 u32 data; 2102 2103 /* rk3066b does support any pulls */ 2104 if (ctrl->type == RK3066B) 2105 return PIN_CONFIG_BIAS_DISABLE; 2106 2107 ret = ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); 2108 if (ret) 2109 return ret; 2110 2111 ret = regmap_read(regmap, reg, &data); 2112 if (ret) 2113 return ret; 2114 2115 switch (ctrl->type) { 2116 case RK2928: 2117 case RK3128: 2118 return !(data & BIT(bit)) 2119 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT 2120 : PIN_CONFIG_BIAS_DISABLE; 2121 case PX30: 2122 case RV1108: 2123 case RK3188: 2124 case RK3288: 2125 case RK3308: 2126 case RK3368: 2127 case RK3399: 2128 case RK3588: 2129 pull_type = bank->pull_type[pin_num / 8]; 2130 data >>= bit; 2131 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1; 2132 2133 return rockchip_pull_list[pull_type][data]; 2134 default: 2135 dev_err(dev, "unsupported pinctrl type\n"); 2136 return -EINVAL; 2137 }; 2138 } 2139 2140 static int rockchip_set_pull(struct rockchip_pin_bank *bank, 2141 int pin_num, int pull) 2142 { 2143 struct rockchip_pinctrl *info = bank->drvdata; 2144 struct rockchip_pin_ctrl *ctrl = info->ctrl; 2145 struct device *dev = info->dev; 2146 struct regmap *regmap; 2147 int reg, ret, i, pull_type; 2148 u8 bit; 2149 u32 data, rmask; 2150 2151 dev_dbg(dev, "setting pull of GPIO%d-%d to %d\n", bank->bank_num, pin_num, pull); 2152 2153 /* rk3066b does support any pulls */ 2154 if (ctrl->type == RK3066B) 2155 return pull ? -EINVAL : 0; 2156 2157 ret = ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); 2158 if (ret) 2159 return ret; 2160 2161 switch (ctrl->type) { 2162 case RK2928: 2163 case RK3128: 2164 data = BIT(bit + 16); 2165 if (pull == PIN_CONFIG_BIAS_DISABLE) 2166 data |= BIT(bit); 2167 ret = regmap_write(regmap, reg, data); 2168 break; 2169 case PX30: 2170 case RV1108: 2171 case RK3188: 2172 case RK3288: 2173 case RK3308: 2174 case RK3368: 2175 case RK3399: 2176 case RK3568: 2177 case RK3588: 2178 pull_type = bank->pull_type[pin_num / 8]; 2179 ret = -EINVAL; 2180 for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]); 2181 i++) { 2182 if (rockchip_pull_list[pull_type][i] == pull) { 2183 ret = i; 2184 break; 2185 } 2186 } 2187 /* 2188 * In the TRM, pull-up being 1 for everything except the GPIO0_D0-D6, 2189 * where that pull up value becomes 3. 2190 */ 2191 if (ctrl->type == RK3568 && bank->bank_num == 0 && pin_num >= 27 && pin_num <= 30) { 2192 if (ret == 1) 2193 ret = 3; 2194 } 2195 2196 if (ret < 0) { 2197 dev_err(dev, "unsupported pull setting %d\n", pull); 2198 return ret; 2199 } 2200 2201 /* enable the write to the equivalent lower bits */ 2202 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16); 2203 rmask = data | (data >> 16); 2204 data |= (ret << bit); 2205 2206 ret = regmap_update_bits(regmap, reg, rmask, data); 2207 break; 2208 default: 2209 dev_err(dev, "unsupported pinctrl type\n"); 2210 return -EINVAL; 2211 } 2212 2213 return ret; 2214 } 2215 2216 #define RK3328_SCHMITT_BITS_PER_PIN 1 2217 #define RK3328_SCHMITT_PINS_PER_REG 16 2218 #define RK3328_SCHMITT_BANK_STRIDE 8 2219 #define RK3328_SCHMITT_GRF_OFFSET 0x380 2220 2221 static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 2222 int pin_num, 2223 struct regmap **regmap, 2224 int *reg, u8 *bit) 2225 { 2226 struct rockchip_pinctrl *info = bank->drvdata; 2227 2228 *regmap = info->regmap_base; 2229 *reg = RK3328_SCHMITT_GRF_OFFSET; 2230 2231 *reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE; 2232 *reg += ((pin_num / RK3328_SCHMITT_PINS_PER_REG) * 4); 2233 *bit = pin_num % RK3328_SCHMITT_PINS_PER_REG; 2234 2235 return 0; 2236 } 2237 2238 #define RK3568_SCHMITT_BITS_PER_PIN 2 2239 #define RK3568_SCHMITT_PINS_PER_REG 8 2240 #define RK3568_SCHMITT_BANK_STRIDE 0x10 2241 #define RK3568_SCHMITT_GRF_OFFSET 0xc0 2242 #define RK3568_SCHMITT_PMUGRF_OFFSET 0x30 2243 2244 static int rk3568_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 2245 int pin_num, 2246 struct regmap **regmap, 2247 int *reg, u8 *bit) 2248 { 2249 struct rockchip_pinctrl *info = bank->drvdata; 2250 2251 if (bank->bank_num == 0) { 2252 *regmap = info->regmap_pmu; 2253 *reg = RK3568_SCHMITT_PMUGRF_OFFSET; 2254 } else { 2255 *regmap = info->regmap_base; 2256 *reg = RK3568_SCHMITT_GRF_OFFSET; 2257 *reg += (bank->bank_num - 1) * RK3568_SCHMITT_BANK_STRIDE; 2258 } 2259 2260 *reg += ((pin_num / RK3568_SCHMITT_PINS_PER_REG) * 4); 2261 *bit = pin_num % RK3568_SCHMITT_PINS_PER_REG; 2262 *bit *= RK3568_SCHMITT_BITS_PER_PIN; 2263 2264 return 0; 2265 } 2266 2267 static int rockchip_get_schmitt(struct rockchip_pin_bank *bank, int pin_num) 2268 { 2269 struct rockchip_pinctrl *info = bank->drvdata; 2270 struct rockchip_pin_ctrl *ctrl = info->ctrl; 2271 struct regmap *regmap; 2272 int reg, ret; 2273 u8 bit; 2274 u32 data; 2275 2276 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit); 2277 if (ret) 2278 return ret; 2279 2280 ret = regmap_read(regmap, reg, &data); 2281 if (ret) 2282 return ret; 2283 2284 data >>= bit; 2285 switch (ctrl->type) { 2286 case RK3568: 2287 return data & ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1); 2288 default: 2289 break; 2290 } 2291 2292 return data & 0x1; 2293 } 2294 2295 static int rockchip_set_schmitt(struct rockchip_pin_bank *bank, 2296 int pin_num, int enable) 2297 { 2298 struct rockchip_pinctrl *info = bank->drvdata; 2299 struct rockchip_pin_ctrl *ctrl = info->ctrl; 2300 struct device *dev = info->dev; 2301 struct regmap *regmap; 2302 int reg, ret; 2303 u8 bit; 2304 u32 data, rmask; 2305 2306 dev_dbg(dev, "setting input schmitt of GPIO%d-%d to %d\n", 2307 bank->bank_num, pin_num, enable); 2308 2309 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit); 2310 if (ret) 2311 return ret; 2312 2313 /* enable the write to the equivalent lower bits */ 2314 switch (ctrl->type) { 2315 case RK3568: 2316 data = ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1) << (bit + 16); 2317 rmask = data | (data >> 16); 2318 data |= ((enable ? 0x2 : 0x1) << bit); 2319 break; 2320 default: 2321 data = BIT(bit + 16) | (enable << bit); 2322 rmask = BIT(bit + 16) | BIT(bit); 2323 break; 2324 } 2325 2326 return regmap_update_bits(regmap, reg, rmask, data); 2327 } 2328 2329 /* 2330 * Pinmux_ops handling 2331 */ 2332 2333 static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev) 2334 { 2335 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 2336 2337 return info->nfunctions; 2338 } 2339 2340 static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev, 2341 unsigned selector) 2342 { 2343 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 2344 2345 return info->functions[selector].name; 2346 } 2347 2348 static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev, 2349 unsigned selector, const char * const **groups, 2350 unsigned * const num_groups) 2351 { 2352 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 2353 2354 *groups = info->functions[selector].groups; 2355 *num_groups = info->functions[selector].ngroups; 2356 2357 return 0; 2358 } 2359 2360 static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector, 2361 unsigned group) 2362 { 2363 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 2364 const unsigned int *pins = info->groups[group].pins; 2365 const struct rockchip_pin_config *data = info->groups[group].data; 2366 struct device *dev = info->dev; 2367 struct rockchip_pin_bank *bank; 2368 int cnt, ret = 0; 2369 2370 dev_dbg(dev, "enable function %s group %s\n", 2371 info->functions[selector].name, info->groups[group].name); 2372 2373 /* 2374 * for each pin in the pin group selected, program the corresponding 2375 * pin function number in the config register. 2376 */ 2377 for (cnt = 0; cnt < info->groups[group].npins; cnt++) { 2378 bank = pin_to_bank(info, pins[cnt]); 2379 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 2380 data[cnt].func); 2381 if (ret) 2382 break; 2383 } 2384 2385 if (ret) { 2386 /* revert the already done pin settings */ 2387 for (cnt--; cnt >= 0; cnt--) 2388 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0); 2389 2390 return ret; 2391 } 2392 2393 return 0; 2394 } 2395 2396 static const struct pinmux_ops rockchip_pmx_ops = { 2397 .get_functions_count = rockchip_pmx_get_funcs_count, 2398 .get_function_name = rockchip_pmx_get_func_name, 2399 .get_function_groups = rockchip_pmx_get_groups, 2400 .set_mux = rockchip_pmx_set, 2401 }; 2402 2403 /* 2404 * Pinconf_ops handling 2405 */ 2406 2407 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl, 2408 enum pin_config_param pull) 2409 { 2410 switch (ctrl->type) { 2411 case RK2928: 2412 case RK3128: 2413 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT || 2414 pull == PIN_CONFIG_BIAS_DISABLE); 2415 case RK3066B: 2416 return pull ? false : true; 2417 case PX30: 2418 case RV1108: 2419 case RK3188: 2420 case RK3288: 2421 case RK3308: 2422 case RK3368: 2423 case RK3399: 2424 case RK3568: 2425 case RK3588: 2426 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT); 2427 } 2428 2429 return false; 2430 } 2431 2432 static int rockchip_pinconf_defer_pin(struct rockchip_pin_bank *bank, 2433 unsigned int pin, u32 param, u32 arg) 2434 { 2435 struct rockchip_pin_deferred *cfg; 2436 2437 cfg = kzalloc(sizeof(*cfg), GFP_KERNEL); 2438 if (!cfg) 2439 return -ENOMEM; 2440 2441 cfg->pin = pin; 2442 cfg->param = param; 2443 cfg->arg = arg; 2444 2445 list_add_tail(&cfg->head, &bank->deferred_pins); 2446 2447 return 0; 2448 } 2449 2450 /* set the pin config settings for a specified pin */ 2451 static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 2452 unsigned long *configs, unsigned num_configs) 2453 { 2454 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 2455 struct rockchip_pin_bank *bank = pin_to_bank(info, pin); 2456 struct gpio_chip *gpio = &bank->gpio_chip; 2457 enum pin_config_param param; 2458 u32 arg; 2459 int i; 2460 int rc; 2461 2462 for (i = 0; i < num_configs; i++) { 2463 param = pinconf_to_config_param(configs[i]); 2464 arg = pinconf_to_config_argument(configs[i]); 2465 2466 if (param == PIN_CONFIG_OUTPUT || param == PIN_CONFIG_INPUT_ENABLE) { 2467 /* 2468 * Check for gpio driver not being probed yet. 2469 * The lock makes sure that either gpio-probe has completed 2470 * or the gpio driver hasn't probed yet. 2471 */ 2472 mutex_lock(&bank->deferred_lock); 2473 if (!gpio || !gpio->direction_output) { 2474 rc = rockchip_pinconf_defer_pin(bank, pin - bank->pin_base, param, 2475 arg); 2476 mutex_unlock(&bank->deferred_lock); 2477 if (rc) 2478 return rc; 2479 2480 break; 2481 } 2482 mutex_unlock(&bank->deferred_lock); 2483 } 2484 2485 switch (param) { 2486 case PIN_CONFIG_BIAS_DISABLE: 2487 rc = rockchip_set_pull(bank, pin - bank->pin_base, 2488 param); 2489 if (rc) 2490 return rc; 2491 break; 2492 case PIN_CONFIG_BIAS_PULL_UP: 2493 case PIN_CONFIG_BIAS_PULL_DOWN: 2494 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: 2495 case PIN_CONFIG_BIAS_BUS_HOLD: 2496 if (!rockchip_pinconf_pull_valid(info->ctrl, param)) 2497 return -ENOTSUPP; 2498 2499 if (!arg) 2500 return -EINVAL; 2501 2502 rc = rockchip_set_pull(bank, pin - bank->pin_base, 2503 param); 2504 if (rc) 2505 return rc; 2506 break; 2507 case PIN_CONFIG_OUTPUT: 2508 rc = rockchip_set_mux(bank, pin - bank->pin_base, 2509 RK_FUNC_GPIO); 2510 if (rc != RK_FUNC_GPIO) 2511 return -EINVAL; 2512 2513 rc = gpio->direction_output(gpio, pin - bank->pin_base, 2514 arg); 2515 if (rc) 2516 return rc; 2517 break; 2518 case PIN_CONFIG_INPUT_ENABLE: 2519 rc = rockchip_set_mux(bank, pin - bank->pin_base, 2520 RK_FUNC_GPIO); 2521 if (rc != RK_FUNC_GPIO) 2522 return -EINVAL; 2523 2524 rc = gpio->direction_input(gpio, pin - bank->pin_base); 2525 if (rc) 2526 return rc; 2527 break; 2528 case PIN_CONFIG_DRIVE_STRENGTH: 2529 /* rk3288 is the first with per-pin drive-strength */ 2530 if (!info->ctrl->drv_calc_reg) 2531 return -ENOTSUPP; 2532 2533 rc = rockchip_set_drive_perpin(bank, 2534 pin - bank->pin_base, arg); 2535 if (rc < 0) 2536 return rc; 2537 break; 2538 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 2539 if (!info->ctrl->schmitt_calc_reg) 2540 return -ENOTSUPP; 2541 2542 rc = rockchip_set_schmitt(bank, 2543 pin - bank->pin_base, arg); 2544 if (rc < 0) 2545 return rc; 2546 break; 2547 default: 2548 return -ENOTSUPP; 2549 break; 2550 } 2551 } /* for each config */ 2552 2553 return 0; 2554 } 2555 2556 /* get the pin config settings for a specified pin */ 2557 static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, 2558 unsigned long *config) 2559 { 2560 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 2561 struct rockchip_pin_bank *bank = pin_to_bank(info, pin); 2562 struct gpio_chip *gpio = &bank->gpio_chip; 2563 enum pin_config_param param = pinconf_to_config_param(*config); 2564 u16 arg; 2565 int rc; 2566 2567 switch (param) { 2568 case PIN_CONFIG_BIAS_DISABLE: 2569 if (rockchip_get_pull(bank, pin - bank->pin_base) != param) 2570 return -EINVAL; 2571 2572 arg = 0; 2573 break; 2574 case PIN_CONFIG_BIAS_PULL_UP: 2575 case PIN_CONFIG_BIAS_PULL_DOWN: 2576 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: 2577 case PIN_CONFIG_BIAS_BUS_HOLD: 2578 if (!rockchip_pinconf_pull_valid(info->ctrl, param)) 2579 return -ENOTSUPP; 2580 2581 if (rockchip_get_pull(bank, pin - bank->pin_base) != param) 2582 return -EINVAL; 2583 2584 arg = 1; 2585 break; 2586 case PIN_CONFIG_OUTPUT: 2587 rc = rockchip_get_mux(bank, pin - bank->pin_base); 2588 if (rc != RK_FUNC_GPIO) 2589 return -EINVAL; 2590 2591 if (!gpio || !gpio->get) { 2592 arg = 0; 2593 break; 2594 } 2595 2596 rc = gpio->get(gpio, pin - bank->pin_base); 2597 if (rc < 0) 2598 return rc; 2599 2600 arg = rc ? 1 : 0; 2601 break; 2602 case PIN_CONFIG_DRIVE_STRENGTH: 2603 /* rk3288 is the first with per-pin drive-strength */ 2604 if (!info->ctrl->drv_calc_reg) 2605 return -ENOTSUPP; 2606 2607 rc = rockchip_get_drive_perpin(bank, pin - bank->pin_base); 2608 if (rc < 0) 2609 return rc; 2610 2611 arg = rc; 2612 break; 2613 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 2614 if (!info->ctrl->schmitt_calc_reg) 2615 return -ENOTSUPP; 2616 2617 rc = rockchip_get_schmitt(bank, pin - bank->pin_base); 2618 if (rc < 0) 2619 return rc; 2620 2621 arg = rc; 2622 break; 2623 default: 2624 return -ENOTSUPP; 2625 break; 2626 } 2627 2628 *config = pinconf_to_config_packed(param, arg); 2629 2630 return 0; 2631 } 2632 2633 static const struct pinconf_ops rockchip_pinconf_ops = { 2634 .pin_config_get = rockchip_pinconf_get, 2635 .pin_config_set = rockchip_pinconf_set, 2636 .is_generic = true, 2637 }; 2638 2639 static const struct of_device_id rockchip_bank_match[] = { 2640 { .compatible = "rockchip,gpio-bank" }, 2641 { .compatible = "rockchip,rk3188-gpio-bank0" }, 2642 {}, 2643 }; 2644 2645 static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info, 2646 struct device_node *np) 2647 { 2648 struct device_node *child; 2649 2650 for_each_child_of_node(np, child) { 2651 if (of_match_node(rockchip_bank_match, child)) 2652 continue; 2653 2654 info->nfunctions++; 2655 info->ngroups += of_get_child_count(child); 2656 } 2657 } 2658 2659 static int rockchip_pinctrl_parse_groups(struct device_node *np, 2660 struct rockchip_pin_group *grp, 2661 struct rockchip_pinctrl *info, 2662 u32 index) 2663 { 2664 struct device *dev = info->dev; 2665 struct rockchip_pin_bank *bank; 2666 int size; 2667 const __be32 *list; 2668 int num; 2669 int i, j; 2670 int ret; 2671 2672 dev_dbg(dev, "group(%d): %pOFn\n", index, np); 2673 2674 /* Initialise group */ 2675 grp->name = np->name; 2676 2677 /* 2678 * the binding format is rockchip,pins = <bank pin mux CONFIG>, 2679 * do sanity check and calculate pins number 2680 */ 2681 list = of_get_property(np, "rockchip,pins", &size); 2682 /* we do not check return since it's safe node passed down */ 2683 size /= sizeof(*list); 2684 if (!size || size % 4) 2685 return dev_err_probe(dev, -EINVAL, "wrong pins number or pins and configs should be by 4\n"); 2686 2687 grp->npins = size / 4; 2688 2689 grp->pins = devm_kcalloc(dev, grp->npins, sizeof(*grp->pins), GFP_KERNEL); 2690 grp->data = devm_kcalloc(dev, grp->npins, sizeof(*grp->data), GFP_KERNEL); 2691 if (!grp->pins || !grp->data) 2692 return -ENOMEM; 2693 2694 for (i = 0, j = 0; i < size; i += 4, j++) { 2695 const __be32 *phandle; 2696 struct device_node *np_config; 2697 2698 num = be32_to_cpu(*list++); 2699 bank = bank_num_to_bank(info, num); 2700 if (IS_ERR(bank)) 2701 return PTR_ERR(bank); 2702 2703 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++); 2704 grp->data[j].func = be32_to_cpu(*list++); 2705 2706 phandle = list++; 2707 if (!phandle) 2708 return -EINVAL; 2709 2710 np_config = of_find_node_by_phandle(be32_to_cpup(phandle)); 2711 ret = pinconf_generic_parse_dt_config(np_config, NULL, 2712 &grp->data[j].configs, &grp->data[j].nconfigs); 2713 if (ret) 2714 return ret; 2715 } 2716 2717 return 0; 2718 } 2719 2720 static int rockchip_pinctrl_parse_functions(struct device_node *np, 2721 struct rockchip_pinctrl *info, 2722 u32 index) 2723 { 2724 struct device *dev = info->dev; 2725 struct device_node *child; 2726 struct rockchip_pmx_func *func; 2727 struct rockchip_pin_group *grp; 2728 int ret; 2729 static u32 grp_index; 2730 u32 i = 0; 2731 2732 dev_dbg(dev, "parse function(%d): %pOFn\n", index, np); 2733 2734 func = &info->functions[index]; 2735 2736 /* Initialise function */ 2737 func->name = np->name; 2738 func->ngroups = of_get_child_count(np); 2739 if (func->ngroups <= 0) 2740 return 0; 2741 2742 func->groups = devm_kcalloc(dev, func->ngroups, sizeof(*func->groups), GFP_KERNEL); 2743 if (!func->groups) 2744 return -ENOMEM; 2745 2746 for_each_child_of_node(np, child) { 2747 func->groups[i] = child->name; 2748 grp = &info->groups[grp_index++]; 2749 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++); 2750 if (ret) { 2751 of_node_put(child); 2752 return ret; 2753 } 2754 } 2755 2756 return 0; 2757 } 2758 2759 static int rockchip_pinctrl_parse_dt(struct platform_device *pdev, 2760 struct rockchip_pinctrl *info) 2761 { 2762 struct device *dev = &pdev->dev; 2763 struct device_node *np = dev->of_node; 2764 struct device_node *child; 2765 int ret; 2766 int i; 2767 2768 rockchip_pinctrl_child_count(info, np); 2769 2770 dev_dbg(dev, "nfunctions = %d\n", info->nfunctions); 2771 dev_dbg(dev, "ngroups = %d\n", info->ngroups); 2772 2773 info->functions = devm_kcalloc(dev, info->nfunctions, sizeof(*info->functions), GFP_KERNEL); 2774 if (!info->functions) 2775 return -ENOMEM; 2776 2777 info->groups = devm_kcalloc(dev, info->ngroups, sizeof(*info->groups), GFP_KERNEL); 2778 if (!info->groups) 2779 return -ENOMEM; 2780 2781 i = 0; 2782 2783 for_each_child_of_node(np, child) { 2784 if (of_match_node(rockchip_bank_match, child)) 2785 continue; 2786 2787 ret = rockchip_pinctrl_parse_functions(child, info, i++); 2788 if (ret) { 2789 dev_err(dev, "failed to parse function\n"); 2790 of_node_put(child); 2791 return ret; 2792 } 2793 } 2794 2795 return 0; 2796 } 2797 2798 static int rockchip_pinctrl_register(struct platform_device *pdev, 2799 struct rockchip_pinctrl *info) 2800 { 2801 struct pinctrl_desc *ctrldesc = &info->pctl; 2802 struct pinctrl_pin_desc *pindesc, *pdesc; 2803 struct rockchip_pin_bank *pin_bank; 2804 struct device *dev = &pdev->dev; 2805 char **pin_names; 2806 int pin, bank, ret; 2807 int k; 2808 2809 ctrldesc->name = "rockchip-pinctrl"; 2810 ctrldesc->owner = THIS_MODULE; 2811 ctrldesc->pctlops = &rockchip_pctrl_ops; 2812 ctrldesc->pmxops = &rockchip_pmx_ops; 2813 ctrldesc->confops = &rockchip_pinconf_ops; 2814 2815 pindesc = devm_kcalloc(dev, info->ctrl->nr_pins, sizeof(*pindesc), GFP_KERNEL); 2816 if (!pindesc) 2817 return -ENOMEM; 2818 2819 ctrldesc->pins = pindesc; 2820 ctrldesc->npins = info->ctrl->nr_pins; 2821 2822 pdesc = pindesc; 2823 for (bank = 0, k = 0; bank < info->ctrl->nr_banks; bank++) { 2824 pin_bank = &info->ctrl->pin_banks[bank]; 2825 2826 pin_names = devm_kasprintf_strarray(dev, pin_bank->name, pin_bank->nr_pins); 2827 if (IS_ERR(pin_names)) 2828 return PTR_ERR(pin_names); 2829 2830 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) { 2831 pdesc->number = k; 2832 pdesc->name = pin_names[pin]; 2833 pdesc++; 2834 } 2835 2836 INIT_LIST_HEAD(&pin_bank->deferred_pins); 2837 mutex_init(&pin_bank->deferred_lock); 2838 } 2839 2840 ret = rockchip_pinctrl_parse_dt(pdev, info); 2841 if (ret) 2842 return ret; 2843 2844 info->pctl_dev = devm_pinctrl_register(dev, ctrldesc, info); 2845 if (IS_ERR(info->pctl_dev)) 2846 return dev_err_probe(dev, PTR_ERR(info->pctl_dev), "could not register pinctrl driver\n"); 2847 2848 return 0; 2849 } 2850 2851 static const struct of_device_id rockchip_pinctrl_dt_match[]; 2852 2853 /* retrieve the soc specific data */ 2854 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data( 2855 struct rockchip_pinctrl *d, 2856 struct platform_device *pdev) 2857 { 2858 struct device *dev = &pdev->dev; 2859 struct device_node *node = dev->of_node; 2860 const struct of_device_id *match; 2861 struct rockchip_pin_ctrl *ctrl; 2862 struct rockchip_pin_bank *bank; 2863 int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j; 2864 2865 match = of_match_node(rockchip_pinctrl_dt_match, node); 2866 ctrl = (struct rockchip_pin_ctrl *)match->data; 2867 2868 grf_offs = ctrl->grf_mux_offset; 2869 pmu_offs = ctrl->pmu_mux_offset; 2870 drv_pmu_offs = ctrl->pmu_drv_offset; 2871 drv_grf_offs = ctrl->grf_drv_offset; 2872 bank = ctrl->pin_banks; 2873 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 2874 int bank_pins = 0; 2875 2876 raw_spin_lock_init(&bank->slock); 2877 bank->drvdata = d; 2878 bank->pin_base = ctrl->nr_pins; 2879 ctrl->nr_pins += bank->nr_pins; 2880 2881 /* calculate iomux and drv offsets */ 2882 for (j = 0; j < 4; j++) { 2883 struct rockchip_iomux *iom = &bank->iomux[j]; 2884 struct rockchip_drv *drv = &bank->drv[j]; 2885 int inc; 2886 2887 if (bank_pins >= bank->nr_pins) 2888 break; 2889 2890 /* preset iomux offset value, set new start value */ 2891 if (iom->offset >= 0) { 2892 if (iom->type & IOMUX_SOURCE_PMU) 2893 pmu_offs = iom->offset; 2894 else 2895 grf_offs = iom->offset; 2896 } else { /* set current iomux offset */ 2897 iom->offset = (iom->type & IOMUX_SOURCE_PMU) ? 2898 pmu_offs : grf_offs; 2899 } 2900 2901 /* preset drv offset value, set new start value */ 2902 if (drv->offset >= 0) { 2903 if (iom->type & IOMUX_SOURCE_PMU) 2904 drv_pmu_offs = drv->offset; 2905 else 2906 drv_grf_offs = drv->offset; 2907 } else { /* set current drv offset */ 2908 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ? 2909 drv_pmu_offs : drv_grf_offs; 2910 } 2911 2912 dev_dbg(dev, "bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n", 2913 i, j, iom->offset, drv->offset); 2914 2915 /* 2916 * Increase offset according to iomux width. 2917 * 4bit iomux'es are spread over two registers. 2918 */ 2919 inc = (iom->type & (IOMUX_WIDTH_4BIT | 2920 IOMUX_WIDTH_3BIT | 2921 IOMUX_WIDTH_2BIT)) ? 8 : 4; 2922 if (iom->type & IOMUX_SOURCE_PMU) 2923 pmu_offs += inc; 2924 else 2925 grf_offs += inc; 2926 2927 /* 2928 * Increase offset according to drv width. 2929 * 3bit drive-strenth'es are spread over two registers. 2930 */ 2931 if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) || 2932 (drv->drv_type == DRV_TYPE_IO_3V3_ONLY)) 2933 inc = 8; 2934 else 2935 inc = 4; 2936 2937 if (iom->type & IOMUX_SOURCE_PMU) 2938 drv_pmu_offs += inc; 2939 else 2940 drv_grf_offs += inc; 2941 2942 bank_pins += 8; 2943 } 2944 2945 /* calculate the per-bank recalced_mask */ 2946 for (j = 0; j < ctrl->niomux_recalced; j++) { 2947 int pin = 0; 2948 2949 if (ctrl->iomux_recalced[j].num == bank->bank_num) { 2950 pin = ctrl->iomux_recalced[j].pin; 2951 bank->recalced_mask |= BIT(pin); 2952 } 2953 } 2954 2955 /* calculate the per-bank route_mask */ 2956 for (j = 0; j < ctrl->niomux_routes; j++) { 2957 int pin = 0; 2958 2959 if (ctrl->iomux_routes[j].bank_num == bank->bank_num) { 2960 pin = ctrl->iomux_routes[j].pin; 2961 bank->route_mask |= BIT(pin); 2962 } 2963 } 2964 } 2965 2966 return ctrl; 2967 } 2968 2969 #define RK3288_GRF_GPIO6C_IOMUX 0x64 2970 #define GPIO6C6_SEL_WRITE_ENABLE BIT(28) 2971 2972 static u32 rk3288_grf_gpio6c_iomux; 2973 2974 static int __maybe_unused rockchip_pinctrl_suspend(struct device *dev) 2975 { 2976 struct rockchip_pinctrl *info = dev_get_drvdata(dev); 2977 int ret = pinctrl_force_sleep(info->pctl_dev); 2978 2979 if (ret) 2980 return ret; 2981 2982 /* 2983 * RK3288 GPIO6_C6 mux would be modified by Maskrom when resume, so save 2984 * the setting here, and restore it at resume. 2985 */ 2986 if (info->ctrl->type == RK3288) { 2987 ret = regmap_read(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX, 2988 &rk3288_grf_gpio6c_iomux); 2989 if (ret) { 2990 pinctrl_force_default(info->pctl_dev); 2991 return ret; 2992 } 2993 } 2994 2995 return 0; 2996 } 2997 2998 static int __maybe_unused rockchip_pinctrl_resume(struct device *dev) 2999 { 3000 struct rockchip_pinctrl *info = dev_get_drvdata(dev); 3001 int ret; 3002 3003 if (info->ctrl->type == RK3288) { 3004 ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX, 3005 rk3288_grf_gpio6c_iomux | 3006 GPIO6C6_SEL_WRITE_ENABLE); 3007 if (ret) 3008 return ret; 3009 } 3010 3011 return pinctrl_force_default(info->pctl_dev); 3012 } 3013 3014 static SIMPLE_DEV_PM_OPS(rockchip_pinctrl_dev_pm_ops, rockchip_pinctrl_suspend, 3015 rockchip_pinctrl_resume); 3016 3017 static int rockchip_pinctrl_probe(struct platform_device *pdev) 3018 { 3019 struct rockchip_pinctrl *info; 3020 struct device *dev = &pdev->dev; 3021 struct device_node *np = dev->of_node, *node; 3022 struct rockchip_pin_ctrl *ctrl; 3023 struct resource *res; 3024 void __iomem *base; 3025 int ret; 3026 3027 if (!dev->of_node) 3028 return dev_err_probe(dev, -ENODEV, "device tree node not found\n"); 3029 3030 info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL); 3031 if (!info) 3032 return -ENOMEM; 3033 3034 info->dev = dev; 3035 3036 ctrl = rockchip_pinctrl_get_soc_data(info, pdev); 3037 if (!ctrl) 3038 return dev_err_probe(dev, -EINVAL, "driver data not available\n"); 3039 info->ctrl = ctrl; 3040 3041 node = of_parse_phandle(np, "rockchip,grf", 0); 3042 if (node) { 3043 info->regmap_base = syscon_node_to_regmap(node); 3044 of_node_put(node); 3045 if (IS_ERR(info->regmap_base)) 3046 return PTR_ERR(info->regmap_base); 3047 } else { 3048 base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 3049 if (IS_ERR(base)) 3050 return PTR_ERR(base); 3051 3052 rockchip_regmap_config.max_register = resource_size(res) - 4; 3053 rockchip_regmap_config.name = "rockchip,pinctrl"; 3054 info->regmap_base = 3055 devm_regmap_init_mmio(dev, base, &rockchip_regmap_config); 3056 3057 /* to check for the old dt-bindings */ 3058 info->reg_size = resource_size(res); 3059 3060 /* Honor the old binding, with pull registers as 2nd resource */ 3061 if (ctrl->type == RK3188 && info->reg_size < 0x200) { 3062 base = devm_platform_get_and_ioremap_resource(pdev, 1, &res); 3063 if (IS_ERR(base)) 3064 return PTR_ERR(base); 3065 3066 rockchip_regmap_config.max_register = resource_size(res) - 4; 3067 rockchip_regmap_config.name = "rockchip,pinctrl-pull"; 3068 info->regmap_pull = 3069 devm_regmap_init_mmio(dev, base, &rockchip_regmap_config); 3070 } 3071 } 3072 3073 /* try to find the optional reference to the pmu syscon */ 3074 node = of_parse_phandle(np, "rockchip,pmu", 0); 3075 if (node) { 3076 info->regmap_pmu = syscon_node_to_regmap(node); 3077 of_node_put(node); 3078 if (IS_ERR(info->regmap_pmu)) 3079 return PTR_ERR(info->regmap_pmu); 3080 } 3081 3082 ret = rockchip_pinctrl_register(pdev, info); 3083 if (ret) 3084 return ret; 3085 3086 platform_set_drvdata(pdev, info); 3087 3088 ret = of_platform_populate(np, NULL, NULL, &pdev->dev); 3089 if (ret) 3090 return dev_err_probe(dev, ret, "failed to register gpio device\n"); 3091 3092 return 0; 3093 } 3094 3095 static int rockchip_pinctrl_remove(struct platform_device *pdev) 3096 { 3097 struct rockchip_pinctrl *info = platform_get_drvdata(pdev); 3098 struct rockchip_pin_bank *bank; 3099 struct rockchip_pin_deferred *cfg; 3100 int i; 3101 3102 of_platform_depopulate(&pdev->dev); 3103 3104 for (i = 0; i < info->ctrl->nr_banks; i++) { 3105 bank = &info->ctrl->pin_banks[i]; 3106 3107 mutex_lock(&bank->deferred_lock); 3108 while (!list_empty(&bank->deferred_pins)) { 3109 cfg = list_first_entry(&bank->deferred_pins, 3110 struct rockchip_pin_deferred, head); 3111 list_del(&cfg->head); 3112 kfree(cfg); 3113 } 3114 mutex_unlock(&bank->deferred_lock); 3115 } 3116 3117 return 0; 3118 } 3119 3120 static struct rockchip_pin_bank px30_pin_banks[] = { 3121 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, 3122 IOMUX_SOURCE_PMU, 3123 IOMUX_SOURCE_PMU, 3124 IOMUX_SOURCE_PMU 3125 ), 3126 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT, 3127 IOMUX_WIDTH_4BIT, 3128 IOMUX_WIDTH_4BIT, 3129 IOMUX_WIDTH_4BIT 3130 ), 3131 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT, 3132 IOMUX_WIDTH_4BIT, 3133 IOMUX_WIDTH_4BIT, 3134 IOMUX_WIDTH_4BIT 3135 ), 3136 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT, 3137 IOMUX_WIDTH_4BIT, 3138 IOMUX_WIDTH_4BIT, 3139 IOMUX_WIDTH_4BIT 3140 ), 3141 }; 3142 3143 static struct rockchip_pin_ctrl px30_pin_ctrl = { 3144 .pin_banks = px30_pin_banks, 3145 .nr_banks = ARRAY_SIZE(px30_pin_banks), 3146 .label = "PX30-GPIO", 3147 .type = PX30, 3148 .grf_mux_offset = 0x0, 3149 .pmu_mux_offset = 0x0, 3150 .iomux_routes = px30_mux_route_data, 3151 .niomux_routes = ARRAY_SIZE(px30_mux_route_data), 3152 .pull_calc_reg = px30_calc_pull_reg_and_bit, 3153 .drv_calc_reg = px30_calc_drv_reg_and_bit, 3154 .schmitt_calc_reg = px30_calc_schmitt_reg_and_bit, 3155 }; 3156 3157 static struct rockchip_pin_bank rv1108_pin_banks[] = { 3158 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, 3159 IOMUX_SOURCE_PMU, 3160 IOMUX_SOURCE_PMU, 3161 IOMUX_SOURCE_PMU), 3162 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0), 3163 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0), 3164 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0), 3165 }; 3166 3167 static struct rockchip_pin_ctrl rv1108_pin_ctrl = { 3168 .pin_banks = rv1108_pin_banks, 3169 .nr_banks = ARRAY_SIZE(rv1108_pin_banks), 3170 .label = "RV1108-GPIO", 3171 .type = RV1108, 3172 .grf_mux_offset = 0x10, 3173 .pmu_mux_offset = 0x0, 3174 .iomux_recalced = rv1108_mux_recalced_data, 3175 .niomux_recalced = ARRAY_SIZE(rv1108_mux_recalced_data), 3176 .pull_calc_reg = rv1108_calc_pull_reg_and_bit, 3177 .drv_calc_reg = rv1108_calc_drv_reg_and_bit, 3178 .schmitt_calc_reg = rv1108_calc_schmitt_reg_and_bit, 3179 }; 3180 3181 static struct rockchip_pin_bank rk2928_pin_banks[] = { 3182 PIN_BANK(0, 32, "gpio0"), 3183 PIN_BANK(1, 32, "gpio1"), 3184 PIN_BANK(2, 32, "gpio2"), 3185 PIN_BANK(3, 32, "gpio3"), 3186 }; 3187 3188 static struct rockchip_pin_ctrl rk2928_pin_ctrl = { 3189 .pin_banks = rk2928_pin_banks, 3190 .nr_banks = ARRAY_SIZE(rk2928_pin_banks), 3191 .label = "RK2928-GPIO", 3192 .type = RK2928, 3193 .grf_mux_offset = 0xa8, 3194 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 3195 }; 3196 3197 static struct rockchip_pin_bank rk3036_pin_banks[] = { 3198 PIN_BANK(0, 32, "gpio0"), 3199 PIN_BANK(1, 32, "gpio1"), 3200 PIN_BANK(2, 32, "gpio2"), 3201 }; 3202 3203 static struct rockchip_pin_ctrl rk3036_pin_ctrl = { 3204 .pin_banks = rk3036_pin_banks, 3205 .nr_banks = ARRAY_SIZE(rk3036_pin_banks), 3206 .label = "RK3036-GPIO", 3207 .type = RK2928, 3208 .grf_mux_offset = 0xa8, 3209 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 3210 }; 3211 3212 static struct rockchip_pin_bank rk3066a_pin_banks[] = { 3213 PIN_BANK(0, 32, "gpio0"), 3214 PIN_BANK(1, 32, "gpio1"), 3215 PIN_BANK(2, 32, "gpio2"), 3216 PIN_BANK(3, 32, "gpio3"), 3217 PIN_BANK(4, 32, "gpio4"), 3218 PIN_BANK(6, 16, "gpio6"), 3219 }; 3220 3221 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = { 3222 .pin_banks = rk3066a_pin_banks, 3223 .nr_banks = ARRAY_SIZE(rk3066a_pin_banks), 3224 .label = "RK3066a-GPIO", 3225 .type = RK2928, 3226 .grf_mux_offset = 0xa8, 3227 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 3228 }; 3229 3230 static struct rockchip_pin_bank rk3066b_pin_banks[] = { 3231 PIN_BANK(0, 32, "gpio0"), 3232 PIN_BANK(1, 32, "gpio1"), 3233 PIN_BANK(2, 32, "gpio2"), 3234 PIN_BANK(3, 32, "gpio3"), 3235 }; 3236 3237 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = { 3238 .pin_banks = rk3066b_pin_banks, 3239 .nr_banks = ARRAY_SIZE(rk3066b_pin_banks), 3240 .label = "RK3066b-GPIO", 3241 .type = RK3066B, 3242 .grf_mux_offset = 0x60, 3243 }; 3244 3245 static struct rockchip_pin_bank rk3128_pin_banks[] = { 3246 PIN_BANK(0, 32, "gpio0"), 3247 PIN_BANK(1, 32, "gpio1"), 3248 PIN_BANK(2, 32, "gpio2"), 3249 PIN_BANK(3, 32, "gpio3"), 3250 }; 3251 3252 static struct rockchip_pin_ctrl rk3128_pin_ctrl = { 3253 .pin_banks = rk3128_pin_banks, 3254 .nr_banks = ARRAY_SIZE(rk3128_pin_banks), 3255 .label = "RK3128-GPIO", 3256 .type = RK3128, 3257 .grf_mux_offset = 0xa8, 3258 .iomux_recalced = rk3128_mux_recalced_data, 3259 .niomux_recalced = ARRAY_SIZE(rk3128_mux_recalced_data), 3260 .iomux_routes = rk3128_mux_route_data, 3261 .niomux_routes = ARRAY_SIZE(rk3128_mux_route_data), 3262 .pull_calc_reg = rk3128_calc_pull_reg_and_bit, 3263 }; 3264 3265 static struct rockchip_pin_bank rk3188_pin_banks[] = { 3266 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0), 3267 PIN_BANK(1, 32, "gpio1"), 3268 PIN_BANK(2, 32, "gpio2"), 3269 PIN_BANK(3, 32, "gpio3"), 3270 }; 3271 3272 static struct rockchip_pin_ctrl rk3188_pin_ctrl = { 3273 .pin_banks = rk3188_pin_banks, 3274 .nr_banks = ARRAY_SIZE(rk3188_pin_banks), 3275 .label = "RK3188-GPIO", 3276 .type = RK3188, 3277 .grf_mux_offset = 0x60, 3278 .iomux_routes = rk3188_mux_route_data, 3279 .niomux_routes = ARRAY_SIZE(rk3188_mux_route_data), 3280 .pull_calc_reg = rk3188_calc_pull_reg_and_bit, 3281 }; 3282 3283 static struct rockchip_pin_bank rk3228_pin_banks[] = { 3284 PIN_BANK(0, 32, "gpio0"), 3285 PIN_BANK(1, 32, "gpio1"), 3286 PIN_BANK(2, 32, "gpio2"), 3287 PIN_BANK(3, 32, "gpio3"), 3288 }; 3289 3290 static struct rockchip_pin_ctrl rk3228_pin_ctrl = { 3291 .pin_banks = rk3228_pin_banks, 3292 .nr_banks = ARRAY_SIZE(rk3228_pin_banks), 3293 .label = "RK3228-GPIO", 3294 .type = RK3288, 3295 .grf_mux_offset = 0x0, 3296 .iomux_routes = rk3228_mux_route_data, 3297 .niomux_routes = ARRAY_SIZE(rk3228_mux_route_data), 3298 .pull_calc_reg = rk3228_calc_pull_reg_and_bit, 3299 .drv_calc_reg = rk3228_calc_drv_reg_and_bit, 3300 }; 3301 3302 static struct rockchip_pin_bank rk3288_pin_banks[] = { 3303 PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU, 3304 IOMUX_SOURCE_PMU, 3305 IOMUX_SOURCE_PMU, 3306 IOMUX_UNROUTED 3307 ), 3308 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED, 3309 IOMUX_UNROUTED, 3310 IOMUX_UNROUTED, 3311 0 3312 ), 3313 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED), 3314 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT), 3315 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT, 3316 IOMUX_WIDTH_4BIT, 3317 0, 3318 0 3319 ), 3320 PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED, 3321 0, 3322 0, 3323 IOMUX_UNROUTED 3324 ), 3325 PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED), 3326 PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0, 3327 0, 3328 IOMUX_WIDTH_4BIT, 3329 IOMUX_UNROUTED 3330 ), 3331 PIN_BANK(8, 16, "gpio8"), 3332 }; 3333 3334 static struct rockchip_pin_ctrl rk3288_pin_ctrl = { 3335 .pin_banks = rk3288_pin_banks, 3336 .nr_banks = ARRAY_SIZE(rk3288_pin_banks), 3337 .label = "RK3288-GPIO", 3338 .type = RK3288, 3339 .grf_mux_offset = 0x0, 3340 .pmu_mux_offset = 0x84, 3341 .iomux_routes = rk3288_mux_route_data, 3342 .niomux_routes = ARRAY_SIZE(rk3288_mux_route_data), 3343 .pull_calc_reg = rk3288_calc_pull_reg_and_bit, 3344 .drv_calc_reg = rk3288_calc_drv_reg_and_bit, 3345 }; 3346 3347 static struct rockchip_pin_bank rk3308_pin_banks[] = { 3348 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_WIDTH_2BIT, 3349 IOMUX_WIDTH_2BIT, 3350 IOMUX_WIDTH_2BIT, 3351 IOMUX_WIDTH_2BIT), 3352 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_2BIT, 3353 IOMUX_WIDTH_2BIT, 3354 IOMUX_WIDTH_2BIT, 3355 IOMUX_WIDTH_2BIT), 3356 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_2BIT, 3357 IOMUX_WIDTH_2BIT, 3358 IOMUX_WIDTH_2BIT, 3359 IOMUX_WIDTH_2BIT), 3360 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_2BIT, 3361 IOMUX_WIDTH_2BIT, 3362 IOMUX_WIDTH_2BIT, 3363 IOMUX_WIDTH_2BIT), 3364 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_2BIT, 3365 IOMUX_WIDTH_2BIT, 3366 IOMUX_WIDTH_2BIT, 3367 IOMUX_WIDTH_2BIT), 3368 }; 3369 3370 static struct rockchip_pin_ctrl rk3308_pin_ctrl = { 3371 .pin_banks = rk3308_pin_banks, 3372 .nr_banks = ARRAY_SIZE(rk3308_pin_banks), 3373 .label = "RK3308-GPIO", 3374 .type = RK3308, 3375 .grf_mux_offset = 0x0, 3376 .iomux_recalced = rk3308_mux_recalced_data, 3377 .niomux_recalced = ARRAY_SIZE(rk3308_mux_recalced_data), 3378 .iomux_routes = rk3308_mux_route_data, 3379 .niomux_routes = ARRAY_SIZE(rk3308_mux_route_data), 3380 .pull_calc_reg = rk3308_calc_pull_reg_and_bit, 3381 .drv_calc_reg = rk3308_calc_drv_reg_and_bit, 3382 .schmitt_calc_reg = rk3308_calc_schmitt_reg_and_bit, 3383 }; 3384 3385 static struct rockchip_pin_bank rk3328_pin_banks[] = { 3386 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0), 3387 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0), 3388 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 3389 IOMUX_WIDTH_3BIT, 3390 IOMUX_WIDTH_3BIT, 3391 0), 3392 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 3393 IOMUX_WIDTH_3BIT, 3394 IOMUX_WIDTH_3BIT, 3395 0, 3396 0), 3397 }; 3398 3399 static struct rockchip_pin_ctrl rk3328_pin_ctrl = { 3400 .pin_banks = rk3328_pin_banks, 3401 .nr_banks = ARRAY_SIZE(rk3328_pin_banks), 3402 .label = "RK3328-GPIO", 3403 .type = RK3288, 3404 .grf_mux_offset = 0x0, 3405 .iomux_recalced = rk3328_mux_recalced_data, 3406 .niomux_recalced = ARRAY_SIZE(rk3328_mux_recalced_data), 3407 .iomux_routes = rk3328_mux_route_data, 3408 .niomux_routes = ARRAY_SIZE(rk3328_mux_route_data), 3409 .pull_calc_reg = rk3228_calc_pull_reg_and_bit, 3410 .drv_calc_reg = rk3228_calc_drv_reg_and_bit, 3411 .schmitt_calc_reg = rk3328_calc_schmitt_reg_and_bit, 3412 }; 3413 3414 static struct rockchip_pin_bank rk3368_pin_banks[] = { 3415 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, 3416 IOMUX_SOURCE_PMU, 3417 IOMUX_SOURCE_PMU, 3418 IOMUX_SOURCE_PMU 3419 ), 3420 PIN_BANK(1, 32, "gpio1"), 3421 PIN_BANK(2, 32, "gpio2"), 3422 PIN_BANK(3, 32, "gpio3"), 3423 }; 3424 3425 static struct rockchip_pin_ctrl rk3368_pin_ctrl = { 3426 .pin_banks = rk3368_pin_banks, 3427 .nr_banks = ARRAY_SIZE(rk3368_pin_banks), 3428 .label = "RK3368-GPIO", 3429 .type = RK3368, 3430 .grf_mux_offset = 0x0, 3431 .pmu_mux_offset = 0x0, 3432 .pull_calc_reg = rk3368_calc_pull_reg_and_bit, 3433 .drv_calc_reg = rk3368_calc_drv_reg_and_bit, 3434 }; 3435 3436 static struct rockchip_pin_bank rk3399_pin_banks[] = { 3437 PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0", 3438 IOMUX_SOURCE_PMU, 3439 IOMUX_SOURCE_PMU, 3440 IOMUX_SOURCE_PMU, 3441 IOMUX_SOURCE_PMU, 3442 DRV_TYPE_IO_1V8_ONLY, 3443 DRV_TYPE_IO_1V8_ONLY, 3444 DRV_TYPE_IO_DEFAULT, 3445 DRV_TYPE_IO_DEFAULT, 3446 0x80, 3447 0x88, 3448 -1, 3449 -1, 3450 PULL_TYPE_IO_1V8_ONLY, 3451 PULL_TYPE_IO_1V8_ONLY, 3452 PULL_TYPE_IO_DEFAULT, 3453 PULL_TYPE_IO_DEFAULT 3454 ), 3455 PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU, 3456 IOMUX_SOURCE_PMU, 3457 IOMUX_SOURCE_PMU, 3458 IOMUX_SOURCE_PMU, 3459 DRV_TYPE_IO_1V8_OR_3V0, 3460 DRV_TYPE_IO_1V8_OR_3V0, 3461 DRV_TYPE_IO_1V8_OR_3V0, 3462 DRV_TYPE_IO_1V8_OR_3V0, 3463 0xa0, 3464 0xa8, 3465 0xb0, 3466 0xb8 3467 ), 3468 PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0, 3469 DRV_TYPE_IO_1V8_OR_3V0, 3470 DRV_TYPE_IO_1V8_ONLY, 3471 DRV_TYPE_IO_1V8_ONLY, 3472 PULL_TYPE_IO_DEFAULT, 3473 PULL_TYPE_IO_DEFAULT, 3474 PULL_TYPE_IO_1V8_ONLY, 3475 PULL_TYPE_IO_1V8_ONLY 3476 ), 3477 PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY, 3478 DRV_TYPE_IO_3V3_ONLY, 3479 DRV_TYPE_IO_3V3_ONLY, 3480 DRV_TYPE_IO_1V8_OR_3V0 3481 ), 3482 PIN_BANK_DRV_FLAGS(4, 32, "gpio4", DRV_TYPE_IO_1V8_OR_3V0, 3483 DRV_TYPE_IO_1V8_3V0_AUTO, 3484 DRV_TYPE_IO_1V8_OR_3V0, 3485 DRV_TYPE_IO_1V8_OR_3V0 3486 ), 3487 }; 3488 3489 static struct rockchip_pin_ctrl rk3399_pin_ctrl = { 3490 .pin_banks = rk3399_pin_banks, 3491 .nr_banks = ARRAY_SIZE(rk3399_pin_banks), 3492 .label = "RK3399-GPIO", 3493 .type = RK3399, 3494 .grf_mux_offset = 0xe000, 3495 .pmu_mux_offset = 0x0, 3496 .grf_drv_offset = 0xe100, 3497 .pmu_drv_offset = 0x80, 3498 .iomux_routes = rk3399_mux_route_data, 3499 .niomux_routes = ARRAY_SIZE(rk3399_mux_route_data), 3500 .pull_calc_reg = rk3399_calc_pull_reg_and_bit, 3501 .drv_calc_reg = rk3399_calc_drv_reg_and_bit, 3502 }; 3503 3504 static struct rockchip_pin_bank rk3568_pin_banks[] = { 3505 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT, 3506 IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT, 3507 IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT, 3508 IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT), 3509 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT, 3510 IOMUX_WIDTH_4BIT, 3511 IOMUX_WIDTH_4BIT, 3512 IOMUX_WIDTH_4BIT), 3513 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT, 3514 IOMUX_WIDTH_4BIT, 3515 IOMUX_WIDTH_4BIT, 3516 IOMUX_WIDTH_4BIT), 3517 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT, 3518 IOMUX_WIDTH_4BIT, 3519 IOMUX_WIDTH_4BIT, 3520 IOMUX_WIDTH_4BIT), 3521 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT, 3522 IOMUX_WIDTH_4BIT, 3523 IOMUX_WIDTH_4BIT, 3524 IOMUX_WIDTH_4BIT), 3525 }; 3526 3527 static struct rockchip_pin_ctrl rk3568_pin_ctrl = { 3528 .pin_banks = rk3568_pin_banks, 3529 .nr_banks = ARRAY_SIZE(rk3568_pin_banks), 3530 .label = "RK3568-GPIO", 3531 .type = RK3568, 3532 .grf_mux_offset = 0x0, 3533 .pmu_mux_offset = 0x0, 3534 .grf_drv_offset = 0x0200, 3535 .pmu_drv_offset = 0x0070, 3536 .iomux_routes = rk3568_mux_route_data, 3537 .niomux_routes = ARRAY_SIZE(rk3568_mux_route_data), 3538 .pull_calc_reg = rk3568_calc_pull_reg_and_bit, 3539 .drv_calc_reg = rk3568_calc_drv_reg_and_bit, 3540 .schmitt_calc_reg = rk3568_calc_schmitt_reg_and_bit, 3541 }; 3542 3543 static struct rockchip_pin_bank rk3588_pin_banks[] = { 3544 RK3588_PIN_BANK_FLAGS(0, 32, "gpio0", 3545 IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY), 3546 RK3588_PIN_BANK_FLAGS(1, 32, "gpio1", 3547 IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY), 3548 RK3588_PIN_BANK_FLAGS(2, 32, "gpio2", 3549 IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY), 3550 RK3588_PIN_BANK_FLAGS(3, 32, "gpio3", 3551 IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY), 3552 RK3588_PIN_BANK_FLAGS(4, 32, "gpio4", 3553 IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY), 3554 }; 3555 3556 static struct rockchip_pin_ctrl rk3588_pin_ctrl = { 3557 .pin_banks = rk3588_pin_banks, 3558 .nr_banks = ARRAY_SIZE(rk3588_pin_banks), 3559 .label = "RK3588-GPIO", 3560 .type = RK3588, 3561 .pull_calc_reg = rk3588_calc_pull_reg_and_bit, 3562 .drv_calc_reg = rk3588_calc_drv_reg_and_bit, 3563 .schmitt_calc_reg = rk3588_calc_schmitt_reg_and_bit, 3564 }; 3565 3566 static const struct of_device_id rockchip_pinctrl_dt_match[] = { 3567 { .compatible = "rockchip,px30-pinctrl", 3568 .data = &px30_pin_ctrl }, 3569 { .compatible = "rockchip,rv1108-pinctrl", 3570 .data = &rv1108_pin_ctrl }, 3571 { .compatible = "rockchip,rk2928-pinctrl", 3572 .data = &rk2928_pin_ctrl }, 3573 { .compatible = "rockchip,rk3036-pinctrl", 3574 .data = &rk3036_pin_ctrl }, 3575 { .compatible = "rockchip,rk3066a-pinctrl", 3576 .data = &rk3066a_pin_ctrl }, 3577 { .compatible = "rockchip,rk3066b-pinctrl", 3578 .data = &rk3066b_pin_ctrl }, 3579 { .compatible = "rockchip,rk3128-pinctrl", 3580 .data = (void *)&rk3128_pin_ctrl }, 3581 { .compatible = "rockchip,rk3188-pinctrl", 3582 .data = &rk3188_pin_ctrl }, 3583 { .compatible = "rockchip,rk3228-pinctrl", 3584 .data = &rk3228_pin_ctrl }, 3585 { .compatible = "rockchip,rk3288-pinctrl", 3586 .data = &rk3288_pin_ctrl }, 3587 { .compatible = "rockchip,rk3308-pinctrl", 3588 .data = &rk3308_pin_ctrl }, 3589 { .compatible = "rockchip,rk3328-pinctrl", 3590 .data = &rk3328_pin_ctrl }, 3591 { .compatible = "rockchip,rk3368-pinctrl", 3592 .data = &rk3368_pin_ctrl }, 3593 { .compatible = "rockchip,rk3399-pinctrl", 3594 .data = &rk3399_pin_ctrl }, 3595 { .compatible = "rockchip,rk3568-pinctrl", 3596 .data = &rk3568_pin_ctrl }, 3597 { .compatible = "rockchip,rk3588-pinctrl", 3598 .data = &rk3588_pin_ctrl }, 3599 {}, 3600 }; 3601 3602 static struct platform_driver rockchip_pinctrl_driver = { 3603 .probe = rockchip_pinctrl_probe, 3604 .remove = rockchip_pinctrl_remove, 3605 .driver = { 3606 .name = "rockchip-pinctrl", 3607 .pm = &rockchip_pinctrl_dev_pm_ops, 3608 .of_match_table = rockchip_pinctrl_dt_match, 3609 }, 3610 }; 3611 3612 static int __init rockchip_pinctrl_drv_register(void) 3613 { 3614 return platform_driver_register(&rockchip_pinctrl_driver); 3615 } 3616 postcore_initcall(rockchip_pinctrl_drv_register); 3617 3618 static void __exit rockchip_pinctrl_drv_unregister(void) 3619 { 3620 platform_driver_unregister(&rockchip_pinctrl_driver); 3621 } 3622 module_exit(rockchip_pinctrl_drv_unregister); 3623 3624 MODULE_DESCRIPTION("ROCKCHIP Pin Controller Driver"); 3625 MODULE_LICENSE("GPL"); 3626 MODULE_ALIAS("platform:pinctrl-rockchip"); 3627 MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match); 3628