1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Pinctrl driver for Rockchip SoCs 4 * 5 * Copyright (c) 2013 MundoReader S.L. 6 * Author: Heiko Stuebner <heiko@sntech.de> 7 * 8 * With some ideas taken from pinctrl-samsung: 9 * Copyright (c) 2012 Samsung Electronics Co., Ltd. 10 * http://www.samsung.com 11 * Copyright (c) 2012 Linaro Ltd 12 * https://www.linaro.org 13 * 14 * and pinctrl-at91: 15 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> 16 */ 17 18 #include <linux/init.h> 19 #include <linux/module.h> 20 #include <linux/platform_device.h> 21 #include <linux/io.h> 22 #include <linux/bitops.h> 23 #include <linux/gpio/driver.h> 24 #include <linux/of.h> 25 #include <linux/of_platform.h> 26 #include <linux/pinctrl/machine.h> 27 #include <linux/pinctrl/pinconf.h> 28 #include <linux/pinctrl/pinctrl.h> 29 #include <linux/pinctrl/pinmux.h> 30 #include <linux/pinctrl/pinconf-generic.h> 31 #include <linux/irqchip/chained_irq.h> 32 #include <linux/clk.h> 33 #include <linux/regmap.h> 34 #include <linux/mfd/syscon.h> 35 #include <linux/string_helpers.h> 36 37 #include <dt-bindings/pinctrl/rockchip.h> 38 39 #include "core.h" 40 #include "pinconf.h" 41 #include "pinctrl-rockchip.h" 42 43 /* 44 * Generate a bitmask for setting a value (v) with a write mask bit in hiword 45 * register 31:16 area. 46 */ 47 #define WRITE_MASK_VAL(h, l, v) \ 48 (GENMASK(((h) + 16), ((l) + 16)) | (((v) << (l)) & GENMASK((h), (l)))) 49 50 /* 51 * Encode variants of iomux registers into a type variable 52 */ 53 #define IOMUX_GPIO_ONLY BIT(0) 54 #define IOMUX_WIDTH_4BIT BIT(1) 55 #define IOMUX_SOURCE_PMU BIT(2) 56 #define IOMUX_UNROUTED BIT(3) 57 #define IOMUX_WIDTH_3BIT BIT(4) 58 #define IOMUX_WIDTH_2BIT BIT(5) 59 #define IOMUX_L_SOURCE_PMU BIT(6) 60 61 #define PIN_BANK(id, pins, label) \ 62 { \ 63 .bank_num = id, \ 64 .nr_pins = pins, \ 65 .name = label, \ 66 .iomux = { \ 67 { .offset = -1 }, \ 68 { .offset = -1 }, \ 69 { .offset = -1 }, \ 70 { .offset = -1 }, \ 71 }, \ 72 } 73 74 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \ 75 { \ 76 .bank_num = id, \ 77 .nr_pins = pins, \ 78 .name = label, \ 79 .iomux = { \ 80 { .type = iom0, .offset = -1 }, \ 81 { .type = iom1, .offset = -1 }, \ 82 { .type = iom2, .offset = -1 }, \ 83 { .type = iom3, .offset = -1 }, \ 84 }, \ 85 } 86 87 #define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \ 88 { \ 89 .bank_num = id, \ 90 .nr_pins = pins, \ 91 .name = label, \ 92 .iomux = { \ 93 { .offset = -1 }, \ 94 { .offset = -1 }, \ 95 { .offset = -1 }, \ 96 { .offset = -1 }, \ 97 }, \ 98 .drv = { \ 99 { .drv_type = type0, .offset = -1 }, \ 100 { .drv_type = type1, .offset = -1 }, \ 101 { .drv_type = type2, .offset = -1 }, \ 102 { .drv_type = type3, .offset = -1 }, \ 103 }, \ 104 } 105 106 #define PIN_BANK_IOMUX_FLAGS_PULL_FLAGS(id, pins, label, iom0, iom1, \ 107 iom2, iom3, pull0, pull1, \ 108 pull2, pull3) \ 109 { \ 110 .bank_num = id, \ 111 .nr_pins = pins, \ 112 .name = label, \ 113 .iomux = { \ 114 { .type = iom0, .offset = -1 }, \ 115 { .type = iom1, .offset = -1 }, \ 116 { .type = iom2, .offset = -1 }, \ 117 { .type = iom3, .offset = -1 }, \ 118 }, \ 119 .pull_type[0] = pull0, \ 120 .pull_type[1] = pull1, \ 121 .pull_type[2] = pull2, \ 122 .pull_type[3] = pull3, \ 123 } 124 125 #define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1, \ 126 drv2, drv3, pull0, pull1, \ 127 pull2, pull3) \ 128 { \ 129 .bank_num = id, \ 130 .nr_pins = pins, \ 131 .name = label, \ 132 .iomux = { \ 133 { .offset = -1 }, \ 134 { .offset = -1 }, \ 135 { .offset = -1 }, \ 136 { .offset = -1 }, \ 137 }, \ 138 .drv = { \ 139 { .drv_type = drv0, .offset = -1 }, \ 140 { .drv_type = drv1, .offset = -1 }, \ 141 { .drv_type = drv2, .offset = -1 }, \ 142 { .drv_type = drv3, .offset = -1 }, \ 143 }, \ 144 .pull_type[0] = pull0, \ 145 .pull_type[1] = pull1, \ 146 .pull_type[2] = pull2, \ 147 .pull_type[3] = pull3, \ 148 } 149 150 #define PIN_BANK_IOMUX_FLAGS_OFFSET(id, pins, label, iom0, iom1, iom2, \ 151 iom3, offset0, offset1, offset2, \ 152 offset3) \ 153 { \ 154 .bank_num = id, \ 155 .nr_pins = pins, \ 156 .name = label, \ 157 .iomux = { \ 158 { .type = iom0, .offset = offset0 }, \ 159 { .type = iom1, .offset = offset1 }, \ 160 { .type = iom2, .offset = offset2 }, \ 161 { .type = iom3, .offset = offset3 }, \ 162 }, \ 163 } 164 165 #define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1, \ 166 iom2, iom3, drv0, drv1, drv2, \ 167 drv3, offset0, offset1, \ 168 offset2, offset3) \ 169 { \ 170 .bank_num = id, \ 171 .nr_pins = pins, \ 172 .name = label, \ 173 .iomux = { \ 174 { .type = iom0, .offset = -1 }, \ 175 { .type = iom1, .offset = -1 }, \ 176 { .type = iom2, .offset = -1 }, \ 177 { .type = iom3, .offset = -1 }, \ 178 }, \ 179 .drv = { \ 180 { .drv_type = drv0, .offset = offset0 }, \ 181 { .drv_type = drv1, .offset = offset1 }, \ 182 { .drv_type = drv2, .offset = offset2 }, \ 183 { .drv_type = drv3, .offset = offset3 }, \ 184 }, \ 185 } 186 187 #define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins, \ 188 label, iom0, iom1, iom2, \ 189 iom3, drv0, drv1, drv2, \ 190 drv3, offset0, offset1, \ 191 offset2, offset3, pull0, \ 192 pull1, pull2, pull3) \ 193 { \ 194 .bank_num = id, \ 195 .nr_pins = pins, \ 196 .name = label, \ 197 .iomux = { \ 198 { .type = iom0, .offset = -1 }, \ 199 { .type = iom1, .offset = -1 }, \ 200 { .type = iom2, .offset = -1 }, \ 201 { .type = iom3, .offset = -1 }, \ 202 }, \ 203 .drv = { \ 204 { .drv_type = drv0, .offset = offset0 }, \ 205 { .drv_type = drv1, .offset = offset1 }, \ 206 { .drv_type = drv2, .offset = offset2 }, \ 207 { .drv_type = drv3, .offset = offset3 }, \ 208 }, \ 209 .pull_type[0] = pull0, \ 210 .pull_type[1] = pull1, \ 211 .pull_type[2] = pull2, \ 212 .pull_type[3] = pull3, \ 213 } 214 215 #define PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, FLAG) \ 216 { \ 217 .bank_num = ID, \ 218 .pin = PIN, \ 219 .func = FUNC, \ 220 .route_offset = REG, \ 221 .route_val = VAL, \ 222 .route_location = FLAG, \ 223 } 224 225 #define RK_MUXROUTE_SAME(ID, PIN, FUNC, REG, VAL) \ 226 PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_SAME) 227 228 #define RK_MUXROUTE_GRF(ID, PIN, FUNC, REG, VAL) \ 229 PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_GRF) 230 231 #define RK_MUXROUTE_PMU(ID, PIN, FUNC, REG, VAL) \ 232 PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_PMU) 233 234 #define RK3588_PIN_BANK_FLAGS(ID, PIN, LABEL, M, P) \ 235 PIN_BANK_IOMUX_FLAGS_PULL_FLAGS(ID, PIN, LABEL, M, M, M, M, P, P, P, P) 236 237 static struct regmap_config rockchip_regmap_config = { 238 .reg_bits = 32, 239 .val_bits = 32, 240 .reg_stride = 4, 241 }; 242 243 static inline const struct rockchip_pin_group *pinctrl_name_to_group( 244 const struct rockchip_pinctrl *info, 245 const char *name) 246 { 247 int i; 248 249 for (i = 0; i < info->ngroups; i++) { 250 if (!strcmp(info->groups[i].name, name)) 251 return &info->groups[i]; 252 } 253 254 return NULL; 255 } 256 257 /* 258 * given a pin number that is local to a pin controller, find out the pin bank 259 * and the register base of the pin bank. 260 */ 261 static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info, 262 unsigned pin) 263 { 264 struct rockchip_pin_bank *b = info->ctrl->pin_banks; 265 266 while (pin >= (b->pin_base + b->nr_pins)) 267 b++; 268 269 return b; 270 } 271 272 static struct rockchip_pin_bank *bank_num_to_bank( 273 struct rockchip_pinctrl *info, 274 unsigned num) 275 { 276 struct rockchip_pin_bank *b = info->ctrl->pin_banks; 277 int i; 278 279 for (i = 0; i < info->ctrl->nr_banks; i++, b++) { 280 if (b->bank_num == num) 281 return b; 282 } 283 284 return ERR_PTR(-EINVAL); 285 } 286 287 /* 288 * Pinctrl_ops handling 289 */ 290 291 static int rockchip_get_groups_count(struct pinctrl_dev *pctldev) 292 { 293 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 294 295 return info->ngroups; 296 } 297 298 static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev, 299 unsigned selector) 300 { 301 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 302 303 return info->groups[selector].name; 304 } 305 306 static int rockchip_get_group_pins(struct pinctrl_dev *pctldev, 307 unsigned selector, const unsigned **pins, 308 unsigned *npins) 309 { 310 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 311 312 if (selector >= info->ngroups) 313 return -EINVAL; 314 315 *pins = info->groups[selector].pins; 316 *npins = info->groups[selector].npins; 317 318 return 0; 319 } 320 321 static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev, 322 struct device_node *np, 323 struct pinctrl_map **map, unsigned *num_maps) 324 { 325 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 326 const struct rockchip_pin_group *grp; 327 struct device *dev = info->dev; 328 struct pinctrl_map *new_map; 329 struct device_node *parent; 330 int map_num = 1; 331 int i; 332 333 /* 334 * first find the group of this node and check if we need to create 335 * config maps for pins 336 */ 337 grp = pinctrl_name_to_group(info, np->name); 338 if (!grp) { 339 dev_err(dev, "unable to find group for node %pOFn\n", np); 340 return -EINVAL; 341 } 342 343 map_num += grp->npins; 344 345 new_map = kcalloc(map_num, sizeof(*new_map), GFP_KERNEL); 346 if (!new_map) 347 return -ENOMEM; 348 349 *map = new_map; 350 *num_maps = map_num; 351 352 /* create mux map */ 353 parent = of_get_parent(np); 354 if (!parent) { 355 kfree(new_map); 356 return -EINVAL; 357 } 358 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP; 359 new_map[0].data.mux.function = parent->name; 360 new_map[0].data.mux.group = np->name; 361 of_node_put(parent); 362 363 /* create config map */ 364 new_map++; 365 for (i = 0; i < grp->npins; i++) { 366 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN; 367 new_map[i].data.configs.group_or_pin = 368 pin_get_name(pctldev, grp->pins[i]); 369 new_map[i].data.configs.configs = grp->data[i].configs; 370 new_map[i].data.configs.num_configs = grp->data[i].nconfigs; 371 } 372 373 dev_dbg(dev, "maps: function %s group %s num %d\n", 374 (*map)->data.mux.function, (*map)->data.mux.group, map_num); 375 376 return 0; 377 } 378 379 static void rockchip_dt_free_map(struct pinctrl_dev *pctldev, 380 struct pinctrl_map *map, unsigned num_maps) 381 { 382 kfree(map); 383 } 384 385 static const struct pinctrl_ops rockchip_pctrl_ops = { 386 .get_groups_count = rockchip_get_groups_count, 387 .get_group_name = rockchip_get_group_name, 388 .get_group_pins = rockchip_get_group_pins, 389 .dt_node_to_map = rockchip_dt_node_to_map, 390 .dt_free_map = rockchip_dt_free_map, 391 }; 392 393 /* 394 * Hardware access 395 */ 396 397 static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = { 398 { 399 .num = 1, 400 .pin = 0, 401 .reg = 0x418, 402 .bit = 0, 403 .mask = 0x3 404 }, { 405 .num = 1, 406 .pin = 1, 407 .reg = 0x418, 408 .bit = 2, 409 .mask = 0x3 410 }, { 411 .num = 1, 412 .pin = 2, 413 .reg = 0x418, 414 .bit = 4, 415 .mask = 0x3 416 }, { 417 .num = 1, 418 .pin = 3, 419 .reg = 0x418, 420 .bit = 6, 421 .mask = 0x3 422 }, { 423 .num = 1, 424 .pin = 4, 425 .reg = 0x418, 426 .bit = 8, 427 .mask = 0x3 428 }, { 429 .num = 1, 430 .pin = 5, 431 .reg = 0x418, 432 .bit = 10, 433 .mask = 0x3 434 }, { 435 .num = 1, 436 .pin = 6, 437 .reg = 0x418, 438 .bit = 12, 439 .mask = 0x3 440 }, { 441 .num = 1, 442 .pin = 7, 443 .reg = 0x418, 444 .bit = 14, 445 .mask = 0x3 446 }, { 447 .num = 1, 448 .pin = 8, 449 .reg = 0x41c, 450 .bit = 0, 451 .mask = 0x3 452 }, { 453 .num = 1, 454 .pin = 9, 455 .reg = 0x41c, 456 .bit = 2, 457 .mask = 0x3 458 }, 459 }; 460 461 static struct rockchip_mux_recalced_data rv1126_mux_recalced_data[] = { 462 { 463 .num = 0, 464 .pin = 20, 465 .reg = 0x10000, 466 .bit = 0, 467 .mask = 0xf 468 }, 469 { 470 .num = 0, 471 .pin = 21, 472 .reg = 0x10000, 473 .bit = 4, 474 .mask = 0xf 475 }, 476 { 477 .num = 0, 478 .pin = 22, 479 .reg = 0x10000, 480 .bit = 8, 481 .mask = 0xf 482 }, 483 { 484 .num = 0, 485 .pin = 23, 486 .reg = 0x10000, 487 .bit = 12, 488 .mask = 0xf 489 }, 490 }; 491 492 static struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = { 493 { 494 .num = 2, 495 .pin = 20, 496 .reg = 0xe8, 497 .bit = 0, 498 .mask = 0x7 499 }, { 500 .num = 2, 501 .pin = 21, 502 .reg = 0xe8, 503 .bit = 4, 504 .mask = 0x7 505 }, { 506 .num = 2, 507 .pin = 22, 508 .reg = 0xe8, 509 .bit = 8, 510 .mask = 0x7 511 }, { 512 .num = 2, 513 .pin = 23, 514 .reg = 0xe8, 515 .bit = 12, 516 .mask = 0x7 517 }, { 518 .num = 2, 519 .pin = 24, 520 .reg = 0xd4, 521 .bit = 12, 522 .mask = 0x7 523 }, 524 }; 525 526 static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = { 527 { 528 /* gpio1b6_sel */ 529 .num = 1, 530 .pin = 14, 531 .reg = 0x28, 532 .bit = 12, 533 .mask = 0xf 534 }, { 535 /* gpio1b7_sel */ 536 .num = 1, 537 .pin = 15, 538 .reg = 0x2c, 539 .bit = 0, 540 .mask = 0x3 541 }, { 542 /* gpio1c2_sel */ 543 .num = 1, 544 .pin = 18, 545 .reg = 0x30, 546 .bit = 4, 547 .mask = 0xf 548 }, { 549 /* gpio1c3_sel */ 550 .num = 1, 551 .pin = 19, 552 .reg = 0x30, 553 .bit = 8, 554 .mask = 0xf 555 }, { 556 /* gpio1c4_sel */ 557 .num = 1, 558 .pin = 20, 559 .reg = 0x30, 560 .bit = 12, 561 .mask = 0xf 562 }, { 563 /* gpio1c5_sel */ 564 .num = 1, 565 .pin = 21, 566 .reg = 0x34, 567 .bit = 0, 568 .mask = 0xf 569 }, { 570 /* gpio1c6_sel */ 571 .num = 1, 572 .pin = 22, 573 .reg = 0x34, 574 .bit = 4, 575 .mask = 0xf 576 }, { 577 /* gpio1c7_sel */ 578 .num = 1, 579 .pin = 23, 580 .reg = 0x34, 581 .bit = 8, 582 .mask = 0xf 583 }, { 584 /* gpio2a2_sel */ 585 .num = 2, 586 .pin = 2, 587 .reg = 0x40, 588 .bit = 4, 589 .mask = 0x3 590 }, { 591 /* gpio2a3_sel */ 592 .num = 2, 593 .pin = 3, 594 .reg = 0x40, 595 .bit = 6, 596 .mask = 0x3 597 }, { 598 /* gpio2c0_sel */ 599 .num = 2, 600 .pin = 16, 601 .reg = 0x50, 602 .bit = 0, 603 .mask = 0x3 604 }, { 605 /* gpio3b2_sel */ 606 .num = 3, 607 .pin = 10, 608 .reg = 0x68, 609 .bit = 4, 610 .mask = 0x3 611 }, { 612 /* gpio3b3_sel */ 613 .num = 3, 614 .pin = 11, 615 .reg = 0x68, 616 .bit = 6, 617 .mask = 0x3 618 }, { 619 /* gpio3b4_sel */ 620 .num = 3, 621 .pin = 12, 622 .reg = 0x68, 623 .bit = 8, 624 .mask = 0xf 625 }, { 626 /* gpio3b5_sel */ 627 .num = 3, 628 .pin = 13, 629 .reg = 0x68, 630 .bit = 12, 631 .mask = 0xf 632 }, 633 }; 634 635 static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = { 636 { 637 /* gpio2_b7_sel */ 638 .num = 2, 639 .pin = 15, 640 .reg = 0x28, 641 .bit = 0, 642 .mask = 0x7 643 }, { 644 /* gpio2_c7_sel */ 645 .num = 2, 646 .pin = 23, 647 .reg = 0x30, 648 .bit = 14, 649 .mask = 0x3 650 }, { 651 /* gpio3_b1_sel */ 652 .num = 3, 653 .pin = 9, 654 .reg = 0x44, 655 .bit = 2, 656 .mask = 0x3 657 }, { 658 /* gpio3_b2_sel */ 659 .num = 3, 660 .pin = 10, 661 .reg = 0x44, 662 .bit = 4, 663 .mask = 0x3 664 }, { 665 /* gpio3_b3_sel */ 666 .num = 3, 667 .pin = 11, 668 .reg = 0x44, 669 .bit = 6, 670 .mask = 0x3 671 }, { 672 /* gpio3_b4_sel */ 673 .num = 3, 674 .pin = 12, 675 .reg = 0x44, 676 .bit = 8, 677 .mask = 0x3 678 }, { 679 /* gpio3_b5_sel */ 680 .num = 3, 681 .pin = 13, 682 .reg = 0x44, 683 .bit = 10, 684 .mask = 0x3 685 }, { 686 /* gpio3_b6_sel */ 687 .num = 3, 688 .pin = 14, 689 .reg = 0x44, 690 .bit = 12, 691 .mask = 0x3 692 }, { 693 /* gpio3_b7_sel */ 694 .num = 3, 695 .pin = 15, 696 .reg = 0x44, 697 .bit = 14, 698 .mask = 0x3 699 }, 700 }; 701 702 static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin, 703 int *reg, u8 *bit, int *mask) 704 { 705 struct rockchip_pinctrl *info = bank->drvdata; 706 struct rockchip_pin_ctrl *ctrl = info->ctrl; 707 struct rockchip_mux_recalced_data *data; 708 int i; 709 710 for (i = 0; i < ctrl->niomux_recalced; i++) { 711 data = &ctrl->iomux_recalced[i]; 712 if (data->num == bank->bank_num && 713 data->pin == pin) 714 break; 715 } 716 717 if (i >= ctrl->niomux_recalced) 718 return; 719 720 *reg = data->reg; 721 *mask = data->mask; 722 *bit = data->bit; 723 } 724 725 static struct rockchip_mux_route_data px30_mux_route_data[] = { 726 RK_MUXROUTE_SAME(2, RK_PB4, 1, 0x184, BIT(16 + 7)), /* cif-d0m0 */ 727 RK_MUXROUTE_SAME(3, RK_PA1, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d0m1 */ 728 RK_MUXROUTE_SAME(2, RK_PB6, 1, 0x184, BIT(16 + 7)), /* cif-d1m0 */ 729 RK_MUXROUTE_SAME(3, RK_PA2, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d1m1 */ 730 RK_MUXROUTE_SAME(2, RK_PA0, 1, 0x184, BIT(16 + 7)), /* cif-d2m0 */ 731 RK_MUXROUTE_SAME(3, RK_PA3, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d2m1 */ 732 RK_MUXROUTE_SAME(2, RK_PA1, 1, 0x184, BIT(16 + 7)), /* cif-d3m0 */ 733 RK_MUXROUTE_SAME(3, RK_PA5, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d3m1 */ 734 RK_MUXROUTE_SAME(2, RK_PA2, 1, 0x184, BIT(16 + 7)), /* cif-d4m0 */ 735 RK_MUXROUTE_SAME(3, RK_PA7, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d4m1 */ 736 RK_MUXROUTE_SAME(2, RK_PA3, 1, 0x184, BIT(16 + 7)), /* cif-d5m0 */ 737 RK_MUXROUTE_SAME(3, RK_PB0, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d5m1 */ 738 RK_MUXROUTE_SAME(2, RK_PA4, 1, 0x184, BIT(16 + 7)), /* cif-d6m0 */ 739 RK_MUXROUTE_SAME(3, RK_PB1, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d6m1 */ 740 RK_MUXROUTE_SAME(2, RK_PA5, 1, 0x184, BIT(16 + 7)), /* cif-d7m0 */ 741 RK_MUXROUTE_SAME(3, RK_PB4, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d7m1 */ 742 RK_MUXROUTE_SAME(2, RK_PA6, 1, 0x184, BIT(16 + 7)), /* cif-d8m0 */ 743 RK_MUXROUTE_SAME(3, RK_PB6, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d8m1 */ 744 RK_MUXROUTE_SAME(2, RK_PA7, 1, 0x184, BIT(16 + 7)), /* cif-d9m0 */ 745 RK_MUXROUTE_SAME(3, RK_PB7, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d9m1 */ 746 RK_MUXROUTE_SAME(2, RK_PB7, 1, 0x184, BIT(16 + 7)), /* cif-d10m0 */ 747 RK_MUXROUTE_SAME(3, RK_PC6, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d10m1 */ 748 RK_MUXROUTE_SAME(2, RK_PC0, 1, 0x184, BIT(16 + 7)), /* cif-d11m0 */ 749 RK_MUXROUTE_SAME(3, RK_PC7, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d11m1 */ 750 RK_MUXROUTE_SAME(2, RK_PB0, 1, 0x184, BIT(16 + 7)), /* cif-vsyncm0 */ 751 RK_MUXROUTE_SAME(3, RK_PD1, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-vsyncm1 */ 752 RK_MUXROUTE_SAME(2, RK_PB1, 1, 0x184, BIT(16 + 7)), /* cif-hrefm0 */ 753 RK_MUXROUTE_SAME(3, RK_PD2, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-hrefm1 */ 754 RK_MUXROUTE_SAME(2, RK_PB2, 1, 0x184, BIT(16 + 7)), /* cif-clkinm0 */ 755 RK_MUXROUTE_SAME(3, RK_PD3, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-clkinm1 */ 756 RK_MUXROUTE_SAME(2, RK_PB3, 1, 0x184, BIT(16 + 7)), /* cif-clkoutm0 */ 757 RK_MUXROUTE_SAME(3, RK_PD0, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-clkoutm1 */ 758 RK_MUXROUTE_SAME(3, RK_PC6, 2, 0x184, BIT(16 + 8)), /* pdm-m0 */ 759 RK_MUXROUTE_SAME(2, RK_PC6, 1, 0x184, BIT(16 + 8) | BIT(8)), /* pdm-m1 */ 760 RK_MUXROUTE_SAME(3, RK_PD3, 2, 0x184, BIT(16 + 8)), /* pdm-sdi0m0 */ 761 RK_MUXROUTE_SAME(2, RK_PC5, 2, 0x184, BIT(16 + 8) | BIT(8)), /* pdm-sdi0m1 */ 762 RK_MUXROUTE_SAME(1, RK_PD3, 2, 0x184, BIT(16 + 10)), /* uart2-rxm0 */ 763 RK_MUXROUTE_SAME(2, RK_PB6, 2, 0x184, BIT(16 + 10) | BIT(10)), /* uart2-rxm1 */ 764 RK_MUXROUTE_SAME(1, RK_PD2, 2, 0x184, BIT(16 + 10)), /* uart2-txm0 */ 765 RK_MUXROUTE_SAME(2, RK_PB4, 2, 0x184, BIT(16 + 10) | BIT(10)), /* uart2-txm1 */ 766 RK_MUXROUTE_SAME(0, RK_PC1, 2, 0x184, BIT(16 + 9)), /* uart3-rxm0 */ 767 RK_MUXROUTE_SAME(1, RK_PB7, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-rxm1 */ 768 RK_MUXROUTE_SAME(0, RK_PC0, 2, 0x184, BIT(16 + 9)), /* uart3-txm0 */ 769 RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-txm1 */ 770 RK_MUXROUTE_SAME(0, RK_PC2, 2, 0x184, BIT(16 + 9)), /* uart3-ctsm0 */ 771 RK_MUXROUTE_SAME(1, RK_PB4, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-ctsm1 */ 772 RK_MUXROUTE_SAME(0, RK_PC3, 2, 0x184, BIT(16 + 9)), /* uart3-rtsm0 */ 773 RK_MUXROUTE_SAME(1, RK_PB5, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-rtsm1 */ 774 }; 775 776 static struct rockchip_mux_route_data rv1126_mux_route_data[] = { 777 RK_MUXROUTE_GRF(3, RK_PD2, 1, 0x10260, WRITE_MASK_VAL(0, 0, 0)), /* I2S0_MCLK_M0 */ 778 RK_MUXROUTE_GRF(3, RK_PB0, 3, 0x10260, WRITE_MASK_VAL(0, 0, 1)), /* I2S0_MCLK_M1 */ 779 780 RK_MUXROUTE_GRF(0, RK_PD4, 4, 0x10260, WRITE_MASK_VAL(3, 2, 0)), /* I2S1_MCLK_M0 */ 781 RK_MUXROUTE_GRF(1, RK_PD5, 2, 0x10260, WRITE_MASK_VAL(3, 2, 1)), /* I2S1_MCLK_M1 */ 782 RK_MUXROUTE_GRF(2, RK_PC7, 6, 0x10260, WRITE_MASK_VAL(3, 2, 2)), /* I2S1_MCLK_M2 */ 783 784 RK_MUXROUTE_GRF(1, RK_PD0, 1, 0x10260, WRITE_MASK_VAL(4, 4, 0)), /* I2S2_MCLK_M0 */ 785 RK_MUXROUTE_GRF(2, RK_PB3, 2, 0x10260, WRITE_MASK_VAL(4, 4, 1)), /* I2S2_MCLK_M1 */ 786 787 RK_MUXROUTE_GRF(3, RK_PD4, 2, 0x10260, WRITE_MASK_VAL(12, 12, 0)), /* PDM_CLK0_M0 */ 788 RK_MUXROUTE_GRF(3, RK_PC0, 3, 0x10260, WRITE_MASK_VAL(12, 12, 1)), /* PDM_CLK0_M1 */ 789 790 RK_MUXROUTE_GRF(3, RK_PC6, 1, 0x10264, WRITE_MASK_VAL(0, 0, 0)), /* CIF_CLKOUT_M0 */ 791 RK_MUXROUTE_GRF(2, RK_PD1, 3, 0x10264, WRITE_MASK_VAL(0, 0, 1)), /* CIF_CLKOUT_M1 */ 792 793 RK_MUXROUTE_GRF(3, RK_PA4, 5, 0x10264, WRITE_MASK_VAL(5, 4, 0)), /* I2C3_SCL_M0 */ 794 RK_MUXROUTE_GRF(2, RK_PD4, 7, 0x10264, WRITE_MASK_VAL(5, 4, 1)), /* I2C3_SCL_M1 */ 795 RK_MUXROUTE_GRF(1, RK_PD6, 3, 0x10264, WRITE_MASK_VAL(5, 4, 2)), /* I2C3_SCL_M2 */ 796 797 RK_MUXROUTE_GRF(3, RK_PA0, 7, 0x10264, WRITE_MASK_VAL(6, 6, 0)), /* I2C4_SCL_M0 */ 798 RK_MUXROUTE_GRF(4, RK_PA0, 4, 0x10264, WRITE_MASK_VAL(6, 6, 1)), /* I2C4_SCL_M1 */ 799 800 RK_MUXROUTE_GRF(2, RK_PA5, 7, 0x10264, WRITE_MASK_VAL(9, 8, 0)), /* I2C5_SCL_M0 */ 801 RK_MUXROUTE_GRF(3, RK_PB0, 5, 0x10264, WRITE_MASK_VAL(9, 8, 1)), /* I2C5_SCL_M1 */ 802 RK_MUXROUTE_GRF(1, RK_PD0, 4, 0x10264, WRITE_MASK_VAL(9, 8, 2)), /* I2C5_SCL_M2 */ 803 804 RK_MUXROUTE_GRF(3, RK_PC0, 5, 0x10264, WRITE_MASK_VAL(11, 10, 0)), /* SPI1_CLK_M0 */ 805 RK_MUXROUTE_GRF(1, RK_PC6, 3, 0x10264, WRITE_MASK_VAL(11, 10, 1)), /* SPI1_CLK_M1 */ 806 RK_MUXROUTE_GRF(2, RK_PD5, 6, 0x10264, WRITE_MASK_VAL(11, 10, 2)), /* SPI1_CLK_M2 */ 807 808 RK_MUXROUTE_GRF(3, RK_PC0, 2, 0x10264, WRITE_MASK_VAL(12, 12, 0)), /* RGMII_CLK_M0 */ 809 RK_MUXROUTE_GRF(2, RK_PB7, 2, 0x10264, WRITE_MASK_VAL(12, 12, 1)), /* RGMII_CLK_M1 */ 810 811 RK_MUXROUTE_GRF(3, RK_PA1, 3, 0x10264, WRITE_MASK_VAL(13, 13, 0)), /* CAN_TXD_M0 */ 812 RK_MUXROUTE_GRF(3, RK_PA7, 5, 0x10264, WRITE_MASK_VAL(13, 13, 1)), /* CAN_TXD_M1 */ 813 814 RK_MUXROUTE_GRF(3, RK_PA4, 6, 0x10268, WRITE_MASK_VAL(0, 0, 0)), /* PWM8_M0 */ 815 RK_MUXROUTE_GRF(2, RK_PD7, 5, 0x10268, WRITE_MASK_VAL(0, 0, 1)), /* PWM8_M1 */ 816 817 RK_MUXROUTE_GRF(3, RK_PA5, 6, 0x10268, WRITE_MASK_VAL(2, 2, 0)), /* PWM9_M0 */ 818 RK_MUXROUTE_GRF(2, RK_PD6, 5, 0x10268, WRITE_MASK_VAL(2, 2, 1)), /* PWM9_M1 */ 819 820 RK_MUXROUTE_GRF(3, RK_PA6, 6, 0x10268, WRITE_MASK_VAL(4, 4, 0)), /* PWM10_M0 */ 821 RK_MUXROUTE_GRF(2, RK_PD5, 5, 0x10268, WRITE_MASK_VAL(4, 4, 1)), /* PWM10_M1 */ 822 823 RK_MUXROUTE_GRF(3, RK_PA7, 6, 0x10268, WRITE_MASK_VAL(6, 6, 0)), /* PWM11_IR_M0 */ 824 RK_MUXROUTE_GRF(3, RK_PA1, 5, 0x10268, WRITE_MASK_VAL(6, 6, 1)), /* PWM11_IR_M1 */ 825 826 RK_MUXROUTE_GRF(1, RK_PA5, 3, 0x10268, WRITE_MASK_VAL(8, 8, 0)), /* UART2_TX_M0 */ 827 RK_MUXROUTE_GRF(3, RK_PA2, 1, 0x10268, WRITE_MASK_VAL(8, 8, 1)), /* UART2_TX_M1 */ 828 829 RK_MUXROUTE_GRF(3, RK_PC6, 3, 0x10268, WRITE_MASK_VAL(11, 10, 0)), /* UART3_TX_M0 */ 830 RK_MUXROUTE_GRF(1, RK_PA7, 2, 0x10268, WRITE_MASK_VAL(11, 10, 1)), /* UART3_TX_M1 */ 831 RK_MUXROUTE_GRF(3, RK_PA0, 4, 0x10268, WRITE_MASK_VAL(11, 10, 2)), /* UART3_TX_M2 */ 832 833 RK_MUXROUTE_GRF(3, RK_PA4, 4, 0x10268, WRITE_MASK_VAL(13, 12, 0)), /* UART4_TX_M0 */ 834 RK_MUXROUTE_GRF(2, RK_PA6, 4, 0x10268, WRITE_MASK_VAL(13, 12, 1)), /* UART4_TX_M1 */ 835 RK_MUXROUTE_GRF(1, RK_PD5, 3, 0x10268, WRITE_MASK_VAL(13, 12, 2)), /* UART4_TX_M2 */ 836 837 RK_MUXROUTE_GRF(3, RK_PA6, 4, 0x10268, WRITE_MASK_VAL(15, 14, 0)), /* UART5_TX_M0 */ 838 RK_MUXROUTE_GRF(2, RK_PB0, 4, 0x10268, WRITE_MASK_VAL(15, 14, 1)), /* UART5_TX_M1 */ 839 RK_MUXROUTE_GRF(2, RK_PA0, 3, 0x10268, WRITE_MASK_VAL(15, 14, 2)), /* UART5_TX_M2 */ 840 841 RK_MUXROUTE_PMU(0, RK_PB6, 3, 0x0114, WRITE_MASK_VAL(0, 0, 0)), /* PWM0_M0 */ 842 RK_MUXROUTE_PMU(2, RK_PB3, 5, 0x0114, WRITE_MASK_VAL(0, 0, 1)), /* PWM0_M1 */ 843 844 RK_MUXROUTE_PMU(0, RK_PB7, 3, 0x0114, WRITE_MASK_VAL(2, 2, 0)), /* PWM1_M0 */ 845 RK_MUXROUTE_PMU(2, RK_PB2, 5, 0x0114, WRITE_MASK_VAL(2, 2, 1)), /* PWM1_M1 */ 846 847 RK_MUXROUTE_PMU(0, RK_PC0, 3, 0x0114, WRITE_MASK_VAL(4, 4, 0)), /* PWM2_M0 */ 848 RK_MUXROUTE_PMU(2, RK_PB1, 5, 0x0114, WRITE_MASK_VAL(4, 4, 1)), /* PWM2_M1 */ 849 850 RK_MUXROUTE_PMU(0, RK_PC1, 3, 0x0114, WRITE_MASK_VAL(6, 6, 0)), /* PWM3_IR_M0 */ 851 RK_MUXROUTE_PMU(2, RK_PB0, 5, 0x0114, WRITE_MASK_VAL(6, 6, 1)), /* PWM3_IR_M1 */ 852 853 RK_MUXROUTE_PMU(0, RK_PC2, 3, 0x0114, WRITE_MASK_VAL(8, 8, 0)), /* PWM4_M0 */ 854 RK_MUXROUTE_PMU(2, RK_PA7, 5, 0x0114, WRITE_MASK_VAL(8, 8, 1)), /* PWM4_M1 */ 855 856 RK_MUXROUTE_PMU(0, RK_PC3, 3, 0x0114, WRITE_MASK_VAL(10, 10, 0)), /* PWM5_M0 */ 857 RK_MUXROUTE_PMU(2, RK_PA6, 5, 0x0114, WRITE_MASK_VAL(10, 10, 1)), /* PWM5_M1 */ 858 859 RK_MUXROUTE_PMU(0, RK_PB2, 3, 0x0114, WRITE_MASK_VAL(12, 12, 0)), /* PWM6_M0 */ 860 RK_MUXROUTE_PMU(2, RK_PD4, 5, 0x0114, WRITE_MASK_VAL(12, 12, 1)), /* PWM6_M1 */ 861 862 RK_MUXROUTE_PMU(0, RK_PB1, 3, 0x0114, WRITE_MASK_VAL(14, 14, 0)), /* PWM7_IR_M0 */ 863 RK_MUXROUTE_PMU(3, RK_PA0, 5, 0x0114, WRITE_MASK_VAL(14, 14, 1)), /* PWM7_IR_M1 */ 864 865 RK_MUXROUTE_PMU(0, RK_PB0, 1, 0x0118, WRITE_MASK_VAL(1, 0, 0)), /* SPI0_CLK_M0 */ 866 RK_MUXROUTE_PMU(2, RK_PA1, 1, 0x0118, WRITE_MASK_VAL(1, 0, 1)), /* SPI0_CLK_M1 */ 867 RK_MUXROUTE_PMU(2, RK_PB2, 6, 0x0118, WRITE_MASK_VAL(1, 0, 2)), /* SPI0_CLK_M2 */ 868 869 RK_MUXROUTE_PMU(0, RK_PB6, 2, 0x0118, WRITE_MASK_VAL(2, 2, 0)), /* UART1_TX_M0 */ 870 RK_MUXROUTE_PMU(1, RK_PD0, 5, 0x0118, WRITE_MASK_VAL(2, 2, 1)), /* UART1_TX_M1 */ 871 }; 872 873 static struct rockchip_mux_route_data rk3128_mux_route_data[] = { 874 RK_MUXROUTE_SAME(1, RK_PB2, 1, 0x144, BIT(16 + 3) | BIT(16 + 4)), /* spi-0 */ 875 RK_MUXROUTE_SAME(1, RK_PD3, 3, 0x144, BIT(16 + 3) | BIT(16 + 4) | BIT(3)), /* spi-1 */ 876 RK_MUXROUTE_SAME(0, RK_PB5, 2, 0x144, BIT(16 + 3) | BIT(16 + 4) | BIT(4)), /* spi-2 */ 877 RK_MUXROUTE_SAME(1, RK_PA5, 1, 0x144, BIT(16 + 5)), /* i2s-0 */ 878 RK_MUXROUTE_SAME(0, RK_PB6, 1, 0x144, BIT(16 + 5) | BIT(5)), /* i2s-1 */ 879 RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x144, BIT(16 + 6)), /* emmc-0 */ 880 RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x144, BIT(16 + 6) | BIT(6)), /* emmc-1 */ 881 }; 882 883 static struct rockchip_mux_route_data rk3188_mux_route_data[] = { 884 RK_MUXROUTE_SAME(0, RK_PD0, 1, 0xa0, BIT(16 + 11)), /* non-iomuxed emmc/flash pins on flash-dqs */ 885 RK_MUXROUTE_SAME(0, RK_PD0, 2, 0xa0, BIT(16 + 11) | BIT(11)), /* non-iomuxed emmc/flash pins on emmc-clk */ 886 }; 887 888 static struct rockchip_mux_route_data rk3228_mux_route_data[] = { 889 RK_MUXROUTE_SAME(0, RK_PD2, 1, 0x50, BIT(16)), /* pwm0-0 */ 890 RK_MUXROUTE_SAME(3, RK_PC5, 1, 0x50, BIT(16) | BIT(0)), /* pwm0-1 */ 891 RK_MUXROUTE_SAME(0, RK_PD3, 1, 0x50, BIT(16 + 1)), /* pwm1-0 */ 892 RK_MUXROUTE_SAME(0, RK_PD6, 2, 0x50, BIT(16 + 1) | BIT(1)), /* pwm1-1 */ 893 RK_MUXROUTE_SAME(0, RK_PD4, 1, 0x50, BIT(16 + 2)), /* pwm2-0 */ 894 RK_MUXROUTE_SAME(1, RK_PB4, 2, 0x50, BIT(16 + 2) | BIT(2)), /* pwm2-1 */ 895 RK_MUXROUTE_SAME(3, RK_PD2, 1, 0x50, BIT(16 + 3)), /* pwm3-0 */ 896 RK_MUXROUTE_SAME(1, RK_PB3, 2, 0x50, BIT(16 + 3) | BIT(3)), /* pwm3-1 */ 897 RK_MUXROUTE_SAME(1, RK_PA1, 1, 0x50, BIT(16 + 4)), /* sdio-0_d0 */ 898 RK_MUXROUTE_SAME(3, RK_PA2, 1, 0x50, BIT(16 + 4) | BIT(4)), /* sdio-1_d0 */ 899 RK_MUXROUTE_SAME(0, RK_PB5, 2, 0x50, BIT(16 + 5)), /* spi-0_rx */ 900 RK_MUXROUTE_SAME(2, RK_PA0, 2, 0x50, BIT(16 + 5) | BIT(5)), /* spi-1_rx */ 901 RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x50, BIT(16 + 7)), /* emmc-0_cmd */ 902 RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x50, BIT(16 + 7) | BIT(7)), /* emmc-1_cmd */ 903 RK_MUXROUTE_SAME(1, RK_PC3, 2, 0x50, BIT(16 + 8)), /* uart2-0_rx */ 904 RK_MUXROUTE_SAME(1, RK_PB2, 2, 0x50, BIT(16 + 8) | BIT(8)), /* uart2-1_rx */ 905 RK_MUXROUTE_SAME(1, RK_PB2, 1, 0x50, BIT(16 + 11)), /* uart1-0_rx */ 906 RK_MUXROUTE_SAME(3, RK_PB5, 1, 0x50, BIT(16 + 11) | BIT(11)), /* uart1-1_rx */ 907 }; 908 909 static struct rockchip_mux_route_data rk3288_mux_route_data[] = { 910 RK_MUXROUTE_SAME(7, RK_PC0, 2, 0x264, BIT(16 + 12) | BIT(12)), /* edphdmi_cecinoutt1 */ 911 RK_MUXROUTE_SAME(7, RK_PC7, 4, 0x264, BIT(16 + 12)), /* edphdmi_cecinout */ 912 }; 913 914 static struct rockchip_mux_route_data rk3308_mux_route_data[] = { 915 RK_MUXROUTE_SAME(0, RK_PC3, 1, 0x314, BIT(16 + 0) | BIT(0)), /* rtc_clk */ 916 RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x314, BIT(16 + 2) | BIT(16 + 3)), /* uart2_rxm0 */ 917 RK_MUXROUTE_SAME(4, RK_PD2, 2, 0x314, BIT(16 + 2) | BIT(16 + 3) | BIT(2)), /* uart2_rxm1 */ 918 RK_MUXROUTE_SAME(0, RK_PB7, 2, 0x314, BIT(16 + 4)), /* i2c3_sdam0 */ 919 RK_MUXROUTE_SAME(3, RK_PB4, 2, 0x314, BIT(16 + 4) | BIT(4)), /* i2c3_sdam1 */ 920 RK_MUXROUTE_SAME(1, RK_PA3, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclktxm0 */ 921 RK_MUXROUTE_SAME(1, RK_PA4, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclkrxm0 */ 922 RK_MUXROUTE_SAME(1, RK_PB5, 2, 0x308, BIT(16 + 3) | BIT(3)), /* i2s-8ch-1-sclktxm1 */ 923 RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x308, BIT(16 + 3) | BIT(3)), /* i2s-8ch-1-sclkrxm1 */ 924 RK_MUXROUTE_SAME(1, RK_PA4, 3, 0x308, BIT(16 + 12) | BIT(16 + 13)), /* pdm-clkm0 */ 925 RK_MUXROUTE_SAME(1, RK_PB6, 4, 0x308, BIT(16 + 12) | BIT(16 + 13) | BIT(12)), /* pdm-clkm1 */ 926 RK_MUXROUTE_SAME(2, RK_PA6, 2, 0x308, BIT(16 + 12) | BIT(16 + 13) | BIT(13)), /* pdm-clkm2 */ 927 RK_MUXROUTE_SAME(2, RK_PA4, 3, 0x600, BIT(16 + 2) | BIT(2)), /* pdm-clkm-m2 */ 928 }; 929 930 static struct rockchip_mux_route_data rk3328_mux_route_data[] = { 931 RK_MUXROUTE_SAME(1, RK_PA1, 2, 0x50, BIT(16) | BIT(16 + 1)), /* uart2dbg_rxm0 */ 932 RK_MUXROUTE_SAME(2, RK_PA1, 1, 0x50, BIT(16) | BIT(16 + 1) | BIT(0)), /* uart2dbg_rxm1 */ 933 RK_MUXROUTE_SAME(1, RK_PB3, 2, 0x50, BIT(16 + 2) | BIT(2)), /* gmac-m1_rxd0 */ 934 RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x50, BIT(16 + 10) | BIT(10)), /* gmac-m1-optimized_rxd3 */ 935 RK_MUXROUTE_SAME(2, RK_PC3, 2, 0x50, BIT(16 + 3)), /* pdm_sdi0m0 */ 936 RK_MUXROUTE_SAME(1, RK_PC7, 3, 0x50, BIT(16 + 3) | BIT(3)), /* pdm_sdi0m1 */ 937 RK_MUXROUTE_SAME(3, RK_PA2, 4, 0x50, BIT(16 + 4) | BIT(16 + 5) | BIT(5)), /* spi_rxdm2 */ 938 RK_MUXROUTE_SAME(1, RK_PD0, 1, 0x50, BIT(16 + 6)), /* i2s2_sdim0 */ 939 RK_MUXROUTE_SAME(3, RK_PA2, 6, 0x50, BIT(16 + 6) | BIT(6)), /* i2s2_sdim1 */ 940 RK_MUXROUTE_SAME(2, RK_PC6, 3, 0x50, BIT(16 + 7) | BIT(7)), /* card_iom1 */ 941 RK_MUXROUTE_SAME(2, RK_PC0, 3, 0x50, BIT(16 + 8) | BIT(8)), /* tsp_d5m1 */ 942 RK_MUXROUTE_SAME(2, RK_PC0, 4, 0x50, BIT(16 + 9) | BIT(9)), /* cif_data5m1 */ 943 }; 944 945 static struct rockchip_mux_route_data rk3399_mux_route_data[] = { 946 RK_MUXROUTE_SAME(4, RK_PB0, 2, 0xe21c, BIT(16 + 10) | BIT(16 + 11)), /* uart2dbga_rx */ 947 RK_MUXROUTE_SAME(4, RK_PC0, 2, 0xe21c, BIT(16 + 10) | BIT(16 + 11) | BIT(10)), /* uart2dbgb_rx */ 948 RK_MUXROUTE_SAME(4, RK_PC3, 1, 0xe21c, BIT(16 + 10) | BIT(16 + 11) | BIT(11)), /* uart2dbgc_rx */ 949 RK_MUXROUTE_SAME(2, RK_PD2, 2, 0xe21c, BIT(16 + 14)), /* pcie_clkreqn */ 950 RK_MUXROUTE_SAME(4, RK_PD0, 1, 0xe21c, BIT(16 + 14) | BIT(14)), /* pcie_clkreqnb */ 951 }; 952 953 static struct rockchip_mux_route_data rk3568_mux_route_data[] = { 954 RK_MUXROUTE_PMU(0, RK_PB7, 1, 0x0110, WRITE_MASK_VAL(1, 0, 0)), /* PWM0 IO mux M0 */ 955 RK_MUXROUTE_PMU(0, RK_PC7, 2, 0x0110, WRITE_MASK_VAL(1, 0, 1)), /* PWM0 IO mux M1 */ 956 RK_MUXROUTE_PMU(0, RK_PC0, 1, 0x0110, WRITE_MASK_VAL(3, 2, 0)), /* PWM1 IO mux M0 */ 957 RK_MUXROUTE_PMU(0, RK_PB5, 4, 0x0110, WRITE_MASK_VAL(3, 2, 1)), /* PWM1 IO mux M1 */ 958 RK_MUXROUTE_PMU(0, RK_PC1, 1, 0x0110, WRITE_MASK_VAL(5, 4, 0)), /* PWM2 IO mux M0 */ 959 RK_MUXROUTE_PMU(0, RK_PB6, 4, 0x0110, WRITE_MASK_VAL(5, 4, 1)), /* PWM2 IO mux M1 */ 960 RK_MUXROUTE_GRF(0, RK_PB3, 2, 0x0300, WRITE_MASK_VAL(0, 0, 0)), /* CAN0 IO mux M0 */ 961 RK_MUXROUTE_GRF(2, RK_PA1, 4, 0x0300, WRITE_MASK_VAL(0, 0, 1)), /* CAN0 IO mux M1 */ 962 RK_MUXROUTE_GRF(1, RK_PA1, 3, 0x0300, WRITE_MASK_VAL(2, 2, 0)), /* CAN1 IO mux M0 */ 963 RK_MUXROUTE_GRF(4, RK_PC3, 3, 0x0300, WRITE_MASK_VAL(2, 2, 1)), /* CAN1 IO mux M1 */ 964 RK_MUXROUTE_GRF(4, RK_PB5, 3, 0x0300, WRITE_MASK_VAL(4, 4, 0)), /* CAN2 IO mux M0 */ 965 RK_MUXROUTE_GRF(2, RK_PB2, 4, 0x0300, WRITE_MASK_VAL(4, 4, 1)), /* CAN2 IO mux M1 */ 966 RK_MUXROUTE_GRF(4, RK_PC4, 1, 0x0300, WRITE_MASK_VAL(6, 6, 0)), /* HPDIN IO mux M0 */ 967 RK_MUXROUTE_GRF(0, RK_PC2, 2, 0x0300, WRITE_MASK_VAL(6, 6, 1)), /* HPDIN IO mux M1 */ 968 RK_MUXROUTE_GRF(3, RK_PB1, 3, 0x0300, WRITE_MASK_VAL(8, 8, 0)), /* GMAC1 IO mux M0 */ 969 RK_MUXROUTE_GRF(4, RK_PA7, 3, 0x0300, WRITE_MASK_VAL(8, 8, 1)), /* GMAC1 IO mux M1 */ 970 RK_MUXROUTE_GRF(4, RK_PD1, 1, 0x0300, WRITE_MASK_VAL(10, 10, 0)), /* HDMITX IO mux M0 */ 971 RK_MUXROUTE_GRF(0, RK_PC7, 1, 0x0300, WRITE_MASK_VAL(10, 10, 1)), /* HDMITX IO mux M1 */ 972 RK_MUXROUTE_GRF(0, RK_PB6, 1, 0x0300, WRITE_MASK_VAL(14, 14, 0)), /* I2C2 IO mux M0 */ 973 RK_MUXROUTE_GRF(4, RK_PB4, 1, 0x0300, WRITE_MASK_VAL(14, 14, 1)), /* I2C2 IO mux M1 */ 974 RK_MUXROUTE_GRF(1, RK_PA0, 1, 0x0304, WRITE_MASK_VAL(0, 0, 0)), /* I2C3 IO mux M0 */ 975 RK_MUXROUTE_GRF(3, RK_PB6, 4, 0x0304, WRITE_MASK_VAL(0, 0, 1)), /* I2C3 IO mux M1 */ 976 RK_MUXROUTE_GRF(4, RK_PB2, 1, 0x0304, WRITE_MASK_VAL(2, 2, 0)), /* I2C4 IO mux M0 */ 977 RK_MUXROUTE_GRF(2, RK_PB1, 2, 0x0304, WRITE_MASK_VAL(2, 2, 1)), /* I2C4 IO mux M1 */ 978 RK_MUXROUTE_GRF(3, RK_PB4, 4, 0x0304, WRITE_MASK_VAL(4, 4, 0)), /* I2C5 IO mux M0 */ 979 RK_MUXROUTE_GRF(4, RK_PD0, 2, 0x0304, WRITE_MASK_VAL(4, 4, 1)), /* I2C5 IO mux M1 */ 980 RK_MUXROUTE_GRF(3, RK_PB1, 5, 0x0304, WRITE_MASK_VAL(14, 14, 0)), /* PWM8 IO mux M0 */ 981 RK_MUXROUTE_GRF(1, RK_PD5, 4, 0x0304, WRITE_MASK_VAL(14, 14, 1)), /* PWM8 IO mux M1 */ 982 RK_MUXROUTE_GRF(3, RK_PB2, 5, 0x0308, WRITE_MASK_VAL(0, 0, 0)), /* PWM9 IO mux M0 */ 983 RK_MUXROUTE_GRF(1, RK_PD6, 4, 0x0308, WRITE_MASK_VAL(0, 0, 1)), /* PWM9 IO mux M1 */ 984 RK_MUXROUTE_GRF(3, RK_PB5, 5, 0x0308, WRITE_MASK_VAL(2, 2, 0)), /* PWM10 IO mux M0 */ 985 RK_MUXROUTE_GRF(2, RK_PA1, 2, 0x0308, WRITE_MASK_VAL(2, 2, 1)), /* PWM10 IO mux M1 */ 986 RK_MUXROUTE_GRF(3, RK_PB6, 5, 0x0308, WRITE_MASK_VAL(4, 4, 0)), /* PWM11 IO mux M0 */ 987 RK_MUXROUTE_GRF(4, RK_PC0, 3, 0x0308, WRITE_MASK_VAL(4, 4, 1)), /* PWM11 IO mux M1 */ 988 RK_MUXROUTE_GRF(3, RK_PB7, 2, 0x0308, WRITE_MASK_VAL(6, 6, 0)), /* PWM12 IO mux M0 */ 989 RK_MUXROUTE_GRF(4, RK_PC5, 1, 0x0308, WRITE_MASK_VAL(6, 6, 1)), /* PWM12 IO mux M1 */ 990 RK_MUXROUTE_GRF(3, RK_PC0, 2, 0x0308, WRITE_MASK_VAL(8, 8, 0)), /* PWM13 IO mux M0 */ 991 RK_MUXROUTE_GRF(4, RK_PC6, 1, 0x0308, WRITE_MASK_VAL(8, 8, 1)), /* PWM13 IO mux M1 */ 992 RK_MUXROUTE_GRF(3, RK_PC4, 1, 0x0308, WRITE_MASK_VAL(10, 10, 0)), /* PWM14 IO mux M0 */ 993 RK_MUXROUTE_GRF(4, RK_PC2, 1, 0x0308, WRITE_MASK_VAL(10, 10, 1)), /* PWM14 IO mux M1 */ 994 RK_MUXROUTE_GRF(3, RK_PC5, 1, 0x0308, WRITE_MASK_VAL(12, 12, 0)), /* PWM15 IO mux M0 */ 995 RK_MUXROUTE_GRF(4, RK_PC3, 1, 0x0308, WRITE_MASK_VAL(12, 12, 1)), /* PWM15 IO mux M1 */ 996 RK_MUXROUTE_GRF(3, RK_PD2, 3, 0x0308, WRITE_MASK_VAL(14, 14, 0)), /* SDMMC2 IO mux M0 */ 997 RK_MUXROUTE_GRF(3, RK_PA5, 5, 0x0308, WRITE_MASK_VAL(14, 14, 1)), /* SDMMC2 IO mux M1 */ 998 RK_MUXROUTE_GRF(0, RK_PB5, 2, 0x030c, WRITE_MASK_VAL(0, 0, 0)), /* SPI0 IO mux M0 */ 999 RK_MUXROUTE_GRF(2, RK_PD3, 3, 0x030c, WRITE_MASK_VAL(0, 0, 1)), /* SPI0 IO mux M1 */ 1000 RK_MUXROUTE_GRF(2, RK_PB5, 3, 0x030c, WRITE_MASK_VAL(2, 2, 0)), /* SPI1 IO mux M0 */ 1001 RK_MUXROUTE_GRF(3, RK_PC3, 3, 0x030c, WRITE_MASK_VAL(2, 2, 1)), /* SPI1 IO mux M1 */ 1002 RK_MUXROUTE_GRF(2, RK_PC1, 4, 0x030c, WRITE_MASK_VAL(4, 4, 0)), /* SPI2 IO mux M0 */ 1003 RK_MUXROUTE_GRF(3, RK_PA0, 3, 0x030c, WRITE_MASK_VAL(4, 4, 1)), /* SPI2 IO mux M1 */ 1004 RK_MUXROUTE_GRF(4, RK_PB3, 4, 0x030c, WRITE_MASK_VAL(6, 6, 0)), /* SPI3 IO mux M0 */ 1005 RK_MUXROUTE_GRF(4, RK_PC2, 2, 0x030c, WRITE_MASK_VAL(6, 6, 1)), /* SPI3 IO mux M1 */ 1006 RK_MUXROUTE_GRF(2, RK_PB4, 2, 0x030c, WRITE_MASK_VAL(8, 8, 0)), /* UART1 IO mux M0 */ 1007 RK_MUXROUTE_GRF(3, RK_PD6, 4, 0x030c, WRITE_MASK_VAL(8, 8, 1)), /* UART1 IO mux M1 */ 1008 RK_MUXROUTE_GRF(0, RK_PD1, 1, 0x030c, WRITE_MASK_VAL(10, 10, 0)), /* UART2 IO mux M0 */ 1009 RK_MUXROUTE_GRF(1, RK_PD5, 2, 0x030c, WRITE_MASK_VAL(10, 10, 1)), /* UART2 IO mux M1 */ 1010 RK_MUXROUTE_GRF(1, RK_PA1, 2, 0x030c, WRITE_MASK_VAL(12, 12, 0)), /* UART3 IO mux M0 */ 1011 RK_MUXROUTE_GRF(3, RK_PB7, 4, 0x030c, WRITE_MASK_VAL(12, 12, 1)), /* UART3 IO mux M1 */ 1012 RK_MUXROUTE_GRF(1, RK_PA6, 2, 0x030c, WRITE_MASK_VAL(14, 14, 0)), /* UART4 IO mux M0 */ 1013 RK_MUXROUTE_GRF(3, RK_PB2, 4, 0x030c, WRITE_MASK_VAL(14, 14, 1)), /* UART4 IO mux M1 */ 1014 RK_MUXROUTE_GRF(2, RK_PA2, 3, 0x0310, WRITE_MASK_VAL(0, 0, 0)), /* UART5 IO mux M0 */ 1015 RK_MUXROUTE_GRF(3, RK_PC2, 4, 0x0310, WRITE_MASK_VAL(0, 0, 1)), /* UART5 IO mux M1 */ 1016 RK_MUXROUTE_GRF(2, RK_PA4, 3, 0x0310, WRITE_MASK_VAL(2, 2, 0)), /* UART6 IO mux M0 */ 1017 RK_MUXROUTE_GRF(1, RK_PD5, 3, 0x0310, WRITE_MASK_VAL(2, 2, 1)), /* UART6 IO mux M1 */ 1018 RK_MUXROUTE_GRF(2, RK_PA6, 3, 0x0310, WRITE_MASK_VAL(5, 4, 0)), /* UART7 IO mux M0 */ 1019 RK_MUXROUTE_GRF(3, RK_PC4, 4, 0x0310, WRITE_MASK_VAL(5, 4, 1)), /* UART7 IO mux M1 */ 1020 RK_MUXROUTE_GRF(4, RK_PA2, 4, 0x0310, WRITE_MASK_VAL(5, 4, 2)), /* UART7 IO mux M2 */ 1021 RK_MUXROUTE_GRF(2, RK_PC5, 3, 0x0310, WRITE_MASK_VAL(6, 6, 0)), /* UART8 IO mux M0 */ 1022 RK_MUXROUTE_GRF(2, RK_PD7, 4, 0x0310, WRITE_MASK_VAL(6, 6, 1)), /* UART8 IO mux M1 */ 1023 RK_MUXROUTE_GRF(2, RK_PB0, 3, 0x0310, WRITE_MASK_VAL(9, 8, 0)), /* UART9 IO mux M0 */ 1024 RK_MUXROUTE_GRF(4, RK_PC5, 4, 0x0310, WRITE_MASK_VAL(9, 8, 1)), /* UART9 IO mux M1 */ 1025 RK_MUXROUTE_GRF(4, RK_PA4, 4, 0x0310, WRITE_MASK_VAL(9, 8, 2)), /* UART9 IO mux M2 */ 1026 RK_MUXROUTE_GRF(1, RK_PA2, 1, 0x0310, WRITE_MASK_VAL(11, 10, 0)), /* I2S1 IO mux M0 */ 1027 RK_MUXROUTE_GRF(3, RK_PC6, 4, 0x0310, WRITE_MASK_VAL(11, 10, 1)), /* I2S1 IO mux M1 */ 1028 RK_MUXROUTE_GRF(2, RK_PD0, 5, 0x0310, WRITE_MASK_VAL(11, 10, 2)), /* I2S1 IO mux M2 */ 1029 RK_MUXROUTE_GRF(2, RK_PC1, 1, 0x0310, WRITE_MASK_VAL(12, 12, 0)), /* I2S2 IO mux M0 */ 1030 RK_MUXROUTE_GRF(4, RK_PB6, 5, 0x0310, WRITE_MASK_VAL(12, 12, 1)), /* I2S2 IO mux M1 */ 1031 RK_MUXROUTE_GRF(3, RK_PA2, 4, 0x0310, WRITE_MASK_VAL(14, 14, 0)), /* I2S3 IO mux M0 */ 1032 RK_MUXROUTE_GRF(4, RK_PC2, 5, 0x0310, WRITE_MASK_VAL(14, 14, 1)), /* I2S3 IO mux M1 */ 1033 RK_MUXROUTE_GRF(1, RK_PA4, 3, 0x0314, WRITE_MASK_VAL(1, 0, 0)), /* PDM IO mux M0 */ 1034 RK_MUXROUTE_GRF(1, RK_PA6, 3, 0x0314, WRITE_MASK_VAL(1, 0, 0)), /* PDM IO mux M0 */ 1035 RK_MUXROUTE_GRF(3, RK_PD6, 5, 0x0314, WRITE_MASK_VAL(1, 0, 1)), /* PDM IO mux M1 */ 1036 RK_MUXROUTE_GRF(4, RK_PA0, 4, 0x0314, WRITE_MASK_VAL(1, 0, 1)), /* PDM IO mux M1 */ 1037 RK_MUXROUTE_GRF(3, RK_PC4, 5, 0x0314, WRITE_MASK_VAL(1, 0, 2)), /* PDM IO mux M2 */ 1038 RK_MUXROUTE_GRF(0, RK_PA5, 3, 0x0314, WRITE_MASK_VAL(3, 2, 0)), /* PCIE20 IO mux M0 */ 1039 RK_MUXROUTE_GRF(2, RK_PD0, 4, 0x0314, WRITE_MASK_VAL(3, 2, 1)), /* PCIE20 IO mux M1 */ 1040 RK_MUXROUTE_GRF(1, RK_PB0, 4, 0x0314, WRITE_MASK_VAL(3, 2, 2)), /* PCIE20 IO mux M2 */ 1041 RK_MUXROUTE_GRF(0, RK_PA4, 3, 0x0314, WRITE_MASK_VAL(5, 4, 0)), /* PCIE30X1 IO mux M0 */ 1042 RK_MUXROUTE_GRF(2, RK_PD2, 4, 0x0314, WRITE_MASK_VAL(5, 4, 1)), /* PCIE30X1 IO mux M1 */ 1043 RK_MUXROUTE_GRF(1, RK_PA5, 4, 0x0314, WRITE_MASK_VAL(5, 4, 2)), /* PCIE30X1 IO mux M2 */ 1044 RK_MUXROUTE_GRF(0, RK_PA6, 2, 0x0314, WRITE_MASK_VAL(7, 6, 0)), /* PCIE30X2 IO mux M0 */ 1045 RK_MUXROUTE_GRF(2, RK_PD4, 4, 0x0314, WRITE_MASK_VAL(7, 6, 1)), /* PCIE30X2 IO mux M1 */ 1046 RK_MUXROUTE_GRF(4, RK_PC2, 4, 0x0314, WRITE_MASK_VAL(7, 6, 2)), /* PCIE30X2 IO mux M2 */ 1047 }; 1048 1049 static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin, 1050 int mux, u32 *loc, u32 *reg, u32 *value) 1051 { 1052 struct rockchip_pinctrl *info = bank->drvdata; 1053 struct rockchip_pin_ctrl *ctrl = info->ctrl; 1054 struct rockchip_mux_route_data *data; 1055 int i; 1056 1057 for (i = 0; i < ctrl->niomux_routes; i++) { 1058 data = &ctrl->iomux_routes[i]; 1059 if ((data->bank_num == bank->bank_num) && 1060 (data->pin == pin) && (data->func == mux)) 1061 break; 1062 } 1063 1064 if (i >= ctrl->niomux_routes) 1065 return false; 1066 1067 *loc = data->route_location; 1068 *reg = data->route_offset; 1069 *value = data->route_val; 1070 1071 return true; 1072 } 1073 1074 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) 1075 { 1076 struct rockchip_pinctrl *info = bank->drvdata; 1077 struct rockchip_pin_ctrl *ctrl = info->ctrl; 1078 int iomux_num = (pin / 8); 1079 struct regmap *regmap; 1080 unsigned int val; 1081 int reg, ret, mask, mux_type; 1082 u8 bit; 1083 1084 if (iomux_num > 3) 1085 return -EINVAL; 1086 1087 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { 1088 dev_err(info->dev, "pin %d is unrouted\n", pin); 1089 return -EINVAL; 1090 } 1091 1092 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) 1093 return RK_FUNC_GPIO; 1094 1095 if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) 1096 regmap = info->regmap_pmu; 1097 else if (bank->iomux[iomux_num].type & IOMUX_L_SOURCE_PMU) 1098 regmap = (pin % 8 < 4) ? info->regmap_pmu : info->regmap_base; 1099 else 1100 regmap = info->regmap_base; 1101 1102 /* get basic quadrupel of mux registers and the correct reg inside */ 1103 mux_type = bank->iomux[iomux_num].type; 1104 reg = bank->iomux[iomux_num].offset; 1105 if (mux_type & IOMUX_WIDTH_4BIT) { 1106 if ((pin % 8) >= 4) 1107 reg += 0x4; 1108 bit = (pin % 4) * 4; 1109 mask = 0xf; 1110 } else if (mux_type & IOMUX_WIDTH_3BIT) { 1111 if ((pin % 8) >= 5) 1112 reg += 0x4; 1113 bit = (pin % 8 % 5) * 3; 1114 mask = 0x7; 1115 } else { 1116 bit = (pin % 8) * 2; 1117 mask = 0x3; 1118 } 1119 1120 if (bank->recalced_mask & BIT(pin)) 1121 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); 1122 1123 if (ctrl->type == RK3588) { 1124 if (bank->bank_num == 0) { 1125 if ((pin >= RK_PB4) && (pin <= RK_PD7)) { 1126 u32 reg0 = 0; 1127 1128 reg0 = reg + 0x4000 - 0xC; /* PMU2_IOC_BASE */ 1129 ret = regmap_read(regmap, reg0, &val); 1130 if (ret) 1131 return ret; 1132 1133 if (!(val & BIT(8))) 1134 return ((val >> bit) & mask); 1135 1136 reg = reg + 0x8000; /* BUS_IOC_BASE */ 1137 regmap = info->regmap_base; 1138 } 1139 } else if (bank->bank_num > 0) { 1140 reg += 0x8000; /* BUS_IOC_BASE */ 1141 } 1142 } 1143 1144 ret = regmap_read(regmap, reg, &val); 1145 if (ret) 1146 return ret; 1147 1148 return ((val >> bit) & mask); 1149 } 1150 1151 static int rockchip_verify_mux(struct rockchip_pin_bank *bank, 1152 int pin, int mux) 1153 { 1154 struct rockchip_pinctrl *info = bank->drvdata; 1155 struct device *dev = info->dev; 1156 int iomux_num = (pin / 8); 1157 1158 if (iomux_num > 3) 1159 return -EINVAL; 1160 1161 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { 1162 dev_err(dev, "pin %d is unrouted\n", pin); 1163 return -EINVAL; 1164 } 1165 1166 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) { 1167 if (mux != RK_FUNC_GPIO) { 1168 dev_err(dev, "pin %d only supports a gpio mux\n", pin); 1169 return -ENOTSUPP; 1170 } 1171 } 1172 1173 return 0; 1174 } 1175 1176 /* 1177 * Set a new mux function for a pin. 1178 * 1179 * The register is divided into the upper and lower 16 bit. When changing 1180 * a value, the previous register value is not read and changed. Instead 1181 * it seems the changed bits are marked in the upper 16 bit, while the 1182 * changed value gets set in the same offset in the lower 16 bit. 1183 * All pin settings seem to be 2 bit wide in both the upper and lower 1184 * parts. 1185 * @bank: pin bank to change 1186 * @pin: pin to change 1187 * @mux: new mux function to set 1188 */ 1189 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) 1190 { 1191 struct rockchip_pinctrl *info = bank->drvdata; 1192 struct rockchip_pin_ctrl *ctrl = info->ctrl; 1193 struct device *dev = info->dev; 1194 int iomux_num = (pin / 8); 1195 struct regmap *regmap; 1196 int reg, ret, mask, mux_type; 1197 u8 bit; 1198 u32 data, rmask, route_location, route_reg, route_val; 1199 1200 ret = rockchip_verify_mux(bank, pin, mux); 1201 if (ret < 0) 1202 return ret; 1203 1204 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) 1205 return 0; 1206 1207 dev_dbg(dev, "setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux); 1208 1209 if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) 1210 regmap = info->regmap_pmu; 1211 else if (bank->iomux[iomux_num].type & IOMUX_L_SOURCE_PMU) 1212 regmap = (pin % 8 < 4) ? info->regmap_pmu : info->regmap_base; 1213 else 1214 regmap = info->regmap_base; 1215 1216 /* get basic quadrupel of mux registers and the correct reg inside */ 1217 mux_type = bank->iomux[iomux_num].type; 1218 reg = bank->iomux[iomux_num].offset; 1219 if (mux_type & IOMUX_WIDTH_4BIT) { 1220 if ((pin % 8) >= 4) 1221 reg += 0x4; 1222 bit = (pin % 4) * 4; 1223 mask = 0xf; 1224 } else if (mux_type & IOMUX_WIDTH_3BIT) { 1225 if ((pin % 8) >= 5) 1226 reg += 0x4; 1227 bit = (pin % 8 % 5) * 3; 1228 mask = 0x7; 1229 } else { 1230 bit = (pin % 8) * 2; 1231 mask = 0x3; 1232 } 1233 1234 if (bank->recalced_mask & BIT(pin)) 1235 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); 1236 1237 if (ctrl->type == RK3588) { 1238 if (bank->bank_num == 0) { 1239 if ((pin >= RK_PB4) && (pin <= RK_PD7)) { 1240 if (mux < 8) { 1241 reg += 0x4000 - 0xC; /* PMU2_IOC_BASE */ 1242 data = (mask << (bit + 16)); 1243 rmask = data | (data >> 16); 1244 data |= (mux & mask) << bit; 1245 ret = regmap_update_bits(regmap, reg, rmask, data); 1246 } else { 1247 u32 reg0 = 0; 1248 1249 reg0 = reg + 0x4000 - 0xC; /* PMU2_IOC_BASE */ 1250 data = (mask << (bit + 16)); 1251 rmask = data | (data >> 16); 1252 data |= 8 << bit; 1253 ret = regmap_update_bits(regmap, reg0, rmask, data); 1254 1255 reg0 = reg + 0x8000; /* BUS_IOC_BASE */ 1256 data = (mask << (bit + 16)); 1257 rmask = data | (data >> 16); 1258 data |= mux << bit; 1259 regmap = info->regmap_base; 1260 ret |= regmap_update_bits(regmap, reg0, rmask, data); 1261 } 1262 } else { 1263 data = (mask << (bit + 16)); 1264 rmask = data | (data >> 16); 1265 data |= (mux & mask) << bit; 1266 ret = regmap_update_bits(regmap, reg, rmask, data); 1267 } 1268 return ret; 1269 } else if (bank->bank_num > 0) { 1270 reg += 0x8000; /* BUS_IOC_BASE */ 1271 } 1272 } 1273 1274 if (mux > mask) 1275 return -EINVAL; 1276 1277 if (bank->route_mask & BIT(pin)) { 1278 if (rockchip_get_mux_route(bank, pin, mux, &route_location, 1279 &route_reg, &route_val)) { 1280 struct regmap *route_regmap = regmap; 1281 1282 /* handle special locations */ 1283 switch (route_location) { 1284 case ROCKCHIP_ROUTE_PMU: 1285 route_regmap = info->regmap_pmu; 1286 break; 1287 case ROCKCHIP_ROUTE_GRF: 1288 route_regmap = info->regmap_base; 1289 break; 1290 } 1291 1292 ret = regmap_write(route_regmap, route_reg, route_val); 1293 if (ret) 1294 return ret; 1295 } 1296 } 1297 1298 data = (mask << (bit + 16)); 1299 rmask = data | (data >> 16); 1300 data |= (mux & mask) << bit; 1301 ret = regmap_update_bits(regmap, reg, rmask, data); 1302 1303 return ret; 1304 } 1305 1306 #define PX30_PULL_PMU_OFFSET 0x10 1307 #define PX30_PULL_GRF_OFFSET 0x60 1308 #define PX30_PULL_BITS_PER_PIN 2 1309 #define PX30_PULL_PINS_PER_REG 8 1310 #define PX30_PULL_BANK_STRIDE 16 1311 1312 static int px30_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1313 int pin_num, struct regmap **regmap, 1314 int *reg, u8 *bit) 1315 { 1316 struct rockchip_pinctrl *info = bank->drvdata; 1317 1318 /* The first 32 pins of the first bank are located in PMU */ 1319 if (bank->bank_num == 0) { 1320 *regmap = info->regmap_pmu; 1321 *reg = PX30_PULL_PMU_OFFSET; 1322 } else { 1323 *regmap = info->regmap_base; 1324 *reg = PX30_PULL_GRF_OFFSET; 1325 1326 /* correct the offset, as we're starting with the 2nd bank */ 1327 *reg -= 0x10; 1328 *reg += bank->bank_num * PX30_PULL_BANK_STRIDE; 1329 } 1330 1331 *reg += ((pin_num / PX30_PULL_PINS_PER_REG) * 4); 1332 *bit = (pin_num % PX30_PULL_PINS_PER_REG); 1333 *bit *= PX30_PULL_BITS_PER_PIN; 1334 1335 return 0; 1336 } 1337 1338 #define PX30_DRV_PMU_OFFSET 0x20 1339 #define PX30_DRV_GRF_OFFSET 0xf0 1340 #define PX30_DRV_BITS_PER_PIN 2 1341 #define PX30_DRV_PINS_PER_REG 8 1342 #define PX30_DRV_BANK_STRIDE 16 1343 1344 static int px30_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1345 int pin_num, struct regmap **regmap, 1346 int *reg, u8 *bit) 1347 { 1348 struct rockchip_pinctrl *info = bank->drvdata; 1349 1350 /* The first 32 pins of the first bank are located in PMU */ 1351 if (bank->bank_num == 0) { 1352 *regmap = info->regmap_pmu; 1353 *reg = PX30_DRV_PMU_OFFSET; 1354 } else { 1355 *regmap = info->regmap_base; 1356 *reg = PX30_DRV_GRF_OFFSET; 1357 1358 /* correct the offset, as we're starting with the 2nd bank */ 1359 *reg -= 0x10; 1360 *reg += bank->bank_num * PX30_DRV_BANK_STRIDE; 1361 } 1362 1363 *reg += ((pin_num / PX30_DRV_PINS_PER_REG) * 4); 1364 *bit = (pin_num % PX30_DRV_PINS_PER_REG); 1365 *bit *= PX30_DRV_BITS_PER_PIN; 1366 1367 return 0; 1368 } 1369 1370 #define PX30_SCHMITT_PMU_OFFSET 0x38 1371 #define PX30_SCHMITT_GRF_OFFSET 0xc0 1372 #define PX30_SCHMITT_PINS_PER_PMU_REG 16 1373 #define PX30_SCHMITT_BANK_STRIDE 16 1374 #define PX30_SCHMITT_PINS_PER_GRF_REG 8 1375 1376 static int px30_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1377 int pin_num, 1378 struct regmap **regmap, 1379 int *reg, u8 *bit) 1380 { 1381 struct rockchip_pinctrl *info = bank->drvdata; 1382 int pins_per_reg; 1383 1384 if (bank->bank_num == 0) { 1385 *regmap = info->regmap_pmu; 1386 *reg = PX30_SCHMITT_PMU_OFFSET; 1387 pins_per_reg = PX30_SCHMITT_PINS_PER_PMU_REG; 1388 } else { 1389 *regmap = info->regmap_base; 1390 *reg = PX30_SCHMITT_GRF_OFFSET; 1391 pins_per_reg = PX30_SCHMITT_PINS_PER_GRF_REG; 1392 *reg += (bank->bank_num - 1) * PX30_SCHMITT_BANK_STRIDE; 1393 } 1394 1395 *reg += ((pin_num / pins_per_reg) * 4); 1396 *bit = pin_num % pins_per_reg; 1397 1398 return 0; 1399 } 1400 1401 #define RV1108_PULL_PMU_OFFSET 0x10 1402 #define RV1108_PULL_OFFSET 0x110 1403 #define RV1108_PULL_PINS_PER_REG 8 1404 #define RV1108_PULL_BITS_PER_PIN 2 1405 #define RV1108_PULL_BANK_STRIDE 16 1406 1407 static int rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1408 int pin_num, struct regmap **regmap, 1409 int *reg, u8 *bit) 1410 { 1411 struct rockchip_pinctrl *info = bank->drvdata; 1412 1413 /* The first 24 pins of the first bank are located in PMU */ 1414 if (bank->bank_num == 0) { 1415 *regmap = info->regmap_pmu; 1416 *reg = RV1108_PULL_PMU_OFFSET; 1417 } else { 1418 *reg = RV1108_PULL_OFFSET; 1419 *regmap = info->regmap_base; 1420 /* correct the offset, as we're starting with the 2nd bank */ 1421 *reg -= 0x10; 1422 *reg += bank->bank_num * RV1108_PULL_BANK_STRIDE; 1423 } 1424 1425 *reg += ((pin_num / RV1108_PULL_PINS_PER_REG) * 4); 1426 *bit = (pin_num % RV1108_PULL_PINS_PER_REG); 1427 *bit *= RV1108_PULL_BITS_PER_PIN; 1428 1429 return 0; 1430 } 1431 1432 #define RV1108_DRV_PMU_OFFSET 0x20 1433 #define RV1108_DRV_GRF_OFFSET 0x210 1434 #define RV1108_DRV_BITS_PER_PIN 2 1435 #define RV1108_DRV_PINS_PER_REG 8 1436 #define RV1108_DRV_BANK_STRIDE 16 1437 1438 static int rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1439 int pin_num, struct regmap **regmap, 1440 int *reg, u8 *bit) 1441 { 1442 struct rockchip_pinctrl *info = bank->drvdata; 1443 1444 /* The first 24 pins of the first bank are located in PMU */ 1445 if (bank->bank_num == 0) { 1446 *regmap = info->regmap_pmu; 1447 *reg = RV1108_DRV_PMU_OFFSET; 1448 } else { 1449 *regmap = info->regmap_base; 1450 *reg = RV1108_DRV_GRF_OFFSET; 1451 1452 /* correct the offset, as we're starting with the 2nd bank */ 1453 *reg -= 0x10; 1454 *reg += bank->bank_num * RV1108_DRV_BANK_STRIDE; 1455 } 1456 1457 *reg += ((pin_num / RV1108_DRV_PINS_PER_REG) * 4); 1458 *bit = pin_num % RV1108_DRV_PINS_PER_REG; 1459 *bit *= RV1108_DRV_BITS_PER_PIN; 1460 1461 return 0; 1462 } 1463 1464 #define RV1108_SCHMITT_PMU_OFFSET 0x30 1465 #define RV1108_SCHMITT_GRF_OFFSET 0x388 1466 #define RV1108_SCHMITT_BANK_STRIDE 8 1467 #define RV1108_SCHMITT_PINS_PER_GRF_REG 16 1468 #define RV1108_SCHMITT_PINS_PER_PMU_REG 8 1469 1470 static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1471 int pin_num, 1472 struct regmap **regmap, 1473 int *reg, u8 *bit) 1474 { 1475 struct rockchip_pinctrl *info = bank->drvdata; 1476 int pins_per_reg; 1477 1478 if (bank->bank_num == 0) { 1479 *regmap = info->regmap_pmu; 1480 *reg = RV1108_SCHMITT_PMU_OFFSET; 1481 pins_per_reg = RV1108_SCHMITT_PINS_PER_PMU_REG; 1482 } else { 1483 *regmap = info->regmap_base; 1484 *reg = RV1108_SCHMITT_GRF_OFFSET; 1485 pins_per_reg = RV1108_SCHMITT_PINS_PER_GRF_REG; 1486 *reg += (bank->bank_num - 1) * RV1108_SCHMITT_BANK_STRIDE; 1487 } 1488 *reg += ((pin_num / pins_per_reg) * 4); 1489 *bit = pin_num % pins_per_reg; 1490 1491 return 0; 1492 } 1493 1494 #define RV1126_PULL_PMU_OFFSET 0x40 1495 #define RV1126_PULL_GRF_GPIO1A0_OFFSET 0x10108 1496 #define RV1126_PULL_PINS_PER_REG 8 1497 #define RV1126_PULL_BITS_PER_PIN 2 1498 #define RV1126_PULL_BANK_STRIDE 16 1499 #define RV1126_GPIO_C4_D7(p) (p >= 20 && p <= 31) /* GPIO0_C4 ~ GPIO0_D7 */ 1500 1501 static int rv1126_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1502 int pin_num, struct regmap **regmap, 1503 int *reg, u8 *bit) 1504 { 1505 struct rockchip_pinctrl *info = bank->drvdata; 1506 1507 /* The first 24 pins of the first bank are located in PMU */ 1508 if (bank->bank_num == 0) { 1509 if (RV1126_GPIO_C4_D7(pin_num)) { 1510 *regmap = info->regmap_base; 1511 *reg = RV1126_PULL_GRF_GPIO1A0_OFFSET; 1512 *reg -= (((31 - pin_num) / RV1126_PULL_PINS_PER_REG + 1) * 4); 1513 *bit = pin_num % RV1126_PULL_PINS_PER_REG; 1514 *bit *= RV1126_PULL_BITS_PER_PIN; 1515 return 0; 1516 } 1517 *regmap = info->regmap_pmu; 1518 *reg = RV1126_PULL_PMU_OFFSET; 1519 } else { 1520 *reg = RV1126_PULL_GRF_GPIO1A0_OFFSET; 1521 *regmap = info->regmap_base; 1522 *reg += (bank->bank_num - 1) * RV1126_PULL_BANK_STRIDE; 1523 } 1524 1525 *reg += ((pin_num / RV1126_PULL_PINS_PER_REG) * 4); 1526 *bit = (pin_num % RV1126_PULL_PINS_PER_REG); 1527 *bit *= RV1126_PULL_BITS_PER_PIN; 1528 1529 return 0; 1530 } 1531 1532 #define RV1126_DRV_PMU_OFFSET 0x20 1533 #define RV1126_DRV_GRF_GPIO1A0_OFFSET 0x10090 1534 #define RV1126_DRV_BITS_PER_PIN 4 1535 #define RV1126_DRV_PINS_PER_REG 4 1536 #define RV1126_DRV_BANK_STRIDE 32 1537 1538 static int rv1126_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1539 int pin_num, struct regmap **regmap, 1540 int *reg, u8 *bit) 1541 { 1542 struct rockchip_pinctrl *info = bank->drvdata; 1543 1544 /* The first 24 pins of the first bank are located in PMU */ 1545 if (bank->bank_num == 0) { 1546 if (RV1126_GPIO_C4_D7(pin_num)) { 1547 *regmap = info->regmap_base; 1548 *reg = RV1126_DRV_GRF_GPIO1A0_OFFSET; 1549 *reg -= (((31 - pin_num) / RV1126_DRV_PINS_PER_REG + 1) * 4); 1550 *reg -= 0x4; 1551 *bit = pin_num % RV1126_DRV_PINS_PER_REG; 1552 *bit *= RV1126_DRV_BITS_PER_PIN; 1553 return 0; 1554 } 1555 *regmap = info->regmap_pmu; 1556 *reg = RV1126_DRV_PMU_OFFSET; 1557 } else { 1558 *regmap = info->regmap_base; 1559 *reg = RV1126_DRV_GRF_GPIO1A0_OFFSET; 1560 *reg += (bank->bank_num - 1) * RV1126_DRV_BANK_STRIDE; 1561 } 1562 1563 *reg += ((pin_num / RV1126_DRV_PINS_PER_REG) * 4); 1564 *bit = pin_num % RV1126_DRV_PINS_PER_REG; 1565 *bit *= RV1126_DRV_BITS_PER_PIN; 1566 1567 return 0; 1568 } 1569 1570 #define RV1126_SCHMITT_PMU_OFFSET 0x60 1571 #define RV1126_SCHMITT_GRF_GPIO1A0_OFFSET 0x10188 1572 #define RV1126_SCHMITT_BANK_STRIDE 16 1573 #define RV1126_SCHMITT_PINS_PER_GRF_REG 8 1574 #define RV1126_SCHMITT_PINS_PER_PMU_REG 8 1575 1576 static int rv1126_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1577 int pin_num, 1578 struct regmap **regmap, 1579 int *reg, u8 *bit) 1580 { 1581 struct rockchip_pinctrl *info = bank->drvdata; 1582 int pins_per_reg; 1583 1584 if (bank->bank_num == 0) { 1585 if (RV1126_GPIO_C4_D7(pin_num)) { 1586 *regmap = info->regmap_base; 1587 *reg = RV1126_SCHMITT_GRF_GPIO1A0_OFFSET; 1588 *reg -= (((31 - pin_num) / RV1126_SCHMITT_PINS_PER_GRF_REG + 1) * 4); 1589 *bit = pin_num % RV1126_SCHMITT_PINS_PER_GRF_REG; 1590 return 0; 1591 } 1592 *regmap = info->regmap_pmu; 1593 *reg = RV1126_SCHMITT_PMU_OFFSET; 1594 pins_per_reg = RV1126_SCHMITT_PINS_PER_PMU_REG; 1595 } else { 1596 *regmap = info->regmap_base; 1597 *reg = RV1126_SCHMITT_GRF_GPIO1A0_OFFSET; 1598 pins_per_reg = RV1126_SCHMITT_PINS_PER_GRF_REG; 1599 *reg += (bank->bank_num - 1) * RV1126_SCHMITT_BANK_STRIDE; 1600 } 1601 *reg += ((pin_num / pins_per_reg) * 4); 1602 *bit = pin_num % pins_per_reg; 1603 1604 return 0; 1605 } 1606 1607 #define RK3308_SCHMITT_PINS_PER_REG 8 1608 #define RK3308_SCHMITT_BANK_STRIDE 16 1609 #define RK3308_SCHMITT_GRF_OFFSET 0x1a0 1610 1611 static int rk3308_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1612 int pin_num, struct regmap **regmap, 1613 int *reg, u8 *bit) 1614 { 1615 struct rockchip_pinctrl *info = bank->drvdata; 1616 1617 *regmap = info->regmap_base; 1618 *reg = RK3308_SCHMITT_GRF_OFFSET; 1619 1620 *reg += bank->bank_num * RK3308_SCHMITT_BANK_STRIDE; 1621 *reg += ((pin_num / RK3308_SCHMITT_PINS_PER_REG) * 4); 1622 *bit = pin_num % RK3308_SCHMITT_PINS_PER_REG; 1623 1624 return 0; 1625 } 1626 1627 #define RK2928_PULL_OFFSET 0x118 1628 #define RK2928_PULL_PINS_PER_REG 16 1629 #define RK2928_PULL_BANK_STRIDE 8 1630 1631 static int rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1632 int pin_num, struct regmap **regmap, 1633 int *reg, u8 *bit) 1634 { 1635 struct rockchip_pinctrl *info = bank->drvdata; 1636 1637 *regmap = info->regmap_base; 1638 *reg = RK2928_PULL_OFFSET; 1639 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; 1640 *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4; 1641 1642 *bit = pin_num % RK2928_PULL_PINS_PER_REG; 1643 1644 return 0; 1645 }; 1646 1647 #define RK3128_PULL_OFFSET 0x118 1648 1649 static int rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1650 int pin_num, struct regmap **regmap, 1651 int *reg, u8 *bit) 1652 { 1653 struct rockchip_pinctrl *info = bank->drvdata; 1654 1655 *regmap = info->regmap_base; 1656 *reg = RK3128_PULL_OFFSET; 1657 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; 1658 *reg += ((pin_num / RK2928_PULL_PINS_PER_REG) * 4); 1659 1660 *bit = pin_num % RK2928_PULL_PINS_PER_REG; 1661 1662 return 0; 1663 } 1664 1665 #define RK3188_PULL_OFFSET 0x164 1666 #define RK3188_PULL_BITS_PER_PIN 2 1667 #define RK3188_PULL_PINS_PER_REG 8 1668 #define RK3188_PULL_BANK_STRIDE 16 1669 #define RK3188_PULL_PMU_OFFSET 0x64 1670 1671 static int rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1672 int pin_num, struct regmap **regmap, 1673 int *reg, u8 *bit) 1674 { 1675 struct rockchip_pinctrl *info = bank->drvdata; 1676 1677 /* The first 12 pins of the first bank are located elsewhere */ 1678 if (bank->bank_num == 0 && pin_num < 12) { 1679 *regmap = info->regmap_pmu ? info->regmap_pmu 1680 : bank->regmap_pull; 1681 *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0; 1682 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1683 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 1684 *bit *= RK3188_PULL_BITS_PER_PIN; 1685 } else { 1686 *regmap = info->regmap_pull ? info->regmap_pull 1687 : info->regmap_base; 1688 *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET; 1689 1690 /* correct the offset, as it is the 2nd pull register */ 1691 *reg -= 4; 1692 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1693 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1694 1695 /* 1696 * The bits in these registers have an inverse ordering 1697 * with the lowest pin being in bits 15:14 and the highest 1698 * pin in bits 1:0 1699 */ 1700 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG); 1701 *bit *= RK3188_PULL_BITS_PER_PIN; 1702 } 1703 1704 return 0; 1705 } 1706 1707 #define RK3288_PULL_OFFSET 0x140 1708 static int rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1709 int pin_num, struct regmap **regmap, 1710 int *reg, u8 *bit) 1711 { 1712 struct rockchip_pinctrl *info = bank->drvdata; 1713 1714 /* The first 24 pins of the first bank are located in PMU */ 1715 if (bank->bank_num == 0) { 1716 *regmap = info->regmap_pmu; 1717 *reg = RK3188_PULL_PMU_OFFSET; 1718 1719 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1720 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 1721 *bit *= RK3188_PULL_BITS_PER_PIN; 1722 } else { 1723 *regmap = info->regmap_base; 1724 *reg = RK3288_PULL_OFFSET; 1725 1726 /* correct the offset, as we're starting with the 2nd bank */ 1727 *reg -= 0x10; 1728 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1729 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1730 1731 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1732 *bit *= RK3188_PULL_BITS_PER_PIN; 1733 } 1734 1735 return 0; 1736 } 1737 1738 #define RK3288_DRV_PMU_OFFSET 0x70 1739 #define RK3288_DRV_GRF_OFFSET 0x1c0 1740 #define RK3288_DRV_BITS_PER_PIN 2 1741 #define RK3288_DRV_PINS_PER_REG 8 1742 #define RK3288_DRV_BANK_STRIDE 16 1743 1744 static int rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1745 int pin_num, struct regmap **regmap, 1746 int *reg, u8 *bit) 1747 { 1748 struct rockchip_pinctrl *info = bank->drvdata; 1749 1750 /* The first 24 pins of the first bank are located in PMU */ 1751 if (bank->bank_num == 0) { 1752 *regmap = info->regmap_pmu; 1753 *reg = RK3288_DRV_PMU_OFFSET; 1754 1755 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1756 *bit = pin_num % RK3288_DRV_PINS_PER_REG; 1757 *bit *= RK3288_DRV_BITS_PER_PIN; 1758 } else { 1759 *regmap = info->regmap_base; 1760 *reg = RK3288_DRV_GRF_OFFSET; 1761 1762 /* correct the offset, as we're starting with the 2nd bank */ 1763 *reg -= 0x10; 1764 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 1765 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1766 1767 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 1768 *bit *= RK3288_DRV_BITS_PER_PIN; 1769 } 1770 1771 return 0; 1772 } 1773 1774 #define RK3228_PULL_OFFSET 0x100 1775 1776 static int rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1777 int pin_num, struct regmap **regmap, 1778 int *reg, u8 *bit) 1779 { 1780 struct rockchip_pinctrl *info = bank->drvdata; 1781 1782 *regmap = info->regmap_base; 1783 *reg = RK3228_PULL_OFFSET; 1784 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1785 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1786 1787 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1788 *bit *= RK3188_PULL_BITS_PER_PIN; 1789 1790 return 0; 1791 } 1792 1793 #define RK3228_DRV_GRF_OFFSET 0x200 1794 1795 static int rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1796 int pin_num, struct regmap **regmap, 1797 int *reg, u8 *bit) 1798 { 1799 struct rockchip_pinctrl *info = bank->drvdata; 1800 1801 *regmap = info->regmap_base; 1802 *reg = RK3228_DRV_GRF_OFFSET; 1803 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 1804 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1805 1806 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 1807 *bit *= RK3288_DRV_BITS_PER_PIN; 1808 1809 return 0; 1810 } 1811 1812 #define RK3308_PULL_OFFSET 0xa0 1813 1814 static int rk3308_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1815 int pin_num, struct regmap **regmap, 1816 int *reg, u8 *bit) 1817 { 1818 struct rockchip_pinctrl *info = bank->drvdata; 1819 1820 *regmap = info->regmap_base; 1821 *reg = RK3308_PULL_OFFSET; 1822 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1823 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1824 1825 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1826 *bit *= RK3188_PULL_BITS_PER_PIN; 1827 1828 return 0; 1829 } 1830 1831 #define RK3308_DRV_GRF_OFFSET 0x100 1832 1833 static int rk3308_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1834 int pin_num, struct regmap **regmap, 1835 int *reg, u8 *bit) 1836 { 1837 struct rockchip_pinctrl *info = bank->drvdata; 1838 1839 *regmap = info->regmap_base; 1840 *reg = RK3308_DRV_GRF_OFFSET; 1841 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 1842 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1843 1844 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 1845 *bit *= RK3288_DRV_BITS_PER_PIN; 1846 1847 return 0; 1848 } 1849 1850 #define RK3368_PULL_GRF_OFFSET 0x100 1851 #define RK3368_PULL_PMU_OFFSET 0x10 1852 1853 static int rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1854 int pin_num, struct regmap **regmap, 1855 int *reg, u8 *bit) 1856 { 1857 struct rockchip_pinctrl *info = bank->drvdata; 1858 1859 /* The first 32 pins of the first bank are located in PMU */ 1860 if (bank->bank_num == 0) { 1861 *regmap = info->regmap_pmu; 1862 *reg = RK3368_PULL_PMU_OFFSET; 1863 1864 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1865 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 1866 *bit *= RK3188_PULL_BITS_PER_PIN; 1867 } else { 1868 *regmap = info->regmap_base; 1869 *reg = RK3368_PULL_GRF_OFFSET; 1870 1871 /* correct the offset, as we're starting with the 2nd bank */ 1872 *reg -= 0x10; 1873 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1874 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1875 1876 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1877 *bit *= RK3188_PULL_BITS_PER_PIN; 1878 } 1879 1880 return 0; 1881 } 1882 1883 #define RK3368_DRV_PMU_OFFSET 0x20 1884 #define RK3368_DRV_GRF_OFFSET 0x200 1885 1886 static int rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1887 int pin_num, struct regmap **regmap, 1888 int *reg, u8 *bit) 1889 { 1890 struct rockchip_pinctrl *info = bank->drvdata; 1891 1892 /* The first 32 pins of the first bank are located in PMU */ 1893 if (bank->bank_num == 0) { 1894 *regmap = info->regmap_pmu; 1895 *reg = RK3368_DRV_PMU_OFFSET; 1896 1897 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1898 *bit = pin_num % RK3288_DRV_PINS_PER_REG; 1899 *bit *= RK3288_DRV_BITS_PER_PIN; 1900 } else { 1901 *regmap = info->regmap_base; 1902 *reg = RK3368_DRV_GRF_OFFSET; 1903 1904 /* correct the offset, as we're starting with the 2nd bank */ 1905 *reg -= 0x10; 1906 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 1907 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1908 1909 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 1910 *bit *= RK3288_DRV_BITS_PER_PIN; 1911 } 1912 1913 return 0; 1914 } 1915 1916 #define RK3399_PULL_GRF_OFFSET 0xe040 1917 #define RK3399_PULL_PMU_OFFSET 0x40 1918 #define RK3399_DRV_3BITS_PER_PIN 3 1919 1920 static int rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1921 int pin_num, struct regmap **regmap, 1922 int *reg, u8 *bit) 1923 { 1924 struct rockchip_pinctrl *info = bank->drvdata; 1925 1926 /* The bank0:16 and bank1:32 pins are located in PMU */ 1927 if ((bank->bank_num == 0) || (bank->bank_num == 1)) { 1928 *regmap = info->regmap_pmu; 1929 *reg = RK3399_PULL_PMU_OFFSET; 1930 1931 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1932 1933 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1934 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 1935 *bit *= RK3188_PULL_BITS_PER_PIN; 1936 } else { 1937 *regmap = info->regmap_base; 1938 *reg = RK3399_PULL_GRF_OFFSET; 1939 1940 /* correct the offset, as we're starting with the 3rd bank */ 1941 *reg -= 0x20; 1942 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1943 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1944 1945 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1946 *bit *= RK3188_PULL_BITS_PER_PIN; 1947 } 1948 1949 return 0; 1950 } 1951 1952 static int rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1953 int pin_num, struct regmap **regmap, 1954 int *reg, u8 *bit) 1955 { 1956 struct rockchip_pinctrl *info = bank->drvdata; 1957 int drv_num = (pin_num / 8); 1958 1959 /* The bank0:16 and bank1:32 pins are located in PMU */ 1960 if ((bank->bank_num == 0) || (bank->bank_num == 1)) 1961 *regmap = info->regmap_pmu; 1962 else 1963 *regmap = info->regmap_base; 1964 1965 *reg = bank->drv[drv_num].offset; 1966 if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) || 1967 (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY)) 1968 *bit = (pin_num % 8) * 3; 1969 else 1970 *bit = (pin_num % 8) * 2; 1971 1972 return 0; 1973 } 1974 1975 #define RK3568_PULL_PMU_OFFSET 0x20 1976 #define RK3568_PULL_GRF_OFFSET 0x80 1977 #define RK3568_PULL_BITS_PER_PIN 2 1978 #define RK3568_PULL_PINS_PER_REG 8 1979 #define RK3568_PULL_BANK_STRIDE 0x10 1980 1981 static int rk3568_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1982 int pin_num, struct regmap **regmap, 1983 int *reg, u8 *bit) 1984 { 1985 struct rockchip_pinctrl *info = bank->drvdata; 1986 1987 if (bank->bank_num == 0) { 1988 *regmap = info->regmap_pmu; 1989 *reg = RK3568_PULL_PMU_OFFSET; 1990 *reg += bank->bank_num * RK3568_PULL_BANK_STRIDE; 1991 *reg += ((pin_num / RK3568_PULL_PINS_PER_REG) * 4); 1992 1993 *bit = pin_num % RK3568_PULL_PINS_PER_REG; 1994 *bit *= RK3568_PULL_BITS_PER_PIN; 1995 } else { 1996 *regmap = info->regmap_base; 1997 *reg = RK3568_PULL_GRF_OFFSET; 1998 *reg += (bank->bank_num - 1) * RK3568_PULL_BANK_STRIDE; 1999 *reg += ((pin_num / RK3568_PULL_PINS_PER_REG) * 4); 2000 2001 *bit = (pin_num % RK3568_PULL_PINS_PER_REG); 2002 *bit *= RK3568_PULL_BITS_PER_PIN; 2003 } 2004 2005 return 0; 2006 } 2007 2008 #define RK3568_DRV_PMU_OFFSET 0x70 2009 #define RK3568_DRV_GRF_OFFSET 0x200 2010 #define RK3568_DRV_BITS_PER_PIN 8 2011 #define RK3568_DRV_PINS_PER_REG 2 2012 #define RK3568_DRV_BANK_STRIDE 0x40 2013 2014 static int rk3568_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 2015 int pin_num, struct regmap **regmap, 2016 int *reg, u8 *bit) 2017 { 2018 struct rockchip_pinctrl *info = bank->drvdata; 2019 2020 /* The first 32 pins of the first bank are located in PMU */ 2021 if (bank->bank_num == 0) { 2022 *regmap = info->regmap_pmu; 2023 *reg = RK3568_DRV_PMU_OFFSET; 2024 *reg += ((pin_num / RK3568_DRV_PINS_PER_REG) * 4); 2025 2026 *bit = pin_num % RK3568_DRV_PINS_PER_REG; 2027 *bit *= RK3568_DRV_BITS_PER_PIN; 2028 } else { 2029 *regmap = info->regmap_base; 2030 *reg = RK3568_DRV_GRF_OFFSET; 2031 *reg += (bank->bank_num - 1) * RK3568_DRV_BANK_STRIDE; 2032 *reg += ((pin_num / RK3568_DRV_PINS_PER_REG) * 4); 2033 2034 *bit = (pin_num % RK3568_DRV_PINS_PER_REG); 2035 *bit *= RK3568_DRV_BITS_PER_PIN; 2036 } 2037 2038 return 0; 2039 } 2040 2041 #define RK3588_PMU1_IOC_REG (0x0000) 2042 #define RK3588_PMU2_IOC_REG (0x4000) 2043 #define RK3588_BUS_IOC_REG (0x8000) 2044 #define RK3588_VCCIO1_4_IOC_REG (0x9000) 2045 #define RK3588_VCCIO3_5_IOC_REG (0xA000) 2046 #define RK3588_VCCIO2_IOC_REG (0xB000) 2047 #define RK3588_VCCIO6_IOC_REG (0xC000) 2048 #define RK3588_EMMC_IOC_REG (0xD000) 2049 2050 static const u32 rk3588_ds_regs[][2] = { 2051 {RK_GPIO0_A0, RK3588_PMU1_IOC_REG + 0x0010}, 2052 {RK_GPIO0_A4, RK3588_PMU1_IOC_REG + 0x0014}, 2053 {RK_GPIO0_B0, RK3588_PMU1_IOC_REG + 0x0018}, 2054 {RK_GPIO0_B4, RK3588_PMU2_IOC_REG + 0x0014}, 2055 {RK_GPIO0_C0, RK3588_PMU2_IOC_REG + 0x0018}, 2056 {RK_GPIO0_C4, RK3588_PMU2_IOC_REG + 0x001C}, 2057 {RK_GPIO0_D0, RK3588_PMU2_IOC_REG + 0x0020}, 2058 {RK_GPIO0_D4, RK3588_PMU2_IOC_REG + 0x0024}, 2059 {RK_GPIO1_A0, RK3588_VCCIO1_4_IOC_REG + 0x0020}, 2060 {RK_GPIO1_A4, RK3588_VCCIO1_4_IOC_REG + 0x0024}, 2061 {RK_GPIO1_B0, RK3588_VCCIO1_4_IOC_REG + 0x0028}, 2062 {RK_GPIO1_B4, RK3588_VCCIO1_4_IOC_REG + 0x002C}, 2063 {RK_GPIO1_C0, RK3588_VCCIO1_4_IOC_REG + 0x0030}, 2064 {RK_GPIO1_C4, RK3588_VCCIO1_4_IOC_REG + 0x0034}, 2065 {RK_GPIO1_D0, RK3588_VCCIO1_4_IOC_REG + 0x0038}, 2066 {RK_GPIO1_D4, RK3588_VCCIO1_4_IOC_REG + 0x003C}, 2067 {RK_GPIO2_A0, RK3588_EMMC_IOC_REG + 0x0040}, 2068 {RK_GPIO2_A4, RK3588_VCCIO3_5_IOC_REG + 0x0044}, 2069 {RK_GPIO2_B0, RK3588_VCCIO3_5_IOC_REG + 0x0048}, 2070 {RK_GPIO2_B4, RK3588_VCCIO3_5_IOC_REG + 0x004C}, 2071 {RK_GPIO2_C0, RK3588_VCCIO3_5_IOC_REG + 0x0050}, 2072 {RK_GPIO2_C4, RK3588_VCCIO3_5_IOC_REG + 0x0054}, 2073 {RK_GPIO2_D0, RK3588_EMMC_IOC_REG + 0x0058}, 2074 {RK_GPIO2_D4, RK3588_EMMC_IOC_REG + 0x005C}, 2075 {RK_GPIO3_A0, RK3588_VCCIO3_5_IOC_REG + 0x0060}, 2076 {RK_GPIO3_A4, RK3588_VCCIO3_5_IOC_REG + 0x0064}, 2077 {RK_GPIO3_B0, RK3588_VCCIO3_5_IOC_REG + 0x0068}, 2078 {RK_GPIO3_B4, RK3588_VCCIO3_5_IOC_REG + 0x006C}, 2079 {RK_GPIO3_C0, RK3588_VCCIO3_5_IOC_REG + 0x0070}, 2080 {RK_GPIO3_C4, RK3588_VCCIO3_5_IOC_REG + 0x0074}, 2081 {RK_GPIO3_D0, RK3588_VCCIO3_5_IOC_REG + 0x0078}, 2082 {RK_GPIO3_D4, RK3588_VCCIO3_5_IOC_REG + 0x007C}, 2083 {RK_GPIO4_A0, RK3588_VCCIO6_IOC_REG + 0x0080}, 2084 {RK_GPIO4_A4, RK3588_VCCIO6_IOC_REG + 0x0084}, 2085 {RK_GPIO4_B0, RK3588_VCCIO6_IOC_REG + 0x0088}, 2086 {RK_GPIO4_B4, RK3588_VCCIO6_IOC_REG + 0x008C}, 2087 {RK_GPIO4_C0, RK3588_VCCIO6_IOC_REG + 0x0090}, 2088 {RK_GPIO4_C2, RK3588_VCCIO3_5_IOC_REG + 0x0090}, 2089 {RK_GPIO4_C4, RK3588_VCCIO3_5_IOC_REG + 0x0094}, 2090 {RK_GPIO4_D0, RK3588_VCCIO2_IOC_REG + 0x0098}, 2091 {RK_GPIO4_D4, RK3588_VCCIO2_IOC_REG + 0x009C}, 2092 }; 2093 2094 static const u32 rk3588_p_regs[][2] = { 2095 {RK_GPIO0_A0, RK3588_PMU1_IOC_REG + 0x0020}, 2096 {RK_GPIO0_B0, RK3588_PMU1_IOC_REG + 0x0024}, 2097 {RK_GPIO0_B5, RK3588_PMU2_IOC_REG + 0x0028}, 2098 {RK_GPIO0_C0, RK3588_PMU2_IOC_REG + 0x002C}, 2099 {RK_GPIO0_D0, RK3588_PMU2_IOC_REG + 0x0030}, 2100 {RK_GPIO1_A0, RK3588_VCCIO1_4_IOC_REG + 0x0110}, 2101 {RK_GPIO1_B0, RK3588_VCCIO1_4_IOC_REG + 0x0114}, 2102 {RK_GPIO1_C0, RK3588_VCCIO1_4_IOC_REG + 0x0118}, 2103 {RK_GPIO1_D0, RK3588_VCCIO1_4_IOC_REG + 0x011C}, 2104 {RK_GPIO2_A0, RK3588_EMMC_IOC_REG + 0x0120}, 2105 {RK_GPIO2_A6, RK3588_VCCIO3_5_IOC_REG + 0x0120}, 2106 {RK_GPIO2_B0, RK3588_VCCIO3_5_IOC_REG + 0x0124}, 2107 {RK_GPIO2_C0, RK3588_VCCIO3_5_IOC_REG + 0x0128}, 2108 {RK_GPIO2_D0, RK3588_EMMC_IOC_REG + 0x012C}, 2109 {RK_GPIO3_A0, RK3588_VCCIO3_5_IOC_REG + 0x0130}, 2110 {RK_GPIO3_B0, RK3588_VCCIO3_5_IOC_REG + 0x0134}, 2111 {RK_GPIO3_C0, RK3588_VCCIO3_5_IOC_REG + 0x0138}, 2112 {RK_GPIO3_D0, RK3588_VCCIO3_5_IOC_REG + 0x013C}, 2113 {RK_GPIO4_A0, RK3588_VCCIO6_IOC_REG + 0x0140}, 2114 {RK_GPIO4_B0, RK3588_VCCIO6_IOC_REG + 0x0144}, 2115 {RK_GPIO4_C0, RK3588_VCCIO6_IOC_REG + 0x0148}, 2116 {RK_GPIO4_C2, RK3588_VCCIO3_5_IOC_REG + 0x0148}, 2117 {RK_GPIO4_D0, RK3588_VCCIO2_IOC_REG + 0x014C}, 2118 }; 2119 2120 static const u32 rk3588_smt_regs[][2] = { 2121 {RK_GPIO0_A0, RK3588_PMU1_IOC_REG + 0x0030}, 2122 {RK_GPIO0_B0, RK3588_PMU1_IOC_REG + 0x0034}, 2123 {RK_GPIO0_B5, RK3588_PMU2_IOC_REG + 0x0040}, 2124 {RK_GPIO0_C0, RK3588_PMU2_IOC_REG + 0x0044}, 2125 {RK_GPIO0_D0, RK3588_PMU2_IOC_REG + 0x0048}, 2126 {RK_GPIO1_A0, RK3588_VCCIO1_4_IOC_REG + 0x0210}, 2127 {RK_GPIO1_B0, RK3588_VCCIO1_4_IOC_REG + 0x0214}, 2128 {RK_GPIO1_C0, RK3588_VCCIO1_4_IOC_REG + 0x0218}, 2129 {RK_GPIO1_D0, RK3588_VCCIO1_4_IOC_REG + 0x021C}, 2130 {RK_GPIO2_A0, RK3588_EMMC_IOC_REG + 0x0220}, 2131 {RK_GPIO2_A6, RK3588_VCCIO3_5_IOC_REG + 0x0220}, 2132 {RK_GPIO2_B0, RK3588_VCCIO3_5_IOC_REG + 0x0224}, 2133 {RK_GPIO2_C0, RK3588_VCCIO3_5_IOC_REG + 0x0228}, 2134 {RK_GPIO2_D0, RK3588_EMMC_IOC_REG + 0x022C}, 2135 {RK_GPIO3_A0, RK3588_VCCIO3_5_IOC_REG + 0x0230}, 2136 {RK_GPIO3_B0, RK3588_VCCIO3_5_IOC_REG + 0x0234}, 2137 {RK_GPIO3_C0, RK3588_VCCIO3_5_IOC_REG + 0x0238}, 2138 {RK_GPIO3_D0, RK3588_VCCIO3_5_IOC_REG + 0x023C}, 2139 {RK_GPIO4_A0, RK3588_VCCIO6_IOC_REG + 0x0240}, 2140 {RK_GPIO4_B0, RK3588_VCCIO6_IOC_REG + 0x0244}, 2141 {RK_GPIO4_C0, RK3588_VCCIO6_IOC_REG + 0x0248}, 2142 {RK_GPIO4_C2, RK3588_VCCIO3_5_IOC_REG + 0x0248}, 2143 {RK_GPIO4_D0, RK3588_VCCIO2_IOC_REG + 0x024C}, 2144 }; 2145 2146 #define RK3588_PULL_BITS_PER_PIN 2 2147 #define RK3588_PULL_PINS_PER_REG 8 2148 2149 static int rk3588_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 2150 int pin_num, struct regmap **regmap, 2151 int *reg, u8 *bit) 2152 { 2153 struct rockchip_pinctrl *info = bank->drvdata; 2154 u8 bank_num = bank->bank_num; 2155 u32 pin = bank_num * 32 + pin_num; 2156 int i; 2157 2158 for (i = ARRAY_SIZE(rk3588_p_regs) - 1; i >= 0; i--) { 2159 if (pin >= rk3588_p_regs[i][0]) { 2160 *reg = rk3588_p_regs[i][1]; 2161 *regmap = info->regmap_base; 2162 *bit = pin_num % RK3588_PULL_PINS_PER_REG; 2163 *bit *= RK3588_PULL_BITS_PER_PIN; 2164 return 0; 2165 } 2166 } 2167 2168 return -EINVAL; 2169 } 2170 2171 #define RK3588_DRV_BITS_PER_PIN 4 2172 #define RK3588_DRV_PINS_PER_REG 4 2173 2174 static int rk3588_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 2175 int pin_num, struct regmap **regmap, 2176 int *reg, u8 *bit) 2177 { 2178 struct rockchip_pinctrl *info = bank->drvdata; 2179 u8 bank_num = bank->bank_num; 2180 u32 pin = bank_num * 32 + pin_num; 2181 int i; 2182 2183 for (i = ARRAY_SIZE(rk3588_ds_regs) - 1; i >= 0; i--) { 2184 if (pin >= rk3588_ds_regs[i][0]) { 2185 *reg = rk3588_ds_regs[i][1]; 2186 *regmap = info->regmap_base; 2187 *bit = pin_num % RK3588_DRV_PINS_PER_REG; 2188 *bit *= RK3588_DRV_BITS_PER_PIN; 2189 return 0; 2190 } 2191 } 2192 2193 return -EINVAL; 2194 } 2195 2196 #define RK3588_SMT_BITS_PER_PIN 1 2197 #define RK3588_SMT_PINS_PER_REG 8 2198 2199 static int rk3588_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 2200 int pin_num, 2201 struct regmap **regmap, 2202 int *reg, u8 *bit) 2203 { 2204 struct rockchip_pinctrl *info = bank->drvdata; 2205 u8 bank_num = bank->bank_num; 2206 u32 pin = bank_num * 32 + pin_num; 2207 int i; 2208 2209 for (i = ARRAY_SIZE(rk3588_smt_regs) - 1; i >= 0; i--) { 2210 if (pin >= rk3588_smt_regs[i][0]) { 2211 *reg = rk3588_smt_regs[i][1]; 2212 *regmap = info->regmap_base; 2213 *bit = pin_num % RK3588_SMT_PINS_PER_REG; 2214 *bit *= RK3588_SMT_BITS_PER_PIN; 2215 return 0; 2216 } 2217 } 2218 2219 return -EINVAL; 2220 } 2221 2222 static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = { 2223 { 2, 4, 8, 12, -1, -1, -1, -1 }, 2224 { 3, 6, 9, 12, -1, -1, -1, -1 }, 2225 { 5, 10, 15, 20, -1, -1, -1, -1 }, 2226 { 4, 6, 8, 10, 12, 14, 16, 18 }, 2227 { 4, 7, 10, 13, 16, 19, 22, 26 } 2228 }; 2229 2230 static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank, 2231 int pin_num) 2232 { 2233 struct rockchip_pinctrl *info = bank->drvdata; 2234 struct rockchip_pin_ctrl *ctrl = info->ctrl; 2235 struct device *dev = info->dev; 2236 struct regmap *regmap; 2237 int reg, ret; 2238 u32 data, temp, rmask_bits; 2239 u8 bit; 2240 int drv_type = bank->drv[pin_num / 8].drv_type; 2241 2242 ret = ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); 2243 if (ret) 2244 return ret; 2245 2246 switch (drv_type) { 2247 case DRV_TYPE_IO_1V8_3V0_AUTO: 2248 case DRV_TYPE_IO_3V3_ONLY: 2249 rmask_bits = RK3399_DRV_3BITS_PER_PIN; 2250 switch (bit) { 2251 case 0 ... 12: 2252 /* regular case, nothing to do */ 2253 break; 2254 case 15: 2255 /* 2256 * drive-strength offset is special, as it is 2257 * spread over 2 registers 2258 */ 2259 ret = regmap_read(regmap, reg, &data); 2260 if (ret) 2261 return ret; 2262 2263 ret = regmap_read(regmap, reg + 0x4, &temp); 2264 if (ret) 2265 return ret; 2266 2267 /* 2268 * the bit data[15] contains bit 0 of the value 2269 * while temp[1:0] contains bits 2 and 1 2270 */ 2271 data >>= 15; 2272 temp &= 0x3; 2273 temp <<= 1; 2274 data |= temp; 2275 2276 return rockchip_perpin_drv_list[drv_type][data]; 2277 case 18 ... 21: 2278 /* setting fully enclosed in the second register */ 2279 reg += 4; 2280 bit -= 16; 2281 break; 2282 default: 2283 dev_err(dev, "unsupported bit: %d for pinctrl drive type: %d\n", 2284 bit, drv_type); 2285 return -EINVAL; 2286 } 2287 2288 break; 2289 case DRV_TYPE_IO_DEFAULT: 2290 case DRV_TYPE_IO_1V8_OR_3V0: 2291 case DRV_TYPE_IO_1V8_ONLY: 2292 rmask_bits = RK3288_DRV_BITS_PER_PIN; 2293 break; 2294 default: 2295 dev_err(dev, "unsupported pinctrl drive type: %d\n", drv_type); 2296 return -EINVAL; 2297 } 2298 2299 ret = regmap_read(regmap, reg, &data); 2300 if (ret) 2301 return ret; 2302 2303 data >>= bit; 2304 data &= (1 << rmask_bits) - 1; 2305 2306 return rockchip_perpin_drv_list[drv_type][data]; 2307 } 2308 2309 static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank, 2310 int pin_num, int strength) 2311 { 2312 struct rockchip_pinctrl *info = bank->drvdata; 2313 struct rockchip_pin_ctrl *ctrl = info->ctrl; 2314 struct device *dev = info->dev; 2315 struct regmap *regmap; 2316 int reg, ret, i; 2317 u32 data, rmask, rmask_bits, temp; 2318 u8 bit; 2319 int drv_type = bank->drv[pin_num / 8].drv_type; 2320 2321 dev_dbg(dev, "setting drive of GPIO%d-%d to %d\n", 2322 bank->bank_num, pin_num, strength); 2323 2324 ret = ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); 2325 if (ret) 2326 return ret; 2327 if (ctrl->type == RK3588) { 2328 rmask_bits = RK3588_DRV_BITS_PER_PIN; 2329 ret = strength; 2330 goto config; 2331 } else if (ctrl->type == RK3568) { 2332 rmask_bits = RK3568_DRV_BITS_PER_PIN; 2333 ret = (1 << (strength + 1)) - 1; 2334 goto config; 2335 } 2336 2337 if (ctrl->type == RV1126) { 2338 rmask_bits = RV1126_DRV_BITS_PER_PIN; 2339 ret = strength; 2340 goto config; 2341 } 2342 2343 ret = -EINVAL; 2344 for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) { 2345 if (rockchip_perpin_drv_list[drv_type][i] == strength) { 2346 ret = i; 2347 break; 2348 } else if (rockchip_perpin_drv_list[drv_type][i] < 0) { 2349 ret = rockchip_perpin_drv_list[drv_type][i]; 2350 break; 2351 } 2352 } 2353 2354 if (ret < 0) { 2355 dev_err(dev, "unsupported driver strength %d\n", strength); 2356 return ret; 2357 } 2358 2359 switch (drv_type) { 2360 case DRV_TYPE_IO_1V8_3V0_AUTO: 2361 case DRV_TYPE_IO_3V3_ONLY: 2362 rmask_bits = RK3399_DRV_3BITS_PER_PIN; 2363 switch (bit) { 2364 case 0 ... 12: 2365 /* regular case, nothing to do */ 2366 break; 2367 case 15: 2368 /* 2369 * drive-strength offset is special, as it is spread 2370 * over 2 registers, the bit data[15] contains bit 0 2371 * of the value while temp[1:0] contains bits 2 and 1 2372 */ 2373 data = (ret & 0x1) << 15; 2374 temp = (ret >> 0x1) & 0x3; 2375 2376 rmask = BIT(15) | BIT(31); 2377 data |= BIT(31); 2378 ret = regmap_update_bits(regmap, reg, rmask, data); 2379 if (ret) 2380 return ret; 2381 2382 rmask = 0x3 | (0x3 << 16); 2383 temp |= (0x3 << 16); 2384 reg += 0x4; 2385 ret = regmap_update_bits(regmap, reg, rmask, temp); 2386 2387 return ret; 2388 case 18 ... 21: 2389 /* setting fully enclosed in the second register */ 2390 reg += 4; 2391 bit -= 16; 2392 break; 2393 default: 2394 dev_err(dev, "unsupported bit: %d for pinctrl drive type: %d\n", 2395 bit, drv_type); 2396 return -EINVAL; 2397 } 2398 break; 2399 case DRV_TYPE_IO_DEFAULT: 2400 case DRV_TYPE_IO_1V8_OR_3V0: 2401 case DRV_TYPE_IO_1V8_ONLY: 2402 rmask_bits = RK3288_DRV_BITS_PER_PIN; 2403 break; 2404 default: 2405 dev_err(dev, "unsupported pinctrl drive type: %d\n", drv_type); 2406 return -EINVAL; 2407 } 2408 2409 config: 2410 /* enable the write to the equivalent lower bits */ 2411 data = ((1 << rmask_bits) - 1) << (bit + 16); 2412 rmask = data | (data >> 16); 2413 data |= (ret << bit); 2414 2415 ret = regmap_update_bits(regmap, reg, rmask, data); 2416 2417 return ret; 2418 } 2419 2420 static int rockchip_pull_list[PULL_TYPE_MAX][4] = { 2421 { 2422 PIN_CONFIG_BIAS_DISABLE, 2423 PIN_CONFIG_BIAS_PULL_UP, 2424 PIN_CONFIG_BIAS_PULL_DOWN, 2425 PIN_CONFIG_BIAS_BUS_HOLD 2426 }, 2427 { 2428 PIN_CONFIG_BIAS_DISABLE, 2429 PIN_CONFIG_BIAS_PULL_DOWN, 2430 PIN_CONFIG_BIAS_DISABLE, 2431 PIN_CONFIG_BIAS_PULL_UP 2432 }, 2433 }; 2434 2435 static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num) 2436 { 2437 struct rockchip_pinctrl *info = bank->drvdata; 2438 struct rockchip_pin_ctrl *ctrl = info->ctrl; 2439 struct device *dev = info->dev; 2440 struct regmap *regmap; 2441 int reg, ret, pull_type; 2442 u8 bit; 2443 u32 data; 2444 2445 /* rk3066b does support any pulls */ 2446 if (ctrl->type == RK3066B) 2447 return PIN_CONFIG_BIAS_DISABLE; 2448 2449 ret = ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); 2450 if (ret) 2451 return ret; 2452 2453 ret = regmap_read(regmap, reg, &data); 2454 if (ret) 2455 return ret; 2456 2457 switch (ctrl->type) { 2458 case RK2928: 2459 case RK3128: 2460 return !(data & BIT(bit)) 2461 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT 2462 : PIN_CONFIG_BIAS_DISABLE; 2463 case PX30: 2464 case RV1108: 2465 case RK3188: 2466 case RK3288: 2467 case RK3308: 2468 case RK3328: 2469 case RK3368: 2470 case RK3399: 2471 case RK3568: 2472 case RK3588: 2473 pull_type = bank->pull_type[pin_num / 8]; 2474 data >>= bit; 2475 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1; 2476 /* 2477 * In the TRM, pull-up being 1 for everything except the GPIO0_D3-D6, 2478 * where that pull up value becomes 3. 2479 */ 2480 if (ctrl->type == RK3568 && bank->bank_num == 0 && pin_num >= 27 && pin_num <= 30) { 2481 if (data == 3) 2482 data = 1; 2483 } 2484 2485 return rockchip_pull_list[pull_type][data]; 2486 default: 2487 dev_err(dev, "unsupported pinctrl type\n"); 2488 return -EINVAL; 2489 }; 2490 } 2491 2492 static int rockchip_set_pull(struct rockchip_pin_bank *bank, 2493 int pin_num, int pull) 2494 { 2495 struct rockchip_pinctrl *info = bank->drvdata; 2496 struct rockchip_pin_ctrl *ctrl = info->ctrl; 2497 struct device *dev = info->dev; 2498 struct regmap *regmap; 2499 int reg, ret, i, pull_type; 2500 u8 bit; 2501 u32 data, rmask; 2502 2503 dev_dbg(dev, "setting pull of GPIO%d-%d to %d\n", bank->bank_num, pin_num, pull); 2504 2505 /* rk3066b does support any pulls */ 2506 if (ctrl->type == RK3066B) 2507 return pull ? -EINVAL : 0; 2508 2509 ret = ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); 2510 if (ret) 2511 return ret; 2512 2513 switch (ctrl->type) { 2514 case RK2928: 2515 case RK3128: 2516 data = BIT(bit + 16); 2517 if (pull == PIN_CONFIG_BIAS_DISABLE) 2518 data |= BIT(bit); 2519 ret = regmap_write(regmap, reg, data); 2520 break; 2521 case PX30: 2522 case RV1108: 2523 case RV1126: 2524 case RK3188: 2525 case RK3288: 2526 case RK3308: 2527 case RK3328: 2528 case RK3368: 2529 case RK3399: 2530 case RK3568: 2531 case RK3588: 2532 pull_type = bank->pull_type[pin_num / 8]; 2533 ret = -EINVAL; 2534 for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]); 2535 i++) { 2536 if (rockchip_pull_list[pull_type][i] == pull) { 2537 ret = i; 2538 break; 2539 } 2540 } 2541 /* 2542 * In the TRM, pull-up being 1 for everything except the GPIO0_D3-D6, 2543 * where that pull up value becomes 3. 2544 */ 2545 if (ctrl->type == RK3568 && bank->bank_num == 0 && pin_num >= 27 && pin_num <= 30) { 2546 if (ret == 1) 2547 ret = 3; 2548 } 2549 2550 if (ret < 0) { 2551 dev_err(dev, "unsupported pull setting %d\n", pull); 2552 return ret; 2553 } 2554 2555 /* enable the write to the equivalent lower bits */ 2556 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16); 2557 rmask = data | (data >> 16); 2558 data |= (ret << bit); 2559 2560 ret = regmap_update_bits(regmap, reg, rmask, data); 2561 break; 2562 default: 2563 dev_err(dev, "unsupported pinctrl type\n"); 2564 return -EINVAL; 2565 } 2566 2567 return ret; 2568 } 2569 2570 #define RK3328_SCHMITT_BITS_PER_PIN 1 2571 #define RK3328_SCHMITT_PINS_PER_REG 16 2572 #define RK3328_SCHMITT_BANK_STRIDE 8 2573 #define RK3328_SCHMITT_GRF_OFFSET 0x380 2574 2575 static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 2576 int pin_num, 2577 struct regmap **regmap, 2578 int *reg, u8 *bit) 2579 { 2580 struct rockchip_pinctrl *info = bank->drvdata; 2581 2582 *regmap = info->regmap_base; 2583 *reg = RK3328_SCHMITT_GRF_OFFSET; 2584 2585 *reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE; 2586 *reg += ((pin_num / RK3328_SCHMITT_PINS_PER_REG) * 4); 2587 *bit = pin_num % RK3328_SCHMITT_PINS_PER_REG; 2588 2589 return 0; 2590 } 2591 2592 #define RK3568_SCHMITT_BITS_PER_PIN 2 2593 #define RK3568_SCHMITT_PINS_PER_REG 8 2594 #define RK3568_SCHMITT_BANK_STRIDE 0x10 2595 #define RK3568_SCHMITT_GRF_OFFSET 0xc0 2596 #define RK3568_SCHMITT_PMUGRF_OFFSET 0x30 2597 2598 static int rk3568_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 2599 int pin_num, 2600 struct regmap **regmap, 2601 int *reg, u8 *bit) 2602 { 2603 struct rockchip_pinctrl *info = bank->drvdata; 2604 2605 if (bank->bank_num == 0) { 2606 *regmap = info->regmap_pmu; 2607 *reg = RK3568_SCHMITT_PMUGRF_OFFSET; 2608 } else { 2609 *regmap = info->regmap_base; 2610 *reg = RK3568_SCHMITT_GRF_OFFSET; 2611 *reg += (bank->bank_num - 1) * RK3568_SCHMITT_BANK_STRIDE; 2612 } 2613 2614 *reg += ((pin_num / RK3568_SCHMITT_PINS_PER_REG) * 4); 2615 *bit = pin_num % RK3568_SCHMITT_PINS_PER_REG; 2616 *bit *= RK3568_SCHMITT_BITS_PER_PIN; 2617 2618 return 0; 2619 } 2620 2621 static int rockchip_get_schmitt(struct rockchip_pin_bank *bank, int pin_num) 2622 { 2623 struct rockchip_pinctrl *info = bank->drvdata; 2624 struct rockchip_pin_ctrl *ctrl = info->ctrl; 2625 struct regmap *regmap; 2626 int reg, ret; 2627 u8 bit; 2628 u32 data; 2629 2630 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit); 2631 if (ret) 2632 return ret; 2633 2634 ret = regmap_read(regmap, reg, &data); 2635 if (ret) 2636 return ret; 2637 2638 data >>= bit; 2639 switch (ctrl->type) { 2640 case RK3568: 2641 return data & ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1); 2642 default: 2643 break; 2644 } 2645 2646 return data & 0x1; 2647 } 2648 2649 static int rockchip_set_schmitt(struct rockchip_pin_bank *bank, 2650 int pin_num, int enable) 2651 { 2652 struct rockchip_pinctrl *info = bank->drvdata; 2653 struct rockchip_pin_ctrl *ctrl = info->ctrl; 2654 struct device *dev = info->dev; 2655 struct regmap *regmap; 2656 int reg, ret; 2657 u8 bit; 2658 u32 data, rmask; 2659 2660 dev_dbg(dev, "setting input schmitt of GPIO%d-%d to %d\n", 2661 bank->bank_num, pin_num, enable); 2662 2663 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit); 2664 if (ret) 2665 return ret; 2666 2667 /* enable the write to the equivalent lower bits */ 2668 switch (ctrl->type) { 2669 case RK3568: 2670 data = ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1) << (bit + 16); 2671 rmask = data | (data >> 16); 2672 data |= ((enable ? 0x2 : 0x1) << bit); 2673 break; 2674 default: 2675 data = BIT(bit + 16) | (enable << bit); 2676 rmask = BIT(bit + 16) | BIT(bit); 2677 break; 2678 } 2679 2680 return regmap_update_bits(regmap, reg, rmask, data); 2681 } 2682 2683 /* 2684 * Pinmux_ops handling 2685 */ 2686 2687 static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev) 2688 { 2689 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 2690 2691 return info->nfunctions; 2692 } 2693 2694 static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev, 2695 unsigned selector) 2696 { 2697 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 2698 2699 return info->functions[selector].name; 2700 } 2701 2702 static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev, 2703 unsigned selector, const char * const **groups, 2704 unsigned * const num_groups) 2705 { 2706 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 2707 2708 *groups = info->functions[selector].groups; 2709 *num_groups = info->functions[selector].ngroups; 2710 2711 return 0; 2712 } 2713 2714 static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector, 2715 unsigned group) 2716 { 2717 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 2718 const unsigned int *pins = info->groups[group].pins; 2719 const struct rockchip_pin_config *data = info->groups[group].data; 2720 struct device *dev = info->dev; 2721 struct rockchip_pin_bank *bank; 2722 int cnt, ret = 0; 2723 2724 dev_dbg(dev, "enable function %s group %s\n", 2725 info->functions[selector].name, info->groups[group].name); 2726 2727 /* 2728 * for each pin in the pin group selected, program the corresponding 2729 * pin function number in the config register. 2730 */ 2731 for (cnt = 0; cnt < info->groups[group].npins; cnt++) { 2732 bank = pin_to_bank(info, pins[cnt]); 2733 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 2734 data[cnt].func); 2735 if (ret) 2736 break; 2737 } 2738 2739 if (ret) { 2740 /* revert the already done pin settings */ 2741 for (cnt--; cnt >= 0; cnt--) { 2742 bank = pin_to_bank(info, pins[cnt]); 2743 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0); 2744 } 2745 2746 return ret; 2747 } 2748 2749 return 0; 2750 } 2751 2752 static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, 2753 struct pinctrl_gpio_range *range, 2754 unsigned offset, 2755 bool input) 2756 { 2757 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 2758 struct rockchip_pin_bank *bank; 2759 2760 bank = pin_to_bank(info, offset); 2761 return rockchip_set_mux(bank, offset - bank->pin_base, RK_FUNC_GPIO); 2762 } 2763 2764 static const struct pinmux_ops rockchip_pmx_ops = { 2765 .get_functions_count = rockchip_pmx_get_funcs_count, 2766 .get_function_name = rockchip_pmx_get_func_name, 2767 .get_function_groups = rockchip_pmx_get_groups, 2768 .set_mux = rockchip_pmx_set, 2769 .gpio_set_direction = rockchip_pmx_gpio_set_direction, 2770 }; 2771 2772 /* 2773 * Pinconf_ops handling 2774 */ 2775 2776 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl, 2777 enum pin_config_param pull) 2778 { 2779 switch (ctrl->type) { 2780 case RK2928: 2781 case RK3128: 2782 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT || 2783 pull == PIN_CONFIG_BIAS_DISABLE); 2784 case RK3066B: 2785 return pull ? false : true; 2786 case PX30: 2787 case RV1108: 2788 case RV1126: 2789 case RK3188: 2790 case RK3288: 2791 case RK3308: 2792 case RK3328: 2793 case RK3368: 2794 case RK3399: 2795 case RK3568: 2796 case RK3588: 2797 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT); 2798 } 2799 2800 return false; 2801 } 2802 2803 static int rockchip_pinconf_defer_pin(struct rockchip_pin_bank *bank, 2804 unsigned int pin, u32 param, u32 arg) 2805 { 2806 struct rockchip_pin_deferred *cfg; 2807 2808 cfg = kzalloc(sizeof(*cfg), GFP_KERNEL); 2809 if (!cfg) 2810 return -ENOMEM; 2811 2812 cfg->pin = pin; 2813 cfg->param = param; 2814 cfg->arg = arg; 2815 2816 list_add_tail(&cfg->head, &bank->deferred_pins); 2817 2818 return 0; 2819 } 2820 2821 /* set the pin config settings for a specified pin */ 2822 static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 2823 unsigned long *configs, unsigned num_configs) 2824 { 2825 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 2826 struct rockchip_pin_bank *bank = pin_to_bank(info, pin); 2827 struct gpio_chip *gpio = &bank->gpio_chip; 2828 enum pin_config_param param; 2829 u32 arg; 2830 int i; 2831 int rc; 2832 2833 for (i = 0; i < num_configs; i++) { 2834 param = pinconf_to_config_param(configs[i]); 2835 arg = pinconf_to_config_argument(configs[i]); 2836 2837 if (param == PIN_CONFIG_OUTPUT || param == PIN_CONFIG_INPUT_ENABLE) { 2838 /* 2839 * Check for gpio driver not being probed yet. 2840 * The lock makes sure that either gpio-probe has completed 2841 * or the gpio driver hasn't probed yet. 2842 */ 2843 mutex_lock(&bank->deferred_lock); 2844 if (!gpio || !gpio->direction_output) { 2845 rc = rockchip_pinconf_defer_pin(bank, pin - bank->pin_base, param, 2846 arg); 2847 mutex_unlock(&bank->deferred_lock); 2848 if (rc) 2849 return rc; 2850 2851 break; 2852 } 2853 mutex_unlock(&bank->deferred_lock); 2854 } 2855 2856 switch (param) { 2857 case PIN_CONFIG_BIAS_DISABLE: 2858 rc = rockchip_set_pull(bank, pin - bank->pin_base, 2859 param); 2860 if (rc) 2861 return rc; 2862 break; 2863 case PIN_CONFIG_BIAS_PULL_UP: 2864 case PIN_CONFIG_BIAS_PULL_DOWN: 2865 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: 2866 case PIN_CONFIG_BIAS_BUS_HOLD: 2867 if (!rockchip_pinconf_pull_valid(info->ctrl, param)) 2868 return -ENOTSUPP; 2869 2870 if (!arg) 2871 return -EINVAL; 2872 2873 rc = rockchip_set_pull(bank, pin - bank->pin_base, 2874 param); 2875 if (rc) 2876 return rc; 2877 break; 2878 case PIN_CONFIG_OUTPUT: 2879 rc = rockchip_set_mux(bank, pin - bank->pin_base, 2880 RK_FUNC_GPIO); 2881 if (rc != RK_FUNC_GPIO) 2882 return -EINVAL; 2883 2884 rc = gpio->direction_output(gpio, pin - bank->pin_base, 2885 arg); 2886 if (rc) 2887 return rc; 2888 break; 2889 case PIN_CONFIG_INPUT_ENABLE: 2890 rc = rockchip_set_mux(bank, pin - bank->pin_base, 2891 RK_FUNC_GPIO); 2892 if (rc != RK_FUNC_GPIO) 2893 return -EINVAL; 2894 2895 rc = gpio->direction_input(gpio, pin - bank->pin_base); 2896 if (rc) 2897 return rc; 2898 break; 2899 case PIN_CONFIG_DRIVE_STRENGTH: 2900 /* rk3288 is the first with per-pin drive-strength */ 2901 if (!info->ctrl->drv_calc_reg) 2902 return -ENOTSUPP; 2903 2904 rc = rockchip_set_drive_perpin(bank, 2905 pin - bank->pin_base, arg); 2906 if (rc < 0) 2907 return rc; 2908 break; 2909 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 2910 if (!info->ctrl->schmitt_calc_reg) 2911 return -ENOTSUPP; 2912 2913 rc = rockchip_set_schmitt(bank, 2914 pin - bank->pin_base, arg); 2915 if (rc < 0) 2916 return rc; 2917 break; 2918 default: 2919 return -ENOTSUPP; 2920 break; 2921 } 2922 } /* for each config */ 2923 2924 return 0; 2925 } 2926 2927 /* get the pin config settings for a specified pin */ 2928 static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, 2929 unsigned long *config) 2930 { 2931 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 2932 struct rockchip_pin_bank *bank = pin_to_bank(info, pin); 2933 struct gpio_chip *gpio = &bank->gpio_chip; 2934 enum pin_config_param param = pinconf_to_config_param(*config); 2935 u16 arg; 2936 int rc; 2937 2938 switch (param) { 2939 case PIN_CONFIG_BIAS_DISABLE: 2940 if (rockchip_get_pull(bank, pin - bank->pin_base) != param) 2941 return -EINVAL; 2942 2943 arg = 0; 2944 break; 2945 case PIN_CONFIG_BIAS_PULL_UP: 2946 case PIN_CONFIG_BIAS_PULL_DOWN: 2947 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: 2948 case PIN_CONFIG_BIAS_BUS_HOLD: 2949 if (!rockchip_pinconf_pull_valid(info->ctrl, param)) 2950 return -ENOTSUPP; 2951 2952 if (rockchip_get_pull(bank, pin - bank->pin_base) != param) 2953 return -EINVAL; 2954 2955 arg = 1; 2956 break; 2957 case PIN_CONFIG_OUTPUT: 2958 rc = rockchip_get_mux(bank, pin - bank->pin_base); 2959 if (rc != RK_FUNC_GPIO) 2960 return -EINVAL; 2961 2962 if (!gpio || !gpio->get) { 2963 arg = 0; 2964 break; 2965 } 2966 2967 rc = gpio->get(gpio, pin - bank->pin_base); 2968 if (rc < 0) 2969 return rc; 2970 2971 arg = rc ? 1 : 0; 2972 break; 2973 case PIN_CONFIG_DRIVE_STRENGTH: 2974 /* rk3288 is the first with per-pin drive-strength */ 2975 if (!info->ctrl->drv_calc_reg) 2976 return -ENOTSUPP; 2977 2978 rc = rockchip_get_drive_perpin(bank, pin - bank->pin_base); 2979 if (rc < 0) 2980 return rc; 2981 2982 arg = rc; 2983 break; 2984 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 2985 if (!info->ctrl->schmitt_calc_reg) 2986 return -ENOTSUPP; 2987 2988 rc = rockchip_get_schmitt(bank, pin - bank->pin_base); 2989 if (rc < 0) 2990 return rc; 2991 2992 arg = rc; 2993 break; 2994 default: 2995 return -ENOTSUPP; 2996 break; 2997 } 2998 2999 *config = pinconf_to_config_packed(param, arg); 3000 3001 return 0; 3002 } 3003 3004 static const struct pinconf_ops rockchip_pinconf_ops = { 3005 .pin_config_get = rockchip_pinconf_get, 3006 .pin_config_set = rockchip_pinconf_set, 3007 .is_generic = true, 3008 }; 3009 3010 static const struct of_device_id rockchip_bank_match[] = { 3011 { .compatible = "rockchip,gpio-bank" }, 3012 { .compatible = "rockchip,rk3188-gpio-bank0" }, 3013 {}, 3014 }; 3015 3016 static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info, 3017 struct device_node *np) 3018 { 3019 struct device_node *child; 3020 3021 for_each_child_of_node(np, child) { 3022 if (of_match_node(rockchip_bank_match, child)) 3023 continue; 3024 3025 info->nfunctions++; 3026 info->ngroups += of_get_child_count(child); 3027 } 3028 } 3029 3030 static int rockchip_pinctrl_parse_groups(struct device_node *np, 3031 struct rockchip_pin_group *grp, 3032 struct rockchip_pinctrl *info, 3033 u32 index) 3034 { 3035 struct device *dev = info->dev; 3036 struct rockchip_pin_bank *bank; 3037 int size; 3038 const __be32 *list; 3039 int num; 3040 int i, j; 3041 int ret; 3042 3043 dev_dbg(dev, "group(%d): %pOFn\n", index, np); 3044 3045 /* Initialise group */ 3046 grp->name = np->name; 3047 3048 /* 3049 * the binding format is rockchip,pins = <bank pin mux CONFIG>, 3050 * do sanity check and calculate pins number 3051 */ 3052 list = of_get_property(np, "rockchip,pins", &size); 3053 /* we do not check return since it's safe node passed down */ 3054 size /= sizeof(*list); 3055 if (!size || size % 4) 3056 return dev_err_probe(dev, -EINVAL, "wrong pins number or pins and configs should be by 4\n"); 3057 3058 grp->npins = size / 4; 3059 3060 grp->pins = devm_kcalloc(dev, grp->npins, sizeof(*grp->pins), GFP_KERNEL); 3061 grp->data = devm_kcalloc(dev, grp->npins, sizeof(*grp->data), GFP_KERNEL); 3062 if (!grp->pins || !grp->data) 3063 return -ENOMEM; 3064 3065 for (i = 0, j = 0; i < size; i += 4, j++) { 3066 const __be32 *phandle; 3067 struct device_node *np_config; 3068 3069 num = be32_to_cpu(*list++); 3070 bank = bank_num_to_bank(info, num); 3071 if (IS_ERR(bank)) 3072 return PTR_ERR(bank); 3073 3074 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++); 3075 grp->data[j].func = be32_to_cpu(*list++); 3076 3077 phandle = list++; 3078 if (!phandle) 3079 return -EINVAL; 3080 3081 np_config = of_find_node_by_phandle(be32_to_cpup(phandle)); 3082 ret = pinconf_generic_parse_dt_config(np_config, NULL, 3083 &grp->data[j].configs, &grp->data[j].nconfigs); 3084 of_node_put(np_config); 3085 if (ret) 3086 return ret; 3087 } 3088 3089 return 0; 3090 } 3091 3092 static int rockchip_pinctrl_parse_functions(struct device_node *np, 3093 struct rockchip_pinctrl *info, 3094 u32 index) 3095 { 3096 struct device *dev = info->dev; 3097 struct device_node *child; 3098 struct rockchip_pmx_func *func; 3099 struct rockchip_pin_group *grp; 3100 int ret; 3101 static u32 grp_index; 3102 u32 i = 0; 3103 3104 dev_dbg(dev, "parse function(%d): %pOFn\n", index, np); 3105 3106 func = &info->functions[index]; 3107 3108 /* Initialise function */ 3109 func->name = np->name; 3110 func->ngroups = of_get_child_count(np); 3111 if (func->ngroups <= 0) 3112 return 0; 3113 3114 func->groups = devm_kcalloc(dev, func->ngroups, sizeof(*func->groups), GFP_KERNEL); 3115 if (!func->groups) 3116 return -ENOMEM; 3117 3118 for_each_child_of_node(np, child) { 3119 func->groups[i] = child->name; 3120 grp = &info->groups[grp_index++]; 3121 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++); 3122 if (ret) { 3123 of_node_put(child); 3124 return ret; 3125 } 3126 } 3127 3128 return 0; 3129 } 3130 3131 static int rockchip_pinctrl_parse_dt(struct platform_device *pdev, 3132 struct rockchip_pinctrl *info) 3133 { 3134 struct device *dev = &pdev->dev; 3135 struct device_node *np = dev->of_node; 3136 struct device_node *child; 3137 int ret; 3138 int i; 3139 3140 rockchip_pinctrl_child_count(info, np); 3141 3142 dev_dbg(dev, "nfunctions = %d\n", info->nfunctions); 3143 dev_dbg(dev, "ngroups = %d\n", info->ngroups); 3144 3145 info->functions = devm_kcalloc(dev, info->nfunctions, sizeof(*info->functions), GFP_KERNEL); 3146 if (!info->functions) 3147 return -ENOMEM; 3148 3149 info->groups = devm_kcalloc(dev, info->ngroups, sizeof(*info->groups), GFP_KERNEL); 3150 if (!info->groups) 3151 return -ENOMEM; 3152 3153 i = 0; 3154 3155 for_each_child_of_node(np, child) { 3156 if (of_match_node(rockchip_bank_match, child)) 3157 continue; 3158 3159 ret = rockchip_pinctrl_parse_functions(child, info, i++); 3160 if (ret) { 3161 dev_err(dev, "failed to parse function\n"); 3162 of_node_put(child); 3163 return ret; 3164 } 3165 } 3166 3167 return 0; 3168 } 3169 3170 static int rockchip_pinctrl_register(struct platform_device *pdev, 3171 struct rockchip_pinctrl *info) 3172 { 3173 struct pinctrl_desc *ctrldesc = &info->pctl; 3174 struct pinctrl_pin_desc *pindesc, *pdesc; 3175 struct rockchip_pin_bank *pin_bank; 3176 struct device *dev = &pdev->dev; 3177 char **pin_names; 3178 int pin, bank, ret; 3179 int k; 3180 3181 ctrldesc->name = "rockchip-pinctrl"; 3182 ctrldesc->owner = THIS_MODULE; 3183 ctrldesc->pctlops = &rockchip_pctrl_ops; 3184 ctrldesc->pmxops = &rockchip_pmx_ops; 3185 ctrldesc->confops = &rockchip_pinconf_ops; 3186 3187 pindesc = devm_kcalloc(dev, info->ctrl->nr_pins, sizeof(*pindesc), GFP_KERNEL); 3188 if (!pindesc) 3189 return -ENOMEM; 3190 3191 ctrldesc->pins = pindesc; 3192 ctrldesc->npins = info->ctrl->nr_pins; 3193 3194 pdesc = pindesc; 3195 for (bank = 0, k = 0; bank < info->ctrl->nr_banks; bank++) { 3196 pin_bank = &info->ctrl->pin_banks[bank]; 3197 3198 pin_names = devm_kasprintf_strarray(dev, pin_bank->name, pin_bank->nr_pins); 3199 if (IS_ERR(pin_names)) 3200 return PTR_ERR(pin_names); 3201 3202 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) { 3203 pdesc->number = k; 3204 pdesc->name = pin_names[pin]; 3205 pdesc++; 3206 } 3207 3208 INIT_LIST_HEAD(&pin_bank->deferred_pins); 3209 mutex_init(&pin_bank->deferred_lock); 3210 } 3211 3212 ret = rockchip_pinctrl_parse_dt(pdev, info); 3213 if (ret) 3214 return ret; 3215 3216 info->pctl_dev = devm_pinctrl_register(dev, ctrldesc, info); 3217 if (IS_ERR(info->pctl_dev)) 3218 return dev_err_probe(dev, PTR_ERR(info->pctl_dev), "could not register pinctrl driver\n"); 3219 3220 return 0; 3221 } 3222 3223 static const struct of_device_id rockchip_pinctrl_dt_match[]; 3224 3225 /* retrieve the soc specific data */ 3226 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data( 3227 struct rockchip_pinctrl *d, 3228 struct platform_device *pdev) 3229 { 3230 struct device *dev = &pdev->dev; 3231 struct device_node *node = dev->of_node; 3232 const struct of_device_id *match; 3233 struct rockchip_pin_ctrl *ctrl; 3234 struct rockchip_pin_bank *bank; 3235 int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j; 3236 3237 match = of_match_node(rockchip_pinctrl_dt_match, node); 3238 ctrl = (struct rockchip_pin_ctrl *)match->data; 3239 3240 grf_offs = ctrl->grf_mux_offset; 3241 pmu_offs = ctrl->pmu_mux_offset; 3242 drv_pmu_offs = ctrl->pmu_drv_offset; 3243 drv_grf_offs = ctrl->grf_drv_offset; 3244 bank = ctrl->pin_banks; 3245 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 3246 int bank_pins = 0; 3247 3248 raw_spin_lock_init(&bank->slock); 3249 bank->drvdata = d; 3250 bank->pin_base = ctrl->nr_pins; 3251 ctrl->nr_pins += bank->nr_pins; 3252 3253 /* calculate iomux and drv offsets */ 3254 for (j = 0; j < 4; j++) { 3255 struct rockchip_iomux *iom = &bank->iomux[j]; 3256 struct rockchip_drv *drv = &bank->drv[j]; 3257 int inc; 3258 3259 if (bank_pins >= bank->nr_pins) 3260 break; 3261 3262 /* preset iomux offset value, set new start value */ 3263 if (iom->offset >= 0) { 3264 if ((iom->type & IOMUX_SOURCE_PMU) || 3265 (iom->type & IOMUX_L_SOURCE_PMU)) 3266 pmu_offs = iom->offset; 3267 else 3268 grf_offs = iom->offset; 3269 } else { /* set current iomux offset */ 3270 iom->offset = ((iom->type & IOMUX_SOURCE_PMU) || 3271 (iom->type & IOMUX_L_SOURCE_PMU)) ? 3272 pmu_offs : grf_offs; 3273 } 3274 3275 /* preset drv offset value, set new start value */ 3276 if (drv->offset >= 0) { 3277 if (iom->type & IOMUX_SOURCE_PMU) 3278 drv_pmu_offs = drv->offset; 3279 else 3280 drv_grf_offs = drv->offset; 3281 } else { /* set current drv offset */ 3282 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ? 3283 drv_pmu_offs : drv_grf_offs; 3284 } 3285 3286 dev_dbg(dev, "bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n", 3287 i, j, iom->offset, drv->offset); 3288 3289 /* 3290 * Increase offset according to iomux width. 3291 * 4bit iomux'es are spread over two registers. 3292 */ 3293 inc = (iom->type & (IOMUX_WIDTH_4BIT | 3294 IOMUX_WIDTH_3BIT | 3295 IOMUX_WIDTH_2BIT)) ? 8 : 4; 3296 if ((iom->type & IOMUX_SOURCE_PMU) || (iom->type & IOMUX_L_SOURCE_PMU)) 3297 pmu_offs += inc; 3298 else 3299 grf_offs += inc; 3300 3301 /* 3302 * Increase offset according to drv width. 3303 * 3bit drive-strenth'es are spread over two registers. 3304 */ 3305 if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) || 3306 (drv->drv_type == DRV_TYPE_IO_3V3_ONLY)) 3307 inc = 8; 3308 else 3309 inc = 4; 3310 3311 if (iom->type & IOMUX_SOURCE_PMU) 3312 drv_pmu_offs += inc; 3313 else 3314 drv_grf_offs += inc; 3315 3316 bank_pins += 8; 3317 } 3318 3319 /* calculate the per-bank recalced_mask */ 3320 for (j = 0; j < ctrl->niomux_recalced; j++) { 3321 int pin = 0; 3322 3323 if (ctrl->iomux_recalced[j].num == bank->bank_num) { 3324 pin = ctrl->iomux_recalced[j].pin; 3325 bank->recalced_mask |= BIT(pin); 3326 } 3327 } 3328 3329 /* calculate the per-bank route_mask */ 3330 for (j = 0; j < ctrl->niomux_routes; j++) { 3331 int pin = 0; 3332 3333 if (ctrl->iomux_routes[j].bank_num == bank->bank_num) { 3334 pin = ctrl->iomux_routes[j].pin; 3335 bank->route_mask |= BIT(pin); 3336 } 3337 } 3338 } 3339 3340 return ctrl; 3341 } 3342 3343 #define RK3288_GRF_GPIO6C_IOMUX 0x64 3344 #define GPIO6C6_SEL_WRITE_ENABLE BIT(28) 3345 3346 static u32 rk3288_grf_gpio6c_iomux; 3347 3348 static int __maybe_unused rockchip_pinctrl_suspend(struct device *dev) 3349 { 3350 struct rockchip_pinctrl *info = dev_get_drvdata(dev); 3351 int ret = pinctrl_force_sleep(info->pctl_dev); 3352 3353 if (ret) 3354 return ret; 3355 3356 /* 3357 * RK3288 GPIO6_C6 mux would be modified by Maskrom when resume, so save 3358 * the setting here, and restore it at resume. 3359 */ 3360 if (info->ctrl->type == RK3288) { 3361 ret = regmap_read(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX, 3362 &rk3288_grf_gpio6c_iomux); 3363 if (ret) { 3364 pinctrl_force_default(info->pctl_dev); 3365 return ret; 3366 } 3367 } 3368 3369 return 0; 3370 } 3371 3372 static int __maybe_unused rockchip_pinctrl_resume(struct device *dev) 3373 { 3374 struct rockchip_pinctrl *info = dev_get_drvdata(dev); 3375 int ret; 3376 3377 if (info->ctrl->type == RK3288) { 3378 ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX, 3379 rk3288_grf_gpio6c_iomux | 3380 GPIO6C6_SEL_WRITE_ENABLE); 3381 if (ret) 3382 return ret; 3383 } 3384 3385 return pinctrl_force_default(info->pctl_dev); 3386 } 3387 3388 static SIMPLE_DEV_PM_OPS(rockchip_pinctrl_dev_pm_ops, rockchip_pinctrl_suspend, 3389 rockchip_pinctrl_resume); 3390 3391 static int rockchip_pinctrl_probe(struct platform_device *pdev) 3392 { 3393 struct rockchip_pinctrl *info; 3394 struct device *dev = &pdev->dev; 3395 struct device_node *np = dev->of_node, *node; 3396 struct rockchip_pin_ctrl *ctrl; 3397 struct resource *res; 3398 void __iomem *base; 3399 int ret; 3400 3401 if (!dev->of_node) 3402 return dev_err_probe(dev, -ENODEV, "device tree node not found\n"); 3403 3404 info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL); 3405 if (!info) 3406 return -ENOMEM; 3407 3408 info->dev = dev; 3409 3410 ctrl = rockchip_pinctrl_get_soc_data(info, pdev); 3411 if (!ctrl) 3412 return dev_err_probe(dev, -EINVAL, "driver data not available\n"); 3413 info->ctrl = ctrl; 3414 3415 node = of_parse_phandle(np, "rockchip,grf", 0); 3416 if (node) { 3417 info->regmap_base = syscon_node_to_regmap(node); 3418 of_node_put(node); 3419 if (IS_ERR(info->regmap_base)) 3420 return PTR_ERR(info->regmap_base); 3421 } else { 3422 base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 3423 if (IS_ERR(base)) 3424 return PTR_ERR(base); 3425 3426 rockchip_regmap_config.max_register = resource_size(res) - 4; 3427 rockchip_regmap_config.name = "rockchip,pinctrl"; 3428 info->regmap_base = 3429 devm_regmap_init_mmio(dev, base, &rockchip_regmap_config); 3430 3431 /* to check for the old dt-bindings */ 3432 info->reg_size = resource_size(res); 3433 3434 /* Honor the old binding, with pull registers as 2nd resource */ 3435 if (ctrl->type == RK3188 && info->reg_size < 0x200) { 3436 base = devm_platform_get_and_ioremap_resource(pdev, 1, &res); 3437 if (IS_ERR(base)) 3438 return PTR_ERR(base); 3439 3440 rockchip_regmap_config.max_register = resource_size(res) - 4; 3441 rockchip_regmap_config.name = "rockchip,pinctrl-pull"; 3442 info->regmap_pull = 3443 devm_regmap_init_mmio(dev, base, &rockchip_regmap_config); 3444 } 3445 } 3446 3447 /* try to find the optional reference to the pmu syscon */ 3448 node = of_parse_phandle(np, "rockchip,pmu", 0); 3449 if (node) { 3450 info->regmap_pmu = syscon_node_to_regmap(node); 3451 of_node_put(node); 3452 if (IS_ERR(info->regmap_pmu)) 3453 return PTR_ERR(info->regmap_pmu); 3454 } 3455 3456 ret = rockchip_pinctrl_register(pdev, info); 3457 if (ret) 3458 return ret; 3459 3460 platform_set_drvdata(pdev, info); 3461 3462 ret = of_platform_populate(np, NULL, NULL, &pdev->dev); 3463 if (ret) 3464 return dev_err_probe(dev, ret, "failed to register gpio device\n"); 3465 3466 return 0; 3467 } 3468 3469 static int rockchip_pinctrl_remove(struct platform_device *pdev) 3470 { 3471 struct rockchip_pinctrl *info = platform_get_drvdata(pdev); 3472 struct rockchip_pin_bank *bank; 3473 struct rockchip_pin_deferred *cfg; 3474 int i; 3475 3476 of_platform_depopulate(&pdev->dev); 3477 3478 for (i = 0; i < info->ctrl->nr_banks; i++) { 3479 bank = &info->ctrl->pin_banks[i]; 3480 3481 mutex_lock(&bank->deferred_lock); 3482 while (!list_empty(&bank->deferred_pins)) { 3483 cfg = list_first_entry(&bank->deferred_pins, 3484 struct rockchip_pin_deferred, head); 3485 list_del(&cfg->head); 3486 kfree(cfg); 3487 } 3488 mutex_unlock(&bank->deferred_lock); 3489 } 3490 3491 return 0; 3492 } 3493 3494 static struct rockchip_pin_bank px30_pin_banks[] = { 3495 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, 3496 IOMUX_SOURCE_PMU, 3497 IOMUX_SOURCE_PMU, 3498 IOMUX_SOURCE_PMU 3499 ), 3500 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT, 3501 IOMUX_WIDTH_4BIT, 3502 IOMUX_WIDTH_4BIT, 3503 IOMUX_WIDTH_4BIT 3504 ), 3505 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT, 3506 IOMUX_WIDTH_4BIT, 3507 IOMUX_WIDTH_4BIT, 3508 IOMUX_WIDTH_4BIT 3509 ), 3510 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT, 3511 IOMUX_WIDTH_4BIT, 3512 IOMUX_WIDTH_4BIT, 3513 IOMUX_WIDTH_4BIT 3514 ), 3515 }; 3516 3517 static struct rockchip_pin_ctrl px30_pin_ctrl = { 3518 .pin_banks = px30_pin_banks, 3519 .nr_banks = ARRAY_SIZE(px30_pin_banks), 3520 .label = "PX30-GPIO", 3521 .type = PX30, 3522 .grf_mux_offset = 0x0, 3523 .pmu_mux_offset = 0x0, 3524 .iomux_routes = px30_mux_route_data, 3525 .niomux_routes = ARRAY_SIZE(px30_mux_route_data), 3526 .pull_calc_reg = px30_calc_pull_reg_and_bit, 3527 .drv_calc_reg = px30_calc_drv_reg_and_bit, 3528 .schmitt_calc_reg = px30_calc_schmitt_reg_and_bit, 3529 }; 3530 3531 static struct rockchip_pin_bank rv1108_pin_banks[] = { 3532 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, 3533 IOMUX_SOURCE_PMU, 3534 IOMUX_SOURCE_PMU, 3535 IOMUX_SOURCE_PMU), 3536 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0), 3537 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0), 3538 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0), 3539 }; 3540 3541 static struct rockchip_pin_ctrl rv1108_pin_ctrl = { 3542 .pin_banks = rv1108_pin_banks, 3543 .nr_banks = ARRAY_SIZE(rv1108_pin_banks), 3544 .label = "RV1108-GPIO", 3545 .type = RV1108, 3546 .grf_mux_offset = 0x10, 3547 .pmu_mux_offset = 0x0, 3548 .iomux_recalced = rv1108_mux_recalced_data, 3549 .niomux_recalced = ARRAY_SIZE(rv1108_mux_recalced_data), 3550 .pull_calc_reg = rv1108_calc_pull_reg_and_bit, 3551 .drv_calc_reg = rv1108_calc_drv_reg_and_bit, 3552 .schmitt_calc_reg = rv1108_calc_schmitt_reg_and_bit, 3553 }; 3554 3555 static struct rockchip_pin_bank rv1126_pin_banks[] = { 3556 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 3557 IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU, 3558 IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU, 3559 IOMUX_WIDTH_4BIT | IOMUX_L_SOURCE_PMU, 3560 IOMUX_WIDTH_4BIT), 3561 PIN_BANK_IOMUX_FLAGS_OFFSET(1, 32, "gpio1", 3562 IOMUX_WIDTH_4BIT, 3563 IOMUX_WIDTH_4BIT, 3564 IOMUX_WIDTH_4BIT, 3565 IOMUX_WIDTH_4BIT, 3566 0x10010, 0x10018, 0x10020, 0x10028), 3567 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 3568 IOMUX_WIDTH_4BIT, 3569 IOMUX_WIDTH_4BIT, 3570 IOMUX_WIDTH_4BIT, 3571 IOMUX_WIDTH_4BIT), 3572 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 3573 IOMUX_WIDTH_4BIT, 3574 IOMUX_WIDTH_4BIT, 3575 IOMUX_WIDTH_4BIT, 3576 IOMUX_WIDTH_4BIT), 3577 PIN_BANK_IOMUX_FLAGS(4, 2, "gpio4", 3578 IOMUX_WIDTH_4BIT, 0, 0, 0), 3579 }; 3580 3581 static struct rockchip_pin_ctrl rv1126_pin_ctrl = { 3582 .pin_banks = rv1126_pin_banks, 3583 .nr_banks = ARRAY_SIZE(rv1126_pin_banks), 3584 .label = "RV1126-GPIO", 3585 .type = RV1126, 3586 .grf_mux_offset = 0x10004, /* mux offset from GPIO0_D0 */ 3587 .pmu_mux_offset = 0x0, 3588 .iomux_routes = rv1126_mux_route_data, 3589 .niomux_routes = ARRAY_SIZE(rv1126_mux_route_data), 3590 .iomux_recalced = rv1126_mux_recalced_data, 3591 .niomux_recalced = ARRAY_SIZE(rv1126_mux_recalced_data), 3592 .pull_calc_reg = rv1126_calc_pull_reg_and_bit, 3593 .drv_calc_reg = rv1126_calc_drv_reg_and_bit, 3594 .schmitt_calc_reg = rv1126_calc_schmitt_reg_and_bit, 3595 }; 3596 3597 static struct rockchip_pin_bank rk2928_pin_banks[] = { 3598 PIN_BANK(0, 32, "gpio0"), 3599 PIN_BANK(1, 32, "gpio1"), 3600 PIN_BANK(2, 32, "gpio2"), 3601 PIN_BANK(3, 32, "gpio3"), 3602 }; 3603 3604 static struct rockchip_pin_ctrl rk2928_pin_ctrl = { 3605 .pin_banks = rk2928_pin_banks, 3606 .nr_banks = ARRAY_SIZE(rk2928_pin_banks), 3607 .label = "RK2928-GPIO", 3608 .type = RK2928, 3609 .grf_mux_offset = 0xa8, 3610 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 3611 }; 3612 3613 static struct rockchip_pin_bank rk3036_pin_banks[] = { 3614 PIN_BANK(0, 32, "gpio0"), 3615 PIN_BANK(1, 32, "gpio1"), 3616 PIN_BANK(2, 32, "gpio2"), 3617 }; 3618 3619 static struct rockchip_pin_ctrl rk3036_pin_ctrl = { 3620 .pin_banks = rk3036_pin_banks, 3621 .nr_banks = ARRAY_SIZE(rk3036_pin_banks), 3622 .label = "RK3036-GPIO", 3623 .type = RK2928, 3624 .grf_mux_offset = 0xa8, 3625 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 3626 }; 3627 3628 static struct rockchip_pin_bank rk3066a_pin_banks[] = { 3629 PIN_BANK(0, 32, "gpio0"), 3630 PIN_BANK(1, 32, "gpio1"), 3631 PIN_BANK(2, 32, "gpio2"), 3632 PIN_BANK(3, 32, "gpio3"), 3633 PIN_BANK(4, 32, "gpio4"), 3634 PIN_BANK(6, 16, "gpio6"), 3635 }; 3636 3637 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = { 3638 .pin_banks = rk3066a_pin_banks, 3639 .nr_banks = ARRAY_SIZE(rk3066a_pin_banks), 3640 .label = "RK3066a-GPIO", 3641 .type = RK2928, 3642 .grf_mux_offset = 0xa8, 3643 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 3644 }; 3645 3646 static struct rockchip_pin_bank rk3066b_pin_banks[] = { 3647 PIN_BANK(0, 32, "gpio0"), 3648 PIN_BANK(1, 32, "gpio1"), 3649 PIN_BANK(2, 32, "gpio2"), 3650 PIN_BANK(3, 32, "gpio3"), 3651 }; 3652 3653 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = { 3654 .pin_banks = rk3066b_pin_banks, 3655 .nr_banks = ARRAY_SIZE(rk3066b_pin_banks), 3656 .label = "RK3066b-GPIO", 3657 .type = RK3066B, 3658 .grf_mux_offset = 0x60, 3659 }; 3660 3661 static struct rockchip_pin_bank rk3128_pin_banks[] = { 3662 PIN_BANK(0, 32, "gpio0"), 3663 PIN_BANK(1, 32, "gpio1"), 3664 PIN_BANK(2, 32, "gpio2"), 3665 PIN_BANK(3, 32, "gpio3"), 3666 }; 3667 3668 static struct rockchip_pin_ctrl rk3128_pin_ctrl = { 3669 .pin_banks = rk3128_pin_banks, 3670 .nr_banks = ARRAY_SIZE(rk3128_pin_banks), 3671 .label = "RK3128-GPIO", 3672 .type = RK3128, 3673 .grf_mux_offset = 0xa8, 3674 .iomux_recalced = rk3128_mux_recalced_data, 3675 .niomux_recalced = ARRAY_SIZE(rk3128_mux_recalced_data), 3676 .iomux_routes = rk3128_mux_route_data, 3677 .niomux_routes = ARRAY_SIZE(rk3128_mux_route_data), 3678 .pull_calc_reg = rk3128_calc_pull_reg_and_bit, 3679 }; 3680 3681 static struct rockchip_pin_bank rk3188_pin_banks[] = { 3682 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0), 3683 PIN_BANK(1, 32, "gpio1"), 3684 PIN_BANK(2, 32, "gpio2"), 3685 PIN_BANK(3, 32, "gpio3"), 3686 }; 3687 3688 static struct rockchip_pin_ctrl rk3188_pin_ctrl = { 3689 .pin_banks = rk3188_pin_banks, 3690 .nr_banks = ARRAY_SIZE(rk3188_pin_banks), 3691 .label = "RK3188-GPIO", 3692 .type = RK3188, 3693 .grf_mux_offset = 0x60, 3694 .iomux_routes = rk3188_mux_route_data, 3695 .niomux_routes = ARRAY_SIZE(rk3188_mux_route_data), 3696 .pull_calc_reg = rk3188_calc_pull_reg_and_bit, 3697 }; 3698 3699 static struct rockchip_pin_bank rk3228_pin_banks[] = { 3700 PIN_BANK(0, 32, "gpio0"), 3701 PIN_BANK(1, 32, "gpio1"), 3702 PIN_BANK(2, 32, "gpio2"), 3703 PIN_BANK(3, 32, "gpio3"), 3704 }; 3705 3706 static struct rockchip_pin_ctrl rk3228_pin_ctrl = { 3707 .pin_banks = rk3228_pin_banks, 3708 .nr_banks = ARRAY_SIZE(rk3228_pin_banks), 3709 .label = "RK3228-GPIO", 3710 .type = RK3288, 3711 .grf_mux_offset = 0x0, 3712 .iomux_routes = rk3228_mux_route_data, 3713 .niomux_routes = ARRAY_SIZE(rk3228_mux_route_data), 3714 .pull_calc_reg = rk3228_calc_pull_reg_and_bit, 3715 .drv_calc_reg = rk3228_calc_drv_reg_and_bit, 3716 }; 3717 3718 static struct rockchip_pin_bank rk3288_pin_banks[] = { 3719 PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU, 3720 IOMUX_SOURCE_PMU, 3721 IOMUX_SOURCE_PMU, 3722 IOMUX_UNROUTED 3723 ), 3724 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED, 3725 IOMUX_UNROUTED, 3726 IOMUX_UNROUTED, 3727 0 3728 ), 3729 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED), 3730 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT), 3731 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT, 3732 IOMUX_WIDTH_4BIT, 3733 0, 3734 0 3735 ), 3736 PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED, 3737 0, 3738 0, 3739 IOMUX_UNROUTED 3740 ), 3741 PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED), 3742 PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0, 3743 0, 3744 IOMUX_WIDTH_4BIT, 3745 IOMUX_UNROUTED 3746 ), 3747 PIN_BANK(8, 16, "gpio8"), 3748 }; 3749 3750 static struct rockchip_pin_ctrl rk3288_pin_ctrl = { 3751 .pin_banks = rk3288_pin_banks, 3752 .nr_banks = ARRAY_SIZE(rk3288_pin_banks), 3753 .label = "RK3288-GPIO", 3754 .type = RK3288, 3755 .grf_mux_offset = 0x0, 3756 .pmu_mux_offset = 0x84, 3757 .iomux_routes = rk3288_mux_route_data, 3758 .niomux_routes = ARRAY_SIZE(rk3288_mux_route_data), 3759 .pull_calc_reg = rk3288_calc_pull_reg_and_bit, 3760 .drv_calc_reg = rk3288_calc_drv_reg_and_bit, 3761 }; 3762 3763 static struct rockchip_pin_bank rk3308_pin_banks[] = { 3764 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_WIDTH_2BIT, 3765 IOMUX_WIDTH_2BIT, 3766 IOMUX_WIDTH_2BIT, 3767 IOMUX_WIDTH_2BIT), 3768 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_2BIT, 3769 IOMUX_WIDTH_2BIT, 3770 IOMUX_WIDTH_2BIT, 3771 IOMUX_WIDTH_2BIT), 3772 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_2BIT, 3773 IOMUX_WIDTH_2BIT, 3774 IOMUX_WIDTH_2BIT, 3775 IOMUX_WIDTH_2BIT), 3776 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_2BIT, 3777 IOMUX_WIDTH_2BIT, 3778 IOMUX_WIDTH_2BIT, 3779 IOMUX_WIDTH_2BIT), 3780 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_2BIT, 3781 IOMUX_WIDTH_2BIT, 3782 IOMUX_WIDTH_2BIT, 3783 IOMUX_WIDTH_2BIT), 3784 }; 3785 3786 static struct rockchip_pin_ctrl rk3308_pin_ctrl = { 3787 .pin_banks = rk3308_pin_banks, 3788 .nr_banks = ARRAY_SIZE(rk3308_pin_banks), 3789 .label = "RK3308-GPIO", 3790 .type = RK3308, 3791 .grf_mux_offset = 0x0, 3792 .iomux_recalced = rk3308_mux_recalced_data, 3793 .niomux_recalced = ARRAY_SIZE(rk3308_mux_recalced_data), 3794 .iomux_routes = rk3308_mux_route_data, 3795 .niomux_routes = ARRAY_SIZE(rk3308_mux_route_data), 3796 .pull_calc_reg = rk3308_calc_pull_reg_and_bit, 3797 .drv_calc_reg = rk3308_calc_drv_reg_and_bit, 3798 .schmitt_calc_reg = rk3308_calc_schmitt_reg_and_bit, 3799 }; 3800 3801 static struct rockchip_pin_bank rk3328_pin_banks[] = { 3802 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0), 3803 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0), 3804 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 3805 IOMUX_WIDTH_2BIT, 3806 IOMUX_WIDTH_3BIT, 3807 0), 3808 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 3809 IOMUX_WIDTH_3BIT, 3810 IOMUX_WIDTH_3BIT, 3811 0, 3812 0), 3813 }; 3814 3815 static struct rockchip_pin_ctrl rk3328_pin_ctrl = { 3816 .pin_banks = rk3328_pin_banks, 3817 .nr_banks = ARRAY_SIZE(rk3328_pin_banks), 3818 .label = "RK3328-GPIO", 3819 .type = RK3328, 3820 .grf_mux_offset = 0x0, 3821 .iomux_recalced = rk3328_mux_recalced_data, 3822 .niomux_recalced = ARRAY_SIZE(rk3328_mux_recalced_data), 3823 .iomux_routes = rk3328_mux_route_data, 3824 .niomux_routes = ARRAY_SIZE(rk3328_mux_route_data), 3825 .pull_calc_reg = rk3228_calc_pull_reg_and_bit, 3826 .drv_calc_reg = rk3228_calc_drv_reg_and_bit, 3827 .schmitt_calc_reg = rk3328_calc_schmitt_reg_and_bit, 3828 }; 3829 3830 static struct rockchip_pin_bank rk3368_pin_banks[] = { 3831 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, 3832 IOMUX_SOURCE_PMU, 3833 IOMUX_SOURCE_PMU, 3834 IOMUX_SOURCE_PMU 3835 ), 3836 PIN_BANK(1, 32, "gpio1"), 3837 PIN_BANK(2, 32, "gpio2"), 3838 PIN_BANK(3, 32, "gpio3"), 3839 }; 3840 3841 static struct rockchip_pin_ctrl rk3368_pin_ctrl = { 3842 .pin_banks = rk3368_pin_banks, 3843 .nr_banks = ARRAY_SIZE(rk3368_pin_banks), 3844 .label = "RK3368-GPIO", 3845 .type = RK3368, 3846 .grf_mux_offset = 0x0, 3847 .pmu_mux_offset = 0x0, 3848 .pull_calc_reg = rk3368_calc_pull_reg_and_bit, 3849 .drv_calc_reg = rk3368_calc_drv_reg_and_bit, 3850 }; 3851 3852 static struct rockchip_pin_bank rk3399_pin_banks[] = { 3853 PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0", 3854 IOMUX_SOURCE_PMU, 3855 IOMUX_SOURCE_PMU, 3856 IOMUX_SOURCE_PMU, 3857 IOMUX_SOURCE_PMU, 3858 DRV_TYPE_IO_1V8_ONLY, 3859 DRV_TYPE_IO_1V8_ONLY, 3860 DRV_TYPE_IO_DEFAULT, 3861 DRV_TYPE_IO_DEFAULT, 3862 0x80, 3863 0x88, 3864 -1, 3865 -1, 3866 PULL_TYPE_IO_1V8_ONLY, 3867 PULL_TYPE_IO_1V8_ONLY, 3868 PULL_TYPE_IO_DEFAULT, 3869 PULL_TYPE_IO_DEFAULT 3870 ), 3871 PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU, 3872 IOMUX_SOURCE_PMU, 3873 IOMUX_SOURCE_PMU, 3874 IOMUX_SOURCE_PMU, 3875 DRV_TYPE_IO_1V8_OR_3V0, 3876 DRV_TYPE_IO_1V8_OR_3V0, 3877 DRV_TYPE_IO_1V8_OR_3V0, 3878 DRV_TYPE_IO_1V8_OR_3V0, 3879 0xa0, 3880 0xa8, 3881 0xb0, 3882 0xb8 3883 ), 3884 PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0, 3885 DRV_TYPE_IO_1V8_OR_3V0, 3886 DRV_TYPE_IO_1V8_ONLY, 3887 DRV_TYPE_IO_1V8_ONLY, 3888 PULL_TYPE_IO_DEFAULT, 3889 PULL_TYPE_IO_DEFAULT, 3890 PULL_TYPE_IO_1V8_ONLY, 3891 PULL_TYPE_IO_1V8_ONLY 3892 ), 3893 PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY, 3894 DRV_TYPE_IO_3V3_ONLY, 3895 DRV_TYPE_IO_3V3_ONLY, 3896 DRV_TYPE_IO_1V8_OR_3V0 3897 ), 3898 PIN_BANK_DRV_FLAGS(4, 32, "gpio4", DRV_TYPE_IO_1V8_OR_3V0, 3899 DRV_TYPE_IO_1V8_3V0_AUTO, 3900 DRV_TYPE_IO_1V8_OR_3V0, 3901 DRV_TYPE_IO_1V8_OR_3V0 3902 ), 3903 }; 3904 3905 static struct rockchip_pin_ctrl rk3399_pin_ctrl = { 3906 .pin_banks = rk3399_pin_banks, 3907 .nr_banks = ARRAY_SIZE(rk3399_pin_banks), 3908 .label = "RK3399-GPIO", 3909 .type = RK3399, 3910 .grf_mux_offset = 0xe000, 3911 .pmu_mux_offset = 0x0, 3912 .grf_drv_offset = 0xe100, 3913 .pmu_drv_offset = 0x80, 3914 .iomux_routes = rk3399_mux_route_data, 3915 .niomux_routes = ARRAY_SIZE(rk3399_mux_route_data), 3916 .pull_calc_reg = rk3399_calc_pull_reg_and_bit, 3917 .drv_calc_reg = rk3399_calc_drv_reg_and_bit, 3918 }; 3919 3920 static struct rockchip_pin_bank rk3568_pin_banks[] = { 3921 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT, 3922 IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT, 3923 IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT, 3924 IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT), 3925 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT, 3926 IOMUX_WIDTH_4BIT, 3927 IOMUX_WIDTH_4BIT, 3928 IOMUX_WIDTH_4BIT), 3929 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT, 3930 IOMUX_WIDTH_4BIT, 3931 IOMUX_WIDTH_4BIT, 3932 IOMUX_WIDTH_4BIT), 3933 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT, 3934 IOMUX_WIDTH_4BIT, 3935 IOMUX_WIDTH_4BIT, 3936 IOMUX_WIDTH_4BIT), 3937 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT, 3938 IOMUX_WIDTH_4BIT, 3939 IOMUX_WIDTH_4BIT, 3940 IOMUX_WIDTH_4BIT), 3941 }; 3942 3943 static struct rockchip_pin_ctrl rk3568_pin_ctrl = { 3944 .pin_banks = rk3568_pin_banks, 3945 .nr_banks = ARRAY_SIZE(rk3568_pin_banks), 3946 .label = "RK3568-GPIO", 3947 .type = RK3568, 3948 .grf_mux_offset = 0x0, 3949 .pmu_mux_offset = 0x0, 3950 .grf_drv_offset = 0x0200, 3951 .pmu_drv_offset = 0x0070, 3952 .iomux_routes = rk3568_mux_route_data, 3953 .niomux_routes = ARRAY_SIZE(rk3568_mux_route_data), 3954 .pull_calc_reg = rk3568_calc_pull_reg_and_bit, 3955 .drv_calc_reg = rk3568_calc_drv_reg_and_bit, 3956 .schmitt_calc_reg = rk3568_calc_schmitt_reg_and_bit, 3957 }; 3958 3959 static struct rockchip_pin_bank rk3588_pin_banks[] = { 3960 RK3588_PIN_BANK_FLAGS(0, 32, "gpio0", 3961 IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY), 3962 RK3588_PIN_BANK_FLAGS(1, 32, "gpio1", 3963 IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY), 3964 RK3588_PIN_BANK_FLAGS(2, 32, "gpio2", 3965 IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY), 3966 RK3588_PIN_BANK_FLAGS(3, 32, "gpio3", 3967 IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY), 3968 RK3588_PIN_BANK_FLAGS(4, 32, "gpio4", 3969 IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY), 3970 }; 3971 3972 static struct rockchip_pin_ctrl rk3588_pin_ctrl = { 3973 .pin_banks = rk3588_pin_banks, 3974 .nr_banks = ARRAY_SIZE(rk3588_pin_banks), 3975 .label = "RK3588-GPIO", 3976 .type = RK3588, 3977 .pull_calc_reg = rk3588_calc_pull_reg_and_bit, 3978 .drv_calc_reg = rk3588_calc_drv_reg_and_bit, 3979 .schmitt_calc_reg = rk3588_calc_schmitt_reg_and_bit, 3980 }; 3981 3982 static const struct of_device_id rockchip_pinctrl_dt_match[] = { 3983 { .compatible = "rockchip,px30-pinctrl", 3984 .data = &px30_pin_ctrl }, 3985 { .compatible = "rockchip,rv1108-pinctrl", 3986 .data = &rv1108_pin_ctrl }, 3987 { .compatible = "rockchip,rv1126-pinctrl", 3988 .data = &rv1126_pin_ctrl }, 3989 { .compatible = "rockchip,rk2928-pinctrl", 3990 .data = &rk2928_pin_ctrl }, 3991 { .compatible = "rockchip,rk3036-pinctrl", 3992 .data = &rk3036_pin_ctrl }, 3993 { .compatible = "rockchip,rk3066a-pinctrl", 3994 .data = &rk3066a_pin_ctrl }, 3995 { .compatible = "rockchip,rk3066b-pinctrl", 3996 .data = &rk3066b_pin_ctrl }, 3997 { .compatible = "rockchip,rk3128-pinctrl", 3998 .data = (void *)&rk3128_pin_ctrl }, 3999 { .compatible = "rockchip,rk3188-pinctrl", 4000 .data = &rk3188_pin_ctrl }, 4001 { .compatible = "rockchip,rk3228-pinctrl", 4002 .data = &rk3228_pin_ctrl }, 4003 { .compatible = "rockchip,rk3288-pinctrl", 4004 .data = &rk3288_pin_ctrl }, 4005 { .compatible = "rockchip,rk3308-pinctrl", 4006 .data = &rk3308_pin_ctrl }, 4007 { .compatible = "rockchip,rk3328-pinctrl", 4008 .data = &rk3328_pin_ctrl }, 4009 { .compatible = "rockchip,rk3368-pinctrl", 4010 .data = &rk3368_pin_ctrl }, 4011 { .compatible = "rockchip,rk3399-pinctrl", 4012 .data = &rk3399_pin_ctrl }, 4013 { .compatible = "rockchip,rk3568-pinctrl", 4014 .data = &rk3568_pin_ctrl }, 4015 { .compatible = "rockchip,rk3588-pinctrl", 4016 .data = &rk3588_pin_ctrl }, 4017 {}, 4018 }; 4019 4020 static struct platform_driver rockchip_pinctrl_driver = { 4021 .probe = rockchip_pinctrl_probe, 4022 .remove = rockchip_pinctrl_remove, 4023 .driver = { 4024 .name = "rockchip-pinctrl", 4025 .pm = &rockchip_pinctrl_dev_pm_ops, 4026 .of_match_table = rockchip_pinctrl_dt_match, 4027 }, 4028 }; 4029 4030 static int __init rockchip_pinctrl_drv_register(void) 4031 { 4032 return platform_driver_register(&rockchip_pinctrl_driver); 4033 } 4034 postcore_initcall(rockchip_pinctrl_drv_register); 4035 4036 static void __exit rockchip_pinctrl_drv_unregister(void) 4037 { 4038 platform_driver_unregister(&rockchip_pinctrl_driver); 4039 } 4040 module_exit(rockchip_pinctrl_drv_unregister); 4041 4042 MODULE_DESCRIPTION("ROCKCHIP Pin Controller Driver"); 4043 MODULE_LICENSE("GPL"); 4044 MODULE_ALIAS("platform:pinctrl-rockchip"); 4045 MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match); 4046