1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Pinctrl driver for Rockchip SoCs 4 * 5 * Copyright (c) 2013 MundoReader S.L. 6 * Author: Heiko Stuebner <heiko@sntech.de> 7 * 8 * With some ideas taken from pinctrl-samsung: 9 * Copyright (c) 2012 Samsung Electronics Co., Ltd. 10 * http://www.samsung.com 11 * Copyright (c) 2012 Linaro Ltd 12 * https://www.linaro.org 13 * 14 * and pinctrl-at91: 15 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> 16 */ 17 18 #include <linux/init.h> 19 #include <linux/module.h> 20 #include <linux/platform_device.h> 21 #include <linux/io.h> 22 #include <linux/bitops.h> 23 #include <linux/gpio/driver.h> 24 #include <linux/of_address.h> 25 #include <linux/of_device.h> 26 #include <linux/of_irq.h> 27 #include <linux/pinctrl/machine.h> 28 #include <linux/pinctrl/pinconf.h> 29 #include <linux/pinctrl/pinctrl.h> 30 #include <linux/pinctrl/pinmux.h> 31 #include <linux/pinctrl/pinconf-generic.h> 32 #include <linux/irqchip/chained_irq.h> 33 #include <linux/clk.h> 34 #include <linux/regmap.h> 35 #include <linux/mfd/syscon.h> 36 #include <linux/string_helpers.h> 37 38 #include <dt-bindings/pinctrl/rockchip.h> 39 40 #include "core.h" 41 #include "pinconf.h" 42 #include "pinctrl-rockchip.h" 43 44 /* 45 * Generate a bitmask for setting a value (v) with a write mask bit in hiword 46 * register 31:16 area. 47 */ 48 #define WRITE_MASK_VAL(h, l, v) \ 49 (GENMASK(((h) + 16), ((l) + 16)) | (((v) << (l)) & GENMASK((h), (l)))) 50 51 /* 52 * Encode variants of iomux registers into a type variable 53 */ 54 #define IOMUX_GPIO_ONLY BIT(0) 55 #define IOMUX_WIDTH_4BIT BIT(1) 56 #define IOMUX_SOURCE_PMU BIT(2) 57 #define IOMUX_UNROUTED BIT(3) 58 #define IOMUX_WIDTH_3BIT BIT(4) 59 #define IOMUX_WIDTH_2BIT BIT(5) 60 #define IOMUX_L_SOURCE_PMU BIT(6) 61 62 #define PIN_BANK(id, pins, label) \ 63 { \ 64 .bank_num = id, \ 65 .nr_pins = pins, \ 66 .name = label, \ 67 .iomux = { \ 68 { .offset = -1 }, \ 69 { .offset = -1 }, \ 70 { .offset = -1 }, \ 71 { .offset = -1 }, \ 72 }, \ 73 } 74 75 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \ 76 { \ 77 .bank_num = id, \ 78 .nr_pins = pins, \ 79 .name = label, \ 80 .iomux = { \ 81 { .type = iom0, .offset = -1 }, \ 82 { .type = iom1, .offset = -1 }, \ 83 { .type = iom2, .offset = -1 }, \ 84 { .type = iom3, .offset = -1 }, \ 85 }, \ 86 } 87 88 #define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \ 89 { \ 90 .bank_num = id, \ 91 .nr_pins = pins, \ 92 .name = label, \ 93 .iomux = { \ 94 { .offset = -1 }, \ 95 { .offset = -1 }, \ 96 { .offset = -1 }, \ 97 { .offset = -1 }, \ 98 }, \ 99 .drv = { \ 100 { .drv_type = type0, .offset = -1 }, \ 101 { .drv_type = type1, .offset = -1 }, \ 102 { .drv_type = type2, .offset = -1 }, \ 103 { .drv_type = type3, .offset = -1 }, \ 104 }, \ 105 } 106 107 #define PIN_BANK_IOMUX_FLAGS_PULL_FLAGS(id, pins, label, iom0, iom1, \ 108 iom2, iom3, pull0, pull1, \ 109 pull2, pull3) \ 110 { \ 111 .bank_num = id, \ 112 .nr_pins = pins, \ 113 .name = label, \ 114 .iomux = { \ 115 { .type = iom0, .offset = -1 }, \ 116 { .type = iom1, .offset = -1 }, \ 117 { .type = iom2, .offset = -1 }, \ 118 { .type = iom3, .offset = -1 }, \ 119 }, \ 120 .pull_type[0] = pull0, \ 121 .pull_type[1] = pull1, \ 122 .pull_type[2] = pull2, \ 123 .pull_type[3] = pull3, \ 124 } 125 126 #define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1, \ 127 drv2, drv3, pull0, pull1, \ 128 pull2, pull3) \ 129 { \ 130 .bank_num = id, \ 131 .nr_pins = pins, \ 132 .name = label, \ 133 .iomux = { \ 134 { .offset = -1 }, \ 135 { .offset = -1 }, \ 136 { .offset = -1 }, \ 137 { .offset = -1 }, \ 138 }, \ 139 .drv = { \ 140 { .drv_type = drv0, .offset = -1 }, \ 141 { .drv_type = drv1, .offset = -1 }, \ 142 { .drv_type = drv2, .offset = -1 }, \ 143 { .drv_type = drv3, .offset = -1 }, \ 144 }, \ 145 .pull_type[0] = pull0, \ 146 .pull_type[1] = pull1, \ 147 .pull_type[2] = pull2, \ 148 .pull_type[3] = pull3, \ 149 } 150 151 #define PIN_BANK_IOMUX_FLAGS_OFFSET(id, pins, label, iom0, iom1, iom2, \ 152 iom3, offset0, offset1, offset2, \ 153 offset3) \ 154 { \ 155 .bank_num = id, \ 156 .nr_pins = pins, \ 157 .name = label, \ 158 .iomux = { \ 159 { .type = iom0, .offset = offset0 }, \ 160 { .type = iom1, .offset = offset1 }, \ 161 { .type = iom2, .offset = offset2 }, \ 162 { .type = iom3, .offset = offset3 }, \ 163 }, \ 164 } 165 166 #define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1, \ 167 iom2, iom3, drv0, drv1, drv2, \ 168 drv3, offset0, offset1, \ 169 offset2, offset3) \ 170 { \ 171 .bank_num = id, \ 172 .nr_pins = pins, \ 173 .name = label, \ 174 .iomux = { \ 175 { .type = iom0, .offset = -1 }, \ 176 { .type = iom1, .offset = -1 }, \ 177 { .type = iom2, .offset = -1 }, \ 178 { .type = iom3, .offset = -1 }, \ 179 }, \ 180 .drv = { \ 181 { .drv_type = drv0, .offset = offset0 }, \ 182 { .drv_type = drv1, .offset = offset1 }, \ 183 { .drv_type = drv2, .offset = offset2 }, \ 184 { .drv_type = drv3, .offset = offset3 }, \ 185 }, \ 186 } 187 188 #define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins, \ 189 label, iom0, iom1, iom2, \ 190 iom3, drv0, drv1, drv2, \ 191 drv3, offset0, offset1, \ 192 offset2, offset3, pull0, \ 193 pull1, pull2, pull3) \ 194 { \ 195 .bank_num = id, \ 196 .nr_pins = pins, \ 197 .name = label, \ 198 .iomux = { \ 199 { .type = iom0, .offset = -1 }, \ 200 { .type = iom1, .offset = -1 }, \ 201 { .type = iom2, .offset = -1 }, \ 202 { .type = iom3, .offset = -1 }, \ 203 }, \ 204 .drv = { \ 205 { .drv_type = drv0, .offset = offset0 }, \ 206 { .drv_type = drv1, .offset = offset1 }, \ 207 { .drv_type = drv2, .offset = offset2 }, \ 208 { .drv_type = drv3, .offset = offset3 }, \ 209 }, \ 210 .pull_type[0] = pull0, \ 211 .pull_type[1] = pull1, \ 212 .pull_type[2] = pull2, \ 213 .pull_type[3] = pull3, \ 214 } 215 216 #define PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, FLAG) \ 217 { \ 218 .bank_num = ID, \ 219 .pin = PIN, \ 220 .func = FUNC, \ 221 .route_offset = REG, \ 222 .route_val = VAL, \ 223 .route_location = FLAG, \ 224 } 225 226 #define RK_MUXROUTE_SAME(ID, PIN, FUNC, REG, VAL) \ 227 PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_SAME) 228 229 #define RK_MUXROUTE_GRF(ID, PIN, FUNC, REG, VAL) \ 230 PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_GRF) 231 232 #define RK_MUXROUTE_PMU(ID, PIN, FUNC, REG, VAL) \ 233 PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_PMU) 234 235 #define RK3588_PIN_BANK_FLAGS(ID, PIN, LABEL, M, P) \ 236 PIN_BANK_IOMUX_FLAGS_PULL_FLAGS(ID, PIN, LABEL, M, M, M, M, P, P, P, P) 237 238 static struct regmap_config rockchip_regmap_config = { 239 .reg_bits = 32, 240 .val_bits = 32, 241 .reg_stride = 4, 242 }; 243 244 static inline const struct rockchip_pin_group *pinctrl_name_to_group( 245 const struct rockchip_pinctrl *info, 246 const char *name) 247 { 248 int i; 249 250 for (i = 0; i < info->ngroups; i++) { 251 if (!strcmp(info->groups[i].name, name)) 252 return &info->groups[i]; 253 } 254 255 return NULL; 256 } 257 258 /* 259 * given a pin number that is local to a pin controller, find out the pin bank 260 * and the register base of the pin bank. 261 */ 262 static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info, 263 unsigned pin) 264 { 265 struct rockchip_pin_bank *b = info->ctrl->pin_banks; 266 267 while (pin >= (b->pin_base + b->nr_pins)) 268 b++; 269 270 return b; 271 } 272 273 static struct rockchip_pin_bank *bank_num_to_bank( 274 struct rockchip_pinctrl *info, 275 unsigned num) 276 { 277 struct rockchip_pin_bank *b = info->ctrl->pin_banks; 278 int i; 279 280 for (i = 0; i < info->ctrl->nr_banks; i++, b++) { 281 if (b->bank_num == num) 282 return b; 283 } 284 285 return ERR_PTR(-EINVAL); 286 } 287 288 /* 289 * Pinctrl_ops handling 290 */ 291 292 static int rockchip_get_groups_count(struct pinctrl_dev *pctldev) 293 { 294 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 295 296 return info->ngroups; 297 } 298 299 static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev, 300 unsigned selector) 301 { 302 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 303 304 return info->groups[selector].name; 305 } 306 307 static int rockchip_get_group_pins(struct pinctrl_dev *pctldev, 308 unsigned selector, const unsigned **pins, 309 unsigned *npins) 310 { 311 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 312 313 if (selector >= info->ngroups) 314 return -EINVAL; 315 316 *pins = info->groups[selector].pins; 317 *npins = info->groups[selector].npins; 318 319 return 0; 320 } 321 322 static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev, 323 struct device_node *np, 324 struct pinctrl_map **map, unsigned *num_maps) 325 { 326 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 327 const struct rockchip_pin_group *grp; 328 struct device *dev = info->dev; 329 struct pinctrl_map *new_map; 330 struct device_node *parent; 331 int map_num = 1; 332 int i; 333 334 /* 335 * first find the group of this node and check if we need to create 336 * config maps for pins 337 */ 338 grp = pinctrl_name_to_group(info, np->name); 339 if (!grp) { 340 dev_err(dev, "unable to find group for node %pOFn\n", np); 341 return -EINVAL; 342 } 343 344 map_num += grp->npins; 345 346 new_map = kcalloc(map_num, sizeof(*new_map), GFP_KERNEL); 347 if (!new_map) 348 return -ENOMEM; 349 350 *map = new_map; 351 *num_maps = map_num; 352 353 /* create mux map */ 354 parent = of_get_parent(np); 355 if (!parent) { 356 kfree(new_map); 357 return -EINVAL; 358 } 359 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP; 360 new_map[0].data.mux.function = parent->name; 361 new_map[0].data.mux.group = np->name; 362 of_node_put(parent); 363 364 /* create config map */ 365 new_map++; 366 for (i = 0; i < grp->npins; i++) { 367 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN; 368 new_map[i].data.configs.group_or_pin = 369 pin_get_name(pctldev, grp->pins[i]); 370 new_map[i].data.configs.configs = grp->data[i].configs; 371 new_map[i].data.configs.num_configs = grp->data[i].nconfigs; 372 } 373 374 dev_dbg(dev, "maps: function %s group %s num %d\n", 375 (*map)->data.mux.function, (*map)->data.mux.group, map_num); 376 377 return 0; 378 } 379 380 static void rockchip_dt_free_map(struct pinctrl_dev *pctldev, 381 struct pinctrl_map *map, unsigned num_maps) 382 { 383 kfree(map); 384 } 385 386 static const struct pinctrl_ops rockchip_pctrl_ops = { 387 .get_groups_count = rockchip_get_groups_count, 388 .get_group_name = rockchip_get_group_name, 389 .get_group_pins = rockchip_get_group_pins, 390 .dt_node_to_map = rockchip_dt_node_to_map, 391 .dt_free_map = rockchip_dt_free_map, 392 }; 393 394 /* 395 * Hardware access 396 */ 397 398 static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = { 399 { 400 .num = 1, 401 .pin = 0, 402 .reg = 0x418, 403 .bit = 0, 404 .mask = 0x3 405 }, { 406 .num = 1, 407 .pin = 1, 408 .reg = 0x418, 409 .bit = 2, 410 .mask = 0x3 411 }, { 412 .num = 1, 413 .pin = 2, 414 .reg = 0x418, 415 .bit = 4, 416 .mask = 0x3 417 }, { 418 .num = 1, 419 .pin = 3, 420 .reg = 0x418, 421 .bit = 6, 422 .mask = 0x3 423 }, { 424 .num = 1, 425 .pin = 4, 426 .reg = 0x418, 427 .bit = 8, 428 .mask = 0x3 429 }, { 430 .num = 1, 431 .pin = 5, 432 .reg = 0x418, 433 .bit = 10, 434 .mask = 0x3 435 }, { 436 .num = 1, 437 .pin = 6, 438 .reg = 0x418, 439 .bit = 12, 440 .mask = 0x3 441 }, { 442 .num = 1, 443 .pin = 7, 444 .reg = 0x418, 445 .bit = 14, 446 .mask = 0x3 447 }, { 448 .num = 1, 449 .pin = 8, 450 .reg = 0x41c, 451 .bit = 0, 452 .mask = 0x3 453 }, { 454 .num = 1, 455 .pin = 9, 456 .reg = 0x41c, 457 .bit = 2, 458 .mask = 0x3 459 }, 460 }; 461 462 static struct rockchip_mux_recalced_data rv1126_mux_recalced_data[] = { 463 { 464 .num = 0, 465 .pin = 20, 466 .reg = 0x10000, 467 .bit = 0, 468 .mask = 0xf 469 }, 470 { 471 .num = 0, 472 .pin = 21, 473 .reg = 0x10000, 474 .bit = 4, 475 .mask = 0xf 476 }, 477 { 478 .num = 0, 479 .pin = 22, 480 .reg = 0x10000, 481 .bit = 8, 482 .mask = 0xf 483 }, 484 { 485 .num = 0, 486 .pin = 23, 487 .reg = 0x10000, 488 .bit = 12, 489 .mask = 0xf 490 }, 491 }; 492 493 static struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = { 494 { 495 .num = 2, 496 .pin = 20, 497 .reg = 0xe8, 498 .bit = 0, 499 .mask = 0x7 500 }, { 501 .num = 2, 502 .pin = 21, 503 .reg = 0xe8, 504 .bit = 4, 505 .mask = 0x7 506 }, { 507 .num = 2, 508 .pin = 22, 509 .reg = 0xe8, 510 .bit = 8, 511 .mask = 0x7 512 }, { 513 .num = 2, 514 .pin = 23, 515 .reg = 0xe8, 516 .bit = 12, 517 .mask = 0x7 518 }, { 519 .num = 2, 520 .pin = 24, 521 .reg = 0xd4, 522 .bit = 12, 523 .mask = 0x7 524 }, 525 }; 526 527 static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = { 528 { 529 /* gpio1b6_sel */ 530 .num = 1, 531 .pin = 14, 532 .reg = 0x28, 533 .bit = 12, 534 .mask = 0xf 535 }, { 536 /* gpio1b7_sel */ 537 .num = 1, 538 .pin = 15, 539 .reg = 0x2c, 540 .bit = 0, 541 .mask = 0x3 542 }, { 543 /* gpio1c2_sel */ 544 .num = 1, 545 .pin = 18, 546 .reg = 0x30, 547 .bit = 4, 548 .mask = 0xf 549 }, { 550 /* gpio1c3_sel */ 551 .num = 1, 552 .pin = 19, 553 .reg = 0x30, 554 .bit = 8, 555 .mask = 0xf 556 }, { 557 /* gpio1c4_sel */ 558 .num = 1, 559 .pin = 20, 560 .reg = 0x30, 561 .bit = 12, 562 .mask = 0xf 563 }, { 564 /* gpio1c5_sel */ 565 .num = 1, 566 .pin = 21, 567 .reg = 0x34, 568 .bit = 0, 569 .mask = 0xf 570 }, { 571 /* gpio1c6_sel */ 572 .num = 1, 573 .pin = 22, 574 .reg = 0x34, 575 .bit = 4, 576 .mask = 0xf 577 }, { 578 /* gpio1c7_sel */ 579 .num = 1, 580 .pin = 23, 581 .reg = 0x34, 582 .bit = 8, 583 .mask = 0xf 584 }, { 585 /* gpio2a2_sel */ 586 .num = 2, 587 .pin = 2, 588 .reg = 0x40, 589 .bit = 4, 590 .mask = 0x3 591 }, { 592 /* gpio2a3_sel */ 593 .num = 2, 594 .pin = 3, 595 .reg = 0x40, 596 .bit = 6, 597 .mask = 0x3 598 }, { 599 /* gpio2c0_sel */ 600 .num = 2, 601 .pin = 16, 602 .reg = 0x50, 603 .bit = 0, 604 .mask = 0x3 605 }, { 606 /* gpio3b2_sel */ 607 .num = 3, 608 .pin = 10, 609 .reg = 0x68, 610 .bit = 4, 611 .mask = 0x3 612 }, { 613 /* gpio3b3_sel */ 614 .num = 3, 615 .pin = 11, 616 .reg = 0x68, 617 .bit = 6, 618 .mask = 0x3 619 }, { 620 /* gpio3b4_sel */ 621 .num = 3, 622 .pin = 12, 623 .reg = 0x68, 624 .bit = 8, 625 .mask = 0xf 626 }, { 627 /* gpio3b5_sel */ 628 .num = 3, 629 .pin = 13, 630 .reg = 0x68, 631 .bit = 12, 632 .mask = 0xf 633 }, 634 }; 635 636 static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = { 637 { 638 .num = 2, 639 .pin = 12, 640 .reg = 0x24, 641 .bit = 8, 642 .mask = 0x3 643 }, { 644 .num = 2, 645 .pin = 15, 646 .reg = 0x28, 647 .bit = 0, 648 .mask = 0x7 649 }, { 650 .num = 2, 651 .pin = 23, 652 .reg = 0x30, 653 .bit = 14, 654 .mask = 0x3 655 }, 656 }; 657 658 static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin, 659 int *reg, u8 *bit, int *mask) 660 { 661 struct rockchip_pinctrl *info = bank->drvdata; 662 struct rockchip_pin_ctrl *ctrl = info->ctrl; 663 struct rockchip_mux_recalced_data *data; 664 int i; 665 666 for (i = 0; i < ctrl->niomux_recalced; i++) { 667 data = &ctrl->iomux_recalced[i]; 668 if (data->num == bank->bank_num && 669 data->pin == pin) 670 break; 671 } 672 673 if (i >= ctrl->niomux_recalced) 674 return; 675 676 *reg = data->reg; 677 *mask = data->mask; 678 *bit = data->bit; 679 } 680 681 static struct rockchip_mux_route_data px30_mux_route_data[] = { 682 RK_MUXROUTE_SAME(2, RK_PA0, 1, 0x184, BIT(16 + 7)), /* cif-d2m0 */ 683 RK_MUXROUTE_SAME(3, RK_PA3, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d2m1 */ 684 RK_MUXROUTE_SAME(3, RK_PC6, 2, 0x184, BIT(16 + 8)), /* pdm-m0 */ 685 RK_MUXROUTE_SAME(2, RK_PC6, 1, 0x184, BIT(16 + 8) | BIT(8)), /* pdm-m1 */ 686 RK_MUXROUTE_SAME(1, RK_PD3, 2, 0x184, BIT(16 + 10)), /* uart2-rxm0 */ 687 RK_MUXROUTE_SAME(2, RK_PB6, 2, 0x184, BIT(16 + 10) | BIT(10)), /* uart2-rxm1 */ 688 RK_MUXROUTE_SAME(0, RK_PC1, 2, 0x184, BIT(16 + 9)), /* uart3-rxm0 */ 689 RK_MUXROUTE_SAME(1, RK_PB7, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-rxm1 */ 690 }; 691 692 static struct rockchip_mux_route_data rv1126_mux_route_data[] = { 693 RK_MUXROUTE_GRF(3, RK_PD2, 1, 0x10260, WRITE_MASK_VAL(0, 0, 0)), /* I2S0_MCLK_M0 */ 694 RK_MUXROUTE_GRF(3, RK_PB0, 3, 0x10260, WRITE_MASK_VAL(0, 0, 1)), /* I2S0_MCLK_M1 */ 695 696 RK_MUXROUTE_GRF(0, RK_PD4, 4, 0x10260, WRITE_MASK_VAL(3, 2, 0)), /* I2S1_MCLK_M0 */ 697 RK_MUXROUTE_GRF(1, RK_PD5, 2, 0x10260, WRITE_MASK_VAL(3, 2, 1)), /* I2S1_MCLK_M1 */ 698 RK_MUXROUTE_GRF(2, RK_PC7, 6, 0x10260, WRITE_MASK_VAL(3, 2, 2)), /* I2S1_MCLK_M2 */ 699 700 RK_MUXROUTE_GRF(1, RK_PD0, 1, 0x10260, WRITE_MASK_VAL(4, 4, 0)), /* I2S2_MCLK_M0 */ 701 RK_MUXROUTE_GRF(2, RK_PB3, 2, 0x10260, WRITE_MASK_VAL(4, 4, 1)), /* I2S2_MCLK_M1 */ 702 703 RK_MUXROUTE_GRF(3, RK_PD4, 2, 0x10260, WRITE_MASK_VAL(12, 12, 0)), /* PDM_CLK0_M0 */ 704 RK_MUXROUTE_GRF(3, RK_PC0, 3, 0x10260, WRITE_MASK_VAL(12, 12, 1)), /* PDM_CLK0_M1 */ 705 706 RK_MUXROUTE_GRF(3, RK_PC6, 1, 0x10264, WRITE_MASK_VAL(0, 0, 0)), /* CIF_CLKOUT_M0 */ 707 RK_MUXROUTE_GRF(2, RK_PD1, 3, 0x10264, WRITE_MASK_VAL(0, 0, 1)), /* CIF_CLKOUT_M1 */ 708 709 RK_MUXROUTE_GRF(3, RK_PA4, 5, 0x10264, WRITE_MASK_VAL(5, 4, 0)), /* I2C3_SCL_M0 */ 710 RK_MUXROUTE_GRF(2, RK_PD4, 7, 0x10264, WRITE_MASK_VAL(5, 4, 1)), /* I2C3_SCL_M1 */ 711 RK_MUXROUTE_GRF(1, RK_PD6, 3, 0x10264, WRITE_MASK_VAL(5, 4, 2)), /* I2C3_SCL_M2 */ 712 713 RK_MUXROUTE_GRF(3, RK_PA0, 7, 0x10264, WRITE_MASK_VAL(6, 6, 0)), /* I2C4_SCL_M0 */ 714 RK_MUXROUTE_GRF(4, RK_PA0, 4, 0x10264, WRITE_MASK_VAL(6, 6, 1)), /* I2C4_SCL_M1 */ 715 716 RK_MUXROUTE_GRF(2, RK_PA5, 7, 0x10264, WRITE_MASK_VAL(9, 8, 0)), /* I2C5_SCL_M0 */ 717 RK_MUXROUTE_GRF(3, RK_PB0, 5, 0x10264, WRITE_MASK_VAL(9, 8, 1)), /* I2C5_SCL_M1 */ 718 RK_MUXROUTE_GRF(1, RK_PD0, 4, 0x10264, WRITE_MASK_VAL(9, 8, 2)), /* I2C5_SCL_M2 */ 719 720 RK_MUXROUTE_GRF(3, RK_PC0, 5, 0x10264, WRITE_MASK_VAL(11, 10, 0)), /* SPI1_CLK_M0 */ 721 RK_MUXROUTE_GRF(1, RK_PC6, 3, 0x10264, WRITE_MASK_VAL(11, 10, 1)), /* SPI1_CLK_M1 */ 722 RK_MUXROUTE_GRF(2, RK_PD5, 6, 0x10264, WRITE_MASK_VAL(11, 10, 2)), /* SPI1_CLK_M2 */ 723 724 RK_MUXROUTE_GRF(3, RK_PC0, 2, 0x10264, WRITE_MASK_VAL(12, 12, 0)), /* RGMII_CLK_M0 */ 725 RK_MUXROUTE_GRF(2, RK_PB7, 2, 0x10264, WRITE_MASK_VAL(12, 12, 1)), /* RGMII_CLK_M1 */ 726 727 RK_MUXROUTE_GRF(3, RK_PA1, 3, 0x10264, WRITE_MASK_VAL(13, 13, 0)), /* CAN_TXD_M0 */ 728 RK_MUXROUTE_GRF(3, RK_PA7, 5, 0x10264, WRITE_MASK_VAL(13, 13, 1)), /* CAN_TXD_M1 */ 729 730 RK_MUXROUTE_GRF(3, RK_PA4, 6, 0x10268, WRITE_MASK_VAL(0, 0, 0)), /* PWM8_M0 */ 731 RK_MUXROUTE_GRF(2, RK_PD7, 5, 0x10268, WRITE_MASK_VAL(0, 0, 1)), /* PWM8_M1 */ 732 733 RK_MUXROUTE_GRF(3, RK_PA5, 6, 0x10268, WRITE_MASK_VAL(2, 2, 0)), /* PWM9_M0 */ 734 RK_MUXROUTE_GRF(2, RK_PD6, 5, 0x10268, WRITE_MASK_VAL(2, 2, 1)), /* PWM9_M1 */ 735 736 RK_MUXROUTE_GRF(3, RK_PA6, 6, 0x10268, WRITE_MASK_VAL(4, 4, 0)), /* PWM10_M0 */ 737 RK_MUXROUTE_GRF(2, RK_PD5, 5, 0x10268, WRITE_MASK_VAL(4, 4, 1)), /* PWM10_M1 */ 738 739 RK_MUXROUTE_GRF(3, RK_PA7, 6, 0x10268, WRITE_MASK_VAL(6, 6, 0)), /* PWM11_IR_M0 */ 740 RK_MUXROUTE_GRF(3, RK_PA1, 5, 0x10268, WRITE_MASK_VAL(6, 6, 1)), /* PWM11_IR_M1 */ 741 742 RK_MUXROUTE_GRF(1, RK_PA5, 3, 0x10268, WRITE_MASK_VAL(8, 8, 0)), /* UART2_TX_M0 */ 743 RK_MUXROUTE_GRF(3, RK_PA2, 1, 0x10268, WRITE_MASK_VAL(8, 8, 1)), /* UART2_TX_M1 */ 744 745 RK_MUXROUTE_GRF(3, RK_PC6, 3, 0x10268, WRITE_MASK_VAL(11, 10, 0)), /* UART3_TX_M0 */ 746 RK_MUXROUTE_GRF(1, RK_PA7, 2, 0x10268, WRITE_MASK_VAL(11, 10, 1)), /* UART3_TX_M1 */ 747 RK_MUXROUTE_GRF(3, RK_PA0, 4, 0x10268, WRITE_MASK_VAL(11, 10, 2)), /* UART3_TX_M2 */ 748 749 RK_MUXROUTE_GRF(3, RK_PA4, 4, 0x10268, WRITE_MASK_VAL(13, 12, 0)), /* UART4_TX_M0 */ 750 RK_MUXROUTE_GRF(2, RK_PA6, 4, 0x10268, WRITE_MASK_VAL(13, 12, 1)), /* UART4_TX_M1 */ 751 RK_MUXROUTE_GRF(1, RK_PD5, 3, 0x10268, WRITE_MASK_VAL(13, 12, 2)), /* UART4_TX_M2 */ 752 753 RK_MUXROUTE_GRF(3, RK_PA6, 4, 0x10268, WRITE_MASK_VAL(15, 14, 0)), /* UART5_TX_M0 */ 754 RK_MUXROUTE_GRF(2, RK_PB0, 4, 0x10268, WRITE_MASK_VAL(15, 14, 1)), /* UART5_TX_M1 */ 755 RK_MUXROUTE_GRF(2, RK_PA0, 3, 0x10268, WRITE_MASK_VAL(15, 14, 2)), /* UART5_TX_M2 */ 756 757 RK_MUXROUTE_PMU(0, RK_PB6, 3, 0x0114, WRITE_MASK_VAL(0, 0, 0)), /* PWM0_M0 */ 758 RK_MUXROUTE_PMU(2, RK_PB3, 5, 0x0114, WRITE_MASK_VAL(0, 0, 1)), /* PWM0_M1 */ 759 760 RK_MUXROUTE_PMU(0, RK_PB7, 3, 0x0114, WRITE_MASK_VAL(2, 2, 0)), /* PWM1_M0 */ 761 RK_MUXROUTE_PMU(2, RK_PB2, 5, 0x0114, WRITE_MASK_VAL(2, 2, 1)), /* PWM1_M1 */ 762 763 RK_MUXROUTE_PMU(0, RK_PC0, 3, 0x0114, WRITE_MASK_VAL(4, 4, 0)), /* PWM2_M0 */ 764 RK_MUXROUTE_PMU(2, RK_PB1, 5, 0x0114, WRITE_MASK_VAL(4, 4, 1)), /* PWM2_M1 */ 765 766 RK_MUXROUTE_PMU(0, RK_PC1, 3, 0x0114, WRITE_MASK_VAL(6, 6, 0)), /* PWM3_IR_M0 */ 767 RK_MUXROUTE_PMU(2, RK_PB0, 5, 0x0114, WRITE_MASK_VAL(6, 6, 1)), /* PWM3_IR_M1 */ 768 769 RK_MUXROUTE_PMU(0, RK_PC2, 3, 0x0114, WRITE_MASK_VAL(8, 8, 0)), /* PWM4_M0 */ 770 RK_MUXROUTE_PMU(2, RK_PA7, 5, 0x0114, WRITE_MASK_VAL(8, 8, 1)), /* PWM4_M1 */ 771 772 RK_MUXROUTE_PMU(0, RK_PC3, 3, 0x0114, WRITE_MASK_VAL(10, 10, 0)), /* PWM5_M0 */ 773 RK_MUXROUTE_PMU(2, RK_PA6, 5, 0x0114, WRITE_MASK_VAL(10, 10, 1)), /* PWM5_M1 */ 774 775 RK_MUXROUTE_PMU(0, RK_PB2, 3, 0x0114, WRITE_MASK_VAL(12, 12, 0)), /* PWM6_M0 */ 776 RK_MUXROUTE_PMU(2, RK_PD4, 5, 0x0114, WRITE_MASK_VAL(12, 12, 1)), /* PWM6_M1 */ 777 778 RK_MUXROUTE_PMU(0, RK_PB1, 3, 0x0114, WRITE_MASK_VAL(14, 14, 0)), /* PWM7_IR_M0 */ 779 RK_MUXROUTE_PMU(3, RK_PA0, 5, 0x0114, WRITE_MASK_VAL(14, 14, 1)), /* PWM7_IR_M1 */ 780 781 RK_MUXROUTE_PMU(0, RK_PB0, 1, 0x0118, WRITE_MASK_VAL(1, 0, 0)), /* SPI0_CLK_M0 */ 782 RK_MUXROUTE_PMU(2, RK_PA1, 1, 0x0118, WRITE_MASK_VAL(1, 0, 1)), /* SPI0_CLK_M1 */ 783 RK_MUXROUTE_PMU(2, RK_PB2, 6, 0x0118, WRITE_MASK_VAL(1, 0, 2)), /* SPI0_CLK_M2 */ 784 785 RK_MUXROUTE_PMU(0, RK_PB6, 2, 0x0118, WRITE_MASK_VAL(2, 2, 0)), /* UART1_TX_M0 */ 786 RK_MUXROUTE_PMU(1, RK_PD0, 5, 0x0118, WRITE_MASK_VAL(2, 2, 1)), /* UART1_TX_M1 */ 787 }; 788 789 static struct rockchip_mux_route_data rk3128_mux_route_data[] = { 790 RK_MUXROUTE_SAME(1, RK_PB2, 1, 0x144, BIT(16 + 3) | BIT(16 + 4)), /* spi-0 */ 791 RK_MUXROUTE_SAME(1, RK_PD3, 3, 0x144, BIT(16 + 3) | BIT(16 + 4) | BIT(3)), /* spi-1 */ 792 RK_MUXROUTE_SAME(0, RK_PB5, 2, 0x144, BIT(16 + 3) | BIT(16 + 4) | BIT(4)), /* spi-2 */ 793 RK_MUXROUTE_SAME(1, RK_PA5, 1, 0x144, BIT(16 + 5)), /* i2s-0 */ 794 RK_MUXROUTE_SAME(0, RK_PB6, 1, 0x144, BIT(16 + 5) | BIT(5)), /* i2s-1 */ 795 RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x144, BIT(16 + 6)), /* emmc-0 */ 796 RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x144, BIT(16 + 6) | BIT(6)), /* emmc-1 */ 797 }; 798 799 static struct rockchip_mux_route_data rk3188_mux_route_data[] = { 800 RK_MUXROUTE_SAME(0, RK_PD0, 1, 0xa0, BIT(16 + 11)), /* non-iomuxed emmc/flash pins on flash-dqs */ 801 RK_MUXROUTE_SAME(0, RK_PD0, 2, 0xa0, BIT(16 + 11) | BIT(11)), /* non-iomuxed emmc/flash pins on emmc-clk */ 802 }; 803 804 static struct rockchip_mux_route_data rk3228_mux_route_data[] = { 805 RK_MUXROUTE_SAME(0, RK_PD2, 1, 0x50, BIT(16)), /* pwm0-0 */ 806 RK_MUXROUTE_SAME(3, RK_PC5, 1, 0x50, BIT(16) | BIT(0)), /* pwm0-1 */ 807 RK_MUXROUTE_SAME(0, RK_PD3, 1, 0x50, BIT(16 + 1)), /* pwm1-0 */ 808 RK_MUXROUTE_SAME(0, RK_PD6, 2, 0x50, BIT(16 + 1) | BIT(1)), /* pwm1-1 */ 809 RK_MUXROUTE_SAME(0, RK_PD4, 1, 0x50, BIT(16 + 2)), /* pwm2-0 */ 810 RK_MUXROUTE_SAME(1, RK_PB4, 2, 0x50, BIT(16 + 2) | BIT(2)), /* pwm2-1 */ 811 RK_MUXROUTE_SAME(3, RK_PD2, 1, 0x50, BIT(16 + 3)), /* pwm3-0 */ 812 RK_MUXROUTE_SAME(1, RK_PB3, 2, 0x50, BIT(16 + 3) | BIT(3)), /* pwm3-1 */ 813 RK_MUXROUTE_SAME(1, RK_PA1, 1, 0x50, BIT(16 + 4)), /* sdio-0_d0 */ 814 RK_MUXROUTE_SAME(3, RK_PA2, 1, 0x50, BIT(16 + 4) | BIT(4)), /* sdio-1_d0 */ 815 RK_MUXROUTE_SAME(0, RK_PB5, 2, 0x50, BIT(16 + 5)), /* spi-0_rx */ 816 RK_MUXROUTE_SAME(2, RK_PA0, 2, 0x50, BIT(16 + 5) | BIT(5)), /* spi-1_rx */ 817 RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x50, BIT(16 + 7)), /* emmc-0_cmd */ 818 RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x50, BIT(16 + 7) | BIT(7)), /* emmc-1_cmd */ 819 RK_MUXROUTE_SAME(1, RK_PC3, 2, 0x50, BIT(16 + 8)), /* uart2-0_rx */ 820 RK_MUXROUTE_SAME(1, RK_PB2, 2, 0x50, BIT(16 + 8) | BIT(8)), /* uart2-1_rx */ 821 RK_MUXROUTE_SAME(1, RK_PB2, 1, 0x50, BIT(16 + 11)), /* uart1-0_rx */ 822 RK_MUXROUTE_SAME(3, RK_PB5, 1, 0x50, BIT(16 + 11) | BIT(11)), /* uart1-1_rx */ 823 }; 824 825 static struct rockchip_mux_route_data rk3288_mux_route_data[] = { 826 RK_MUXROUTE_SAME(7, RK_PC0, 2, 0x264, BIT(16 + 12) | BIT(12)), /* edphdmi_cecinoutt1 */ 827 RK_MUXROUTE_SAME(7, RK_PC7, 4, 0x264, BIT(16 + 12)), /* edphdmi_cecinout */ 828 }; 829 830 static struct rockchip_mux_route_data rk3308_mux_route_data[] = { 831 RK_MUXROUTE_SAME(0, RK_PC3, 1, 0x314, BIT(16 + 0) | BIT(0)), /* rtc_clk */ 832 RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x314, BIT(16 + 2) | BIT(16 + 3)), /* uart2_rxm0 */ 833 RK_MUXROUTE_SAME(4, RK_PD2, 2, 0x314, BIT(16 + 2) | BIT(16 + 3) | BIT(2)), /* uart2_rxm1 */ 834 RK_MUXROUTE_SAME(0, RK_PB7, 2, 0x608, BIT(16 + 8) | BIT(16 + 9)), /* i2c3_sdam0 */ 835 RK_MUXROUTE_SAME(3, RK_PB4, 2, 0x608, BIT(16 + 8) | BIT(16 + 9) | BIT(8)), /* i2c3_sdam1 */ 836 RK_MUXROUTE_SAME(2, RK_PA0, 3, 0x608, BIT(16 + 8) | BIT(16 + 9) | BIT(9)), /* i2c3_sdam2 */ 837 RK_MUXROUTE_SAME(1, RK_PA3, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclktxm0 */ 838 RK_MUXROUTE_SAME(1, RK_PA4, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclkrxm0 */ 839 RK_MUXROUTE_SAME(1, RK_PB5, 2, 0x308, BIT(16 + 3) | BIT(3)), /* i2s-8ch-1-sclktxm1 */ 840 RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x308, BIT(16 + 3) | BIT(3)), /* i2s-8ch-1-sclkrxm1 */ 841 RK_MUXROUTE_SAME(1, RK_PA4, 3, 0x308, BIT(16 + 12) | BIT(16 + 13)), /* pdm-clkm0 */ 842 RK_MUXROUTE_SAME(1, RK_PB6, 4, 0x308, BIT(16 + 12) | BIT(16 + 13) | BIT(12)), /* pdm-clkm1 */ 843 RK_MUXROUTE_SAME(2, RK_PA6, 2, 0x308, BIT(16 + 12) | BIT(16 + 13) | BIT(13)), /* pdm-clkm2 */ 844 RK_MUXROUTE_SAME(2, RK_PA4, 3, 0x600, BIT(16 + 2) | BIT(2)), /* pdm-clkm-m2 */ 845 RK_MUXROUTE_SAME(3, RK_PB2, 3, 0x314, BIT(16 + 9)), /* spi1_miso */ 846 RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x314, BIT(16 + 9) | BIT(9)), /* spi1_miso_m1 */ 847 RK_MUXROUTE_SAME(0, RK_PB3, 3, 0x314, BIT(16 + 10) | BIT(16 + 11)), /* owire_m0 */ 848 RK_MUXROUTE_SAME(1, RK_PC6, 7, 0x314, BIT(16 + 10) | BIT(16 + 11) | BIT(10)), /* owire_m1 */ 849 RK_MUXROUTE_SAME(2, RK_PA2, 5, 0x314, BIT(16 + 10) | BIT(16 + 11) | BIT(11)), /* owire_m2 */ 850 RK_MUXROUTE_SAME(0, RK_PB3, 2, 0x314, BIT(16 + 12) | BIT(16 + 13)), /* can_rxd_m0 */ 851 RK_MUXROUTE_SAME(1, RK_PC6, 5, 0x314, BIT(16 + 12) | BIT(16 + 13) | BIT(12)), /* can_rxd_m1 */ 852 RK_MUXROUTE_SAME(2, RK_PA2, 4, 0x314, BIT(16 + 12) | BIT(16 + 13) | BIT(13)), /* can_rxd_m2 */ 853 RK_MUXROUTE_SAME(1, RK_PC4, 3, 0x314, BIT(16 + 14)), /* mac_rxd0_m0 */ 854 RK_MUXROUTE_SAME(4, RK_PA2, 2, 0x314, BIT(16 + 14) | BIT(14)), /* mac_rxd0_m1 */ 855 RK_MUXROUTE_SAME(3, RK_PB4, 4, 0x314, BIT(16 + 15)), /* uart3_rx */ 856 RK_MUXROUTE_SAME(0, RK_PC1, 3, 0x314, BIT(16 + 15) | BIT(15)), /* uart3_rx_m1 */ 857 }; 858 859 static struct rockchip_mux_route_data rk3328_mux_route_data[] = { 860 RK_MUXROUTE_SAME(1, RK_PA1, 2, 0x50, BIT(16) | BIT(16 + 1)), /* uart2dbg_rxm0 */ 861 RK_MUXROUTE_SAME(2, RK_PA1, 1, 0x50, BIT(16) | BIT(16 + 1) | BIT(0)), /* uart2dbg_rxm1 */ 862 RK_MUXROUTE_SAME(1, RK_PB3, 2, 0x50, BIT(16 + 2) | BIT(2)), /* gmac-m1_rxd0 */ 863 RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x50, BIT(16 + 10) | BIT(10)), /* gmac-m1-optimized_rxd3 */ 864 RK_MUXROUTE_SAME(2, RK_PC3, 2, 0x50, BIT(16 + 3)), /* pdm_sdi0m0 */ 865 RK_MUXROUTE_SAME(1, RK_PC7, 3, 0x50, BIT(16 + 3) | BIT(3)), /* pdm_sdi0m1 */ 866 RK_MUXROUTE_SAME(3, RK_PA2, 4, 0x50, BIT(16 + 4) | BIT(16 + 5) | BIT(5)), /* spi_rxdm2 */ 867 RK_MUXROUTE_SAME(1, RK_PD0, 1, 0x50, BIT(16 + 6)), /* i2s2_sdim0 */ 868 RK_MUXROUTE_SAME(3, RK_PA2, 6, 0x50, BIT(16 + 6) | BIT(6)), /* i2s2_sdim1 */ 869 RK_MUXROUTE_SAME(2, RK_PC6, 3, 0x50, BIT(16 + 7) | BIT(7)), /* card_iom1 */ 870 RK_MUXROUTE_SAME(2, RK_PC0, 3, 0x50, BIT(16 + 8) | BIT(8)), /* tsp_d5m1 */ 871 RK_MUXROUTE_SAME(2, RK_PC0, 4, 0x50, BIT(16 + 9) | BIT(9)), /* cif_data5m1 */ 872 }; 873 874 static struct rockchip_mux_route_data rk3399_mux_route_data[] = { 875 RK_MUXROUTE_SAME(4, RK_PB0, 2, 0xe21c, BIT(16 + 10) | BIT(16 + 11)), /* uart2dbga_rx */ 876 RK_MUXROUTE_SAME(4, RK_PC0, 2, 0xe21c, BIT(16 + 10) | BIT(16 + 11) | BIT(10)), /* uart2dbgb_rx */ 877 RK_MUXROUTE_SAME(4, RK_PC3, 1, 0xe21c, BIT(16 + 10) | BIT(16 + 11) | BIT(11)), /* uart2dbgc_rx */ 878 RK_MUXROUTE_SAME(2, RK_PD2, 2, 0xe21c, BIT(16 + 14)), /* pcie_clkreqn */ 879 RK_MUXROUTE_SAME(4, RK_PD0, 1, 0xe21c, BIT(16 + 14) | BIT(14)), /* pcie_clkreqnb */ 880 }; 881 882 static struct rockchip_mux_route_data rk3568_mux_route_data[] = { 883 RK_MUXROUTE_PMU(0, RK_PB7, 1, 0x0110, WRITE_MASK_VAL(1, 0, 0)), /* PWM0 IO mux M0 */ 884 RK_MUXROUTE_PMU(0, RK_PC7, 2, 0x0110, WRITE_MASK_VAL(1, 0, 1)), /* PWM0 IO mux M1 */ 885 RK_MUXROUTE_PMU(0, RK_PC0, 1, 0x0110, WRITE_MASK_VAL(3, 2, 0)), /* PWM1 IO mux M0 */ 886 RK_MUXROUTE_PMU(0, RK_PB5, 4, 0x0110, WRITE_MASK_VAL(3, 2, 1)), /* PWM1 IO mux M1 */ 887 RK_MUXROUTE_PMU(0, RK_PC1, 1, 0x0110, WRITE_MASK_VAL(5, 4, 0)), /* PWM2 IO mux M0 */ 888 RK_MUXROUTE_PMU(0, RK_PB6, 4, 0x0110, WRITE_MASK_VAL(5, 4, 1)), /* PWM2 IO mux M1 */ 889 RK_MUXROUTE_PMU(0, RK_PB3, 2, 0x0300, WRITE_MASK_VAL(0, 0, 0)), /* CAN0 IO mux M0 */ 890 RK_MUXROUTE_GRF(2, RK_PA1, 4, 0x0300, WRITE_MASK_VAL(0, 0, 1)), /* CAN0 IO mux M1 */ 891 RK_MUXROUTE_GRF(1, RK_PA1, 3, 0x0300, WRITE_MASK_VAL(2, 2, 0)), /* CAN1 IO mux M0 */ 892 RK_MUXROUTE_GRF(4, RK_PC3, 3, 0x0300, WRITE_MASK_VAL(2, 2, 1)), /* CAN1 IO mux M1 */ 893 RK_MUXROUTE_GRF(4, RK_PB5, 3, 0x0300, WRITE_MASK_VAL(4, 4, 0)), /* CAN2 IO mux M0 */ 894 RK_MUXROUTE_GRF(2, RK_PB2, 4, 0x0300, WRITE_MASK_VAL(4, 4, 1)), /* CAN2 IO mux M1 */ 895 RK_MUXROUTE_GRF(4, RK_PC4, 1, 0x0300, WRITE_MASK_VAL(6, 6, 0)), /* HPDIN IO mux M0 */ 896 RK_MUXROUTE_PMU(0, RK_PC2, 2, 0x0300, WRITE_MASK_VAL(6, 6, 1)), /* HPDIN IO mux M1 */ 897 RK_MUXROUTE_GRF(3, RK_PB1, 3, 0x0300, WRITE_MASK_VAL(8, 8, 0)), /* GMAC1 IO mux M0 */ 898 RK_MUXROUTE_GRF(4, RK_PA7, 3, 0x0300, WRITE_MASK_VAL(8, 8, 1)), /* GMAC1 IO mux M1 */ 899 RK_MUXROUTE_GRF(4, RK_PD1, 1, 0x0300, WRITE_MASK_VAL(10, 10, 0)), /* HDMITX IO mux M0 */ 900 RK_MUXROUTE_PMU(0, RK_PC7, 1, 0x0300, WRITE_MASK_VAL(10, 10, 1)), /* HDMITX IO mux M1 */ 901 RK_MUXROUTE_PMU(0, RK_PB6, 1, 0x0300, WRITE_MASK_VAL(14, 14, 0)), /* I2C2 IO mux M0 */ 902 RK_MUXROUTE_GRF(4, RK_PB4, 1, 0x0300, WRITE_MASK_VAL(14, 14, 1)), /* I2C2 IO mux M1 */ 903 RK_MUXROUTE_GRF(1, RK_PA0, 1, 0x0304, WRITE_MASK_VAL(0, 0, 0)), /* I2C3 IO mux M0 */ 904 RK_MUXROUTE_GRF(3, RK_PB6, 4, 0x0304, WRITE_MASK_VAL(0, 0, 1)), /* I2C3 IO mux M1 */ 905 RK_MUXROUTE_GRF(4, RK_PB2, 1, 0x0304, WRITE_MASK_VAL(2, 2, 0)), /* I2C4 IO mux M0 */ 906 RK_MUXROUTE_GRF(2, RK_PB1, 2, 0x0304, WRITE_MASK_VAL(2, 2, 1)), /* I2C4 IO mux M1 */ 907 RK_MUXROUTE_GRF(3, RK_PB4, 4, 0x0304, WRITE_MASK_VAL(4, 4, 0)), /* I2C5 IO mux M0 */ 908 RK_MUXROUTE_GRF(4, RK_PD0, 2, 0x0304, WRITE_MASK_VAL(4, 4, 1)), /* I2C5 IO mux M1 */ 909 RK_MUXROUTE_GRF(3, RK_PB1, 5, 0x0304, WRITE_MASK_VAL(14, 14, 0)), /* PWM8 IO mux M0 */ 910 RK_MUXROUTE_GRF(1, RK_PD5, 4, 0x0304, WRITE_MASK_VAL(14, 14, 1)), /* PWM8 IO mux M1 */ 911 RK_MUXROUTE_GRF(3, RK_PB2, 5, 0x0308, WRITE_MASK_VAL(0, 0, 0)), /* PWM9 IO mux M0 */ 912 RK_MUXROUTE_GRF(1, RK_PD6, 4, 0x0308, WRITE_MASK_VAL(0, 0, 1)), /* PWM9 IO mux M1 */ 913 RK_MUXROUTE_GRF(3, RK_PB5, 5, 0x0308, WRITE_MASK_VAL(2, 2, 0)), /* PWM10 IO mux M0 */ 914 RK_MUXROUTE_GRF(2, RK_PA1, 2, 0x0308, WRITE_MASK_VAL(2, 2, 1)), /* PWM10 IO mux M1 */ 915 RK_MUXROUTE_GRF(3, RK_PB6, 5, 0x0308, WRITE_MASK_VAL(4, 4, 0)), /* PWM11 IO mux M0 */ 916 RK_MUXROUTE_GRF(4, RK_PC0, 3, 0x0308, WRITE_MASK_VAL(4, 4, 1)), /* PWM11 IO mux M1 */ 917 RK_MUXROUTE_GRF(3, RK_PB7, 2, 0x0308, WRITE_MASK_VAL(6, 6, 0)), /* PWM12 IO mux M0 */ 918 RK_MUXROUTE_GRF(4, RK_PC5, 1, 0x0308, WRITE_MASK_VAL(6, 6, 1)), /* PWM12 IO mux M1 */ 919 RK_MUXROUTE_GRF(3, RK_PC0, 2, 0x0308, WRITE_MASK_VAL(8, 8, 0)), /* PWM13 IO mux M0 */ 920 RK_MUXROUTE_GRF(4, RK_PC6, 1, 0x0308, WRITE_MASK_VAL(8, 8, 1)), /* PWM13 IO mux M1 */ 921 RK_MUXROUTE_GRF(3, RK_PC4, 1, 0x0308, WRITE_MASK_VAL(10, 10, 0)), /* PWM14 IO mux M0 */ 922 RK_MUXROUTE_GRF(4, RK_PC2, 1, 0x0308, WRITE_MASK_VAL(10, 10, 1)), /* PWM14 IO mux M1 */ 923 RK_MUXROUTE_GRF(3, RK_PC5, 1, 0x0308, WRITE_MASK_VAL(12, 12, 0)), /* PWM15 IO mux M0 */ 924 RK_MUXROUTE_GRF(4, RK_PC3, 1, 0x0308, WRITE_MASK_VAL(12, 12, 1)), /* PWM15 IO mux M1 */ 925 RK_MUXROUTE_GRF(3, RK_PD2, 3, 0x0308, WRITE_MASK_VAL(14, 14, 0)), /* SDMMC2 IO mux M0 */ 926 RK_MUXROUTE_GRF(3, RK_PA5, 5, 0x0308, WRITE_MASK_VAL(14, 14, 1)), /* SDMMC2 IO mux M1 */ 927 RK_MUXROUTE_PMU(0, RK_PB5, 2, 0x030c, WRITE_MASK_VAL(0, 0, 0)), /* SPI0 IO mux M0 */ 928 RK_MUXROUTE_GRF(2, RK_PD3, 3, 0x030c, WRITE_MASK_VAL(0, 0, 1)), /* SPI0 IO mux M1 */ 929 RK_MUXROUTE_GRF(2, RK_PB5, 3, 0x030c, WRITE_MASK_VAL(2, 2, 0)), /* SPI1 IO mux M0 */ 930 RK_MUXROUTE_GRF(3, RK_PC3, 3, 0x030c, WRITE_MASK_VAL(2, 2, 1)), /* SPI1 IO mux M1 */ 931 RK_MUXROUTE_GRF(2, RK_PC1, 4, 0x030c, WRITE_MASK_VAL(4, 4, 0)), /* SPI2 IO mux M0 */ 932 RK_MUXROUTE_GRF(3, RK_PA0, 3, 0x030c, WRITE_MASK_VAL(4, 4, 1)), /* SPI2 IO mux M1 */ 933 RK_MUXROUTE_GRF(4, RK_PB3, 4, 0x030c, WRITE_MASK_VAL(6, 6, 0)), /* SPI3 IO mux M0 */ 934 RK_MUXROUTE_GRF(4, RK_PC2, 2, 0x030c, WRITE_MASK_VAL(6, 6, 1)), /* SPI3 IO mux M1 */ 935 RK_MUXROUTE_GRF(2, RK_PB4, 2, 0x030c, WRITE_MASK_VAL(8, 8, 0)), /* UART1 IO mux M0 */ 936 RK_MUXROUTE_PMU(0, RK_PD1, 1, 0x030c, WRITE_MASK_VAL(8, 8, 1)), /* UART1 IO mux M1 */ 937 RK_MUXROUTE_PMU(0, RK_PD1, 1, 0x030c, WRITE_MASK_VAL(10, 10, 0)), /* UART2 IO mux M0 */ 938 RK_MUXROUTE_GRF(1, RK_PD5, 2, 0x030c, WRITE_MASK_VAL(10, 10, 1)), /* UART2 IO mux M1 */ 939 RK_MUXROUTE_GRF(1, RK_PA1, 2, 0x030c, WRITE_MASK_VAL(12, 12, 0)), /* UART3 IO mux M0 */ 940 RK_MUXROUTE_GRF(3, RK_PB7, 4, 0x030c, WRITE_MASK_VAL(12, 12, 1)), /* UART3 IO mux M1 */ 941 RK_MUXROUTE_GRF(1, RK_PA6, 2, 0x030c, WRITE_MASK_VAL(14, 14, 0)), /* UART4 IO mux M0 */ 942 RK_MUXROUTE_GRF(3, RK_PB2, 4, 0x030c, WRITE_MASK_VAL(14, 14, 1)), /* UART4 IO mux M1 */ 943 RK_MUXROUTE_GRF(2, RK_PA2, 3, 0x0310, WRITE_MASK_VAL(0, 0, 0)), /* UART5 IO mux M0 */ 944 RK_MUXROUTE_GRF(3, RK_PC2, 4, 0x0310, WRITE_MASK_VAL(0, 0, 1)), /* UART5 IO mux M1 */ 945 RK_MUXROUTE_GRF(2, RK_PA4, 3, 0x0310, WRITE_MASK_VAL(2, 2, 0)), /* UART6 IO mux M0 */ 946 RK_MUXROUTE_GRF(1, RK_PD5, 3, 0x0310, WRITE_MASK_VAL(2, 2, 1)), /* UART6 IO mux M1 */ 947 RK_MUXROUTE_GRF(2, RK_PA6, 3, 0x0310, WRITE_MASK_VAL(5, 4, 0)), /* UART7 IO mux M0 */ 948 RK_MUXROUTE_GRF(3, RK_PC4, 4, 0x0310, WRITE_MASK_VAL(5, 4, 1)), /* UART7 IO mux M1 */ 949 RK_MUXROUTE_GRF(4, RK_PA2, 4, 0x0310, WRITE_MASK_VAL(5, 4, 2)), /* UART7 IO mux M2 */ 950 RK_MUXROUTE_GRF(2, RK_PC5, 3, 0x0310, WRITE_MASK_VAL(6, 6, 0)), /* UART8 IO mux M0 */ 951 RK_MUXROUTE_GRF(2, RK_PD7, 4, 0x0310, WRITE_MASK_VAL(6, 6, 1)), /* UART8 IO mux M1 */ 952 RK_MUXROUTE_GRF(2, RK_PB0, 3, 0x0310, WRITE_MASK_VAL(9, 8, 0)), /* UART9 IO mux M0 */ 953 RK_MUXROUTE_GRF(4, RK_PC5, 4, 0x0310, WRITE_MASK_VAL(9, 8, 1)), /* UART9 IO mux M1 */ 954 RK_MUXROUTE_GRF(4, RK_PA4, 4, 0x0310, WRITE_MASK_VAL(9, 8, 2)), /* UART9 IO mux M2 */ 955 RK_MUXROUTE_GRF(1, RK_PA2, 1, 0x0310, WRITE_MASK_VAL(11, 10, 0)), /* I2S1 IO mux M0 */ 956 RK_MUXROUTE_GRF(3, RK_PC6, 4, 0x0310, WRITE_MASK_VAL(11, 10, 1)), /* I2S1 IO mux M1 */ 957 RK_MUXROUTE_GRF(2, RK_PD0, 5, 0x0310, WRITE_MASK_VAL(11, 10, 2)), /* I2S1 IO mux M2 */ 958 RK_MUXROUTE_GRF(2, RK_PC1, 1, 0x0310, WRITE_MASK_VAL(12, 12, 0)), /* I2S2 IO mux M0 */ 959 RK_MUXROUTE_GRF(4, RK_PB6, 5, 0x0310, WRITE_MASK_VAL(12, 12, 1)), /* I2S2 IO mux M1 */ 960 RK_MUXROUTE_GRF(3, RK_PA2, 4, 0x0310, WRITE_MASK_VAL(14, 14, 0)), /* I2S3 IO mux M0 */ 961 RK_MUXROUTE_GRF(4, RK_PC2, 5, 0x0310, WRITE_MASK_VAL(14, 14, 1)), /* I2S3 IO mux M1 */ 962 RK_MUXROUTE_GRF(1, RK_PA4, 3, 0x0314, WRITE_MASK_VAL(1, 0, 0)), /* PDM IO mux M0 */ 963 RK_MUXROUTE_GRF(1, RK_PA6, 3, 0x0314, WRITE_MASK_VAL(1, 0, 0)), /* PDM IO mux M0 */ 964 RK_MUXROUTE_GRF(3, RK_PD6, 5, 0x0314, WRITE_MASK_VAL(1, 0, 1)), /* PDM IO mux M1 */ 965 RK_MUXROUTE_GRF(4, RK_PA0, 4, 0x0314, WRITE_MASK_VAL(1, 0, 1)), /* PDM IO mux M1 */ 966 RK_MUXROUTE_GRF(3, RK_PC4, 5, 0x0314, WRITE_MASK_VAL(1, 0, 2)), /* PDM IO mux M2 */ 967 RK_MUXROUTE_PMU(0, RK_PA5, 3, 0x0314, WRITE_MASK_VAL(3, 2, 0)), /* PCIE20 IO mux M0 */ 968 RK_MUXROUTE_GRF(2, RK_PD0, 4, 0x0314, WRITE_MASK_VAL(3, 2, 1)), /* PCIE20 IO mux M1 */ 969 RK_MUXROUTE_GRF(1, RK_PB0, 4, 0x0314, WRITE_MASK_VAL(3, 2, 2)), /* PCIE20 IO mux M2 */ 970 RK_MUXROUTE_PMU(0, RK_PA4, 3, 0x0314, WRITE_MASK_VAL(5, 4, 0)), /* PCIE30X1 IO mux M0 */ 971 RK_MUXROUTE_GRF(2, RK_PD2, 4, 0x0314, WRITE_MASK_VAL(5, 4, 1)), /* PCIE30X1 IO mux M1 */ 972 RK_MUXROUTE_GRF(1, RK_PA5, 4, 0x0314, WRITE_MASK_VAL(5, 4, 2)), /* PCIE30X1 IO mux M2 */ 973 RK_MUXROUTE_PMU(0, RK_PA6, 2, 0x0314, WRITE_MASK_VAL(7, 6, 0)), /* PCIE30X2 IO mux M0 */ 974 RK_MUXROUTE_GRF(2, RK_PD4, 4, 0x0314, WRITE_MASK_VAL(7, 6, 1)), /* PCIE30X2 IO mux M1 */ 975 RK_MUXROUTE_GRF(4, RK_PC2, 4, 0x0314, WRITE_MASK_VAL(7, 6, 2)), /* PCIE30X2 IO mux M2 */ 976 }; 977 978 static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin, 979 int mux, u32 *loc, u32 *reg, u32 *value) 980 { 981 struct rockchip_pinctrl *info = bank->drvdata; 982 struct rockchip_pin_ctrl *ctrl = info->ctrl; 983 struct rockchip_mux_route_data *data; 984 int i; 985 986 for (i = 0; i < ctrl->niomux_routes; i++) { 987 data = &ctrl->iomux_routes[i]; 988 if ((data->bank_num == bank->bank_num) && 989 (data->pin == pin) && (data->func == mux)) 990 break; 991 } 992 993 if (i >= ctrl->niomux_routes) 994 return false; 995 996 *loc = data->route_location; 997 *reg = data->route_offset; 998 *value = data->route_val; 999 1000 return true; 1001 } 1002 1003 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) 1004 { 1005 struct rockchip_pinctrl *info = bank->drvdata; 1006 struct rockchip_pin_ctrl *ctrl = info->ctrl; 1007 int iomux_num = (pin / 8); 1008 struct regmap *regmap; 1009 unsigned int val; 1010 int reg, ret, mask, mux_type; 1011 u8 bit; 1012 1013 if (iomux_num > 3) 1014 return -EINVAL; 1015 1016 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { 1017 dev_err(info->dev, "pin %d is unrouted\n", pin); 1018 return -EINVAL; 1019 } 1020 1021 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) 1022 return RK_FUNC_GPIO; 1023 1024 if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) 1025 regmap = info->regmap_pmu; 1026 else if (bank->iomux[iomux_num].type & IOMUX_L_SOURCE_PMU) 1027 regmap = (pin % 8 < 4) ? info->regmap_pmu : info->regmap_base; 1028 else 1029 regmap = info->regmap_base; 1030 1031 /* get basic quadrupel of mux registers and the correct reg inside */ 1032 mux_type = bank->iomux[iomux_num].type; 1033 reg = bank->iomux[iomux_num].offset; 1034 if (mux_type & IOMUX_WIDTH_4BIT) { 1035 if ((pin % 8) >= 4) 1036 reg += 0x4; 1037 bit = (pin % 4) * 4; 1038 mask = 0xf; 1039 } else if (mux_type & IOMUX_WIDTH_3BIT) { 1040 if ((pin % 8) >= 5) 1041 reg += 0x4; 1042 bit = (pin % 8 % 5) * 3; 1043 mask = 0x7; 1044 } else { 1045 bit = (pin % 8) * 2; 1046 mask = 0x3; 1047 } 1048 1049 if (bank->recalced_mask & BIT(pin)) 1050 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); 1051 1052 if (ctrl->type == RK3588) { 1053 if (bank->bank_num == 0) { 1054 if ((pin >= RK_PB4) && (pin <= RK_PD7)) { 1055 u32 reg0 = 0; 1056 1057 reg0 = reg + 0x4000 - 0xC; /* PMU2_IOC_BASE */ 1058 ret = regmap_read(regmap, reg0, &val); 1059 if (ret) 1060 return ret; 1061 1062 if (!(val & BIT(8))) 1063 return ((val >> bit) & mask); 1064 1065 reg = reg + 0x8000; /* BUS_IOC_BASE */ 1066 regmap = info->regmap_base; 1067 } 1068 } else if (bank->bank_num > 0) { 1069 reg += 0x8000; /* BUS_IOC_BASE */ 1070 } 1071 } 1072 1073 ret = regmap_read(regmap, reg, &val); 1074 if (ret) 1075 return ret; 1076 1077 return ((val >> bit) & mask); 1078 } 1079 1080 static int rockchip_verify_mux(struct rockchip_pin_bank *bank, 1081 int pin, int mux) 1082 { 1083 struct rockchip_pinctrl *info = bank->drvdata; 1084 struct device *dev = info->dev; 1085 int iomux_num = (pin / 8); 1086 1087 if (iomux_num > 3) 1088 return -EINVAL; 1089 1090 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { 1091 dev_err(dev, "pin %d is unrouted\n", pin); 1092 return -EINVAL; 1093 } 1094 1095 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) { 1096 if (mux != RK_FUNC_GPIO) { 1097 dev_err(dev, "pin %d only supports a gpio mux\n", pin); 1098 return -ENOTSUPP; 1099 } 1100 } 1101 1102 return 0; 1103 } 1104 1105 /* 1106 * Set a new mux function for a pin. 1107 * 1108 * The register is divided into the upper and lower 16 bit. When changing 1109 * a value, the previous register value is not read and changed. Instead 1110 * it seems the changed bits are marked in the upper 16 bit, while the 1111 * changed value gets set in the same offset in the lower 16 bit. 1112 * All pin settings seem to be 2 bit wide in both the upper and lower 1113 * parts. 1114 * @bank: pin bank to change 1115 * @pin: pin to change 1116 * @mux: new mux function to set 1117 */ 1118 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) 1119 { 1120 struct rockchip_pinctrl *info = bank->drvdata; 1121 struct rockchip_pin_ctrl *ctrl = info->ctrl; 1122 struct device *dev = info->dev; 1123 int iomux_num = (pin / 8); 1124 struct regmap *regmap; 1125 int reg, ret, mask, mux_type; 1126 u8 bit; 1127 u32 data, rmask, route_location, route_reg, route_val; 1128 1129 ret = rockchip_verify_mux(bank, pin, mux); 1130 if (ret < 0) 1131 return ret; 1132 1133 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) 1134 return 0; 1135 1136 dev_dbg(dev, "setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux); 1137 1138 if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) 1139 regmap = info->regmap_pmu; 1140 else if (bank->iomux[iomux_num].type & IOMUX_L_SOURCE_PMU) 1141 regmap = (pin % 8 < 4) ? info->regmap_pmu : info->regmap_base; 1142 else 1143 regmap = info->regmap_base; 1144 1145 /* get basic quadrupel of mux registers and the correct reg inside */ 1146 mux_type = bank->iomux[iomux_num].type; 1147 reg = bank->iomux[iomux_num].offset; 1148 if (mux_type & IOMUX_WIDTH_4BIT) { 1149 if ((pin % 8) >= 4) 1150 reg += 0x4; 1151 bit = (pin % 4) * 4; 1152 mask = 0xf; 1153 } else if (mux_type & IOMUX_WIDTH_3BIT) { 1154 if ((pin % 8) >= 5) 1155 reg += 0x4; 1156 bit = (pin % 8 % 5) * 3; 1157 mask = 0x7; 1158 } else { 1159 bit = (pin % 8) * 2; 1160 mask = 0x3; 1161 } 1162 1163 if (bank->recalced_mask & BIT(pin)) 1164 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); 1165 1166 if (ctrl->type == RK3588) { 1167 if (bank->bank_num == 0) { 1168 if ((pin >= RK_PB4) && (pin <= RK_PD7)) { 1169 if (mux < 8) { 1170 reg += 0x4000 - 0xC; /* PMU2_IOC_BASE */ 1171 data = (mask << (bit + 16)); 1172 rmask = data | (data >> 16); 1173 data |= (mux & mask) << bit; 1174 ret = regmap_update_bits(regmap, reg, rmask, data); 1175 } else { 1176 u32 reg0 = 0; 1177 1178 reg0 = reg + 0x4000 - 0xC; /* PMU2_IOC_BASE */ 1179 data = (mask << (bit + 16)); 1180 rmask = data | (data >> 16); 1181 data |= 8 << bit; 1182 ret = regmap_update_bits(regmap, reg0, rmask, data); 1183 1184 reg0 = reg + 0x8000; /* BUS_IOC_BASE */ 1185 data = (mask << (bit + 16)); 1186 rmask = data | (data >> 16); 1187 data |= mux << bit; 1188 regmap = info->regmap_base; 1189 ret |= regmap_update_bits(regmap, reg0, rmask, data); 1190 } 1191 } else { 1192 data = (mask << (bit + 16)); 1193 rmask = data | (data >> 16); 1194 data |= (mux & mask) << bit; 1195 ret = regmap_update_bits(regmap, reg, rmask, data); 1196 } 1197 return ret; 1198 } else if (bank->bank_num > 0) { 1199 reg += 0x8000; /* BUS_IOC_BASE */ 1200 } 1201 } 1202 1203 if (mux > mask) 1204 return -EINVAL; 1205 1206 if (bank->route_mask & BIT(pin)) { 1207 if (rockchip_get_mux_route(bank, pin, mux, &route_location, 1208 &route_reg, &route_val)) { 1209 struct regmap *route_regmap = regmap; 1210 1211 /* handle special locations */ 1212 switch (route_location) { 1213 case ROCKCHIP_ROUTE_PMU: 1214 route_regmap = info->regmap_pmu; 1215 break; 1216 case ROCKCHIP_ROUTE_GRF: 1217 route_regmap = info->regmap_base; 1218 break; 1219 } 1220 1221 ret = regmap_write(route_regmap, route_reg, route_val); 1222 if (ret) 1223 return ret; 1224 } 1225 } 1226 1227 data = (mask << (bit + 16)); 1228 rmask = data | (data >> 16); 1229 data |= (mux & mask) << bit; 1230 ret = regmap_update_bits(regmap, reg, rmask, data); 1231 1232 return ret; 1233 } 1234 1235 #define PX30_PULL_PMU_OFFSET 0x10 1236 #define PX30_PULL_GRF_OFFSET 0x60 1237 #define PX30_PULL_BITS_PER_PIN 2 1238 #define PX30_PULL_PINS_PER_REG 8 1239 #define PX30_PULL_BANK_STRIDE 16 1240 1241 static int px30_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1242 int pin_num, struct regmap **regmap, 1243 int *reg, u8 *bit) 1244 { 1245 struct rockchip_pinctrl *info = bank->drvdata; 1246 1247 /* The first 32 pins of the first bank are located in PMU */ 1248 if (bank->bank_num == 0) { 1249 *regmap = info->regmap_pmu; 1250 *reg = PX30_PULL_PMU_OFFSET; 1251 } else { 1252 *regmap = info->regmap_base; 1253 *reg = PX30_PULL_GRF_OFFSET; 1254 1255 /* correct the offset, as we're starting with the 2nd bank */ 1256 *reg -= 0x10; 1257 *reg += bank->bank_num * PX30_PULL_BANK_STRIDE; 1258 } 1259 1260 *reg += ((pin_num / PX30_PULL_PINS_PER_REG) * 4); 1261 *bit = (pin_num % PX30_PULL_PINS_PER_REG); 1262 *bit *= PX30_PULL_BITS_PER_PIN; 1263 1264 return 0; 1265 } 1266 1267 #define PX30_DRV_PMU_OFFSET 0x20 1268 #define PX30_DRV_GRF_OFFSET 0xf0 1269 #define PX30_DRV_BITS_PER_PIN 2 1270 #define PX30_DRV_PINS_PER_REG 8 1271 #define PX30_DRV_BANK_STRIDE 16 1272 1273 static int px30_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1274 int pin_num, struct regmap **regmap, 1275 int *reg, u8 *bit) 1276 { 1277 struct rockchip_pinctrl *info = bank->drvdata; 1278 1279 /* The first 32 pins of the first bank are located in PMU */ 1280 if (bank->bank_num == 0) { 1281 *regmap = info->regmap_pmu; 1282 *reg = PX30_DRV_PMU_OFFSET; 1283 } else { 1284 *regmap = info->regmap_base; 1285 *reg = PX30_DRV_GRF_OFFSET; 1286 1287 /* correct the offset, as we're starting with the 2nd bank */ 1288 *reg -= 0x10; 1289 *reg += bank->bank_num * PX30_DRV_BANK_STRIDE; 1290 } 1291 1292 *reg += ((pin_num / PX30_DRV_PINS_PER_REG) * 4); 1293 *bit = (pin_num % PX30_DRV_PINS_PER_REG); 1294 *bit *= PX30_DRV_BITS_PER_PIN; 1295 1296 return 0; 1297 } 1298 1299 #define PX30_SCHMITT_PMU_OFFSET 0x38 1300 #define PX30_SCHMITT_GRF_OFFSET 0xc0 1301 #define PX30_SCHMITT_PINS_PER_PMU_REG 16 1302 #define PX30_SCHMITT_BANK_STRIDE 16 1303 #define PX30_SCHMITT_PINS_PER_GRF_REG 8 1304 1305 static int px30_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1306 int pin_num, 1307 struct regmap **regmap, 1308 int *reg, u8 *bit) 1309 { 1310 struct rockchip_pinctrl *info = bank->drvdata; 1311 int pins_per_reg; 1312 1313 if (bank->bank_num == 0) { 1314 *regmap = info->regmap_pmu; 1315 *reg = PX30_SCHMITT_PMU_OFFSET; 1316 pins_per_reg = PX30_SCHMITT_PINS_PER_PMU_REG; 1317 } else { 1318 *regmap = info->regmap_base; 1319 *reg = PX30_SCHMITT_GRF_OFFSET; 1320 pins_per_reg = PX30_SCHMITT_PINS_PER_GRF_REG; 1321 *reg += (bank->bank_num - 1) * PX30_SCHMITT_BANK_STRIDE; 1322 } 1323 1324 *reg += ((pin_num / pins_per_reg) * 4); 1325 *bit = pin_num % pins_per_reg; 1326 1327 return 0; 1328 } 1329 1330 #define RV1108_PULL_PMU_OFFSET 0x10 1331 #define RV1108_PULL_OFFSET 0x110 1332 #define RV1108_PULL_PINS_PER_REG 8 1333 #define RV1108_PULL_BITS_PER_PIN 2 1334 #define RV1108_PULL_BANK_STRIDE 16 1335 1336 static int rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1337 int pin_num, struct regmap **regmap, 1338 int *reg, u8 *bit) 1339 { 1340 struct rockchip_pinctrl *info = bank->drvdata; 1341 1342 /* The first 24 pins of the first bank are located in PMU */ 1343 if (bank->bank_num == 0) { 1344 *regmap = info->regmap_pmu; 1345 *reg = RV1108_PULL_PMU_OFFSET; 1346 } else { 1347 *reg = RV1108_PULL_OFFSET; 1348 *regmap = info->regmap_base; 1349 /* correct the offset, as we're starting with the 2nd bank */ 1350 *reg -= 0x10; 1351 *reg += bank->bank_num * RV1108_PULL_BANK_STRIDE; 1352 } 1353 1354 *reg += ((pin_num / RV1108_PULL_PINS_PER_REG) * 4); 1355 *bit = (pin_num % RV1108_PULL_PINS_PER_REG); 1356 *bit *= RV1108_PULL_BITS_PER_PIN; 1357 1358 return 0; 1359 } 1360 1361 #define RV1108_DRV_PMU_OFFSET 0x20 1362 #define RV1108_DRV_GRF_OFFSET 0x210 1363 #define RV1108_DRV_BITS_PER_PIN 2 1364 #define RV1108_DRV_PINS_PER_REG 8 1365 #define RV1108_DRV_BANK_STRIDE 16 1366 1367 static int rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1368 int pin_num, struct regmap **regmap, 1369 int *reg, u8 *bit) 1370 { 1371 struct rockchip_pinctrl *info = bank->drvdata; 1372 1373 /* The first 24 pins of the first bank are located in PMU */ 1374 if (bank->bank_num == 0) { 1375 *regmap = info->regmap_pmu; 1376 *reg = RV1108_DRV_PMU_OFFSET; 1377 } else { 1378 *regmap = info->regmap_base; 1379 *reg = RV1108_DRV_GRF_OFFSET; 1380 1381 /* correct the offset, as we're starting with the 2nd bank */ 1382 *reg -= 0x10; 1383 *reg += bank->bank_num * RV1108_DRV_BANK_STRIDE; 1384 } 1385 1386 *reg += ((pin_num / RV1108_DRV_PINS_PER_REG) * 4); 1387 *bit = pin_num % RV1108_DRV_PINS_PER_REG; 1388 *bit *= RV1108_DRV_BITS_PER_PIN; 1389 1390 return 0; 1391 } 1392 1393 #define RV1108_SCHMITT_PMU_OFFSET 0x30 1394 #define RV1108_SCHMITT_GRF_OFFSET 0x388 1395 #define RV1108_SCHMITT_BANK_STRIDE 8 1396 #define RV1108_SCHMITT_PINS_PER_GRF_REG 16 1397 #define RV1108_SCHMITT_PINS_PER_PMU_REG 8 1398 1399 static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1400 int pin_num, 1401 struct regmap **regmap, 1402 int *reg, u8 *bit) 1403 { 1404 struct rockchip_pinctrl *info = bank->drvdata; 1405 int pins_per_reg; 1406 1407 if (bank->bank_num == 0) { 1408 *regmap = info->regmap_pmu; 1409 *reg = RV1108_SCHMITT_PMU_OFFSET; 1410 pins_per_reg = RV1108_SCHMITT_PINS_PER_PMU_REG; 1411 } else { 1412 *regmap = info->regmap_base; 1413 *reg = RV1108_SCHMITT_GRF_OFFSET; 1414 pins_per_reg = RV1108_SCHMITT_PINS_PER_GRF_REG; 1415 *reg += (bank->bank_num - 1) * RV1108_SCHMITT_BANK_STRIDE; 1416 } 1417 *reg += ((pin_num / pins_per_reg) * 4); 1418 *bit = pin_num % pins_per_reg; 1419 1420 return 0; 1421 } 1422 1423 #define RV1126_PULL_PMU_OFFSET 0x40 1424 #define RV1126_PULL_GRF_GPIO1A0_OFFSET 0x10108 1425 #define RV1126_PULL_PINS_PER_REG 8 1426 #define RV1126_PULL_BITS_PER_PIN 2 1427 #define RV1126_PULL_BANK_STRIDE 16 1428 #define RV1126_GPIO_C4_D7(p) (p >= 20 && p <= 31) /* GPIO0_C4 ~ GPIO0_D7 */ 1429 1430 static int rv1126_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1431 int pin_num, struct regmap **regmap, 1432 int *reg, u8 *bit) 1433 { 1434 struct rockchip_pinctrl *info = bank->drvdata; 1435 1436 /* The first 24 pins of the first bank are located in PMU */ 1437 if (bank->bank_num == 0) { 1438 if (RV1126_GPIO_C4_D7(pin_num)) { 1439 *regmap = info->regmap_base; 1440 *reg = RV1126_PULL_GRF_GPIO1A0_OFFSET; 1441 *reg -= (((31 - pin_num) / RV1126_PULL_PINS_PER_REG + 1) * 4); 1442 *bit = pin_num % RV1126_PULL_PINS_PER_REG; 1443 *bit *= RV1126_PULL_BITS_PER_PIN; 1444 return 0; 1445 } 1446 *regmap = info->regmap_pmu; 1447 *reg = RV1126_PULL_PMU_OFFSET; 1448 } else { 1449 *reg = RV1126_PULL_GRF_GPIO1A0_OFFSET; 1450 *regmap = info->regmap_base; 1451 *reg += (bank->bank_num - 1) * RV1126_PULL_BANK_STRIDE; 1452 } 1453 1454 *reg += ((pin_num / RV1126_PULL_PINS_PER_REG) * 4); 1455 *bit = (pin_num % RV1126_PULL_PINS_PER_REG); 1456 *bit *= RV1126_PULL_BITS_PER_PIN; 1457 1458 return 0; 1459 } 1460 1461 #define RV1126_DRV_PMU_OFFSET 0x20 1462 #define RV1126_DRV_GRF_GPIO1A0_OFFSET 0x10090 1463 #define RV1126_DRV_BITS_PER_PIN 4 1464 #define RV1126_DRV_PINS_PER_REG 4 1465 #define RV1126_DRV_BANK_STRIDE 32 1466 1467 static int rv1126_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1468 int pin_num, struct regmap **regmap, 1469 int *reg, u8 *bit) 1470 { 1471 struct rockchip_pinctrl *info = bank->drvdata; 1472 1473 /* The first 24 pins of the first bank are located in PMU */ 1474 if (bank->bank_num == 0) { 1475 if (RV1126_GPIO_C4_D7(pin_num)) { 1476 *regmap = info->regmap_base; 1477 *reg = RV1126_DRV_GRF_GPIO1A0_OFFSET; 1478 *reg -= (((31 - pin_num) / RV1126_DRV_PINS_PER_REG + 1) * 4); 1479 *reg -= 0x4; 1480 *bit = pin_num % RV1126_DRV_PINS_PER_REG; 1481 *bit *= RV1126_DRV_BITS_PER_PIN; 1482 return 0; 1483 } 1484 *regmap = info->regmap_pmu; 1485 *reg = RV1126_DRV_PMU_OFFSET; 1486 } else { 1487 *regmap = info->regmap_base; 1488 *reg = RV1126_DRV_GRF_GPIO1A0_OFFSET; 1489 *reg += (bank->bank_num - 1) * RV1126_DRV_BANK_STRIDE; 1490 } 1491 1492 *reg += ((pin_num / RV1126_DRV_PINS_PER_REG) * 4); 1493 *bit = pin_num % RV1126_DRV_PINS_PER_REG; 1494 *bit *= RV1126_DRV_BITS_PER_PIN; 1495 1496 return 0; 1497 } 1498 1499 #define RV1126_SCHMITT_PMU_OFFSET 0x60 1500 #define RV1126_SCHMITT_GRF_GPIO1A0_OFFSET 0x10188 1501 #define RV1126_SCHMITT_BANK_STRIDE 16 1502 #define RV1126_SCHMITT_PINS_PER_GRF_REG 8 1503 #define RV1126_SCHMITT_PINS_PER_PMU_REG 8 1504 1505 static int rv1126_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1506 int pin_num, 1507 struct regmap **regmap, 1508 int *reg, u8 *bit) 1509 { 1510 struct rockchip_pinctrl *info = bank->drvdata; 1511 int pins_per_reg; 1512 1513 if (bank->bank_num == 0) { 1514 if (RV1126_GPIO_C4_D7(pin_num)) { 1515 *regmap = info->regmap_base; 1516 *reg = RV1126_SCHMITT_GRF_GPIO1A0_OFFSET; 1517 *reg -= (((31 - pin_num) / RV1126_SCHMITT_PINS_PER_GRF_REG + 1) * 4); 1518 *bit = pin_num % RV1126_SCHMITT_PINS_PER_GRF_REG; 1519 return 0; 1520 } 1521 *regmap = info->regmap_pmu; 1522 *reg = RV1126_SCHMITT_PMU_OFFSET; 1523 pins_per_reg = RV1126_SCHMITT_PINS_PER_PMU_REG; 1524 } else { 1525 *regmap = info->regmap_base; 1526 *reg = RV1126_SCHMITT_GRF_GPIO1A0_OFFSET; 1527 pins_per_reg = RV1126_SCHMITT_PINS_PER_GRF_REG; 1528 *reg += (bank->bank_num - 1) * RV1126_SCHMITT_BANK_STRIDE; 1529 } 1530 *reg += ((pin_num / pins_per_reg) * 4); 1531 *bit = pin_num % pins_per_reg; 1532 1533 return 0; 1534 } 1535 1536 #define RK3308_SCHMITT_PINS_PER_REG 8 1537 #define RK3308_SCHMITT_BANK_STRIDE 16 1538 #define RK3308_SCHMITT_GRF_OFFSET 0x1a0 1539 1540 static int rk3308_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1541 int pin_num, struct regmap **regmap, 1542 int *reg, u8 *bit) 1543 { 1544 struct rockchip_pinctrl *info = bank->drvdata; 1545 1546 *regmap = info->regmap_base; 1547 *reg = RK3308_SCHMITT_GRF_OFFSET; 1548 1549 *reg += bank->bank_num * RK3308_SCHMITT_BANK_STRIDE; 1550 *reg += ((pin_num / RK3308_SCHMITT_PINS_PER_REG) * 4); 1551 *bit = pin_num % RK3308_SCHMITT_PINS_PER_REG; 1552 1553 return 0; 1554 } 1555 1556 #define RK2928_PULL_OFFSET 0x118 1557 #define RK2928_PULL_PINS_PER_REG 16 1558 #define RK2928_PULL_BANK_STRIDE 8 1559 1560 static int rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1561 int pin_num, struct regmap **regmap, 1562 int *reg, u8 *bit) 1563 { 1564 struct rockchip_pinctrl *info = bank->drvdata; 1565 1566 *regmap = info->regmap_base; 1567 *reg = RK2928_PULL_OFFSET; 1568 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; 1569 *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4; 1570 1571 *bit = pin_num % RK2928_PULL_PINS_PER_REG; 1572 1573 return 0; 1574 }; 1575 1576 #define RK3128_PULL_OFFSET 0x118 1577 1578 static int rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1579 int pin_num, struct regmap **regmap, 1580 int *reg, u8 *bit) 1581 { 1582 struct rockchip_pinctrl *info = bank->drvdata; 1583 1584 *regmap = info->regmap_base; 1585 *reg = RK3128_PULL_OFFSET; 1586 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; 1587 *reg += ((pin_num / RK2928_PULL_PINS_PER_REG) * 4); 1588 1589 *bit = pin_num % RK2928_PULL_PINS_PER_REG; 1590 1591 return 0; 1592 } 1593 1594 #define RK3188_PULL_OFFSET 0x164 1595 #define RK3188_PULL_BITS_PER_PIN 2 1596 #define RK3188_PULL_PINS_PER_REG 8 1597 #define RK3188_PULL_BANK_STRIDE 16 1598 #define RK3188_PULL_PMU_OFFSET 0x64 1599 1600 static int rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1601 int pin_num, struct regmap **regmap, 1602 int *reg, u8 *bit) 1603 { 1604 struct rockchip_pinctrl *info = bank->drvdata; 1605 1606 /* The first 12 pins of the first bank are located elsewhere */ 1607 if (bank->bank_num == 0 && pin_num < 12) { 1608 *regmap = info->regmap_pmu ? info->regmap_pmu 1609 : bank->regmap_pull; 1610 *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0; 1611 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1612 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 1613 *bit *= RK3188_PULL_BITS_PER_PIN; 1614 } else { 1615 *regmap = info->regmap_pull ? info->regmap_pull 1616 : info->regmap_base; 1617 *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET; 1618 1619 /* correct the offset, as it is the 2nd pull register */ 1620 *reg -= 4; 1621 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1622 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1623 1624 /* 1625 * The bits in these registers have an inverse ordering 1626 * with the lowest pin being in bits 15:14 and the highest 1627 * pin in bits 1:0 1628 */ 1629 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG); 1630 *bit *= RK3188_PULL_BITS_PER_PIN; 1631 } 1632 1633 return 0; 1634 } 1635 1636 #define RK3288_PULL_OFFSET 0x140 1637 static int rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1638 int pin_num, struct regmap **regmap, 1639 int *reg, u8 *bit) 1640 { 1641 struct rockchip_pinctrl *info = bank->drvdata; 1642 1643 /* The first 24 pins of the first bank are located in PMU */ 1644 if (bank->bank_num == 0) { 1645 *regmap = info->regmap_pmu; 1646 *reg = RK3188_PULL_PMU_OFFSET; 1647 1648 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1649 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 1650 *bit *= RK3188_PULL_BITS_PER_PIN; 1651 } else { 1652 *regmap = info->regmap_base; 1653 *reg = RK3288_PULL_OFFSET; 1654 1655 /* correct the offset, as we're starting with the 2nd bank */ 1656 *reg -= 0x10; 1657 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1658 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1659 1660 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1661 *bit *= RK3188_PULL_BITS_PER_PIN; 1662 } 1663 1664 return 0; 1665 } 1666 1667 #define RK3288_DRV_PMU_OFFSET 0x70 1668 #define RK3288_DRV_GRF_OFFSET 0x1c0 1669 #define RK3288_DRV_BITS_PER_PIN 2 1670 #define RK3288_DRV_PINS_PER_REG 8 1671 #define RK3288_DRV_BANK_STRIDE 16 1672 1673 static int rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1674 int pin_num, struct regmap **regmap, 1675 int *reg, u8 *bit) 1676 { 1677 struct rockchip_pinctrl *info = bank->drvdata; 1678 1679 /* The first 24 pins of the first bank are located in PMU */ 1680 if (bank->bank_num == 0) { 1681 *regmap = info->regmap_pmu; 1682 *reg = RK3288_DRV_PMU_OFFSET; 1683 1684 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1685 *bit = pin_num % RK3288_DRV_PINS_PER_REG; 1686 *bit *= RK3288_DRV_BITS_PER_PIN; 1687 } else { 1688 *regmap = info->regmap_base; 1689 *reg = RK3288_DRV_GRF_OFFSET; 1690 1691 /* correct the offset, as we're starting with the 2nd bank */ 1692 *reg -= 0x10; 1693 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 1694 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1695 1696 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 1697 *bit *= RK3288_DRV_BITS_PER_PIN; 1698 } 1699 1700 return 0; 1701 } 1702 1703 #define RK3228_PULL_OFFSET 0x100 1704 1705 static int rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1706 int pin_num, struct regmap **regmap, 1707 int *reg, u8 *bit) 1708 { 1709 struct rockchip_pinctrl *info = bank->drvdata; 1710 1711 *regmap = info->regmap_base; 1712 *reg = RK3228_PULL_OFFSET; 1713 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1714 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1715 1716 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1717 *bit *= RK3188_PULL_BITS_PER_PIN; 1718 1719 return 0; 1720 } 1721 1722 #define RK3228_DRV_GRF_OFFSET 0x200 1723 1724 static int rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1725 int pin_num, struct regmap **regmap, 1726 int *reg, u8 *bit) 1727 { 1728 struct rockchip_pinctrl *info = bank->drvdata; 1729 1730 *regmap = info->regmap_base; 1731 *reg = RK3228_DRV_GRF_OFFSET; 1732 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 1733 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1734 1735 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 1736 *bit *= RK3288_DRV_BITS_PER_PIN; 1737 1738 return 0; 1739 } 1740 1741 #define RK3308_PULL_OFFSET 0xa0 1742 1743 static int rk3308_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1744 int pin_num, struct regmap **regmap, 1745 int *reg, u8 *bit) 1746 { 1747 struct rockchip_pinctrl *info = bank->drvdata; 1748 1749 *regmap = info->regmap_base; 1750 *reg = RK3308_PULL_OFFSET; 1751 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1752 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1753 1754 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1755 *bit *= RK3188_PULL_BITS_PER_PIN; 1756 1757 return 0; 1758 } 1759 1760 #define RK3308_DRV_GRF_OFFSET 0x100 1761 1762 static int rk3308_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1763 int pin_num, struct regmap **regmap, 1764 int *reg, u8 *bit) 1765 { 1766 struct rockchip_pinctrl *info = bank->drvdata; 1767 1768 *regmap = info->regmap_base; 1769 *reg = RK3308_DRV_GRF_OFFSET; 1770 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 1771 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1772 1773 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 1774 *bit *= RK3288_DRV_BITS_PER_PIN; 1775 1776 return 0; 1777 } 1778 1779 #define RK3368_PULL_GRF_OFFSET 0x100 1780 #define RK3368_PULL_PMU_OFFSET 0x10 1781 1782 static int rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1783 int pin_num, struct regmap **regmap, 1784 int *reg, u8 *bit) 1785 { 1786 struct rockchip_pinctrl *info = bank->drvdata; 1787 1788 /* The first 32 pins of the first bank are located in PMU */ 1789 if (bank->bank_num == 0) { 1790 *regmap = info->regmap_pmu; 1791 *reg = RK3368_PULL_PMU_OFFSET; 1792 1793 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1794 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 1795 *bit *= RK3188_PULL_BITS_PER_PIN; 1796 } else { 1797 *regmap = info->regmap_base; 1798 *reg = RK3368_PULL_GRF_OFFSET; 1799 1800 /* correct the offset, as we're starting with the 2nd bank */ 1801 *reg -= 0x10; 1802 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1803 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1804 1805 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1806 *bit *= RK3188_PULL_BITS_PER_PIN; 1807 } 1808 1809 return 0; 1810 } 1811 1812 #define RK3368_DRV_PMU_OFFSET 0x20 1813 #define RK3368_DRV_GRF_OFFSET 0x200 1814 1815 static int rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1816 int pin_num, struct regmap **regmap, 1817 int *reg, u8 *bit) 1818 { 1819 struct rockchip_pinctrl *info = bank->drvdata; 1820 1821 /* The first 32 pins of the first bank are located in PMU */ 1822 if (bank->bank_num == 0) { 1823 *regmap = info->regmap_pmu; 1824 *reg = RK3368_DRV_PMU_OFFSET; 1825 1826 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1827 *bit = pin_num % RK3288_DRV_PINS_PER_REG; 1828 *bit *= RK3288_DRV_BITS_PER_PIN; 1829 } else { 1830 *regmap = info->regmap_base; 1831 *reg = RK3368_DRV_GRF_OFFSET; 1832 1833 /* correct the offset, as we're starting with the 2nd bank */ 1834 *reg -= 0x10; 1835 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 1836 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1837 1838 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 1839 *bit *= RK3288_DRV_BITS_PER_PIN; 1840 } 1841 1842 return 0; 1843 } 1844 1845 #define RK3399_PULL_GRF_OFFSET 0xe040 1846 #define RK3399_PULL_PMU_OFFSET 0x40 1847 #define RK3399_DRV_3BITS_PER_PIN 3 1848 1849 static int rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1850 int pin_num, struct regmap **regmap, 1851 int *reg, u8 *bit) 1852 { 1853 struct rockchip_pinctrl *info = bank->drvdata; 1854 1855 /* The bank0:16 and bank1:32 pins are located in PMU */ 1856 if ((bank->bank_num == 0) || (bank->bank_num == 1)) { 1857 *regmap = info->regmap_pmu; 1858 *reg = RK3399_PULL_PMU_OFFSET; 1859 1860 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1861 1862 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1863 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 1864 *bit *= RK3188_PULL_BITS_PER_PIN; 1865 } else { 1866 *regmap = info->regmap_base; 1867 *reg = RK3399_PULL_GRF_OFFSET; 1868 1869 /* correct the offset, as we're starting with the 3rd bank */ 1870 *reg -= 0x20; 1871 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1872 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1873 1874 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1875 *bit *= RK3188_PULL_BITS_PER_PIN; 1876 } 1877 1878 return 0; 1879 } 1880 1881 static int rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1882 int pin_num, struct regmap **regmap, 1883 int *reg, u8 *bit) 1884 { 1885 struct rockchip_pinctrl *info = bank->drvdata; 1886 int drv_num = (pin_num / 8); 1887 1888 /* The bank0:16 and bank1:32 pins are located in PMU */ 1889 if ((bank->bank_num == 0) || (bank->bank_num == 1)) 1890 *regmap = info->regmap_pmu; 1891 else 1892 *regmap = info->regmap_base; 1893 1894 *reg = bank->drv[drv_num].offset; 1895 if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) || 1896 (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY)) 1897 *bit = (pin_num % 8) * 3; 1898 else 1899 *bit = (pin_num % 8) * 2; 1900 1901 return 0; 1902 } 1903 1904 #define RK3568_PULL_PMU_OFFSET 0x20 1905 #define RK3568_PULL_GRF_OFFSET 0x80 1906 #define RK3568_PULL_BITS_PER_PIN 2 1907 #define RK3568_PULL_PINS_PER_REG 8 1908 #define RK3568_PULL_BANK_STRIDE 0x10 1909 1910 static int rk3568_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1911 int pin_num, struct regmap **regmap, 1912 int *reg, u8 *bit) 1913 { 1914 struct rockchip_pinctrl *info = bank->drvdata; 1915 1916 if (bank->bank_num == 0) { 1917 *regmap = info->regmap_pmu; 1918 *reg = RK3568_PULL_PMU_OFFSET; 1919 *reg += bank->bank_num * RK3568_PULL_BANK_STRIDE; 1920 *reg += ((pin_num / RK3568_PULL_PINS_PER_REG) * 4); 1921 1922 *bit = pin_num % RK3568_PULL_PINS_PER_REG; 1923 *bit *= RK3568_PULL_BITS_PER_PIN; 1924 } else { 1925 *regmap = info->regmap_base; 1926 *reg = RK3568_PULL_GRF_OFFSET; 1927 *reg += (bank->bank_num - 1) * RK3568_PULL_BANK_STRIDE; 1928 *reg += ((pin_num / RK3568_PULL_PINS_PER_REG) * 4); 1929 1930 *bit = (pin_num % RK3568_PULL_PINS_PER_REG); 1931 *bit *= RK3568_PULL_BITS_PER_PIN; 1932 } 1933 1934 return 0; 1935 } 1936 1937 #define RK3568_DRV_PMU_OFFSET 0x70 1938 #define RK3568_DRV_GRF_OFFSET 0x200 1939 #define RK3568_DRV_BITS_PER_PIN 8 1940 #define RK3568_DRV_PINS_PER_REG 2 1941 #define RK3568_DRV_BANK_STRIDE 0x40 1942 1943 static int rk3568_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1944 int pin_num, struct regmap **regmap, 1945 int *reg, u8 *bit) 1946 { 1947 struct rockchip_pinctrl *info = bank->drvdata; 1948 1949 /* The first 32 pins of the first bank are located in PMU */ 1950 if (bank->bank_num == 0) { 1951 *regmap = info->regmap_pmu; 1952 *reg = RK3568_DRV_PMU_OFFSET; 1953 *reg += ((pin_num / RK3568_DRV_PINS_PER_REG) * 4); 1954 1955 *bit = pin_num % RK3568_DRV_PINS_PER_REG; 1956 *bit *= RK3568_DRV_BITS_PER_PIN; 1957 } else { 1958 *regmap = info->regmap_base; 1959 *reg = RK3568_DRV_GRF_OFFSET; 1960 *reg += (bank->bank_num - 1) * RK3568_DRV_BANK_STRIDE; 1961 *reg += ((pin_num / RK3568_DRV_PINS_PER_REG) * 4); 1962 1963 *bit = (pin_num % RK3568_DRV_PINS_PER_REG); 1964 *bit *= RK3568_DRV_BITS_PER_PIN; 1965 } 1966 1967 return 0; 1968 } 1969 1970 #define RK3588_PMU1_IOC_REG (0x0000) 1971 #define RK3588_PMU2_IOC_REG (0x4000) 1972 #define RK3588_BUS_IOC_REG (0x8000) 1973 #define RK3588_VCCIO1_4_IOC_REG (0x9000) 1974 #define RK3588_VCCIO3_5_IOC_REG (0xA000) 1975 #define RK3588_VCCIO2_IOC_REG (0xB000) 1976 #define RK3588_VCCIO6_IOC_REG (0xC000) 1977 #define RK3588_EMMC_IOC_REG (0xD000) 1978 1979 static const u32 rk3588_ds_regs[][2] = { 1980 {RK_GPIO0_A0, RK3588_PMU1_IOC_REG + 0x0010}, 1981 {RK_GPIO0_A4, RK3588_PMU1_IOC_REG + 0x0014}, 1982 {RK_GPIO0_B0, RK3588_PMU1_IOC_REG + 0x0018}, 1983 {RK_GPIO0_B4, RK3588_PMU2_IOC_REG + 0x0014}, 1984 {RK_GPIO0_C0, RK3588_PMU2_IOC_REG + 0x0018}, 1985 {RK_GPIO0_C4, RK3588_PMU2_IOC_REG + 0x001C}, 1986 {RK_GPIO0_D0, RK3588_PMU2_IOC_REG + 0x0020}, 1987 {RK_GPIO0_D4, RK3588_PMU2_IOC_REG + 0x0024}, 1988 {RK_GPIO1_A0, RK3588_VCCIO1_4_IOC_REG + 0x0020}, 1989 {RK_GPIO1_A4, RK3588_VCCIO1_4_IOC_REG + 0x0024}, 1990 {RK_GPIO1_B0, RK3588_VCCIO1_4_IOC_REG + 0x0028}, 1991 {RK_GPIO1_B4, RK3588_VCCIO1_4_IOC_REG + 0x002C}, 1992 {RK_GPIO1_C0, RK3588_VCCIO1_4_IOC_REG + 0x0030}, 1993 {RK_GPIO1_C4, RK3588_VCCIO1_4_IOC_REG + 0x0034}, 1994 {RK_GPIO1_D0, RK3588_VCCIO1_4_IOC_REG + 0x0038}, 1995 {RK_GPIO1_D4, RK3588_VCCIO1_4_IOC_REG + 0x003C}, 1996 {RK_GPIO2_A0, RK3588_EMMC_IOC_REG + 0x0040}, 1997 {RK_GPIO2_A4, RK3588_VCCIO3_5_IOC_REG + 0x0044}, 1998 {RK_GPIO2_B0, RK3588_VCCIO3_5_IOC_REG + 0x0048}, 1999 {RK_GPIO2_B4, RK3588_VCCIO3_5_IOC_REG + 0x004C}, 2000 {RK_GPIO2_C0, RK3588_VCCIO3_5_IOC_REG + 0x0050}, 2001 {RK_GPIO2_C4, RK3588_VCCIO3_5_IOC_REG + 0x0054}, 2002 {RK_GPIO2_D0, RK3588_EMMC_IOC_REG + 0x0058}, 2003 {RK_GPIO2_D4, RK3588_EMMC_IOC_REG + 0x005C}, 2004 {RK_GPIO3_A0, RK3588_VCCIO3_5_IOC_REG + 0x0060}, 2005 {RK_GPIO3_A4, RK3588_VCCIO3_5_IOC_REG + 0x0064}, 2006 {RK_GPIO3_B0, RK3588_VCCIO3_5_IOC_REG + 0x0068}, 2007 {RK_GPIO3_B4, RK3588_VCCIO3_5_IOC_REG + 0x006C}, 2008 {RK_GPIO3_C0, RK3588_VCCIO3_5_IOC_REG + 0x0070}, 2009 {RK_GPIO3_C4, RK3588_VCCIO3_5_IOC_REG + 0x0074}, 2010 {RK_GPIO3_D0, RK3588_VCCIO3_5_IOC_REG + 0x0078}, 2011 {RK_GPIO3_D4, RK3588_VCCIO3_5_IOC_REG + 0x007C}, 2012 {RK_GPIO4_A0, RK3588_VCCIO6_IOC_REG + 0x0080}, 2013 {RK_GPIO4_A4, RK3588_VCCIO6_IOC_REG + 0x0084}, 2014 {RK_GPIO4_B0, RK3588_VCCIO6_IOC_REG + 0x0088}, 2015 {RK_GPIO4_B4, RK3588_VCCIO6_IOC_REG + 0x008C}, 2016 {RK_GPIO4_C0, RK3588_VCCIO6_IOC_REG + 0x0090}, 2017 {RK_GPIO4_C2, RK3588_VCCIO3_5_IOC_REG + 0x0090}, 2018 {RK_GPIO4_C4, RK3588_VCCIO3_5_IOC_REG + 0x0094}, 2019 {RK_GPIO4_D0, RK3588_VCCIO2_IOC_REG + 0x0098}, 2020 {RK_GPIO4_D4, RK3588_VCCIO2_IOC_REG + 0x009C}, 2021 }; 2022 2023 static const u32 rk3588_p_regs[][2] = { 2024 {RK_GPIO0_A0, RK3588_PMU1_IOC_REG + 0x0020}, 2025 {RK_GPIO0_B0, RK3588_PMU1_IOC_REG + 0x0024}, 2026 {RK_GPIO0_B5, RK3588_PMU2_IOC_REG + 0x0028}, 2027 {RK_GPIO0_C0, RK3588_PMU2_IOC_REG + 0x002C}, 2028 {RK_GPIO0_D0, RK3588_PMU2_IOC_REG + 0x0030}, 2029 {RK_GPIO1_A0, RK3588_VCCIO1_4_IOC_REG + 0x0110}, 2030 {RK_GPIO1_B0, RK3588_VCCIO1_4_IOC_REG + 0x0114}, 2031 {RK_GPIO1_C0, RK3588_VCCIO1_4_IOC_REG + 0x0118}, 2032 {RK_GPIO1_D0, RK3588_VCCIO1_4_IOC_REG + 0x011C}, 2033 {RK_GPIO2_A0, RK3588_EMMC_IOC_REG + 0x0120}, 2034 {RK_GPIO2_A6, RK3588_VCCIO3_5_IOC_REG + 0x0120}, 2035 {RK_GPIO2_B0, RK3588_VCCIO3_5_IOC_REG + 0x0124}, 2036 {RK_GPIO2_C0, RK3588_VCCIO3_5_IOC_REG + 0x0128}, 2037 {RK_GPIO2_D0, RK3588_EMMC_IOC_REG + 0x012C}, 2038 {RK_GPIO3_A0, RK3588_VCCIO3_5_IOC_REG + 0x0130}, 2039 {RK_GPIO3_B0, RK3588_VCCIO3_5_IOC_REG + 0x0134}, 2040 {RK_GPIO3_C0, RK3588_VCCIO3_5_IOC_REG + 0x0138}, 2041 {RK_GPIO3_D0, RK3588_VCCIO3_5_IOC_REG + 0x013C}, 2042 {RK_GPIO4_A0, RK3588_VCCIO6_IOC_REG + 0x0140}, 2043 {RK_GPIO4_B0, RK3588_VCCIO6_IOC_REG + 0x0144}, 2044 {RK_GPIO4_C0, RK3588_VCCIO6_IOC_REG + 0x0148}, 2045 {RK_GPIO4_C2, RK3588_VCCIO3_5_IOC_REG + 0x0148}, 2046 {RK_GPIO4_D0, RK3588_VCCIO2_IOC_REG + 0x014C}, 2047 }; 2048 2049 static const u32 rk3588_smt_regs[][2] = { 2050 {RK_GPIO0_A0, RK3588_PMU1_IOC_REG + 0x0030}, 2051 {RK_GPIO0_B0, RK3588_PMU1_IOC_REG + 0x0034}, 2052 {RK_GPIO0_B5, RK3588_PMU2_IOC_REG + 0x0040}, 2053 {RK_GPIO0_C0, RK3588_PMU2_IOC_REG + 0x0044}, 2054 {RK_GPIO0_D0, RK3588_PMU2_IOC_REG + 0x0048}, 2055 {RK_GPIO1_A0, RK3588_VCCIO1_4_IOC_REG + 0x0210}, 2056 {RK_GPIO1_B0, RK3588_VCCIO1_4_IOC_REG + 0x0214}, 2057 {RK_GPIO1_C0, RK3588_VCCIO1_4_IOC_REG + 0x0218}, 2058 {RK_GPIO1_D0, RK3588_VCCIO1_4_IOC_REG + 0x021C}, 2059 {RK_GPIO2_A0, RK3588_EMMC_IOC_REG + 0x0220}, 2060 {RK_GPIO2_A6, RK3588_VCCIO3_5_IOC_REG + 0x0220}, 2061 {RK_GPIO2_B0, RK3588_VCCIO3_5_IOC_REG + 0x0224}, 2062 {RK_GPIO2_C0, RK3588_VCCIO3_5_IOC_REG + 0x0228}, 2063 {RK_GPIO2_D0, RK3588_EMMC_IOC_REG + 0x022C}, 2064 {RK_GPIO3_A0, RK3588_VCCIO3_5_IOC_REG + 0x0230}, 2065 {RK_GPIO3_B0, RK3588_VCCIO3_5_IOC_REG + 0x0234}, 2066 {RK_GPIO3_C0, RK3588_VCCIO3_5_IOC_REG + 0x0238}, 2067 {RK_GPIO3_D0, RK3588_VCCIO3_5_IOC_REG + 0x023C}, 2068 {RK_GPIO4_A0, RK3588_VCCIO6_IOC_REG + 0x0240}, 2069 {RK_GPIO4_B0, RK3588_VCCIO6_IOC_REG + 0x0244}, 2070 {RK_GPIO4_C0, RK3588_VCCIO6_IOC_REG + 0x0248}, 2071 {RK_GPIO4_C2, RK3588_VCCIO3_5_IOC_REG + 0x0248}, 2072 {RK_GPIO4_D0, RK3588_VCCIO2_IOC_REG + 0x024C}, 2073 }; 2074 2075 #define RK3588_PULL_BITS_PER_PIN 2 2076 #define RK3588_PULL_PINS_PER_REG 8 2077 2078 static int rk3588_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 2079 int pin_num, struct regmap **regmap, 2080 int *reg, u8 *bit) 2081 { 2082 struct rockchip_pinctrl *info = bank->drvdata; 2083 u8 bank_num = bank->bank_num; 2084 u32 pin = bank_num * 32 + pin_num; 2085 int i; 2086 2087 for (i = ARRAY_SIZE(rk3588_p_regs) - 1; i >= 0; i--) { 2088 if (pin >= rk3588_p_regs[i][0]) { 2089 *reg = rk3588_p_regs[i][1]; 2090 *regmap = info->regmap_base; 2091 *bit = pin_num % RK3588_PULL_PINS_PER_REG; 2092 *bit *= RK3588_PULL_BITS_PER_PIN; 2093 return 0; 2094 } 2095 } 2096 2097 return -EINVAL; 2098 } 2099 2100 #define RK3588_DRV_BITS_PER_PIN 4 2101 #define RK3588_DRV_PINS_PER_REG 4 2102 2103 static int rk3588_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 2104 int pin_num, struct regmap **regmap, 2105 int *reg, u8 *bit) 2106 { 2107 struct rockchip_pinctrl *info = bank->drvdata; 2108 u8 bank_num = bank->bank_num; 2109 u32 pin = bank_num * 32 + pin_num; 2110 int i; 2111 2112 for (i = ARRAY_SIZE(rk3588_ds_regs) - 1; i >= 0; i--) { 2113 if (pin >= rk3588_ds_regs[i][0]) { 2114 *reg = rk3588_ds_regs[i][1]; 2115 *regmap = info->regmap_base; 2116 *bit = pin_num % RK3588_DRV_PINS_PER_REG; 2117 *bit *= RK3588_DRV_BITS_PER_PIN; 2118 return 0; 2119 } 2120 } 2121 2122 return -EINVAL; 2123 } 2124 2125 #define RK3588_SMT_BITS_PER_PIN 1 2126 #define RK3588_SMT_PINS_PER_REG 8 2127 2128 static int rk3588_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 2129 int pin_num, 2130 struct regmap **regmap, 2131 int *reg, u8 *bit) 2132 { 2133 struct rockchip_pinctrl *info = bank->drvdata; 2134 u8 bank_num = bank->bank_num; 2135 u32 pin = bank_num * 32 + pin_num; 2136 int i; 2137 2138 for (i = ARRAY_SIZE(rk3588_smt_regs) - 1; i >= 0; i--) { 2139 if (pin >= rk3588_smt_regs[i][0]) { 2140 *reg = rk3588_smt_regs[i][1]; 2141 *regmap = info->regmap_base; 2142 *bit = pin_num % RK3588_SMT_PINS_PER_REG; 2143 *bit *= RK3588_SMT_BITS_PER_PIN; 2144 return 0; 2145 } 2146 } 2147 2148 return -EINVAL; 2149 } 2150 2151 static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = { 2152 { 2, 4, 8, 12, -1, -1, -1, -1 }, 2153 { 3, 6, 9, 12, -1, -1, -1, -1 }, 2154 { 5, 10, 15, 20, -1, -1, -1, -1 }, 2155 { 4, 6, 8, 10, 12, 14, 16, 18 }, 2156 { 4, 7, 10, 13, 16, 19, 22, 26 } 2157 }; 2158 2159 static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank, 2160 int pin_num) 2161 { 2162 struct rockchip_pinctrl *info = bank->drvdata; 2163 struct rockchip_pin_ctrl *ctrl = info->ctrl; 2164 struct device *dev = info->dev; 2165 struct regmap *regmap; 2166 int reg, ret; 2167 u32 data, temp, rmask_bits; 2168 u8 bit; 2169 int drv_type = bank->drv[pin_num / 8].drv_type; 2170 2171 ret = ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); 2172 if (ret) 2173 return ret; 2174 2175 switch (drv_type) { 2176 case DRV_TYPE_IO_1V8_3V0_AUTO: 2177 case DRV_TYPE_IO_3V3_ONLY: 2178 rmask_bits = RK3399_DRV_3BITS_PER_PIN; 2179 switch (bit) { 2180 case 0 ... 12: 2181 /* regular case, nothing to do */ 2182 break; 2183 case 15: 2184 /* 2185 * drive-strength offset is special, as it is 2186 * spread over 2 registers 2187 */ 2188 ret = regmap_read(regmap, reg, &data); 2189 if (ret) 2190 return ret; 2191 2192 ret = regmap_read(regmap, reg + 0x4, &temp); 2193 if (ret) 2194 return ret; 2195 2196 /* 2197 * the bit data[15] contains bit 0 of the value 2198 * while temp[1:0] contains bits 2 and 1 2199 */ 2200 data >>= 15; 2201 temp &= 0x3; 2202 temp <<= 1; 2203 data |= temp; 2204 2205 return rockchip_perpin_drv_list[drv_type][data]; 2206 case 18 ... 21: 2207 /* setting fully enclosed in the second register */ 2208 reg += 4; 2209 bit -= 16; 2210 break; 2211 default: 2212 dev_err(dev, "unsupported bit: %d for pinctrl drive type: %d\n", 2213 bit, drv_type); 2214 return -EINVAL; 2215 } 2216 2217 break; 2218 case DRV_TYPE_IO_DEFAULT: 2219 case DRV_TYPE_IO_1V8_OR_3V0: 2220 case DRV_TYPE_IO_1V8_ONLY: 2221 rmask_bits = RK3288_DRV_BITS_PER_PIN; 2222 break; 2223 default: 2224 dev_err(dev, "unsupported pinctrl drive type: %d\n", drv_type); 2225 return -EINVAL; 2226 } 2227 2228 ret = regmap_read(regmap, reg, &data); 2229 if (ret) 2230 return ret; 2231 2232 data >>= bit; 2233 data &= (1 << rmask_bits) - 1; 2234 2235 return rockchip_perpin_drv_list[drv_type][data]; 2236 } 2237 2238 static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank, 2239 int pin_num, int strength) 2240 { 2241 struct rockchip_pinctrl *info = bank->drvdata; 2242 struct rockchip_pin_ctrl *ctrl = info->ctrl; 2243 struct device *dev = info->dev; 2244 struct regmap *regmap; 2245 int reg, ret, i; 2246 u32 data, rmask, rmask_bits, temp; 2247 u8 bit; 2248 int drv_type = bank->drv[pin_num / 8].drv_type; 2249 2250 dev_dbg(dev, "setting drive of GPIO%d-%d to %d\n", 2251 bank->bank_num, pin_num, strength); 2252 2253 ret = ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); 2254 if (ret) 2255 return ret; 2256 if (ctrl->type == RK3588) { 2257 rmask_bits = RK3588_DRV_BITS_PER_PIN; 2258 ret = strength; 2259 goto config; 2260 } else if (ctrl->type == RK3568) { 2261 rmask_bits = RK3568_DRV_BITS_PER_PIN; 2262 ret = (1 << (strength + 1)) - 1; 2263 goto config; 2264 } 2265 2266 if (ctrl->type == RV1126) { 2267 rmask_bits = RV1126_DRV_BITS_PER_PIN; 2268 ret = strength; 2269 goto config; 2270 } 2271 2272 ret = -EINVAL; 2273 for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) { 2274 if (rockchip_perpin_drv_list[drv_type][i] == strength) { 2275 ret = i; 2276 break; 2277 } else if (rockchip_perpin_drv_list[drv_type][i] < 0) { 2278 ret = rockchip_perpin_drv_list[drv_type][i]; 2279 break; 2280 } 2281 } 2282 2283 if (ret < 0) { 2284 dev_err(dev, "unsupported driver strength %d\n", strength); 2285 return ret; 2286 } 2287 2288 switch (drv_type) { 2289 case DRV_TYPE_IO_1V8_3V0_AUTO: 2290 case DRV_TYPE_IO_3V3_ONLY: 2291 rmask_bits = RK3399_DRV_3BITS_PER_PIN; 2292 switch (bit) { 2293 case 0 ... 12: 2294 /* regular case, nothing to do */ 2295 break; 2296 case 15: 2297 /* 2298 * drive-strength offset is special, as it is spread 2299 * over 2 registers, the bit data[15] contains bit 0 2300 * of the value while temp[1:0] contains bits 2 and 1 2301 */ 2302 data = (ret & 0x1) << 15; 2303 temp = (ret >> 0x1) & 0x3; 2304 2305 rmask = BIT(15) | BIT(31); 2306 data |= BIT(31); 2307 ret = regmap_update_bits(regmap, reg, rmask, data); 2308 if (ret) 2309 return ret; 2310 2311 rmask = 0x3 | (0x3 << 16); 2312 temp |= (0x3 << 16); 2313 reg += 0x4; 2314 ret = regmap_update_bits(regmap, reg, rmask, temp); 2315 2316 return ret; 2317 case 18 ... 21: 2318 /* setting fully enclosed in the second register */ 2319 reg += 4; 2320 bit -= 16; 2321 break; 2322 default: 2323 dev_err(dev, "unsupported bit: %d for pinctrl drive type: %d\n", 2324 bit, drv_type); 2325 return -EINVAL; 2326 } 2327 break; 2328 case DRV_TYPE_IO_DEFAULT: 2329 case DRV_TYPE_IO_1V8_OR_3V0: 2330 case DRV_TYPE_IO_1V8_ONLY: 2331 rmask_bits = RK3288_DRV_BITS_PER_PIN; 2332 break; 2333 default: 2334 dev_err(dev, "unsupported pinctrl drive type: %d\n", drv_type); 2335 return -EINVAL; 2336 } 2337 2338 config: 2339 /* enable the write to the equivalent lower bits */ 2340 data = ((1 << rmask_bits) - 1) << (bit + 16); 2341 rmask = data | (data >> 16); 2342 data |= (ret << bit); 2343 2344 ret = regmap_update_bits(regmap, reg, rmask, data); 2345 2346 return ret; 2347 } 2348 2349 static int rockchip_pull_list[PULL_TYPE_MAX][4] = { 2350 { 2351 PIN_CONFIG_BIAS_DISABLE, 2352 PIN_CONFIG_BIAS_PULL_UP, 2353 PIN_CONFIG_BIAS_PULL_DOWN, 2354 PIN_CONFIG_BIAS_BUS_HOLD 2355 }, 2356 { 2357 PIN_CONFIG_BIAS_DISABLE, 2358 PIN_CONFIG_BIAS_PULL_DOWN, 2359 PIN_CONFIG_BIAS_DISABLE, 2360 PIN_CONFIG_BIAS_PULL_UP 2361 }, 2362 }; 2363 2364 static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num) 2365 { 2366 struct rockchip_pinctrl *info = bank->drvdata; 2367 struct rockchip_pin_ctrl *ctrl = info->ctrl; 2368 struct device *dev = info->dev; 2369 struct regmap *regmap; 2370 int reg, ret, pull_type; 2371 u8 bit; 2372 u32 data; 2373 2374 /* rk3066b does support any pulls */ 2375 if (ctrl->type == RK3066B) 2376 return PIN_CONFIG_BIAS_DISABLE; 2377 2378 ret = ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); 2379 if (ret) 2380 return ret; 2381 2382 ret = regmap_read(regmap, reg, &data); 2383 if (ret) 2384 return ret; 2385 2386 switch (ctrl->type) { 2387 case RK2928: 2388 case RK3128: 2389 return !(data & BIT(bit)) 2390 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT 2391 : PIN_CONFIG_BIAS_DISABLE; 2392 case PX30: 2393 case RV1108: 2394 case RK3188: 2395 case RK3288: 2396 case RK3308: 2397 case RK3368: 2398 case RK3399: 2399 case RK3588: 2400 pull_type = bank->pull_type[pin_num / 8]; 2401 data >>= bit; 2402 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1; 2403 2404 return rockchip_pull_list[pull_type][data]; 2405 default: 2406 dev_err(dev, "unsupported pinctrl type\n"); 2407 return -EINVAL; 2408 }; 2409 } 2410 2411 static int rockchip_set_pull(struct rockchip_pin_bank *bank, 2412 int pin_num, int pull) 2413 { 2414 struct rockchip_pinctrl *info = bank->drvdata; 2415 struct rockchip_pin_ctrl *ctrl = info->ctrl; 2416 struct device *dev = info->dev; 2417 struct regmap *regmap; 2418 int reg, ret, i, pull_type; 2419 u8 bit; 2420 u32 data, rmask; 2421 2422 dev_dbg(dev, "setting pull of GPIO%d-%d to %d\n", bank->bank_num, pin_num, pull); 2423 2424 /* rk3066b does support any pulls */ 2425 if (ctrl->type == RK3066B) 2426 return pull ? -EINVAL : 0; 2427 2428 ret = ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); 2429 if (ret) 2430 return ret; 2431 2432 switch (ctrl->type) { 2433 case RK2928: 2434 case RK3128: 2435 data = BIT(bit + 16); 2436 if (pull == PIN_CONFIG_BIAS_DISABLE) 2437 data |= BIT(bit); 2438 ret = regmap_write(regmap, reg, data); 2439 break; 2440 case PX30: 2441 case RV1108: 2442 case RV1126: 2443 case RK3188: 2444 case RK3288: 2445 case RK3308: 2446 case RK3368: 2447 case RK3399: 2448 case RK3568: 2449 case RK3588: 2450 pull_type = bank->pull_type[pin_num / 8]; 2451 ret = -EINVAL; 2452 for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]); 2453 i++) { 2454 if (rockchip_pull_list[pull_type][i] == pull) { 2455 ret = i; 2456 break; 2457 } 2458 } 2459 /* 2460 * In the TRM, pull-up being 1 for everything except the GPIO0_D0-D6, 2461 * where that pull up value becomes 3. 2462 */ 2463 if (ctrl->type == RK3568 && bank->bank_num == 0 && pin_num >= 27 && pin_num <= 30) { 2464 if (ret == 1) 2465 ret = 3; 2466 } 2467 2468 if (ret < 0) { 2469 dev_err(dev, "unsupported pull setting %d\n", pull); 2470 return ret; 2471 } 2472 2473 /* enable the write to the equivalent lower bits */ 2474 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16); 2475 rmask = data | (data >> 16); 2476 data |= (ret << bit); 2477 2478 ret = regmap_update_bits(regmap, reg, rmask, data); 2479 break; 2480 default: 2481 dev_err(dev, "unsupported pinctrl type\n"); 2482 return -EINVAL; 2483 } 2484 2485 return ret; 2486 } 2487 2488 #define RK3328_SCHMITT_BITS_PER_PIN 1 2489 #define RK3328_SCHMITT_PINS_PER_REG 16 2490 #define RK3328_SCHMITT_BANK_STRIDE 8 2491 #define RK3328_SCHMITT_GRF_OFFSET 0x380 2492 2493 static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 2494 int pin_num, 2495 struct regmap **regmap, 2496 int *reg, u8 *bit) 2497 { 2498 struct rockchip_pinctrl *info = bank->drvdata; 2499 2500 *regmap = info->regmap_base; 2501 *reg = RK3328_SCHMITT_GRF_OFFSET; 2502 2503 *reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE; 2504 *reg += ((pin_num / RK3328_SCHMITT_PINS_PER_REG) * 4); 2505 *bit = pin_num % RK3328_SCHMITT_PINS_PER_REG; 2506 2507 return 0; 2508 } 2509 2510 #define RK3568_SCHMITT_BITS_PER_PIN 2 2511 #define RK3568_SCHMITT_PINS_PER_REG 8 2512 #define RK3568_SCHMITT_BANK_STRIDE 0x10 2513 #define RK3568_SCHMITT_GRF_OFFSET 0xc0 2514 #define RK3568_SCHMITT_PMUGRF_OFFSET 0x30 2515 2516 static int rk3568_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 2517 int pin_num, 2518 struct regmap **regmap, 2519 int *reg, u8 *bit) 2520 { 2521 struct rockchip_pinctrl *info = bank->drvdata; 2522 2523 if (bank->bank_num == 0) { 2524 *regmap = info->regmap_pmu; 2525 *reg = RK3568_SCHMITT_PMUGRF_OFFSET; 2526 } else { 2527 *regmap = info->regmap_base; 2528 *reg = RK3568_SCHMITT_GRF_OFFSET; 2529 *reg += (bank->bank_num - 1) * RK3568_SCHMITT_BANK_STRIDE; 2530 } 2531 2532 *reg += ((pin_num / RK3568_SCHMITT_PINS_PER_REG) * 4); 2533 *bit = pin_num % RK3568_SCHMITT_PINS_PER_REG; 2534 *bit *= RK3568_SCHMITT_BITS_PER_PIN; 2535 2536 return 0; 2537 } 2538 2539 static int rockchip_get_schmitt(struct rockchip_pin_bank *bank, int pin_num) 2540 { 2541 struct rockchip_pinctrl *info = bank->drvdata; 2542 struct rockchip_pin_ctrl *ctrl = info->ctrl; 2543 struct regmap *regmap; 2544 int reg, ret; 2545 u8 bit; 2546 u32 data; 2547 2548 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit); 2549 if (ret) 2550 return ret; 2551 2552 ret = regmap_read(regmap, reg, &data); 2553 if (ret) 2554 return ret; 2555 2556 data >>= bit; 2557 switch (ctrl->type) { 2558 case RK3568: 2559 return data & ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1); 2560 default: 2561 break; 2562 } 2563 2564 return data & 0x1; 2565 } 2566 2567 static int rockchip_set_schmitt(struct rockchip_pin_bank *bank, 2568 int pin_num, int enable) 2569 { 2570 struct rockchip_pinctrl *info = bank->drvdata; 2571 struct rockchip_pin_ctrl *ctrl = info->ctrl; 2572 struct device *dev = info->dev; 2573 struct regmap *regmap; 2574 int reg, ret; 2575 u8 bit; 2576 u32 data, rmask; 2577 2578 dev_dbg(dev, "setting input schmitt of GPIO%d-%d to %d\n", 2579 bank->bank_num, pin_num, enable); 2580 2581 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit); 2582 if (ret) 2583 return ret; 2584 2585 /* enable the write to the equivalent lower bits */ 2586 switch (ctrl->type) { 2587 case RK3568: 2588 data = ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1) << (bit + 16); 2589 rmask = data | (data >> 16); 2590 data |= ((enable ? 0x2 : 0x1) << bit); 2591 break; 2592 default: 2593 data = BIT(bit + 16) | (enable << bit); 2594 rmask = BIT(bit + 16) | BIT(bit); 2595 break; 2596 } 2597 2598 return regmap_update_bits(regmap, reg, rmask, data); 2599 } 2600 2601 /* 2602 * Pinmux_ops handling 2603 */ 2604 2605 static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev) 2606 { 2607 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 2608 2609 return info->nfunctions; 2610 } 2611 2612 static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev, 2613 unsigned selector) 2614 { 2615 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 2616 2617 return info->functions[selector].name; 2618 } 2619 2620 static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev, 2621 unsigned selector, const char * const **groups, 2622 unsigned * const num_groups) 2623 { 2624 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 2625 2626 *groups = info->functions[selector].groups; 2627 *num_groups = info->functions[selector].ngroups; 2628 2629 return 0; 2630 } 2631 2632 static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector, 2633 unsigned group) 2634 { 2635 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 2636 const unsigned int *pins = info->groups[group].pins; 2637 const struct rockchip_pin_config *data = info->groups[group].data; 2638 struct device *dev = info->dev; 2639 struct rockchip_pin_bank *bank; 2640 int cnt, ret = 0; 2641 2642 dev_dbg(dev, "enable function %s group %s\n", 2643 info->functions[selector].name, info->groups[group].name); 2644 2645 /* 2646 * for each pin in the pin group selected, program the corresponding 2647 * pin function number in the config register. 2648 */ 2649 for (cnt = 0; cnt < info->groups[group].npins; cnt++) { 2650 bank = pin_to_bank(info, pins[cnt]); 2651 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 2652 data[cnt].func); 2653 if (ret) 2654 break; 2655 } 2656 2657 if (ret) { 2658 /* revert the already done pin settings */ 2659 for (cnt--; cnt >= 0; cnt--) 2660 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0); 2661 2662 return ret; 2663 } 2664 2665 return 0; 2666 } 2667 2668 static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, 2669 struct pinctrl_gpio_range *range, 2670 unsigned offset, 2671 bool input) 2672 { 2673 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 2674 struct rockchip_pin_bank *bank; 2675 2676 bank = pin_to_bank(info, offset); 2677 return rockchip_set_mux(bank, offset - bank->pin_base, RK_FUNC_GPIO); 2678 } 2679 2680 static const struct pinmux_ops rockchip_pmx_ops = { 2681 .get_functions_count = rockchip_pmx_get_funcs_count, 2682 .get_function_name = rockchip_pmx_get_func_name, 2683 .get_function_groups = rockchip_pmx_get_groups, 2684 .set_mux = rockchip_pmx_set, 2685 .gpio_set_direction = rockchip_pmx_gpio_set_direction, 2686 }; 2687 2688 /* 2689 * Pinconf_ops handling 2690 */ 2691 2692 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl, 2693 enum pin_config_param pull) 2694 { 2695 switch (ctrl->type) { 2696 case RK2928: 2697 case RK3128: 2698 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT || 2699 pull == PIN_CONFIG_BIAS_DISABLE); 2700 case RK3066B: 2701 return pull ? false : true; 2702 case PX30: 2703 case RV1108: 2704 case RV1126: 2705 case RK3188: 2706 case RK3288: 2707 case RK3308: 2708 case RK3368: 2709 case RK3399: 2710 case RK3568: 2711 case RK3588: 2712 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT); 2713 } 2714 2715 return false; 2716 } 2717 2718 static int rockchip_pinconf_defer_pin(struct rockchip_pin_bank *bank, 2719 unsigned int pin, u32 param, u32 arg) 2720 { 2721 struct rockchip_pin_deferred *cfg; 2722 2723 cfg = kzalloc(sizeof(*cfg), GFP_KERNEL); 2724 if (!cfg) 2725 return -ENOMEM; 2726 2727 cfg->pin = pin; 2728 cfg->param = param; 2729 cfg->arg = arg; 2730 2731 list_add_tail(&cfg->head, &bank->deferred_pins); 2732 2733 return 0; 2734 } 2735 2736 /* set the pin config settings for a specified pin */ 2737 static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 2738 unsigned long *configs, unsigned num_configs) 2739 { 2740 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 2741 struct rockchip_pin_bank *bank = pin_to_bank(info, pin); 2742 struct gpio_chip *gpio = &bank->gpio_chip; 2743 enum pin_config_param param; 2744 u32 arg; 2745 int i; 2746 int rc; 2747 2748 for (i = 0; i < num_configs; i++) { 2749 param = pinconf_to_config_param(configs[i]); 2750 arg = pinconf_to_config_argument(configs[i]); 2751 2752 if (param == PIN_CONFIG_OUTPUT || param == PIN_CONFIG_INPUT_ENABLE) { 2753 /* 2754 * Check for gpio driver not being probed yet. 2755 * The lock makes sure that either gpio-probe has completed 2756 * or the gpio driver hasn't probed yet. 2757 */ 2758 mutex_lock(&bank->deferred_lock); 2759 if (!gpio || !gpio->direction_output) { 2760 rc = rockchip_pinconf_defer_pin(bank, pin - bank->pin_base, param, 2761 arg); 2762 mutex_unlock(&bank->deferred_lock); 2763 if (rc) 2764 return rc; 2765 2766 break; 2767 } 2768 mutex_unlock(&bank->deferred_lock); 2769 } 2770 2771 switch (param) { 2772 case PIN_CONFIG_BIAS_DISABLE: 2773 rc = rockchip_set_pull(bank, pin - bank->pin_base, 2774 param); 2775 if (rc) 2776 return rc; 2777 break; 2778 case PIN_CONFIG_BIAS_PULL_UP: 2779 case PIN_CONFIG_BIAS_PULL_DOWN: 2780 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: 2781 case PIN_CONFIG_BIAS_BUS_HOLD: 2782 if (!rockchip_pinconf_pull_valid(info->ctrl, param)) 2783 return -ENOTSUPP; 2784 2785 if (!arg) 2786 return -EINVAL; 2787 2788 rc = rockchip_set_pull(bank, pin - bank->pin_base, 2789 param); 2790 if (rc) 2791 return rc; 2792 break; 2793 case PIN_CONFIG_OUTPUT: 2794 rc = rockchip_set_mux(bank, pin - bank->pin_base, 2795 RK_FUNC_GPIO); 2796 if (rc != RK_FUNC_GPIO) 2797 return -EINVAL; 2798 2799 rc = gpio->direction_output(gpio, pin - bank->pin_base, 2800 arg); 2801 if (rc) 2802 return rc; 2803 break; 2804 case PIN_CONFIG_INPUT_ENABLE: 2805 rc = rockchip_set_mux(bank, pin - bank->pin_base, 2806 RK_FUNC_GPIO); 2807 if (rc != RK_FUNC_GPIO) 2808 return -EINVAL; 2809 2810 rc = gpio->direction_input(gpio, pin - bank->pin_base); 2811 if (rc) 2812 return rc; 2813 break; 2814 case PIN_CONFIG_DRIVE_STRENGTH: 2815 /* rk3288 is the first with per-pin drive-strength */ 2816 if (!info->ctrl->drv_calc_reg) 2817 return -ENOTSUPP; 2818 2819 rc = rockchip_set_drive_perpin(bank, 2820 pin - bank->pin_base, arg); 2821 if (rc < 0) 2822 return rc; 2823 break; 2824 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 2825 if (!info->ctrl->schmitt_calc_reg) 2826 return -ENOTSUPP; 2827 2828 rc = rockchip_set_schmitt(bank, 2829 pin - bank->pin_base, arg); 2830 if (rc < 0) 2831 return rc; 2832 break; 2833 default: 2834 return -ENOTSUPP; 2835 break; 2836 } 2837 } /* for each config */ 2838 2839 return 0; 2840 } 2841 2842 /* get the pin config settings for a specified pin */ 2843 static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, 2844 unsigned long *config) 2845 { 2846 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 2847 struct rockchip_pin_bank *bank = pin_to_bank(info, pin); 2848 struct gpio_chip *gpio = &bank->gpio_chip; 2849 enum pin_config_param param = pinconf_to_config_param(*config); 2850 u16 arg; 2851 int rc; 2852 2853 switch (param) { 2854 case PIN_CONFIG_BIAS_DISABLE: 2855 if (rockchip_get_pull(bank, pin - bank->pin_base) != param) 2856 return -EINVAL; 2857 2858 arg = 0; 2859 break; 2860 case PIN_CONFIG_BIAS_PULL_UP: 2861 case PIN_CONFIG_BIAS_PULL_DOWN: 2862 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: 2863 case PIN_CONFIG_BIAS_BUS_HOLD: 2864 if (!rockchip_pinconf_pull_valid(info->ctrl, param)) 2865 return -ENOTSUPP; 2866 2867 if (rockchip_get_pull(bank, pin - bank->pin_base) != param) 2868 return -EINVAL; 2869 2870 arg = 1; 2871 break; 2872 case PIN_CONFIG_OUTPUT: 2873 rc = rockchip_get_mux(bank, pin - bank->pin_base); 2874 if (rc != RK_FUNC_GPIO) 2875 return -EINVAL; 2876 2877 if (!gpio || !gpio->get) { 2878 arg = 0; 2879 break; 2880 } 2881 2882 rc = gpio->get(gpio, pin - bank->pin_base); 2883 if (rc < 0) 2884 return rc; 2885 2886 arg = rc ? 1 : 0; 2887 break; 2888 case PIN_CONFIG_DRIVE_STRENGTH: 2889 /* rk3288 is the first with per-pin drive-strength */ 2890 if (!info->ctrl->drv_calc_reg) 2891 return -ENOTSUPP; 2892 2893 rc = rockchip_get_drive_perpin(bank, pin - bank->pin_base); 2894 if (rc < 0) 2895 return rc; 2896 2897 arg = rc; 2898 break; 2899 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 2900 if (!info->ctrl->schmitt_calc_reg) 2901 return -ENOTSUPP; 2902 2903 rc = rockchip_get_schmitt(bank, pin - bank->pin_base); 2904 if (rc < 0) 2905 return rc; 2906 2907 arg = rc; 2908 break; 2909 default: 2910 return -ENOTSUPP; 2911 break; 2912 } 2913 2914 *config = pinconf_to_config_packed(param, arg); 2915 2916 return 0; 2917 } 2918 2919 static const struct pinconf_ops rockchip_pinconf_ops = { 2920 .pin_config_get = rockchip_pinconf_get, 2921 .pin_config_set = rockchip_pinconf_set, 2922 .is_generic = true, 2923 }; 2924 2925 static const struct of_device_id rockchip_bank_match[] = { 2926 { .compatible = "rockchip,gpio-bank" }, 2927 { .compatible = "rockchip,rk3188-gpio-bank0" }, 2928 {}, 2929 }; 2930 2931 static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info, 2932 struct device_node *np) 2933 { 2934 struct device_node *child; 2935 2936 for_each_child_of_node(np, child) { 2937 if (of_match_node(rockchip_bank_match, child)) 2938 continue; 2939 2940 info->nfunctions++; 2941 info->ngroups += of_get_child_count(child); 2942 } 2943 } 2944 2945 static int rockchip_pinctrl_parse_groups(struct device_node *np, 2946 struct rockchip_pin_group *grp, 2947 struct rockchip_pinctrl *info, 2948 u32 index) 2949 { 2950 struct device *dev = info->dev; 2951 struct rockchip_pin_bank *bank; 2952 int size; 2953 const __be32 *list; 2954 int num; 2955 int i, j; 2956 int ret; 2957 2958 dev_dbg(dev, "group(%d): %pOFn\n", index, np); 2959 2960 /* Initialise group */ 2961 grp->name = np->name; 2962 2963 /* 2964 * the binding format is rockchip,pins = <bank pin mux CONFIG>, 2965 * do sanity check and calculate pins number 2966 */ 2967 list = of_get_property(np, "rockchip,pins", &size); 2968 /* we do not check return since it's safe node passed down */ 2969 size /= sizeof(*list); 2970 if (!size || size % 4) 2971 return dev_err_probe(dev, -EINVAL, "wrong pins number or pins and configs should be by 4\n"); 2972 2973 grp->npins = size / 4; 2974 2975 grp->pins = devm_kcalloc(dev, grp->npins, sizeof(*grp->pins), GFP_KERNEL); 2976 grp->data = devm_kcalloc(dev, grp->npins, sizeof(*grp->data), GFP_KERNEL); 2977 if (!grp->pins || !grp->data) 2978 return -ENOMEM; 2979 2980 for (i = 0, j = 0; i < size; i += 4, j++) { 2981 const __be32 *phandle; 2982 struct device_node *np_config; 2983 2984 num = be32_to_cpu(*list++); 2985 bank = bank_num_to_bank(info, num); 2986 if (IS_ERR(bank)) 2987 return PTR_ERR(bank); 2988 2989 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++); 2990 grp->data[j].func = be32_to_cpu(*list++); 2991 2992 phandle = list++; 2993 if (!phandle) 2994 return -EINVAL; 2995 2996 np_config = of_find_node_by_phandle(be32_to_cpup(phandle)); 2997 ret = pinconf_generic_parse_dt_config(np_config, NULL, 2998 &grp->data[j].configs, &grp->data[j].nconfigs); 2999 if (ret) 3000 return ret; 3001 } 3002 3003 return 0; 3004 } 3005 3006 static int rockchip_pinctrl_parse_functions(struct device_node *np, 3007 struct rockchip_pinctrl *info, 3008 u32 index) 3009 { 3010 struct device *dev = info->dev; 3011 struct device_node *child; 3012 struct rockchip_pmx_func *func; 3013 struct rockchip_pin_group *grp; 3014 int ret; 3015 static u32 grp_index; 3016 u32 i = 0; 3017 3018 dev_dbg(dev, "parse function(%d): %pOFn\n", index, np); 3019 3020 func = &info->functions[index]; 3021 3022 /* Initialise function */ 3023 func->name = np->name; 3024 func->ngroups = of_get_child_count(np); 3025 if (func->ngroups <= 0) 3026 return 0; 3027 3028 func->groups = devm_kcalloc(dev, func->ngroups, sizeof(*func->groups), GFP_KERNEL); 3029 if (!func->groups) 3030 return -ENOMEM; 3031 3032 for_each_child_of_node(np, child) { 3033 func->groups[i] = child->name; 3034 grp = &info->groups[grp_index++]; 3035 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++); 3036 if (ret) { 3037 of_node_put(child); 3038 return ret; 3039 } 3040 } 3041 3042 return 0; 3043 } 3044 3045 static int rockchip_pinctrl_parse_dt(struct platform_device *pdev, 3046 struct rockchip_pinctrl *info) 3047 { 3048 struct device *dev = &pdev->dev; 3049 struct device_node *np = dev->of_node; 3050 struct device_node *child; 3051 int ret; 3052 int i; 3053 3054 rockchip_pinctrl_child_count(info, np); 3055 3056 dev_dbg(dev, "nfunctions = %d\n", info->nfunctions); 3057 dev_dbg(dev, "ngroups = %d\n", info->ngroups); 3058 3059 info->functions = devm_kcalloc(dev, info->nfunctions, sizeof(*info->functions), GFP_KERNEL); 3060 if (!info->functions) 3061 return -ENOMEM; 3062 3063 info->groups = devm_kcalloc(dev, info->ngroups, sizeof(*info->groups), GFP_KERNEL); 3064 if (!info->groups) 3065 return -ENOMEM; 3066 3067 i = 0; 3068 3069 for_each_child_of_node(np, child) { 3070 if (of_match_node(rockchip_bank_match, child)) 3071 continue; 3072 3073 ret = rockchip_pinctrl_parse_functions(child, info, i++); 3074 if (ret) { 3075 dev_err(dev, "failed to parse function\n"); 3076 of_node_put(child); 3077 return ret; 3078 } 3079 } 3080 3081 return 0; 3082 } 3083 3084 static int rockchip_pinctrl_register(struct platform_device *pdev, 3085 struct rockchip_pinctrl *info) 3086 { 3087 struct pinctrl_desc *ctrldesc = &info->pctl; 3088 struct pinctrl_pin_desc *pindesc, *pdesc; 3089 struct rockchip_pin_bank *pin_bank; 3090 struct device *dev = &pdev->dev; 3091 char **pin_names; 3092 int pin, bank, ret; 3093 int k; 3094 3095 ctrldesc->name = "rockchip-pinctrl"; 3096 ctrldesc->owner = THIS_MODULE; 3097 ctrldesc->pctlops = &rockchip_pctrl_ops; 3098 ctrldesc->pmxops = &rockchip_pmx_ops; 3099 ctrldesc->confops = &rockchip_pinconf_ops; 3100 3101 pindesc = devm_kcalloc(dev, info->ctrl->nr_pins, sizeof(*pindesc), GFP_KERNEL); 3102 if (!pindesc) 3103 return -ENOMEM; 3104 3105 ctrldesc->pins = pindesc; 3106 ctrldesc->npins = info->ctrl->nr_pins; 3107 3108 pdesc = pindesc; 3109 for (bank = 0, k = 0; bank < info->ctrl->nr_banks; bank++) { 3110 pin_bank = &info->ctrl->pin_banks[bank]; 3111 3112 pin_names = devm_kasprintf_strarray(dev, pin_bank->name, pin_bank->nr_pins); 3113 if (IS_ERR(pin_names)) 3114 return PTR_ERR(pin_names); 3115 3116 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) { 3117 pdesc->number = k; 3118 pdesc->name = pin_names[pin]; 3119 pdesc++; 3120 } 3121 3122 INIT_LIST_HEAD(&pin_bank->deferred_pins); 3123 mutex_init(&pin_bank->deferred_lock); 3124 } 3125 3126 ret = rockchip_pinctrl_parse_dt(pdev, info); 3127 if (ret) 3128 return ret; 3129 3130 info->pctl_dev = devm_pinctrl_register(dev, ctrldesc, info); 3131 if (IS_ERR(info->pctl_dev)) 3132 return dev_err_probe(dev, PTR_ERR(info->pctl_dev), "could not register pinctrl driver\n"); 3133 3134 return 0; 3135 } 3136 3137 static const struct of_device_id rockchip_pinctrl_dt_match[]; 3138 3139 /* retrieve the soc specific data */ 3140 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data( 3141 struct rockchip_pinctrl *d, 3142 struct platform_device *pdev) 3143 { 3144 struct device *dev = &pdev->dev; 3145 struct device_node *node = dev->of_node; 3146 const struct of_device_id *match; 3147 struct rockchip_pin_ctrl *ctrl; 3148 struct rockchip_pin_bank *bank; 3149 int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j; 3150 3151 match = of_match_node(rockchip_pinctrl_dt_match, node); 3152 ctrl = (struct rockchip_pin_ctrl *)match->data; 3153 3154 grf_offs = ctrl->grf_mux_offset; 3155 pmu_offs = ctrl->pmu_mux_offset; 3156 drv_pmu_offs = ctrl->pmu_drv_offset; 3157 drv_grf_offs = ctrl->grf_drv_offset; 3158 bank = ctrl->pin_banks; 3159 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 3160 int bank_pins = 0; 3161 3162 raw_spin_lock_init(&bank->slock); 3163 bank->drvdata = d; 3164 bank->pin_base = ctrl->nr_pins; 3165 ctrl->nr_pins += bank->nr_pins; 3166 3167 /* calculate iomux and drv offsets */ 3168 for (j = 0; j < 4; j++) { 3169 struct rockchip_iomux *iom = &bank->iomux[j]; 3170 struct rockchip_drv *drv = &bank->drv[j]; 3171 int inc; 3172 3173 if (bank_pins >= bank->nr_pins) 3174 break; 3175 3176 /* preset iomux offset value, set new start value */ 3177 if (iom->offset >= 0) { 3178 if ((iom->type & IOMUX_SOURCE_PMU) || 3179 (iom->type & IOMUX_L_SOURCE_PMU)) 3180 pmu_offs = iom->offset; 3181 else 3182 grf_offs = iom->offset; 3183 } else { /* set current iomux offset */ 3184 iom->offset = ((iom->type & IOMUX_SOURCE_PMU) || 3185 (iom->type & IOMUX_L_SOURCE_PMU)) ? 3186 pmu_offs : grf_offs; 3187 } 3188 3189 /* preset drv offset value, set new start value */ 3190 if (drv->offset >= 0) { 3191 if (iom->type & IOMUX_SOURCE_PMU) 3192 drv_pmu_offs = drv->offset; 3193 else 3194 drv_grf_offs = drv->offset; 3195 } else { /* set current drv offset */ 3196 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ? 3197 drv_pmu_offs : drv_grf_offs; 3198 } 3199 3200 dev_dbg(dev, "bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n", 3201 i, j, iom->offset, drv->offset); 3202 3203 /* 3204 * Increase offset according to iomux width. 3205 * 4bit iomux'es are spread over two registers. 3206 */ 3207 inc = (iom->type & (IOMUX_WIDTH_4BIT | 3208 IOMUX_WIDTH_3BIT | 3209 IOMUX_WIDTH_2BIT)) ? 8 : 4; 3210 if ((iom->type & IOMUX_SOURCE_PMU) || (iom->type & IOMUX_L_SOURCE_PMU)) 3211 pmu_offs += inc; 3212 else 3213 grf_offs += inc; 3214 3215 /* 3216 * Increase offset according to drv width. 3217 * 3bit drive-strenth'es are spread over two registers. 3218 */ 3219 if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) || 3220 (drv->drv_type == DRV_TYPE_IO_3V3_ONLY)) 3221 inc = 8; 3222 else 3223 inc = 4; 3224 3225 if (iom->type & IOMUX_SOURCE_PMU) 3226 drv_pmu_offs += inc; 3227 else 3228 drv_grf_offs += inc; 3229 3230 bank_pins += 8; 3231 } 3232 3233 /* calculate the per-bank recalced_mask */ 3234 for (j = 0; j < ctrl->niomux_recalced; j++) { 3235 int pin = 0; 3236 3237 if (ctrl->iomux_recalced[j].num == bank->bank_num) { 3238 pin = ctrl->iomux_recalced[j].pin; 3239 bank->recalced_mask |= BIT(pin); 3240 } 3241 } 3242 3243 /* calculate the per-bank route_mask */ 3244 for (j = 0; j < ctrl->niomux_routes; j++) { 3245 int pin = 0; 3246 3247 if (ctrl->iomux_routes[j].bank_num == bank->bank_num) { 3248 pin = ctrl->iomux_routes[j].pin; 3249 bank->route_mask |= BIT(pin); 3250 } 3251 } 3252 } 3253 3254 return ctrl; 3255 } 3256 3257 #define RK3288_GRF_GPIO6C_IOMUX 0x64 3258 #define GPIO6C6_SEL_WRITE_ENABLE BIT(28) 3259 3260 static u32 rk3288_grf_gpio6c_iomux; 3261 3262 static int __maybe_unused rockchip_pinctrl_suspend(struct device *dev) 3263 { 3264 struct rockchip_pinctrl *info = dev_get_drvdata(dev); 3265 int ret = pinctrl_force_sleep(info->pctl_dev); 3266 3267 if (ret) 3268 return ret; 3269 3270 /* 3271 * RK3288 GPIO6_C6 mux would be modified by Maskrom when resume, so save 3272 * the setting here, and restore it at resume. 3273 */ 3274 if (info->ctrl->type == RK3288) { 3275 ret = regmap_read(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX, 3276 &rk3288_grf_gpio6c_iomux); 3277 if (ret) { 3278 pinctrl_force_default(info->pctl_dev); 3279 return ret; 3280 } 3281 } 3282 3283 return 0; 3284 } 3285 3286 static int __maybe_unused rockchip_pinctrl_resume(struct device *dev) 3287 { 3288 struct rockchip_pinctrl *info = dev_get_drvdata(dev); 3289 int ret; 3290 3291 if (info->ctrl->type == RK3288) { 3292 ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX, 3293 rk3288_grf_gpio6c_iomux | 3294 GPIO6C6_SEL_WRITE_ENABLE); 3295 if (ret) 3296 return ret; 3297 } 3298 3299 return pinctrl_force_default(info->pctl_dev); 3300 } 3301 3302 static SIMPLE_DEV_PM_OPS(rockchip_pinctrl_dev_pm_ops, rockchip_pinctrl_suspend, 3303 rockchip_pinctrl_resume); 3304 3305 static int rockchip_pinctrl_probe(struct platform_device *pdev) 3306 { 3307 struct rockchip_pinctrl *info; 3308 struct device *dev = &pdev->dev; 3309 struct device_node *np = dev->of_node, *node; 3310 struct rockchip_pin_ctrl *ctrl; 3311 struct resource *res; 3312 void __iomem *base; 3313 int ret; 3314 3315 if (!dev->of_node) 3316 return dev_err_probe(dev, -ENODEV, "device tree node not found\n"); 3317 3318 info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL); 3319 if (!info) 3320 return -ENOMEM; 3321 3322 info->dev = dev; 3323 3324 ctrl = rockchip_pinctrl_get_soc_data(info, pdev); 3325 if (!ctrl) 3326 return dev_err_probe(dev, -EINVAL, "driver data not available\n"); 3327 info->ctrl = ctrl; 3328 3329 node = of_parse_phandle(np, "rockchip,grf", 0); 3330 if (node) { 3331 info->regmap_base = syscon_node_to_regmap(node); 3332 of_node_put(node); 3333 if (IS_ERR(info->regmap_base)) 3334 return PTR_ERR(info->regmap_base); 3335 } else { 3336 base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 3337 if (IS_ERR(base)) 3338 return PTR_ERR(base); 3339 3340 rockchip_regmap_config.max_register = resource_size(res) - 4; 3341 rockchip_regmap_config.name = "rockchip,pinctrl"; 3342 info->regmap_base = 3343 devm_regmap_init_mmio(dev, base, &rockchip_regmap_config); 3344 3345 /* to check for the old dt-bindings */ 3346 info->reg_size = resource_size(res); 3347 3348 /* Honor the old binding, with pull registers as 2nd resource */ 3349 if (ctrl->type == RK3188 && info->reg_size < 0x200) { 3350 base = devm_platform_get_and_ioremap_resource(pdev, 1, &res); 3351 if (IS_ERR(base)) 3352 return PTR_ERR(base); 3353 3354 rockchip_regmap_config.max_register = resource_size(res) - 4; 3355 rockchip_regmap_config.name = "rockchip,pinctrl-pull"; 3356 info->regmap_pull = 3357 devm_regmap_init_mmio(dev, base, &rockchip_regmap_config); 3358 } 3359 } 3360 3361 /* try to find the optional reference to the pmu syscon */ 3362 node = of_parse_phandle(np, "rockchip,pmu", 0); 3363 if (node) { 3364 info->regmap_pmu = syscon_node_to_regmap(node); 3365 of_node_put(node); 3366 if (IS_ERR(info->regmap_pmu)) 3367 return PTR_ERR(info->regmap_pmu); 3368 } 3369 3370 ret = rockchip_pinctrl_register(pdev, info); 3371 if (ret) 3372 return ret; 3373 3374 platform_set_drvdata(pdev, info); 3375 3376 ret = of_platform_populate(np, NULL, NULL, &pdev->dev); 3377 if (ret) 3378 return dev_err_probe(dev, ret, "failed to register gpio device\n"); 3379 3380 return 0; 3381 } 3382 3383 static int rockchip_pinctrl_remove(struct platform_device *pdev) 3384 { 3385 struct rockchip_pinctrl *info = platform_get_drvdata(pdev); 3386 struct rockchip_pin_bank *bank; 3387 struct rockchip_pin_deferred *cfg; 3388 int i; 3389 3390 of_platform_depopulate(&pdev->dev); 3391 3392 for (i = 0; i < info->ctrl->nr_banks; i++) { 3393 bank = &info->ctrl->pin_banks[i]; 3394 3395 mutex_lock(&bank->deferred_lock); 3396 while (!list_empty(&bank->deferred_pins)) { 3397 cfg = list_first_entry(&bank->deferred_pins, 3398 struct rockchip_pin_deferred, head); 3399 list_del(&cfg->head); 3400 kfree(cfg); 3401 } 3402 mutex_unlock(&bank->deferred_lock); 3403 } 3404 3405 return 0; 3406 } 3407 3408 static struct rockchip_pin_bank px30_pin_banks[] = { 3409 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, 3410 IOMUX_SOURCE_PMU, 3411 IOMUX_SOURCE_PMU, 3412 IOMUX_SOURCE_PMU 3413 ), 3414 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT, 3415 IOMUX_WIDTH_4BIT, 3416 IOMUX_WIDTH_4BIT, 3417 IOMUX_WIDTH_4BIT 3418 ), 3419 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT, 3420 IOMUX_WIDTH_4BIT, 3421 IOMUX_WIDTH_4BIT, 3422 IOMUX_WIDTH_4BIT 3423 ), 3424 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT, 3425 IOMUX_WIDTH_4BIT, 3426 IOMUX_WIDTH_4BIT, 3427 IOMUX_WIDTH_4BIT 3428 ), 3429 }; 3430 3431 static struct rockchip_pin_ctrl px30_pin_ctrl = { 3432 .pin_banks = px30_pin_banks, 3433 .nr_banks = ARRAY_SIZE(px30_pin_banks), 3434 .label = "PX30-GPIO", 3435 .type = PX30, 3436 .grf_mux_offset = 0x0, 3437 .pmu_mux_offset = 0x0, 3438 .iomux_routes = px30_mux_route_data, 3439 .niomux_routes = ARRAY_SIZE(px30_mux_route_data), 3440 .pull_calc_reg = px30_calc_pull_reg_and_bit, 3441 .drv_calc_reg = px30_calc_drv_reg_and_bit, 3442 .schmitt_calc_reg = px30_calc_schmitt_reg_and_bit, 3443 }; 3444 3445 static struct rockchip_pin_bank rv1108_pin_banks[] = { 3446 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, 3447 IOMUX_SOURCE_PMU, 3448 IOMUX_SOURCE_PMU, 3449 IOMUX_SOURCE_PMU), 3450 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0), 3451 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0), 3452 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0), 3453 }; 3454 3455 static struct rockchip_pin_ctrl rv1108_pin_ctrl = { 3456 .pin_banks = rv1108_pin_banks, 3457 .nr_banks = ARRAY_SIZE(rv1108_pin_banks), 3458 .label = "RV1108-GPIO", 3459 .type = RV1108, 3460 .grf_mux_offset = 0x10, 3461 .pmu_mux_offset = 0x0, 3462 .iomux_recalced = rv1108_mux_recalced_data, 3463 .niomux_recalced = ARRAY_SIZE(rv1108_mux_recalced_data), 3464 .pull_calc_reg = rv1108_calc_pull_reg_and_bit, 3465 .drv_calc_reg = rv1108_calc_drv_reg_and_bit, 3466 .schmitt_calc_reg = rv1108_calc_schmitt_reg_and_bit, 3467 }; 3468 3469 static struct rockchip_pin_bank rv1126_pin_banks[] = { 3470 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 3471 IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU, 3472 IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU, 3473 IOMUX_WIDTH_4BIT | IOMUX_L_SOURCE_PMU, 3474 IOMUX_WIDTH_4BIT), 3475 PIN_BANK_IOMUX_FLAGS_OFFSET(1, 32, "gpio1", 3476 IOMUX_WIDTH_4BIT, 3477 IOMUX_WIDTH_4BIT, 3478 IOMUX_WIDTH_4BIT, 3479 IOMUX_WIDTH_4BIT, 3480 0x10010, 0x10018, 0x10020, 0x10028), 3481 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 3482 IOMUX_WIDTH_4BIT, 3483 IOMUX_WIDTH_4BIT, 3484 IOMUX_WIDTH_4BIT, 3485 IOMUX_WIDTH_4BIT), 3486 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 3487 IOMUX_WIDTH_4BIT, 3488 IOMUX_WIDTH_4BIT, 3489 IOMUX_WIDTH_4BIT, 3490 IOMUX_WIDTH_4BIT), 3491 PIN_BANK_IOMUX_FLAGS(4, 2, "gpio4", 3492 IOMUX_WIDTH_4BIT, 0, 0, 0), 3493 }; 3494 3495 static struct rockchip_pin_ctrl rv1126_pin_ctrl = { 3496 .pin_banks = rv1126_pin_banks, 3497 .nr_banks = ARRAY_SIZE(rv1126_pin_banks), 3498 .label = "RV1126-GPIO", 3499 .type = RV1126, 3500 .grf_mux_offset = 0x10004, /* mux offset from GPIO0_D0 */ 3501 .pmu_mux_offset = 0x0, 3502 .iomux_routes = rv1126_mux_route_data, 3503 .niomux_routes = ARRAY_SIZE(rv1126_mux_route_data), 3504 .iomux_recalced = rv1126_mux_recalced_data, 3505 .niomux_recalced = ARRAY_SIZE(rv1126_mux_recalced_data), 3506 .pull_calc_reg = rv1126_calc_pull_reg_and_bit, 3507 .drv_calc_reg = rv1126_calc_drv_reg_and_bit, 3508 .schmitt_calc_reg = rv1126_calc_schmitt_reg_and_bit, 3509 }; 3510 3511 static struct rockchip_pin_bank rk2928_pin_banks[] = { 3512 PIN_BANK(0, 32, "gpio0"), 3513 PIN_BANK(1, 32, "gpio1"), 3514 PIN_BANK(2, 32, "gpio2"), 3515 PIN_BANK(3, 32, "gpio3"), 3516 }; 3517 3518 static struct rockchip_pin_ctrl rk2928_pin_ctrl = { 3519 .pin_banks = rk2928_pin_banks, 3520 .nr_banks = ARRAY_SIZE(rk2928_pin_banks), 3521 .label = "RK2928-GPIO", 3522 .type = RK2928, 3523 .grf_mux_offset = 0xa8, 3524 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 3525 }; 3526 3527 static struct rockchip_pin_bank rk3036_pin_banks[] = { 3528 PIN_BANK(0, 32, "gpio0"), 3529 PIN_BANK(1, 32, "gpio1"), 3530 PIN_BANK(2, 32, "gpio2"), 3531 }; 3532 3533 static struct rockchip_pin_ctrl rk3036_pin_ctrl = { 3534 .pin_banks = rk3036_pin_banks, 3535 .nr_banks = ARRAY_SIZE(rk3036_pin_banks), 3536 .label = "RK3036-GPIO", 3537 .type = RK2928, 3538 .grf_mux_offset = 0xa8, 3539 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 3540 }; 3541 3542 static struct rockchip_pin_bank rk3066a_pin_banks[] = { 3543 PIN_BANK(0, 32, "gpio0"), 3544 PIN_BANK(1, 32, "gpio1"), 3545 PIN_BANK(2, 32, "gpio2"), 3546 PIN_BANK(3, 32, "gpio3"), 3547 PIN_BANK(4, 32, "gpio4"), 3548 PIN_BANK(6, 16, "gpio6"), 3549 }; 3550 3551 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = { 3552 .pin_banks = rk3066a_pin_banks, 3553 .nr_banks = ARRAY_SIZE(rk3066a_pin_banks), 3554 .label = "RK3066a-GPIO", 3555 .type = RK2928, 3556 .grf_mux_offset = 0xa8, 3557 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 3558 }; 3559 3560 static struct rockchip_pin_bank rk3066b_pin_banks[] = { 3561 PIN_BANK(0, 32, "gpio0"), 3562 PIN_BANK(1, 32, "gpio1"), 3563 PIN_BANK(2, 32, "gpio2"), 3564 PIN_BANK(3, 32, "gpio3"), 3565 }; 3566 3567 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = { 3568 .pin_banks = rk3066b_pin_banks, 3569 .nr_banks = ARRAY_SIZE(rk3066b_pin_banks), 3570 .label = "RK3066b-GPIO", 3571 .type = RK3066B, 3572 .grf_mux_offset = 0x60, 3573 }; 3574 3575 static struct rockchip_pin_bank rk3128_pin_banks[] = { 3576 PIN_BANK(0, 32, "gpio0"), 3577 PIN_BANK(1, 32, "gpio1"), 3578 PIN_BANK(2, 32, "gpio2"), 3579 PIN_BANK(3, 32, "gpio3"), 3580 }; 3581 3582 static struct rockchip_pin_ctrl rk3128_pin_ctrl = { 3583 .pin_banks = rk3128_pin_banks, 3584 .nr_banks = ARRAY_SIZE(rk3128_pin_banks), 3585 .label = "RK3128-GPIO", 3586 .type = RK3128, 3587 .grf_mux_offset = 0xa8, 3588 .iomux_recalced = rk3128_mux_recalced_data, 3589 .niomux_recalced = ARRAY_SIZE(rk3128_mux_recalced_data), 3590 .iomux_routes = rk3128_mux_route_data, 3591 .niomux_routes = ARRAY_SIZE(rk3128_mux_route_data), 3592 .pull_calc_reg = rk3128_calc_pull_reg_and_bit, 3593 }; 3594 3595 static struct rockchip_pin_bank rk3188_pin_banks[] = { 3596 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0), 3597 PIN_BANK(1, 32, "gpio1"), 3598 PIN_BANK(2, 32, "gpio2"), 3599 PIN_BANK(3, 32, "gpio3"), 3600 }; 3601 3602 static struct rockchip_pin_ctrl rk3188_pin_ctrl = { 3603 .pin_banks = rk3188_pin_banks, 3604 .nr_banks = ARRAY_SIZE(rk3188_pin_banks), 3605 .label = "RK3188-GPIO", 3606 .type = RK3188, 3607 .grf_mux_offset = 0x60, 3608 .iomux_routes = rk3188_mux_route_data, 3609 .niomux_routes = ARRAY_SIZE(rk3188_mux_route_data), 3610 .pull_calc_reg = rk3188_calc_pull_reg_and_bit, 3611 }; 3612 3613 static struct rockchip_pin_bank rk3228_pin_banks[] = { 3614 PIN_BANK(0, 32, "gpio0"), 3615 PIN_BANK(1, 32, "gpio1"), 3616 PIN_BANK(2, 32, "gpio2"), 3617 PIN_BANK(3, 32, "gpio3"), 3618 }; 3619 3620 static struct rockchip_pin_ctrl rk3228_pin_ctrl = { 3621 .pin_banks = rk3228_pin_banks, 3622 .nr_banks = ARRAY_SIZE(rk3228_pin_banks), 3623 .label = "RK3228-GPIO", 3624 .type = RK3288, 3625 .grf_mux_offset = 0x0, 3626 .iomux_routes = rk3228_mux_route_data, 3627 .niomux_routes = ARRAY_SIZE(rk3228_mux_route_data), 3628 .pull_calc_reg = rk3228_calc_pull_reg_and_bit, 3629 .drv_calc_reg = rk3228_calc_drv_reg_and_bit, 3630 }; 3631 3632 static struct rockchip_pin_bank rk3288_pin_banks[] = { 3633 PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU, 3634 IOMUX_SOURCE_PMU, 3635 IOMUX_SOURCE_PMU, 3636 IOMUX_UNROUTED 3637 ), 3638 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED, 3639 IOMUX_UNROUTED, 3640 IOMUX_UNROUTED, 3641 0 3642 ), 3643 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED), 3644 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT), 3645 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT, 3646 IOMUX_WIDTH_4BIT, 3647 0, 3648 0 3649 ), 3650 PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED, 3651 0, 3652 0, 3653 IOMUX_UNROUTED 3654 ), 3655 PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED), 3656 PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0, 3657 0, 3658 IOMUX_WIDTH_4BIT, 3659 IOMUX_UNROUTED 3660 ), 3661 PIN_BANK(8, 16, "gpio8"), 3662 }; 3663 3664 static struct rockchip_pin_ctrl rk3288_pin_ctrl = { 3665 .pin_banks = rk3288_pin_banks, 3666 .nr_banks = ARRAY_SIZE(rk3288_pin_banks), 3667 .label = "RK3288-GPIO", 3668 .type = RK3288, 3669 .grf_mux_offset = 0x0, 3670 .pmu_mux_offset = 0x84, 3671 .iomux_routes = rk3288_mux_route_data, 3672 .niomux_routes = ARRAY_SIZE(rk3288_mux_route_data), 3673 .pull_calc_reg = rk3288_calc_pull_reg_and_bit, 3674 .drv_calc_reg = rk3288_calc_drv_reg_and_bit, 3675 }; 3676 3677 static struct rockchip_pin_bank rk3308_pin_banks[] = { 3678 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_WIDTH_2BIT, 3679 IOMUX_WIDTH_2BIT, 3680 IOMUX_WIDTH_2BIT, 3681 IOMUX_WIDTH_2BIT), 3682 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_2BIT, 3683 IOMUX_WIDTH_2BIT, 3684 IOMUX_WIDTH_2BIT, 3685 IOMUX_WIDTH_2BIT), 3686 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_2BIT, 3687 IOMUX_WIDTH_2BIT, 3688 IOMUX_WIDTH_2BIT, 3689 IOMUX_WIDTH_2BIT), 3690 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_2BIT, 3691 IOMUX_WIDTH_2BIT, 3692 IOMUX_WIDTH_2BIT, 3693 IOMUX_WIDTH_2BIT), 3694 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_2BIT, 3695 IOMUX_WIDTH_2BIT, 3696 IOMUX_WIDTH_2BIT, 3697 IOMUX_WIDTH_2BIT), 3698 }; 3699 3700 static struct rockchip_pin_ctrl rk3308_pin_ctrl = { 3701 .pin_banks = rk3308_pin_banks, 3702 .nr_banks = ARRAY_SIZE(rk3308_pin_banks), 3703 .label = "RK3308-GPIO", 3704 .type = RK3308, 3705 .grf_mux_offset = 0x0, 3706 .iomux_recalced = rk3308_mux_recalced_data, 3707 .niomux_recalced = ARRAY_SIZE(rk3308_mux_recalced_data), 3708 .iomux_routes = rk3308_mux_route_data, 3709 .niomux_routes = ARRAY_SIZE(rk3308_mux_route_data), 3710 .pull_calc_reg = rk3308_calc_pull_reg_and_bit, 3711 .drv_calc_reg = rk3308_calc_drv_reg_and_bit, 3712 .schmitt_calc_reg = rk3308_calc_schmitt_reg_and_bit, 3713 }; 3714 3715 static struct rockchip_pin_bank rk3328_pin_banks[] = { 3716 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0), 3717 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0), 3718 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 3719 IOMUX_WIDTH_3BIT, 3720 IOMUX_WIDTH_3BIT, 3721 0), 3722 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 3723 IOMUX_WIDTH_3BIT, 3724 IOMUX_WIDTH_3BIT, 3725 0, 3726 0), 3727 }; 3728 3729 static struct rockchip_pin_ctrl rk3328_pin_ctrl = { 3730 .pin_banks = rk3328_pin_banks, 3731 .nr_banks = ARRAY_SIZE(rk3328_pin_banks), 3732 .label = "RK3328-GPIO", 3733 .type = RK3288, 3734 .grf_mux_offset = 0x0, 3735 .iomux_recalced = rk3328_mux_recalced_data, 3736 .niomux_recalced = ARRAY_SIZE(rk3328_mux_recalced_data), 3737 .iomux_routes = rk3328_mux_route_data, 3738 .niomux_routes = ARRAY_SIZE(rk3328_mux_route_data), 3739 .pull_calc_reg = rk3228_calc_pull_reg_and_bit, 3740 .drv_calc_reg = rk3228_calc_drv_reg_and_bit, 3741 .schmitt_calc_reg = rk3328_calc_schmitt_reg_and_bit, 3742 }; 3743 3744 static struct rockchip_pin_bank rk3368_pin_banks[] = { 3745 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, 3746 IOMUX_SOURCE_PMU, 3747 IOMUX_SOURCE_PMU, 3748 IOMUX_SOURCE_PMU 3749 ), 3750 PIN_BANK(1, 32, "gpio1"), 3751 PIN_BANK(2, 32, "gpio2"), 3752 PIN_BANK(3, 32, "gpio3"), 3753 }; 3754 3755 static struct rockchip_pin_ctrl rk3368_pin_ctrl = { 3756 .pin_banks = rk3368_pin_banks, 3757 .nr_banks = ARRAY_SIZE(rk3368_pin_banks), 3758 .label = "RK3368-GPIO", 3759 .type = RK3368, 3760 .grf_mux_offset = 0x0, 3761 .pmu_mux_offset = 0x0, 3762 .pull_calc_reg = rk3368_calc_pull_reg_and_bit, 3763 .drv_calc_reg = rk3368_calc_drv_reg_and_bit, 3764 }; 3765 3766 static struct rockchip_pin_bank rk3399_pin_banks[] = { 3767 PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0", 3768 IOMUX_SOURCE_PMU, 3769 IOMUX_SOURCE_PMU, 3770 IOMUX_SOURCE_PMU, 3771 IOMUX_SOURCE_PMU, 3772 DRV_TYPE_IO_1V8_ONLY, 3773 DRV_TYPE_IO_1V8_ONLY, 3774 DRV_TYPE_IO_DEFAULT, 3775 DRV_TYPE_IO_DEFAULT, 3776 0x80, 3777 0x88, 3778 -1, 3779 -1, 3780 PULL_TYPE_IO_1V8_ONLY, 3781 PULL_TYPE_IO_1V8_ONLY, 3782 PULL_TYPE_IO_DEFAULT, 3783 PULL_TYPE_IO_DEFAULT 3784 ), 3785 PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU, 3786 IOMUX_SOURCE_PMU, 3787 IOMUX_SOURCE_PMU, 3788 IOMUX_SOURCE_PMU, 3789 DRV_TYPE_IO_1V8_OR_3V0, 3790 DRV_TYPE_IO_1V8_OR_3V0, 3791 DRV_TYPE_IO_1V8_OR_3V0, 3792 DRV_TYPE_IO_1V8_OR_3V0, 3793 0xa0, 3794 0xa8, 3795 0xb0, 3796 0xb8 3797 ), 3798 PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0, 3799 DRV_TYPE_IO_1V8_OR_3V0, 3800 DRV_TYPE_IO_1V8_ONLY, 3801 DRV_TYPE_IO_1V8_ONLY, 3802 PULL_TYPE_IO_DEFAULT, 3803 PULL_TYPE_IO_DEFAULT, 3804 PULL_TYPE_IO_1V8_ONLY, 3805 PULL_TYPE_IO_1V8_ONLY 3806 ), 3807 PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY, 3808 DRV_TYPE_IO_3V3_ONLY, 3809 DRV_TYPE_IO_3V3_ONLY, 3810 DRV_TYPE_IO_1V8_OR_3V0 3811 ), 3812 PIN_BANK_DRV_FLAGS(4, 32, "gpio4", DRV_TYPE_IO_1V8_OR_3V0, 3813 DRV_TYPE_IO_1V8_3V0_AUTO, 3814 DRV_TYPE_IO_1V8_OR_3V0, 3815 DRV_TYPE_IO_1V8_OR_3V0 3816 ), 3817 }; 3818 3819 static struct rockchip_pin_ctrl rk3399_pin_ctrl = { 3820 .pin_banks = rk3399_pin_banks, 3821 .nr_banks = ARRAY_SIZE(rk3399_pin_banks), 3822 .label = "RK3399-GPIO", 3823 .type = RK3399, 3824 .grf_mux_offset = 0xe000, 3825 .pmu_mux_offset = 0x0, 3826 .grf_drv_offset = 0xe100, 3827 .pmu_drv_offset = 0x80, 3828 .iomux_routes = rk3399_mux_route_data, 3829 .niomux_routes = ARRAY_SIZE(rk3399_mux_route_data), 3830 .pull_calc_reg = rk3399_calc_pull_reg_and_bit, 3831 .drv_calc_reg = rk3399_calc_drv_reg_and_bit, 3832 }; 3833 3834 static struct rockchip_pin_bank rk3568_pin_banks[] = { 3835 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT, 3836 IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT, 3837 IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT, 3838 IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT), 3839 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT, 3840 IOMUX_WIDTH_4BIT, 3841 IOMUX_WIDTH_4BIT, 3842 IOMUX_WIDTH_4BIT), 3843 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT, 3844 IOMUX_WIDTH_4BIT, 3845 IOMUX_WIDTH_4BIT, 3846 IOMUX_WIDTH_4BIT), 3847 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT, 3848 IOMUX_WIDTH_4BIT, 3849 IOMUX_WIDTH_4BIT, 3850 IOMUX_WIDTH_4BIT), 3851 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT, 3852 IOMUX_WIDTH_4BIT, 3853 IOMUX_WIDTH_4BIT, 3854 IOMUX_WIDTH_4BIT), 3855 }; 3856 3857 static struct rockchip_pin_ctrl rk3568_pin_ctrl = { 3858 .pin_banks = rk3568_pin_banks, 3859 .nr_banks = ARRAY_SIZE(rk3568_pin_banks), 3860 .label = "RK3568-GPIO", 3861 .type = RK3568, 3862 .grf_mux_offset = 0x0, 3863 .pmu_mux_offset = 0x0, 3864 .grf_drv_offset = 0x0200, 3865 .pmu_drv_offset = 0x0070, 3866 .iomux_routes = rk3568_mux_route_data, 3867 .niomux_routes = ARRAY_SIZE(rk3568_mux_route_data), 3868 .pull_calc_reg = rk3568_calc_pull_reg_and_bit, 3869 .drv_calc_reg = rk3568_calc_drv_reg_and_bit, 3870 .schmitt_calc_reg = rk3568_calc_schmitt_reg_and_bit, 3871 }; 3872 3873 static struct rockchip_pin_bank rk3588_pin_banks[] = { 3874 RK3588_PIN_BANK_FLAGS(0, 32, "gpio0", 3875 IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY), 3876 RK3588_PIN_BANK_FLAGS(1, 32, "gpio1", 3877 IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY), 3878 RK3588_PIN_BANK_FLAGS(2, 32, "gpio2", 3879 IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY), 3880 RK3588_PIN_BANK_FLAGS(3, 32, "gpio3", 3881 IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY), 3882 RK3588_PIN_BANK_FLAGS(4, 32, "gpio4", 3883 IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY), 3884 }; 3885 3886 static struct rockchip_pin_ctrl rk3588_pin_ctrl = { 3887 .pin_banks = rk3588_pin_banks, 3888 .nr_banks = ARRAY_SIZE(rk3588_pin_banks), 3889 .label = "RK3588-GPIO", 3890 .type = RK3588, 3891 .pull_calc_reg = rk3588_calc_pull_reg_and_bit, 3892 .drv_calc_reg = rk3588_calc_drv_reg_and_bit, 3893 .schmitt_calc_reg = rk3588_calc_schmitt_reg_and_bit, 3894 }; 3895 3896 static const struct of_device_id rockchip_pinctrl_dt_match[] = { 3897 { .compatible = "rockchip,px30-pinctrl", 3898 .data = &px30_pin_ctrl }, 3899 { .compatible = "rockchip,rv1108-pinctrl", 3900 .data = &rv1108_pin_ctrl }, 3901 { .compatible = "rockchip,rv1126-pinctrl", 3902 .data = &rv1126_pin_ctrl }, 3903 { .compatible = "rockchip,rk2928-pinctrl", 3904 .data = &rk2928_pin_ctrl }, 3905 { .compatible = "rockchip,rk3036-pinctrl", 3906 .data = &rk3036_pin_ctrl }, 3907 { .compatible = "rockchip,rk3066a-pinctrl", 3908 .data = &rk3066a_pin_ctrl }, 3909 { .compatible = "rockchip,rk3066b-pinctrl", 3910 .data = &rk3066b_pin_ctrl }, 3911 { .compatible = "rockchip,rk3128-pinctrl", 3912 .data = (void *)&rk3128_pin_ctrl }, 3913 { .compatible = "rockchip,rk3188-pinctrl", 3914 .data = &rk3188_pin_ctrl }, 3915 { .compatible = "rockchip,rk3228-pinctrl", 3916 .data = &rk3228_pin_ctrl }, 3917 { .compatible = "rockchip,rk3288-pinctrl", 3918 .data = &rk3288_pin_ctrl }, 3919 { .compatible = "rockchip,rk3308-pinctrl", 3920 .data = &rk3308_pin_ctrl }, 3921 { .compatible = "rockchip,rk3328-pinctrl", 3922 .data = &rk3328_pin_ctrl }, 3923 { .compatible = "rockchip,rk3368-pinctrl", 3924 .data = &rk3368_pin_ctrl }, 3925 { .compatible = "rockchip,rk3399-pinctrl", 3926 .data = &rk3399_pin_ctrl }, 3927 { .compatible = "rockchip,rk3568-pinctrl", 3928 .data = &rk3568_pin_ctrl }, 3929 { .compatible = "rockchip,rk3588-pinctrl", 3930 .data = &rk3588_pin_ctrl }, 3931 {}, 3932 }; 3933 3934 static struct platform_driver rockchip_pinctrl_driver = { 3935 .probe = rockchip_pinctrl_probe, 3936 .remove = rockchip_pinctrl_remove, 3937 .driver = { 3938 .name = "rockchip-pinctrl", 3939 .pm = &rockchip_pinctrl_dev_pm_ops, 3940 .of_match_table = rockchip_pinctrl_dt_match, 3941 }, 3942 }; 3943 3944 static int __init rockchip_pinctrl_drv_register(void) 3945 { 3946 return platform_driver_register(&rockchip_pinctrl_driver); 3947 } 3948 postcore_initcall(rockchip_pinctrl_drv_register); 3949 3950 static void __exit rockchip_pinctrl_drv_unregister(void) 3951 { 3952 platform_driver_unregister(&rockchip_pinctrl_driver); 3953 } 3954 module_exit(rockchip_pinctrl_drv_unregister); 3955 3956 MODULE_DESCRIPTION("ROCKCHIP Pin Controller Driver"); 3957 MODULE_LICENSE("GPL"); 3958 MODULE_ALIAS("platform:pinctrl-rockchip"); 3959 MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match); 3960