1 /* 2 * Pinctrl driver for Rockchip SoCs 3 * 4 * Copyright (c) 2013 MundoReader S.L. 5 * Author: Heiko Stuebner <heiko@sntech.de> 6 * 7 * With some ideas taken from pinctrl-samsung: 8 * Copyright (c) 2012 Samsung Electronics Co., Ltd. 9 * http://www.samsung.com 10 * Copyright (c) 2012 Linaro Ltd 11 * http://www.linaro.org 12 * 13 * and pinctrl-at91: 14 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> 15 * 16 * This program is free software; you can redistribute it and/or modify 17 * it under the terms of the GNU General Public License version 2 as published 18 * by the Free Software Foundation. 19 * 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 */ 25 26 #include <linux/init.h> 27 #include <linux/platform_device.h> 28 #include <linux/io.h> 29 #include <linux/bitops.h> 30 #include <linux/gpio.h> 31 #include <linux/of_address.h> 32 #include <linux/of_irq.h> 33 #include <linux/pinctrl/machine.h> 34 #include <linux/pinctrl/pinconf.h> 35 #include <linux/pinctrl/pinctrl.h> 36 #include <linux/pinctrl/pinmux.h> 37 #include <linux/pinctrl/pinconf-generic.h> 38 #include <linux/irqchip/chained_irq.h> 39 #include <linux/clk.h> 40 #include <linux/regmap.h> 41 #include <linux/mfd/syscon.h> 42 #include <dt-bindings/pinctrl/rockchip.h> 43 44 #include "core.h" 45 #include "pinconf.h" 46 47 /* GPIO control registers */ 48 #define GPIO_SWPORT_DR 0x00 49 #define GPIO_SWPORT_DDR 0x04 50 #define GPIO_INTEN 0x30 51 #define GPIO_INTMASK 0x34 52 #define GPIO_INTTYPE_LEVEL 0x38 53 #define GPIO_INT_POLARITY 0x3c 54 #define GPIO_INT_STATUS 0x40 55 #define GPIO_INT_RAWSTATUS 0x44 56 #define GPIO_DEBOUNCE 0x48 57 #define GPIO_PORTS_EOI 0x4c 58 #define GPIO_EXT_PORT 0x50 59 #define GPIO_LS_SYNC 0x60 60 61 enum rockchip_pinctrl_type { 62 RV1108, 63 RK2928, 64 RK3066B, 65 RK3128, 66 RK3188, 67 RK3288, 68 RK3368, 69 RK3399, 70 }; 71 72 /** 73 * Encode variants of iomux registers into a type variable 74 */ 75 #define IOMUX_GPIO_ONLY BIT(0) 76 #define IOMUX_WIDTH_4BIT BIT(1) 77 #define IOMUX_SOURCE_PMU BIT(2) 78 #define IOMUX_UNROUTED BIT(3) 79 #define IOMUX_WIDTH_3BIT BIT(4) 80 81 /** 82 * @type: iomux variant using IOMUX_* constants 83 * @offset: if initialized to -1 it will be autocalculated, by specifying 84 * an initial offset value the relevant source offset can be reset 85 * to a new value for autocalculating the following iomux registers. 86 */ 87 struct rockchip_iomux { 88 int type; 89 int offset; 90 }; 91 92 /** 93 * enum type index corresponding to rockchip_perpin_drv_list arrays index. 94 */ 95 enum rockchip_pin_drv_type { 96 DRV_TYPE_IO_DEFAULT = 0, 97 DRV_TYPE_IO_1V8_OR_3V0, 98 DRV_TYPE_IO_1V8_ONLY, 99 DRV_TYPE_IO_1V8_3V0_AUTO, 100 DRV_TYPE_IO_3V3_ONLY, 101 DRV_TYPE_MAX 102 }; 103 104 /** 105 * enum type index corresponding to rockchip_pull_list arrays index. 106 */ 107 enum rockchip_pin_pull_type { 108 PULL_TYPE_IO_DEFAULT = 0, 109 PULL_TYPE_IO_1V8_ONLY, 110 PULL_TYPE_MAX 111 }; 112 113 /** 114 * @drv_type: drive strength variant using rockchip_perpin_drv_type 115 * @offset: if initialized to -1 it will be autocalculated, by specifying 116 * an initial offset value the relevant source offset can be reset 117 * to a new value for autocalculating the following drive strength 118 * registers. if used chips own cal_drv func instead to calculate 119 * registers offset, the variant could be ignored. 120 */ 121 struct rockchip_drv { 122 enum rockchip_pin_drv_type drv_type; 123 int offset; 124 }; 125 126 /** 127 * @reg_base: register base of the gpio bank 128 * @reg_pull: optional separate register for additional pull settings 129 * @clk: clock of the gpio bank 130 * @irq: interrupt of the gpio bank 131 * @saved_masks: Saved content of GPIO_INTEN at suspend time. 132 * @pin_base: first pin number 133 * @nr_pins: number of pins in this bank 134 * @name: name of the bank 135 * @bank_num: number of the bank, to account for holes 136 * @iomux: array describing the 4 iomux sources of the bank 137 * @drv: array describing the 4 drive strength sources of the bank 138 * @pull_type: array describing the 4 pull type sources of the bank 139 * @valid: are all necessary informations present 140 * @of_node: dt node of this bank 141 * @drvdata: common pinctrl basedata 142 * @domain: irqdomain of the gpio bank 143 * @gpio_chip: gpiolib chip 144 * @grange: gpio range 145 * @slock: spinlock for the gpio bank 146 * @route_mask: bits describing the routing pins of per bank 147 */ 148 struct rockchip_pin_bank { 149 void __iomem *reg_base; 150 struct regmap *regmap_pull; 151 struct clk *clk; 152 int irq; 153 u32 saved_masks; 154 u32 pin_base; 155 u8 nr_pins; 156 char *name; 157 u8 bank_num; 158 struct rockchip_iomux iomux[4]; 159 struct rockchip_drv drv[4]; 160 enum rockchip_pin_pull_type pull_type[4]; 161 bool valid; 162 struct device_node *of_node; 163 struct rockchip_pinctrl *drvdata; 164 struct irq_domain *domain; 165 struct gpio_chip gpio_chip; 166 struct pinctrl_gpio_range grange; 167 raw_spinlock_t slock; 168 u32 toggle_edge_mode; 169 u32 recalced_mask; 170 u32 route_mask; 171 }; 172 173 #define PIN_BANK(id, pins, label) \ 174 { \ 175 .bank_num = id, \ 176 .nr_pins = pins, \ 177 .name = label, \ 178 .iomux = { \ 179 { .offset = -1 }, \ 180 { .offset = -1 }, \ 181 { .offset = -1 }, \ 182 { .offset = -1 }, \ 183 }, \ 184 } 185 186 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \ 187 { \ 188 .bank_num = id, \ 189 .nr_pins = pins, \ 190 .name = label, \ 191 .iomux = { \ 192 { .type = iom0, .offset = -1 }, \ 193 { .type = iom1, .offset = -1 }, \ 194 { .type = iom2, .offset = -1 }, \ 195 { .type = iom3, .offset = -1 }, \ 196 }, \ 197 } 198 199 #define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \ 200 { \ 201 .bank_num = id, \ 202 .nr_pins = pins, \ 203 .name = label, \ 204 .iomux = { \ 205 { .offset = -1 }, \ 206 { .offset = -1 }, \ 207 { .offset = -1 }, \ 208 { .offset = -1 }, \ 209 }, \ 210 .drv = { \ 211 { .drv_type = type0, .offset = -1 }, \ 212 { .drv_type = type1, .offset = -1 }, \ 213 { .drv_type = type2, .offset = -1 }, \ 214 { .drv_type = type3, .offset = -1 }, \ 215 }, \ 216 } 217 218 #define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1, \ 219 drv2, drv3, pull0, pull1, \ 220 pull2, pull3) \ 221 { \ 222 .bank_num = id, \ 223 .nr_pins = pins, \ 224 .name = label, \ 225 .iomux = { \ 226 { .offset = -1 }, \ 227 { .offset = -1 }, \ 228 { .offset = -1 }, \ 229 { .offset = -1 }, \ 230 }, \ 231 .drv = { \ 232 { .drv_type = drv0, .offset = -1 }, \ 233 { .drv_type = drv1, .offset = -1 }, \ 234 { .drv_type = drv2, .offset = -1 }, \ 235 { .drv_type = drv3, .offset = -1 }, \ 236 }, \ 237 .pull_type[0] = pull0, \ 238 .pull_type[1] = pull1, \ 239 .pull_type[2] = pull2, \ 240 .pull_type[3] = pull3, \ 241 } 242 243 #define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1, \ 244 iom2, iom3, drv0, drv1, drv2, \ 245 drv3, offset0, offset1, \ 246 offset2, offset3) \ 247 { \ 248 .bank_num = id, \ 249 .nr_pins = pins, \ 250 .name = label, \ 251 .iomux = { \ 252 { .type = iom0, .offset = -1 }, \ 253 { .type = iom1, .offset = -1 }, \ 254 { .type = iom2, .offset = -1 }, \ 255 { .type = iom3, .offset = -1 }, \ 256 }, \ 257 .drv = { \ 258 { .drv_type = drv0, .offset = offset0 }, \ 259 { .drv_type = drv1, .offset = offset1 }, \ 260 { .drv_type = drv2, .offset = offset2 }, \ 261 { .drv_type = drv3, .offset = offset3 }, \ 262 }, \ 263 } 264 265 #define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins, \ 266 label, iom0, iom1, iom2, \ 267 iom3, drv0, drv1, drv2, \ 268 drv3, offset0, offset1, \ 269 offset2, offset3, pull0, \ 270 pull1, pull2, pull3) \ 271 { \ 272 .bank_num = id, \ 273 .nr_pins = pins, \ 274 .name = label, \ 275 .iomux = { \ 276 { .type = iom0, .offset = -1 }, \ 277 { .type = iom1, .offset = -1 }, \ 278 { .type = iom2, .offset = -1 }, \ 279 { .type = iom3, .offset = -1 }, \ 280 }, \ 281 .drv = { \ 282 { .drv_type = drv0, .offset = offset0 }, \ 283 { .drv_type = drv1, .offset = offset1 }, \ 284 { .drv_type = drv2, .offset = offset2 }, \ 285 { .drv_type = drv3, .offset = offset3 }, \ 286 }, \ 287 .pull_type[0] = pull0, \ 288 .pull_type[1] = pull1, \ 289 .pull_type[2] = pull2, \ 290 .pull_type[3] = pull3, \ 291 } 292 293 /** 294 * struct rockchip_mux_recalced_data: represent a pin iomux data. 295 * @num: bank number. 296 * @pin: pin number. 297 * @bit: index at register. 298 * @reg: register offset. 299 * @mask: mask bit 300 */ 301 struct rockchip_mux_recalced_data { 302 u8 num; 303 u8 pin; 304 u32 reg; 305 u8 bit; 306 u8 mask; 307 }; 308 309 /** 310 * struct rockchip_mux_recalced_data: represent a pin iomux data. 311 * @bank_num: bank number. 312 * @pin: index at register or used to calc index. 313 * @func: the min pin. 314 * @route_offset: the max pin. 315 * @route_val: the register offset. 316 */ 317 struct rockchip_mux_route_data { 318 u8 bank_num; 319 u8 pin; 320 u8 func; 321 u32 route_offset; 322 u32 route_val; 323 }; 324 325 /** 326 */ 327 struct rockchip_pin_ctrl { 328 struct rockchip_pin_bank *pin_banks; 329 u32 nr_banks; 330 u32 nr_pins; 331 char *label; 332 enum rockchip_pinctrl_type type; 333 int grf_mux_offset; 334 int pmu_mux_offset; 335 int grf_drv_offset; 336 int pmu_drv_offset; 337 struct rockchip_mux_recalced_data *iomux_recalced; 338 u32 niomux_recalced; 339 struct rockchip_mux_route_data *iomux_routes; 340 u32 niomux_routes; 341 342 void (*pull_calc_reg)(struct rockchip_pin_bank *bank, 343 int pin_num, struct regmap **regmap, 344 int *reg, u8 *bit); 345 void (*drv_calc_reg)(struct rockchip_pin_bank *bank, 346 int pin_num, struct regmap **regmap, 347 int *reg, u8 *bit); 348 int (*schmitt_calc_reg)(struct rockchip_pin_bank *bank, 349 int pin_num, struct regmap **regmap, 350 int *reg, u8 *bit); 351 }; 352 353 struct rockchip_pin_config { 354 unsigned int func; 355 unsigned long *configs; 356 unsigned int nconfigs; 357 }; 358 359 /** 360 * struct rockchip_pin_group: represent group of pins of a pinmux function. 361 * @name: name of the pin group, used to lookup the group. 362 * @pins: the pins included in this group. 363 * @npins: number of pins included in this group. 364 * @func: the mux function number to be programmed when selected. 365 * @configs: the config values to be set for each pin 366 * @nconfigs: number of configs for each pin 367 */ 368 struct rockchip_pin_group { 369 const char *name; 370 unsigned int npins; 371 unsigned int *pins; 372 struct rockchip_pin_config *data; 373 }; 374 375 /** 376 * struct rockchip_pmx_func: represent a pin function. 377 * @name: name of the pin function, used to lookup the function. 378 * @groups: one or more names of pin groups that provide this function. 379 * @num_groups: number of groups included in @groups. 380 */ 381 struct rockchip_pmx_func { 382 const char *name; 383 const char **groups; 384 u8 ngroups; 385 }; 386 387 struct rockchip_pinctrl { 388 struct regmap *regmap_base; 389 int reg_size; 390 struct regmap *regmap_pull; 391 struct regmap *regmap_pmu; 392 struct device *dev; 393 struct rockchip_pin_ctrl *ctrl; 394 struct pinctrl_desc pctl; 395 struct pinctrl_dev *pctl_dev; 396 struct rockchip_pin_group *groups; 397 unsigned int ngroups; 398 struct rockchip_pmx_func *functions; 399 unsigned int nfunctions; 400 }; 401 402 static struct regmap_config rockchip_regmap_config = { 403 .reg_bits = 32, 404 .val_bits = 32, 405 .reg_stride = 4, 406 }; 407 408 static inline const struct rockchip_pin_group *pinctrl_name_to_group( 409 const struct rockchip_pinctrl *info, 410 const char *name) 411 { 412 int i; 413 414 for (i = 0; i < info->ngroups; i++) { 415 if (!strcmp(info->groups[i].name, name)) 416 return &info->groups[i]; 417 } 418 419 return NULL; 420 } 421 422 /* 423 * given a pin number that is local to a pin controller, find out the pin bank 424 * and the register base of the pin bank. 425 */ 426 static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info, 427 unsigned pin) 428 { 429 struct rockchip_pin_bank *b = info->ctrl->pin_banks; 430 431 while (pin >= (b->pin_base + b->nr_pins)) 432 b++; 433 434 return b; 435 } 436 437 static struct rockchip_pin_bank *bank_num_to_bank( 438 struct rockchip_pinctrl *info, 439 unsigned num) 440 { 441 struct rockchip_pin_bank *b = info->ctrl->pin_banks; 442 int i; 443 444 for (i = 0; i < info->ctrl->nr_banks; i++, b++) { 445 if (b->bank_num == num) 446 return b; 447 } 448 449 return ERR_PTR(-EINVAL); 450 } 451 452 /* 453 * Pinctrl_ops handling 454 */ 455 456 static int rockchip_get_groups_count(struct pinctrl_dev *pctldev) 457 { 458 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 459 460 return info->ngroups; 461 } 462 463 static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev, 464 unsigned selector) 465 { 466 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 467 468 return info->groups[selector].name; 469 } 470 471 static int rockchip_get_group_pins(struct pinctrl_dev *pctldev, 472 unsigned selector, const unsigned **pins, 473 unsigned *npins) 474 { 475 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 476 477 if (selector >= info->ngroups) 478 return -EINVAL; 479 480 *pins = info->groups[selector].pins; 481 *npins = info->groups[selector].npins; 482 483 return 0; 484 } 485 486 static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev, 487 struct device_node *np, 488 struct pinctrl_map **map, unsigned *num_maps) 489 { 490 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 491 const struct rockchip_pin_group *grp; 492 struct pinctrl_map *new_map; 493 struct device_node *parent; 494 int map_num = 1; 495 int i; 496 497 /* 498 * first find the group of this node and check if we need to create 499 * config maps for pins 500 */ 501 grp = pinctrl_name_to_group(info, np->name); 502 if (!grp) { 503 dev_err(info->dev, "unable to find group for node %s\n", 504 np->name); 505 return -EINVAL; 506 } 507 508 map_num += grp->npins; 509 new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num, 510 GFP_KERNEL); 511 if (!new_map) 512 return -ENOMEM; 513 514 *map = new_map; 515 *num_maps = map_num; 516 517 /* create mux map */ 518 parent = of_get_parent(np); 519 if (!parent) { 520 devm_kfree(pctldev->dev, new_map); 521 return -EINVAL; 522 } 523 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP; 524 new_map[0].data.mux.function = parent->name; 525 new_map[0].data.mux.group = np->name; 526 of_node_put(parent); 527 528 /* create config map */ 529 new_map++; 530 for (i = 0; i < grp->npins; i++) { 531 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN; 532 new_map[i].data.configs.group_or_pin = 533 pin_get_name(pctldev, grp->pins[i]); 534 new_map[i].data.configs.configs = grp->data[i].configs; 535 new_map[i].data.configs.num_configs = grp->data[i].nconfigs; 536 } 537 538 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n", 539 (*map)->data.mux.function, (*map)->data.mux.group, map_num); 540 541 return 0; 542 } 543 544 static void rockchip_dt_free_map(struct pinctrl_dev *pctldev, 545 struct pinctrl_map *map, unsigned num_maps) 546 { 547 } 548 549 static const struct pinctrl_ops rockchip_pctrl_ops = { 550 .get_groups_count = rockchip_get_groups_count, 551 .get_group_name = rockchip_get_group_name, 552 .get_group_pins = rockchip_get_group_pins, 553 .dt_node_to_map = rockchip_dt_node_to_map, 554 .dt_free_map = rockchip_dt_free_map, 555 }; 556 557 /* 558 * Hardware access 559 */ 560 561 static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = { 562 { 563 .num = 1, 564 .pin = 0, 565 .reg = 0x418, 566 .bit = 0, 567 .mask = 0x3 568 }, { 569 .num = 1, 570 .pin = 1, 571 .reg = 0x418, 572 .bit = 2, 573 .mask = 0x3 574 }, { 575 .num = 1, 576 .pin = 2, 577 .reg = 0x418, 578 .bit = 4, 579 .mask = 0x3 580 }, { 581 .num = 1, 582 .pin = 3, 583 .reg = 0x418, 584 .bit = 6, 585 .mask = 0x3 586 }, { 587 .num = 1, 588 .pin = 4, 589 .reg = 0x418, 590 .bit = 8, 591 .mask = 0x3 592 }, { 593 .num = 1, 594 .pin = 5, 595 .reg = 0x418, 596 .bit = 10, 597 .mask = 0x3 598 }, { 599 .num = 1, 600 .pin = 6, 601 .reg = 0x418, 602 .bit = 12, 603 .mask = 0x3 604 }, { 605 .num = 1, 606 .pin = 7, 607 .reg = 0x418, 608 .bit = 14, 609 .mask = 0x3 610 }, { 611 .num = 1, 612 .pin = 8, 613 .reg = 0x41c, 614 .bit = 0, 615 .mask = 0x3 616 }, { 617 .num = 1, 618 .pin = 9, 619 .reg = 0x41c, 620 .bit = 2, 621 .mask = 0x3 622 }, 623 }; 624 625 static struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = { 626 { 627 .num = 2, 628 .pin = 20, 629 .reg = 0xe8, 630 .bit = 0, 631 .mask = 0x7 632 }, { 633 .num = 2, 634 .pin = 21, 635 .reg = 0xe8, 636 .bit = 4, 637 .mask = 0x7 638 }, { 639 .num = 2, 640 .pin = 22, 641 .reg = 0xe8, 642 .bit = 8, 643 .mask = 0x7 644 }, { 645 .num = 2, 646 .pin = 23, 647 .reg = 0xe8, 648 .bit = 12, 649 .mask = 0x7 650 }, { 651 .num = 2, 652 .pin = 24, 653 .reg = 0xd4, 654 .bit = 12, 655 .mask = 0x7 656 }, 657 }; 658 659 static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = { 660 { 661 .num = 2, 662 .pin = 12, 663 .reg = 0x24, 664 .bit = 8, 665 .mask = 0x3 666 }, { 667 .num = 2, 668 .pin = 15, 669 .reg = 0x28, 670 .bit = 0, 671 .mask = 0x7 672 }, { 673 .num = 2, 674 .pin = 23, 675 .reg = 0x30, 676 .bit = 14, 677 .mask = 0x3 678 }, 679 }; 680 681 static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin, 682 int *reg, u8 *bit, int *mask) 683 { 684 struct rockchip_pinctrl *info = bank->drvdata; 685 struct rockchip_pin_ctrl *ctrl = info->ctrl; 686 struct rockchip_mux_recalced_data *data; 687 int i; 688 689 for (i = 0; i < ctrl->niomux_recalced; i++) { 690 data = &ctrl->iomux_recalced[i]; 691 if (data->num == bank->bank_num && 692 data->pin == pin) 693 break; 694 } 695 696 if (i >= ctrl->niomux_recalced) 697 return; 698 699 *reg = data->reg; 700 *mask = data->mask; 701 *bit = data->bit; 702 } 703 704 static struct rockchip_mux_route_data rk3128_mux_route_data[] = { 705 { 706 /* spi-0 */ 707 .bank_num = 1, 708 .pin = 10, 709 .func = 1, 710 .route_offset = 0x144, 711 .route_val = BIT(16 + 3) | BIT(16 + 4), 712 }, { 713 /* spi-1 */ 714 .bank_num = 1, 715 .pin = 27, 716 .func = 3, 717 .route_offset = 0x144, 718 .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(3), 719 }, { 720 /* spi-2 */ 721 .bank_num = 0, 722 .pin = 13, 723 .func = 2, 724 .route_offset = 0x144, 725 .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(4), 726 }, { 727 /* i2s-0 */ 728 .bank_num = 1, 729 .pin = 5, 730 .func = 1, 731 .route_offset = 0x144, 732 .route_val = BIT(16 + 5), 733 }, { 734 /* i2s-1 */ 735 .bank_num = 0, 736 .pin = 14, 737 .func = 1, 738 .route_offset = 0x144, 739 .route_val = BIT(16 + 5) | BIT(5), 740 }, { 741 /* emmc-0 */ 742 .bank_num = 1, 743 .pin = 22, 744 .func = 2, 745 .route_offset = 0x144, 746 .route_val = BIT(16 + 6), 747 }, { 748 /* emmc-1 */ 749 .bank_num = 2, 750 .pin = 4, 751 .func = 2, 752 .route_offset = 0x144, 753 .route_val = BIT(16 + 6) | BIT(6), 754 }, 755 }; 756 757 static struct rockchip_mux_route_data rk3228_mux_route_data[] = { 758 { 759 /* pwm0-0 */ 760 .bank_num = 0, 761 .pin = 26, 762 .func = 1, 763 .route_offset = 0x50, 764 .route_val = BIT(16), 765 }, { 766 /* pwm0-1 */ 767 .bank_num = 3, 768 .pin = 21, 769 .func = 1, 770 .route_offset = 0x50, 771 .route_val = BIT(16) | BIT(0), 772 }, { 773 /* pwm1-0 */ 774 .bank_num = 0, 775 .pin = 27, 776 .func = 1, 777 .route_offset = 0x50, 778 .route_val = BIT(16 + 1), 779 }, { 780 /* pwm1-1 */ 781 .bank_num = 0, 782 .pin = 30, 783 .func = 2, 784 .route_offset = 0x50, 785 .route_val = BIT(16 + 1) | BIT(1), 786 }, { 787 /* pwm2-0 */ 788 .bank_num = 0, 789 .pin = 28, 790 .func = 1, 791 .route_offset = 0x50, 792 .route_val = BIT(16 + 2), 793 }, { 794 /* pwm2-1 */ 795 .bank_num = 1, 796 .pin = 12, 797 .func = 2, 798 .route_offset = 0x50, 799 .route_val = BIT(16 + 2) | BIT(2), 800 }, { 801 /* pwm3-0 */ 802 .bank_num = 3, 803 .pin = 26, 804 .func = 1, 805 .route_offset = 0x50, 806 .route_val = BIT(16 + 3), 807 }, { 808 /* pwm3-1 */ 809 .bank_num = 1, 810 .pin = 11, 811 .func = 2, 812 .route_offset = 0x50, 813 .route_val = BIT(16 + 3) | BIT(3), 814 }, { 815 /* sdio-0_d0 */ 816 .bank_num = 1, 817 .pin = 1, 818 .func = 1, 819 .route_offset = 0x50, 820 .route_val = BIT(16 + 4), 821 }, { 822 /* sdio-1_d0 */ 823 .bank_num = 3, 824 .pin = 2, 825 .func = 1, 826 .route_offset = 0x50, 827 .route_val = BIT(16 + 4) | BIT(4), 828 }, { 829 /* spi-0_rx */ 830 .bank_num = 0, 831 .pin = 13, 832 .func = 2, 833 .route_offset = 0x50, 834 .route_val = BIT(16 + 5), 835 }, { 836 /* spi-1_rx */ 837 .bank_num = 2, 838 .pin = 0, 839 .func = 2, 840 .route_offset = 0x50, 841 .route_val = BIT(16 + 5) | BIT(5), 842 }, { 843 /* emmc-0_cmd */ 844 .bank_num = 1, 845 .pin = 22, 846 .func = 2, 847 .route_offset = 0x50, 848 .route_val = BIT(16 + 7), 849 }, { 850 /* emmc-1_cmd */ 851 .bank_num = 2, 852 .pin = 4, 853 .func = 2, 854 .route_offset = 0x50, 855 .route_val = BIT(16 + 7) | BIT(7), 856 }, { 857 /* uart2-0_rx */ 858 .bank_num = 1, 859 .pin = 19, 860 .func = 2, 861 .route_offset = 0x50, 862 .route_val = BIT(16 + 8), 863 }, { 864 /* uart2-1_rx */ 865 .bank_num = 1, 866 .pin = 10, 867 .func = 2, 868 .route_offset = 0x50, 869 .route_val = BIT(16 + 8) | BIT(8), 870 }, { 871 /* uart1-0_rx */ 872 .bank_num = 1, 873 .pin = 10, 874 .func = 1, 875 .route_offset = 0x50, 876 .route_val = BIT(16 + 11), 877 }, { 878 /* uart1-1_rx */ 879 .bank_num = 3, 880 .pin = 13, 881 .func = 1, 882 .route_offset = 0x50, 883 .route_val = BIT(16 + 11) | BIT(11), 884 }, 885 }; 886 887 static struct rockchip_mux_route_data rk3288_mux_route_data[] = { 888 { 889 /* edphdmi_cecinoutt1 */ 890 .bank_num = 7, 891 .pin = 16, 892 .func = 2, 893 .route_offset = 0x264, 894 .route_val = BIT(16 + 12) | BIT(12), 895 }, { 896 /* edphdmi_cecinout */ 897 .bank_num = 7, 898 .pin = 23, 899 .func = 4, 900 .route_offset = 0x264, 901 .route_val = BIT(16 + 12), 902 }, 903 }; 904 905 static struct rockchip_mux_route_data rk3328_mux_route_data[] = { 906 { 907 /* uart2dbg_rxm0 */ 908 .bank_num = 1, 909 .pin = 1, 910 .func = 2, 911 .route_offset = 0x50, 912 .route_val = BIT(16) | BIT(16 + 1), 913 }, { 914 /* uart2dbg_rxm1 */ 915 .bank_num = 2, 916 .pin = 1, 917 .func = 1, 918 .route_offset = 0x50, 919 .route_val = BIT(16) | BIT(16 + 1) | BIT(0), 920 }, { 921 /* gmac-m1_rxd0 */ 922 .bank_num = 1, 923 .pin = 11, 924 .func = 2, 925 .route_offset = 0x50, 926 .route_val = BIT(16 + 2) | BIT(2), 927 }, { 928 /* gmac-m1-optimized_rxd3 */ 929 .bank_num = 1, 930 .pin = 14, 931 .func = 2, 932 .route_offset = 0x50, 933 .route_val = BIT(16 + 10) | BIT(10), 934 }, { 935 /* pdm_sdi0m0 */ 936 .bank_num = 2, 937 .pin = 19, 938 .func = 2, 939 .route_offset = 0x50, 940 .route_val = BIT(16 + 3), 941 }, { 942 /* pdm_sdi0m1 */ 943 .bank_num = 1, 944 .pin = 23, 945 .func = 3, 946 .route_offset = 0x50, 947 .route_val = BIT(16 + 3) | BIT(3), 948 }, { 949 /* spi_rxdm2 */ 950 .bank_num = 3, 951 .pin = 2, 952 .func = 4, 953 .route_offset = 0x50, 954 .route_val = BIT(16 + 4) | BIT(16 + 5) | BIT(5), 955 }, { 956 /* i2s2_sdim0 */ 957 .bank_num = 1, 958 .pin = 24, 959 .func = 1, 960 .route_offset = 0x50, 961 .route_val = BIT(16 + 6), 962 }, { 963 /* i2s2_sdim1 */ 964 .bank_num = 3, 965 .pin = 2, 966 .func = 6, 967 .route_offset = 0x50, 968 .route_val = BIT(16 + 6) | BIT(6), 969 }, { 970 /* card_iom1 */ 971 .bank_num = 2, 972 .pin = 22, 973 .func = 3, 974 .route_offset = 0x50, 975 .route_val = BIT(16 + 7) | BIT(7), 976 }, { 977 /* tsp_d5m1 */ 978 .bank_num = 2, 979 .pin = 16, 980 .func = 3, 981 .route_offset = 0x50, 982 .route_val = BIT(16 + 8) | BIT(8), 983 }, { 984 /* cif_data5m1 */ 985 .bank_num = 2, 986 .pin = 16, 987 .func = 4, 988 .route_offset = 0x50, 989 .route_val = BIT(16 + 9) | BIT(9), 990 }, 991 }; 992 993 static struct rockchip_mux_route_data rk3399_mux_route_data[] = { 994 { 995 /* uart2dbga_rx */ 996 .bank_num = 4, 997 .pin = 8, 998 .func = 2, 999 .route_offset = 0xe21c, 1000 .route_val = BIT(16 + 10) | BIT(16 + 11), 1001 }, { 1002 /* uart2dbgb_rx */ 1003 .bank_num = 4, 1004 .pin = 16, 1005 .func = 2, 1006 .route_offset = 0xe21c, 1007 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10), 1008 }, { 1009 /* uart2dbgc_rx */ 1010 .bank_num = 4, 1011 .pin = 19, 1012 .func = 1, 1013 .route_offset = 0xe21c, 1014 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11), 1015 }, { 1016 /* pcie_clkreqn */ 1017 .bank_num = 2, 1018 .pin = 26, 1019 .func = 2, 1020 .route_offset = 0xe21c, 1021 .route_val = BIT(16 + 14), 1022 }, { 1023 /* pcie_clkreqnb */ 1024 .bank_num = 4, 1025 .pin = 24, 1026 .func = 1, 1027 .route_offset = 0xe21c, 1028 .route_val = BIT(16 + 14) | BIT(14), 1029 }, 1030 }; 1031 1032 static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin, 1033 int mux, u32 *reg, u32 *value) 1034 { 1035 struct rockchip_pinctrl *info = bank->drvdata; 1036 struct rockchip_pin_ctrl *ctrl = info->ctrl; 1037 struct rockchip_mux_route_data *data; 1038 int i; 1039 1040 for (i = 0; i < ctrl->niomux_routes; i++) { 1041 data = &ctrl->iomux_routes[i]; 1042 if ((data->bank_num == bank->bank_num) && 1043 (data->pin == pin) && (data->func == mux)) 1044 break; 1045 } 1046 1047 if (i >= ctrl->niomux_routes) 1048 return false; 1049 1050 *reg = data->route_offset; 1051 *value = data->route_val; 1052 1053 return true; 1054 } 1055 1056 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) 1057 { 1058 struct rockchip_pinctrl *info = bank->drvdata; 1059 int iomux_num = (pin / 8); 1060 struct regmap *regmap; 1061 unsigned int val; 1062 int reg, ret, mask, mux_type; 1063 u8 bit; 1064 1065 if (iomux_num > 3) 1066 return -EINVAL; 1067 1068 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { 1069 dev_err(info->dev, "pin %d is unrouted\n", pin); 1070 return -EINVAL; 1071 } 1072 1073 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) 1074 return RK_FUNC_GPIO; 1075 1076 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) 1077 ? info->regmap_pmu : info->regmap_base; 1078 1079 /* get basic quadrupel of mux registers and the correct reg inside */ 1080 mux_type = bank->iomux[iomux_num].type; 1081 reg = bank->iomux[iomux_num].offset; 1082 if (mux_type & IOMUX_WIDTH_4BIT) { 1083 if ((pin % 8) >= 4) 1084 reg += 0x4; 1085 bit = (pin % 4) * 4; 1086 mask = 0xf; 1087 } else if (mux_type & IOMUX_WIDTH_3BIT) { 1088 if ((pin % 8) >= 5) 1089 reg += 0x4; 1090 bit = (pin % 8 % 5) * 3; 1091 mask = 0x7; 1092 } else { 1093 bit = (pin % 8) * 2; 1094 mask = 0x3; 1095 } 1096 1097 if (bank->recalced_mask & BIT(pin)) 1098 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); 1099 1100 ret = regmap_read(regmap, reg, &val); 1101 if (ret) 1102 return ret; 1103 1104 return ((val >> bit) & mask); 1105 } 1106 1107 static int rockchip_verify_mux(struct rockchip_pin_bank *bank, 1108 int pin, int mux) 1109 { 1110 struct rockchip_pinctrl *info = bank->drvdata; 1111 int iomux_num = (pin / 8); 1112 1113 if (iomux_num > 3) 1114 return -EINVAL; 1115 1116 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { 1117 dev_err(info->dev, "pin %d is unrouted\n", pin); 1118 return -EINVAL; 1119 } 1120 1121 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) { 1122 if (mux != RK_FUNC_GPIO) { 1123 dev_err(info->dev, 1124 "pin %d only supports a gpio mux\n", pin); 1125 return -ENOTSUPP; 1126 } 1127 } 1128 1129 return 0; 1130 } 1131 1132 /* 1133 * Set a new mux function for a pin. 1134 * 1135 * The register is divided into the upper and lower 16 bit. When changing 1136 * a value, the previous register value is not read and changed. Instead 1137 * it seems the changed bits are marked in the upper 16 bit, while the 1138 * changed value gets set in the same offset in the lower 16 bit. 1139 * All pin settings seem to be 2 bit wide in both the upper and lower 1140 * parts. 1141 * @bank: pin bank to change 1142 * @pin: pin to change 1143 * @mux: new mux function to set 1144 */ 1145 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) 1146 { 1147 struct rockchip_pinctrl *info = bank->drvdata; 1148 int iomux_num = (pin / 8); 1149 struct regmap *regmap; 1150 int reg, ret, mask, mux_type; 1151 u8 bit; 1152 u32 data, rmask, route_reg, route_val; 1153 1154 ret = rockchip_verify_mux(bank, pin, mux); 1155 if (ret < 0) 1156 return ret; 1157 1158 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) 1159 return 0; 1160 1161 dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n", 1162 bank->bank_num, pin, mux); 1163 1164 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) 1165 ? info->regmap_pmu : info->regmap_base; 1166 1167 /* get basic quadrupel of mux registers and the correct reg inside */ 1168 mux_type = bank->iomux[iomux_num].type; 1169 reg = bank->iomux[iomux_num].offset; 1170 if (mux_type & IOMUX_WIDTH_4BIT) { 1171 if ((pin % 8) >= 4) 1172 reg += 0x4; 1173 bit = (pin % 4) * 4; 1174 mask = 0xf; 1175 } else if (mux_type & IOMUX_WIDTH_3BIT) { 1176 if ((pin % 8) >= 5) 1177 reg += 0x4; 1178 bit = (pin % 8 % 5) * 3; 1179 mask = 0x7; 1180 } else { 1181 bit = (pin % 8) * 2; 1182 mask = 0x3; 1183 } 1184 1185 if (bank->recalced_mask & BIT(pin)) 1186 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); 1187 1188 if (bank->route_mask & BIT(pin)) { 1189 if (rockchip_get_mux_route(bank, pin, mux, &route_reg, 1190 &route_val)) { 1191 ret = regmap_write(regmap, route_reg, route_val); 1192 if (ret) 1193 return ret; 1194 } 1195 } 1196 1197 data = (mask << (bit + 16)); 1198 rmask = data | (data >> 16); 1199 data |= (mux & mask) << bit; 1200 ret = regmap_update_bits(regmap, reg, rmask, data); 1201 1202 return ret; 1203 } 1204 1205 #define RV1108_PULL_PMU_OFFSET 0x10 1206 #define RV1108_PULL_OFFSET 0x110 1207 #define RV1108_PULL_PINS_PER_REG 8 1208 #define RV1108_PULL_BITS_PER_PIN 2 1209 #define RV1108_PULL_BANK_STRIDE 16 1210 1211 static void rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1212 int pin_num, struct regmap **regmap, 1213 int *reg, u8 *bit) 1214 { 1215 struct rockchip_pinctrl *info = bank->drvdata; 1216 1217 /* The first 24 pins of the first bank are located in PMU */ 1218 if (bank->bank_num == 0) { 1219 *regmap = info->regmap_pmu; 1220 *reg = RV1108_PULL_PMU_OFFSET; 1221 } else { 1222 *reg = RV1108_PULL_OFFSET; 1223 *regmap = info->regmap_base; 1224 /* correct the offset, as we're starting with the 2nd bank */ 1225 *reg -= 0x10; 1226 *reg += bank->bank_num * RV1108_PULL_BANK_STRIDE; 1227 } 1228 1229 *reg += ((pin_num / RV1108_PULL_PINS_PER_REG) * 4); 1230 *bit = (pin_num % RV1108_PULL_PINS_PER_REG); 1231 *bit *= RV1108_PULL_BITS_PER_PIN; 1232 } 1233 1234 #define RV1108_DRV_PMU_OFFSET 0x20 1235 #define RV1108_DRV_GRF_OFFSET 0x210 1236 #define RV1108_DRV_BITS_PER_PIN 2 1237 #define RV1108_DRV_PINS_PER_REG 8 1238 #define RV1108_DRV_BANK_STRIDE 16 1239 1240 static void rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1241 int pin_num, struct regmap **regmap, 1242 int *reg, u8 *bit) 1243 { 1244 struct rockchip_pinctrl *info = bank->drvdata; 1245 1246 /* The first 24 pins of the first bank are located in PMU */ 1247 if (bank->bank_num == 0) { 1248 *regmap = info->regmap_pmu; 1249 *reg = RV1108_DRV_PMU_OFFSET; 1250 } else { 1251 *regmap = info->regmap_base; 1252 *reg = RV1108_DRV_GRF_OFFSET; 1253 1254 /* correct the offset, as we're starting with the 2nd bank */ 1255 *reg -= 0x10; 1256 *reg += bank->bank_num * RV1108_DRV_BANK_STRIDE; 1257 } 1258 1259 *reg += ((pin_num / RV1108_DRV_PINS_PER_REG) * 4); 1260 *bit = pin_num % RV1108_DRV_PINS_PER_REG; 1261 *bit *= RV1108_DRV_BITS_PER_PIN; 1262 } 1263 1264 #define RV1108_SCHMITT_PMU_OFFSET 0x30 1265 #define RV1108_SCHMITT_GRF_OFFSET 0x388 1266 #define RV1108_SCHMITT_BANK_STRIDE 8 1267 #define RV1108_SCHMITT_PINS_PER_GRF_REG 16 1268 #define RV1108_SCHMITT_PINS_PER_PMU_REG 8 1269 1270 static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1271 int pin_num, 1272 struct regmap **regmap, 1273 int *reg, u8 *bit) 1274 { 1275 struct rockchip_pinctrl *info = bank->drvdata; 1276 int pins_per_reg; 1277 1278 if (bank->bank_num == 0) { 1279 *regmap = info->regmap_pmu; 1280 *reg = RV1108_SCHMITT_PMU_OFFSET; 1281 pins_per_reg = RV1108_SCHMITT_PINS_PER_PMU_REG; 1282 } else { 1283 *regmap = info->regmap_base; 1284 *reg = RV1108_SCHMITT_GRF_OFFSET; 1285 pins_per_reg = RV1108_SCHMITT_PINS_PER_GRF_REG; 1286 *reg += (bank->bank_num - 1) * RV1108_SCHMITT_BANK_STRIDE; 1287 } 1288 *reg += ((pin_num / pins_per_reg) * 4); 1289 *bit = pin_num % pins_per_reg; 1290 1291 return 0; 1292 } 1293 1294 #define RK2928_PULL_OFFSET 0x118 1295 #define RK2928_PULL_PINS_PER_REG 16 1296 #define RK2928_PULL_BANK_STRIDE 8 1297 1298 static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1299 int pin_num, struct regmap **regmap, 1300 int *reg, u8 *bit) 1301 { 1302 struct rockchip_pinctrl *info = bank->drvdata; 1303 1304 *regmap = info->regmap_base; 1305 *reg = RK2928_PULL_OFFSET; 1306 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; 1307 *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4; 1308 1309 *bit = pin_num % RK2928_PULL_PINS_PER_REG; 1310 }; 1311 1312 #define RK3128_PULL_OFFSET 0x118 1313 1314 static void rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1315 int pin_num, struct regmap **regmap, 1316 int *reg, u8 *bit) 1317 { 1318 struct rockchip_pinctrl *info = bank->drvdata; 1319 1320 *regmap = info->regmap_base; 1321 *reg = RK3128_PULL_OFFSET; 1322 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; 1323 *reg += ((pin_num / RK2928_PULL_PINS_PER_REG) * 4); 1324 1325 *bit = pin_num % RK2928_PULL_PINS_PER_REG; 1326 } 1327 1328 #define RK3188_PULL_OFFSET 0x164 1329 #define RK3188_PULL_BITS_PER_PIN 2 1330 #define RK3188_PULL_PINS_PER_REG 8 1331 #define RK3188_PULL_BANK_STRIDE 16 1332 #define RK3188_PULL_PMU_OFFSET 0x64 1333 1334 static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1335 int pin_num, struct regmap **regmap, 1336 int *reg, u8 *bit) 1337 { 1338 struct rockchip_pinctrl *info = bank->drvdata; 1339 1340 /* The first 12 pins of the first bank are located elsewhere */ 1341 if (bank->bank_num == 0 && pin_num < 12) { 1342 *regmap = info->regmap_pmu ? info->regmap_pmu 1343 : bank->regmap_pull; 1344 *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0; 1345 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1346 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 1347 *bit *= RK3188_PULL_BITS_PER_PIN; 1348 } else { 1349 *regmap = info->regmap_pull ? info->regmap_pull 1350 : info->regmap_base; 1351 *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET; 1352 1353 /* correct the offset, as it is the 2nd pull register */ 1354 *reg -= 4; 1355 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1356 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1357 1358 /* 1359 * The bits in these registers have an inverse ordering 1360 * with the lowest pin being in bits 15:14 and the highest 1361 * pin in bits 1:0 1362 */ 1363 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG); 1364 *bit *= RK3188_PULL_BITS_PER_PIN; 1365 } 1366 } 1367 1368 #define RK3288_PULL_OFFSET 0x140 1369 static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1370 int pin_num, struct regmap **regmap, 1371 int *reg, u8 *bit) 1372 { 1373 struct rockchip_pinctrl *info = bank->drvdata; 1374 1375 /* The first 24 pins of the first bank are located in PMU */ 1376 if (bank->bank_num == 0) { 1377 *regmap = info->regmap_pmu; 1378 *reg = RK3188_PULL_PMU_OFFSET; 1379 1380 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1381 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 1382 *bit *= RK3188_PULL_BITS_PER_PIN; 1383 } else { 1384 *regmap = info->regmap_base; 1385 *reg = RK3288_PULL_OFFSET; 1386 1387 /* correct the offset, as we're starting with the 2nd bank */ 1388 *reg -= 0x10; 1389 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1390 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1391 1392 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1393 *bit *= RK3188_PULL_BITS_PER_PIN; 1394 } 1395 } 1396 1397 #define RK3288_DRV_PMU_OFFSET 0x70 1398 #define RK3288_DRV_GRF_OFFSET 0x1c0 1399 #define RK3288_DRV_BITS_PER_PIN 2 1400 #define RK3288_DRV_PINS_PER_REG 8 1401 #define RK3288_DRV_BANK_STRIDE 16 1402 1403 static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1404 int pin_num, struct regmap **regmap, 1405 int *reg, u8 *bit) 1406 { 1407 struct rockchip_pinctrl *info = bank->drvdata; 1408 1409 /* The first 24 pins of the first bank are located in PMU */ 1410 if (bank->bank_num == 0) { 1411 *regmap = info->regmap_pmu; 1412 *reg = RK3288_DRV_PMU_OFFSET; 1413 1414 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1415 *bit = pin_num % RK3288_DRV_PINS_PER_REG; 1416 *bit *= RK3288_DRV_BITS_PER_PIN; 1417 } else { 1418 *regmap = info->regmap_base; 1419 *reg = RK3288_DRV_GRF_OFFSET; 1420 1421 /* correct the offset, as we're starting with the 2nd bank */ 1422 *reg -= 0x10; 1423 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 1424 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1425 1426 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 1427 *bit *= RK3288_DRV_BITS_PER_PIN; 1428 } 1429 } 1430 1431 #define RK3228_PULL_OFFSET 0x100 1432 1433 static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1434 int pin_num, struct regmap **regmap, 1435 int *reg, u8 *bit) 1436 { 1437 struct rockchip_pinctrl *info = bank->drvdata; 1438 1439 *regmap = info->regmap_base; 1440 *reg = RK3228_PULL_OFFSET; 1441 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1442 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1443 1444 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1445 *bit *= RK3188_PULL_BITS_PER_PIN; 1446 } 1447 1448 #define RK3228_DRV_GRF_OFFSET 0x200 1449 1450 static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1451 int pin_num, struct regmap **regmap, 1452 int *reg, u8 *bit) 1453 { 1454 struct rockchip_pinctrl *info = bank->drvdata; 1455 1456 *regmap = info->regmap_base; 1457 *reg = RK3228_DRV_GRF_OFFSET; 1458 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 1459 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1460 1461 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 1462 *bit *= RK3288_DRV_BITS_PER_PIN; 1463 } 1464 1465 #define RK3368_PULL_GRF_OFFSET 0x100 1466 #define RK3368_PULL_PMU_OFFSET 0x10 1467 1468 static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1469 int pin_num, struct regmap **regmap, 1470 int *reg, u8 *bit) 1471 { 1472 struct rockchip_pinctrl *info = bank->drvdata; 1473 1474 /* The first 32 pins of the first bank are located in PMU */ 1475 if (bank->bank_num == 0) { 1476 *regmap = info->regmap_pmu; 1477 *reg = RK3368_PULL_PMU_OFFSET; 1478 1479 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1480 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 1481 *bit *= RK3188_PULL_BITS_PER_PIN; 1482 } else { 1483 *regmap = info->regmap_base; 1484 *reg = RK3368_PULL_GRF_OFFSET; 1485 1486 /* correct the offset, as we're starting with the 2nd bank */ 1487 *reg -= 0x10; 1488 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1489 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1490 1491 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1492 *bit *= RK3188_PULL_BITS_PER_PIN; 1493 } 1494 } 1495 1496 #define RK3368_DRV_PMU_OFFSET 0x20 1497 #define RK3368_DRV_GRF_OFFSET 0x200 1498 1499 static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1500 int pin_num, struct regmap **regmap, 1501 int *reg, u8 *bit) 1502 { 1503 struct rockchip_pinctrl *info = bank->drvdata; 1504 1505 /* The first 32 pins of the first bank are located in PMU */ 1506 if (bank->bank_num == 0) { 1507 *regmap = info->regmap_pmu; 1508 *reg = RK3368_DRV_PMU_OFFSET; 1509 1510 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1511 *bit = pin_num % RK3288_DRV_PINS_PER_REG; 1512 *bit *= RK3288_DRV_BITS_PER_PIN; 1513 } else { 1514 *regmap = info->regmap_base; 1515 *reg = RK3368_DRV_GRF_OFFSET; 1516 1517 /* correct the offset, as we're starting with the 2nd bank */ 1518 *reg -= 0x10; 1519 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 1520 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1521 1522 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 1523 *bit *= RK3288_DRV_BITS_PER_PIN; 1524 } 1525 } 1526 1527 #define RK3399_PULL_GRF_OFFSET 0xe040 1528 #define RK3399_PULL_PMU_OFFSET 0x40 1529 #define RK3399_DRV_3BITS_PER_PIN 3 1530 1531 static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1532 int pin_num, struct regmap **regmap, 1533 int *reg, u8 *bit) 1534 { 1535 struct rockchip_pinctrl *info = bank->drvdata; 1536 1537 /* The bank0:16 and bank1:32 pins are located in PMU */ 1538 if ((bank->bank_num == 0) || (bank->bank_num == 1)) { 1539 *regmap = info->regmap_pmu; 1540 *reg = RK3399_PULL_PMU_OFFSET; 1541 1542 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1543 1544 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1545 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 1546 *bit *= RK3188_PULL_BITS_PER_PIN; 1547 } else { 1548 *regmap = info->regmap_base; 1549 *reg = RK3399_PULL_GRF_OFFSET; 1550 1551 /* correct the offset, as we're starting with the 3rd bank */ 1552 *reg -= 0x20; 1553 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1554 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1555 1556 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1557 *bit *= RK3188_PULL_BITS_PER_PIN; 1558 } 1559 } 1560 1561 static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1562 int pin_num, struct regmap **regmap, 1563 int *reg, u8 *bit) 1564 { 1565 struct rockchip_pinctrl *info = bank->drvdata; 1566 int drv_num = (pin_num / 8); 1567 1568 /* The bank0:16 and bank1:32 pins are located in PMU */ 1569 if ((bank->bank_num == 0) || (bank->bank_num == 1)) 1570 *regmap = info->regmap_pmu; 1571 else 1572 *regmap = info->regmap_base; 1573 1574 *reg = bank->drv[drv_num].offset; 1575 if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) || 1576 (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY)) 1577 *bit = (pin_num % 8) * 3; 1578 else 1579 *bit = (pin_num % 8) * 2; 1580 } 1581 1582 static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = { 1583 { 2, 4, 8, 12, -1, -1, -1, -1 }, 1584 { 3, 6, 9, 12, -1, -1, -1, -1 }, 1585 { 5, 10, 15, 20, -1, -1, -1, -1 }, 1586 { 4, 6, 8, 10, 12, 14, 16, 18 }, 1587 { 4, 7, 10, 13, 16, 19, 22, 26 } 1588 }; 1589 1590 static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank, 1591 int pin_num) 1592 { 1593 struct rockchip_pinctrl *info = bank->drvdata; 1594 struct rockchip_pin_ctrl *ctrl = info->ctrl; 1595 struct regmap *regmap; 1596 int reg, ret; 1597 u32 data, temp, rmask_bits; 1598 u8 bit; 1599 int drv_type = bank->drv[pin_num / 8].drv_type; 1600 1601 ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); 1602 1603 switch (drv_type) { 1604 case DRV_TYPE_IO_1V8_3V0_AUTO: 1605 case DRV_TYPE_IO_3V3_ONLY: 1606 rmask_bits = RK3399_DRV_3BITS_PER_PIN; 1607 switch (bit) { 1608 case 0 ... 12: 1609 /* regular case, nothing to do */ 1610 break; 1611 case 15: 1612 /* 1613 * drive-strength offset is special, as it is 1614 * spread over 2 registers 1615 */ 1616 ret = regmap_read(regmap, reg, &data); 1617 if (ret) 1618 return ret; 1619 1620 ret = regmap_read(regmap, reg + 0x4, &temp); 1621 if (ret) 1622 return ret; 1623 1624 /* 1625 * the bit data[15] contains bit 0 of the value 1626 * while temp[1:0] contains bits 2 and 1 1627 */ 1628 data >>= 15; 1629 temp &= 0x3; 1630 temp <<= 1; 1631 data |= temp; 1632 1633 return rockchip_perpin_drv_list[drv_type][data]; 1634 case 18 ... 21: 1635 /* setting fully enclosed in the second register */ 1636 reg += 4; 1637 bit -= 16; 1638 break; 1639 default: 1640 dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n", 1641 bit, drv_type); 1642 return -EINVAL; 1643 } 1644 1645 break; 1646 case DRV_TYPE_IO_DEFAULT: 1647 case DRV_TYPE_IO_1V8_OR_3V0: 1648 case DRV_TYPE_IO_1V8_ONLY: 1649 rmask_bits = RK3288_DRV_BITS_PER_PIN; 1650 break; 1651 default: 1652 dev_err(info->dev, "unsupported pinctrl drive type: %d\n", 1653 drv_type); 1654 return -EINVAL; 1655 } 1656 1657 ret = regmap_read(regmap, reg, &data); 1658 if (ret) 1659 return ret; 1660 1661 data >>= bit; 1662 data &= (1 << rmask_bits) - 1; 1663 1664 return rockchip_perpin_drv_list[drv_type][data]; 1665 } 1666 1667 static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank, 1668 int pin_num, int strength) 1669 { 1670 struct rockchip_pinctrl *info = bank->drvdata; 1671 struct rockchip_pin_ctrl *ctrl = info->ctrl; 1672 struct regmap *regmap; 1673 int reg, ret, i; 1674 u32 data, rmask, rmask_bits, temp; 1675 u8 bit; 1676 int drv_type = bank->drv[pin_num / 8].drv_type; 1677 1678 dev_dbg(info->dev, "setting drive of GPIO%d-%d to %d\n", 1679 bank->bank_num, pin_num, strength); 1680 1681 ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); 1682 1683 ret = -EINVAL; 1684 for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) { 1685 if (rockchip_perpin_drv_list[drv_type][i] == strength) { 1686 ret = i; 1687 break; 1688 } else if (rockchip_perpin_drv_list[drv_type][i] < 0) { 1689 ret = rockchip_perpin_drv_list[drv_type][i]; 1690 break; 1691 } 1692 } 1693 1694 if (ret < 0) { 1695 dev_err(info->dev, "unsupported driver strength %d\n", 1696 strength); 1697 return ret; 1698 } 1699 1700 switch (drv_type) { 1701 case DRV_TYPE_IO_1V8_3V0_AUTO: 1702 case DRV_TYPE_IO_3V3_ONLY: 1703 rmask_bits = RK3399_DRV_3BITS_PER_PIN; 1704 switch (bit) { 1705 case 0 ... 12: 1706 /* regular case, nothing to do */ 1707 break; 1708 case 15: 1709 /* 1710 * drive-strength offset is special, as it is spread 1711 * over 2 registers, the bit data[15] contains bit 0 1712 * of the value while temp[1:0] contains bits 2 and 1 1713 */ 1714 data = (ret & 0x1) << 15; 1715 temp = (ret >> 0x1) & 0x3; 1716 1717 rmask = BIT(15) | BIT(31); 1718 data |= BIT(31); 1719 ret = regmap_update_bits(regmap, reg, rmask, data); 1720 if (ret) 1721 return ret; 1722 1723 rmask = 0x3 | (0x3 << 16); 1724 temp |= (0x3 << 16); 1725 reg += 0x4; 1726 ret = regmap_update_bits(regmap, reg, rmask, temp); 1727 1728 return ret; 1729 case 18 ... 21: 1730 /* setting fully enclosed in the second register */ 1731 reg += 4; 1732 bit -= 16; 1733 break; 1734 default: 1735 dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n", 1736 bit, drv_type); 1737 return -EINVAL; 1738 } 1739 break; 1740 case DRV_TYPE_IO_DEFAULT: 1741 case DRV_TYPE_IO_1V8_OR_3V0: 1742 case DRV_TYPE_IO_1V8_ONLY: 1743 rmask_bits = RK3288_DRV_BITS_PER_PIN; 1744 break; 1745 default: 1746 dev_err(info->dev, "unsupported pinctrl drive type: %d\n", 1747 drv_type); 1748 return -EINVAL; 1749 } 1750 1751 /* enable the write to the equivalent lower bits */ 1752 data = ((1 << rmask_bits) - 1) << (bit + 16); 1753 rmask = data | (data >> 16); 1754 data |= (ret << bit); 1755 1756 ret = regmap_update_bits(regmap, reg, rmask, data); 1757 1758 return ret; 1759 } 1760 1761 static int rockchip_pull_list[PULL_TYPE_MAX][4] = { 1762 { 1763 PIN_CONFIG_BIAS_DISABLE, 1764 PIN_CONFIG_BIAS_PULL_UP, 1765 PIN_CONFIG_BIAS_PULL_DOWN, 1766 PIN_CONFIG_BIAS_BUS_HOLD 1767 }, 1768 { 1769 PIN_CONFIG_BIAS_DISABLE, 1770 PIN_CONFIG_BIAS_PULL_DOWN, 1771 PIN_CONFIG_BIAS_DISABLE, 1772 PIN_CONFIG_BIAS_PULL_UP 1773 }, 1774 }; 1775 1776 static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num) 1777 { 1778 struct rockchip_pinctrl *info = bank->drvdata; 1779 struct rockchip_pin_ctrl *ctrl = info->ctrl; 1780 struct regmap *regmap; 1781 int reg, ret, pull_type; 1782 u8 bit; 1783 u32 data; 1784 1785 /* rk3066b does support any pulls */ 1786 if (ctrl->type == RK3066B) 1787 return PIN_CONFIG_BIAS_DISABLE; 1788 1789 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); 1790 1791 ret = regmap_read(regmap, reg, &data); 1792 if (ret) 1793 return ret; 1794 1795 switch (ctrl->type) { 1796 case RK2928: 1797 case RK3128: 1798 return !(data & BIT(bit)) 1799 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT 1800 : PIN_CONFIG_BIAS_DISABLE; 1801 case RV1108: 1802 case RK3188: 1803 case RK3288: 1804 case RK3368: 1805 case RK3399: 1806 pull_type = bank->pull_type[pin_num / 8]; 1807 data >>= bit; 1808 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1; 1809 1810 return rockchip_pull_list[pull_type][data]; 1811 default: 1812 dev_err(info->dev, "unsupported pinctrl type\n"); 1813 return -EINVAL; 1814 }; 1815 } 1816 1817 static int rockchip_set_pull(struct rockchip_pin_bank *bank, 1818 int pin_num, int pull) 1819 { 1820 struct rockchip_pinctrl *info = bank->drvdata; 1821 struct rockchip_pin_ctrl *ctrl = info->ctrl; 1822 struct regmap *regmap; 1823 int reg, ret, i, pull_type; 1824 u8 bit; 1825 u32 data, rmask; 1826 1827 dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n", 1828 bank->bank_num, pin_num, pull); 1829 1830 /* rk3066b does support any pulls */ 1831 if (ctrl->type == RK3066B) 1832 return pull ? -EINVAL : 0; 1833 1834 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); 1835 1836 switch (ctrl->type) { 1837 case RK2928: 1838 case RK3128: 1839 data = BIT(bit + 16); 1840 if (pull == PIN_CONFIG_BIAS_DISABLE) 1841 data |= BIT(bit); 1842 ret = regmap_write(regmap, reg, data); 1843 break; 1844 case RV1108: 1845 case RK3188: 1846 case RK3288: 1847 case RK3368: 1848 case RK3399: 1849 pull_type = bank->pull_type[pin_num / 8]; 1850 ret = -EINVAL; 1851 for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]); 1852 i++) { 1853 if (rockchip_pull_list[pull_type][i] == pull) { 1854 ret = i; 1855 break; 1856 } 1857 } 1858 1859 if (ret < 0) { 1860 dev_err(info->dev, "unsupported pull setting %d\n", 1861 pull); 1862 return ret; 1863 } 1864 1865 /* enable the write to the equivalent lower bits */ 1866 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16); 1867 rmask = data | (data >> 16); 1868 data |= (ret << bit); 1869 1870 ret = regmap_update_bits(regmap, reg, rmask, data); 1871 break; 1872 default: 1873 dev_err(info->dev, "unsupported pinctrl type\n"); 1874 return -EINVAL; 1875 } 1876 1877 return ret; 1878 } 1879 1880 #define RK3328_SCHMITT_BITS_PER_PIN 1 1881 #define RK3328_SCHMITT_PINS_PER_REG 16 1882 #define RK3328_SCHMITT_BANK_STRIDE 8 1883 #define RK3328_SCHMITT_GRF_OFFSET 0x380 1884 1885 static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1886 int pin_num, 1887 struct regmap **regmap, 1888 int *reg, u8 *bit) 1889 { 1890 struct rockchip_pinctrl *info = bank->drvdata; 1891 1892 *regmap = info->regmap_base; 1893 *reg = RK3328_SCHMITT_GRF_OFFSET; 1894 1895 *reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE; 1896 *reg += ((pin_num / RK3328_SCHMITT_PINS_PER_REG) * 4); 1897 *bit = pin_num % RK3328_SCHMITT_PINS_PER_REG; 1898 1899 return 0; 1900 } 1901 1902 static int rockchip_get_schmitt(struct rockchip_pin_bank *bank, int pin_num) 1903 { 1904 struct rockchip_pinctrl *info = bank->drvdata; 1905 struct rockchip_pin_ctrl *ctrl = info->ctrl; 1906 struct regmap *regmap; 1907 int reg, ret; 1908 u8 bit; 1909 u32 data; 1910 1911 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit); 1912 if (ret) 1913 return ret; 1914 1915 ret = regmap_read(regmap, reg, &data); 1916 if (ret) 1917 return ret; 1918 1919 data >>= bit; 1920 return data & 0x1; 1921 } 1922 1923 static int rockchip_set_schmitt(struct rockchip_pin_bank *bank, 1924 int pin_num, int enable) 1925 { 1926 struct rockchip_pinctrl *info = bank->drvdata; 1927 struct rockchip_pin_ctrl *ctrl = info->ctrl; 1928 struct regmap *regmap; 1929 int reg, ret; 1930 u8 bit; 1931 u32 data, rmask; 1932 1933 dev_dbg(info->dev, "setting input schmitt of GPIO%d-%d to %d\n", 1934 bank->bank_num, pin_num, enable); 1935 1936 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit); 1937 if (ret) 1938 return ret; 1939 1940 /* enable the write to the equivalent lower bits */ 1941 data = BIT(bit + 16) | (enable << bit); 1942 rmask = BIT(bit + 16) | BIT(bit); 1943 1944 return regmap_update_bits(regmap, reg, rmask, data); 1945 } 1946 1947 /* 1948 * Pinmux_ops handling 1949 */ 1950 1951 static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev) 1952 { 1953 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1954 1955 return info->nfunctions; 1956 } 1957 1958 static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev, 1959 unsigned selector) 1960 { 1961 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1962 1963 return info->functions[selector].name; 1964 } 1965 1966 static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev, 1967 unsigned selector, const char * const **groups, 1968 unsigned * const num_groups) 1969 { 1970 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1971 1972 *groups = info->functions[selector].groups; 1973 *num_groups = info->functions[selector].ngroups; 1974 1975 return 0; 1976 } 1977 1978 static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector, 1979 unsigned group) 1980 { 1981 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1982 const unsigned int *pins = info->groups[group].pins; 1983 const struct rockchip_pin_config *data = info->groups[group].data; 1984 struct rockchip_pin_bank *bank; 1985 int cnt, ret = 0; 1986 1987 dev_dbg(info->dev, "enable function %s group %s\n", 1988 info->functions[selector].name, info->groups[group].name); 1989 1990 /* 1991 * for each pin in the pin group selected, program the correspoding pin 1992 * pin function number in the config register. 1993 */ 1994 for (cnt = 0; cnt < info->groups[group].npins; cnt++) { 1995 bank = pin_to_bank(info, pins[cnt]); 1996 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 1997 data[cnt].func); 1998 if (ret) 1999 break; 2000 } 2001 2002 if (ret) { 2003 /* revert the already done pin settings */ 2004 for (cnt--; cnt >= 0; cnt--) 2005 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0); 2006 2007 return ret; 2008 } 2009 2010 return 0; 2011 } 2012 2013 static int rockchip_gpio_get_direction(struct gpio_chip *chip, unsigned offset) 2014 { 2015 struct rockchip_pin_bank *bank = gpiochip_get_data(chip); 2016 u32 data; 2017 2018 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); 2019 2020 return !(data & BIT(offset)); 2021 } 2022 2023 /* 2024 * The calls to gpio_direction_output() and gpio_direction_input() 2025 * leads to this function call (via the pinctrl_gpio_direction_{input|output}() 2026 * function called from the gpiolib interface). 2027 */ 2028 static int _rockchip_pmx_gpio_set_direction(struct gpio_chip *chip, 2029 int pin, bool input) 2030 { 2031 struct rockchip_pin_bank *bank; 2032 int ret; 2033 unsigned long flags; 2034 u32 data; 2035 2036 bank = gpiochip_get_data(chip); 2037 2038 ret = rockchip_set_mux(bank, pin, RK_FUNC_GPIO); 2039 if (ret < 0) 2040 return ret; 2041 2042 clk_enable(bank->clk); 2043 raw_spin_lock_irqsave(&bank->slock, flags); 2044 2045 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); 2046 /* set bit to 1 for output, 0 for input */ 2047 if (!input) 2048 data |= BIT(pin); 2049 else 2050 data &= ~BIT(pin); 2051 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR); 2052 2053 raw_spin_unlock_irqrestore(&bank->slock, flags); 2054 clk_disable(bank->clk); 2055 2056 return 0; 2057 } 2058 2059 static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, 2060 struct pinctrl_gpio_range *range, 2061 unsigned offset, bool input) 2062 { 2063 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 2064 struct gpio_chip *chip; 2065 int pin; 2066 2067 chip = range->gc; 2068 pin = offset - chip->base; 2069 dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n", 2070 offset, range->name, pin, input ? "input" : "output"); 2071 2072 return _rockchip_pmx_gpio_set_direction(chip, offset - chip->base, 2073 input); 2074 } 2075 2076 static const struct pinmux_ops rockchip_pmx_ops = { 2077 .get_functions_count = rockchip_pmx_get_funcs_count, 2078 .get_function_name = rockchip_pmx_get_func_name, 2079 .get_function_groups = rockchip_pmx_get_groups, 2080 .set_mux = rockchip_pmx_set, 2081 .gpio_set_direction = rockchip_pmx_gpio_set_direction, 2082 }; 2083 2084 /* 2085 * Pinconf_ops handling 2086 */ 2087 2088 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl, 2089 enum pin_config_param pull) 2090 { 2091 switch (ctrl->type) { 2092 case RK2928: 2093 case RK3128: 2094 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT || 2095 pull == PIN_CONFIG_BIAS_DISABLE); 2096 case RK3066B: 2097 return pull ? false : true; 2098 case RV1108: 2099 case RK3188: 2100 case RK3288: 2101 case RK3368: 2102 case RK3399: 2103 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT); 2104 } 2105 2106 return false; 2107 } 2108 2109 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value); 2110 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset); 2111 2112 /* set the pin config settings for a specified pin */ 2113 static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 2114 unsigned long *configs, unsigned num_configs) 2115 { 2116 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 2117 struct rockchip_pin_bank *bank = pin_to_bank(info, pin); 2118 enum pin_config_param param; 2119 u32 arg; 2120 int i; 2121 int rc; 2122 2123 for (i = 0; i < num_configs; i++) { 2124 param = pinconf_to_config_param(configs[i]); 2125 arg = pinconf_to_config_argument(configs[i]); 2126 2127 switch (param) { 2128 case PIN_CONFIG_BIAS_DISABLE: 2129 rc = rockchip_set_pull(bank, pin - bank->pin_base, 2130 param); 2131 if (rc) 2132 return rc; 2133 break; 2134 case PIN_CONFIG_BIAS_PULL_UP: 2135 case PIN_CONFIG_BIAS_PULL_DOWN: 2136 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: 2137 case PIN_CONFIG_BIAS_BUS_HOLD: 2138 if (!rockchip_pinconf_pull_valid(info->ctrl, param)) 2139 return -ENOTSUPP; 2140 2141 if (!arg) 2142 return -EINVAL; 2143 2144 rc = rockchip_set_pull(bank, pin - bank->pin_base, 2145 param); 2146 if (rc) 2147 return rc; 2148 break; 2149 case PIN_CONFIG_OUTPUT: 2150 rockchip_gpio_set(&bank->gpio_chip, 2151 pin - bank->pin_base, arg); 2152 rc = _rockchip_pmx_gpio_set_direction(&bank->gpio_chip, 2153 pin - bank->pin_base, false); 2154 if (rc) 2155 return rc; 2156 break; 2157 case PIN_CONFIG_DRIVE_STRENGTH: 2158 /* rk3288 is the first with per-pin drive-strength */ 2159 if (!info->ctrl->drv_calc_reg) 2160 return -ENOTSUPP; 2161 2162 rc = rockchip_set_drive_perpin(bank, 2163 pin - bank->pin_base, arg); 2164 if (rc < 0) 2165 return rc; 2166 break; 2167 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 2168 if (!info->ctrl->schmitt_calc_reg) 2169 return -ENOTSUPP; 2170 2171 rc = rockchip_set_schmitt(bank, 2172 pin - bank->pin_base, arg); 2173 if (rc < 0) 2174 return rc; 2175 break; 2176 default: 2177 return -ENOTSUPP; 2178 break; 2179 } 2180 } /* for each config */ 2181 2182 return 0; 2183 } 2184 2185 /* get the pin config settings for a specified pin */ 2186 static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, 2187 unsigned long *config) 2188 { 2189 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 2190 struct rockchip_pin_bank *bank = pin_to_bank(info, pin); 2191 enum pin_config_param param = pinconf_to_config_param(*config); 2192 u16 arg; 2193 int rc; 2194 2195 switch (param) { 2196 case PIN_CONFIG_BIAS_DISABLE: 2197 if (rockchip_get_pull(bank, pin - bank->pin_base) != param) 2198 return -EINVAL; 2199 2200 arg = 0; 2201 break; 2202 case PIN_CONFIG_BIAS_PULL_UP: 2203 case PIN_CONFIG_BIAS_PULL_DOWN: 2204 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: 2205 case PIN_CONFIG_BIAS_BUS_HOLD: 2206 if (!rockchip_pinconf_pull_valid(info->ctrl, param)) 2207 return -ENOTSUPP; 2208 2209 if (rockchip_get_pull(bank, pin - bank->pin_base) != param) 2210 return -EINVAL; 2211 2212 arg = 1; 2213 break; 2214 case PIN_CONFIG_OUTPUT: 2215 rc = rockchip_get_mux(bank, pin - bank->pin_base); 2216 if (rc != RK_FUNC_GPIO) 2217 return -EINVAL; 2218 2219 rc = rockchip_gpio_get(&bank->gpio_chip, pin - bank->pin_base); 2220 if (rc < 0) 2221 return rc; 2222 2223 arg = rc ? 1 : 0; 2224 break; 2225 case PIN_CONFIG_DRIVE_STRENGTH: 2226 /* rk3288 is the first with per-pin drive-strength */ 2227 if (!info->ctrl->drv_calc_reg) 2228 return -ENOTSUPP; 2229 2230 rc = rockchip_get_drive_perpin(bank, pin - bank->pin_base); 2231 if (rc < 0) 2232 return rc; 2233 2234 arg = rc; 2235 break; 2236 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 2237 if (!info->ctrl->schmitt_calc_reg) 2238 return -ENOTSUPP; 2239 2240 rc = rockchip_get_schmitt(bank, pin - bank->pin_base); 2241 if (rc < 0) 2242 return rc; 2243 2244 arg = rc; 2245 break; 2246 default: 2247 return -ENOTSUPP; 2248 break; 2249 } 2250 2251 *config = pinconf_to_config_packed(param, arg); 2252 2253 return 0; 2254 } 2255 2256 static const struct pinconf_ops rockchip_pinconf_ops = { 2257 .pin_config_get = rockchip_pinconf_get, 2258 .pin_config_set = rockchip_pinconf_set, 2259 .is_generic = true, 2260 }; 2261 2262 static const struct of_device_id rockchip_bank_match[] = { 2263 { .compatible = "rockchip,gpio-bank" }, 2264 { .compatible = "rockchip,rk3188-gpio-bank0" }, 2265 {}, 2266 }; 2267 2268 static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info, 2269 struct device_node *np) 2270 { 2271 struct device_node *child; 2272 2273 for_each_child_of_node(np, child) { 2274 if (of_match_node(rockchip_bank_match, child)) 2275 continue; 2276 2277 info->nfunctions++; 2278 info->ngroups += of_get_child_count(child); 2279 } 2280 } 2281 2282 static int rockchip_pinctrl_parse_groups(struct device_node *np, 2283 struct rockchip_pin_group *grp, 2284 struct rockchip_pinctrl *info, 2285 u32 index) 2286 { 2287 struct rockchip_pin_bank *bank; 2288 int size; 2289 const __be32 *list; 2290 int num; 2291 int i, j; 2292 int ret; 2293 2294 dev_dbg(info->dev, "group(%d): %s\n", index, np->name); 2295 2296 /* Initialise group */ 2297 grp->name = np->name; 2298 2299 /* 2300 * the binding format is rockchip,pins = <bank pin mux CONFIG>, 2301 * do sanity check and calculate pins number 2302 */ 2303 list = of_get_property(np, "rockchip,pins", &size); 2304 /* we do not check return since it's safe node passed down */ 2305 size /= sizeof(*list); 2306 if (!size || size % 4) { 2307 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n"); 2308 return -EINVAL; 2309 } 2310 2311 grp->npins = size / 4; 2312 2313 grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int), 2314 GFP_KERNEL); 2315 grp->data = devm_kzalloc(info->dev, grp->npins * 2316 sizeof(struct rockchip_pin_config), 2317 GFP_KERNEL); 2318 if (!grp->pins || !grp->data) 2319 return -ENOMEM; 2320 2321 for (i = 0, j = 0; i < size; i += 4, j++) { 2322 const __be32 *phandle; 2323 struct device_node *np_config; 2324 2325 num = be32_to_cpu(*list++); 2326 bank = bank_num_to_bank(info, num); 2327 if (IS_ERR(bank)) 2328 return PTR_ERR(bank); 2329 2330 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++); 2331 grp->data[j].func = be32_to_cpu(*list++); 2332 2333 phandle = list++; 2334 if (!phandle) 2335 return -EINVAL; 2336 2337 np_config = of_find_node_by_phandle(be32_to_cpup(phandle)); 2338 ret = pinconf_generic_parse_dt_config(np_config, NULL, 2339 &grp->data[j].configs, &grp->data[j].nconfigs); 2340 if (ret) 2341 return ret; 2342 } 2343 2344 return 0; 2345 } 2346 2347 static int rockchip_pinctrl_parse_functions(struct device_node *np, 2348 struct rockchip_pinctrl *info, 2349 u32 index) 2350 { 2351 struct device_node *child; 2352 struct rockchip_pmx_func *func; 2353 struct rockchip_pin_group *grp; 2354 int ret; 2355 static u32 grp_index; 2356 u32 i = 0; 2357 2358 dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name); 2359 2360 func = &info->functions[index]; 2361 2362 /* Initialise function */ 2363 func->name = np->name; 2364 func->ngroups = of_get_child_count(np); 2365 if (func->ngroups <= 0) 2366 return 0; 2367 2368 func->groups = devm_kzalloc(info->dev, 2369 func->ngroups * sizeof(char *), GFP_KERNEL); 2370 if (!func->groups) 2371 return -ENOMEM; 2372 2373 for_each_child_of_node(np, child) { 2374 func->groups[i] = child->name; 2375 grp = &info->groups[grp_index++]; 2376 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++); 2377 if (ret) { 2378 of_node_put(child); 2379 return ret; 2380 } 2381 } 2382 2383 return 0; 2384 } 2385 2386 static int rockchip_pinctrl_parse_dt(struct platform_device *pdev, 2387 struct rockchip_pinctrl *info) 2388 { 2389 struct device *dev = &pdev->dev; 2390 struct device_node *np = dev->of_node; 2391 struct device_node *child; 2392 int ret; 2393 int i; 2394 2395 rockchip_pinctrl_child_count(info, np); 2396 2397 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions); 2398 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups); 2399 2400 info->functions = devm_kzalloc(dev, info->nfunctions * 2401 sizeof(struct rockchip_pmx_func), 2402 GFP_KERNEL); 2403 if (!info->functions) { 2404 dev_err(dev, "failed to allocate memory for function list\n"); 2405 return -EINVAL; 2406 } 2407 2408 info->groups = devm_kzalloc(dev, info->ngroups * 2409 sizeof(struct rockchip_pin_group), 2410 GFP_KERNEL); 2411 if (!info->groups) { 2412 dev_err(dev, "failed allocate memory for ping group list\n"); 2413 return -EINVAL; 2414 } 2415 2416 i = 0; 2417 2418 for_each_child_of_node(np, child) { 2419 if (of_match_node(rockchip_bank_match, child)) 2420 continue; 2421 2422 ret = rockchip_pinctrl_parse_functions(child, info, i++); 2423 if (ret) { 2424 dev_err(&pdev->dev, "failed to parse function\n"); 2425 of_node_put(child); 2426 return ret; 2427 } 2428 } 2429 2430 return 0; 2431 } 2432 2433 static int rockchip_pinctrl_register(struct platform_device *pdev, 2434 struct rockchip_pinctrl *info) 2435 { 2436 struct pinctrl_desc *ctrldesc = &info->pctl; 2437 struct pinctrl_pin_desc *pindesc, *pdesc; 2438 struct rockchip_pin_bank *pin_bank; 2439 int pin, bank, ret; 2440 int k; 2441 2442 ctrldesc->name = "rockchip-pinctrl"; 2443 ctrldesc->owner = THIS_MODULE; 2444 ctrldesc->pctlops = &rockchip_pctrl_ops; 2445 ctrldesc->pmxops = &rockchip_pmx_ops; 2446 ctrldesc->confops = &rockchip_pinconf_ops; 2447 2448 pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) * 2449 info->ctrl->nr_pins, GFP_KERNEL); 2450 if (!pindesc) { 2451 dev_err(&pdev->dev, "mem alloc for pin descriptors failed\n"); 2452 return -ENOMEM; 2453 } 2454 ctrldesc->pins = pindesc; 2455 ctrldesc->npins = info->ctrl->nr_pins; 2456 2457 pdesc = pindesc; 2458 for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) { 2459 pin_bank = &info->ctrl->pin_banks[bank]; 2460 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) { 2461 pdesc->number = k; 2462 pdesc->name = kasprintf(GFP_KERNEL, "%s-%d", 2463 pin_bank->name, pin); 2464 pdesc++; 2465 } 2466 } 2467 2468 ret = rockchip_pinctrl_parse_dt(pdev, info); 2469 if (ret) 2470 return ret; 2471 2472 info->pctl_dev = devm_pinctrl_register(&pdev->dev, ctrldesc, info); 2473 if (IS_ERR(info->pctl_dev)) { 2474 dev_err(&pdev->dev, "could not register pinctrl driver\n"); 2475 return PTR_ERR(info->pctl_dev); 2476 } 2477 2478 for (bank = 0; bank < info->ctrl->nr_banks; ++bank) { 2479 pin_bank = &info->ctrl->pin_banks[bank]; 2480 pin_bank->grange.name = pin_bank->name; 2481 pin_bank->grange.id = bank; 2482 pin_bank->grange.pin_base = pin_bank->pin_base; 2483 pin_bank->grange.base = pin_bank->gpio_chip.base; 2484 pin_bank->grange.npins = pin_bank->gpio_chip.ngpio; 2485 pin_bank->grange.gc = &pin_bank->gpio_chip; 2486 pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange); 2487 } 2488 2489 return 0; 2490 } 2491 2492 /* 2493 * GPIO handling 2494 */ 2495 2496 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value) 2497 { 2498 struct rockchip_pin_bank *bank = gpiochip_get_data(gc); 2499 void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR; 2500 unsigned long flags; 2501 u32 data; 2502 2503 clk_enable(bank->clk); 2504 raw_spin_lock_irqsave(&bank->slock, flags); 2505 2506 data = readl(reg); 2507 data &= ~BIT(offset); 2508 if (value) 2509 data |= BIT(offset); 2510 writel(data, reg); 2511 2512 raw_spin_unlock_irqrestore(&bank->slock, flags); 2513 clk_disable(bank->clk); 2514 } 2515 2516 /* 2517 * Returns the level of the pin for input direction and setting of the DR 2518 * register for output gpios. 2519 */ 2520 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset) 2521 { 2522 struct rockchip_pin_bank *bank = gpiochip_get_data(gc); 2523 u32 data; 2524 2525 clk_enable(bank->clk); 2526 data = readl(bank->reg_base + GPIO_EXT_PORT); 2527 clk_disable(bank->clk); 2528 data >>= offset; 2529 data &= 1; 2530 return data; 2531 } 2532 2533 /* 2534 * gpiolib gpio_direction_input callback function. The setting of the pin 2535 * mux function as 'gpio input' will be handled by the pinctrl susbsystem 2536 * interface. 2537 */ 2538 static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset) 2539 { 2540 return pinctrl_gpio_direction_input(gc->base + offset); 2541 } 2542 2543 /* 2544 * gpiolib gpio_direction_output callback function. The setting of the pin 2545 * mux function as 'gpio output' will be handled by the pinctrl susbsystem 2546 * interface. 2547 */ 2548 static int rockchip_gpio_direction_output(struct gpio_chip *gc, 2549 unsigned offset, int value) 2550 { 2551 rockchip_gpio_set(gc, offset, value); 2552 return pinctrl_gpio_direction_output(gc->base + offset); 2553 } 2554 2555 /* 2556 * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin 2557 * and a virtual IRQ, if not already present. 2558 */ 2559 static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset) 2560 { 2561 struct rockchip_pin_bank *bank = gpiochip_get_data(gc); 2562 unsigned int virq; 2563 2564 if (!bank->domain) 2565 return -ENXIO; 2566 2567 virq = irq_create_mapping(bank->domain, offset); 2568 2569 return (virq) ? : -ENXIO; 2570 } 2571 2572 static const struct gpio_chip rockchip_gpiolib_chip = { 2573 .request = gpiochip_generic_request, 2574 .free = gpiochip_generic_free, 2575 .set = rockchip_gpio_set, 2576 .get = rockchip_gpio_get, 2577 .get_direction = rockchip_gpio_get_direction, 2578 .direction_input = rockchip_gpio_direction_input, 2579 .direction_output = rockchip_gpio_direction_output, 2580 .to_irq = rockchip_gpio_to_irq, 2581 .owner = THIS_MODULE, 2582 }; 2583 2584 /* 2585 * Interrupt handling 2586 */ 2587 2588 static void rockchip_irq_demux(struct irq_desc *desc) 2589 { 2590 struct irq_chip *chip = irq_desc_get_chip(desc); 2591 struct rockchip_pin_bank *bank = irq_desc_get_handler_data(desc); 2592 u32 pend; 2593 2594 dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name); 2595 2596 chained_irq_enter(chip, desc); 2597 2598 pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS); 2599 2600 while (pend) { 2601 unsigned int irq, virq; 2602 2603 irq = __ffs(pend); 2604 pend &= ~BIT(irq); 2605 virq = irq_linear_revmap(bank->domain, irq); 2606 2607 if (!virq) { 2608 dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq); 2609 continue; 2610 } 2611 2612 dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq); 2613 2614 /* 2615 * Triggering IRQ on both rising and falling edge 2616 * needs manual intervention. 2617 */ 2618 if (bank->toggle_edge_mode & BIT(irq)) { 2619 u32 data, data_old, polarity; 2620 unsigned long flags; 2621 2622 data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT); 2623 do { 2624 raw_spin_lock_irqsave(&bank->slock, flags); 2625 2626 polarity = readl_relaxed(bank->reg_base + 2627 GPIO_INT_POLARITY); 2628 if (data & BIT(irq)) 2629 polarity &= ~BIT(irq); 2630 else 2631 polarity |= BIT(irq); 2632 writel(polarity, 2633 bank->reg_base + GPIO_INT_POLARITY); 2634 2635 raw_spin_unlock_irqrestore(&bank->slock, flags); 2636 2637 data_old = data; 2638 data = readl_relaxed(bank->reg_base + 2639 GPIO_EXT_PORT); 2640 } while ((data & BIT(irq)) != (data_old & BIT(irq))); 2641 } 2642 2643 generic_handle_irq(virq); 2644 } 2645 2646 chained_irq_exit(chip, desc); 2647 } 2648 2649 static int rockchip_irq_set_type(struct irq_data *d, unsigned int type) 2650 { 2651 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 2652 struct rockchip_pin_bank *bank = gc->private; 2653 u32 mask = BIT(d->hwirq); 2654 u32 polarity; 2655 u32 level; 2656 u32 data; 2657 unsigned long flags; 2658 int ret; 2659 2660 /* make sure the pin is configured as gpio input */ 2661 ret = rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO); 2662 if (ret < 0) 2663 return ret; 2664 2665 clk_enable(bank->clk); 2666 raw_spin_lock_irqsave(&bank->slock, flags); 2667 2668 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); 2669 data &= ~mask; 2670 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR); 2671 2672 raw_spin_unlock_irqrestore(&bank->slock, flags); 2673 2674 if (type & IRQ_TYPE_EDGE_BOTH) 2675 irq_set_handler_locked(d, handle_edge_irq); 2676 else 2677 irq_set_handler_locked(d, handle_level_irq); 2678 2679 raw_spin_lock_irqsave(&bank->slock, flags); 2680 irq_gc_lock(gc); 2681 2682 level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL); 2683 polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY); 2684 2685 switch (type) { 2686 case IRQ_TYPE_EDGE_BOTH: 2687 bank->toggle_edge_mode |= mask; 2688 level |= mask; 2689 2690 /* 2691 * Determine gpio state. If 1 next interrupt should be falling 2692 * otherwise rising. 2693 */ 2694 data = readl(bank->reg_base + GPIO_EXT_PORT); 2695 if (data & mask) 2696 polarity &= ~mask; 2697 else 2698 polarity |= mask; 2699 break; 2700 case IRQ_TYPE_EDGE_RISING: 2701 bank->toggle_edge_mode &= ~mask; 2702 level |= mask; 2703 polarity |= mask; 2704 break; 2705 case IRQ_TYPE_EDGE_FALLING: 2706 bank->toggle_edge_mode &= ~mask; 2707 level |= mask; 2708 polarity &= ~mask; 2709 break; 2710 case IRQ_TYPE_LEVEL_HIGH: 2711 bank->toggle_edge_mode &= ~mask; 2712 level &= ~mask; 2713 polarity |= mask; 2714 break; 2715 case IRQ_TYPE_LEVEL_LOW: 2716 bank->toggle_edge_mode &= ~mask; 2717 level &= ~mask; 2718 polarity &= ~mask; 2719 break; 2720 default: 2721 irq_gc_unlock(gc); 2722 raw_spin_unlock_irqrestore(&bank->slock, flags); 2723 clk_disable(bank->clk); 2724 return -EINVAL; 2725 } 2726 2727 writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL); 2728 writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY); 2729 2730 irq_gc_unlock(gc); 2731 raw_spin_unlock_irqrestore(&bank->slock, flags); 2732 clk_disable(bank->clk); 2733 2734 return 0; 2735 } 2736 2737 static void rockchip_irq_suspend(struct irq_data *d) 2738 { 2739 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 2740 struct rockchip_pin_bank *bank = gc->private; 2741 2742 clk_enable(bank->clk); 2743 bank->saved_masks = irq_reg_readl(gc, GPIO_INTMASK); 2744 irq_reg_writel(gc, ~gc->wake_active, GPIO_INTMASK); 2745 clk_disable(bank->clk); 2746 } 2747 2748 static void rockchip_irq_resume(struct irq_data *d) 2749 { 2750 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 2751 struct rockchip_pin_bank *bank = gc->private; 2752 2753 clk_enable(bank->clk); 2754 irq_reg_writel(gc, bank->saved_masks, GPIO_INTMASK); 2755 clk_disable(bank->clk); 2756 } 2757 2758 static void rockchip_irq_enable(struct irq_data *d) 2759 { 2760 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 2761 struct rockchip_pin_bank *bank = gc->private; 2762 2763 clk_enable(bank->clk); 2764 irq_gc_mask_clr_bit(d); 2765 } 2766 2767 static void rockchip_irq_disable(struct irq_data *d) 2768 { 2769 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 2770 struct rockchip_pin_bank *bank = gc->private; 2771 2772 irq_gc_mask_set_bit(d); 2773 clk_disable(bank->clk); 2774 } 2775 2776 static int rockchip_interrupts_register(struct platform_device *pdev, 2777 struct rockchip_pinctrl *info) 2778 { 2779 struct rockchip_pin_ctrl *ctrl = info->ctrl; 2780 struct rockchip_pin_bank *bank = ctrl->pin_banks; 2781 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; 2782 struct irq_chip_generic *gc; 2783 int ret; 2784 int i, j; 2785 2786 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 2787 if (!bank->valid) { 2788 dev_warn(&pdev->dev, "bank %s is not valid\n", 2789 bank->name); 2790 continue; 2791 } 2792 2793 ret = clk_enable(bank->clk); 2794 if (ret) { 2795 dev_err(&pdev->dev, "failed to enable clock for bank %s\n", 2796 bank->name); 2797 continue; 2798 } 2799 2800 bank->domain = irq_domain_add_linear(bank->of_node, 32, 2801 &irq_generic_chip_ops, NULL); 2802 if (!bank->domain) { 2803 dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n", 2804 bank->name); 2805 clk_disable(bank->clk); 2806 continue; 2807 } 2808 2809 ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1, 2810 "rockchip_gpio_irq", handle_level_irq, 2811 clr, 0, IRQ_GC_INIT_MASK_CACHE); 2812 if (ret) { 2813 dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n", 2814 bank->name); 2815 irq_domain_remove(bank->domain); 2816 clk_disable(bank->clk); 2817 continue; 2818 } 2819 2820 /* 2821 * Linux assumes that all interrupts start out disabled/masked. 2822 * Our driver only uses the concept of masked and always keeps 2823 * things enabled, so for us that's all masked and all enabled. 2824 */ 2825 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTMASK); 2826 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTEN); 2827 2828 gc = irq_get_domain_generic_chip(bank->domain, 0); 2829 gc->reg_base = bank->reg_base; 2830 gc->private = bank; 2831 gc->chip_types[0].regs.mask = GPIO_INTMASK; 2832 gc->chip_types[0].regs.ack = GPIO_PORTS_EOI; 2833 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit; 2834 gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit; 2835 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit; 2836 gc->chip_types[0].chip.irq_enable = rockchip_irq_enable; 2837 gc->chip_types[0].chip.irq_disable = rockchip_irq_disable; 2838 gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake; 2839 gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend; 2840 gc->chip_types[0].chip.irq_resume = rockchip_irq_resume; 2841 gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type; 2842 gc->wake_enabled = IRQ_MSK(bank->nr_pins); 2843 2844 irq_set_chained_handler_and_data(bank->irq, 2845 rockchip_irq_demux, bank); 2846 2847 /* map the gpio irqs here, when the clock is still running */ 2848 for (j = 0 ; j < 32 ; j++) 2849 irq_create_mapping(bank->domain, j); 2850 2851 clk_disable(bank->clk); 2852 } 2853 2854 return 0; 2855 } 2856 2857 static int rockchip_gpiolib_register(struct platform_device *pdev, 2858 struct rockchip_pinctrl *info) 2859 { 2860 struct rockchip_pin_ctrl *ctrl = info->ctrl; 2861 struct rockchip_pin_bank *bank = ctrl->pin_banks; 2862 struct gpio_chip *gc; 2863 int ret; 2864 int i; 2865 2866 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 2867 if (!bank->valid) { 2868 dev_warn(&pdev->dev, "bank %s is not valid\n", 2869 bank->name); 2870 continue; 2871 } 2872 2873 bank->gpio_chip = rockchip_gpiolib_chip; 2874 2875 gc = &bank->gpio_chip; 2876 gc->base = bank->pin_base; 2877 gc->ngpio = bank->nr_pins; 2878 gc->parent = &pdev->dev; 2879 gc->of_node = bank->of_node; 2880 gc->label = bank->name; 2881 2882 ret = gpiochip_add_data(gc, bank); 2883 if (ret) { 2884 dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n", 2885 gc->label, ret); 2886 goto fail; 2887 } 2888 } 2889 2890 rockchip_interrupts_register(pdev, info); 2891 2892 return 0; 2893 2894 fail: 2895 for (--i, --bank; i >= 0; --i, --bank) { 2896 if (!bank->valid) 2897 continue; 2898 gpiochip_remove(&bank->gpio_chip); 2899 } 2900 return ret; 2901 } 2902 2903 static int rockchip_gpiolib_unregister(struct platform_device *pdev, 2904 struct rockchip_pinctrl *info) 2905 { 2906 struct rockchip_pin_ctrl *ctrl = info->ctrl; 2907 struct rockchip_pin_bank *bank = ctrl->pin_banks; 2908 int i; 2909 2910 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 2911 if (!bank->valid) 2912 continue; 2913 gpiochip_remove(&bank->gpio_chip); 2914 } 2915 2916 return 0; 2917 } 2918 2919 static int rockchip_get_bank_data(struct rockchip_pin_bank *bank, 2920 struct rockchip_pinctrl *info) 2921 { 2922 struct resource res; 2923 void __iomem *base; 2924 2925 if (of_address_to_resource(bank->of_node, 0, &res)) { 2926 dev_err(info->dev, "cannot find IO resource for bank\n"); 2927 return -ENOENT; 2928 } 2929 2930 bank->reg_base = devm_ioremap_resource(info->dev, &res); 2931 if (IS_ERR(bank->reg_base)) 2932 return PTR_ERR(bank->reg_base); 2933 2934 /* 2935 * special case, where parts of the pull setting-registers are 2936 * part of the PMU register space 2937 */ 2938 if (of_device_is_compatible(bank->of_node, 2939 "rockchip,rk3188-gpio-bank0")) { 2940 struct device_node *node; 2941 2942 node = of_parse_phandle(bank->of_node->parent, 2943 "rockchip,pmu", 0); 2944 if (!node) { 2945 if (of_address_to_resource(bank->of_node, 1, &res)) { 2946 dev_err(info->dev, "cannot find IO resource for bank\n"); 2947 return -ENOENT; 2948 } 2949 2950 base = devm_ioremap_resource(info->dev, &res); 2951 if (IS_ERR(base)) 2952 return PTR_ERR(base); 2953 rockchip_regmap_config.max_register = 2954 resource_size(&res) - 4; 2955 rockchip_regmap_config.name = 2956 "rockchip,rk3188-gpio-bank0-pull"; 2957 bank->regmap_pull = devm_regmap_init_mmio(info->dev, 2958 base, 2959 &rockchip_regmap_config); 2960 } 2961 } 2962 2963 bank->irq = irq_of_parse_and_map(bank->of_node, 0); 2964 2965 bank->clk = of_clk_get(bank->of_node, 0); 2966 if (IS_ERR(bank->clk)) 2967 return PTR_ERR(bank->clk); 2968 2969 return clk_prepare(bank->clk); 2970 } 2971 2972 static const struct of_device_id rockchip_pinctrl_dt_match[]; 2973 2974 /* retrieve the soc specific data */ 2975 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data( 2976 struct rockchip_pinctrl *d, 2977 struct platform_device *pdev) 2978 { 2979 const struct of_device_id *match; 2980 struct device_node *node = pdev->dev.of_node; 2981 struct device_node *np; 2982 struct rockchip_pin_ctrl *ctrl; 2983 struct rockchip_pin_bank *bank; 2984 int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j; 2985 2986 match = of_match_node(rockchip_pinctrl_dt_match, node); 2987 ctrl = (struct rockchip_pin_ctrl *)match->data; 2988 2989 for_each_child_of_node(node, np) { 2990 if (!of_find_property(np, "gpio-controller", NULL)) 2991 continue; 2992 2993 bank = ctrl->pin_banks; 2994 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 2995 if (!strcmp(bank->name, np->name)) { 2996 bank->of_node = np; 2997 2998 if (!rockchip_get_bank_data(bank, d)) 2999 bank->valid = true; 3000 3001 break; 3002 } 3003 } 3004 } 3005 3006 grf_offs = ctrl->grf_mux_offset; 3007 pmu_offs = ctrl->pmu_mux_offset; 3008 drv_pmu_offs = ctrl->pmu_drv_offset; 3009 drv_grf_offs = ctrl->grf_drv_offset; 3010 bank = ctrl->pin_banks; 3011 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 3012 int bank_pins = 0; 3013 3014 raw_spin_lock_init(&bank->slock); 3015 bank->drvdata = d; 3016 bank->pin_base = ctrl->nr_pins; 3017 ctrl->nr_pins += bank->nr_pins; 3018 3019 /* calculate iomux and drv offsets */ 3020 for (j = 0; j < 4; j++) { 3021 struct rockchip_iomux *iom = &bank->iomux[j]; 3022 struct rockchip_drv *drv = &bank->drv[j]; 3023 int inc; 3024 3025 if (bank_pins >= bank->nr_pins) 3026 break; 3027 3028 /* preset iomux offset value, set new start value */ 3029 if (iom->offset >= 0) { 3030 if (iom->type & IOMUX_SOURCE_PMU) 3031 pmu_offs = iom->offset; 3032 else 3033 grf_offs = iom->offset; 3034 } else { /* set current iomux offset */ 3035 iom->offset = (iom->type & IOMUX_SOURCE_PMU) ? 3036 pmu_offs : grf_offs; 3037 } 3038 3039 /* preset drv offset value, set new start value */ 3040 if (drv->offset >= 0) { 3041 if (iom->type & IOMUX_SOURCE_PMU) 3042 drv_pmu_offs = drv->offset; 3043 else 3044 drv_grf_offs = drv->offset; 3045 } else { /* set current drv offset */ 3046 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ? 3047 drv_pmu_offs : drv_grf_offs; 3048 } 3049 3050 dev_dbg(d->dev, "bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n", 3051 i, j, iom->offset, drv->offset); 3052 3053 /* 3054 * Increase offset according to iomux width. 3055 * 4bit iomux'es are spread over two registers. 3056 */ 3057 inc = (iom->type & (IOMUX_WIDTH_4BIT | 3058 IOMUX_WIDTH_3BIT)) ? 8 : 4; 3059 if (iom->type & IOMUX_SOURCE_PMU) 3060 pmu_offs += inc; 3061 else 3062 grf_offs += inc; 3063 3064 /* 3065 * Increase offset according to drv width. 3066 * 3bit drive-strenth'es are spread over two registers. 3067 */ 3068 if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) || 3069 (drv->drv_type == DRV_TYPE_IO_3V3_ONLY)) 3070 inc = 8; 3071 else 3072 inc = 4; 3073 3074 if (iom->type & IOMUX_SOURCE_PMU) 3075 drv_pmu_offs += inc; 3076 else 3077 drv_grf_offs += inc; 3078 3079 bank_pins += 8; 3080 } 3081 3082 /* calculate the per-bank recalced_mask */ 3083 for (j = 0; j < ctrl->niomux_recalced; j++) { 3084 int pin = 0; 3085 3086 if (ctrl->iomux_recalced[j].num == bank->bank_num) { 3087 pin = ctrl->iomux_recalced[j].pin; 3088 bank->recalced_mask |= BIT(pin); 3089 } 3090 } 3091 3092 /* calculate the per-bank route_mask */ 3093 for (j = 0; j < ctrl->niomux_routes; j++) { 3094 int pin = 0; 3095 3096 if (ctrl->iomux_routes[j].bank_num == bank->bank_num) { 3097 pin = ctrl->iomux_routes[j].pin; 3098 bank->route_mask |= BIT(pin); 3099 } 3100 } 3101 } 3102 3103 return ctrl; 3104 } 3105 3106 #define RK3288_GRF_GPIO6C_IOMUX 0x64 3107 #define GPIO6C6_SEL_WRITE_ENABLE BIT(28) 3108 3109 static u32 rk3288_grf_gpio6c_iomux; 3110 3111 static int __maybe_unused rockchip_pinctrl_suspend(struct device *dev) 3112 { 3113 struct rockchip_pinctrl *info = dev_get_drvdata(dev); 3114 int ret = pinctrl_force_sleep(info->pctl_dev); 3115 3116 if (ret) 3117 return ret; 3118 3119 /* 3120 * RK3288 GPIO6_C6 mux would be modified by Maskrom when resume, so save 3121 * the setting here, and restore it at resume. 3122 */ 3123 if (info->ctrl->type == RK3288) { 3124 ret = regmap_read(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX, 3125 &rk3288_grf_gpio6c_iomux); 3126 if (ret) { 3127 pinctrl_force_default(info->pctl_dev); 3128 return ret; 3129 } 3130 } 3131 3132 return 0; 3133 } 3134 3135 static int __maybe_unused rockchip_pinctrl_resume(struct device *dev) 3136 { 3137 struct rockchip_pinctrl *info = dev_get_drvdata(dev); 3138 int ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX, 3139 rk3288_grf_gpio6c_iomux | 3140 GPIO6C6_SEL_WRITE_ENABLE); 3141 3142 if (ret) 3143 return ret; 3144 3145 return pinctrl_force_default(info->pctl_dev); 3146 } 3147 3148 static SIMPLE_DEV_PM_OPS(rockchip_pinctrl_dev_pm_ops, rockchip_pinctrl_suspend, 3149 rockchip_pinctrl_resume); 3150 3151 static int rockchip_pinctrl_probe(struct platform_device *pdev) 3152 { 3153 struct rockchip_pinctrl *info; 3154 struct device *dev = &pdev->dev; 3155 struct rockchip_pin_ctrl *ctrl; 3156 struct device_node *np = pdev->dev.of_node, *node; 3157 struct resource *res; 3158 void __iomem *base; 3159 int ret; 3160 3161 if (!dev->of_node) { 3162 dev_err(dev, "device tree node not found\n"); 3163 return -ENODEV; 3164 } 3165 3166 info = devm_kzalloc(dev, sizeof(struct rockchip_pinctrl), GFP_KERNEL); 3167 if (!info) 3168 return -ENOMEM; 3169 3170 info->dev = dev; 3171 3172 ctrl = rockchip_pinctrl_get_soc_data(info, pdev); 3173 if (!ctrl) { 3174 dev_err(dev, "driver data not available\n"); 3175 return -EINVAL; 3176 } 3177 info->ctrl = ctrl; 3178 3179 node = of_parse_phandle(np, "rockchip,grf", 0); 3180 if (node) { 3181 info->regmap_base = syscon_node_to_regmap(node); 3182 if (IS_ERR(info->regmap_base)) 3183 return PTR_ERR(info->regmap_base); 3184 } else { 3185 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 3186 base = devm_ioremap_resource(&pdev->dev, res); 3187 if (IS_ERR(base)) 3188 return PTR_ERR(base); 3189 3190 rockchip_regmap_config.max_register = resource_size(res) - 4; 3191 rockchip_regmap_config.name = "rockchip,pinctrl"; 3192 info->regmap_base = devm_regmap_init_mmio(&pdev->dev, base, 3193 &rockchip_regmap_config); 3194 3195 /* to check for the old dt-bindings */ 3196 info->reg_size = resource_size(res); 3197 3198 /* Honor the old binding, with pull registers as 2nd resource */ 3199 if (ctrl->type == RK3188 && info->reg_size < 0x200) { 3200 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 3201 base = devm_ioremap_resource(&pdev->dev, res); 3202 if (IS_ERR(base)) 3203 return PTR_ERR(base); 3204 3205 rockchip_regmap_config.max_register = 3206 resource_size(res) - 4; 3207 rockchip_regmap_config.name = "rockchip,pinctrl-pull"; 3208 info->regmap_pull = devm_regmap_init_mmio(&pdev->dev, 3209 base, 3210 &rockchip_regmap_config); 3211 } 3212 } 3213 3214 /* try to find the optional reference to the pmu syscon */ 3215 node = of_parse_phandle(np, "rockchip,pmu", 0); 3216 if (node) { 3217 info->regmap_pmu = syscon_node_to_regmap(node); 3218 if (IS_ERR(info->regmap_pmu)) 3219 return PTR_ERR(info->regmap_pmu); 3220 } 3221 3222 ret = rockchip_gpiolib_register(pdev, info); 3223 if (ret) 3224 return ret; 3225 3226 ret = rockchip_pinctrl_register(pdev, info); 3227 if (ret) { 3228 rockchip_gpiolib_unregister(pdev, info); 3229 return ret; 3230 } 3231 3232 platform_set_drvdata(pdev, info); 3233 3234 return 0; 3235 } 3236 3237 static struct rockchip_pin_bank rv1108_pin_banks[] = { 3238 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, 3239 IOMUX_SOURCE_PMU, 3240 IOMUX_SOURCE_PMU, 3241 IOMUX_SOURCE_PMU), 3242 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0), 3243 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0), 3244 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0), 3245 }; 3246 3247 static struct rockchip_pin_ctrl rv1108_pin_ctrl = { 3248 .pin_banks = rv1108_pin_banks, 3249 .nr_banks = ARRAY_SIZE(rv1108_pin_banks), 3250 .label = "RV1108-GPIO", 3251 .type = RV1108, 3252 .grf_mux_offset = 0x10, 3253 .pmu_mux_offset = 0x0, 3254 .iomux_recalced = rv1108_mux_recalced_data, 3255 .niomux_recalced = ARRAY_SIZE(rv1108_mux_recalced_data), 3256 .pull_calc_reg = rv1108_calc_pull_reg_and_bit, 3257 .drv_calc_reg = rv1108_calc_drv_reg_and_bit, 3258 .schmitt_calc_reg = rv1108_calc_schmitt_reg_and_bit, 3259 }; 3260 3261 static struct rockchip_pin_bank rk2928_pin_banks[] = { 3262 PIN_BANK(0, 32, "gpio0"), 3263 PIN_BANK(1, 32, "gpio1"), 3264 PIN_BANK(2, 32, "gpio2"), 3265 PIN_BANK(3, 32, "gpio3"), 3266 }; 3267 3268 static struct rockchip_pin_ctrl rk2928_pin_ctrl = { 3269 .pin_banks = rk2928_pin_banks, 3270 .nr_banks = ARRAY_SIZE(rk2928_pin_banks), 3271 .label = "RK2928-GPIO", 3272 .type = RK2928, 3273 .grf_mux_offset = 0xa8, 3274 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 3275 }; 3276 3277 static struct rockchip_pin_bank rk3036_pin_banks[] = { 3278 PIN_BANK(0, 32, "gpio0"), 3279 PIN_BANK(1, 32, "gpio1"), 3280 PIN_BANK(2, 32, "gpio2"), 3281 }; 3282 3283 static struct rockchip_pin_ctrl rk3036_pin_ctrl = { 3284 .pin_banks = rk3036_pin_banks, 3285 .nr_banks = ARRAY_SIZE(rk3036_pin_banks), 3286 .label = "RK3036-GPIO", 3287 .type = RK2928, 3288 .grf_mux_offset = 0xa8, 3289 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 3290 }; 3291 3292 static struct rockchip_pin_bank rk3066a_pin_banks[] = { 3293 PIN_BANK(0, 32, "gpio0"), 3294 PIN_BANK(1, 32, "gpio1"), 3295 PIN_BANK(2, 32, "gpio2"), 3296 PIN_BANK(3, 32, "gpio3"), 3297 PIN_BANK(4, 32, "gpio4"), 3298 PIN_BANK(6, 16, "gpio6"), 3299 }; 3300 3301 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = { 3302 .pin_banks = rk3066a_pin_banks, 3303 .nr_banks = ARRAY_SIZE(rk3066a_pin_banks), 3304 .label = "RK3066a-GPIO", 3305 .type = RK2928, 3306 .grf_mux_offset = 0xa8, 3307 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 3308 }; 3309 3310 static struct rockchip_pin_bank rk3066b_pin_banks[] = { 3311 PIN_BANK(0, 32, "gpio0"), 3312 PIN_BANK(1, 32, "gpio1"), 3313 PIN_BANK(2, 32, "gpio2"), 3314 PIN_BANK(3, 32, "gpio3"), 3315 }; 3316 3317 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = { 3318 .pin_banks = rk3066b_pin_banks, 3319 .nr_banks = ARRAY_SIZE(rk3066b_pin_banks), 3320 .label = "RK3066b-GPIO", 3321 .type = RK3066B, 3322 .grf_mux_offset = 0x60, 3323 }; 3324 3325 static struct rockchip_pin_bank rk3128_pin_banks[] = { 3326 PIN_BANK(0, 32, "gpio0"), 3327 PIN_BANK(1, 32, "gpio1"), 3328 PIN_BANK(2, 32, "gpio2"), 3329 PIN_BANK(3, 32, "gpio3"), 3330 }; 3331 3332 static struct rockchip_pin_ctrl rk3128_pin_ctrl = { 3333 .pin_banks = rk3128_pin_banks, 3334 .nr_banks = ARRAY_SIZE(rk3128_pin_banks), 3335 .label = "RK3128-GPIO", 3336 .type = RK3128, 3337 .grf_mux_offset = 0xa8, 3338 .iomux_recalced = rk3128_mux_recalced_data, 3339 .niomux_recalced = ARRAY_SIZE(rk3128_mux_recalced_data), 3340 .iomux_routes = rk3128_mux_route_data, 3341 .niomux_routes = ARRAY_SIZE(rk3128_mux_route_data), 3342 .pull_calc_reg = rk3128_calc_pull_reg_and_bit, 3343 }; 3344 3345 static struct rockchip_pin_bank rk3188_pin_banks[] = { 3346 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0), 3347 PIN_BANK(1, 32, "gpio1"), 3348 PIN_BANK(2, 32, "gpio2"), 3349 PIN_BANK(3, 32, "gpio3"), 3350 }; 3351 3352 static struct rockchip_pin_ctrl rk3188_pin_ctrl = { 3353 .pin_banks = rk3188_pin_banks, 3354 .nr_banks = ARRAY_SIZE(rk3188_pin_banks), 3355 .label = "RK3188-GPIO", 3356 .type = RK3188, 3357 .grf_mux_offset = 0x60, 3358 .pull_calc_reg = rk3188_calc_pull_reg_and_bit, 3359 }; 3360 3361 static struct rockchip_pin_bank rk3228_pin_banks[] = { 3362 PIN_BANK(0, 32, "gpio0"), 3363 PIN_BANK(1, 32, "gpio1"), 3364 PIN_BANK(2, 32, "gpio2"), 3365 PIN_BANK(3, 32, "gpio3"), 3366 }; 3367 3368 static struct rockchip_pin_ctrl rk3228_pin_ctrl = { 3369 .pin_banks = rk3228_pin_banks, 3370 .nr_banks = ARRAY_SIZE(rk3228_pin_banks), 3371 .label = "RK3228-GPIO", 3372 .type = RK3288, 3373 .grf_mux_offset = 0x0, 3374 .iomux_routes = rk3228_mux_route_data, 3375 .niomux_routes = ARRAY_SIZE(rk3228_mux_route_data), 3376 .pull_calc_reg = rk3228_calc_pull_reg_and_bit, 3377 .drv_calc_reg = rk3228_calc_drv_reg_and_bit, 3378 }; 3379 3380 static struct rockchip_pin_bank rk3288_pin_banks[] = { 3381 PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU, 3382 IOMUX_SOURCE_PMU, 3383 IOMUX_SOURCE_PMU, 3384 IOMUX_UNROUTED 3385 ), 3386 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED, 3387 IOMUX_UNROUTED, 3388 IOMUX_UNROUTED, 3389 0 3390 ), 3391 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED), 3392 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT), 3393 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT, 3394 IOMUX_WIDTH_4BIT, 3395 0, 3396 0 3397 ), 3398 PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED, 3399 0, 3400 0, 3401 IOMUX_UNROUTED 3402 ), 3403 PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED), 3404 PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0, 3405 0, 3406 IOMUX_WIDTH_4BIT, 3407 IOMUX_UNROUTED 3408 ), 3409 PIN_BANK(8, 16, "gpio8"), 3410 }; 3411 3412 static struct rockchip_pin_ctrl rk3288_pin_ctrl = { 3413 .pin_banks = rk3288_pin_banks, 3414 .nr_banks = ARRAY_SIZE(rk3288_pin_banks), 3415 .label = "RK3288-GPIO", 3416 .type = RK3288, 3417 .grf_mux_offset = 0x0, 3418 .pmu_mux_offset = 0x84, 3419 .iomux_routes = rk3288_mux_route_data, 3420 .niomux_routes = ARRAY_SIZE(rk3288_mux_route_data), 3421 .pull_calc_reg = rk3288_calc_pull_reg_and_bit, 3422 .drv_calc_reg = rk3288_calc_drv_reg_and_bit, 3423 }; 3424 3425 static struct rockchip_pin_bank rk3328_pin_banks[] = { 3426 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0), 3427 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0), 3428 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 3429 IOMUX_WIDTH_3BIT, 3430 IOMUX_WIDTH_3BIT, 3431 0), 3432 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 3433 IOMUX_WIDTH_3BIT, 3434 IOMUX_WIDTH_3BIT, 3435 0, 3436 0), 3437 }; 3438 3439 static struct rockchip_pin_ctrl rk3328_pin_ctrl = { 3440 .pin_banks = rk3328_pin_banks, 3441 .nr_banks = ARRAY_SIZE(rk3328_pin_banks), 3442 .label = "RK3328-GPIO", 3443 .type = RK3288, 3444 .grf_mux_offset = 0x0, 3445 .iomux_recalced = rk3328_mux_recalced_data, 3446 .niomux_recalced = ARRAY_SIZE(rk3328_mux_recalced_data), 3447 .iomux_routes = rk3328_mux_route_data, 3448 .niomux_routes = ARRAY_SIZE(rk3328_mux_route_data), 3449 .pull_calc_reg = rk3228_calc_pull_reg_and_bit, 3450 .drv_calc_reg = rk3228_calc_drv_reg_and_bit, 3451 .schmitt_calc_reg = rk3328_calc_schmitt_reg_and_bit, 3452 }; 3453 3454 static struct rockchip_pin_bank rk3368_pin_banks[] = { 3455 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, 3456 IOMUX_SOURCE_PMU, 3457 IOMUX_SOURCE_PMU, 3458 IOMUX_SOURCE_PMU 3459 ), 3460 PIN_BANK(1, 32, "gpio1"), 3461 PIN_BANK(2, 32, "gpio2"), 3462 PIN_BANK(3, 32, "gpio3"), 3463 }; 3464 3465 static struct rockchip_pin_ctrl rk3368_pin_ctrl = { 3466 .pin_banks = rk3368_pin_banks, 3467 .nr_banks = ARRAY_SIZE(rk3368_pin_banks), 3468 .label = "RK3368-GPIO", 3469 .type = RK3368, 3470 .grf_mux_offset = 0x0, 3471 .pmu_mux_offset = 0x0, 3472 .pull_calc_reg = rk3368_calc_pull_reg_and_bit, 3473 .drv_calc_reg = rk3368_calc_drv_reg_and_bit, 3474 }; 3475 3476 static struct rockchip_pin_bank rk3399_pin_banks[] = { 3477 PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0", 3478 IOMUX_SOURCE_PMU, 3479 IOMUX_SOURCE_PMU, 3480 IOMUX_SOURCE_PMU, 3481 IOMUX_SOURCE_PMU, 3482 DRV_TYPE_IO_1V8_ONLY, 3483 DRV_TYPE_IO_1V8_ONLY, 3484 DRV_TYPE_IO_DEFAULT, 3485 DRV_TYPE_IO_DEFAULT, 3486 0x80, 3487 0x88, 3488 -1, 3489 -1, 3490 PULL_TYPE_IO_1V8_ONLY, 3491 PULL_TYPE_IO_1V8_ONLY, 3492 PULL_TYPE_IO_DEFAULT, 3493 PULL_TYPE_IO_DEFAULT 3494 ), 3495 PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU, 3496 IOMUX_SOURCE_PMU, 3497 IOMUX_SOURCE_PMU, 3498 IOMUX_SOURCE_PMU, 3499 DRV_TYPE_IO_1V8_OR_3V0, 3500 DRV_TYPE_IO_1V8_OR_3V0, 3501 DRV_TYPE_IO_1V8_OR_3V0, 3502 DRV_TYPE_IO_1V8_OR_3V0, 3503 0xa0, 3504 0xa8, 3505 0xb0, 3506 0xb8 3507 ), 3508 PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0, 3509 DRV_TYPE_IO_1V8_OR_3V0, 3510 DRV_TYPE_IO_1V8_ONLY, 3511 DRV_TYPE_IO_1V8_ONLY, 3512 PULL_TYPE_IO_DEFAULT, 3513 PULL_TYPE_IO_DEFAULT, 3514 PULL_TYPE_IO_1V8_ONLY, 3515 PULL_TYPE_IO_1V8_ONLY 3516 ), 3517 PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY, 3518 DRV_TYPE_IO_3V3_ONLY, 3519 DRV_TYPE_IO_3V3_ONLY, 3520 DRV_TYPE_IO_1V8_OR_3V0 3521 ), 3522 PIN_BANK_DRV_FLAGS(4, 32, "gpio4", DRV_TYPE_IO_1V8_OR_3V0, 3523 DRV_TYPE_IO_1V8_3V0_AUTO, 3524 DRV_TYPE_IO_1V8_OR_3V0, 3525 DRV_TYPE_IO_1V8_OR_3V0 3526 ), 3527 }; 3528 3529 static struct rockchip_pin_ctrl rk3399_pin_ctrl = { 3530 .pin_banks = rk3399_pin_banks, 3531 .nr_banks = ARRAY_SIZE(rk3399_pin_banks), 3532 .label = "RK3399-GPIO", 3533 .type = RK3399, 3534 .grf_mux_offset = 0xe000, 3535 .pmu_mux_offset = 0x0, 3536 .grf_drv_offset = 0xe100, 3537 .pmu_drv_offset = 0x80, 3538 .iomux_routes = rk3399_mux_route_data, 3539 .niomux_routes = ARRAY_SIZE(rk3399_mux_route_data), 3540 .pull_calc_reg = rk3399_calc_pull_reg_and_bit, 3541 .drv_calc_reg = rk3399_calc_drv_reg_and_bit, 3542 }; 3543 3544 static const struct of_device_id rockchip_pinctrl_dt_match[] = { 3545 { .compatible = "rockchip,rv1108-pinctrl", 3546 .data = &rv1108_pin_ctrl }, 3547 { .compatible = "rockchip,rk2928-pinctrl", 3548 .data = &rk2928_pin_ctrl }, 3549 { .compatible = "rockchip,rk3036-pinctrl", 3550 .data = &rk3036_pin_ctrl }, 3551 { .compatible = "rockchip,rk3066a-pinctrl", 3552 .data = &rk3066a_pin_ctrl }, 3553 { .compatible = "rockchip,rk3066b-pinctrl", 3554 .data = &rk3066b_pin_ctrl }, 3555 { .compatible = "rockchip,rk3128-pinctrl", 3556 .data = (void *)&rk3128_pin_ctrl }, 3557 { .compatible = "rockchip,rk3188-pinctrl", 3558 .data = &rk3188_pin_ctrl }, 3559 { .compatible = "rockchip,rk3228-pinctrl", 3560 .data = &rk3228_pin_ctrl }, 3561 { .compatible = "rockchip,rk3288-pinctrl", 3562 .data = &rk3288_pin_ctrl }, 3563 { .compatible = "rockchip,rk3328-pinctrl", 3564 .data = &rk3328_pin_ctrl }, 3565 { .compatible = "rockchip,rk3368-pinctrl", 3566 .data = &rk3368_pin_ctrl }, 3567 { .compatible = "rockchip,rk3399-pinctrl", 3568 .data = &rk3399_pin_ctrl }, 3569 {}, 3570 }; 3571 3572 static struct platform_driver rockchip_pinctrl_driver = { 3573 .probe = rockchip_pinctrl_probe, 3574 .driver = { 3575 .name = "rockchip-pinctrl", 3576 .pm = &rockchip_pinctrl_dev_pm_ops, 3577 .of_match_table = rockchip_pinctrl_dt_match, 3578 }, 3579 }; 3580 3581 static int __init rockchip_pinctrl_drv_register(void) 3582 { 3583 return platform_driver_register(&rockchip_pinctrl_driver); 3584 } 3585 postcore_initcall(rockchip_pinctrl_drv_register); 3586