1 /* 2 * Pinctrl driver for Rockchip SoCs 3 * 4 * Copyright (c) 2013 MundoReader S.L. 5 * Author: Heiko Stuebner <heiko@sntech.de> 6 * 7 * With some ideas taken from pinctrl-samsung: 8 * Copyright (c) 2012 Samsung Electronics Co., Ltd. 9 * http://www.samsung.com 10 * Copyright (c) 2012 Linaro Ltd 11 * http://www.linaro.org 12 * 13 * and pinctrl-at91: 14 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> 15 * 16 * This program is free software; you can redistribute it and/or modify 17 * it under the terms of the GNU General Public License version 2 as published 18 * by the Free Software Foundation. 19 * 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 */ 25 26 #include <linux/module.h> 27 #include <linux/platform_device.h> 28 #include <linux/io.h> 29 #include <linux/bitops.h> 30 #include <linux/gpio.h> 31 #include <linux/of_address.h> 32 #include <linux/of_irq.h> 33 #include <linux/pinctrl/machine.h> 34 #include <linux/pinctrl/pinconf.h> 35 #include <linux/pinctrl/pinctrl.h> 36 #include <linux/pinctrl/pinmux.h> 37 #include <linux/pinctrl/pinconf-generic.h> 38 #include <linux/irqchip/chained_irq.h> 39 #include <linux/clk.h> 40 #include <linux/regmap.h> 41 #include <linux/mfd/syscon.h> 42 #include <dt-bindings/pinctrl/rockchip.h> 43 44 #include "core.h" 45 #include "pinconf.h" 46 47 /* GPIO control registers */ 48 #define GPIO_SWPORT_DR 0x00 49 #define GPIO_SWPORT_DDR 0x04 50 #define GPIO_INTEN 0x30 51 #define GPIO_INTMASK 0x34 52 #define GPIO_INTTYPE_LEVEL 0x38 53 #define GPIO_INT_POLARITY 0x3c 54 #define GPIO_INT_STATUS 0x40 55 #define GPIO_INT_RAWSTATUS 0x44 56 #define GPIO_DEBOUNCE 0x48 57 #define GPIO_PORTS_EOI 0x4c 58 #define GPIO_EXT_PORT 0x50 59 #define GPIO_LS_SYNC 0x60 60 61 enum rockchip_pinctrl_type { 62 RK2928, 63 RK3066B, 64 RK3188, 65 RK3288, 66 }; 67 68 /** 69 * Encode variants of iomux registers into a type variable 70 */ 71 #define IOMUX_GPIO_ONLY BIT(0) 72 #define IOMUX_WIDTH_4BIT BIT(1) 73 #define IOMUX_SOURCE_PMU BIT(2) 74 #define IOMUX_UNROUTED BIT(3) 75 76 /** 77 * @type: iomux variant using IOMUX_* constants 78 * @offset: if initialized to -1 it will be autocalculated, by specifying 79 * an initial offset value the relevant source offset can be reset 80 * to a new value for autocalculating the following iomux registers. 81 */ 82 struct rockchip_iomux { 83 int type; 84 int offset; 85 }; 86 87 /** 88 * @reg_base: register base of the gpio bank 89 * @reg_pull: optional separate register for additional pull settings 90 * @clk: clock of the gpio bank 91 * @irq: interrupt of the gpio bank 92 * @pin_base: first pin number 93 * @nr_pins: number of pins in this bank 94 * @name: name of the bank 95 * @bank_num: number of the bank, to account for holes 96 * @iomux: array describing the 4 iomux sources of the bank 97 * @valid: are all necessary informations present 98 * @of_node: dt node of this bank 99 * @drvdata: common pinctrl basedata 100 * @domain: irqdomain of the gpio bank 101 * @gpio_chip: gpiolib chip 102 * @grange: gpio range 103 * @slock: spinlock for the gpio bank 104 */ 105 struct rockchip_pin_bank { 106 void __iomem *reg_base; 107 struct regmap *regmap_pull; 108 struct clk *clk; 109 int irq; 110 u32 pin_base; 111 u8 nr_pins; 112 char *name; 113 u8 bank_num; 114 struct rockchip_iomux iomux[4]; 115 bool valid; 116 struct device_node *of_node; 117 struct rockchip_pinctrl *drvdata; 118 struct irq_domain *domain; 119 struct gpio_chip gpio_chip; 120 struct pinctrl_gpio_range grange; 121 spinlock_t slock; 122 u32 toggle_edge_mode; 123 }; 124 125 #define PIN_BANK(id, pins, label) \ 126 { \ 127 .bank_num = id, \ 128 .nr_pins = pins, \ 129 .name = label, \ 130 .iomux = { \ 131 { .offset = -1 }, \ 132 { .offset = -1 }, \ 133 { .offset = -1 }, \ 134 { .offset = -1 }, \ 135 }, \ 136 } 137 138 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \ 139 { \ 140 .bank_num = id, \ 141 .nr_pins = pins, \ 142 .name = label, \ 143 .iomux = { \ 144 { .type = iom0, .offset = -1 }, \ 145 { .type = iom1, .offset = -1 }, \ 146 { .type = iom2, .offset = -1 }, \ 147 { .type = iom3, .offset = -1 }, \ 148 }, \ 149 } 150 151 /** 152 */ 153 struct rockchip_pin_ctrl { 154 struct rockchip_pin_bank *pin_banks; 155 u32 nr_banks; 156 u32 nr_pins; 157 char *label; 158 enum rockchip_pinctrl_type type; 159 int grf_mux_offset; 160 int pmu_mux_offset; 161 void (*pull_calc_reg)(struct rockchip_pin_bank *bank, 162 int pin_num, struct regmap **regmap, 163 int *reg, u8 *bit); 164 }; 165 166 struct rockchip_pin_config { 167 unsigned int func; 168 unsigned long *configs; 169 unsigned int nconfigs; 170 }; 171 172 /** 173 * struct rockchip_pin_group: represent group of pins of a pinmux function. 174 * @name: name of the pin group, used to lookup the group. 175 * @pins: the pins included in this group. 176 * @npins: number of pins included in this group. 177 * @func: the mux function number to be programmed when selected. 178 * @configs: the config values to be set for each pin 179 * @nconfigs: number of configs for each pin 180 */ 181 struct rockchip_pin_group { 182 const char *name; 183 unsigned int npins; 184 unsigned int *pins; 185 struct rockchip_pin_config *data; 186 }; 187 188 /** 189 * struct rockchip_pmx_func: represent a pin function. 190 * @name: name of the pin function, used to lookup the function. 191 * @groups: one or more names of pin groups that provide this function. 192 * @num_groups: number of groups included in @groups. 193 */ 194 struct rockchip_pmx_func { 195 const char *name; 196 const char **groups; 197 u8 ngroups; 198 }; 199 200 struct rockchip_pinctrl { 201 struct regmap *regmap_base; 202 int reg_size; 203 struct regmap *regmap_pull; 204 struct regmap *regmap_pmu; 205 struct device *dev; 206 struct rockchip_pin_ctrl *ctrl; 207 struct pinctrl_desc pctl; 208 struct pinctrl_dev *pctl_dev; 209 struct rockchip_pin_group *groups; 210 unsigned int ngroups; 211 struct rockchip_pmx_func *functions; 212 unsigned int nfunctions; 213 }; 214 215 static struct regmap_config rockchip_regmap_config = { 216 .reg_bits = 32, 217 .val_bits = 32, 218 .reg_stride = 4, 219 }; 220 221 static inline struct rockchip_pin_bank *gc_to_pin_bank(struct gpio_chip *gc) 222 { 223 return container_of(gc, struct rockchip_pin_bank, gpio_chip); 224 } 225 226 static const inline struct rockchip_pin_group *pinctrl_name_to_group( 227 const struct rockchip_pinctrl *info, 228 const char *name) 229 { 230 int i; 231 232 for (i = 0; i < info->ngroups; i++) { 233 if (!strcmp(info->groups[i].name, name)) 234 return &info->groups[i]; 235 } 236 237 return NULL; 238 } 239 240 /* 241 * given a pin number that is local to a pin controller, find out the pin bank 242 * and the register base of the pin bank. 243 */ 244 static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info, 245 unsigned pin) 246 { 247 struct rockchip_pin_bank *b = info->ctrl->pin_banks; 248 249 while (pin >= (b->pin_base + b->nr_pins)) 250 b++; 251 252 return b; 253 } 254 255 static struct rockchip_pin_bank *bank_num_to_bank( 256 struct rockchip_pinctrl *info, 257 unsigned num) 258 { 259 struct rockchip_pin_bank *b = info->ctrl->pin_banks; 260 int i; 261 262 for (i = 0; i < info->ctrl->nr_banks; i++, b++) { 263 if (b->bank_num == num) 264 return b; 265 } 266 267 return ERR_PTR(-EINVAL); 268 } 269 270 /* 271 * Pinctrl_ops handling 272 */ 273 274 static int rockchip_get_groups_count(struct pinctrl_dev *pctldev) 275 { 276 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 277 278 return info->ngroups; 279 } 280 281 static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev, 282 unsigned selector) 283 { 284 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 285 286 return info->groups[selector].name; 287 } 288 289 static int rockchip_get_group_pins(struct pinctrl_dev *pctldev, 290 unsigned selector, const unsigned **pins, 291 unsigned *npins) 292 { 293 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 294 295 if (selector >= info->ngroups) 296 return -EINVAL; 297 298 *pins = info->groups[selector].pins; 299 *npins = info->groups[selector].npins; 300 301 return 0; 302 } 303 304 static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev, 305 struct device_node *np, 306 struct pinctrl_map **map, unsigned *num_maps) 307 { 308 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 309 const struct rockchip_pin_group *grp; 310 struct pinctrl_map *new_map; 311 struct device_node *parent; 312 int map_num = 1; 313 int i; 314 315 /* 316 * first find the group of this node and check if we need to create 317 * config maps for pins 318 */ 319 grp = pinctrl_name_to_group(info, np->name); 320 if (!grp) { 321 dev_err(info->dev, "unable to find group for node %s\n", 322 np->name); 323 return -EINVAL; 324 } 325 326 map_num += grp->npins; 327 new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num, 328 GFP_KERNEL); 329 if (!new_map) 330 return -ENOMEM; 331 332 *map = new_map; 333 *num_maps = map_num; 334 335 /* create mux map */ 336 parent = of_get_parent(np); 337 if (!parent) { 338 devm_kfree(pctldev->dev, new_map); 339 return -EINVAL; 340 } 341 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP; 342 new_map[0].data.mux.function = parent->name; 343 new_map[0].data.mux.group = np->name; 344 of_node_put(parent); 345 346 /* create config map */ 347 new_map++; 348 for (i = 0; i < grp->npins; i++) { 349 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN; 350 new_map[i].data.configs.group_or_pin = 351 pin_get_name(pctldev, grp->pins[i]); 352 new_map[i].data.configs.configs = grp->data[i].configs; 353 new_map[i].data.configs.num_configs = grp->data[i].nconfigs; 354 } 355 356 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n", 357 (*map)->data.mux.function, (*map)->data.mux.group, map_num); 358 359 return 0; 360 } 361 362 static void rockchip_dt_free_map(struct pinctrl_dev *pctldev, 363 struct pinctrl_map *map, unsigned num_maps) 364 { 365 } 366 367 static const struct pinctrl_ops rockchip_pctrl_ops = { 368 .get_groups_count = rockchip_get_groups_count, 369 .get_group_name = rockchip_get_group_name, 370 .get_group_pins = rockchip_get_group_pins, 371 .dt_node_to_map = rockchip_dt_node_to_map, 372 .dt_free_map = rockchip_dt_free_map, 373 }; 374 375 /* 376 * Hardware access 377 */ 378 379 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) 380 { 381 struct rockchip_pinctrl *info = bank->drvdata; 382 int iomux_num = (pin / 8); 383 struct regmap *regmap; 384 unsigned int val; 385 int reg, ret, mask; 386 u8 bit; 387 388 if (iomux_num > 3) 389 return -EINVAL; 390 391 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { 392 dev_err(info->dev, "pin %d is unrouted\n", pin); 393 return -EINVAL; 394 } 395 396 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) 397 return RK_FUNC_GPIO; 398 399 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) 400 ? info->regmap_pmu : info->regmap_base; 401 402 /* get basic quadrupel of mux registers and the correct reg inside */ 403 mask = (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) ? 0xf : 0x3; 404 reg = bank->iomux[iomux_num].offset; 405 if (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) { 406 if ((pin % 8) >= 4) 407 reg += 0x4; 408 bit = (pin % 4) * 4; 409 } else { 410 bit = (pin % 8) * 2; 411 } 412 413 ret = regmap_read(regmap, reg, &val); 414 if (ret) 415 return ret; 416 417 return ((val >> bit) & mask); 418 } 419 420 /* 421 * Set a new mux function for a pin. 422 * 423 * The register is divided into the upper and lower 16 bit. When changing 424 * a value, the previous register value is not read and changed. Instead 425 * it seems the changed bits are marked in the upper 16 bit, while the 426 * changed value gets set in the same offset in the lower 16 bit. 427 * All pin settings seem to be 2 bit wide in both the upper and lower 428 * parts. 429 * @bank: pin bank to change 430 * @pin: pin to change 431 * @mux: new mux function to set 432 */ 433 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) 434 { 435 struct rockchip_pinctrl *info = bank->drvdata; 436 int iomux_num = (pin / 8); 437 struct regmap *regmap; 438 int reg, ret, mask; 439 unsigned long flags; 440 u8 bit; 441 u32 data, rmask; 442 443 if (iomux_num > 3) 444 return -EINVAL; 445 446 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { 447 dev_err(info->dev, "pin %d is unrouted\n", pin); 448 return -EINVAL; 449 } 450 451 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) { 452 if (mux != RK_FUNC_GPIO) { 453 dev_err(info->dev, 454 "pin %d only supports a gpio mux\n", pin); 455 return -ENOTSUPP; 456 } else { 457 return 0; 458 } 459 } 460 461 dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n", 462 bank->bank_num, pin, mux); 463 464 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) 465 ? info->regmap_pmu : info->regmap_base; 466 467 /* get basic quadrupel of mux registers and the correct reg inside */ 468 mask = (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) ? 0xf : 0x3; 469 reg = bank->iomux[iomux_num].offset; 470 if (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) { 471 if ((pin % 8) >= 4) 472 reg += 0x4; 473 bit = (pin % 4) * 4; 474 } else { 475 bit = (pin % 8) * 2; 476 } 477 478 spin_lock_irqsave(&bank->slock, flags); 479 480 data = (mask << (bit + 16)); 481 rmask = data | (data >> 16); 482 data |= (mux & mask) << bit; 483 ret = regmap_update_bits(regmap, reg, rmask, data); 484 485 spin_unlock_irqrestore(&bank->slock, flags); 486 487 return ret; 488 } 489 490 #define RK2928_PULL_OFFSET 0x118 491 #define RK2928_PULL_PINS_PER_REG 16 492 #define RK2928_PULL_BANK_STRIDE 8 493 494 static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 495 int pin_num, struct regmap **regmap, 496 int *reg, u8 *bit) 497 { 498 struct rockchip_pinctrl *info = bank->drvdata; 499 500 *regmap = info->regmap_base; 501 *reg = RK2928_PULL_OFFSET; 502 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; 503 *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4; 504 505 *bit = pin_num % RK2928_PULL_PINS_PER_REG; 506 }; 507 508 #define RK3188_PULL_OFFSET 0x164 509 #define RK3188_PULL_BITS_PER_PIN 2 510 #define RK3188_PULL_PINS_PER_REG 8 511 #define RK3188_PULL_BANK_STRIDE 16 512 #define RK3188_PULL_PMU_OFFSET 0x64 513 514 static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 515 int pin_num, struct regmap **regmap, 516 int *reg, u8 *bit) 517 { 518 struct rockchip_pinctrl *info = bank->drvdata; 519 520 /* The first 12 pins of the first bank are located elsewhere */ 521 if (bank->bank_num == 0 && pin_num < 12) { 522 *regmap = info->regmap_pmu ? info->regmap_pmu 523 : bank->regmap_pull; 524 *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0; 525 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 526 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 527 *bit *= RK3188_PULL_BITS_PER_PIN; 528 } else { 529 *regmap = info->regmap_pull ? info->regmap_pull 530 : info->regmap_base; 531 *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET; 532 533 /* correct the offset, as it is the 2nd pull register */ 534 *reg -= 4; 535 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 536 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 537 538 /* 539 * The bits in these registers have an inverse ordering 540 * with the lowest pin being in bits 15:14 and the highest 541 * pin in bits 1:0 542 */ 543 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG); 544 *bit *= RK3188_PULL_BITS_PER_PIN; 545 } 546 } 547 548 #define RK3288_PULL_OFFSET 0x140 549 static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 550 int pin_num, struct regmap **regmap, 551 int *reg, u8 *bit) 552 { 553 struct rockchip_pinctrl *info = bank->drvdata; 554 555 /* The first 24 pins of the first bank are located in PMU */ 556 if (bank->bank_num == 0) { 557 *regmap = info->regmap_pmu; 558 *reg = RK3188_PULL_PMU_OFFSET; 559 560 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 561 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 562 *bit *= RK3188_PULL_BITS_PER_PIN; 563 } else { 564 *regmap = info->regmap_base; 565 *reg = RK3288_PULL_OFFSET; 566 567 /* correct the offset, as we're starting with the 2nd bank */ 568 *reg -= 0x10; 569 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 570 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 571 572 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 573 *bit *= RK3188_PULL_BITS_PER_PIN; 574 } 575 } 576 577 #define RK3288_DRV_PMU_OFFSET 0x70 578 #define RK3288_DRV_GRF_OFFSET 0x1c0 579 #define RK3288_DRV_BITS_PER_PIN 2 580 #define RK3288_DRV_PINS_PER_REG 8 581 #define RK3288_DRV_BANK_STRIDE 16 582 static int rk3288_drv_list[] = { 2, 4, 8, 12 }; 583 584 static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 585 int pin_num, struct regmap **regmap, 586 int *reg, u8 *bit) 587 { 588 struct rockchip_pinctrl *info = bank->drvdata; 589 590 /* The first 24 pins of the first bank are located in PMU */ 591 if (bank->bank_num == 0) { 592 *regmap = info->regmap_pmu; 593 *reg = RK3288_DRV_PMU_OFFSET; 594 595 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 596 *bit = pin_num % RK3288_DRV_PINS_PER_REG; 597 *bit *= RK3288_DRV_BITS_PER_PIN; 598 } else { 599 *regmap = info->regmap_base; 600 *reg = RK3288_DRV_GRF_OFFSET; 601 602 /* correct the offset, as we're starting with the 2nd bank */ 603 *reg -= 0x10; 604 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 605 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 606 607 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 608 *bit *= RK3288_DRV_BITS_PER_PIN; 609 } 610 } 611 612 static int rk3288_get_drive(struct rockchip_pin_bank *bank, int pin_num) 613 { 614 struct regmap *regmap; 615 int reg, ret; 616 u32 data; 617 u8 bit; 618 619 rk3288_calc_drv_reg_and_bit(bank, pin_num, ®map, ®, &bit); 620 621 ret = regmap_read(regmap, reg, &data); 622 if (ret) 623 return ret; 624 625 data >>= bit; 626 data &= (1 << RK3288_DRV_BITS_PER_PIN) - 1; 627 628 return rk3288_drv_list[data]; 629 } 630 631 static int rk3288_set_drive(struct rockchip_pin_bank *bank, int pin_num, 632 int strength) 633 { 634 struct rockchip_pinctrl *info = bank->drvdata; 635 struct regmap *regmap; 636 unsigned long flags; 637 int reg, ret, i; 638 u32 data, rmask; 639 u8 bit; 640 641 rk3288_calc_drv_reg_and_bit(bank, pin_num, ®map, ®, &bit); 642 643 ret = -EINVAL; 644 for (i = 0; i < ARRAY_SIZE(rk3288_drv_list); i++) { 645 if (rk3288_drv_list[i] == strength) { 646 ret = i; 647 break; 648 } 649 } 650 651 if (ret < 0) { 652 dev_err(info->dev, "unsupported driver strength %d\n", 653 strength); 654 return ret; 655 } 656 657 spin_lock_irqsave(&bank->slock, flags); 658 659 /* enable the write to the equivalent lower bits */ 660 data = ((1 << RK3288_DRV_BITS_PER_PIN) - 1) << (bit + 16); 661 rmask = data | (data >> 16); 662 data |= (ret << bit); 663 664 ret = regmap_update_bits(regmap, reg, rmask, data); 665 spin_unlock_irqrestore(&bank->slock, flags); 666 667 return ret; 668 } 669 670 static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num) 671 { 672 struct rockchip_pinctrl *info = bank->drvdata; 673 struct rockchip_pin_ctrl *ctrl = info->ctrl; 674 struct regmap *regmap; 675 int reg, ret; 676 u8 bit; 677 u32 data; 678 679 /* rk3066b does support any pulls */ 680 if (ctrl->type == RK3066B) 681 return PIN_CONFIG_BIAS_DISABLE; 682 683 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); 684 685 ret = regmap_read(regmap, reg, &data); 686 if (ret) 687 return ret; 688 689 switch (ctrl->type) { 690 case RK2928: 691 return !(data & BIT(bit)) 692 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT 693 : PIN_CONFIG_BIAS_DISABLE; 694 case RK3188: 695 case RK3288: 696 data >>= bit; 697 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1; 698 699 switch (data) { 700 case 0: 701 return PIN_CONFIG_BIAS_DISABLE; 702 case 1: 703 return PIN_CONFIG_BIAS_PULL_UP; 704 case 2: 705 return PIN_CONFIG_BIAS_PULL_DOWN; 706 case 3: 707 return PIN_CONFIG_BIAS_BUS_HOLD; 708 } 709 710 dev_err(info->dev, "unknown pull setting\n"); 711 return -EIO; 712 default: 713 dev_err(info->dev, "unsupported pinctrl type\n"); 714 return -EINVAL; 715 }; 716 } 717 718 static int rockchip_set_pull(struct rockchip_pin_bank *bank, 719 int pin_num, int pull) 720 { 721 struct rockchip_pinctrl *info = bank->drvdata; 722 struct rockchip_pin_ctrl *ctrl = info->ctrl; 723 struct regmap *regmap; 724 int reg, ret; 725 unsigned long flags; 726 u8 bit; 727 u32 data, rmask; 728 729 dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n", 730 bank->bank_num, pin_num, pull); 731 732 /* rk3066b does support any pulls */ 733 if (ctrl->type == RK3066B) 734 return pull ? -EINVAL : 0; 735 736 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); 737 738 switch (ctrl->type) { 739 case RK2928: 740 spin_lock_irqsave(&bank->slock, flags); 741 742 data = BIT(bit + 16); 743 if (pull == PIN_CONFIG_BIAS_DISABLE) 744 data |= BIT(bit); 745 ret = regmap_write(regmap, reg, data); 746 747 spin_unlock_irqrestore(&bank->slock, flags); 748 break; 749 case RK3188: 750 case RK3288: 751 spin_lock_irqsave(&bank->slock, flags); 752 753 /* enable the write to the equivalent lower bits */ 754 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16); 755 rmask = data | (data >> 16); 756 757 switch (pull) { 758 case PIN_CONFIG_BIAS_DISABLE: 759 break; 760 case PIN_CONFIG_BIAS_PULL_UP: 761 data |= (1 << bit); 762 break; 763 case PIN_CONFIG_BIAS_PULL_DOWN: 764 data |= (2 << bit); 765 break; 766 case PIN_CONFIG_BIAS_BUS_HOLD: 767 data |= (3 << bit); 768 break; 769 default: 770 spin_unlock_irqrestore(&bank->slock, flags); 771 dev_err(info->dev, "unsupported pull setting %d\n", 772 pull); 773 return -EINVAL; 774 } 775 776 ret = regmap_update_bits(regmap, reg, rmask, data); 777 778 spin_unlock_irqrestore(&bank->slock, flags); 779 break; 780 default: 781 dev_err(info->dev, "unsupported pinctrl type\n"); 782 return -EINVAL; 783 } 784 785 return ret; 786 } 787 788 /* 789 * Pinmux_ops handling 790 */ 791 792 static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev) 793 { 794 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 795 796 return info->nfunctions; 797 } 798 799 static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev, 800 unsigned selector) 801 { 802 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 803 804 return info->functions[selector].name; 805 } 806 807 static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev, 808 unsigned selector, const char * const **groups, 809 unsigned * const num_groups) 810 { 811 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 812 813 *groups = info->functions[selector].groups; 814 *num_groups = info->functions[selector].ngroups; 815 816 return 0; 817 } 818 819 static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector, 820 unsigned group) 821 { 822 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 823 const unsigned int *pins = info->groups[group].pins; 824 const struct rockchip_pin_config *data = info->groups[group].data; 825 struct rockchip_pin_bank *bank; 826 int cnt, ret = 0; 827 828 dev_dbg(info->dev, "enable function %s group %s\n", 829 info->functions[selector].name, info->groups[group].name); 830 831 /* 832 * for each pin in the pin group selected, program the correspoding pin 833 * pin function number in the config register. 834 */ 835 for (cnt = 0; cnt < info->groups[group].npins; cnt++) { 836 bank = pin_to_bank(info, pins[cnt]); 837 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 838 data[cnt].func); 839 if (ret) 840 break; 841 } 842 843 if (ret) { 844 /* revert the already done pin settings */ 845 for (cnt--; cnt >= 0; cnt--) 846 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0); 847 848 return ret; 849 } 850 851 return 0; 852 } 853 854 /* 855 * The calls to gpio_direction_output() and gpio_direction_input() 856 * leads to this function call (via the pinctrl_gpio_direction_{input|output}() 857 * function called from the gpiolib interface). 858 */ 859 static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, 860 struct pinctrl_gpio_range *range, 861 unsigned offset, bool input) 862 { 863 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 864 struct rockchip_pin_bank *bank; 865 struct gpio_chip *chip; 866 int pin, ret; 867 u32 data; 868 869 chip = range->gc; 870 bank = gc_to_pin_bank(chip); 871 pin = offset - chip->base; 872 873 dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n", 874 offset, range->name, pin, input ? "input" : "output"); 875 876 ret = rockchip_set_mux(bank, pin, RK_FUNC_GPIO); 877 if (ret < 0) 878 return ret; 879 880 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); 881 /* set bit to 1 for output, 0 for input */ 882 if (!input) 883 data |= BIT(pin); 884 else 885 data &= ~BIT(pin); 886 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR); 887 888 return 0; 889 } 890 891 static const struct pinmux_ops rockchip_pmx_ops = { 892 .get_functions_count = rockchip_pmx_get_funcs_count, 893 .get_function_name = rockchip_pmx_get_func_name, 894 .get_function_groups = rockchip_pmx_get_groups, 895 .set_mux = rockchip_pmx_set, 896 .gpio_set_direction = rockchip_pmx_gpio_set_direction, 897 }; 898 899 /* 900 * Pinconf_ops handling 901 */ 902 903 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl, 904 enum pin_config_param pull) 905 { 906 switch (ctrl->type) { 907 case RK2928: 908 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT || 909 pull == PIN_CONFIG_BIAS_DISABLE); 910 case RK3066B: 911 return pull ? false : true; 912 case RK3188: 913 case RK3288: 914 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT); 915 } 916 917 return false; 918 } 919 920 static int rockchip_gpio_direction_output(struct gpio_chip *gc, 921 unsigned offset, int value); 922 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset); 923 924 /* set the pin config settings for a specified pin */ 925 static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 926 unsigned long *configs, unsigned num_configs) 927 { 928 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 929 struct rockchip_pin_bank *bank = pin_to_bank(info, pin); 930 enum pin_config_param param; 931 u16 arg; 932 int i; 933 int rc; 934 935 for (i = 0; i < num_configs; i++) { 936 param = pinconf_to_config_param(configs[i]); 937 arg = pinconf_to_config_argument(configs[i]); 938 939 switch (param) { 940 case PIN_CONFIG_BIAS_DISABLE: 941 rc = rockchip_set_pull(bank, pin - bank->pin_base, 942 param); 943 if (rc) 944 return rc; 945 break; 946 case PIN_CONFIG_BIAS_PULL_UP: 947 case PIN_CONFIG_BIAS_PULL_DOWN: 948 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: 949 case PIN_CONFIG_BIAS_BUS_HOLD: 950 if (!rockchip_pinconf_pull_valid(info->ctrl, param)) 951 return -ENOTSUPP; 952 953 if (!arg) 954 return -EINVAL; 955 956 rc = rockchip_set_pull(bank, pin - bank->pin_base, 957 param); 958 if (rc) 959 return rc; 960 break; 961 case PIN_CONFIG_OUTPUT: 962 rc = rockchip_gpio_direction_output(&bank->gpio_chip, 963 pin - bank->pin_base, 964 arg); 965 if (rc) 966 return rc; 967 break; 968 case PIN_CONFIG_DRIVE_STRENGTH: 969 /* rk3288 is the first with per-pin drive-strength */ 970 if (info->ctrl->type != RK3288) 971 return -ENOTSUPP; 972 973 rc = rk3288_set_drive(bank, pin - bank->pin_base, arg); 974 if (rc < 0) 975 return rc; 976 break; 977 default: 978 return -ENOTSUPP; 979 break; 980 } 981 } /* for each config */ 982 983 return 0; 984 } 985 986 /* get the pin config settings for a specified pin */ 987 static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, 988 unsigned long *config) 989 { 990 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 991 struct rockchip_pin_bank *bank = pin_to_bank(info, pin); 992 enum pin_config_param param = pinconf_to_config_param(*config); 993 u16 arg; 994 int rc; 995 996 switch (param) { 997 case PIN_CONFIG_BIAS_DISABLE: 998 if (rockchip_get_pull(bank, pin - bank->pin_base) != param) 999 return -EINVAL; 1000 1001 arg = 0; 1002 break; 1003 case PIN_CONFIG_BIAS_PULL_UP: 1004 case PIN_CONFIG_BIAS_PULL_DOWN: 1005 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: 1006 case PIN_CONFIG_BIAS_BUS_HOLD: 1007 if (!rockchip_pinconf_pull_valid(info->ctrl, param)) 1008 return -ENOTSUPP; 1009 1010 if (rockchip_get_pull(bank, pin - bank->pin_base) != param) 1011 return -EINVAL; 1012 1013 arg = 1; 1014 break; 1015 case PIN_CONFIG_OUTPUT: 1016 rc = rockchip_get_mux(bank, pin - bank->pin_base); 1017 if (rc != RK_FUNC_GPIO) 1018 return -EINVAL; 1019 1020 rc = rockchip_gpio_get(&bank->gpio_chip, pin - bank->pin_base); 1021 if (rc < 0) 1022 return rc; 1023 1024 arg = rc ? 1 : 0; 1025 break; 1026 case PIN_CONFIG_DRIVE_STRENGTH: 1027 /* rk3288 is the first with per-pin drive-strength */ 1028 if (info->ctrl->type != RK3288) 1029 return -ENOTSUPP; 1030 1031 rc = rk3288_get_drive(bank, pin - bank->pin_base); 1032 if (rc < 0) 1033 return rc; 1034 1035 arg = rc; 1036 break; 1037 default: 1038 return -ENOTSUPP; 1039 break; 1040 } 1041 1042 *config = pinconf_to_config_packed(param, arg); 1043 1044 return 0; 1045 } 1046 1047 static const struct pinconf_ops rockchip_pinconf_ops = { 1048 .pin_config_get = rockchip_pinconf_get, 1049 .pin_config_set = rockchip_pinconf_set, 1050 .is_generic = true, 1051 }; 1052 1053 static const struct of_device_id rockchip_bank_match[] = { 1054 { .compatible = "rockchip,gpio-bank" }, 1055 { .compatible = "rockchip,rk3188-gpio-bank0" }, 1056 {}, 1057 }; 1058 1059 static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info, 1060 struct device_node *np) 1061 { 1062 struct device_node *child; 1063 1064 for_each_child_of_node(np, child) { 1065 if (of_match_node(rockchip_bank_match, child)) 1066 continue; 1067 1068 info->nfunctions++; 1069 info->ngroups += of_get_child_count(child); 1070 } 1071 } 1072 1073 static int rockchip_pinctrl_parse_groups(struct device_node *np, 1074 struct rockchip_pin_group *grp, 1075 struct rockchip_pinctrl *info, 1076 u32 index) 1077 { 1078 struct rockchip_pin_bank *bank; 1079 int size; 1080 const __be32 *list; 1081 int num; 1082 int i, j; 1083 int ret; 1084 1085 dev_dbg(info->dev, "group(%d): %s\n", index, np->name); 1086 1087 /* Initialise group */ 1088 grp->name = np->name; 1089 1090 /* 1091 * the binding format is rockchip,pins = <bank pin mux CONFIG>, 1092 * do sanity check and calculate pins number 1093 */ 1094 list = of_get_property(np, "rockchip,pins", &size); 1095 /* we do not check return since it's safe node passed down */ 1096 size /= sizeof(*list); 1097 if (!size || size % 4) { 1098 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n"); 1099 return -EINVAL; 1100 } 1101 1102 grp->npins = size / 4; 1103 1104 grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int), 1105 GFP_KERNEL); 1106 grp->data = devm_kzalloc(info->dev, grp->npins * 1107 sizeof(struct rockchip_pin_config), 1108 GFP_KERNEL); 1109 if (!grp->pins || !grp->data) 1110 return -ENOMEM; 1111 1112 for (i = 0, j = 0; i < size; i += 4, j++) { 1113 const __be32 *phandle; 1114 struct device_node *np_config; 1115 1116 num = be32_to_cpu(*list++); 1117 bank = bank_num_to_bank(info, num); 1118 if (IS_ERR(bank)) 1119 return PTR_ERR(bank); 1120 1121 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++); 1122 grp->data[j].func = be32_to_cpu(*list++); 1123 1124 phandle = list++; 1125 if (!phandle) 1126 return -EINVAL; 1127 1128 np_config = of_find_node_by_phandle(be32_to_cpup(phandle)); 1129 ret = pinconf_generic_parse_dt_config(np_config, 1130 &grp->data[j].configs, &grp->data[j].nconfigs); 1131 if (ret) 1132 return ret; 1133 } 1134 1135 return 0; 1136 } 1137 1138 static int rockchip_pinctrl_parse_functions(struct device_node *np, 1139 struct rockchip_pinctrl *info, 1140 u32 index) 1141 { 1142 struct device_node *child; 1143 struct rockchip_pmx_func *func; 1144 struct rockchip_pin_group *grp; 1145 int ret; 1146 static u32 grp_index; 1147 u32 i = 0; 1148 1149 dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name); 1150 1151 func = &info->functions[index]; 1152 1153 /* Initialise function */ 1154 func->name = np->name; 1155 func->ngroups = of_get_child_count(np); 1156 if (func->ngroups <= 0) 1157 return 0; 1158 1159 func->groups = devm_kzalloc(info->dev, 1160 func->ngroups * sizeof(char *), GFP_KERNEL); 1161 if (!func->groups) 1162 return -ENOMEM; 1163 1164 for_each_child_of_node(np, child) { 1165 func->groups[i] = child->name; 1166 grp = &info->groups[grp_index++]; 1167 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++); 1168 if (ret) 1169 return ret; 1170 } 1171 1172 return 0; 1173 } 1174 1175 static int rockchip_pinctrl_parse_dt(struct platform_device *pdev, 1176 struct rockchip_pinctrl *info) 1177 { 1178 struct device *dev = &pdev->dev; 1179 struct device_node *np = dev->of_node; 1180 struct device_node *child; 1181 int ret; 1182 int i; 1183 1184 rockchip_pinctrl_child_count(info, np); 1185 1186 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions); 1187 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups); 1188 1189 info->functions = devm_kzalloc(dev, info->nfunctions * 1190 sizeof(struct rockchip_pmx_func), 1191 GFP_KERNEL); 1192 if (!info->functions) { 1193 dev_err(dev, "failed to allocate memory for function list\n"); 1194 return -EINVAL; 1195 } 1196 1197 info->groups = devm_kzalloc(dev, info->ngroups * 1198 sizeof(struct rockchip_pin_group), 1199 GFP_KERNEL); 1200 if (!info->groups) { 1201 dev_err(dev, "failed allocate memory for ping group list\n"); 1202 return -EINVAL; 1203 } 1204 1205 i = 0; 1206 1207 for_each_child_of_node(np, child) { 1208 if (of_match_node(rockchip_bank_match, child)) 1209 continue; 1210 1211 ret = rockchip_pinctrl_parse_functions(child, info, i++); 1212 if (ret) { 1213 dev_err(&pdev->dev, "failed to parse function\n"); 1214 return ret; 1215 } 1216 } 1217 1218 return 0; 1219 } 1220 1221 static int rockchip_pinctrl_register(struct platform_device *pdev, 1222 struct rockchip_pinctrl *info) 1223 { 1224 struct pinctrl_desc *ctrldesc = &info->pctl; 1225 struct pinctrl_pin_desc *pindesc, *pdesc; 1226 struct rockchip_pin_bank *pin_bank; 1227 int pin, bank, ret; 1228 int k; 1229 1230 ctrldesc->name = "rockchip-pinctrl"; 1231 ctrldesc->owner = THIS_MODULE; 1232 ctrldesc->pctlops = &rockchip_pctrl_ops; 1233 ctrldesc->pmxops = &rockchip_pmx_ops; 1234 ctrldesc->confops = &rockchip_pinconf_ops; 1235 1236 pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) * 1237 info->ctrl->nr_pins, GFP_KERNEL); 1238 if (!pindesc) { 1239 dev_err(&pdev->dev, "mem alloc for pin descriptors failed\n"); 1240 return -ENOMEM; 1241 } 1242 ctrldesc->pins = pindesc; 1243 ctrldesc->npins = info->ctrl->nr_pins; 1244 1245 pdesc = pindesc; 1246 for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) { 1247 pin_bank = &info->ctrl->pin_banks[bank]; 1248 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) { 1249 pdesc->number = k; 1250 pdesc->name = kasprintf(GFP_KERNEL, "%s-%d", 1251 pin_bank->name, pin); 1252 pdesc++; 1253 } 1254 } 1255 1256 info->pctl_dev = pinctrl_register(ctrldesc, &pdev->dev, info); 1257 if (!info->pctl_dev) { 1258 dev_err(&pdev->dev, "could not register pinctrl driver\n"); 1259 return -EINVAL; 1260 } 1261 1262 for (bank = 0; bank < info->ctrl->nr_banks; ++bank) { 1263 pin_bank = &info->ctrl->pin_banks[bank]; 1264 pin_bank->grange.name = pin_bank->name; 1265 pin_bank->grange.id = bank; 1266 pin_bank->grange.pin_base = pin_bank->pin_base; 1267 pin_bank->grange.base = pin_bank->gpio_chip.base; 1268 pin_bank->grange.npins = pin_bank->gpio_chip.ngpio; 1269 pin_bank->grange.gc = &pin_bank->gpio_chip; 1270 pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange); 1271 } 1272 1273 ret = rockchip_pinctrl_parse_dt(pdev, info); 1274 if (ret) { 1275 pinctrl_unregister(info->pctl_dev); 1276 return ret; 1277 } 1278 1279 return 0; 1280 } 1281 1282 /* 1283 * GPIO handling 1284 */ 1285 1286 static int rockchip_gpio_request(struct gpio_chip *chip, unsigned offset) 1287 { 1288 return pinctrl_request_gpio(chip->base + offset); 1289 } 1290 1291 static void rockchip_gpio_free(struct gpio_chip *chip, unsigned offset) 1292 { 1293 pinctrl_free_gpio(chip->base + offset); 1294 } 1295 1296 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value) 1297 { 1298 struct rockchip_pin_bank *bank = gc_to_pin_bank(gc); 1299 void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR; 1300 unsigned long flags; 1301 u32 data; 1302 1303 spin_lock_irqsave(&bank->slock, flags); 1304 1305 data = readl(reg); 1306 data &= ~BIT(offset); 1307 if (value) 1308 data |= BIT(offset); 1309 writel(data, reg); 1310 1311 spin_unlock_irqrestore(&bank->slock, flags); 1312 } 1313 1314 /* 1315 * Returns the level of the pin for input direction and setting of the DR 1316 * register for output gpios. 1317 */ 1318 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset) 1319 { 1320 struct rockchip_pin_bank *bank = gc_to_pin_bank(gc); 1321 u32 data; 1322 1323 data = readl(bank->reg_base + GPIO_EXT_PORT); 1324 data >>= offset; 1325 data &= 1; 1326 return data; 1327 } 1328 1329 /* 1330 * gpiolib gpio_direction_input callback function. The setting of the pin 1331 * mux function as 'gpio input' will be handled by the pinctrl susbsystem 1332 * interface. 1333 */ 1334 static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset) 1335 { 1336 return pinctrl_gpio_direction_input(gc->base + offset); 1337 } 1338 1339 /* 1340 * gpiolib gpio_direction_output callback function. The setting of the pin 1341 * mux function as 'gpio output' will be handled by the pinctrl susbsystem 1342 * interface. 1343 */ 1344 static int rockchip_gpio_direction_output(struct gpio_chip *gc, 1345 unsigned offset, int value) 1346 { 1347 rockchip_gpio_set(gc, offset, value); 1348 return pinctrl_gpio_direction_output(gc->base + offset); 1349 } 1350 1351 /* 1352 * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin 1353 * and a virtual IRQ, if not already present. 1354 */ 1355 static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset) 1356 { 1357 struct rockchip_pin_bank *bank = gc_to_pin_bank(gc); 1358 unsigned int virq; 1359 1360 if (!bank->domain) 1361 return -ENXIO; 1362 1363 virq = irq_create_mapping(bank->domain, offset); 1364 1365 return (virq) ? : -ENXIO; 1366 } 1367 1368 static const struct gpio_chip rockchip_gpiolib_chip = { 1369 .request = rockchip_gpio_request, 1370 .free = rockchip_gpio_free, 1371 .set = rockchip_gpio_set, 1372 .get = rockchip_gpio_get, 1373 .direction_input = rockchip_gpio_direction_input, 1374 .direction_output = rockchip_gpio_direction_output, 1375 .to_irq = rockchip_gpio_to_irq, 1376 .owner = THIS_MODULE, 1377 }; 1378 1379 /* 1380 * Interrupt handling 1381 */ 1382 1383 static void rockchip_irq_demux(unsigned int irq, struct irq_desc *desc) 1384 { 1385 struct irq_chip *chip = irq_get_chip(irq); 1386 struct rockchip_pin_bank *bank = irq_get_handler_data(irq); 1387 u32 polarity = 0, data = 0; 1388 u32 pend; 1389 bool edge_changed = false; 1390 1391 dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name); 1392 1393 chained_irq_enter(chip, desc); 1394 1395 pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS); 1396 1397 if (bank->toggle_edge_mode) { 1398 polarity = readl_relaxed(bank->reg_base + 1399 GPIO_INT_POLARITY); 1400 data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT); 1401 } 1402 1403 while (pend) { 1404 unsigned int virq; 1405 1406 irq = __ffs(pend); 1407 pend &= ~BIT(irq); 1408 virq = irq_linear_revmap(bank->domain, irq); 1409 1410 if (!virq) { 1411 dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq); 1412 continue; 1413 } 1414 1415 dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq); 1416 1417 /* 1418 * Triggering IRQ on both rising and falling edge 1419 * needs manual intervention. 1420 */ 1421 if (bank->toggle_edge_mode & BIT(irq)) { 1422 if (data & BIT(irq)) 1423 polarity &= ~BIT(irq); 1424 else 1425 polarity |= BIT(irq); 1426 1427 edge_changed = true; 1428 } 1429 1430 generic_handle_irq(virq); 1431 } 1432 1433 if (bank->toggle_edge_mode && edge_changed) { 1434 /* Interrupt params should only be set with ints disabled */ 1435 data = readl_relaxed(bank->reg_base + GPIO_INTEN); 1436 writel_relaxed(0, bank->reg_base + GPIO_INTEN); 1437 writel(polarity, bank->reg_base + GPIO_INT_POLARITY); 1438 writel(data, bank->reg_base + GPIO_INTEN); 1439 } 1440 1441 chained_irq_exit(chip, desc); 1442 } 1443 1444 static int rockchip_irq_set_type(struct irq_data *d, unsigned int type) 1445 { 1446 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 1447 struct rockchip_pin_bank *bank = gc->private; 1448 u32 mask = BIT(d->hwirq); 1449 u32 polarity; 1450 u32 level; 1451 u32 data; 1452 int ret; 1453 1454 /* make sure the pin is configured as gpio input */ 1455 ret = rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO); 1456 if (ret < 0) 1457 return ret; 1458 1459 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); 1460 data &= ~mask; 1461 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR); 1462 1463 if (type & IRQ_TYPE_EDGE_BOTH) 1464 __irq_set_handler_locked(d->irq, handle_edge_irq); 1465 else 1466 __irq_set_handler_locked(d->irq, handle_level_irq); 1467 1468 irq_gc_lock(gc); 1469 1470 level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL); 1471 polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY); 1472 1473 switch (type) { 1474 case IRQ_TYPE_EDGE_BOTH: 1475 bank->toggle_edge_mode |= mask; 1476 level |= mask; 1477 1478 /* 1479 * Determine gpio state. If 1 next interrupt should be falling 1480 * otherwise rising. 1481 */ 1482 data = readl(bank->reg_base + GPIO_EXT_PORT); 1483 if (data & mask) 1484 polarity &= ~mask; 1485 else 1486 polarity |= mask; 1487 break; 1488 case IRQ_TYPE_EDGE_RISING: 1489 bank->toggle_edge_mode &= ~mask; 1490 level |= mask; 1491 polarity |= mask; 1492 break; 1493 case IRQ_TYPE_EDGE_FALLING: 1494 bank->toggle_edge_mode &= ~mask; 1495 level |= mask; 1496 polarity &= ~mask; 1497 break; 1498 case IRQ_TYPE_LEVEL_HIGH: 1499 bank->toggle_edge_mode &= ~mask; 1500 level &= ~mask; 1501 polarity |= mask; 1502 break; 1503 case IRQ_TYPE_LEVEL_LOW: 1504 bank->toggle_edge_mode &= ~mask; 1505 level &= ~mask; 1506 polarity &= ~mask; 1507 break; 1508 default: 1509 irq_gc_unlock(gc); 1510 return -EINVAL; 1511 } 1512 1513 writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL); 1514 writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY); 1515 1516 irq_gc_unlock(gc); 1517 1518 return 0; 1519 } 1520 1521 static int rockchip_interrupts_register(struct platform_device *pdev, 1522 struct rockchip_pinctrl *info) 1523 { 1524 struct rockchip_pin_ctrl *ctrl = info->ctrl; 1525 struct rockchip_pin_bank *bank = ctrl->pin_banks; 1526 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; 1527 struct irq_chip_generic *gc; 1528 int ret; 1529 int i; 1530 1531 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 1532 if (!bank->valid) { 1533 dev_warn(&pdev->dev, "bank %s is not valid\n", 1534 bank->name); 1535 continue; 1536 } 1537 1538 bank->domain = irq_domain_add_linear(bank->of_node, 32, 1539 &irq_generic_chip_ops, NULL); 1540 if (!bank->domain) { 1541 dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n", 1542 bank->name); 1543 continue; 1544 } 1545 1546 ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1, 1547 "rockchip_gpio_irq", handle_level_irq, 1548 clr, 0, IRQ_GC_INIT_MASK_CACHE); 1549 if (ret) { 1550 dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n", 1551 bank->name); 1552 irq_domain_remove(bank->domain); 1553 continue; 1554 } 1555 1556 gc = irq_get_domain_generic_chip(bank->domain, 0); 1557 gc->reg_base = bank->reg_base; 1558 gc->private = bank; 1559 gc->chip_types[0].regs.mask = GPIO_INTEN; 1560 gc->chip_types[0].regs.ack = GPIO_PORTS_EOI; 1561 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit; 1562 gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit; 1563 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit; 1564 gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake; 1565 gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type; 1566 1567 irq_set_handler_data(bank->irq, bank); 1568 irq_set_chained_handler(bank->irq, rockchip_irq_demux); 1569 } 1570 1571 return 0; 1572 } 1573 1574 static int rockchip_gpiolib_register(struct platform_device *pdev, 1575 struct rockchip_pinctrl *info) 1576 { 1577 struct rockchip_pin_ctrl *ctrl = info->ctrl; 1578 struct rockchip_pin_bank *bank = ctrl->pin_banks; 1579 struct gpio_chip *gc; 1580 int ret; 1581 int i; 1582 1583 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 1584 if (!bank->valid) { 1585 dev_warn(&pdev->dev, "bank %s is not valid\n", 1586 bank->name); 1587 continue; 1588 } 1589 1590 bank->gpio_chip = rockchip_gpiolib_chip; 1591 1592 gc = &bank->gpio_chip; 1593 gc->base = bank->pin_base; 1594 gc->ngpio = bank->nr_pins; 1595 gc->dev = &pdev->dev; 1596 gc->of_node = bank->of_node; 1597 gc->label = bank->name; 1598 1599 ret = gpiochip_add(gc); 1600 if (ret) { 1601 dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n", 1602 gc->label, ret); 1603 goto fail; 1604 } 1605 } 1606 1607 rockchip_interrupts_register(pdev, info); 1608 1609 return 0; 1610 1611 fail: 1612 for (--i, --bank; i >= 0; --i, --bank) { 1613 if (!bank->valid) 1614 continue; 1615 gpiochip_remove(&bank->gpio_chip); 1616 } 1617 return ret; 1618 } 1619 1620 static int rockchip_gpiolib_unregister(struct platform_device *pdev, 1621 struct rockchip_pinctrl *info) 1622 { 1623 struct rockchip_pin_ctrl *ctrl = info->ctrl; 1624 struct rockchip_pin_bank *bank = ctrl->pin_banks; 1625 int i; 1626 1627 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 1628 if (!bank->valid) 1629 continue; 1630 gpiochip_remove(&bank->gpio_chip); 1631 } 1632 1633 return 0; 1634 } 1635 1636 static int rockchip_get_bank_data(struct rockchip_pin_bank *bank, 1637 struct rockchip_pinctrl *info) 1638 { 1639 struct resource res; 1640 void __iomem *base; 1641 1642 if (of_address_to_resource(bank->of_node, 0, &res)) { 1643 dev_err(info->dev, "cannot find IO resource for bank\n"); 1644 return -ENOENT; 1645 } 1646 1647 bank->reg_base = devm_ioremap_resource(info->dev, &res); 1648 if (IS_ERR(bank->reg_base)) 1649 return PTR_ERR(bank->reg_base); 1650 1651 /* 1652 * special case, where parts of the pull setting-registers are 1653 * part of the PMU register space 1654 */ 1655 if (of_device_is_compatible(bank->of_node, 1656 "rockchip,rk3188-gpio-bank0")) { 1657 struct device_node *node; 1658 1659 node = of_parse_phandle(bank->of_node->parent, 1660 "rockchip,pmu", 0); 1661 if (!node) { 1662 if (of_address_to_resource(bank->of_node, 1, &res)) { 1663 dev_err(info->dev, "cannot find IO resource for bank\n"); 1664 return -ENOENT; 1665 } 1666 1667 base = devm_ioremap_resource(info->dev, &res); 1668 if (IS_ERR(base)) 1669 return PTR_ERR(base); 1670 rockchip_regmap_config.max_register = 1671 resource_size(&res) - 4; 1672 rockchip_regmap_config.name = 1673 "rockchip,rk3188-gpio-bank0-pull"; 1674 bank->regmap_pull = devm_regmap_init_mmio(info->dev, 1675 base, 1676 &rockchip_regmap_config); 1677 } 1678 } 1679 1680 bank->irq = irq_of_parse_and_map(bank->of_node, 0); 1681 1682 bank->clk = of_clk_get(bank->of_node, 0); 1683 if (IS_ERR(bank->clk)) 1684 return PTR_ERR(bank->clk); 1685 1686 return clk_prepare_enable(bank->clk); 1687 } 1688 1689 static const struct of_device_id rockchip_pinctrl_dt_match[]; 1690 1691 /* retrieve the soc specific data */ 1692 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data( 1693 struct rockchip_pinctrl *d, 1694 struct platform_device *pdev) 1695 { 1696 const struct of_device_id *match; 1697 struct device_node *node = pdev->dev.of_node; 1698 struct device_node *np; 1699 struct rockchip_pin_ctrl *ctrl; 1700 struct rockchip_pin_bank *bank; 1701 int grf_offs, pmu_offs, i, j; 1702 1703 match = of_match_node(rockchip_pinctrl_dt_match, node); 1704 ctrl = (struct rockchip_pin_ctrl *)match->data; 1705 1706 for_each_child_of_node(node, np) { 1707 if (!of_find_property(np, "gpio-controller", NULL)) 1708 continue; 1709 1710 bank = ctrl->pin_banks; 1711 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 1712 if (!strcmp(bank->name, np->name)) { 1713 bank->of_node = np; 1714 1715 if (!rockchip_get_bank_data(bank, d)) 1716 bank->valid = true; 1717 1718 break; 1719 } 1720 } 1721 } 1722 1723 grf_offs = ctrl->grf_mux_offset; 1724 pmu_offs = ctrl->pmu_mux_offset; 1725 bank = ctrl->pin_banks; 1726 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 1727 int bank_pins = 0; 1728 1729 spin_lock_init(&bank->slock); 1730 bank->drvdata = d; 1731 bank->pin_base = ctrl->nr_pins; 1732 ctrl->nr_pins += bank->nr_pins; 1733 1734 /* calculate iomux offsets */ 1735 for (j = 0; j < 4; j++) { 1736 struct rockchip_iomux *iom = &bank->iomux[j]; 1737 int inc; 1738 1739 if (bank_pins >= bank->nr_pins) 1740 break; 1741 1742 /* preset offset value, set new start value */ 1743 if (iom->offset >= 0) { 1744 if (iom->type & IOMUX_SOURCE_PMU) 1745 pmu_offs = iom->offset; 1746 else 1747 grf_offs = iom->offset; 1748 } else { /* set current offset */ 1749 iom->offset = (iom->type & IOMUX_SOURCE_PMU) ? 1750 pmu_offs : grf_offs; 1751 } 1752 1753 dev_dbg(d->dev, "bank %d, iomux %d has offset 0x%x\n", 1754 i, j, iom->offset); 1755 1756 /* 1757 * Increase offset according to iomux width. 1758 * 4bit iomux'es are spread over two registers. 1759 */ 1760 inc = (iom->type & IOMUX_WIDTH_4BIT) ? 8 : 4; 1761 if (iom->type & IOMUX_SOURCE_PMU) 1762 pmu_offs += inc; 1763 else 1764 grf_offs += inc; 1765 1766 bank_pins += 8; 1767 } 1768 } 1769 1770 return ctrl; 1771 } 1772 1773 static int rockchip_pinctrl_probe(struct platform_device *pdev) 1774 { 1775 struct rockchip_pinctrl *info; 1776 struct device *dev = &pdev->dev; 1777 struct rockchip_pin_ctrl *ctrl; 1778 struct device_node *np = pdev->dev.of_node, *node; 1779 struct resource *res; 1780 void __iomem *base; 1781 int ret; 1782 1783 if (!dev->of_node) { 1784 dev_err(dev, "device tree node not found\n"); 1785 return -ENODEV; 1786 } 1787 1788 info = devm_kzalloc(dev, sizeof(struct rockchip_pinctrl), GFP_KERNEL); 1789 if (!info) 1790 return -ENOMEM; 1791 1792 info->dev = dev; 1793 1794 ctrl = rockchip_pinctrl_get_soc_data(info, pdev); 1795 if (!ctrl) { 1796 dev_err(dev, "driver data not available\n"); 1797 return -EINVAL; 1798 } 1799 info->ctrl = ctrl; 1800 1801 node = of_parse_phandle(np, "rockchip,grf", 0); 1802 if (node) { 1803 info->regmap_base = syscon_node_to_regmap(node); 1804 if (IS_ERR(info->regmap_base)) 1805 return PTR_ERR(info->regmap_base); 1806 } else { 1807 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1808 base = devm_ioremap_resource(&pdev->dev, res); 1809 if (IS_ERR(base)) 1810 return PTR_ERR(base); 1811 1812 rockchip_regmap_config.max_register = resource_size(res) - 4; 1813 rockchip_regmap_config.name = "rockchip,pinctrl"; 1814 info->regmap_base = devm_regmap_init_mmio(&pdev->dev, base, 1815 &rockchip_regmap_config); 1816 1817 /* to check for the old dt-bindings */ 1818 info->reg_size = resource_size(res); 1819 1820 /* Honor the old binding, with pull registers as 2nd resource */ 1821 if (ctrl->type == RK3188 && info->reg_size < 0x200) { 1822 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 1823 base = devm_ioremap_resource(&pdev->dev, res); 1824 if (IS_ERR(base)) 1825 return PTR_ERR(base); 1826 1827 rockchip_regmap_config.max_register = 1828 resource_size(res) - 4; 1829 rockchip_regmap_config.name = "rockchip,pinctrl-pull"; 1830 info->regmap_pull = devm_regmap_init_mmio(&pdev->dev, 1831 base, 1832 &rockchip_regmap_config); 1833 } 1834 } 1835 1836 /* try to find the optional reference to the pmu syscon */ 1837 node = of_parse_phandle(np, "rockchip,pmu", 0); 1838 if (node) { 1839 info->regmap_pmu = syscon_node_to_regmap(node); 1840 if (IS_ERR(info->regmap_pmu)) 1841 return PTR_ERR(info->regmap_pmu); 1842 } 1843 1844 ret = rockchip_gpiolib_register(pdev, info); 1845 if (ret) 1846 return ret; 1847 1848 ret = rockchip_pinctrl_register(pdev, info); 1849 if (ret) { 1850 rockchip_gpiolib_unregister(pdev, info); 1851 return ret; 1852 } 1853 1854 platform_set_drvdata(pdev, info); 1855 1856 return 0; 1857 } 1858 1859 static struct rockchip_pin_bank rk2928_pin_banks[] = { 1860 PIN_BANK(0, 32, "gpio0"), 1861 PIN_BANK(1, 32, "gpio1"), 1862 PIN_BANK(2, 32, "gpio2"), 1863 PIN_BANK(3, 32, "gpio3"), 1864 }; 1865 1866 static struct rockchip_pin_ctrl rk2928_pin_ctrl = { 1867 .pin_banks = rk2928_pin_banks, 1868 .nr_banks = ARRAY_SIZE(rk2928_pin_banks), 1869 .label = "RK2928-GPIO", 1870 .type = RK2928, 1871 .grf_mux_offset = 0xa8, 1872 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 1873 }; 1874 1875 static struct rockchip_pin_bank rk3066a_pin_banks[] = { 1876 PIN_BANK(0, 32, "gpio0"), 1877 PIN_BANK(1, 32, "gpio1"), 1878 PIN_BANK(2, 32, "gpio2"), 1879 PIN_BANK(3, 32, "gpio3"), 1880 PIN_BANK(4, 32, "gpio4"), 1881 PIN_BANK(6, 16, "gpio6"), 1882 }; 1883 1884 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = { 1885 .pin_banks = rk3066a_pin_banks, 1886 .nr_banks = ARRAY_SIZE(rk3066a_pin_banks), 1887 .label = "RK3066a-GPIO", 1888 .type = RK2928, 1889 .grf_mux_offset = 0xa8, 1890 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 1891 }; 1892 1893 static struct rockchip_pin_bank rk3066b_pin_banks[] = { 1894 PIN_BANK(0, 32, "gpio0"), 1895 PIN_BANK(1, 32, "gpio1"), 1896 PIN_BANK(2, 32, "gpio2"), 1897 PIN_BANK(3, 32, "gpio3"), 1898 }; 1899 1900 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = { 1901 .pin_banks = rk3066b_pin_banks, 1902 .nr_banks = ARRAY_SIZE(rk3066b_pin_banks), 1903 .label = "RK3066b-GPIO", 1904 .type = RK3066B, 1905 .grf_mux_offset = 0x60, 1906 }; 1907 1908 static struct rockchip_pin_bank rk3188_pin_banks[] = { 1909 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0), 1910 PIN_BANK(1, 32, "gpio1"), 1911 PIN_BANK(2, 32, "gpio2"), 1912 PIN_BANK(3, 32, "gpio3"), 1913 }; 1914 1915 static struct rockchip_pin_ctrl rk3188_pin_ctrl = { 1916 .pin_banks = rk3188_pin_banks, 1917 .nr_banks = ARRAY_SIZE(rk3188_pin_banks), 1918 .label = "RK3188-GPIO", 1919 .type = RK3188, 1920 .grf_mux_offset = 0x60, 1921 .pull_calc_reg = rk3188_calc_pull_reg_and_bit, 1922 }; 1923 1924 static struct rockchip_pin_bank rk3288_pin_banks[] = { 1925 PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU, 1926 IOMUX_SOURCE_PMU, 1927 IOMUX_SOURCE_PMU, 1928 IOMUX_UNROUTED 1929 ), 1930 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED, 1931 IOMUX_UNROUTED, 1932 IOMUX_UNROUTED, 1933 0 1934 ), 1935 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED), 1936 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT), 1937 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT, 1938 IOMUX_WIDTH_4BIT, 1939 0, 1940 0 1941 ), 1942 PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED, 1943 0, 1944 0, 1945 IOMUX_UNROUTED 1946 ), 1947 PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED), 1948 PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0, 1949 0, 1950 IOMUX_WIDTH_4BIT, 1951 IOMUX_UNROUTED 1952 ), 1953 PIN_BANK(8, 16, "gpio8"), 1954 }; 1955 1956 static struct rockchip_pin_ctrl rk3288_pin_ctrl = { 1957 .pin_banks = rk3288_pin_banks, 1958 .nr_banks = ARRAY_SIZE(rk3288_pin_banks), 1959 .label = "RK3288-GPIO", 1960 .type = RK3288, 1961 .grf_mux_offset = 0x0, 1962 .pmu_mux_offset = 0x84, 1963 .pull_calc_reg = rk3288_calc_pull_reg_and_bit, 1964 }; 1965 1966 static const struct of_device_id rockchip_pinctrl_dt_match[] = { 1967 { .compatible = "rockchip,rk2928-pinctrl", 1968 .data = (void *)&rk2928_pin_ctrl }, 1969 { .compatible = "rockchip,rk3066a-pinctrl", 1970 .data = (void *)&rk3066a_pin_ctrl }, 1971 { .compatible = "rockchip,rk3066b-pinctrl", 1972 .data = (void *)&rk3066b_pin_ctrl }, 1973 { .compatible = "rockchip,rk3188-pinctrl", 1974 .data = (void *)&rk3188_pin_ctrl }, 1975 { .compatible = "rockchip,rk3288-pinctrl", 1976 .data = (void *)&rk3288_pin_ctrl }, 1977 {}, 1978 }; 1979 MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match); 1980 1981 static struct platform_driver rockchip_pinctrl_driver = { 1982 .probe = rockchip_pinctrl_probe, 1983 .driver = { 1984 .name = "rockchip-pinctrl", 1985 .owner = THIS_MODULE, 1986 .of_match_table = rockchip_pinctrl_dt_match, 1987 }, 1988 }; 1989 1990 static int __init rockchip_pinctrl_drv_register(void) 1991 { 1992 return platform_driver_register(&rockchip_pinctrl_driver); 1993 } 1994 postcore_initcall(rockchip_pinctrl_drv_register); 1995 1996 MODULE_AUTHOR("Heiko Stuebner <heiko@sntech.de>"); 1997 MODULE_DESCRIPTION("Rockchip pinctrl driver"); 1998 MODULE_LICENSE("GPL v2"); 1999