1 /* 2 * Pinctrl driver for Rockchip SoCs 3 * 4 * Copyright (c) 2013 MundoReader S.L. 5 * Author: Heiko Stuebner <heiko@sntech.de> 6 * 7 * With some ideas taken from pinctrl-samsung: 8 * Copyright (c) 2012 Samsung Electronics Co., Ltd. 9 * http://www.samsung.com 10 * Copyright (c) 2012 Linaro Ltd 11 * http://www.linaro.org 12 * 13 * and pinctrl-at91: 14 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> 15 * 16 * This program is free software; you can redistribute it and/or modify 17 * it under the terms of the GNU General Public License version 2 as published 18 * by the Free Software Foundation. 19 * 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 */ 25 26 #include <linux/init.h> 27 #include <linux/platform_device.h> 28 #include <linux/io.h> 29 #include <linux/bitops.h> 30 #include <linux/gpio.h> 31 #include <linux/of_address.h> 32 #include <linux/of_irq.h> 33 #include <linux/pinctrl/machine.h> 34 #include <linux/pinctrl/pinconf.h> 35 #include <linux/pinctrl/pinctrl.h> 36 #include <linux/pinctrl/pinmux.h> 37 #include <linux/pinctrl/pinconf-generic.h> 38 #include <linux/irqchip/chained_irq.h> 39 #include <linux/clk.h> 40 #include <linux/regmap.h> 41 #include <linux/mfd/syscon.h> 42 #include <dt-bindings/pinctrl/rockchip.h> 43 44 #include "core.h" 45 #include "pinconf.h" 46 47 /* GPIO control registers */ 48 #define GPIO_SWPORT_DR 0x00 49 #define GPIO_SWPORT_DDR 0x04 50 #define GPIO_INTEN 0x30 51 #define GPIO_INTMASK 0x34 52 #define GPIO_INTTYPE_LEVEL 0x38 53 #define GPIO_INT_POLARITY 0x3c 54 #define GPIO_INT_STATUS 0x40 55 #define GPIO_INT_RAWSTATUS 0x44 56 #define GPIO_DEBOUNCE 0x48 57 #define GPIO_PORTS_EOI 0x4c 58 #define GPIO_EXT_PORT 0x50 59 #define GPIO_LS_SYNC 0x60 60 61 enum rockchip_pinctrl_type { 62 PX30, 63 RV1108, 64 RK2928, 65 RK3066B, 66 RK3128, 67 RK3188, 68 RK3288, 69 RK3368, 70 RK3399, 71 }; 72 73 /** 74 * Encode variants of iomux registers into a type variable 75 */ 76 #define IOMUX_GPIO_ONLY BIT(0) 77 #define IOMUX_WIDTH_4BIT BIT(1) 78 #define IOMUX_SOURCE_PMU BIT(2) 79 #define IOMUX_UNROUTED BIT(3) 80 #define IOMUX_WIDTH_3BIT BIT(4) 81 82 /** 83 * @type: iomux variant using IOMUX_* constants 84 * @offset: if initialized to -1 it will be autocalculated, by specifying 85 * an initial offset value the relevant source offset can be reset 86 * to a new value for autocalculating the following iomux registers. 87 */ 88 struct rockchip_iomux { 89 int type; 90 int offset; 91 }; 92 93 /** 94 * enum type index corresponding to rockchip_perpin_drv_list arrays index. 95 */ 96 enum rockchip_pin_drv_type { 97 DRV_TYPE_IO_DEFAULT = 0, 98 DRV_TYPE_IO_1V8_OR_3V0, 99 DRV_TYPE_IO_1V8_ONLY, 100 DRV_TYPE_IO_1V8_3V0_AUTO, 101 DRV_TYPE_IO_3V3_ONLY, 102 DRV_TYPE_MAX 103 }; 104 105 /** 106 * enum type index corresponding to rockchip_pull_list arrays index. 107 */ 108 enum rockchip_pin_pull_type { 109 PULL_TYPE_IO_DEFAULT = 0, 110 PULL_TYPE_IO_1V8_ONLY, 111 PULL_TYPE_MAX 112 }; 113 114 /** 115 * @drv_type: drive strength variant using rockchip_perpin_drv_type 116 * @offset: if initialized to -1 it will be autocalculated, by specifying 117 * an initial offset value the relevant source offset can be reset 118 * to a new value for autocalculating the following drive strength 119 * registers. if used chips own cal_drv func instead to calculate 120 * registers offset, the variant could be ignored. 121 */ 122 struct rockchip_drv { 123 enum rockchip_pin_drv_type drv_type; 124 int offset; 125 }; 126 127 /** 128 * @reg_base: register base of the gpio bank 129 * @reg_pull: optional separate register for additional pull settings 130 * @clk: clock of the gpio bank 131 * @irq: interrupt of the gpio bank 132 * @saved_masks: Saved content of GPIO_INTEN at suspend time. 133 * @pin_base: first pin number 134 * @nr_pins: number of pins in this bank 135 * @name: name of the bank 136 * @bank_num: number of the bank, to account for holes 137 * @iomux: array describing the 4 iomux sources of the bank 138 * @drv: array describing the 4 drive strength sources of the bank 139 * @pull_type: array describing the 4 pull type sources of the bank 140 * @valid: is all necessary information present 141 * @of_node: dt node of this bank 142 * @drvdata: common pinctrl basedata 143 * @domain: irqdomain of the gpio bank 144 * @gpio_chip: gpiolib chip 145 * @grange: gpio range 146 * @slock: spinlock for the gpio bank 147 * @route_mask: bits describing the routing pins of per bank 148 */ 149 struct rockchip_pin_bank { 150 void __iomem *reg_base; 151 struct regmap *regmap_pull; 152 struct clk *clk; 153 int irq; 154 u32 saved_masks; 155 u32 pin_base; 156 u8 nr_pins; 157 char *name; 158 u8 bank_num; 159 struct rockchip_iomux iomux[4]; 160 struct rockchip_drv drv[4]; 161 enum rockchip_pin_pull_type pull_type[4]; 162 bool valid; 163 struct device_node *of_node; 164 struct rockchip_pinctrl *drvdata; 165 struct irq_domain *domain; 166 struct gpio_chip gpio_chip; 167 struct pinctrl_gpio_range grange; 168 raw_spinlock_t slock; 169 u32 toggle_edge_mode; 170 u32 recalced_mask; 171 u32 route_mask; 172 }; 173 174 #define PIN_BANK(id, pins, label) \ 175 { \ 176 .bank_num = id, \ 177 .nr_pins = pins, \ 178 .name = label, \ 179 .iomux = { \ 180 { .offset = -1 }, \ 181 { .offset = -1 }, \ 182 { .offset = -1 }, \ 183 { .offset = -1 }, \ 184 }, \ 185 } 186 187 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \ 188 { \ 189 .bank_num = id, \ 190 .nr_pins = pins, \ 191 .name = label, \ 192 .iomux = { \ 193 { .type = iom0, .offset = -1 }, \ 194 { .type = iom1, .offset = -1 }, \ 195 { .type = iom2, .offset = -1 }, \ 196 { .type = iom3, .offset = -1 }, \ 197 }, \ 198 } 199 200 #define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \ 201 { \ 202 .bank_num = id, \ 203 .nr_pins = pins, \ 204 .name = label, \ 205 .iomux = { \ 206 { .offset = -1 }, \ 207 { .offset = -1 }, \ 208 { .offset = -1 }, \ 209 { .offset = -1 }, \ 210 }, \ 211 .drv = { \ 212 { .drv_type = type0, .offset = -1 }, \ 213 { .drv_type = type1, .offset = -1 }, \ 214 { .drv_type = type2, .offset = -1 }, \ 215 { .drv_type = type3, .offset = -1 }, \ 216 }, \ 217 } 218 219 #define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1, \ 220 drv2, drv3, pull0, pull1, \ 221 pull2, pull3) \ 222 { \ 223 .bank_num = id, \ 224 .nr_pins = pins, \ 225 .name = label, \ 226 .iomux = { \ 227 { .offset = -1 }, \ 228 { .offset = -1 }, \ 229 { .offset = -1 }, \ 230 { .offset = -1 }, \ 231 }, \ 232 .drv = { \ 233 { .drv_type = drv0, .offset = -1 }, \ 234 { .drv_type = drv1, .offset = -1 }, \ 235 { .drv_type = drv2, .offset = -1 }, \ 236 { .drv_type = drv3, .offset = -1 }, \ 237 }, \ 238 .pull_type[0] = pull0, \ 239 .pull_type[1] = pull1, \ 240 .pull_type[2] = pull2, \ 241 .pull_type[3] = pull3, \ 242 } 243 244 #define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1, \ 245 iom2, iom3, drv0, drv1, drv2, \ 246 drv3, offset0, offset1, \ 247 offset2, offset3) \ 248 { \ 249 .bank_num = id, \ 250 .nr_pins = pins, \ 251 .name = label, \ 252 .iomux = { \ 253 { .type = iom0, .offset = -1 }, \ 254 { .type = iom1, .offset = -1 }, \ 255 { .type = iom2, .offset = -1 }, \ 256 { .type = iom3, .offset = -1 }, \ 257 }, \ 258 .drv = { \ 259 { .drv_type = drv0, .offset = offset0 }, \ 260 { .drv_type = drv1, .offset = offset1 }, \ 261 { .drv_type = drv2, .offset = offset2 }, \ 262 { .drv_type = drv3, .offset = offset3 }, \ 263 }, \ 264 } 265 266 #define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins, \ 267 label, iom0, iom1, iom2, \ 268 iom3, drv0, drv1, drv2, \ 269 drv3, offset0, offset1, \ 270 offset2, offset3, pull0, \ 271 pull1, pull2, pull3) \ 272 { \ 273 .bank_num = id, \ 274 .nr_pins = pins, \ 275 .name = label, \ 276 .iomux = { \ 277 { .type = iom0, .offset = -1 }, \ 278 { .type = iom1, .offset = -1 }, \ 279 { .type = iom2, .offset = -1 }, \ 280 { .type = iom3, .offset = -1 }, \ 281 }, \ 282 .drv = { \ 283 { .drv_type = drv0, .offset = offset0 }, \ 284 { .drv_type = drv1, .offset = offset1 }, \ 285 { .drv_type = drv2, .offset = offset2 }, \ 286 { .drv_type = drv3, .offset = offset3 }, \ 287 }, \ 288 .pull_type[0] = pull0, \ 289 .pull_type[1] = pull1, \ 290 .pull_type[2] = pull2, \ 291 .pull_type[3] = pull3, \ 292 } 293 294 /** 295 * struct rockchip_mux_recalced_data: represent a pin iomux data. 296 * @num: bank number. 297 * @pin: pin number. 298 * @bit: index at register. 299 * @reg: register offset. 300 * @mask: mask bit 301 */ 302 struct rockchip_mux_recalced_data { 303 u8 num; 304 u8 pin; 305 u32 reg; 306 u8 bit; 307 u8 mask; 308 }; 309 310 /** 311 * struct rockchip_mux_recalced_data: represent a pin iomux data. 312 * @bank_num: bank number. 313 * @pin: index at register or used to calc index. 314 * @func: the min pin. 315 * @route_offset: the max pin. 316 * @route_val: the register offset. 317 */ 318 struct rockchip_mux_route_data { 319 u8 bank_num; 320 u8 pin; 321 u8 func; 322 u32 route_offset; 323 u32 route_val; 324 }; 325 326 /** 327 */ 328 struct rockchip_pin_ctrl { 329 struct rockchip_pin_bank *pin_banks; 330 u32 nr_banks; 331 u32 nr_pins; 332 char *label; 333 enum rockchip_pinctrl_type type; 334 int grf_mux_offset; 335 int pmu_mux_offset; 336 int grf_drv_offset; 337 int pmu_drv_offset; 338 struct rockchip_mux_recalced_data *iomux_recalced; 339 u32 niomux_recalced; 340 struct rockchip_mux_route_data *iomux_routes; 341 u32 niomux_routes; 342 343 void (*pull_calc_reg)(struct rockchip_pin_bank *bank, 344 int pin_num, struct regmap **regmap, 345 int *reg, u8 *bit); 346 void (*drv_calc_reg)(struct rockchip_pin_bank *bank, 347 int pin_num, struct regmap **regmap, 348 int *reg, u8 *bit); 349 int (*schmitt_calc_reg)(struct rockchip_pin_bank *bank, 350 int pin_num, struct regmap **regmap, 351 int *reg, u8 *bit); 352 }; 353 354 struct rockchip_pin_config { 355 unsigned int func; 356 unsigned long *configs; 357 unsigned int nconfigs; 358 }; 359 360 /** 361 * struct rockchip_pin_group: represent group of pins of a pinmux function. 362 * @name: name of the pin group, used to lookup the group. 363 * @pins: the pins included in this group. 364 * @npins: number of pins included in this group. 365 * @func: the mux function number to be programmed when selected. 366 * @configs: the config values to be set for each pin 367 * @nconfigs: number of configs for each pin 368 */ 369 struct rockchip_pin_group { 370 const char *name; 371 unsigned int npins; 372 unsigned int *pins; 373 struct rockchip_pin_config *data; 374 }; 375 376 /** 377 * struct rockchip_pmx_func: represent a pin function. 378 * @name: name of the pin function, used to lookup the function. 379 * @groups: one or more names of pin groups that provide this function. 380 * @num_groups: number of groups included in @groups. 381 */ 382 struct rockchip_pmx_func { 383 const char *name; 384 const char **groups; 385 u8 ngroups; 386 }; 387 388 struct rockchip_pinctrl { 389 struct regmap *regmap_base; 390 int reg_size; 391 struct regmap *regmap_pull; 392 struct regmap *regmap_pmu; 393 struct device *dev; 394 struct rockchip_pin_ctrl *ctrl; 395 struct pinctrl_desc pctl; 396 struct pinctrl_dev *pctl_dev; 397 struct rockchip_pin_group *groups; 398 unsigned int ngroups; 399 struct rockchip_pmx_func *functions; 400 unsigned int nfunctions; 401 }; 402 403 static struct regmap_config rockchip_regmap_config = { 404 .reg_bits = 32, 405 .val_bits = 32, 406 .reg_stride = 4, 407 }; 408 409 static inline const struct rockchip_pin_group *pinctrl_name_to_group( 410 const struct rockchip_pinctrl *info, 411 const char *name) 412 { 413 int i; 414 415 for (i = 0; i < info->ngroups; i++) { 416 if (!strcmp(info->groups[i].name, name)) 417 return &info->groups[i]; 418 } 419 420 return NULL; 421 } 422 423 /* 424 * given a pin number that is local to a pin controller, find out the pin bank 425 * and the register base of the pin bank. 426 */ 427 static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info, 428 unsigned pin) 429 { 430 struct rockchip_pin_bank *b = info->ctrl->pin_banks; 431 432 while (pin >= (b->pin_base + b->nr_pins)) 433 b++; 434 435 return b; 436 } 437 438 static struct rockchip_pin_bank *bank_num_to_bank( 439 struct rockchip_pinctrl *info, 440 unsigned num) 441 { 442 struct rockchip_pin_bank *b = info->ctrl->pin_banks; 443 int i; 444 445 for (i = 0; i < info->ctrl->nr_banks; i++, b++) { 446 if (b->bank_num == num) 447 return b; 448 } 449 450 return ERR_PTR(-EINVAL); 451 } 452 453 /* 454 * Pinctrl_ops handling 455 */ 456 457 static int rockchip_get_groups_count(struct pinctrl_dev *pctldev) 458 { 459 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 460 461 return info->ngroups; 462 } 463 464 static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev, 465 unsigned selector) 466 { 467 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 468 469 return info->groups[selector].name; 470 } 471 472 static int rockchip_get_group_pins(struct pinctrl_dev *pctldev, 473 unsigned selector, const unsigned **pins, 474 unsigned *npins) 475 { 476 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 477 478 if (selector >= info->ngroups) 479 return -EINVAL; 480 481 *pins = info->groups[selector].pins; 482 *npins = info->groups[selector].npins; 483 484 return 0; 485 } 486 487 static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev, 488 struct device_node *np, 489 struct pinctrl_map **map, unsigned *num_maps) 490 { 491 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 492 const struct rockchip_pin_group *grp; 493 struct pinctrl_map *new_map; 494 struct device_node *parent; 495 int map_num = 1; 496 int i; 497 498 /* 499 * first find the group of this node and check if we need to create 500 * config maps for pins 501 */ 502 grp = pinctrl_name_to_group(info, np->name); 503 if (!grp) { 504 dev_err(info->dev, "unable to find group for node %s\n", 505 np->name); 506 return -EINVAL; 507 } 508 509 map_num += grp->npins; 510 new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num, 511 GFP_KERNEL); 512 if (!new_map) 513 return -ENOMEM; 514 515 *map = new_map; 516 *num_maps = map_num; 517 518 /* create mux map */ 519 parent = of_get_parent(np); 520 if (!parent) { 521 devm_kfree(pctldev->dev, new_map); 522 return -EINVAL; 523 } 524 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP; 525 new_map[0].data.mux.function = parent->name; 526 new_map[0].data.mux.group = np->name; 527 of_node_put(parent); 528 529 /* create config map */ 530 new_map++; 531 for (i = 0; i < grp->npins; i++) { 532 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN; 533 new_map[i].data.configs.group_or_pin = 534 pin_get_name(pctldev, grp->pins[i]); 535 new_map[i].data.configs.configs = grp->data[i].configs; 536 new_map[i].data.configs.num_configs = grp->data[i].nconfigs; 537 } 538 539 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n", 540 (*map)->data.mux.function, (*map)->data.mux.group, map_num); 541 542 return 0; 543 } 544 545 static void rockchip_dt_free_map(struct pinctrl_dev *pctldev, 546 struct pinctrl_map *map, unsigned num_maps) 547 { 548 } 549 550 static const struct pinctrl_ops rockchip_pctrl_ops = { 551 .get_groups_count = rockchip_get_groups_count, 552 .get_group_name = rockchip_get_group_name, 553 .get_group_pins = rockchip_get_group_pins, 554 .dt_node_to_map = rockchip_dt_node_to_map, 555 .dt_free_map = rockchip_dt_free_map, 556 }; 557 558 /* 559 * Hardware access 560 */ 561 562 static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = { 563 { 564 .num = 1, 565 .pin = 0, 566 .reg = 0x418, 567 .bit = 0, 568 .mask = 0x3 569 }, { 570 .num = 1, 571 .pin = 1, 572 .reg = 0x418, 573 .bit = 2, 574 .mask = 0x3 575 }, { 576 .num = 1, 577 .pin = 2, 578 .reg = 0x418, 579 .bit = 4, 580 .mask = 0x3 581 }, { 582 .num = 1, 583 .pin = 3, 584 .reg = 0x418, 585 .bit = 6, 586 .mask = 0x3 587 }, { 588 .num = 1, 589 .pin = 4, 590 .reg = 0x418, 591 .bit = 8, 592 .mask = 0x3 593 }, { 594 .num = 1, 595 .pin = 5, 596 .reg = 0x418, 597 .bit = 10, 598 .mask = 0x3 599 }, { 600 .num = 1, 601 .pin = 6, 602 .reg = 0x418, 603 .bit = 12, 604 .mask = 0x3 605 }, { 606 .num = 1, 607 .pin = 7, 608 .reg = 0x418, 609 .bit = 14, 610 .mask = 0x3 611 }, { 612 .num = 1, 613 .pin = 8, 614 .reg = 0x41c, 615 .bit = 0, 616 .mask = 0x3 617 }, { 618 .num = 1, 619 .pin = 9, 620 .reg = 0x41c, 621 .bit = 2, 622 .mask = 0x3 623 }, 624 }; 625 626 static struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = { 627 { 628 .num = 2, 629 .pin = 20, 630 .reg = 0xe8, 631 .bit = 0, 632 .mask = 0x7 633 }, { 634 .num = 2, 635 .pin = 21, 636 .reg = 0xe8, 637 .bit = 4, 638 .mask = 0x7 639 }, { 640 .num = 2, 641 .pin = 22, 642 .reg = 0xe8, 643 .bit = 8, 644 .mask = 0x7 645 }, { 646 .num = 2, 647 .pin = 23, 648 .reg = 0xe8, 649 .bit = 12, 650 .mask = 0x7 651 }, { 652 .num = 2, 653 .pin = 24, 654 .reg = 0xd4, 655 .bit = 12, 656 .mask = 0x7 657 }, 658 }; 659 660 static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = { 661 { 662 .num = 2, 663 .pin = 12, 664 .reg = 0x24, 665 .bit = 8, 666 .mask = 0x3 667 }, { 668 .num = 2, 669 .pin = 15, 670 .reg = 0x28, 671 .bit = 0, 672 .mask = 0x7 673 }, { 674 .num = 2, 675 .pin = 23, 676 .reg = 0x30, 677 .bit = 14, 678 .mask = 0x3 679 }, 680 }; 681 682 static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin, 683 int *reg, u8 *bit, int *mask) 684 { 685 struct rockchip_pinctrl *info = bank->drvdata; 686 struct rockchip_pin_ctrl *ctrl = info->ctrl; 687 struct rockchip_mux_recalced_data *data; 688 int i; 689 690 for (i = 0; i < ctrl->niomux_recalced; i++) { 691 data = &ctrl->iomux_recalced[i]; 692 if (data->num == bank->bank_num && 693 data->pin == pin) 694 break; 695 } 696 697 if (i >= ctrl->niomux_recalced) 698 return; 699 700 *reg = data->reg; 701 *mask = data->mask; 702 *bit = data->bit; 703 } 704 705 static struct rockchip_mux_route_data px30_mux_route_data[] = { 706 { 707 /* cif-d2m0 */ 708 .bank_num = 2, 709 .pin = 0, 710 .func = 1, 711 .route_offset = 0x184, 712 .route_val = BIT(16 + 7), 713 }, { 714 /* cif-d2m1 */ 715 .bank_num = 3, 716 .pin = 3, 717 .func = 3, 718 .route_offset = 0x184, 719 .route_val = BIT(16 + 7) | BIT(7), 720 }, { 721 /* pdm-m0 */ 722 .bank_num = 3, 723 .pin = 22, 724 .func = 2, 725 .route_offset = 0x184, 726 .route_val = BIT(16 + 8), 727 }, { 728 /* pdm-m1 */ 729 .bank_num = 2, 730 .pin = 22, 731 .func = 1, 732 .route_offset = 0x184, 733 .route_val = BIT(16 + 8) | BIT(8), 734 }, { 735 /* uart2-rxm0 */ 736 .bank_num = 1, 737 .pin = 27, 738 .func = 2, 739 .route_offset = 0x184, 740 .route_val = BIT(16 + 10), 741 }, { 742 /* uart2-rxm1 */ 743 .bank_num = 2, 744 .pin = 14, 745 .func = 2, 746 .route_offset = 0x184, 747 .route_val = BIT(16 + 10) | BIT(10), 748 }, { 749 /* uart3-rxm0 */ 750 .bank_num = 0, 751 .pin = 17, 752 .func = 2, 753 .route_offset = 0x184, 754 .route_val = BIT(16 + 9), 755 }, { 756 /* uart3-rxm1 */ 757 .bank_num = 1, 758 .pin = 15, 759 .func = 2, 760 .route_offset = 0x184, 761 .route_val = BIT(16 + 9) | BIT(9), 762 }, 763 }; 764 765 static struct rockchip_mux_route_data rk3128_mux_route_data[] = { 766 { 767 /* spi-0 */ 768 .bank_num = 1, 769 .pin = 10, 770 .func = 1, 771 .route_offset = 0x144, 772 .route_val = BIT(16 + 3) | BIT(16 + 4), 773 }, { 774 /* spi-1 */ 775 .bank_num = 1, 776 .pin = 27, 777 .func = 3, 778 .route_offset = 0x144, 779 .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(3), 780 }, { 781 /* spi-2 */ 782 .bank_num = 0, 783 .pin = 13, 784 .func = 2, 785 .route_offset = 0x144, 786 .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(4), 787 }, { 788 /* i2s-0 */ 789 .bank_num = 1, 790 .pin = 5, 791 .func = 1, 792 .route_offset = 0x144, 793 .route_val = BIT(16 + 5), 794 }, { 795 /* i2s-1 */ 796 .bank_num = 0, 797 .pin = 14, 798 .func = 1, 799 .route_offset = 0x144, 800 .route_val = BIT(16 + 5) | BIT(5), 801 }, { 802 /* emmc-0 */ 803 .bank_num = 1, 804 .pin = 22, 805 .func = 2, 806 .route_offset = 0x144, 807 .route_val = BIT(16 + 6), 808 }, { 809 /* emmc-1 */ 810 .bank_num = 2, 811 .pin = 4, 812 .func = 2, 813 .route_offset = 0x144, 814 .route_val = BIT(16 + 6) | BIT(6), 815 }, 816 }; 817 818 static struct rockchip_mux_route_data rk3228_mux_route_data[] = { 819 { 820 /* pwm0-0 */ 821 .bank_num = 0, 822 .pin = 26, 823 .func = 1, 824 .route_offset = 0x50, 825 .route_val = BIT(16), 826 }, { 827 /* pwm0-1 */ 828 .bank_num = 3, 829 .pin = 21, 830 .func = 1, 831 .route_offset = 0x50, 832 .route_val = BIT(16) | BIT(0), 833 }, { 834 /* pwm1-0 */ 835 .bank_num = 0, 836 .pin = 27, 837 .func = 1, 838 .route_offset = 0x50, 839 .route_val = BIT(16 + 1), 840 }, { 841 /* pwm1-1 */ 842 .bank_num = 0, 843 .pin = 30, 844 .func = 2, 845 .route_offset = 0x50, 846 .route_val = BIT(16 + 1) | BIT(1), 847 }, { 848 /* pwm2-0 */ 849 .bank_num = 0, 850 .pin = 28, 851 .func = 1, 852 .route_offset = 0x50, 853 .route_val = BIT(16 + 2), 854 }, { 855 /* pwm2-1 */ 856 .bank_num = 1, 857 .pin = 12, 858 .func = 2, 859 .route_offset = 0x50, 860 .route_val = BIT(16 + 2) | BIT(2), 861 }, { 862 /* pwm3-0 */ 863 .bank_num = 3, 864 .pin = 26, 865 .func = 1, 866 .route_offset = 0x50, 867 .route_val = BIT(16 + 3), 868 }, { 869 /* pwm3-1 */ 870 .bank_num = 1, 871 .pin = 11, 872 .func = 2, 873 .route_offset = 0x50, 874 .route_val = BIT(16 + 3) | BIT(3), 875 }, { 876 /* sdio-0_d0 */ 877 .bank_num = 1, 878 .pin = 1, 879 .func = 1, 880 .route_offset = 0x50, 881 .route_val = BIT(16 + 4), 882 }, { 883 /* sdio-1_d0 */ 884 .bank_num = 3, 885 .pin = 2, 886 .func = 1, 887 .route_offset = 0x50, 888 .route_val = BIT(16 + 4) | BIT(4), 889 }, { 890 /* spi-0_rx */ 891 .bank_num = 0, 892 .pin = 13, 893 .func = 2, 894 .route_offset = 0x50, 895 .route_val = BIT(16 + 5), 896 }, { 897 /* spi-1_rx */ 898 .bank_num = 2, 899 .pin = 0, 900 .func = 2, 901 .route_offset = 0x50, 902 .route_val = BIT(16 + 5) | BIT(5), 903 }, { 904 /* emmc-0_cmd */ 905 .bank_num = 1, 906 .pin = 22, 907 .func = 2, 908 .route_offset = 0x50, 909 .route_val = BIT(16 + 7), 910 }, { 911 /* emmc-1_cmd */ 912 .bank_num = 2, 913 .pin = 4, 914 .func = 2, 915 .route_offset = 0x50, 916 .route_val = BIT(16 + 7) | BIT(7), 917 }, { 918 /* uart2-0_rx */ 919 .bank_num = 1, 920 .pin = 19, 921 .func = 2, 922 .route_offset = 0x50, 923 .route_val = BIT(16 + 8), 924 }, { 925 /* uart2-1_rx */ 926 .bank_num = 1, 927 .pin = 10, 928 .func = 2, 929 .route_offset = 0x50, 930 .route_val = BIT(16 + 8) | BIT(8), 931 }, { 932 /* uart1-0_rx */ 933 .bank_num = 1, 934 .pin = 10, 935 .func = 1, 936 .route_offset = 0x50, 937 .route_val = BIT(16 + 11), 938 }, { 939 /* uart1-1_rx */ 940 .bank_num = 3, 941 .pin = 13, 942 .func = 1, 943 .route_offset = 0x50, 944 .route_val = BIT(16 + 11) | BIT(11), 945 }, 946 }; 947 948 static struct rockchip_mux_route_data rk3288_mux_route_data[] = { 949 { 950 /* edphdmi_cecinoutt1 */ 951 .bank_num = 7, 952 .pin = 16, 953 .func = 2, 954 .route_offset = 0x264, 955 .route_val = BIT(16 + 12) | BIT(12), 956 }, { 957 /* edphdmi_cecinout */ 958 .bank_num = 7, 959 .pin = 23, 960 .func = 4, 961 .route_offset = 0x264, 962 .route_val = BIT(16 + 12), 963 }, 964 }; 965 966 static struct rockchip_mux_route_data rk3328_mux_route_data[] = { 967 { 968 /* uart2dbg_rxm0 */ 969 .bank_num = 1, 970 .pin = 1, 971 .func = 2, 972 .route_offset = 0x50, 973 .route_val = BIT(16) | BIT(16 + 1), 974 }, { 975 /* uart2dbg_rxm1 */ 976 .bank_num = 2, 977 .pin = 1, 978 .func = 1, 979 .route_offset = 0x50, 980 .route_val = BIT(16) | BIT(16 + 1) | BIT(0), 981 }, { 982 /* gmac-m1_rxd0 */ 983 .bank_num = 1, 984 .pin = 11, 985 .func = 2, 986 .route_offset = 0x50, 987 .route_val = BIT(16 + 2) | BIT(2), 988 }, { 989 /* gmac-m1-optimized_rxd3 */ 990 .bank_num = 1, 991 .pin = 14, 992 .func = 2, 993 .route_offset = 0x50, 994 .route_val = BIT(16 + 10) | BIT(10), 995 }, { 996 /* pdm_sdi0m0 */ 997 .bank_num = 2, 998 .pin = 19, 999 .func = 2, 1000 .route_offset = 0x50, 1001 .route_val = BIT(16 + 3), 1002 }, { 1003 /* pdm_sdi0m1 */ 1004 .bank_num = 1, 1005 .pin = 23, 1006 .func = 3, 1007 .route_offset = 0x50, 1008 .route_val = BIT(16 + 3) | BIT(3), 1009 }, { 1010 /* spi_rxdm2 */ 1011 .bank_num = 3, 1012 .pin = 2, 1013 .func = 4, 1014 .route_offset = 0x50, 1015 .route_val = BIT(16 + 4) | BIT(16 + 5) | BIT(5), 1016 }, { 1017 /* i2s2_sdim0 */ 1018 .bank_num = 1, 1019 .pin = 24, 1020 .func = 1, 1021 .route_offset = 0x50, 1022 .route_val = BIT(16 + 6), 1023 }, { 1024 /* i2s2_sdim1 */ 1025 .bank_num = 3, 1026 .pin = 2, 1027 .func = 6, 1028 .route_offset = 0x50, 1029 .route_val = BIT(16 + 6) | BIT(6), 1030 }, { 1031 /* card_iom1 */ 1032 .bank_num = 2, 1033 .pin = 22, 1034 .func = 3, 1035 .route_offset = 0x50, 1036 .route_val = BIT(16 + 7) | BIT(7), 1037 }, { 1038 /* tsp_d5m1 */ 1039 .bank_num = 2, 1040 .pin = 16, 1041 .func = 3, 1042 .route_offset = 0x50, 1043 .route_val = BIT(16 + 8) | BIT(8), 1044 }, { 1045 /* cif_data5m1 */ 1046 .bank_num = 2, 1047 .pin = 16, 1048 .func = 4, 1049 .route_offset = 0x50, 1050 .route_val = BIT(16 + 9) | BIT(9), 1051 }, 1052 }; 1053 1054 static struct rockchip_mux_route_data rk3399_mux_route_data[] = { 1055 { 1056 /* uart2dbga_rx */ 1057 .bank_num = 4, 1058 .pin = 8, 1059 .func = 2, 1060 .route_offset = 0xe21c, 1061 .route_val = BIT(16 + 10) | BIT(16 + 11), 1062 }, { 1063 /* uart2dbgb_rx */ 1064 .bank_num = 4, 1065 .pin = 16, 1066 .func = 2, 1067 .route_offset = 0xe21c, 1068 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10), 1069 }, { 1070 /* uart2dbgc_rx */ 1071 .bank_num = 4, 1072 .pin = 19, 1073 .func = 1, 1074 .route_offset = 0xe21c, 1075 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11), 1076 }, { 1077 /* pcie_clkreqn */ 1078 .bank_num = 2, 1079 .pin = 26, 1080 .func = 2, 1081 .route_offset = 0xe21c, 1082 .route_val = BIT(16 + 14), 1083 }, { 1084 /* pcie_clkreqnb */ 1085 .bank_num = 4, 1086 .pin = 24, 1087 .func = 1, 1088 .route_offset = 0xe21c, 1089 .route_val = BIT(16 + 14) | BIT(14), 1090 }, 1091 }; 1092 1093 static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin, 1094 int mux, u32 *reg, u32 *value) 1095 { 1096 struct rockchip_pinctrl *info = bank->drvdata; 1097 struct rockchip_pin_ctrl *ctrl = info->ctrl; 1098 struct rockchip_mux_route_data *data; 1099 int i; 1100 1101 for (i = 0; i < ctrl->niomux_routes; i++) { 1102 data = &ctrl->iomux_routes[i]; 1103 if ((data->bank_num == bank->bank_num) && 1104 (data->pin == pin) && (data->func == mux)) 1105 break; 1106 } 1107 1108 if (i >= ctrl->niomux_routes) 1109 return false; 1110 1111 *reg = data->route_offset; 1112 *value = data->route_val; 1113 1114 return true; 1115 } 1116 1117 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) 1118 { 1119 struct rockchip_pinctrl *info = bank->drvdata; 1120 int iomux_num = (pin / 8); 1121 struct regmap *regmap; 1122 unsigned int val; 1123 int reg, ret, mask, mux_type; 1124 u8 bit; 1125 1126 if (iomux_num > 3) 1127 return -EINVAL; 1128 1129 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { 1130 dev_err(info->dev, "pin %d is unrouted\n", pin); 1131 return -EINVAL; 1132 } 1133 1134 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) 1135 return RK_FUNC_GPIO; 1136 1137 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) 1138 ? info->regmap_pmu : info->regmap_base; 1139 1140 /* get basic quadrupel of mux registers and the correct reg inside */ 1141 mux_type = bank->iomux[iomux_num].type; 1142 reg = bank->iomux[iomux_num].offset; 1143 if (mux_type & IOMUX_WIDTH_4BIT) { 1144 if ((pin % 8) >= 4) 1145 reg += 0x4; 1146 bit = (pin % 4) * 4; 1147 mask = 0xf; 1148 } else if (mux_type & IOMUX_WIDTH_3BIT) { 1149 if ((pin % 8) >= 5) 1150 reg += 0x4; 1151 bit = (pin % 8 % 5) * 3; 1152 mask = 0x7; 1153 } else { 1154 bit = (pin % 8) * 2; 1155 mask = 0x3; 1156 } 1157 1158 if (bank->recalced_mask & BIT(pin)) 1159 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); 1160 1161 ret = regmap_read(regmap, reg, &val); 1162 if (ret) 1163 return ret; 1164 1165 return ((val >> bit) & mask); 1166 } 1167 1168 static int rockchip_verify_mux(struct rockchip_pin_bank *bank, 1169 int pin, int mux) 1170 { 1171 struct rockchip_pinctrl *info = bank->drvdata; 1172 int iomux_num = (pin / 8); 1173 1174 if (iomux_num > 3) 1175 return -EINVAL; 1176 1177 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { 1178 dev_err(info->dev, "pin %d is unrouted\n", pin); 1179 return -EINVAL; 1180 } 1181 1182 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) { 1183 if (mux != RK_FUNC_GPIO) { 1184 dev_err(info->dev, 1185 "pin %d only supports a gpio mux\n", pin); 1186 return -ENOTSUPP; 1187 } 1188 } 1189 1190 return 0; 1191 } 1192 1193 /* 1194 * Set a new mux function for a pin. 1195 * 1196 * The register is divided into the upper and lower 16 bit. When changing 1197 * a value, the previous register value is not read and changed. Instead 1198 * it seems the changed bits are marked in the upper 16 bit, while the 1199 * changed value gets set in the same offset in the lower 16 bit. 1200 * All pin settings seem to be 2 bit wide in both the upper and lower 1201 * parts. 1202 * @bank: pin bank to change 1203 * @pin: pin to change 1204 * @mux: new mux function to set 1205 */ 1206 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) 1207 { 1208 struct rockchip_pinctrl *info = bank->drvdata; 1209 int iomux_num = (pin / 8); 1210 struct regmap *regmap; 1211 int reg, ret, mask, mux_type; 1212 u8 bit; 1213 u32 data, rmask, route_reg, route_val; 1214 1215 ret = rockchip_verify_mux(bank, pin, mux); 1216 if (ret < 0) 1217 return ret; 1218 1219 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) 1220 return 0; 1221 1222 dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n", 1223 bank->bank_num, pin, mux); 1224 1225 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) 1226 ? info->regmap_pmu : info->regmap_base; 1227 1228 /* get basic quadrupel of mux registers and the correct reg inside */ 1229 mux_type = bank->iomux[iomux_num].type; 1230 reg = bank->iomux[iomux_num].offset; 1231 if (mux_type & IOMUX_WIDTH_4BIT) { 1232 if ((pin % 8) >= 4) 1233 reg += 0x4; 1234 bit = (pin % 4) * 4; 1235 mask = 0xf; 1236 } else if (mux_type & IOMUX_WIDTH_3BIT) { 1237 if ((pin % 8) >= 5) 1238 reg += 0x4; 1239 bit = (pin % 8 % 5) * 3; 1240 mask = 0x7; 1241 } else { 1242 bit = (pin % 8) * 2; 1243 mask = 0x3; 1244 } 1245 1246 if (bank->recalced_mask & BIT(pin)) 1247 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); 1248 1249 if (bank->route_mask & BIT(pin)) { 1250 if (rockchip_get_mux_route(bank, pin, mux, &route_reg, 1251 &route_val)) { 1252 ret = regmap_write(regmap, route_reg, route_val); 1253 if (ret) 1254 return ret; 1255 } 1256 } 1257 1258 data = (mask << (bit + 16)); 1259 rmask = data | (data >> 16); 1260 data |= (mux & mask) << bit; 1261 ret = regmap_update_bits(regmap, reg, rmask, data); 1262 1263 return ret; 1264 } 1265 1266 #define PX30_PULL_PMU_OFFSET 0x10 1267 #define PX30_PULL_GRF_OFFSET 0x60 1268 #define PX30_PULL_BITS_PER_PIN 2 1269 #define PX30_PULL_PINS_PER_REG 8 1270 #define PX30_PULL_BANK_STRIDE 16 1271 1272 static void px30_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1273 int pin_num, struct regmap **regmap, 1274 int *reg, u8 *bit) 1275 { 1276 struct rockchip_pinctrl *info = bank->drvdata; 1277 1278 /* The first 32 pins of the first bank are located in PMU */ 1279 if (bank->bank_num == 0) { 1280 *regmap = info->regmap_pmu; 1281 *reg = PX30_PULL_PMU_OFFSET; 1282 } else { 1283 *regmap = info->regmap_base; 1284 *reg = PX30_PULL_GRF_OFFSET; 1285 1286 /* correct the offset, as we're starting with the 2nd bank */ 1287 *reg -= 0x10; 1288 *reg += bank->bank_num * PX30_PULL_BANK_STRIDE; 1289 } 1290 1291 *reg += ((pin_num / PX30_PULL_PINS_PER_REG) * 4); 1292 *bit = (pin_num % PX30_PULL_PINS_PER_REG); 1293 *bit *= PX30_PULL_BITS_PER_PIN; 1294 } 1295 1296 #define PX30_DRV_PMU_OFFSET 0x20 1297 #define PX30_DRV_GRF_OFFSET 0xf0 1298 #define PX30_DRV_BITS_PER_PIN 2 1299 #define PX30_DRV_PINS_PER_REG 8 1300 #define PX30_DRV_BANK_STRIDE 16 1301 1302 static void px30_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1303 int pin_num, struct regmap **regmap, 1304 int *reg, u8 *bit) 1305 { 1306 struct rockchip_pinctrl *info = bank->drvdata; 1307 1308 /* The first 32 pins of the first bank are located in PMU */ 1309 if (bank->bank_num == 0) { 1310 *regmap = info->regmap_pmu; 1311 *reg = PX30_DRV_PMU_OFFSET; 1312 } else { 1313 *regmap = info->regmap_base; 1314 *reg = PX30_DRV_GRF_OFFSET; 1315 1316 /* correct the offset, as we're starting with the 2nd bank */ 1317 *reg -= 0x10; 1318 *reg += bank->bank_num * PX30_DRV_BANK_STRIDE; 1319 } 1320 1321 *reg += ((pin_num / PX30_DRV_PINS_PER_REG) * 4); 1322 *bit = (pin_num % PX30_DRV_PINS_PER_REG); 1323 *bit *= PX30_DRV_BITS_PER_PIN; 1324 } 1325 1326 #define PX30_SCHMITT_PMU_OFFSET 0x38 1327 #define PX30_SCHMITT_GRF_OFFSET 0xc0 1328 #define PX30_SCHMITT_PINS_PER_PMU_REG 16 1329 #define PX30_SCHMITT_BANK_STRIDE 16 1330 #define PX30_SCHMITT_PINS_PER_GRF_REG 8 1331 1332 static int px30_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1333 int pin_num, 1334 struct regmap **regmap, 1335 int *reg, u8 *bit) 1336 { 1337 struct rockchip_pinctrl *info = bank->drvdata; 1338 int pins_per_reg; 1339 1340 if (bank->bank_num == 0) { 1341 *regmap = info->regmap_pmu; 1342 *reg = PX30_SCHMITT_PMU_OFFSET; 1343 pins_per_reg = PX30_SCHMITT_PINS_PER_PMU_REG; 1344 } else { 1345 *regmap = info->regmap_base; 1346 *reg = PX30_SCHMITT_GRF_OFFSET; 1347 pins_per_reg = PX30_SCHMITT_PINS_PER_GRF_REG; 1348 *reg += (bank->bank_num - 1) * PX30_SCHMITT_BANK_STRIDE; 1349 } 1350 1351 *reg += ((pin_num / pins_per_reg) * 4); 1352 *bit = pin_num % pins_per_reg; 1353 1354 return 0; 1355 } 1356 1357 #define RV1108_PULL_PMU_OFFSET 0x10 1358 #define RV1108_PULL_OFFSET 0x110 1359 #define RV1108_PULL_PINS_PER_REG 8 1360 #define RV1108_PULL_BITS_PER_PIN 2 1361 #define RV1108_PULL_BANK_STRIDE 16 1362 1363 static void rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1364 int pin_num, struct regmap **regmap, 1365 int *reg, u8 *bit) 1366 { 1367 struct rockchip_pinctrl *info = bank->drvdata; 1368 1369 /* The first 24 pins of the first bank are located in PMU */ 1370 if (bank->bank_num == 0) { 1371 *regmap = info->regmap_pmu; 1372 *reg = RV1108_PULL_PMU_OFFSET; 1373 } else { 1374 *reg = RV1108_PULL_OFFSET; 1375 *regmap = info->regmap_base; 1376 /* correct the offset, as we're starting with the 2nd bank */ 1377 *reg -= 0x10; 1378 *reg += bank->bank_num * RV1108_PULL_BANK_STRIDE; 1379 } 1380 1381 *reg += ((pin_num / RV1108_PULL_PINS_PER_REG) * 4); 1382 *bit = (pin_num % RV1108_PULL_PINS_PER_REG); 1383 *bit *= RV1108_PULL_BITS_PER_PIN; 1384 } 1385 1386 #define RV1108_DRV_PMU_OFFSET 0x20 1387 #define RV1108_DRV_GRF_OFFSET 0x210 1388 #define RV1108_DRV_BITS_PER_PIN 2 1389 #define RV1108_DRV_PINS_PER_REG 8 1390 #define RV1108_DRV_BANK_STRIDE 16 1391 1392 static void rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1393 int pin_num, struct regmap **regmap, 1394 int *reg, u8 *bit) 1395 { 1396 struct rockchip_pinctrl *info = bank->drvdata; 1397 1398 /* The first 24 pins of the first bank are located in PMU */ 1399 if (bank->bank_num == 0) { 1400 *regmap = info->regmap_pmu; 1401 *reg = RV1108_DRV_PMU_OFFSET; 1402 } else { 1403 *regmap = info->regmap_base; 1404 *reg = RV1108_DRV_GRF_OFFSET; 1405 1406 /* correct the offset, as we're starting with the 2nd bank */ 1407 *reg -= 0x10; 1408 *reg += bank->bank_num * RV1108_DRV_BANK_STRIDE; 1409 } 1410 1411 *reg += ((pin_num / RV1108_DRV_PINS_PER_REG) * 4); 1412 *bit = pin_num % RV1108_DRV_PINS_PER_REG; 1413 *bit *= RV1108_DRV_BITS_PER_PIN; 1414 } 1415 1416 #define RV1108_SCHMITT_PMU_OFFSET 0x30 1417 #define RV1108_SCHMITT_GRF_OFFSET 0x388 1418 #define RV1108_SCHMITT_BANK_STRIDE 8 1419 #define RV1108_SCHMITT_PINS_PER_GRF_REG 16 1420 #define RV1108_SCHMITT_PINS_PER_PMU_REG 8 1421 1422 static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1423 int pin_num, 1424 struct regmap **regmap, 1425 int *reg, u8 *bit) 1426 { 1427 struct rockchip_pinctrl *info = bank->drvdata; 1428 int pins_per_reg; 1429 1430 if (bank->bank_num == 0) { 1431 *regmap = info->regmap_pmu; 1432 *reg = RV1108_SCHMITT_PMU_OFFSET; 1433 pins_per_reg = RV1108_SCHMITT_PINS_PER_PMU_REG; 1434 } else { 1435 *regmap = info->regmap_base; 1436 *reg = RV1108_SCHMITT_GRF_OFFSET; 1437 pins_per_reg = RV1108_SCHMITT_PINS_PER_GRF_REG; 1438 *reg += (bank->bank_num - 1) * RV1108_SCHMITT_BANK_STRIDE; 1439 } 1440 *reg += ((pin_num / pins_per_reg) * 4); 1441 *bit = pin_num % pins_per_reg; 1442 1443 return 0; 1444 } 1445 1446 #define RK2928_PULL_OFFSET 0x118 1447 #define RK2928_PULL_PINS_PER_REG 16 1448 #define RK2928_PULL_BANK_STRIDE 8 1449 1450 static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1451 int pin_num, struct regmap **regmap, 1452 int *reg, u8 *bit) 1453 { 1454 struct rockchip_pinctrl *info = bank->drvdata; 1455 1456 *regmap = info->regmap_base; 1457 *reg = RK2928_PULL_OFFSET; 1458 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; 1459 *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4; 1460 1461 *bit = pin_num % RK2928_PULL_PINS_PER_REG; 1462 }; 1463 1464 #define RK3128_PULL_OFFSET 0x118 1465 1466 static void rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1467 int pin_num, struct regmap **regmap, 1468 int *reg, u8 *bit) 1469 { 1470 struct rockchip_pinctrl *info = bank->drvdata; 1471 1472 *regmap = info->regmap_base; 1473 *reg = RK3128_PULL_OFFSET; 1474 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; 1475 *reg += ((pin_num / RK2928_PULL_PINS_PER_REG) * 4); 1476 1477 *bit = pin_num % RK2928_PULL_PINS_PER_REG; 1478 } 1479 1480 #define RK3188_PULL_OFFSET 0x164 1481 #define RK3188_PULL_BITS_PER_PIN 2 1482 #define RK3188_PULL_PINS_PER_REG 8 1483 #define RK3188_PULL_BANK_STRIDE 16 1484 #define RK3188_PULL_PMU_OFFSET 0x64 1485 1486 static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1487 int pin_num, struct regmap **regmap, 1488 int *reg, u8 *bit) 1489 { 1490 struct rockchip_pinctrl *info = bank->drvdata; 1491 1492 /* The first 12 pins of the first bank are located elsewhere */ 1493 if (bank->bank_num == 0 && pin_num < 12) { 1494 *regmap = info->regmap_pmu ? info->regmap_pmu 1495 : bank->regmap_pull; 1496 *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0; 1497 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1498 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 1499 *bit *= RK3188_PULL_BITS_PER_PIN; 1500 } else { 1501 *regmap = info->regmap_pull ? info->regmap_pull 1502 : info->regmap_base; 1503 *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET; 1504 1505 /* correct the offset, as it is the 2nd pull register */ 1506 *reg -= 4; 1507 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1508 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1509 1510 /* 1511 * The bits in these registers have an inverse ordering 1512 * with the lowest pin being in bits 15:14 and the highest 1513 * pin in bits 1:0 1514 */ 1515 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG); 1516 *bit *= RK3188_PULL_BITS_PER_PIN; 1517 } 1518 } 1519 1520 #define RK3288_PULL_OFFSET 0x140 1521 static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1522 int pin_num, struct regmap **regmap, 1523 int *reg, u8 *bit) 1524 { 1525 struct rockchip_pinctrl *info = bank->drvdata; 1526 1527 /* The first 24 pins of the first bank are located in PMU */ 1528 if (bank->bank_num == 0) { 1529 *regmap = info->regmap_pmu; 1530 *reg = RK3188_PULL_PMU_OFFSET; 1531 1532 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1533 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 1534 *bit *= RK3188_PULL_BITS_PER_PIN; 1535 } else { 1536 *regmap = info->regmap_base; 1537 *reg = RK3288_PULL_OFFSET; 1538 1539 /* correct the offset, as we're starting with the 2nd bank */ 1540 *reg -= 0x10; 1541 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1542 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1543 1544 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1545 *bit *= RK3188_PULL_BITS_PER_PIN; 1546 } 1547 } 1548 1549 #define RK3288_DRV_PMU_OFFSET 0x70 1550 #define RK3288_DRV_GRF_OFFSET 0x1c0 1551 #define RK3288_DRV_BITS_PER_PIN 2 1552 #define RK3288_DRV_PINS_PER_REG 8 1553 #define RK3288_DRV_BANK_STRIDE 16 1554 1555 static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1556 int pin_num, struct regmap **regmap, 1557 int *reg, u8 *bit) 1558 { 1559 struct rockchip_pinctrl *info = bank->drvdata; 1560 1561 /* The first 24 pins of the first bank are located in PMU */ 1562 if (bank->bank_num == 0) { 1563 *regmap = info->regmap_pmu; 1564 *reg = RK3288_DRV_PMU_OFFSET; 1565 1566 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1567 *bit = pin_num % RK3288_DRV_PINS_PER_REG; 1568 *bit *= RK3288_DRV_BITS_PER_PIN; 1569 } else { 1570 *regmap = info->regmap_base; 1571 *reg = RK3288_DRV_GRF_OFFSET; 1572 1573 /* correct the offset, as we're starting with the 2nd bank */ 1574 *reg -= 0x10; 1575 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 1576 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1577 1578 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 1579 *bit *= RK3288_DRV_BITS_PER_PIN; 1580 } 1581 } 1582 1583 #define RK3228_PULL_OFFSET 0x100 1584 1585 static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1586 int pin_num, struct regmap **regmap, 1587 int *reg, u8 *bit) 1588 { 1589 struct rockchip_pinctrl *info = bank->drvdata; 1590 1591 *regmap = info->regmap_base; 1592 *reg = RK3228_PULL_OFFSET; 1593 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1594 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1595 1596 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1597 *bit *= RK3188_PULL_BITS_PER_PIN; 1598 } 1599 1600 #define RK3228_DRV_GRF_OFFSET 0x200 1601 1602 static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1603 int pin_num, struct regmap **regmap, 1604 int *reg, u8 *bit) 1605 { 1606 struct rockchip_pinctrl *info = bank->drvdata; 1607 1608 *regmap = info->regmap_base; 1609 *reg = RK3228_DRV_GRF_OFFSET; 1610 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 1611 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1612 1613 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 1614 *bit *= RK3288_DRV_BITS_PER_PIN; 1615 } 1616 1617 #define RK3368_PULL_GRF_OFFSET 0x100 1618 #define RK3368_PULL_PMU_OFFSET 0x10 1619 1620 static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1621 int pin_num, struct regmap **regmap, 1622 int *reg, u8 *bit) 1623 { 1624 struct rockchip_pinctrl *info = bank->drvdata; 1625 1626 /* The first 32 pins of the first bank are located in PMU */ 1627 if (bank->bank_num == 0) { 1628 *regmap = info->regmap_pmu; 1629 *reg = RK3368_PULL_PMU_OFFSET; 1630 1631 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1632 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 1633 *bit *= RK3188_PULL_BITS_PER_PIN; 1634 } else { 1635 *regmap = info->regmap_base; 1636 *reg = RK3368_PULL_GRF_OFFSET; 1637 1638 /* correct the offset, as we're starting with the 2nd bank */ 1639 *reg -= 0x10; 1640 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1641 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1642 1643 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1644 *bit *= RK3188_PULL_BITS_PER_PIN; 1645 } 1646 } 1647 1648 #define RK3368_DRV_PMU_OFFSET 0x20 1649 #define RK3368_DRV_GRF_OFFSET 0x200 1650 1651 static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1652 int pin_num, struct regmap **regmap, 1653 int *reg, u8 *bit) 1654 { 1655 struct rockchip_pinctrl *info = bank->drvdata; 1656 1657 /* The first 32 pins of the first bank are located in PMU */ 1658 if (bank->bank_num == 0) { 1659 *regmap = info->regmap_pmu; 1660 *reg = RK3368_DRV_PMU_OFFSET; 1661 1662 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1663 *bit = pin_num % RK3288_DRV_PINS_PER_REG; 1664 *bit *= RK3288_DRV_BITS_PER_PIN; 1665 } else { 1666 *regmap = info->regmap_base; 1667 *reg = RK3368_DRV_GRF_OFFSET; 1668 1669 /* correct the offset, as we're starting with the 2nd bank */ 1670 *reg -= 0x10; 1671 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 1672 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1673 1674 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 1675 *bit *= RK3288_DRV_BITS_PER_PIN; 1676 } 1677 } 1678 1679 #define RK3399_PULL_GRF_OFFSET 0xe040 1680 #define RK3399_PULL_PMU_OFFSET 0x40 1681 #define RK3399_DRV_3BITS_PER_PIN 3 1682 1683 static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1684 int pin_num, struct regmap **regmap, 1685 int *reg, u8 *bit) 1686 { 1687 struct rockchip_pinctrl *info = bank->drvdata; 1688 1689 /* The bank0:16 and bank1:32 pins are located in PMU */ 1690 if ((bank->bank_num == 0) || (bank->bank_num == 1)) { 1691 *regmap = info->regmap_pmu; 1692 *reg = RK3399_PULL_PMU_OFFSET; 1693 1694 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1695 1696 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1697 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 1698 *bit *= RK3188_PULL_BITS_PER_PIN; 1699 } else { 1700 *regmap = info->regmap_base; 1701 *reg = RK3399_PULL_GRF_OFFSET; 1702 1703 /* correct the offset, as we're starting with the 3rd bank */ 1704 *reg -= 0x20; 1705 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1706 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1707 1708 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1709 *bit *= RK3188_PULL_BITS_PER_PIN; 1710 } 1711 } 1712 1713 static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1714 int pin_num, struct regmap **regmap, 1715 int *reg, u8 *bit) 1716 { 1717 struct rockchip_pinctrl *info = bank->drvdata; 1718 int drv_num = (pin_num / 8); 1719 1720 /* The bank0:16 and bank1:32 pins are located in PMU */ 1721 if ((bank->bank_num == 0) || (bank->bank_num == 1)) 1722 *regmap = info->regmap_pmu; 1723 else 1724 *regmap = info->regmap_base; 1725 1726 *reg = bank->drv[drv_num].offset; 1727 if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) || 1728 (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY)) 1729 *bit = (pin_num % 8) * 3; 1730 else 1731 *bit = (pin_num % 8) * 2; 1732 } 1733 1734 static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = { 1735 { 2, 4, 8, 12, -1, -1, -1, -1 }, 1736 { 3, 6, 9, 12, -1, -1, -1, -1 }, 1737 { 5, 10, 15, 20, -1, -1, -1, -1 }, 1738 { 4, 6, 8, 10, 12, 14, 16, 18 }, 1739 { 4, 7, 10, 13, 16, 19, 22, 26 } 1740 }; 1741 1742 static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank, 1743 int pin_num) 1744 { 1745 struct rockchip_pinctrl *info = bank->drvdata; 1746 struct rockchip_pin_ctrl *ctrl = info->ctrl; 1747 struct regmap *regmap; 1748 int reg, ret; 1749 u32 data, temp, rmask_bits; 1750 u8 bit; 1751 int drv_type = bank->drv[pin_num / 8].drv_type; 1752 1753 ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); 1754 1755 switch (drv_type) { 1756 case DRV_TYPE_IO_1V8_3V0_AUTO: 1757 case DRV_TYPE_IO_3V3_ONLY: 1758 rmask_bits = RK3399_DRV_3BITS_PER_PIN; 1759 switch (bit) { 1760 case 0 ... 12: 1761 /* regular case, nothing to do */ 1762 break; 1763 case 15: 1764 /* 1765 * drive-strength offset is special, as it is 1766 * spread over 2 registers 1767 */ 1768 ret = regmap_read(regmap, reg, &data); 1769 if (ret) 1770 return ret; 1771 1772 ret = regmap_read(regmap, reg + 0x4, &temp); 1773 if (ret) 1774 return ret; 1775 1776 /* 1777 * the bit data[15] contains bit 0 of the value 1778 * while temp[1:0] contains bits 2 and 1 1779 */ 1780 data >>= 15; 1781 temp &= 0x3; 1782 temp <<= 1; 1783 data |= temp; 1784 1785 return rockchip_perpin_drv_list[drv_type][data]; 1786 case 18 ... 21: 1787 /* setting fully enclosed in the second register */ 1788 reg += 4; 1789 bit -= 16; 1790 break; 1791 default: 1792 dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n", 1793 bit, drv_type); 1794 return -EINVAL; 1795 } 1796 1797 break; 1798 case DRV_TYPE_IO_DEFAULT: 1799 case DRV_TYPE_IO_1V8_OR_3V0: 1800 case DRV_TYPE_IO_1V8_ONLY: 1801 rmask_bits = RK3288_DRV_BITS_PER_PIN; 1802 break; 1803 default: 1804 dev_err(info->dev, "unsupported pinctrl drive type: %d\n", 1805 drv_type); 1806 return -EINVAL; 1807 } 1808 1809 ret = regmap_read(regmap, reg, &data); 1810 if (ret) 1811 return ret; 1812 1813 data >>= bit; 1814 data &= (1 << rmask_bits) - 1; 1815 1816 return rockchip_perpin_drv_list[drv_type][data]; 1817 } 1818 1819 static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank, 1820 int pin_num, int strength) 1821 { 1822 struct rockchip_pinctrl *info = bank->drvdata; 1823 struct rockchip_pin_ctrl *ctrl = info->ctrl; 1824 struct regmap *regmap; 1825 int reg, ret, i; 1826 u32 data, rmask, rmask_bits, temp; 1827 u8 bit; 1828 int drv_type = bank->drv[pin_num / 8].drv_type; 1829 1830 dev_dbg(info->dev, "setting drive of GPIO%d-%d to %d\n", 1831 bank->bank_num, pin_num, strength); 1832 1833 ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); 1834 1835 ret = -EINVAL; 1836 for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) { 1837 if (rockchip_perpin_drv_list[drv_type][i] == strength) { 1838 ret = i; 1839 break; 1840 } else if (rockchip_perpin_drv_list[drv_type][i] < 0) { 1841 ret = rockchip_perpin_drv_list[drv_type][i]; 1842 break; 1843 } 1844 } 1845 1846 if (ret < 0) { 1847 dev_err(info->dev, "unsupported driver strength %d\n", 1848 strength); 1849 return ret; 1850 } 1851 1852 switch (drv_type) { 1853 case DRV_TYPE_IO_1V8_3V0_AUTO: 1854 case DRV_TYPE_IO_3V3_ONLY: 1855 rmask_bits = RK3399_DRV_3BITS_PER_PIN; 1856 switch (bit) { 1857 case 0 ... 12: 1858 /* regular case, nothing to do */ 1859 break; 1860 case 15: 1861 /* 1862 * drive-strength offset is special, as it is spread 1863 * over 2 registers, the bit data[15] contains bit 0 1864 * of the value while temp[1:0] contains bits 2 and 1 1865 */ 1866 data = (ret & 0x1) << 15; 1867 temp = (ret >> 0x1) & 0x3; 1868 1869 rmask = BIT(15) | BIT(31); 1870 data |= BIT(31); 1871 ret = regmap_update_bits(regmap, reg, rmask, data); 1872 if (ret) 1873 return ret; 1874 1875 rmask = 0x3 | (0x3 << 16); 1876 temp |= (0x3 << 16); 1877 reg += 0x4; 1878 ret = regmap_update_bits(regmap, reg, rmask, temp); 1879 1880 return ret; 1881 case 18 ... 21: 1882 /* setting fully enclosed in the second register */ 1883 reg += 4; 1884 bit -= 16; 1885 break; 1886 default: 1887 dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n", 1888 bit, drv_type); 1889 return -EINVAL; 1890 } 1891 break; 1892 case DRV_TYPE_IO_DEFAULT: 1893 case DRV_TYPE_IO_1V8_OR_3V0: 1894 case DRV_TYPE_IO_1V8_ONLY: 1895 rmask_bits = RK3288_DRV_BITS_PER_PIN; 1896 break; 1897 default: 1898 dev_err(info->dev, "unsupported pinctrl drive type: %d\n", 1899 drv_type); 1900 return -EINVAL; 1901 } 1902 1903 /* enable the write to the equivalent lower bits */ 1904 data = ((1 << rmask_bits) - 1) << (bit + 16); 1905 rmask = data | (data >> 16); 1906 data |= (ret << bit); 1907 1908 ret = regmap_update_bits(regmap, reg, rmask, data); 1909 1910 return ret; 1911 } 1912 1913 static int rockchip_pull_list[PULL_TYPE_MAX][4] = { 1914 { 1915 PIN_CONFIG_BIAS_DISABLE, 1916 PIN_CONFIG_BIAS_PULL_UP, 1917 PIN_CONFIG_BIAS_PULL_DOWN, 1918 PIN_CONFIG_BIAS_BUS_HOLD 1919 }, 1920 { 1921 PIN_CONFIG_BIAS_DISABLE, 1922 PIN_CONFIG_BIAS_PULL_DOWN, 1923 PIN_CONFIG_BIAS_DISABLE, 1924 PIN_CONFIG_BIAS_PULL_UP 1925 }, 1926 }; 1927 1928 static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num) 1929 { 1930 struct rockchip_pinctrl *info = bank->drvdata; 1931 struct rockchip_pin_ctrl *ctrl = info->ctrl; 1932 struct regmap *regmap; 1933 int reg, ret, pull_type; 1934 u8 bit; 1935 u32 data; 1936 1937 /* rk3066b does support any pulls */ 1938 if (ctrl->type == RK3066B) 1939 return PIN_CONFIG_BIAS_DISABLE; 1940 1941 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); 1942 1943 ret = regmap_read(regmap, reg, &data); 1944 if (ret) 1945 return ret; 1946 1947 switch (ctrl->type) { 1948 case RK2928: 1949 case RK3128: 1950 return !(data & BIT(bit)) 1951 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT 1952 : PIN_CONFIG_BIAS_DISABLE; 1953 case PX30: 1954 case RV1108: 1955 case RK3188: 1956 case RK3288: 1957 case RK3368: 1958 case RK3399: 1959 pull_type = bank->pull_type[pin_num / 8]; 1960 data >>= bit; 1961 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1; 1962 1963 return rockchip_pull_list[pull_type][data]; 1964 default: 1965 dev_err(info->dev, "unsupported pinctrl type\n"); 1966 return -EINVAL; 1967 }; 1968 } 1969 1970 static int rockchip_set_pull(struct rockchip_pin_bank *bank, 1971 int pin_num, int pull) 1972 { 1973 struct rockchip_pinctrl *info = bank->drvdata; 1974 struct rockchip_pin_ctrl *ctrl = info->ctrl; 1975 struct regmap *regmap; 1976 int reg, ret, i, pull_type; 1977 u8 bit; 1978 u32 data, rmask; 1979 1980 dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n", 1981 bank->bank_num, pin_num, pull); 1982 1983 /* rk3066b does support any pulls */ 1984 if (ctrl->type == RK3066B) 1985 return pull ? -EINVAL : 0; 1986 1987 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); 1988 1989 switch (ctrl->type) { 1990 case RK2928: 1991 case RK3128: 1992 data = BIT(bit + 16); 1993 if (pull == PIN_CONFIG_BIAS_DISABLE) 1994 data |= BIT(bit); 1995 ret = regmap_write(regmap, reg, data); 1996 break; 1997 case PX30: 1998 case RV1108: 1999 case RK3188: 2000 case RK3288: 2001 case RK3368: 2002 case RK3399: 2003 pull_type = bank->pull_type[pin_num / 8]; 2004 ret = -EINVAL; 2005 for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]); 2006 i++) { 2007 if (rockchip_pull_list[pull_type][i] == pull) { 2008 ret = i; 2009 break; 2010 } 2011 } 2012 2013 if (ret < 0) { 2014 dev_err(info->dev, "unsupported pull setting %d\n", 2015 pull); 2016 return ret; 2017 } 2018 2019 /* enable the write to the equivalent lower bits */ 2020 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16); 2021 rmask = data | (data >> 16); 2022 data |= (ret << bit); 2023 2024 ret = regmap_update_bits(regmap, reg, rmask, data); 2025 break; 2026 default: 2027 dev_err(info->dev, "unsupported pinctrl type\n"); 2028 return -EINVAL; 2029 } 2030 2031 return ret; 2032 } 2033 2034 #define RK3328_SCHMITT_BITS_PER_PIN 1 2035 #define RK3328_SCHMITT_PINS_PER_REG 16 2036 #define RK3328_SCHMITT_BANK_STRIDE 8 2037 #define RK3328_SCHMITT_GRF_OFFSET 0x380 2038 2039 static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 2040 int pin_num, 2041 struct regmap **regmap, 2042 int *reg, u8 *bit) 2043 { 2044 struct rockchip_pinctrl *info = bank->drvdata; 2045 2046 *regmap = info->regmap_base; 2047 *reg = RK3328_SCHMITT_GRF_OFFSET; 2048 2049 *reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE; 2050 *reg += ((pin_num / RK3328_SCHMITT_PINS_PER_REG) * 4); 2051 *bit = pin_num % RK3328_SCHMITT_PINS_PER_REG; 2052 2053 return 0; 2054 } 2055 2056 static int rockchip_get_schmitt(struct rockchip_pin_bank *bank, int pin_num) 2057 { 2058 struct rockchip_pinctrl *info = bank->drvdata; 2059 struct rockchip_pin_ctrl *ctrl = info->ctrl; 2060 struct regmap *regmap; 2061 int reg, ret; 2062 u8 bit; 2063 u32 data; 2064 2065 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit); 2066 if (ret) 2067 return ret; 2068 2069 ret = regmap_read(regmap, reg, &data); 2070 if (ret) 2071 return ret; 2072 2073 data >>= bit; 2074 return data & 0x1; 2075 } 2076 2077 static int rockchip_set_schmitt(struct rockchip_pin_bank *bank, 2078 int pin_num, int enable) 2079 { 2080 struct rockchip_pinctrl *info = bank->drvdata; 2081 struct rockchip_pin_ctrl *ctrl = info->ctrl; 2082 struct regmap *regmap; 2083 int reg, ret; 2084 u8 bit; 2085 u32 data, rmask; 2086 2087 dev_dbg(info->dev, "setting input schmitt of GPIO%d-%d to %d\n", 2088 bank->bank_num, pin_num, enable); 2089 2090 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit); 2091 if (ret) 2092 return ret; 2093 2094 /* enable the write to the equivalent lower bits */ 2095 data = BIT(bit + 16) | (enable << bit); 2096 rmask = BIT(bit + 16) | BIT(bit); 2097 2098 return regmap_update_bits(regmap, reg, rmask, data); 2099 } 2100 2101 /* 2102 * Pinmux_ops handling 2103 */ 2104 2105 static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev) 2106 { 2107 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 2108 2109 return info->nfunctions; 2110 } 2111 2112 static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev, 2113 unsigned selector) 2114 { 2115 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 2116 2117 return info->functions[selector].name; 2118 } 2119 2120 static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev, 2121 unsigned selector, const char * const **groups, 2122 unsigned * const num_groups) 2123 { 2124 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 2125 2126 *groups = info->functions[selector].groups; 2127 *num_groups = info->functions[selector].ngroups; 2128 2129 return 0; 2130 } 2131 2132 static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector, 2133 unsigned group) 2134 { 2135 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 2136 const unsigned int *pins = info->groups[group].pins; 2137 const struct rockchip_pin_config *data = info->groups[group].data; 2138 struct rockchip_pin_bank *bank; 2139 int cnt, ret = 0; 2140 2141 dev_dbg(info->dev, "enable function %s group %s\n", 2142 info->functions[selector].name, info->groups[group].name); 2143 2144 /* 2145 * for each pin in the pin group selected, program the corresponding 2146 * pin function number in the config register. 2147 */ 2148 for (cnt = 0; cnt < info->groups[group].npins; cnt++) { 2149 bank = pin_to_bank(info, pins[cnt]); 2150 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 2151 data[cnt].func); 2152 if (ret) 2153 break; 2154 } 2155 2156 if (ret) { 2157 /* revert the already done pin settings */ 2158 for (cnt--; cnt >= 0; cnt--) 2159 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0); 2160 2161 return ret; 2162 } 2163 2164 return 0; 2165 } 2166 2167 static int rockchip_gpio_get_direction(struct gpio_chip *chip, unsigned offset) 2168 { 2169 struct rockchip_pin_bank *bank = gpiochip_get_data(chip); 2170 u32 data; 2171 int ret; 2172 2173 ret = clk_enable(bank->clk); 2174 if (ret < 0) { 2175 dev_err(bank->drvdata->dev, 2176 "failed to enable clock for bank %s\n", bank->name); 2177 return ret; 2178 } 2179 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); 2180 clk_disable(bank->clk); 2181 2182 return !(data & BIT(offset)); 2183 } 2184 2185 /* 2186 * The calls to gpio_direction_output() and gpio_direction_input() 2187 * leads to this function call (via the pinctrl_gpio_direction_{input|output}() 2188 * function called from the gpiolib interface). 2189 */ 2190 static int _rockchip_pmx_gpio_set_direction(struct gpio_chip *chip, 2191 int pin, bool input) 2192 { 2193 struct rockchip_pin_bank *bank; 2194 int ret; 2195 unsigned long flags; 2196 u32 data; 2197 2198 bank = gpiochip_get_data(chip); 2199 2200 ret = rockchip_set_mux(bank, pin, RK_FUNC_GPIO); 2201 if (ret < 0) 2202 return ret; 2203 2204 clk_enable(bank->clk); 2205 raw_spin_lock_irqsave(&bank->slock, flags); 2206 2207 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); 2208 /* set bit to 1 for output, 0 for input */ 2209 if (!input) 2210 data |= BIT(pin); 2211 else 2212 data &= ~BIT(pin); 2213 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR); 2214 2215 raw_spin_unlock_irqrestore(&bank->slock, flags); 2216 clk_disable(bank->clk); 2217 2218 return 0; 2219 } 2220 2221 static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, 2222 struct pinctrl_gpio_range *range, 2223 unsigned offset, bool input) 2224 { 2225 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 2226 struct gpio_chip *chip; 2227 int pin; 2228 2229 chip = range->gc; 2230 pin = offset - chip->base; 2231 dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n", 2232 offset, range->name, pin, input ? "input" : "output"); 2233 2234 return _rockchip_pmx_gpio_set_direction(chip, offset - chip->base, 2235 input); 2236 } 2237 2238 static const struct pinmux_ops rockchip_pmx_ops = { 2239 .get_functions_count = rockchip_pmx_get_funcs_count, 2240 .get_function_name = rockchip_pmx_get_func_name, 2241 .get_function_groups = rockchip_pmx_get_groups, 2242 .set_mux = rockchip_pmx_set, 2243 .gpio_set_direction = rockchip_pmx_gpio_set_direction, 2244 }; 2245 2246 /* 2247 * Pinconf_ops handling 2248 */ 2249 2250 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl, 2251 enum pin_config_param pull) 2252 { 2253 switch (ctrl->type) { 2254 case RK2928: 2255 case RK3128: 2256 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT || 2257 pull == PIN_CONFIG_BIAS_DISABLE); 2258 case RK3066B: 2259 return pull ? false : true; 2260 case PX30: 2261 case RV1108: 2262 case RK3188: 2263 case RK3288: 2264 case RK3368: 2265 case RK3399: 2266 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT); 2267 } 2268 2269 return false; 2270 } 2271 2272 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value); 2273 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset); 2274 2275 /* set the pin config settings for a specified pin */ 2276 static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 2277 unsigned long *configs, unsigned num_configs) 2278 { 2279 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 2280 struct rockchip_pin_bank *bank = pin_to_bank(info, pin); 2281 enum pin_config_param param; 2282 u32 arg; 2283 int i; 2284 int rc; 2285 2286 for (i = 0; i < num_configs; i++) { 2287 param = pinconf_to_config_param(configs[i]); 2288 arg = pinconf_to_config_argument(configs[i]); 2289 2290 switch (param) { 2291 case PIN_CONFIG_BIAS_DISABLE: 2292 rc = rockchip_set_pull(bank, pin - bank->pin_base, 2293 param); 2294 if (rc) 2295 return rc; 2296 break; 2297 case PIN_CONFIG_BIAS_PULL_UP: 2298 case PIN_CONFIG_BIAS_PULL_DOWN: 2299 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: 2300 case PIN_CONFIG_BIAS_BUS_HOLD: 2301 if (!rockchip_pinconf_pull_valid(info->ctrl, param)) 2302 return -ENOTSUPP; 2303 2304 if (!arg) 2305 return -EINVAL; 2306 2307 rc = rockchip_set_pull(bank, pin - bank->pin_base, 2308 param); 2309 if (rc) 2310 return rc; 2311 break; 2312 case PIN_CONFIG_OUTPUT: 2313 rockchip_gpio_set(&bank->gpio_chip, 2314 pin - bank->pin_base, arg); 2315 rc = _rockchip_pmx_gpio_set_direction(&bank->gpio_chip, 2316 pin - bank->pin_base, false); 2317 if (rc) 2318 return rc; 2319 break; 2320 case PIN_CONFIG_DRIVE_STRENGTH: 2321 /* rk3288 is the first with per-pin drive-strength */ 2322 if (!info->ctrl->drv_calc_reg) 2323 return -ENOTSUPP; 2324 2325 rc = rockchip_set_drive_perpin(bank, 2326 pin - bank->pin_base, arg); 2327 if (rc < 0) 2328 return rc; 2329 break; 2330 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 2331 if (!info->ctrl->schmitt_calc_reg) 2332 return -ENOTSUPP; 2333 2334 rc = rockchip_set_schmitt(bank, 2335 pin - bank->pin_base, arg); 2336 if (rc < 0) 2337 return rc; 2338 break; 2339 default: 2340 return -ENOTSUPP; 2341 break; 2342 } 2343 } /* for each config */ 2344 2345 return 0; 2346 } 2347 2348 /* get the pin config settings for a specified pin */ 2349 static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, 2350 unsigned long *config) 2351 { 2352 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 2353 struct rockchip_pin_bank *bank = pin_to_bank(info, pin); 2354 enum pin_config_param param = pinconf_to_config_param(*config); 2355 u16 arg; 2356 int rc; 2357 2358 switch (param) { 2359 case PIN_CONFIG_BIAS_DISABLE: 2360 if (rockchip_get_pull(bank, pin - bank->pin_base) != param) 2361 return -EINVAL; 2362 2363 arg = 0; 2364 break; 2365 case PIN_CONFIG_BIAS_PULL_UP: 2366 case PIN_CONFIG_BIAS_PULL_DOWN: 2367 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: 2368 case PIN_CONFIG_BIAS_BUS_HOLD: 2369 if (!rockchip_pinconf_pull_valid(info->ctrl, param)) 2370 return -ENOTSUPP; 2371 2372 if (rockchip_get_pull(bank, pin - bank->pin_base) != param) 2373 return -EINVAL; 2374 2375 arg = 1; 2376 break; 2377 case PIN_CONFIG_OUTPUT: 2378 rc = rockchip_get_mux(bank, pin - bank->pin_base); 2379 if (rc != RK_FUNC_GPIO) 2380 return -EINVAL; 2381 2382 rc = rockchip_gpio_get(&bank->gpio_chip, pin - bank->pin_base); 2383 if (rc < 0) 2384 return rc; 2385 2386 arg = rc ? 1 : 0; 2387 break; 2388 case PIN_CONFIG_DRIVE_STRENGTH: 2389 /* rk3288 is the first with per-pin drive-strength */ 2390 if (!info->ctrl->drv_calc_reg) 2391 return -ENOTSUPP; 2392 2393 rc = rockchip_get_drive_perpin(bank, pin - bank->pin_base); 2394 if (rc < 0) 2395 return rc; 2396 2397 arg = rc; 2398 break; 2399 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 2400 if (!info->ctrl->schmitt_calc_reg) 2401 return -ENOTSUPP; 2402 2403 rc = rockchip_get_schmitt(bank, pin - bank->pin_base); 2404 if (rc < 0) 2405 return rc; 2406 2407 arg = rc; 2408 break; 2409 default: 2410 return -ENOTSUPP; 2411 break; 2412 } 2413 2414 *config = pinconf_to_config_packed(param, arg); 2415 2416 return 0; 2417 } 2418 2419 static const struct pinconf_ops rockchip_pinconf_ops = { 2420 .pin_config_get = rockchip_pinconf_get, 2421 .pin_config_set = rockchip_pinconf_set, 2422 .is_generic = true, 2423 }; 2424 2425 static const struct of_device_id rockchip_bank_match[] = { 2426 { .compatible = "rockchip,gpio-bank" }, 2427 { .compatible = "rockchip,rk3188-gpio-bank0" }, 2428 {}, 2429 }; 2430 2431 static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info, 2432 struct device_node *np) 2433 { 2434 struct device_node *child; 2435 2436 for_each_child_of_node(np, child) { 2437 if (of_match_node(rockchip_bank_match, child)) 2438 continue; 2439 2440 info->nfunctions++; 2441 info->ngroups += of_get_child_count(child); 2442 } 2443 } 2444 2445 static int rockchip_pinctrl_parse_groups(struct device_node *np, 2446 struct rockchip_pin_group *grp, 2447 struct rockchip_pinctrl *info, 2448 u32 index) 2449 { 2450 struct rockchip_pin_bank *bank; 2451 int size; 2452 const __be32 *list; 2453 int num; 2454 int i, j; 2455 int ret; 2456 2457 dev_dbg(info->dev, "group(%d): %s\n", index, np->name); 2458 2459 /* Initialise group */ 2460 grp->name = np->name; 2461 2462 /* 2463 * the binding format is rockchip,pins = <bank pin mux CONFIG>, 2464 * do sanity check and calculate pins number 2465 */ 2466 list = of_get_property(np, "rockchip,pins", &size); 2467 /* we do not check return since it's safe node passed down */ 2468 size /= sizeof(*list); 2469 if (!size || size % 4) { 2470 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n"); 2471 return -EINVAL; 2472 } 2473 2474 grp->npins = size / 4; 2475 2476 grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int), 2477 GFP_KERNEL); 2478 grp->data = devm_kzalloc(info->dev, grp->npins * 2479 sizeof(struct rockchip_pin_config), 2480 GFP_KERNEL); 2481 if (!grp->pins || !grp->data) 2482 return -ENOMEM; 2483 2484 for (i = 0, j = 0; i < size; i += 4, j++) { 2485 const __be32 *phandle; 2486 struct device_node *np_config; 2487 2488 num = be32_to_cpu(*list++); 2489 bank = bank_num_to_bank(info, num); 2490 if (IS_ERR(bank)) 2491 return PTR_ERR(bank); 2492 2493 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++); 2494 grp->data[j].func = be32_to_cpu(*list++); 2495 2496 phandle = list++; 2497 if (!phandle) 2498 return -EINVAL; 2499 2500 np_config = of_find_node_by_phandle(be32_to_cpup(phandle)); 2501 ret = pinconf_generic_parse_dt_config(np_config, NULL, 2502 &grp->data[j].configs, &grp->data[j].nconfigs); 2503 if (ret) 2504 return ret; 2505 } 2506 2507 return 0; 2508 } 2509 2510 static int rockchip_pinctrl_parse_functions(struct device_node *np, 2511 struct rockchip_pinctrl *info, 2512 u32 index) 2513 { 2514 struct device_node *child; 2515 struct rockchip_pmx_func *func; 2516 struct rockchip_pin_group *grp; 2517 int ret; 2518 static u32 grp_index; 2519 u32 i = 0; 2520 2521 dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name); 2522 2523 func = &info->functions[index]; 2524 2525 /* Initialise function */ 2526 func->name = np->name; 2527 func->ngroups = of_get_child_count(np); 2528 if (func->ngroups <= 0) 2529 return 0; 2530 2531 func->groups = devm_kzalloc(info->dev, 2532 func->ngroups * sizeof(char *), GFP_KERNEL); 2533 if (!func->groups) 2534 return -ENOMEM; 2535 2536 for_each_child_of_node(np, child) { 2537 func->groups[i] = child->name; 2538 grp = &info->groups[grp_index++]; 2539 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++); 2540 if (ret) { 2541 of_node_put(child); 2542 return ret; 2543 } 2544 } 2545 2546 return 0; 2547 } 2548 2549 static int rockchip_pinctrl_parse_dt(struct platform_device *pdev, 2550 struct rockchip_pinctrl *info) 2551 { 2552 struct device *dev = &pdev->dev; 2553 struct device_node *np = dev->of_node; 2554 struct device_node *child; 2555 int ret; 2556 int i; 2557 2558 rockchip_pinctrl_child_count(info, np); 2559 2560 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions); 2561 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups); 2562 2563 info->functions = devm_kzalloc(dev, info->nfunctions * 2564 sizeof(struct rockchip_pmx_func), 2565 GFP_KERNEL); 2566 if (!info->functions) 2567 return -EINVAL; 2568 2569 info->groups = devm_kzalloc(dev, info->ngroups * 2570 sizeof(struct rockchip_pin_group), 2571 GFP_KERNEL); 2572 if (!info->groups) 2573 return -EINVAL; 2574 2575 i = 0; 2576 2577 for_each_child_of_node(np, child) { 2578 if (of_match_node(rockchip_bank_match, child)) 2579 continue; 2580 2581 ret = rockchip_pinctrl_parse_functions(child, info, i++); 2582 if (ret) { 2583 dev_err(&pdev->dev, "failed to parse function\n"); 2584 of_node_put(child); 2585 return ret; 2586 } 2587 } 2588 2589 return 0; 2590 } 2591 2592 static int rockchip_pinctrl_register(struct platform_device *pdev, 2593 struct rockchip_pinctrl *info) 2594 { 2595 struct pinctrl_desc *ctrldesc = &info->pctl; 2596 struct pinctrl_pin_desc *pindesc, *pdesc; 2597 struct rockchip_pin_bank *pin_bank; 2598 int pin, bank, ret; 2599 int k; 2600 2601 ctrldesc->name = "rockchip-pinctrl"; 2602 ctrldesc->owner = THIS_MODULE; 2603 ctrldesc->pctlops = &rockchip_pctrl_ops; 2604 ctrldesc->pmxops = &rockchip_pmx_ops; 2605 ctrldesc->confops = &rockchip_pinconf_ops; 2606 2607 pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) * 2608 info->ctrl->nr_pins, GFP_KERNEL); 2609 if (!pindesc) 2610 return -ENOMEM; 2611 2612 ctrldesc->pins = pindesc; 2613 ctrldesc->npins = info->ctrl->nr_pins; 2614 2615 pdesc = pindesc; 2616 for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) { 2617 pin_bank = &info->ctrl->pin_banks[bank]; 2618 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) { 2619 pdesc->number = k; 2620 pdesc->name = kasprintf(GFP_KERNEL, "%s-%d", 2621 pin_bank->name, pin); 2622 pdesc++; 2623 } 2624 } 2625 2626 ret = rockchip_pinctrl_parse_dt(pdev, info); 2627 if (ret) 2628 return ret; 2629 2630 info->pctl_dev = devm_pinctrl_register(&pdev->dev, ctrldesc, info); 2631 if (IS_ERR(info->pctl_dev)) { 2632 dev_err(&pdev->dev, "could not register pinctrl driver\n"); 2633 return PTR_ERR(info->pctl_dev); 2634 } 2635 2636 for (bank = 0; bank < info->ctrl->nr_banks; ++bank) { 2637 pin_bank = &info->ctrl->pin_banks[bank]; 2638 pin_bank->grange.name = pin_bank->name; 2639 pin_bank->grange.id = bank; 2640 pin_bank->grange.pin_base = pin_bank->pin_base; 2641 pin_bank->grange.base = pin_bank->gpio_chip.base; 2642 pin_bank->grange.npins = pin_bank->gpio_chip.ngpio; 2643 pin_bank->grange.gc = &pin_bank->gpio_chip; 2644 pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange); 2645 } 2646 2647 return 0; 2648 } 2649 2650 /* 2651 * GPIO handling 2652 */ 2653 2654 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value) 2655 { 2656 struct rockchip_pin_bank *bank = gpiochip_get_data(gc); 2657 void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR; 2658 unsigned long flags; 2659 u32 data; 2660 2661 clk_enable(bank->clk); 2662 raw_spin_lock_irqsave(&bank->slock, flags); 2663 2664 data = readl(reg); 2665 data &= ~BIT(offset); 2666 if (value) 2667 data |= BIT(offset); 2668 writel(data, reg); 2669 2670 raw_spin_unlock_irqrestore(&bank->slock, flags); 2671 clk_disable(bank->clk); 2672 } 2673 2674 /* 2675 * Returns the level of the pin for input direction and setting of the DR 2676 * register for output gpios. 2677 */ 2678 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset) 2679 { 2680 struct rockchip_pin_bank *bank = gpiochip_get_data(gc); 2681 u32 data; 2682 2683 clk_enable(bank->clk); 2684 data = readl(bank->reg_base + GPIO_EXT_PORT); 2685 clk_disable(bank->clk); 2686 data >>= offset; 2687 data &= 1; 2688 return data; 2689 } 2690 2691 /* 2692 * gpiolib gpio_direction_input callback function. The setting of the pin 2693 * mux function as 'gpio input' will be handled by the pinctrl subsystem 2694 * interface. 2695 */ 2696 static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset) 2697 { 2698 return pinctrl_gpio_direction_input(gc->base + offset); 2699 } 2700 2701 /* 2702 * gpiolib gpio_direction_output callback function. The setting of the pin 2703 * mux function as 'gpio output' will be handled by the pinctrl subsystem 2704 * interface. 2705 */ 2706 static int rockchip_gpio_direction_output(struct gpio_chip *gc, 2707 unsigned offset, int value) 2708 { 2709 rockchip_gpio_set(gc, offset, value); 2710 return pinctrl_gpio_direction_output(gc->base + offset); 2711 } 2712 2713 static void rockchip_gpio_set_debounce(struct gpio_chip *gc, 2714 unsigned int offset, bool enable) 2715 { 2716 struct rockchip_pin_bank *bank = gpiochip_get_data(gc); 2717 void __iomem *reg = bank->reg_base + GPIO_DEBOUNCE; 2718 unsigned long flags; 2719 u32 data; 2720 2721 clk_enable(bank->clk); 2722 raw_spin_lock_irqsave(&bank->slock, flags); 2723 2724 data = readl(reg); 2725 if (enable) 2726 data |= BIT(offset); 2727 else 2728 data &= ~BIT(offset); 2729 writel(data, reg); 2730 2731 raw_spin_unlock_irqrestore(&bank->slock, flags); 2732 clk_disable(bank->clk); 2733 } 2734 2735 /* 2736 * gpiolib set_config callback function. The setting of the pin 2737 * mux function as 'gpio output' will be handled by the pinctrl subsystem 2738 * interface. 2739 */ 2740 static int rockchip_gpio_set_config(struct gpio_chip *gc, unsigned int offset, 2741 unsigned long config) 2742 { 2743 enum pin_config_param param = pinconf_to_config_param(config); 2744 2745 switch (param) { 2746 case PIN_CONFIG_INPUT_DEBOUNCE: 2747 rockchip_gpio_set_debounce(gc, offset, true); 2748 /* 2749 * Rockchip's gpio could only support up to one period 2750 * of the debounce clock(pclk), which is far away from 2751 * satisftying the requirement, as pclk is usually near 2752 * 100MHz shared by all peripherals. So the fact is it 2753 * has crippled debounce capability could only be useful 2754 * to prevent any spurious glitches from waking up the system 2755 * if the gpio is conguired as wakeup interrupt source. Let's 2756 * still return -ENOTSUPP as before, to make sure the caller 2757 * of gpiod_set_debounce won't change its behaviour. 2758 */ 2759 default: 2760 return -ENOTSUPP; 2761 } 2762 } 2763 2764 /* 2765 * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin 2766 * and a virtual IRQ, if not already present. 2767 */ 2768 static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset) 2769 { 2770 struct rockchip_pin_bank *bank = gpiochip_get_data(gc); 2771 unsigned int virq; 2772 2773 if (!bank->domain) 2774 return -ENXIO; 2775 2776 virq = irq_create_mapping(bank->domain, offset); 2777 2778 return (virq) ? : -ENXIO; 2779 } 2780 2781 static const struct gpio_chip rockchip_gpiolib_chip = { 2782 .request = gpiochip_generic_request, 2783 .free = gpiochip_generic_free, 2784 .set = rockchip_gpio_set, 2785 .get = rockchip_gpio_get, 2786 .get_direction = rockchip_gpio_get_direction, 2787 .direction_input = rockchip_gpio_direction_input, 2788 .direction_output = rockchip_gpio_direction_output, 2789 .set_config = rockchip_gpio_set_config, 2790 .to_irq = rockchip_gpio_to_irq, 2791 .owner = THIS_MODULE, 2792 }; 2793 2794 /* 2795 * Interrupt handling 2796 */ 2797 2798 static void rockchip_irq_demux(struct irq_desc *desc) 2799 { 2800 struct irq_chip *chip = irq_desc_get_chip(desc); 2801 struct rockchip_pin_bank *bank = irq_desc_get_handler_data(desc); 2802 u32 pend; 2803 2804 dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name); 2805 2806 chained_irq_enter(chip, desc); 2807 2808 pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS); 2809 2810 while (pend) { 2811 unsigned int irq, virq; 2812 2813 irq = __ffs(pend); 2814 pend &= ~BIT(irq); 2815 virq = irq_linear_revmap(bank->domain, irq); 2816 2817 if (!virq) { 2818 dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq); 2819 continue; 2820 } 2821 2822 dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq); 2823 2824 /* 2825 * Triggering IRQ on both rising and falling edge 2826 * needs manual intervention. 2827 */ 2828 if (bank->toggle_edge_mode & BIT(irq)) { 2829 u32 data, data_old, polarity; 2830 unsigned long flags; 2831 2832 data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT); 2833 do { 2834 raw_spin_lock_irqsave(&bank->slock, flags); 2835 2836 polarity = readl_relaxed(bank->reg_base + 2837 GPIO_INT_POLARITY); 2838 if (data & BIT(irq)) 2839 polarity &= ~BIT(irq); 2840 else 2841 polarity |= BIT(irq); 2842 writel(polarity, 2843 bank->reg_base + GPIO_INT_POLARITY); 2844 2845 raw_spin_unlock_irqrestore(&bank->slock, flags); 2846 2847 data_old = data; 2848 data = readl_relaxed(bank->reg_base + 2849 GPIO_EXT_PORT); 2850 } while ((data & BIT(irq)) != (data_old & BIT(irq))); 2851 } 2852 2853 generic_handle_irq(virq); 2854 } 2855 2856 chained_irq_exit(chip, desc); 2857 } 2858 2859 static int rockchip_irq_set_type(struct irq_data *d, unsigned int type) 2860 { 2861 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 2862 struct rockchip_pin_bank *bank = gc->private; 2863 u32 mask = BIT(d->hwirq); 2864 u32 polarity; 2865 u32 level; 2866 u32 data; 2867 unsigned long flags; 2868 int ret; 2869 2870 /* make sure the pin is configured as gpio input */ 2871 ret = rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO); 2872 if (ret < 0) 2873 return ret; 2874 2875 clk_enable(bank->clk); 2876 raw_spin_lock_irqsave(&bank->slock, flags); 2877 2878 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); 2879 data &= ~mask; 2880 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR); 2881 2882 raw_spin_unlock_irqrestore(&bank->slock, flags); 2883 2884 if (type & IRQ_TYPE_EDGE_BOTH) 2885 irq_set_handler_locked(d, handle_edge_irq); 2886 else 2887 irq_set_handler_locked(d, handle_level_irq); 2888 2889 raw_spin_lock_irqsave(&bank->slock, flags); 2890 irq_gc_lock(gc); 2891 2892 level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL); 2893 polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY); 2894 2895 switch (type) { 2896 case IRQ_TYPE_EDGE_BOTH: 2897 bank->toggle_edge_mode |= mask; 2898 level |= mask; 2899 2900 /* 2901 * Determine gpio state. If 1 next interrupt should be falling 2902 * otherwise rising. 2903 */ 2904 data = readl(bank->reg_base + GPIO_EXT_PORT); 2905 if (data & mask) 2906 polarity &= ~mask; 2907 else 2908 polarity |= mask; 2909 break; 2910 case IRQ_TYPE_EDGE_RISING: 2911 bank->toggle_edge_mode &= ~mask; 2912 level |= mask; 2913 polarity |= mask; 2914 break; 2915 case IRQ_TYPE_EDGE_FALLING: 2916 bank->toggle_edge_mode &= ~mask; 2917 level |= mask; 2918 polarity &= ~mask; 2919 break; 2920 case IRQ_TYPE_LEVEL_HIGH: 2921 bank->toggle_edge_mode &= ~mask; 2922 level &= ~mask; 2923 polarity |= mask; 2924 break; 2925 case IRQ_TYPE_LEVEL_LOW: 2926 bank->toggle_edge_mode &= ~mask; 2927 level &= ~mask; 2928 polarity &= ~mask; 2929 break; 2930 default: 2931 irq_gc_unlock(gc); 2932 raw_spin_unlock_irqrestore(&bank->slock, flags); 2933 clk_disable(bank->clk); 2934 return -EINVAL; 2935 } 2936 2937 writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL); 2938 writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY); 2939 2940 irq_gc_unlock(gc); 2941 raw_spin_unlock_irqrestore(&bank->slock, flags); 2942 clk_disable(bank->clk); 2943 2944 return 0; 2945 } 2946 2947 static void rockchip_irq_suspend(struct irq_data *d) 2948 { 2949 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 2950 struct rockchip_pin_bank *bank = gc->private; 2951 2952 clk_enable(bank->clk); 2953 bank->saved_masks = irq_reg_readl(gc, GPIO_INTMASK); 2954 irq_reg_writel(gc, ~gc->wake_active, GPIO_INTMASK); 2955 clk_disable(bank->clk); 2956 } 2957 2958 static void rockchip_irq_resume(struct irq_data *d) 2959 { 2960 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 2961 struct rockchip_pin_bank *bank = gc->private; 2962 2963 clk_enable(bank->clk); 2964 irq_reg_writel(gc, bank->saved_masks, GPIO_INTMASK); 2965 clk_disable(bank->clk); 2966 } 2967 2968 static void rockchip_irq_enable(struct irq_data *d) 2969 { 2970 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 2971 struct rockchip_pin_bank *bank = gc->private; 2972 2973 clk_enable(bank->clk); 2974 irq_gc_mask_clr_bit(d); 2975 } 2976 2977 static void rockchip_irq_disable(struct irq_data *d) 2978 { 2979 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 2980 struct rockchip_pin_bank *bank = gc->private; 2981 2982 irq_gc_mask_set_bit(d); 2983 clk_disable(bank->clk); 2984 } 2985 2986 static int rockchip_interrupts_register(struct platform_device *pdev, 2987 struct rockchip_pinctrl *info) 2988 { 2989 struct rockchip_pin_ctrl *ctrl = info->ctrl; 2990 struct rockchip_pin_bank *bank = ctrl->pin_banks; 2991 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; 2992 struct irq_chip_generic *gc; 2993 int ret; 2994 int i, j; 2995 2996 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 2997 if (!bank->valid) { 2998 dev_warn(&pdev->dev, "bank %s is not valid\n", 2999 bank->name); 3000 continue; 3001 } 3002 3003 ret = clk_enable(bank->clk); 3004 if (ret) { 3005 dev_err(&pdev->dev, "failed to enable clock for bank %s\n", 3006 bank->name); 3007 continue; 3008 } 3009 3010 bank->domain = irq_domain_add_linear(bank->of_node, 32, 3011 &irq_generic_chip_ops, NULL); 3012 if (!bank->domain) { 3013 dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n", 3014 bank->name); 3015 clk_disable(bank->clk); 3016 continue; 3017 } 3018 3019 ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1, 3020 "rockchip_gpio_irq", handle_level_irq, 3021 clr, 0, IRQ_GC_INIT_MASK_CACHE); 3022 if (ret) { 3023 dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n", 3024 bank->name); 3025 irq_domain_remove(bank->domain); 3026 clk_disable(bank->clk); 3027 continue; 3028 } 3029 3030 /* 3031 * Linux assumes that all interrupts start out disabled/masked. 3032 * Our driver only uses the concept of masked and always keeps 3033 * things enabled, so for us that's all masked and all enabled. 3034 */ 3035 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTMASK); 3036 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTEN); 3037 3038 gc = irq_get_domain_generic_chip(bank->domain, 0); 3039 gc->reg_base = bank->reg_base; 3040 gc->private = bank; 3041 gc->chip_types[0].regs.mask = GPIO_INTMASK; 3042 gc->chip_types[0].regs.ack = GPIO_PORTS_EOI; 3043 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit; 3044 gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit; 3045 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit; 3046 gc->chip_types[0].chip.irq_enable = rockchip_irq_enable; 3047 gc->chip_types[0].chip.irq_disable = rockchip_irq_disable; 3048 gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake; 3049 gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend; 3050 gc->chip_types[0].chip.irq_resume = rockchip_irq_resume; 3051 gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type; 3052 gc->wake_enabled = IRQ_MSK(bank->nr_pins); 3053 3054 irq_set_chained_handler_and_data(bank->irq, 3055 rockchip_irq_demux, bank); 3056 3057 /* map the gpio irqs here, when the clock is still running */ 3058 for (j = 0 ; j < 32 ; j++) 3059 irq_create_mapping(bank->domain, j); 3060 3061 clk_disable(bank->clk); 3062 } 3063 3064 return 0; 3065 } 3066 3067 static int rockchip_gpiolib_register(struct platform_device *pdev, 3068 struct rockchip_pinctrl *info) 3069 { 3070 struct rockchip_pin_ctrl *ctrl = info->ctrl; 3071 struct rockchip_pin_bank *bank = ctrl->pin_banks; 3072 struct gpio_chip *gc; 3073 int ret; 3074 int i; 3075 3076 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 3077 if (!bank->valid) { 3078 dev_warn(&pdev->dev, "bank %s is not valid\n", 3079 bank->name); 3080 continue; 3081 } 3082 3083 bank->gpio_chip = rockchip_gpiolib_chip; 3084 3085 gc = &bank->gpio_chip; 3086 gc->base = bank->pin_base; 3087 gc->ngpio = bank->nr_pins; 3088 gc->parent = &pdev->dev; 3089 gc->of_node = bank->of_node; 3090 gc->label = bank->name; 3091 3092 ret = gpiochip_add_data(gc, bank); 3093 if (ret) { 3094 dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n", 3095 gc->label, ret); 3096 goto fail; 3097 } 3098 } 3099 3100 rockchip_interrupts_register(pdev, info); 3101 3102 return 0; 3103 3104 fail: 3105 for (--i, --bank; i >= 0; --i, --bank) { 3106 if (!bank->valid) 3107 continue; 3108 gpiochip_remove(&bank->gpio_chip); 3109 } 3110 return ret; 3111 } 3112 3113 static int rockchip_gpiolib_unregister(struct platform_device *pdev, 3114 struct rockchip_pinctrl *info) 3115 { 3116 struct rockchip_pin_ctrl *ctrl = info->ctrl; 3117 struct rockchip_pin_bank *bank = ctrl->pin_banks; 3118 int i; 3119 3120 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 3121 if (!bank->valid) 3122 continue; 3123 gpiochip_remove(&bank->gpio_chip); 3124 } 3125 3126 return 0; 3127 } 3128 3129 static int rockchip_get_bank_data(struct rockchip_pin_bank *bank, 3130 struct rockchip_pinctrl *info) 3131 { 3132 struct resource res; 3133 void __iomem *base; 3134 3135 if (of_address_to_resource(bank->of_node, 0, &res)) { 3136 dev_err(info->dev, "cannot find IO resource for bank\n"); 3137 return -ENOENT; 3138 } 3139 3140 bank->reg_base = devm_ioremap_resource(info->dev, &res); 3141 if (IS_ERR(bank->reg_base)) 3142 return PTR_ERR(bank->reg_base); 3143 3144 /* 3145 * special case, where parts of the pull setting-registers are 3146 * part of the PMU register space 3147 */ 3148 if (of_device_is_compatible(bank->of_node, 3149 "rockchip,rk3188-gpio-bank0")) { 3150 struct device_node *node; 3151 3152 node = of_parse_phandle(bank->of_node->parent, 3153 "rockchip,pmu", 0); 3154 if (!node) { 3155 if (of_address_to_resource(bank->of_node, 1, &res)) { 3156 dev_err(info->dev, "cannot find IO resource for bank\n"); 3157 return -ENOENT; 3158 } 3159 3160 base = devm_ioremap_resource(info->dev, &res); 3161 if (IS_ERR(base)) 3162 return PTR_ERR(base); 3163 rockchip_regmap_config.max_register = 3164 resource_size(&res) - 4; 3165 rockchip_regmap_config.name = 3166 "rockchip,rk3188-gpio-bank0-pull"; 3167 bank->regmap_pull = devm_regmap_init_mmio(info->dev, 3168 base, 3169 &rockchip_regmap_config); 3170 } 3171 } 3172 3173 bank->irq = irq_of_parse_and_map(bank->of_node, 0); 3174 3175 bank->clk = of_clk_get(bank->of_node, 0); 3176 if (IS_ERR(bank->clk)) 3177 return PTR_ERR(bank->clk); 3178 3179 return clk_prepare(bank->clk); 3180 } 3181 3182 static const struct of_device_id rockchip_pinctrl_dt_match[]; 3183 3184 /* retrieve the soc specific data */ 3185 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data( 3186 struct rockchip_pinctrl *d, 3187 struct platform_device *pdev) 3188 { 3189 const struct of_device_id *match; 3190 struct device_node *node = pdev->dev.of_node; 3191 struct device_node *np; 3192 struct rockchip_pin_ctrl *ctrl; 3193 struct rockchip_pin_bank *bank; 3194 int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j; 3195 3196 match = of_match_node(rockchip_pinctrl_dt_match, node); 3197 ctrl = (struct rockchip_pin_ctrl *)match->data; 3198 3199 for_each_child_of_node(node, np) { 3200 if (!of_find_property(np, "gpio-controller", NULL)) 3201 continue; 3202 3203 bank = ctrl->pin_banks; 3204 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 3205 if (!strcmp(bank->name, np->name)) { 3206 bank->of_node = np; 3207 3208 if (!rockchip_get_bank_data(bank, d)) 3209 bank->valid = true; 3210 3211 break; 3212 } 3213 } 3214 } 3215 3216 grf_offs = ctrl->grf_mux_offset; 3217 pmu_offs = ctrl->pmu_mux_offset; 3218 drv_pmu_offs = ctrl->pmu_drv_offset; 3219 drv_grf_offs = ctrl->grf_drv_offset; 3220 bank = ctrl->pin_banks; 3221 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 3222 int bank_pins = 0; 3223 3224 raw_spin_lock_init(&bank->slock); 3225 bank->drvdata = d; 3226 bank->pin_base = ctrl->nr_pins; 3227 ctrl->nr_pins += bank->nr_pins; 3228 3229 /* calculate iomux and drv offsets */ 3230 for (j = 0; j < 4; j++) { 3231 struct rockchip_iomux *iom = &bank->iomux[j]; 3232 struct rockchip_drv *drv = &bank->drv[j]; 3233 int inc; 3234 3235 if (bank_pins >= bank->nr_pins) 3236 break; 3237 3238 /* preset iomux offset value, set new start value */ 3239 if (iom->offset >= 0) { 3240 if (iom->type & IOMUX_SOURCE_PMU) 3241 pmu_offs = iom->offset; 3242 else 3243 grf_offs = iom->offset; 3244 } else { /* set current iomux offset */ 3245 iom->offset = (iom->type & IOMUX_SOURCE_PMU) ? 3246 pmu_offs : grf_offs; 3247 } 3248 3249 /* preset drv offset value, set new start value */ 3250 if (drv->offset >= 0) { 3251 if (iom->type & IOMUX_SOURCE_PMU) 3252 drv_pmu_offs = drv->offset; 3253 else 3254 drv_grf_offs = drv->offset; 3255 } else { /* set current drv offset */ 3256 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ? 3257 drv_pmu_offs : drv_grf_offs; 3258 } 3259 3260 dev_dbg(d->dev, "bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n", 3261 i, j, iom->offset, drv->offset); 3262 3263 /* 3264 * Increase offset according to iomux width. 3265 * 4bit iomux'es are spread over two registers. 3266 */ 3267 inc = (iom->type & (IOMUX_WIDTH_4BIT | 3268 IOMUX_WIDTH_3BIT)) ? 8 : 4; 3269 if (iom->type & IOMUX_SOURCE_PMU) 3270 pmu_offs += inc; 3271 else 3272 grf_offs += inc; 3273 3274 /* 3275 * Increase offset according to drv width. 3276 * 3bit drive-strenth'es are spread over two registers. 3277 */ 3278 if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) || 3279 (drv->drv_type == DRV_TYPE_IO_3V3_ONLY)) 3280 inc = 8; 3281 else 3282 inc = 4; 3283 3284 if (iom->type & IOMUX_SOURCE_PMU) 3285 drv_pmu_offs += inc; 3286 else 3287 drv_grf_offs += inc; 3288 3289 bank_pins += 8; 3290 } 3291 3292 /* calculate the per-bank recalced_mask */ 3293 for (j = 0; j < ctrl->niomux_recalced; j++) { 3294 int pin = 0; 3295 3296 if (ctrl->iomux_recalced[j].num == bank->bank_num) { 3297 pin = ctrl->iomux_recalced[j].pin; 3298 bank->recalced_mask |= BIT(pin); 3299 } 3300 } 3301 3302 /* calculate the per-bank route_mask */ 3303 for (j = 0; j < ctrl->niomux_routes; j++) { 3304 int pin = 0; 3305 3306 if (ctrl->iomux_routes[j].bank_num == bank->bank_num) { 3307 pin = ctrl->iomux_routes[j].pin; 3308 bank->route_mask |= BIT(pin); 3309 } 3310 } 3311 } 3312 3313 return ctrl; 3314 } 3315 3316 #define RK3288_GRF_GPIO6C_IOMUX 0x64 3317 #define GPIO6C6_SEL_WRITE_ENABLE BIT(28) 3318 3319 static u32 rk3288_grf_gpio6c_iomux; 3320 3321 static int __maybe_unused rockchip_pinctrl_suspend(struct device *dev) 3322 { 3323 struct rockchip_pinctrl *info = dev_get_drvdata(dev); 3324 int ret = pinctrl_force_sleep(info->pctl_dev); 3325 3326 if (ret) 3327 return ret; 3328 3329 /* 3330 * RK3288 GPIO6_C6 mux would be modified by Maskrom when resume, so save 3331 * the setting here, and restore it at resume. 3332 */ 3333 if (info->ctrl->type == RK3288) { 3334 ret = regmap_read(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX, 3335 &rk3288_grf_gpio6c_iomux); 3336 if (ret) { 3337 pinctrl_force_default(info->pctl_dev); 3338 return ret; 3339 } 3340 } 3341 3342 return 0; 3343 } 3344 3345 static int __maybe_unused rockchip_pinctrl_resume(struct device *dev) 3346 { 3347 struct rockchip_pinctrl *info = dev_get_drvdata(dev); 3348 int ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX, 3349 rk3288_grf_gpio6c_iomux | 3350 GPIO6C6_SEL_WRITE_ENABLE); 3351 3352 if (ret) 3353 return ret; 3354 3355 return pinctrl_force_default(info->pctl_dev); 3356 } 3357 3358 static SIMPLE_DEV_PM_OPS(rockchip_pinctrl_dev_pm_ops, rockchip_pinctrl_suspend, 3359 rockchip_pinctrl_resume); 3360 3361 static int rockchip_pinctrl_probe(struct platform_device *pdev) 3362 { 3363 struct rockchip_pinctrl *info; 3364 struct device *dev = &pdev->dev; 3365 struct rockchip_pin_ctrl *ctrl; 3366 struct device_node *np = pdev->dev.of_node, *node; 3367 struct resource *res; 3368 void __iomem *base; 3369 int ret; 3370 3371 if (!dev->of_node) { 3372 dev_err(dev, "device tree node not found\n"); 3373 return -ENODEV; 3374 } 3375 3376 info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL); 3377 if (!info) 3378 return -ENOMEM; 3379 3380 info->dev = dev; 3381 3382 ctrl = rockchip_pinctrl_get_soc_data(info, pdev); 3383 if (!ctrl) { 3384 dev_err(dev, "driver data not available\n"); 3385 return -EINVAL; 3386 } 3387 info->ctrl = ctrl; 3388 3389 node = of_parse_phandle(np, "rockchip,grf", 0); 3390 if (node) { 3391 info->regmap_base = syscon_node_to_regmap(node); 3392 if (IS_ERR(info->regmap_base)) 3393 return PTR_ERR(info->regmap_base); 3394 } else { 3395 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 3396 base = devm_ioremap_resource(&pdev->dev, res); 3397 if (IS_ERR(base)) 3398 return PTR_ERR(base); 3399 3400 rockchip_regmap_config.max_register = resource_size(res) - 4; 3401 rockchip_regmap_config.name = "rockchip,pinctrl"; 3402 info->regmap_base = devm_regmap_init_mmio(&pdev->dev, base, 3403 &rockchip_regmap_config); 3404 3405 /* to check for the old dt-bindings */ 3406 info->reg_size = resource_size(res); 3407 3408 /* Honor the old binding, with pull registers as 2nd resource */ 3409 if (ctrl->type == RK3188 && info->reg_size < 0x200) { 3410 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 3411 base = devm_ioremap_resource(&pdev->dev, res); 3412 if (IS_ERR(base)) 3413 return PTR_ERR(base); 3414 3415 rockchip_regmap_config.max_register = 3416 resource_size(res) - 4; 3417 rockchip_regmap_config.name = "rockchip,pinctrl-pull"; 3418 info->regmap_pull = devm_regmap_init_mmio(&pdev->dev, 3419 base, 3420 &rockchip_regmap_config); 3421 } 3422 } 3423 3424 /* try to find the optional reference to the pmu syscon */ 3425 node = of_parse_phandle(np, "rockchip,pmu", 0); 3426 if (node) { 3427 info->regmap_pmu = syscon_node_to_regmap(node); 3428 if (IS_ERR(info->regmap_pmu)) 3429 return PTR_ERR(info->regmap_pmu); 3430 } 3431 3432 ret = rockchip_gpiolib_register(pdev, info); 3433 if (ret) 3434 return ret; 3435 3436 ret = rockchip_pinctrl_register(pdev, info); 3437 if (ret) { 3438 rockchip_gpiolib_unregister(pdev, info); 3439 return ret; 3440 } 3441 3442 platform_set_drvdata(pdev, info); 3443 3444 return 0; 3445 } 3446 3447 static struct rockchip_pin_bank px30_pin_banks[] = { 3448 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, 3449 IOMUX_SOURCE_PMU, 3450 IOMUX_SOURCE_PMU, 3451 IOMUX_SOURCE_PMU 3452 ), 3453 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT, 3454 IOMUX_WIDTH_4BIT, 3455 IOMUX_WIDTH_4BIT, 3456 IOMUX_WIDTH_4BIT 3457 ), 3458 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT, 3459 IOMUX_WIDTH_4BIT, 3460 IOMUX_WIDTH_4BIT, 3461 IOMUX_WIDTH_4BIT 3462 ), 3463 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT, 3464 IOMUX_WIDTH_4BIT, 3465 IOMUX_WIDTH_4BIT, 3466 IOMUX_WIDTH_4BIT 3467 ), 3468 }; 3469 3470 static struct rockchip_pin_ctrl px30_pin_ctrl = { 3471 .pin_banks = px30_pin_banks, 3472 .nr_banks = ARRAY_SIZE(px30_pin_banks), 3473 .label = "PX30-GPIO", 3474 .type = PX30, 3475 .grf_mux_offset = 0x0, 3476 .pmu_mux_offset = 0x0, 3477 .iomux_routes = px30_mux_route_data, 3478 .niomux_routes = ARRAY_SIZE(px30_mux_route_data), 3479 .pull_calc_reg = px30_calc_pull_reg_and_bit, 3480 .drv_calc_reg = px30_calc_drv_reg_and_bit, 3481 .schmitt_calc_reg = px30_calc_schmitt_reg_and_bit, 3482 }; 3483 3484 static struct rockchip_pin_bank rv1108_pin_banks[] = { 3485 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, 3486 IOMUX_SOURCE_PMU, 3487 IOMUX_SOURCE_PMU, 3488 IOMUX_SOURCE_PMU), 3489 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0), 3490 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0), 3491 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0), 3492 }; 3493 3494 static struct rockchip_pin_ctrl rv1108_pin_ctrl = { 3495 .pin_banks = rv1108_pin_banks, 3496 .nr_banks = ARRAY_SIZE(rv1108_pin_banks), 3497 .label = "RV1108-GPIO", 3498 .type = RV1108, 3499 .grf_mux_offset = 0x10, 3500 .pmu_mux_offset = 0x0, 3501 .iomux_recalced = rv1108_mux_recalced_data, 3502 .niomux_recalced = ARRAY_SIZE(rv1108_mux_recalced_data), 3503 .pull_calc_reg = rv1108_calc_pull_reg_and_bit, 3504 .drv_calc_reg = rv1108_calc_drv_reg_and_bit, 3505 .schmitt_calc_reg = rv1108_calc_schmitt_reg_and_bit, 3506 }; 3507 3508 static struct rockchip_pin_bank rk2928_pin_banks[] = { 3509 PIN_BANK(0, 32, "gpio0"), 3510 PIN_BANK(1, 32, "gpio1"), 3511 PIN_BANK(2, 32, "gpio2"), 3512 PIN_BANK(3, 32, "gpio3"), 3513 }; 3514 3515 static struct rockchip_pin_ctrl rk2928_pin_ctrl = { 3516 .pin_banks = rk2928_pin_banks, 3517 .nr_banks = ARRAY_SIZE(rk2928_pin_banks), 3518 .label = "RK2928-GPIO", 3519 .type = RK2928, 3520 .grf_mux_offset = 0xa8, 3521 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 3522 }; 3523 3524 static struct rockchip_pin_bank rk3036_pin_banks[] = { 3525 PIN_BANK(0, 32, "gpio0"), 3526 PIN_BANK(1, 32, "gpio1"), 3527 PIN_BANK(2, 32, "gpio2"), 3528 }; 3529 3530 static struct rockchip_pin_ctrl rk3036_pin_ctrl = { 3531 .pin_banks = rk3036_pin_banks, 3532 .nr_banks = ARRAY_SIZE(rk3036_pin_banks), 3533 .label = "RK3036-GPIO", 3534 .type = RK2928, 3535 .grf_mux_offset = 0xa8, 3536 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 3537 }; 3538 3539 static struct rockchip_pin_bank rk3066a_pin_banks[] = { 3540 PIN_BANK(0, 32, "gpio0"), 3541 PIN_BANK(1, 32, "gpio1"), 3542 PIN_BANK(2, 32, "gpio2"), 3543 PIN_BANK(3, 32, "gpio3"), 3544 PIN_BANK(4, 32, "gpio4"), 3545 PIN_BANK(6, 16, "gpio6"), 3546 }; 3547 3548 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = { 3549 .pin_banks = rk3066a_pin_banks, 3550 .nr_banks = ARRAY_SIZE(rk3066a_pin_banks), 3551 .label = "RK3066a-GPIO", 3552 .type = RK2928, 3553 .grf_mux_offset = 0xa8, 3554 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 3555 }; 3556 3557 static struct rockchip_pin_bank rk3066b_pin_banks[] = { 3558 PIN_BANK(0, 32, "gpio0"), 3559 PIN_BANK(1, 32, "gpio1"), 3560 PIN_BANK(2, 32, "gpio2"), 3561 PIN_BANK(3, 32, "gpio3"), 3562 }; 3563 3564 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = { 3565 .pin_banks = rk3066b_pin_banks, 3566 .nr_banks = ARRAY_SIZE(rk3066b_pin_banks), 3567 .label = "RK3066b-GPIO", 3568 .type = RK3066B, 3569 .grf_mux_offset = 0x60, 3570 }; 3571 3572 static struct rockchip_pin_bank rk3128_pin_banks[] = { 3573 PIN_BANK(0, 32, "gpio0"), 3574 PIN_BANK(1, 32, "gpio1"), 3575 PIN_BANK(2, 32, "gpio2"), 3576 PIN_BANK(3, 32, "gpio3"), 3577 }; 3578 3579 static struct rockchip_pin_ctrl rk3128_pin_ctrl = { 3580 .pin_banks = rk3128_pin_banks, 3581 .nr_banks = ARRAY_SIZE(rk3128_pin_banks), 3582 .label = "RK3128-GPIO", 3583 .type = RK3128, 3584 .grf_mux_offset = 0xa8, 3585 .iomux_recalced = rk3128_mux_recalced_data, 3586 .niomux_recalced = ARRAY_SIZE(rk3128_mux_recalced_data), 3587 .iomux_routes = rk3128_mux_route_data, 3588 .niomux_routes = ARRAY_SIZE(rk3128_mux_route_data), 3589 .pull_calc_reg = rk3128_calc_pull_reg_and_bit, 3590 }; 3591 3592 static struct rockchip_pin_bank rk3188_pin_banks[] = { 3593 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0), 3594 PIN_BANK(1, 32, "gpio1"), 3595 PIN_BANK(2, 32, "gpio2"), 3596 PIN_BANK(3, 32, "gpio3"), 3597 }; 3598 3599 static struct rockchip_pin_ctrl rk3188_pin_ctrl = { 3600 .pin_banks = rk3188_pin_banks, 3601 .nr_banks = ARRAY_SIZE(rk3188_pin_banks), 3602 .label = "RK3188-GPIO", 3603 .type = RK3188, 3604 .grf_mux_offset = 0x60, 3605 .pull_calc_reg = rk3188_calc_pull_reg_and_bit, 3606 }; 3607 3608 static struct rockchip_pin_bank rk3228_pin_banks[] = { 3609 PIN_BANK(0, 32, "gpio0"), 3610 PIN_BANK(1, 32, "gpio1"), 3611 PIN_BANK(2, 32, "gpio2"), 3612 PIN_BANK(3, 32, "gpio3"), 3613 }; 3614 3615 static struct rockchip_pin_ctrl rk3228_pin_ctrl = { 3616 .pin_banks = rk3228_pin_banks, 3617 .nr_banks = ARRAY_SIZE(rk3228_pin_banks), 3618 .label = "RK3228-GPIO", 3619 .type = RK3288, 3620 .grf_mux_offset = 0x0, 3621 .iomux_routes = rk3228_mux_route_data, 3622 .niomux_routes = ARRAY_SIZE(rk3228_mux_route_data), 3623 .pull_calc_reg = rk3228_calc_pull_reg_and_bit, 3624 .drv_calc_reg = rk3228_calc_drv_reg_and_bit, 3625 }; 3626 3627 static struct rockchip_pin_bank rk3288_pin_banks[] = { 3628 PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU, 3629 IOMUX_SOURCE_PMU, 3630 IOMUX_SOURCE_PMU, 3631 IOMUX_UNROUTED 3632 ), 3633 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED, 3634 IOMUX_UNROUTED, 3635 IOMUX_UNROUTED, 3636 0 3637 ), 3638 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED), 3639 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT), 3640 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT, 3641 IOMUX_WIDTH_4BIT, 3642 0, 3643 0 3644 ), 3645 PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED, 3646 0, 3647 0, 3648 IOMUX_UNROUTED 3649 ), 3650 PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED), 3651 PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0, 3652 0, 3653 IOMUX_WIDTH_4BIT, 3654 IOMUX_UNROUTED 3655 ), 3656 PIN_BANK(8, 16, "gpio8"), 3657 }; 3658 3659 static struct rockchip_pin_ctrl rk3288_pin_ctrl = { 3660 .pin_banks = rk3288_pin_banks, 3661 .nr_banks = ARRAY_SIZE(rk3288_pin_banks), 3662 .label = "RK3288-GPIO", 3663 .type = RK3288, 3664 .grf_mux_offset = 0x0, 3665 .pmu_mux_offset = 0x84, 3666 .iomux_routes = rk3288_mux_route_data, 3667 .niomux_routes = ARRAY_SIZE(rk3288_mux_route_data), 3668 .pull_calc_reg = rk3288_calc_pull_reg_and_bit, 3669 .drv_calc_reg = rk3288_calc_drv_reg_and_bit, 3670 }; 3671 3672 static struct rockchip_pin_bank rk3328_pin_banks[] = { 3673 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0), 3674 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0), 3675 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 3676 IOMUX_WIDTH_3BIT, 3677 IOMUX_WIDTH_3BIT, 3678 0), 3679 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 3680 IOMUX_WIDTH_3BIT, 3681 IOMUX_WIDTH_3BIT, 3682 0, 3683 0), 3684 }; 3685 3686 static struct rockchip_pin_ctrl rk3328_pin_ctrl = { 3687 .pin_banks = rk3328_pin_banks, 3688 .nr_banks = ARRAY_SIZE(rk3328_pin_banks), 3689 .label = "RK3328-GPIO", 3690 .type = RK3288, 3691 .grf_mux_offset = 0x0, 3692 .iomux_recalced = rk3328_mux_recalced_data, 3693 .niomux_recalced = ARRAY_SIZE(rk3328_mux_recalced_data), 3694 .iomux_routes = rk3328_mux_route_data, 3695 .niomux_routes = ARRAY_SIZE(rk3328_mux_route_data), 3696 .pull_calc_reg = rk3228_calc_pull_reg_and_bit, 3697 .drv_calc_reg = rk3228_calc_drv_reg_and_bit, 3698 .schmitt_calc_reg = rk3328_calc_schmitt_reg_and_bit, 3699 }; 3700 3701 static struct rockchip_pin_bank rk3368_pin_banks[] = { 3702 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, 3703 IOMUX_SOURCE_PMU, 3704 IOMUX_SOURCE_PMU, 3705 IOMUX_SOURCE_PMU 3706 ), 3707 PIN_BANK(1, 32, "gpio1"), 3708 PIN_BANK(2, 32, "gpio2"), 3709 PIN_BANK(3, 32, "gpio3"), 3710 }; 3711 3712 static struct rockchip_pin_ctrl rk3368_pin_ctrl = { 3713 .pin_banks = rk3368_pin_banks, 3714 .nr_banks = ARRAY_SIZE(rk3368_pin_banks), 3715 .label = "RK3368-GPIO", 3716 .type = RK3368, 3717 .grf_mux_offset = 0x0, 3718 .pmu_mux_offset = 0x0, 3719 .pull_calc_reg = rk3368_calc_pull_reg_and_bit, 3720 .drv_calc_reg = rk3368_calc_drv_reg_and_bit, 3721 }; 3722 3723 static struct rockchip_pin_bank rk3399_pin_banks[] = { 3724 PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0", 3725 IOMUX_SOURCE_PMU, 3726 IOMUX_SOURCE_PMU, 3727 IOMUX_SOURCE_PMU, 3728 IOMUX_SOURCE_PMU, 3729 DRV_TYPE_IO_1V8_ONLY, 3730 DRV_TYPE_IO_1V8_ONLY, 3731 DRV_TYPE_IO_DEFAULT, 3732 DRV_TYPE_IO_DEFAULT, 3733 0x80, 3734 0x88, 3735 -1, 3736 -1, 3737 PULL_TYPE_IO_1V8_ONLY, 3738 PULL_TYPE_IO_1V8_ONLY, 3739 PULL_TYPE_IO_DEFAULT, 3740 PULL_TYPE_IO_DEFAULT 3741 ), 3742 PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU, 3743 IOMUX_SOURCE_PMU, 3744 IOMUX_SOURCE_PMU, 3745 IOMUX_SOURCE_PMU, 3746 DRV_TYPE_IO_1V8_OR_3V0, 3747 DRV_TYPE_IO_1V8_OR_3V0, 3748 DRV_TYPE_IO_1V8_OR_3V0, 3749 DRV_TYPE_IO_1V8_OR_3V0, 3750 0xa0, 3751 0xa8, 3752 0xb0, 3753 0xb8 3754 ), 3755 PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0, 3756 DRV_TYPE_IO_1V8_OR_3V0, 3757 DRV_TYPE_IO_1V8_ONLY, 3758 DRV_TYPE_IO_1V8_ONLY, 3759 PULL_TYPE_IO_DEFAULT, 3760 PULL_TYPE_IO_DEFAULT, 3761 PULL_TYPE_IO_1V8_ONLY, 3762 PULL_TYPE_IO_1V8_ONLY 3763 ), 3764 PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY, 3765 DRV_TYPE_IO_3V3_ONLY, 3766 DRV_TYPE_IO_3V3_ONLY, 3767 DRV_TYPE_IO_1V8_OR_3V0 3768 ), 3769 PIN_BANK_DRV_FLAGS(4, 32, "gpio4", DRV_TYPE_IO_1V8_OR_3V0, 3770 DRV_TYPE_IO_1V8_3V0_AUTO, 3771 DRV_TYPE_IO_1V8_OR_3V0, 3772 DRV_TYPE_IO_1V8_OR_3V0 3773 ), 3774 }; 3775 3776 static struct rockchip_pin_ctrl rk3399_pin_ctrl = { 3777 .pin_banks = rk3399_pin_banks, 3778 .nr_banks = ARRAY_SIZE(rk3399_pin_banks), 3779 .label = "RK3399-GPIO", 3780 .type = RK3399, 3781 .grf_mux_offset = 0xe000, 3782 .pmu_mux_offset = 0x0, 3783 .grf_drv_offset = 0xe100, 3784 .pmu_drv_offset = 0x80, 3785 .iomux_routes = rk3399_mux_route_data, 3786 .niomux_routes = ARRAY_SIZE(rk3399_mux_route_data), 3787 .pull_calc_reg = rk3399_calc_pull_reg_and_bit, 3788 .drv_calc_reg = rk3399_calc_drv_reg_and_bit, 3789 }; 3790 3791 static const struct of_device_id rockchip_pinctrl_dt_match[] = { 3792 { .compatible = "rockchip,px30-pinctrl", 3793 .data = &px30_pin_ctrl }, 3794 { .compatible = "rockchip,rv1108-pinctrl", 3795 .data = &rv1108_pin_ctrl }, 3796 { .compatible = "rockchip,rk2928-pinctrl", 3797 .data = &rk2928_pin_ctrl }, 3798 { .compatible = "rockchip,rk3036-pinctrl", 3799 .data = &rk3036_pin_ctrl }, 3800 { .compatible = "rockchip,rk3066a-pinctrl", 3801 .data = &rk3066a_pin_ctrl }, 3802 { .compatible = "rockchip,rk3066b-pinctrl", 3803 .data = &rk3066b_pin_ctrl }, 3804 { .compatible = "rockchip,rk3128-pinctrl", 3805 .data = (void *)&rk3128_pin_ctrl }, 3806 { .compatible = "rockchip,rk3188-pinctrl", 3807 .data = &rk3188_pin_ctrl }, 3808 { .compatible = "rockchip,rk3228-pinctrl", 3809 .data = &rk3228_pin_ctrl }, 3810 { .compatible = "rockchip,rk3288-pinctrl", 3811 .data = &rk3288_pin_ctrl }, 3812 { .compatible = "rockchip,rk3328-pinctrl", 3813 .data = &rk3328_pin_ctrl }, 3814 { .compatible = "rockchip,rk3368-pinctrl", 3815 .data = &rk3368_pin_ctrl }, 3816 { .compatible = "rockchip,rk3399-pinctrl", 3817 .data = &rk3399_pin_ctrl }, 3818 {}, 3819 }; 3820 3821 static struct platform_driver rockchip_pinctrl_driver = { 3822 .probe = rockchip_pinctrl_probe, 3823 .driver = { 3824 .name = "rockchip-pinctrl", 3825 .pm = &rockchip_pinctrl_dev_pm_ops, 3826 .of_match_table = rockchip_pinctrl_dt_match, 3827 }, 3828 }; 3829 3830 static int __init rockchip_pinctrl_drv_register(void) 3831 { 3832 return platform_driver_register(&rockchip_pinctrl_driver); 3833 } 3834 postcore_initcall(rockchip_pinctrl_drv_register); 3835