1 /* 2 * Pinctrl driver for Rockchip SoCs 3 * 4 * Copyright (c) 2013 MundoReader S.L. 5 * Author: Heiko Stuebner <heiko@sntech.de> 6 * 7 * With some ideas taken from pinctrl-samsung: 8 * Copyright (c) 2012 Samsung Electronics Co., Ltd. 9 * http://www.samsung.com 10 * Copyright (c) 2012 Linaro Ltd 11 * http://www.linaro.org 12 * 13 * and pinctrl-at91: 14 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> 15 * 16 * This program is free software; you can redistribute it and/or modify 17 * it under the terms of the GNU General Public License version 2 as published 18 * by the Free Software Foundation. 19 * 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 */ 25 26 #include <linux/init.h> 27 #include <linux/platform_device.h> 28 #include <linux/io.h> 29 #include <linux/bitops.h> 30 #include <linux/gpio.h> 31 #include <linux/of_address.h> 32 #include <linux/of_irq.h> 33 #include <linux/pinctrl/machine.h> 34 #include <linux/pinctrl/pinconf.h> 35 #include <linux/pinctrl/pinctrl.h> 36 #include <linux/pinctrl/pinmux.h> 37 #include <linux/pinctrl/pinconf-generic.h> 38 #include <linux/irqchip/chained_irq.h> 39 #include <linux/clk.h> 40 #include <linux/regmap.h> 41 #include <linux/mfd/syscon.h> 42 #include <dt-bindings/pinctrl/rockchip.h> 43 44 #include "core.h" 45 #include "pinconf.h" 46 47 /* GPIO control registers */ 48 #define GPIO_SWPORT_DR 0x00 49 #define GPIO_SWPORT_DDR 0x04 50 #define GPIO_INTEN 0x30 51 #define GPIO_INTMASK 0x34 52 #define GPIO_INTTYPE_LEVEL 0x38 53 #define GPIO_INT_POLARITY 0x3c 54 #define GPIO_INT_STATUS 0x40 55 #define GPIO_INT_RAWSTATUS 0x44 56 #define GPIO_DEBOUNCE 0x48 57 #define GPIO_PORTS_EOI 0x4c 58 #define GPIO_EXT_PORT 0x50 59 #define GPIO_LS_SYNC 0x60 60 61 enum rockchip_pinctrl_type { 62 RV1108, 63 RK2928, 64 RK3066B, 65 RK3188, 66 RK3288, 67 RK3368, 68 RK3399, 69 }; 70 71 /** 72 * Encode variants of iomux registers into a type variable 73 */ 74 #define IOMUX_GPIO_ONLY BIT(0) 75 #define IOMUX_WIDTH_4BIT BIT(1) 76 #define IOMUX_SOURCE_PMU BIT(2) 77 #define IOMUX_UNROUTED BIT(3) 78 #define IOMUX_WIDTH_3BIT BIT(4) 79 #define IOMUX_RECALCED BIT(5) 80 81 /** 82 * @type: iomux variant using IOMUX_* constants 83 * @offset: if initialized to -1 it will be autocalculated, by specifying 84 * an initial offset value the relevant source offset can be reset 85 * to a new value for autocalculating the following iomux registers. 86 */ 87 struct rockchip_iomux { 88 int type; 89 int offset; 90 }; 91 92 /** 93 * enum type index corresponding to rockchip_perpin_drv_list arrays index. 94 */ 95 enum rockchip_pin_drv_type { 96 DRV_TYPE_IO_DEFAULT = 0, 97 DRV_TYPE_IO_1V8_OR_3V0, 98 DRV_TYPE_IO_1V8_ONLY, 99 DRV_TYPE_IO_1V8_3V0_AUTO, 100 DRV_TYPE_IO_3V3_ONLY, 101 DRV_TYPE_MAX 102 }; 103 104 /** 105 * enum type index corresponding to rockchip_pull_list arrays index. 106 */ 107 enum rockchip_pin_pull_type { 108 PULL_TYPE_IO_DEFAULT = 0, 109 PULL_TYPE_IO_1V8_ONLY, 110 PULL_TYPE_MAX 111 }; 112 113 /** 114 * @drv_type: drive strength variant using rockchip_perpin_drv_type 115 * @offset: if initialized to -1 it will be autocalculated, by specifying 116 * an initial offset value the relevant source offset can be reset 117 * to a new value for autocalculating the following drive strength 118 * registers. if used chips own cal_drv func instead to calculate 119 * registers offset, the variant could be ignored. 120 */ 121 struct rockchip_drv { 122 enum rockchip_pin_drv_type drv_type; 123 int offset; 124 }; 125 126 /** 127 * @reg_base: register base of the gpio bank 128 * @reg_pull: optional separate register for additional pull settings 129 * @clk: clock of the gpio bank 130 * @irq: interrupt of the gpio bank 131 * @saved_masks: Saved content of GPIO_INTEN at suspend time. 132 * @pin_base: first pin number 133 * @nr_pins: number of pins in this bank 134 * @name: name of the bank 135 * @bank_num: number of the bank, to account for holes 136 * @iomux: array describing the 4 iomux sources of the bank 137 * @drv: array describing the 4 drive strength sources of the bank 138 * @pull_type: array describing the 4 pull type sources of the bank 139 * @valid: are all necessary informations present 140 * @of_node: dt node of this bank 141 * @drvdata: common pinctrl basedata 142 * @domain: irqdomain of the gpio bank 143 * @gpio_chip: gpiolib chip 144 * @grange: gpio range 145 * @slock: spinlock for the gpio bank 146 * @route_mask: bits describing the routing pins of per bank 147 */ 148 struct rockchip_pin_bank { 149 void __iomem *reg_base; 150 struct regmap *regmap_pull; 151 struct clk *clk; 152 int irq; 153 u32 saved_masks; 154 u32 pin_base; 155 u8 nr_pins; 156 char *name; 157 u8 bank_num; 158 struct rockchip_iomux iomux[4]; 159 struct rockchip_drv drv[4]; 160 enum rockchip_pin_pull_type pull_type[4]; 161 bool valid; 162 struct device_node *of_node; 163 struct rockchip_pinctrl *drvdata; 164 struct irq_domain *domain; 165 struct gpio_chip gpio_chip; 166 struct pinctrl_gpio_range grange; 167 raw_spinlock_t slock; 168 u32 toggle_edge_mode; 169 u32 route_mask; 170 }; 171 172 #define PIN_BANK(id, pins, label) \ 173 { \ 174 .bank_num = id, \ 175 .nr_pins = pins, \ 176 .name = label, \ 177 .iomux = { \ 178 { .offset = -1 }, \ 179 { .offset = -1 }, \ 180 { .offset = -1 }, \ 181 { .offset = -1 }, \ 182 }, \ 183 } 184 185 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \ 186 { \ 187 .bank_num = id, \ 188 .nr_pins = pins, \ 189 .name = label, \ 190 .iomux = { \ 191 { .type = iom0, .offset = -1 }, \ 192 { .type = iom1, .offset = -1 }, \ 193 { .type = iom2, .offset = -1 }, \ 194 { .type = iom3, .offset = -1 }, \ 195 }, \ 196 } 197 198 #define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \ 199 { \ 200 .bank_num = id, \ 201 .nr_pins = pins, \ 202 .name = label, \ 203 .iomux = { \ 204 { .offset = -1 }, \ 205 { .offset = -1 }, \ 206 { .offset = -1 }, \ 207 { .offset = -1 }, \ 208 }, \ 209 .drv = { \ 210 { .drv_type = type0, .offset = -1 }, \ 211 { .drv_type = type1, .offset = -1 }, \ 212 { .drv_type = type2, .offset = -1 }, \ 213 { .drv_type = type3, .offset = -1 }, \ 214 }, \ 215 } 216 217 #define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1, \ 218 drv2, drv3, pull0, pull1, \ 219 pull2, pull3) \ 220 { \ 221 .bank_num = id, \ 222 .nr_pins = pins, \ 223 .name = label, \ 224 .iomux = { \ 225 { .offset = -1 }, \ 226 { .offset = -1 }, \ 227 { .offset = -1 }, \ 228 { .offset = -1 }, \ 229 }, \ 230 .drv = { \ 231 { .drv_type = drv0, .offset = -1 }, \ 232 { .drv_type = drv1, .offset = -1 }, \ 233 { .drv_type = drv2, .offset = -1 }, \ 234 { .drv_type = drv3, .offset = -1 }, \ 235 }, \ 236 .pull_type[0] = pull0, \ 237 .pull_type[1] = pull1, \ 238 .pull_type[2] = pull2, \ 239 .pull_type[3] = pull3, \ 240 } 241 242 #define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1, \ 243 iom2, iom3, drv0, drv1, drv2, \ 244 drv3, offset0, offset1, \ 245 offset2, offset3) \ 246 { \ 247 .bank_num = id, \ 248 .nr_pins = pins, \ 249 .name = label, \ 250 .iomux = { \ 251 { .type = iom0, .offset = -1 }, \ 252 { .type = iom1, .offset = -1 }, \ 253 { .type = iom2, .offset = -1 }, \ 254 { .type = iom3, .offset = -1 }, \ 255 }, \ 256 .drv = { \ 257 { .drv_type = drv0, .offset = offset0 }, \ 258 { .drv_type = drv1, .offset = offset1 }, \ 259 { .drv_type = drv2, .offset = offset2 }, \ 260 { .drv_type = drv3, .offset = offset3 }, \ 261 }, \ 262 } 263 264 #define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins, \ 265 label, iom0, iom1, iom2, \ 266 iom3, drv0, drv1, drv2, \ 267 drv3, offset0, offset1, \ 268 offset2, offset3, pull0, \ 269 pull1, pull2, pull3) \ 270 { \ 271 .bank_num = id, \ 272 .nr_pins = pins, \ 273 .name = label, \ 274 .iomux = { \ 275 { .type = iom0, .offset = -1 }, \ 276 { .type = iom1, .offset = -1 }, \ 277 { .type = iom2, .offset = -1 }, \ 278 { .type = iom3, .offset = -1 }, \ 279 }, \ 280 .drv = { \ 281 { .drv_type = drv0, .offset = offset0 }, \ 282 { .drv_type = drv1, .offset = offset1 }, \ 283 { .drv_type = drv2, .offset = offset2 }, \ 284 { .drv_type = drv3, .offset = offset3 }, \ 285 }, \ 286 .pull_type[0] = pull0, \ 287 .pull_type[1] = pull1, \ 288 .pull_type[2] = pull2, \ 289 .pull_type[3] = pull3, \ 290 } 291 292 /** 293 * struct rockchip_mux_recalced_data: represent a pin iomux data. 294 * @bank_num: bank number. 295 * @pin: index at register or used to calc index. 296 * @func: the min pin. 297 * @route_offset: the max pin. 298 * @route_val: the register offset. 299 */ 300 struct rockchip_mux_route_data { 301 u8 bank_num; 302 u8 pin; 303 u8 func; 304 u32 route_offset; 305 u32 route_val; 306 }; 307 308 /** 309 */ 310 struct rockchip_pin_ctrl { 311 struct rockchip_pin_bank *pin_banks; 312 u32 nr_banks; 313 u32 nr_pins; 314 char *label; 315 enum rockchip_pinctrl_type type; 316 int grf_mux_offset; 317 int pmu_mux_offset; 318 int grf_drv_offset; 319 int pmu_drv_offset; 320 struct rockchip_mux_route_data *iomux_routes; 321 u32 niomux_routes; 322 323 void (*pull_calc_reg)(struct rockchip_pin_bank *bank, 324 int pin_num, struct regmap **regmap, 325 int *reg, u8 *bit); 326 void (*drv_calc_reg)(struct rockchip_pin_bank *bank, 327 int pin_num, struct regmap **regmap, 328 int *reg, u8 *bit); 329 void (*iomux_recalc)(u8 bank_num, int pin, int *reg, 330 u8 *bit, int *mask); 331 int (*schmitt_calc_reg)(struct rockchip_pin_bank *bank, 332 int pin_num, struct regmap **regmap, 333 int *reg, u8 *bit); 334 }; 335 336 struct rockchip_pin_config { 337 unsigned int func; 338 unsigned long *configs; 339 unsigned int nconfigs; 340 }; 341 342 /** 343 * struct rockchip_pin_group: represent group of pins of a pinmux function. 344 * @name: name of the pin group, used to lookup the group. 345 * @pins: the pins included in this group. 346 * @npins: number of pins included in this group. 347 * @func: the mux function number to be programmed when selected. 348 * @configs: the config values to be set for each pin 349 * @nconfigs: number of configs for each pin 350 */ 351 struct rockchip_pin_group { 352 const char *name; 353 unsigned int npins; 354 unsigned int *pins; 355 struct rockchip_pin_config *data; 356 }; 357 358 /** 359 * struct rockchip_pmx_func: represent a pin function. 360 * @name: name of the pin function, used to lookup the function. 361 * @groups: one or more names of pin groups that provide this function. 362 * @num_groups: number of groups included in @groups. 363 */ 364 struct rockchip_pmx_func { 365 const char *name; 366 const char **groups; 367 u8 ngroups; 368 }; 369 370 struct rockchip_pinctrl { 371 struct regmap *regmap_base; 372 int reg_size; 373 struct regmap *regmap_pull; 374 struct regmap *regmap_pmu; 375 struct device *dev; 376 struct rockchip_pin_ctrl *ctrl; 377 struct pinctrl_desc pctl; 378 struct pinctrl_dev *pctl_dev; 379 struct rockchip_pin_group *groups; 380 unsigned int ngroups; 381 struct rockchip_pmx_func *functions; 382 unsigned int nfunctions; 383 }; 384 385 /** 386 * struct rockchip_mux_recalced_data: represent a pin iomux data. 387 * @num: bank number. 388 * @pin: pin number. 389 * @bit: index at register. 390 * @reg: register offset. 391 * @mask: mask bit 392 */ 393 struct rockchip_mux_recalced_data { 394 u8 num; 395 u8 pin; 396 u8 reg; 397 u8 bit; 398 u8 mask; 399 }; 400 401 static struct regmap_config rockchip_regmap_config = { 402 .reg_bits = 32, 403 .val_bits = 32, 404 .reg_stride = 4, 405 }; 406 407 static inline const struct rockchip_pin_group *pinctrl_name_to_group( 408 const struct rockchip_pinctrl *info, 409 const char *name) 410 { 411 int i; 412 413 for (i = 0; i < info->ngroups; i++) { 414 if (!strcmp(info->groups[i].name, name)) 415 return &info->groups[i]; 416 } 417 418 return NULL; 419 } 420 421 /* 422 * given a pin number that is local to a pin controller, find out the pin bank 423 * and the register base of the pin bank. 424 */ 425 static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info, 426 unsigned pin) 427 { 428 struct rockchip_pin_bank *b = info->ctrl->pin_banks; 429 430 while (pin >= (b->pin_base + b->nr_pins)) 431 b++; 432 433 return b; 434 } 435 436 static struct rockchip_pin_bank *bank_num_to_bank( 437 struct rockchip_pinctrl *info, 438 unsigned num) 439 { 440 struct rockchip_pin_bank *b = info->ctrl->pin_banks; 441 int i; 442 443 for (i = 0; i < info->ctrl->nr_banks; i++, b++) { 444 if (b->bank_num == num) 445 return b; 446 } 447 448 return ERR_PTR(-EINVAL); 449 } 450 451 /* 452 * Pinctrl_ops handling 453 */ 454 455 static int rockchip_get_groups_count(struct pinctrl_dev *pctldev) 456 { 457 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 458 459 return info->ngroups; 460 } 461 462 static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev, 463 unsigned selector) 464 { 465 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 466 467 return info->groups[selector].name; 468 } 469 470 static int rockchip_get_group_pins(struct pinctrl_dev *pctldev, 471 unsigned selector, const unsigned **pins, 472 unsigned *npins) 473 { 474 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 475 476 if (selector >= info->ngroups) 477 return -EINVAL; 478 479 *pins = info->groups[selector].pins; 480 *npins = info->groups[selector].npins; 481 482 return 0; 483 } 484 485 static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev, 486 struct device_node *np, 487 struct pinctrl_map **map, unsigned *num_maps) 488 { 489 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 490 const struct rockchip_pin_group *grp; 491 struct pinctrl_map *new_map; 492 struct device_node *parent; 493 int map_num = 1; 494 int i; 495 496 /* 497 * first find the group of this node and check if we need to create 498 * config maps for pins 499 */ 500 grp = pinctrl_name_to_group(info, np->name); 501 if (!grp) { 502 dev_err(info->dev, "unable to find group for node %s\n", 503 np->name); 504 return -EINVAL; 505 } 506 507 map_num += grp->npins; 508 new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num, 509 GFP_KERNEL); 510 if (!new_map) 511 return -ENOMEM; 512 513 *map = new_map; 514 *num_maps = map_num; 515 516 /* create mux map */ 517 parent = of_get_parent(np); 518 if (!parent) { 519 devm_kfree(pctldev->dev, new_map); 520 return -EINVAL; 521 } 522 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP; 523 new_map[0].data.mux.function = parent->name; 524 new_map[0].data.mux.group = np->name; 525 of_node_put(parent); 526 527 /* create config map */ 528 new_map++; 529 for (i = 0; i < grp->npins; i++) { 530 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN; 531 new_map[i].data.configs.group_or_pin = 532 pin_get_name(pctldev, grp->pins[i]); 533 new_map[i].data.configs.configs = grp->data[i].configs; 534 new_map[i].data.configs.num_configs = grp->data[i].nconfigs; 535 } 536 537 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n", 538 (*map)->data.mux.function, (*map)->data.mux.group, map_num); 539 540 return 0; 541 } 542 543 static void rockchip_dt_free_map(struct pinctrl_dev *pctldev, 544 struct pinctrl_map *map, unsigned num_maps) 545 { 546 } 547 548 static const struct pinctrl_ops rockchip_pctrl_ops = { 549 .get_groups_count = rockchip_get_groups_count, 550 .get_group_name = rockchip_get_group_name, 551 .get_group_pins = rockchip_get_group_pins, 552 .dt_node_to_map = rockchip_dt_node_to_map, 553 .dt_free_map = rockchip_dt_free_map, 554 }; 555 556 /* 557 * Hardware access 558 */ 559 560 static const struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = { 561 { 562 .num = 2, 563 .pin = 12, 564 .reg = 0x24, 565 .bit = 8, 566 .mask = 0x3 567 }, { 568 .num = 2, 569 .pin = 15, 570 .reg = 0x28, 571 .bit = 0, 572 .mask = 0x7 573 }, { 574 .num = 2, 575 .pin = 23, 576 .reg = 0x30, 577 .bit = 14, 578 .mask = 0x3 579 }, 580 }; 581 582 static void rk3328_recalc_mux(u8 bank_num, int pin, int *reg, 583 u8 *bit, int *mask) 584 { 585 const struct rockchip_mux_recalced_data *data = NULL; 586 int i; 587 588 for (i = 0; i < ARRAY_SIZE(rk3328_mux_recalced_data); i++) 589 if (rk3328_mux_recalced_data[i].num == bank_num && 590 rk3328_mux_recalced_data[i].pin == pin) { 591 data = &rk3328_mux_recalced_data[i]; 592 break; 593 } 594 595 if (!data) 596 return; 597 598 *reg = data->reg; 599 *mask = data->mask; 600 *bit = data->bit; 601 } 602 603 static struct rockchip_mux_route_data rk3228_mux_route_data[] = { 604 { 605 /* pwm0-0 */ 606 .bank_num = 0, 607 .pin = 26, 608 .func = 1, 609 .route_offset = 0x50, 610 .route_val = BIT(16), 611 }, { 612 /* pwm0-1 */ 613 .bank_num = 3, 614 .pin = 21, 615 .func = 1, 616 .route_offset = 0x50, 617 .route_val = BIT(16) | BIT(0), 618 }, { 619 /* pwm1-0 */ 620 .bank_num = 0, 621 .pin = 27, 622 .func = 1, 623 .route_offset = 0x50, 624 .route_val = BIT(16 + 1), 625 }, { 626 /* pwm1-1 */ 627 .bank_num = 0, 628 .pin = 30, 629 .func = 2, 630 .route_offset = 0x50, 631 .route_val = BIT(16 + 1) | BIT(1), 632 }, { 633 /* pwm2-0 */ 634 .bank_num = 0, 635 .pin = 28, 636 .func = 1, 637 .route_offset = 0x50, 638 .route_val = BIT(16 + 2), 639 }, { 640 /* pwm2-1 */ 641 .bank_num = 1, 642 .pin = 12, 643 .func = 2, 644 .route_offset = 0x50, 645 .route_val = BIT(16 + 2) | BIT(2), 646 }, { 647 /* pwm3-0 */ 648 .bank_num = 3, 649 .pin = 26, 650 .func = 1, 651 .route_offset = 0x50, 652 .route_val = BIT(16 + 3), 653 }, { 654 /* pwm3-1 */ 655 .bank_num = 1, 656 .pin = 11, 657 .func = 2, 658 .route_offset = 0x50, 659 .route_val = BIT(16 + 3) | BIT(3), 660 }, { 661 /* sdio-0_d0 */ 662 .bank_num = 1, 663 .pin = 1, 664 .func = 1, 665 .route_offset = 0x50, 666 .route_val = BIT(16 + 4), 667 }, { 668 /* sdio-1_d0 */ 669 .bank_num = 3, 670 .pin = 2, 671 .func = 1, 672 .route_offset = 0x50, 673 .route_val = BIT(16 + 4) | BIT(4), 674 }, { 675 /* spi-0_rx */ 676 .bank_num = 0, 677 .pin = 13, 678 .func = 2, 679 .route_offset = 0x50, 680 .route_val = BIT(16 + 5), 681 }, { 682 /* spi-1_rx */ 683 .bank_num = 2, 684 .pin = 0, 685 .func = 2, 686 .route_offset = 0x50, 687 .route_val = BIT(16 + 5) | BIT(5), 688 }, { 689 /* emmc-0_cmd */ 690 .bank_num = 1, 691 .pin = 22, 692 .func = 2, 693 .route_offset = 0x50, 694 .route_val = BIT(16 + 7), 695 }, { 696 /* emmc-1_cmd */ 697 .bank_num = 2, 698 .pin = 4, 699 .func = 2, 700 .route_offset = 0x50, 701 .route_val = BIT(16 + 7) | BIT(7), 702 }, { 703 /* uart2-0_rx */ 704 .bank_num = 1, 705 .pin = 19, 706 .func = 2, 707 .route_offset = 0x50, 708 .route_val = BIT(16 + 8), 709 }, { 710 /* uart2-1_rx */ 711 .bank_num = 1, 712 .pin = 10, 713 .func = 2, 714 .route_offset = 0x50, 715 .route_val = BIT(16 + 8) | BIT(8), 716 }, { 717 /* uart1-0_rx */ 718 .bank_num = 1, 719 .pin = 10, 720 .func = 1, 721 .route_offset = 0x50, 722 .route_val = BIT(16 + 11), 723 }, { 724 /* uart1-1_rx */ 725 .bank_num = 3, 726 .pin = 13, 727 .func = 1, 728 .route_offset = 0x50, 729 .route_val = BIT(16 + 11) | BIT(11), 730 }, 731 }; 732 733 static struct rockchip_mux_route_data rk3328_mux_route_data[] = { 734 { 735 /* uart2dbg_rxm0 */ 736 .bank_num = 1, 737 .pin = 1, 738 .func = 2, 739 .route_offset = 0x50, 740 .route_val = BIT(16) | BIT(16 + 1), 741 }, { 742 /* uart2dbg_rxm1 */ 743 .bank_num = 2, 744 .pin = 1, 745 .func = 1, 746 .route_offset = 0x50, 747 .route_val = BIT(16) | BIT(16 + 1) | BIT(0), 748 }, { 749 /* gmac-m1-optimized_rxd0 */ 750 .bank_num = 1, 751 .pin = 11, 752 .func = 2, 753 .route_offset = 0x50, 754 .route_val = BIT(16 + 2) | BIT(16 + 10) | BIT(2) | BIT(10), 755 }, { 756 /* pdm_sdi0m0 */ 757 .bank_num = 2, 758 .pin = 19, 759 .func = 2, 760 .route_offset = 0x50, 761 .route_val = BIT(16 + 3), 762 }, { 763 /* pdm_sdi0m1 */ 764 .bank_num = 1, 765 .pin = 23, 766 .func = 3, 767 .route_offset = 0x50, 768 .route_val = BIT(16 + 3) | BIT(3), 769 }, { 770 /* spi_rxdm2 */ 771 .bank_num = 3, 772 .pin = 2, 773 .func = 4, 774 .route_offset = 0x50, 775 .route_val = BIT(16 + 4) | BIT(16 + 5) | BIT(5), 776 }, { 777 /* i2s2_sdim0 */ 778 .bank_num = 1, 779 .pin = 24, 780 .func = 1, 781 .route_offset = 0x50, 782 .route_val = BIT(16 + 6), 783 }, { 784 /* i2s2_sdim1 */ 785 .bank_num = 3, 786 .pin = 2, 787 .func = 6, 788 .route_offset = 0x50, 789 .route_val = BIT(16 + 6) | BIT(6), 790 }, { 791 /* card_iom1 */ 792 .bank_num = 2, 793 .pin = 22, 794 .func = 3, 795 .route_offset = 0x50, 796 .route_val = BIT(16 + 7) | BIT(7), 797 }, { 798 /* tsp_d5m1 */ 799 .bank_num = 2, 800 .pin = 16, 801 .func = 3, 802 .route_offset = 0x50, 803 .route_val = BIT(16 + 8) | BIT(8), 804 }, { 805 /* cif_data5m1 */ 806 .bank_num = 2, 807 .pin = 16, 808 .func = 4, 809 .route_offset = 0x50, 810 .route_val = BIT(16 + 9) | BIT(9), 811 }, 812 }; 813 814 static struct rockchip_mux_route_data rk3399_mux_route_data[] = { 815 { 816 /* uart2dbga_rx */ 817 .bank_num = 4, 818 .pin = 8, 819 .func = 2, 820 .route_offset = 0xe21c, 821 .route_val = BIT(16 + 10) | BIT(16 + 11), 822 }, { 823 /* uart2dbgb_rx */ 824 .bank_num = 4, 825 .pin = 16, 826 .func = 2, 827 .route_offset = 0xe21c, 828 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10), 829 }, { 830 /* uart2dbgc_rx */ 831 .bank_num = 4, 832 .pin = 19, 833 .func = 1, 834 .route_offset = 0xe21c, 835 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11), 836 }, { 837 /* pcie_clkreqn */ 838 .bank_num = 2, 839 .pin = 26, 840 .func = 2, 841 .route_offset = 0xe21c, 842 .route_val = BIT(16 + 14), 843 }, { 844 /* pcie_clkreqnb */ 845 .bank_num = 4, 846 .pin = 24, 847 .func = 1, 848 .route_offset = 0xe21c, 849 .route_val = BIT(16 + 14) | BIT(14), 850 }, 851 }; 852 853 static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin, 854 int mux, u32 *reg, u32 *value) 855 { 856 struct rockchip_pinctrl *info = bank->drvdata; 857 struct rockchip_pin_ctrl *ctrl = info->ctrl; 858 struct rockchip_mux_route_data *data; 859 int i; 860 861 for (i = 0; i < ctrl->niomux_routes; i++) { 862 data = &ctrl->iomux_routes[i]; 863 if ((data->bank_num == bank->bank_num) && 864 (data->pin == pin) && (data->func == mux)) 865 break; 866 } 867 868 if (i >= ctrl->niomux_routes) 869 return false; 870 871 *reg = data->route_offset; 872 *value = data->route_val; 873 874 return true; 875 } 876 877 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) 878 { 879 struct rockchip_pinctrl *info = bank->drvdata; 880 struct rockchip_pin_ctrl *ctrl = info->ctrl; 881 int iomux_num = (pin / 8); 882 struct regmap *regmap; 883 unsigned int val; 884 int reg, ret, mask, mux_type; 885 u8 bit; 886 887 if (iomux_num > 3) 888 return -EINVAL; 889 890 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { 891 dev_err(info->dev, "pin %d is unrouted\n", pin); 892 return -EINVAL; 893 } 894 895 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) 896 return RK_FUNC_GPIO; 897 898 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) 899 ? info->regmap_pmu : info->regmap_base; 900 901 /* get basic quadrupel of mux registers and the correct reg inside */ 902 mux_type = bank->iomux[iomux_num].type; 903 reg = bank->iomux[iomux_num].offset; 904 if (mux_type & IOMUX_WIDTH_4BIT) { 905 if ((pin % 8) >= 4) 906 reg += 0x4; 907 bit = (pin % 4) * 4; 908 mask = 0xf; 909 } else if (mux_type & IOMUX_WIDTH_3BIT) { 910 if ((pin % 8) >= 5) 911 reg += 0x4; 912 bit = (pin % 8 % 5) * 3; 913 mask = 0x7; 914 } else { 915 bit = (pin % 8) * 2; 916 mask = 0x3; 917 } 918 919 if (ctrl->iomux_recalc && (mux_type & IOMUX_RECALCED)) 920 ctrl->iomux_recalc(bank->bank_num, pin, ®, &bit, &mask); 921 922 ret = regmap_read(regmap, reg, &val); 923 if (ret) 924 return ret; 925 926 return ((val >> bit) & mask); 927 } 928 929 static int rockchip_verify_mux(struct rockchip_pin_bank *bank, 930 int pin, int mux) 931 { 932 struct rockchip_pinctrl *info = bank->drvdata; 933 int iomux_num = (pin / 8); 934 935 if (iomux_num > 3) 936 return -EINVAL; 937 938 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { 939 dev_err(info->dev, "pin %d is unrouted\n", pin); 940 return -EINVAL; 941 } 942 943 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) { 944 if (mux != RK_FUNC_GPIO) { 945 dev_err(info->dev, 946 "pin %d only supports a gpio mux\n", pin); 947 return -ENOTSUPP; 948 } 949 } 950 951 return 0; 952 } 953 954 /* 955 * Set a new mux function for a pin. 956 * 957 * The register is divided into the upper and lower 16 bit. When changing 958 * a value, the previous register value is not read and changed. Instead 959 * it seems the changed bits are marked in the upper 16 bit, while the 960 * changed value gets set in the same offset in the lower 16 bit. 961 * All pin settings seem to be 2 bit wide in both the upper and lower 962 * parts. 963 * @bank: pin bank to change 964 * @pin: pin to change 965 * @mux: new mux function to set 966 */ 967 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) 968 { 969 struct rockchip_pinctrl *info = bank->drvdata; 970 struct rockchip_pin_ctrl *ctrl = info->ctrl; 971 int iomux_num = (pin / 8); 972 struct regmap *regmap; 973 int reg, ret, mask, mux_type; 974 u8 bit; 975 u32 data, rmask, route_reg, route_val; 976 977 ret = rockchip_verify_mux(bank, pin, mux); 978 if (ret < 0) 979 return ret; 980 981 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) 982 return 0; 983 984 dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n", 985 bank->bank_num, pin, mux); 986 987 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) 988 ? info->regmap_pmu : info->regmap_base; 989 990 /* get basic quadrupel of mux registers and the correct reg inside */ 991 mux_type = bank->iomux[iomux_num].type; 992 reg = bank->iomux[iomux_num].offset; 993 if (mux_type & IOMUX_WIDTH_4BIT) { 994 if ((pin % 8) >= 4) 995 reg += 0x4; 996 bit = (pin % 4) * 4; 997 mask = 0xf; 998 } else if (mux_type & IOMUX_WIDTH_3BIT) { 999 if ((pin % 8) >= 5) 1000 reg += 0x4; 1001 bit = (pin % 8 % 5) * 3; 1002 mask = 0x7; 1003 } else { 1004 bit = (pin % 8) * 2; 1005 mask = 0x3; 1006 } 1007 1008 if (ctrl->iomux_recalc && (mux_type & IOMUX_RECALCED)) 1009 ctrl->iomux_recalc(bank->bank_num, pin, ®, &bit, &mask); 1010 1011 if (bank->route_mask & BIT(pin)) { 1012 if (rockchip_get_mux_route(bank, pin, mux, &route_reg, 1013 &route_val)) { 1014 ret = regmap_write(regmap, route_reg, route_val); 1015 if (ret) 1016 return ret; 1017 } 1018 } 1019 1020 data = (mask << (bit + 16)); 1021 rmask = data | (data >> 16); 1022 data |= (mux & mask) << bit; 1023 ret = regmap_update_bits(regmap, reg, rmask, data); 1024 1025 return ret; 1026 } 1027 1028 #define RV1108_PULL_PMU_OFFSET 0x10 1029 #define RV1108_PULL_OFFSET 0x110 1030 #define RV1108_PULL_PINS_PER_REG 8 1031 #define RV1108_PULL_BITS_PER_PIN 2 1032 #define RV1108_PULL_BANK_STRIDE 16 1033 1034 static void rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1035 int pin_num, struct regmap **regmap, 1036 int *reg, u8 *bit) 1037 { 1038 struct rockchip_pinctrl *info = bank->drvdata; 1039 1040 /* The first 24 pins of the first bank are located in PMU */ 1041 if (bank->bank_num == 0) { 1042 *regmap = info->regmap_pmu; 1043 *reg = RV1108_PULL_PMU_OFFSET; 1044 } else { 1045 *reg = RV1108_PULL_OFFSET; 1046 *regmap = info->regmap_base; 1047 /* correct the offset, as we're starting with the 2nd bank */ 1048 *reg -= 0x10; 1049 *reg += bank->bank_num * RV1108_PULL_BANK_STRIDE; 1050 } 1051 1052 *reg += ((pin_num / RV1108_PULL_PINS_PER_REG) * 4); 1053 *bit = (pin_num % RV1108_PULL_PINS_PER_REG); 1054 *bit *= RV1108_PULL_BITS_PER_PIN; 1055 } 1056 1057 #define RV1108_DRV_PMU_OFFSET 0x20 1058 #define RV1108_DRV_GRF_OFFSET 0x210 1059 #define RV1108_DRV_BITS_PER_PIN 2 1060 #define RV1108_DRV_PINS_PER_REG 8 1061 #define RV1108_DRV_BANK_STRIDE 16 1062 1063 static void rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1064 int pin_num, struct regmap **regmap, 1065 int *reg, u8 *bit) 1066 { 1067 struct rockchip_pinctrl *info = bank->drvdata; 1068 1069 /* The first 24 pins of the first bank are located in PMU */ 1070 if (bank->bank_num == 0) { 1071 *regmap = info->regmap_pmu; 1072 *reg = RV1108_DRV_PMU_OFFSET; 1073 } else { 1074 *regmap = info->regmap_base; 1075 *reg = RV1108_DRV_GRF_OFFSET; 1076 1077 /* correct the offset, as we're starting with the 2nd bank */ 1078 *reg -= 0x10; 1079 *reg += bank->bank_num * RV1108_DRV_BANK_STRIDE; 1080 } 1081 1082 *reg += ((pin_num / RV1108_DRV_PINS_PER_REG) * 4); 1083 *bit = pin_num % RV1108_DRV_PINS_PER_REG; 1084 *bit *= RV1108_DRV_BITS_PER_PIN; 1085 } 1086 1087 #define RK2928_PULL_OFFSET 0x118 1088 #define RK2928_PULL_PINS_PER_REG 16 1089 #define RK2928_PULL_BANK_STRIDE 8 1090 1091 static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1092 int pin_num, struct regmap **regmap, 1093 int *reg, u8 *bit) 1094 { 1095 struct rockchip_pinctrl *info = bank->drvdata; 1096 1097 *regmap = info->regmap_base; 1098 *reg = RK2928_PULL_OFFSET; 1099 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; 1100 *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4; 1101 1102 *bit = pin_num % RK2928_PULL_PINS_PER_REG; 1103 }; 1104 1105 #define RK3188_PULL_OFFSET 0x164 1106 #define RK3188_PULL_BITS_PER_PIN 2 1107 #define RK3188_PULL_PINS_PER_REG 8 1108 #define RK3188_PULL_BANK_STRIDE 16 1109 #define RK3188_PULL_PMU_OFFSET 0x64 1110 1111 static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1112 int pin_num, struct regmap **regmap, 1113 int *reg, u8 *bit) 1114 { 1115 struct rockchip_pinctrl *info = bank->drvdata; 1116 1117 /* The first 12 pins of the first bank are located elsewhere */ 1118 if (bank->bank_num == 0 && pin_num < 12) { 1119 *regmap = info->regmap_pmu ? info->regmap_pmu 1120 : bank->regmap_pull; 1121 *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0; 1122 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1123 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 1124 *bit *= RK3188_PULL_BITS_PER_PIN; 1125 } else { 1126 *regmap = info->regmap_pull ? info->regmap_pull 1127 : info->regmap_base; 1128 *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET; 1129 1130 /* correct the offset, as it is the 2nd pull register */ 1131 *reg -= 4; 1132 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1133 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1134 1135 /* 1136 * The bits in these registers have an inverse ordering 1137 * with the lowest pin being in bits 15:14 and the highest 1138 * pin in bits 1:0 1139 */ 1140 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG); 1141 *bit *= RK3188_PULL_BITS_PER_PIN; 1142 } 1143 } 1144 1145 #define RK3288_PULL_OFFSET 0x140 1146 static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1147 int pin_num, struct regmap **regmap, 1148 int *reg, u8 *bit) 1149 { 1150 struct rockchip_pinctrl *info = bank->drvdata; 1151 1152 /* The first 24 pins of the first bank are located in PMU */ 1153 if (bank->bank_num == 0) { 1154 *regmap = info->regmap_pmu; 1155 *reg = RK3188_PULL_PMU_OFFSET; 1156 1157 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1158 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 1159 *bit *= RK3188_PULL_BITS_PER_PIN; 1160 } else { 1161 *regmap = info->regmap_base; 1162 *reg = RK3288_PULL_OFFSET; 1163 1164 /* correct the offset, as we're starting with the 2nd bank */ 1165 *reg -= 0x10; 1166 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1167 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1168 1169 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1170 *bit *= RK3188_PULL_BITS_PER_PIN; 1171 } 1172 } 1173 1174 #define RK3288_DRV_PMU_OFFSET 0x70 1175 #define RK3288_DRV_GRF_OFFSET 0x1c0 1176 #define RK3288_DRV_BITS_PER_PIN 2 1177 #define RK3288_DRV_PINS_PER_REG 8 1178 #define RK3288_DRV_BANK_STRIDE 16 1179 1180 static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1181 int pin_num, struct regmap **regmap, 1182 int *reg, u8 *bit) 1183 { 1184 struct rockchip_pinctrl *info = bank->drvdata; 1185 1186 /* The first 24 pins of the first bank are located in PMU */ 1187 if (bank->bank_num == 0) { 1188 *regmap = info->regmap_pmu; 1189 *reg = RK3288_DRV_PMU_OFFSET; 1190 1191 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1192 *bit = pin_num % RK3288_DRV_PINS_PER_REG; 1193 *bit *= RK3288_DRV_BITS_PER_PIN; 1194 } else { 1195 *regmap = info->regmap_base; 1196 *reg = RK3288_DRV_GRF_OFFSET; 1197 1198 /* correct the offset, as we're starting with the 2nd bank */ 1199 *reg -= 0x10; 1200 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 1201 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1202 1203 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 1204 *bit *= RK3288_DRV_BITS_PER_PIN; 1205 } 1206 } 1207 1208 #define RK3228_PULL_OFFSET 0x100 1209 1210 static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1211 int pin_num, struct regmap **regmap, 1212 int *reg, u8 *bit) 1213 { 1214 struct rockchip_pinctrl *info = bank->drvdata; 1215 1216 *regmap = info->regmap_base; 1217 *reg = RK3228_PULL_OFFSET; 1218 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1219 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1220 1221 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1222 *bit *= RK3188_PULL_BITS_PER_PIN; 1223 } 1224 1225 #define RK3228_DRV_GRF_OFFSET 0x200 1226 1227 static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1228 int pin_num, struct regmap **regmap, 1229 int *reg, u8 *bit) 1230 { 1231 struct rockchip_pinctrl *info = bank->drvdata; 1232 1233 *regmap = info->regmap_base; 1234 *reg = RK3228_DRV_GRF_OFFSET; 1235 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 1236 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1237 1238 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 1239 *bit *= RK3288_DRV_BITS_PER_PIN; 1240 } 1241 1242 #define RK3368_PULL_GRF_OFFSET 0x100 1243 #define RK3368_PULL_PMU_OFFSET 0x10 1244 1245 static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1246 int pin_num, struct regmap **regmap, 1247 int *reg, u8 *bit) 1248 { 1249 struct rockchip_pinctrl *info = bank->drvdata; 1250 1251 /* The first 32 pins of the first bank are located in PMU */ 1252 if (bank->bank_num == 0) { 1253 *regmap = info->regmap_pmu; 1254 *reg = RK3368_PULL_PMU_OFFSET; 1255 1256 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1257 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 1258 *bit *= RK3188_PULL_BITS_PER_PIN; 1259 } else { 1260 *regmap = info->regmap_base; 1261 *reg = RK3368_PULL_GRF_OFFSET; 1262 1263 /* correct the offset, as we're starting with the 2nd bank */ 1264 *reg -= 0x10; 1265 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1266 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1267 1268 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1269 *bit *= RK3188_PULL_BITS_PER_PIN; 1270 } 1271 } 1272 1273 #define RK3368_DRV_PMU_OFFSET 0x20 1274 #define RK3368_DRV_GRF_OFFSET 0x200 1275 1276 static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1277 int pin_num, struct regmap **regmap, 1278 int *reg, u8 *bit) 1279 { 1280 struct rockchip_pinctrl *info = bank->drvdata; 1281 1282 /* The first 32 pins of the first bank are located in PMU */ 1283 if (bank->bank_num == 0) { 1284 *regmap = info->regmap_pmu; 1285 *reg = RK3368_DRV_PMU_OFFSET; 1286 1287 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1288 *bit = pin_num % RK3288_DRV_PINS_PER_REG; 1289 *bit *= RK3288_DRV_BITS_PER_PIN; 1290 } else { 1291 *regmap = info->regmap_base; 1292 *reg = RK3368_DRV_GRF_OFFSET; 1293 1294 /* correct the offset, as we're starting with the 2nd bank */ 1295 *reg -= 0x10; 1296 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 1297 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1298 1299 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 1300 *bit *= RK3288_DRV_BITS_PER_PIN; 1301 } 1302 } 1303 1304 #define RK3399_PULL_GRF_OFFSET 0xe040 1305 #define RK3399_PULL_PMU_OFFSET 0x40 1306 #define RK3399_DRV_3BITS_PER_PIN 3 1307 1308 static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1309 int pin_num, struct regmap **regmap, 1310 int *reg, u8 *bit) 1311 { 1312 struct rockchip_pinctrl *info = bank->drvdata; 1313 1314 /* The bank0:16 and bank1:32 pins are located in PMU */ 1315 if ((bank->bank_num == 0) || (bank->bank_num == 1)) { 1316 *regmap = info->regmap_pmu; 1317 *reg = RK3399_PULL_PMU_OFFSET; 1318 1319 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1320 1321 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1322 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 1323 *bit *= RK3188_PULL_BITS_PER_PIN; 1324 } else { 1325 *regmap = info->regmap_base; 1326 *reg = RK3399_PULL_GRF_OFFSET; 1327 1328 /* correct the offset, as we're starting with the 3rd bank */ 1329 *reg -= 0x20; 1330 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1331 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1332 1333 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1334 *bit *= RK3188_PULL_BITS_PER_PIN; 1335 } 1336 } 1337 1338 static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1339 int pin_num, struct regmap **regmap, 1340 int *reg, u8 *bit) 1341 { 1342 struct rockchip_pinctrl *info = bank->drvdata; 1343 int drv_num = (pin_num / 8); 1344 1345 /* The bank0:16 and bank1:32 pins are located in PMU */ 1346 if ((bank->bank_num == 0) || (bank->bank_num == 1)) 1347 *regmap = info->regmap_pmu; 1348 else 1349 *regmap = info->regmap_base; 1350 1351 *reg = bank->drv[drv_num].offset; 1352 if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) || 1353 (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY)) 1354 *bit = (pin_num % 8) * 3; 1355 else 1356 *bit = (pin_num % 8) * 2; 1357 } 1358 1359 static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = { 1360 { 2, 4, 8, 12, -1, -1, -1, -1 }, 1361 { 3, 6, 9, 12, -1, -1, -1, -1 }, 1362 { 5, 10, 15, 20, -1, -1, -1, -1 }, 1363 { 4, 6, 8, 10, 12, 14, 16, 18 }, 1364 { 4, 7, 10, 13, 16, 19, 22, 26 } 1365 }; 1366 1367 static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank, 1368 int pin_num) 1369 { 1370 struct rockchip_pinctrl *info = bank->drvdata; 1371 struct rockchip_pin_ctrl *ctrl = info->ctrl; 1372 struct regmap *regmap; 1373 int reg, ret; 1374 u32 data, temp, rmask_bits; 1375 u8 bit; 1376 int drv_type = bank->drv[pin_num / 8].drv_type; 1377 1378 ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); 1379 1380 switch (drv_type) { 1381 case DRV_TYPE_IO_1V8_3V0_AUTO: 1382 case DRV_TYPE_IO_3V3_ONLY: 1383 rmask_bits = RK3399_DRV_3BITS_PER_PIN; 1384 switch (bit) { 1385 case 0 ... 12: 1386 /* regular case, nothing to do */ 1387 break; 1388 case 15: 1389 /* 1390 * drive-strength offset is special, as it is 1391 * spread over 2 registers 1392 */ 1393 ret = regmap_read(regmap, reg, &data); 1394 if (ret) 1395 return ret; 1396 1397 ret = regmap_read(regmap, reg + 0x4, &temp); 1398 if (ret) 1399 return ret; 1400 1401 /* 1402 * the bit data[15] contains bit 0 of the value 1403 * while temp[1:0] contains bits 2 and 1 1404 */ 1405 data >>= 15; 1406 temp &= 0x3; 1407 temp <<= 1; 1408 data |= temp; 1409 1410 return rockchip_perpin_drv_list[drv_type][data]; 1411 case 18 ... 21: 1412 /* setting fully enclosed in the second register */ 1413 reg += 4; 1414 bit -= 16; 1415 break; 1416 default: 1417 dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n", 1418 bit, drv_type); 1419 return -EINVAL; 1420 } 1421 1422 break; 1423 case DRV_TYPE_IO_DEFAULT: 1424 case DRV_TYPE_IO_1V8_OR_3V0: 1425 case DRV_TYPE_IO_1V8_ONLY: 1426 rmask_bits = RK3288_DRV_BITS_PER_PIN; 1427 break; 1428 default: 1429 dev_err(info->dev, "unsupported pinctrl drive type: %d\n", 1430 drv_type); 1431 return -EINVAL; 1432 } 1433 1434 ret = regmap_read(regmap, reg, &data); 1435 if (ret) 1436 return ret; 1437 1438 data >>= bit; 1439 data &= (1 << rmask_bits) - 1; 1440 1441 return rockchip_perpin_drv_list[drv_type][data]; 1442 } 1443 1444 static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank, 1445 int pin_num, int strength) 1446 { 1447 struct rockchip_pinctrl *info = bank->drvdata; 1448 struct rockchip_pin_ctrl *ctrl = info->ctrl; 1449 struct regmap *regmap; 1450 int reg, ret, i; 1451 u32 data, rmask, rmask_bits, temp; 1452 u8 bit; 1453 int drv_type = bank->drv[pin_num / 8].drv_type; 1454 1455 dev_dbg(info->dev, "setting drive of GPIO%d-%d to %d\n", 1456 bank->bank_num, pin_num, strength); 1457 1458 ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); 1459 1460 ret = -EINVAL; 1461 for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) { 1462 if (rockchip_perpin_drv_list[drv_type][i] == strength) { 1463 ret = i; 1464 break; 1465 } else if (rockchip_perpin_drv_list[drv_type][i] < 0) { 1466 ret = rockchip_perpin_drv_list[drv_type][i]; 1467 break; 1468 } 1469 } 1470 1471 if (ret < 0) { 1472 dev_err(info->dev, "unsupported driver strength %d\n", 1473 strength); 1474 return ret; 1475 } 1476 1477 switch (drv_type) { 1478 case DRV_TYPE_IO_1V8_3V0_AUTO: 1479 case DRV_TYPE_IO_3V3_ONLY: 1480 rmask_bits = RK3399_DRV_3BITS_PER_PIN; 1481 switch (bit) { 1482 case 0 ... 12: 1483 /* regular case, nothing to do */ 1484 break; 1485 case 15: 1486 /* 1487 * drive-strength offset is special, as it is spread 1488 * over 2 registers, the bit data[15] contains bit 0 1489 * of the value while temp[1:0] contains bits 2 and 1 1490 */ 1491 data = (ret & 0x1) << 15; 1492 temp = (ret >> 0x1) & 0x3; 1493 1494 rmask = BIT(15) | BIT(31); 1495 data |= BIT(31); 1496 ret = regmap_update_bits(regmap, reg, rmask, data); 1497 if (ret) 1498 return ret; 1499 1500 rmask = 0x3 | (0x3 << 16); 1501 temp |= (0x3 << 16); 1502 reg += 0x4; 1503 ret = regmap_update_bits(regmap, reg, rmask, temp); 1504 1505 return ret; 1506 case 18 ... 21: 1507 /* setting fully enclosed in the second register */ 1508 reg += 4; 1509 bit -= 16; 1510 break; 1511 default: 1512 dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n", 1513 bit, drv_type); 1514 return -EINVAL; 1515 } 1516 break; 1517 case DRV_TYPE_IO_DEFAULT: 1518 case DRV_TYPE_IO_1V8_OR_3V0: 1519 case DRV_TYPE_IO_1V8_ONLY: 1520 rmask_bits = RK3288_DRV_BITS_PER_PIN; 1521 break; 1522 default: 1523 dev_err(info->dev, "unsupported pinctrl drive type: %d\n", 1524 drv_type); 1525 return -EINVAL; 1526 } 1527 1528 /* enable the write to the equivalent lower bits */ 1529 data = ((1 << rmask_bits) - 1) << (bit + 16); 1530 rmask = data | (data >> 16); 1531 data |= (ret << bit); 1532 1533 ret = regmap_update_bits(regmap, reg, rmask, data); 1534 1535 return ret; 1536 } 1537 1538 static int rockchip_pull_list[PULL_TYPE_MAX][4] = { 1539 { 1540 PIN_CONFIG_BIAS_DISABLE, 1541 PIN_CONFIG_BIAS_PULL_UP, 1542 PIN_CONFIG_BIAS_PULL_DOWN, 1543 PIN_CONFIG_BIAS_BUS_HOLD 1544 }, 1545 { 1546 PIN_CONFIG_BIAS_DISABLE, 1547 PIN_CONFIG_BIAS_PULL_DOWN, 1548 PIN_CONFIG_BIAS_DISABLE, 1549 PIN_CONFIG_BIAS_PULL_UP 1550 }, 1551 }; 1552 1553 static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num) 1554 { 1555 struct rockchip_pinctrl *info = bank->drvdata; 1556 struct rockchip_pin_ctrl *ctrl = info->ctrl; 1557 struct regmap *regmap; 1558 int reg, ret, pull_type; 1559 u8 bit; 1560 u32 data; 1561 1562 /* rk3066b does support any pulls */ 1563 if (ctrl->type == RK3066B) 1564 return PIN_CONFIG_BIAS_DISABLE; 1565 1566 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); 1567 1568 ret = regmap_read(regmap, reg, &data); 1569 if (ret) 1570 return ret; 1571 1572 switch (ctrl->type) { 1573 case RK2928: 1574 return !(data & BIT(bit)) 1575 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT 1576 : PIN_CONFIG_BIAS_DISABLE; 1577 case RV1108: 1578 case RK3188: 1579 case RK3288: 1580 case RK3368: 1581 case RK3399: 1582 pull_type = bank->pull_type[pin_num / 8]; 1583 data >>= bit; 1584 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1; 1585 1586 return rockchip_pull_list[pull_type][data]; 1587 default: 1588 dev_err(info->dev, "unsupported pinctrl type\n"); 1589 return -EINVAL; 1590 }; 1591 } 1592 1593 static int rockchip_set_pull(struct rockchip_pin_bank *bank, 1594 int pin_num, int pull) 1595 { 1596 struct rockchip_pinctrl *info = bank->drvdata; 1597 struct rockchip_pin_ctrl *ctrl = info->ctrl; 1598 struct regmap *regmap; 1599 int reg, ret, i, pull_type; 1600 u8 bit; 1601 u32 data, rmask; 1602 1603 dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n", 1604 bank->bank_num, pin_num, pull); 1605 1606 /* rk3066b does support any pulls */ 1607 if (ctrl->type == RK3066B) 1608 return pull ? -EINVAL : 0; 1609 1610 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); 1611 1612 switch (ctrl->type) { 1613 case RK2928: 1614 data = BIT(bit + 16); 1615 if (pull == PIN_CONFIG_BIAS_DISABLE) 1616 data |= BIT(bit); 1617 ret = regmap_write(regmap, reg, data); 1618 break; 1619 case RV1108: 1620 case RK3188: 1621 case RK3288: 1622 case RK3368: 1623 case RK3399: 1624 pull_type = bank->pull_type[pin_num / 8]; 1625 ret = -EINVAL; 1626 for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]); 1627 i++) { 1628 if (rockchip_pull_list[pull_type][i] == pull) { 1629 ret = i; 1630 break; 1631 } 1632 } 1633 1634 if (ret < 0) { 1635 dev_err(info->dev, "unsupported pull setting %d\n", 1636 pull); 1637 return ret; 1638 } 1639 1640 /* enable the write to the equivalent lower bits */ 1641 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16); 1642 rmask = data | (data >> 16); 1643 data |= (ret << bit); 1644 1645 ret = regmap_update_bits(regmap, reg, rmask, data); 1646 break; 1647 default: 1648 dev_err(info->dev, "unsupported pinctrl type\n"); 1649 return -EINVAL; 1650 } 1651 1652 return ret; 1653 } 1654 1655 #define RK3328_SCHMITT_BITS_PER_PIN 1 1656 #define RK3328_SCHMITT_PINS_PER_REG 16 1657 #define RK3328_SCHMITT_BANK_STRIDE 8 1658 #define RK3328_SCHMITT_GRF_OFFSET 0x380 1659 1660 static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1661 int pin_num, 1662 struct regmap **regmap, 1663 int *reg, u8 *bit) 1664 { 1665 struct rockchip_pinctrl *info = bank->drvdata; 1666 1667 *regmap = info->regmap_base; 1668 *reg = RK3328_SCHMITT_GRF_OFFSET; 1669 1670 *reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE; 1671 *reg += ((pin_num / RK3328_SCHMITT_PINS_PER_REG) * 4); 1672 *bit = pin_num % RK3328_SCHMITT_PINS_PER_REG; 1673 1674 return 0; 1675 } 1676 1677 static int rockchip_get_schmitt(struct rockchip_pin_bank *bank, int pin_num) 1678 { 1679 struct rockchip_pinctrl *info = bank->drvdata; 1680 struct rockchip_pin_ctrl *ctrl = info->ctrl; 1681 struct regmap *regmap; 1682 int reg, ret; 1683 u8 bit; 1684 u32 data; 1685 1686 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit); 1687 if (ret) 1688 return ret; 1689 1690 ret = regmap_read(regmap, reg, &data); 1691 if (ret) 1692 return ret; 1693 1694 data >>= bit; 1695 return data & 0x1; 1696 } 1697 1698 static int rockchip_set_schmitt(struct rockchip_pin_bank *bank, 1699 int pin_num, int enable) 1700 { 1701 struct rockchip_pinctrl *info = bank->drvdata; 1702 struct rockchip_pin_ctrl *ctrl = info->ctrl; 1703 struct regmap *regmap; 1704 int reg, ret; 1705 u8 bit; 1706 u32 data, rmask; 1707 1708 dev_dbg(info->dev, "setting input schmitt of GPIO%d-%d to %d\n", 1709 bank->bank_num, pin_num, enable); 1710 1711 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit); 1712 if (ret) 1713 return ret; 1714 1715 /* enable the write to the equivalent lower bits */ 1716 data = BIT(bit + 16) | (enable << bit); 1717 rmask = BIT(bit + 16) | BIT(bit); 1718 1719 return regmap_update_bits(regmap, reg, rmask, data); 1720 } 1721 1722 /* 1723 * Pinmux_ops handling 1724 */ 1725 1726 static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev) 1727 { 1728 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1729 1730 return info->nfunctions; 1731 } 1732 1733 static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev, 1734 unsigned selector) 1735 { 1736 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1737 1738 return info->functions[selector].name; 1739 } 1740 1741 static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev, 1742 unsigned selector, const char * const **groups, 1743 unsigned * const num_groups) 1744 { 1745 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1746 1747 *groups = info->functions[selector].groups; 1748 *num_groups = info->functions[selector].ngroups; 1749 1750 return 0; 1751 } 1752 1753 static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector, 1754 unsigned group) 1755 { 1756 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1757 const unsigned int *pins = info->groups[group].pins; 1758 const struct rockchip_pin_config *data = info->groups[group].data; 1759 struct rockchip_pin_bank *bank; 1760 int cnt, ret = 0; 1761 1762 dev_dbg(info->dev, "enable function %s group %s\n", 1763 info->functions[selector].name, info->groups[group].name); 1764 1765 /* 1766 * for each pin in the pin group selected, program the correspoding pin 1767 * pin function number in the config register. 1768 */ 1769 for (cnt = 0; cnt < info->groups[group].npins; cnt++) { 1770 bank = pin_to_bank(info, pins[cnt]); 1771 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 1772 data[cnt].func); 1773 if (ret) 1774 break; 1775 } 1776 1777 if (ret) { 1778 /* revert the already done pin settings */ 1779 for (cnt--; cnt >= 0; cnt--) 1780 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0); 1781 1782 return ret; 1783 } 1784 1785 return 0; 1786 } 1787 1788 static int rockchip_gpio_get_direction(struct gpio_chip *chip, unsigned offset) 1789 { 1790 struct rockchip_pin_bank *bank = gpiochip_get_data(chip); 1791 u32 data; 1792 1793 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); 1794 1795 return !(data & BIT(offset)); 1796 } 1797 1798 /* 1799 * The calls to gpio_direction_output() and gpio_direction_input() 1800 * leads to this function call (via the pinctrl_gpio_direction_{input|output}() 1801 * function called from the gpiolib interface). 1802 */ 1803 static int _rockchip_pmx_gpio_set_direction(struct gpio_chip *chip, 1804 int pin, bool input) 1805 { 1806 struct rockchip_pin_bank *bank; 1807 int ret; 1808 unsigned long flags; 1809 u32 data; 1810 1811 bank = gpiochip_get_data(chip); 1812 1813 ret = rockchip_set_mux(bank, pin, RK_FUNC_GPIO); 1814 if (ret < 0) 1815 return ret; 1816 1817 clk_enable(bank->clk); 1818 raw_spin_lock_irqsave(&bank->slock, flags); 1819 1820 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); 1821 /* set bit to 1 for output, 0 for input */ 1822 if (!input) 1823 data |= BIT(pin); 1824 else 1825 data &= ~BIT(pin); 1826 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR); 1827 1828 raw_spin_unlock_irqrestore(&bank->slock, flags); 1829 clk_disable(bank->clk); 1830 1831 return 0; 1832 } 1833 1834 static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, 1835 struct pinctrl_gpio_range *range, 1836 unsigned offset, bool input) 1837 { 1838 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1839 struct gpio_chip *chip; 1840 int pin; 1841 1842 chip = range->gc; 1843 pin = offset - chip->base; 1844 dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n", 1845 offset, range->name, pin, input ? "input" : "output"); 1846 1847 return _rockchip_pmx_gpio_set_direction(chip, offset - chip->base, 1848 input); 1849 } 1850 1851 static const struct pinmux_ops rockchip_pmx_ops = { 1852 .get_functions_count = rockchip_pmx_get_funcs_count, 1853 .get_function_name = rockchip_pmx_get_func_name, 1854 .get_function_groups = rockchip_pmx_get_groups, 1855 .set_mux = rockchip_pmx_set, 1856 .gpio_set_direction = rockchip_pmx_gpio_set_direction, 1857 }; 1858 1859 /* 1860 * Pinconf_ops handling 1861 */ 1862 1863 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl, 1864 enum pin_config_param pull) 1865 { 1866 switch (ctrl->type) { 1867 case RK2928: 1868 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT || 1869 pull == PIN_CONFIG_BIAS_DISABLE); 1870 case RK3066B: 1871 return pull ? false : true; 1872 case RV1108: 1873 case RK3188: 1874 case RK3288: 1875 case RK3368: 1876 case RK3399: 1877 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT); 1878 } 1879 1880 return false; 1881 } 1882 1883 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value); 1884 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset); 1885 1886 /* set the pin config settings for a specified pin */ 1887 static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 1888 unsigned long *configs, unsigned num_configs) 1889 { 1890 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1891 struct rockchip_pin_bank *bank = pin_to_bank(info, pin); 1892 enum pin_config_param param; 1893 u32 arg; 1894 int i; 1895 int rc; 1896 1897 for (i = 0; i < num_configs; i++) { 1898 param = pinconf_to_config_param(configs[i]); 1899 arg = pinconf_to_config_argument(configs[i]); 1900 1901 switch (param) { 1902 case PIN_CONFIG_BIAS_DISABLE: 1903 rc = rockchip_set_pull(bank, pin - bank->pin_base, 1904 param); 1905 if (rc) 1906 return rc; 1907 break; 1908 case PIN_CONFIG_BIAS_PULL_UP: 1909 case PIN_CONFIG_BIAS_PULL_DOWN: 1910 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: 1911 case PIN_CONFIG_BIAS_BUS_HOLD: 1912 if (!rockchip_pinconf_pull_valid(info->ctrl, param)) 1913 return -ENOTSUPP; 1914 1915 if (!arg) 1916 return -EINVAL; 1917 1918 rc = rockchip_set_pull(bank, pin - bank->pin_base, 1919 param); 1920 if (rc) 1921 return rc; 1922 break; 1923 case PIN_CONFIG_OUTPUT: 1924 rockchip_gpio_set(&bank->gpio_chip, 1925 pin - bank->pin_base, arg); 1926 rc = _rockchip_pmx_gpio_set_direction(&bank->gpio_chip, 1927 pin - bank->pin_base, false); 1928 if (rc) 1929 return rc; 1930 break; 1931 case PIN_CONFIG_DRIVE_STRENGTH: 1932 /* rk3288 is the first with per-pin drive-strength */ 1933 if (!info->ctrl->drv_calc_reg) 1934 return -ENOTSUPP; 1935 1936 rc = rockchip_set_drive_perpin(bank, 1937 pin - bank->pin_base, arg); 1938 if (rc < 0) 1939 return rc; 1940 break; 1941 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 1942 if (!info->ctrl->schmitt_calc_reg) 1943 return -ENOTSUPP; 1944 1945 rc = rockchip_set_schmitt(bank, 1946 pin - bank->pin_base, arg); 1947 if (rc < 0) 1948 return rc; 1949 break; 1950 default: 1951 return -ENOTSUPP; 1952 break; 1953 } 1954 } /* for each config */ 1955 1956 return 0; 1957 } 1958 1959 /* get the pin config settings for a specified pin */ 1960 static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, 1961 unsigned long *config) 1962 { 1963 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1964 struct rockchip_pin_bank *bank = pin_to_bank(info, pin); 1965 enum pin_config_param param = pinconf_to_config_param(*config); 1966 u16 arg; 1967 int rc; 1968 1969 switch (param) { 1970 case PIN_CONFIG_BIAS_DISABLE: 1971 if (rockchip_get_pull(bank, pin - bank->pin_base) != param) 1972 return -EINVAL; 1973 1974 arg = 0; 1975 break; 1976 case PIN_CONFIG_BIAS_PULL_UP: 1977 case PIN_CONFIG_BIAS_PULL_DOWN: 1978 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: 1979 case PIN_CONFIG_BIAS_BUS_HOLD: 1980 if (!rockchip_pinconf_pull_valid(info->ctrl, param)) 1981 return -ENOTSUPP; 1982 1983 if (rockchip_get_pull(bank, pin - bank->pin_base) != param) 1984 return -EINVAL; 1985 1986 arg = 1; 1987 break; 1988 case PIN_CONFIG_OUTPUT: 1989 rc = rockchip_get_mux(bank, pin - bank->pin_base); 1990 if (rc != RK_FUNC_GPIO) 1991 return -EINVAL; 1992 1993 rc = rockchip_gpio_get(&bank->gpio_chip, pin - bank->pin_base); 1994 if (rc < 0) 1995 return rc; 1996 1997 arg = rc ? 1 : 0; 1998 break; 1999 case PIN_CONFIG_DRIVE_STRENGTH: 2000 /* rk3288 is the first with per-pin drive-strength */ 2001 if (!info->ctrl->drv_calc_reg) 2002 return -ENOTSUPP; 2003 2004 rc = rockchip_get_drive_perpin(bank, pin - bank->pin_base); 2005 if (rc < 0) 2006 return rc; 2007 2008 arg = rc; 2009 break; 2010 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 2011 if (!info->ctrl->schmitt_calc_reg) 2012 return -ENOTSUPP; 2013 2014 rc = rockchip_get_schmitt(bank, pin - bank->pin_base); 2015 if (rc < 0) 2016 return rc; 2017 2018 arg = rc; 2019 break; 2020 default: 2021 return -ENOTSUPP; 2022 break; 2023 } 2024 2025 *config = pinconf_to_config_packed(param, arg); 2026 2027 return 0; 2028 } 2029 2030 static const struct pinconf_ops rockchip_pinconf_ops = { 2031 .pin_config_get = rockchip_pinconf_get, 2032 .pin_config_set = rockchip_pinconf_set, 2033 .is_generic = true, 2034 }; 2035 2036 static const struct of_device_id rockchip_bank_match[] = { 2037 { .compatible = "rockchip,gpio-bank" }, 2038 { .compatible = "rockchip,rk3188-gpio-bank0" }, 2039 {}, 2040 }; 2041 2042 static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info, 2043 struct device_node *np) 2044 { 2045 struct device_node *child; 2046 2047 for_each_child_of_node(np, child) { 2048 if (of_match_node(rockchip_bank_match, child)) 2049 continue; 2050 2051 info->nfunctions++; 2052 info->ngroups += of_get_child_count(child); 2053 } 2054 } 2055 2056 static int rockchip_pinctrl_parse_groups(struct device_node *np, 2057 struct rockchip_pin_group *grp, 2058 struct rockchip_pinctrl *info, 2059 u32 index) 2060 { 2061 struct rockchip_pin_bank *bank; 2062 int size; 2063 const __be32 *list; 2064 int num; 2065 int i, j; 2066 int ret; 2067 2068 dev_dbg(info->dev, "group(%d): %s\n", index, np->name); 2069 2070 /* Initialise group */ 2071 grp->name = np->name; 2072 2073 /* 2074 * the binding format is rockchip,pins = <bank pin mux CONFIG>, 2075 * do sanity check and calculate pins number 2076 */ 2077 list = of_get_property(np, "rockchip,pins", &size); 2078 /* we do not check return since it's safe node passed down */ 2079 size /= sizeof(*list); 2080 if (!size || size % 4) { 2081 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n"); 2082 return -EINVAL; 2083 } 2084 2085 grp->npins = size / 4; 2086 2087 grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int), 2088 GFP_KERNEL); 2089 grp->data = devm_kzalloc(info->dev, grp->npins * 2090 sizeof(struct rockchip_pin_config), 2091 GFP_KERNEL); 2092 if (!grp->pins || !grp->data) 2093 return -ENOMEM; 2094 2095 for (i = 0, j = 0; i < size; i += 4, j++) { 2096 const __be32 *phandle; 2097 struct device_node *np_config; 2098 2099 num = be32_to_cpu(*list++); 2100 bank = bank_num_to_bank(info, num); 2101 if (IS_ERR(bank)) 2102 return PTR_ERR(bank); 2103 2104 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++); 2105 grp->data[j].func = be32_to_cpu(*list++); 2106 2107 phandle = list++; 2108 if (!phandle) 2109 return -EINVAL; 2110 2111 np_config = of_find_node_by_phandle(be32_to_cpup(phandle)); 2112 ret = pinconf_generic_parse_dt_config(np_config, NULL, 2113 &grp->data[j].configs, &grp->data[j].nconfigs); 2114 if (ret) 2115 return ret; 2116 } 2117 2118 return 0; 2119 } 2120 2121 static int rockchip_pinctrl_parse_functions(struct device_node *np, 2122 struct rockchip_pinctrl *info, 2123 u32 index) 2124 { 2125 struct device_node *child; 2126 struct rockchip_pmx_func *func; 2127 struct rockchip_pin_group *grp; 2128 int ret; 2129 static u32 grp_index; 2130 u32 i = 0; 2131 2132 dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name); 2133 2134 func = &info->functions[index]; 2135 2136 /* Initialise function */ 2137 func->name = np->name; 2138 func->ngroups = of_get_child_count(np); 2139 if (func->ngroups <= 0) 2140 return 0; 2141 2142 func->groups = devm_kzalloc(info->dev, 2143 func->ngroups * sizeof(char *), GFP_KERNEL); 2144 if (!func->groups) 2145 return -ENOMEM; 2146 2147 for_each_child_of_node(np, child) { 2148 func->groups[i] = child->name; 2149 grp = &info->groups[grp_index++]; 2150 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++); 2151 if (ret) { 2152 of_node_put(child); 2153 return ret; 2154 } 2155 } 2156 2157 return 0; 2158 } 2159 2160 static int rockchip_pinctrl_parse_dt(struct platform_device *pdev, 2161 struct rockchip_pinctrl *info) 2162 { 2163 struct device *dev = &pdev->dev; 2164 struct device_node *np = dev->of_node; 2165 struct device_node *child; 2166 int ret; 2167 int i; 2168 2169 rockchip_pinctrl_child_count(info, np); 2170 2171 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions); 2172 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups); 2173 2174 info->functions = devm_kzalloc(dev, info->nfunctions * 2175 sizeof(struct rockchip_pmx_func), 2176 GFP_KERNEL); 2177 if (!info->functions) { 2178 dev_err(dev, "failed to allocate memory for function list\n"); 2179 return -EINVAL; 2180 } 2181 2182 info->groups = devm_kzalloc(dev, info->ngroups * 2183 sizeof(struct rockchip_pin_group), 2184 GFP_KERNEL); 2185 if (!info->groups) { 2186 dev_err(dev, "failed allocate memory for ping group list\n"); 2187 return -EINVAL; 2188 } 2189 2190 i = 0; 2191 2192 for_each_child_of_node(np, child) { 2193 if (of_match_node(rockchip_bank_match, child)) 2194 continue; 2195 2196 ret = rockchip_pinctrl_parse_functions(child, info, i++); 2197 if (ret) { 2198 dev_err(&pdev->dev, "failed to parse function\n"); 2199 of_node_put(child); 2200 return ret; 2201 } 2202 } 2203 2204 return 0; 2205 } 2206 2207 static int rockchip_pinctrl_register(struct platform_device *pdev, 2208 struct rockchip_pinctrl *info) 2209 { 2210 struct pinctrl_desc *ctrldesc = &info->pctl; 2211 struct pinctrl_pin_desc *pindesc, *pdesc; 2212 struct rockchip_pin_bank *pin_bank; 2213 int pin, bank, ret; 2214 int k; 2215 2216 ctrldesc->name = "rockchip-pinctrl"; 2217 ctrldesc->owner = THIS_MODULE; 2218 ctrldesc->pctlops = &rockchip_pctrl_ops; 2219 ctrldesc->pmxops = &rockchip_pmx_ops; 2220 ctrldesc->confops = &rockchip_pinconf_ops; 2221 2222 pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) * 2223 info->ctrl->nr_pins, GFP_KERNEL); 2224 if (!pindesc) { 2225 dev_err(&pdev->dev, "mem alloc for pin descriptors failed\n"); 2226 return -ENOMEM; 2227 } 2228 ctrldesc->pins = pindesc; 2229 ctrldesc->npins = info->ctrl->nr_pins; 2230 2231 pdesc = pindesc; 2232 for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) { 2233 pin_bank = &info->ctrl->pin_banks[bank]; 2234 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) { 2235 pdesc->number = k; 2236 pdesc->name = kasprintf(GFP_KERNEL, "%s-%d", 2237 pin_bank->name, pin); 2238 pdesc++; 2239 } 2240 } 2241 2242 ret = rockchip_pinctrl_parse_dt(pdev, info); 2243 if (ret) 2244 return ret; 2245 2246 info->pctl_dev = devm_pinctrl_register(&pdev->dev, ctrldesc, info); 2247 if (IS_ERR(info->pctl_dev)) { 2248 dev_err(&pdev->dev, "could not register pinctrl driver\n"); 2249 return PTR_ERR(info->pctl_dev); 2250 } 2251 2252 for (bank = 0; bank < info->ctrl->nr_banks; ++bank) { 2253 pin_bank = &info->ctrl->pin_banks[bank]; 2254 pin_bank->grange.name = pin_bank->name; 2255 pin_bank->grange.id = bank; 2256 pin_bank->grange.pin_base = pin_bank->pin_base; 2257 pin_bank->grange.base = pin_bank->gpio_chip.base; 2258 pin_bank->grange.npins = pin_bank->gpio_chip.ngpio; 2259 pin_bank->grange.gc = &pin_bank->gpio_chip; 2260 pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange); 2261 } 2262 2263 return 0; 2264 } 2265 2266 /* 2267 * GPIO handling 2268 */ 2269 2270 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value) 2271 { 2272 struct rockchip_pin_bank *bank = gpiochip_get_data(gc); 2273 void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR; 2274 unsigned long flags; 2275 u32 data; 2276 2277 clk_enable(bank->clk); 2278 raw_spin_lock_irqsave(&bank->slock, flags); 2279 2280 data = readl(reg); 2281 data &= ~BIT(offset); 2282 if (value) 2283 data |= BIT(offset); 2284 writel(data, reg); 2285 2286 raw_spin_unlock_irqrestore(&bank->slock, flags); 2287 clk_disable(bank->clk); 2288 } 2289 2290 /* 2291 * Returns the level of the pin for input direction and setting of the DR 2292 * register for output gpios. 2293 */ 2294 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset) 2295 { 2296 struct rockchip_pin_bank *bank = gpiochip_get_data(gc); 2297 u32 data; 2298 2299 clk_enable(bank->clk); 2300 data = readl(bank->reg_base + GPIO_EXT_PORT); 2301 clk_disable(bank->clk); 2302 data >>= offset; 2303 data &= 1; 2304 return data; 2305 } 2306 2307 /* 2308 * gpiolib gpio_direction_input callback function. The setting of the pin 2309 * mux function as 'gpio input' will be handled by the pinctrl susbsystem 2310 * interface. 2311 */ 2312 static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset) 2313 { 2314 return pinctrl_gpio_direction_input(gc->base + offset); 2315 } 2316 2317 /* 2318 * gpiolib gpio_direction_output callback function. The setting of the pin 2319 * mux function as 'gpio output' will be handled by the pinctrl susbsystem 2320 * interface. 2321 */ 2322 static int rockchip_gpio_direction_output(struct gpio_chip *gc, 2323 unsigned offset, int value) 2324 { 2325 rockchip_gpio_set(gc, offset, value); 2326 return pinctrl_gpio_direction_output(gc->base + offset); 2327 } 2328 2329 /* 2330 * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin 2331 * and a virtual IRQ, if not already present. 2332 */ 2333 static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset) 2334 { 2335 struct rockchip_pin_bank *bank = gpiochip_get_data(gc); 2336 unsigned int virq; 2337 2338 if (!bank->domain) 2339 return -ENXIO; 2340 2341 virq = irq_create_mapping(bank->domain, offset); 2342 2343 return (virq) ? : -ENXIO; 2344 } 2345 2346 static const struct gpio_chip rockchip_gpiolib_chip = { 2347 .request = gpiochip_generic_request, 2348 .free = gpiochip_generic_free, 2349 .set = rockchip_gpio_set, 2350 .get = rockchip_gpio_get, 2351 .get_direction = rockchip_gpio_get_direction, 2352 .direction_input = rockchip_gpio_direction_input, 2353 .direction_output = rockchip_gpio_direction_output, 2354 .to_irq = rockchip_gpio_to_irq, 2355 .owner = THIS_MODULE, 2356 }; 2357 2358 /* 2359 * Interrupt handling 2360 */ 2361 2362 static void rockchip_irq_demux(struct irq_desc *desc) 2363 { 2364 struct irq_chip *chip = irq_desc_get_chip(desc); 2365 struct rockchip_pin_bank *bank = irq_desc_get_handler_data(desc); 2366 u32 pend; 2367 2368 dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name); 2369 2370 chained_irq_enter(chip, desc); 2371 2372 pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS); 2373 2374 while (pend) { 2375 unsigned int irq, virq; 2376 2377 irq = __ffs(pend); 2378 pend &= ~BIT(irq); 2379 virq = irq_linear_revmap(bank->domain, irq); 2380 2381 if (!virq) { 2382 dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq); 2383 continue; 2384 } 2385 2386 dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq); 2387 2388 /* 2389 * Triggering IRQ on both rising and falling edge 2390 * needs manual intervention. 2391 */ 2392 if (bank->toggle_edge_mode & BIT(irq)) { 2393 u32 data, data_old, polarity; 2394 unsigned long flags; 2395 2396 data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT); 2397 do { 2398 raw_spin_lock_irqsave(&bank->slock, flags); 2399 2400 polarity = readl_relaxed(bank->reg_base + 2401 GPIO_INT_POLARITY); 2402 if (data & BIT(irq)) 2403 polarity &= ~BIT(irq); 2404 else 2405 polarity |= BIT(irq); 2406 writel(polarity, 2407 bank->reg_base + GPIO_INT_POLARITY); 2408 2409 raw_spin_unlock_irqrestore(&bank->slock, flags); 2410 2411 data_old = data; 2412 data = readl_relaxed(bank->reg_base + 2413 GPIO_EXT_PORT); 2414 } while ((data & BIT(irq)) != (data_old & BIT(irq))); 2415 } 2416 2417 generic_handle_irq(virq); 2418 } 2419 2420 chained_irq_exit(chip, desc); 2421 } 2422 2423 static int rockchip_irq_set_type(struct irq_data *d, unsigned int type) 2424 { 2425 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 2426 struct rockchip_pin_bank *bank = gc->private; 2427 u32 mask = BIT(d->hwirq); 2428 u32 polarity; 2429 u32 level; 2430 u32 data; 2431 unsigned long flags; 2432 int ret; 2433 2434 /* make sure the pin is configured as gpio input */ 2435 ret = rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO); 2436 if (ret < 0) 2437 return ret; 2438 2439 clk_enable(bank->clk); 2440 raw_spin_lock_irqsave(&bank->slock, flags); 2441 2442 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); 2443 data &= ~mask; 2444 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR); 2445 2446 raw_spin_unlock_irqrestore(&bank->slock, flags); 2447 2448 if (type & IRQ_TYPE_EDGE_BOTH) 2449 irq_set_handler_locked(d, handle_edge_irq); 2450 else 2451 irq_set_handler_locked(d, handle_level_irq); 2452 2453 raw_spin_lock_irqsave(&bank->slock, flags); 2454 irq_gc_lock(gc); 2455 2456 level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL); 2457 polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY); 2458 2459 switch (type) { 2460 case IRQ_TYPE_EDGE_BOTH: 2461 bank->toggle_edge_mode |= mask; 2462 level |= mask; 2463 2464 /* 2465 * Determine gpio state. If 1 next interrupt should be falling 2466 * otherwise rising. 2467 */ 2468 data = readl(bank->reg_base + GPIO_EXT_PORT); 2469 if (data & mask) 2470 polarity &= ~mask; 2471 else 2472 polarity |= mask; 2473 break; 2474 case IRQ_TYPE_EDGE_RISING: 2475 bank->toggle_edge_mode &= ~mask; 2476 level |= mask; 2477 polarity |= mask; 2478 break; 2479 case IRQ_TYPE_EDGE_FALLING: 2480 bank->toggle_edge_mode &= ~mask; 2481 level |= mask; 2482 polarity &= ~mask; 2483 break; 2484 case IRQ_TYPE_LEVEL_HIGH: 2485 bank->toggle_edge_mode &= ~mask; 2486 level &= ~mask; 2487 polarity |= mask; 2488 break; 2489 case IRQ_TYPE_LEVEL_LOW: 2490 bank->toggle_edge_mode &= ~mask; 2491 level &= ~mask; 2492 polarity &= ~mask; 2493 break; 2494 default: 2495 irq_gc_unlock(gc); 2496 raw_spin_unlock_irqrestore(&bank->slock, flags); 2497 clk_disable(bank->clk); 2498 return -EINVAL; 2499 } 2500 2501 writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL); 2502 writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY); 2503 2504 irq_gc_unlock(gc); 2505 raw_spin_unlock_irqrestore(&bank->slock, flags); 2506 clk_disable(bank->clk); 2507 2508 return 0; 2509 } 2510 2511 static void rockchip_irq_suspend(struct irq_data *d) 2512 { 2513 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 2514 struct rockchip_pin_bank *bank = gc->private; 2515 2516 clk_enable(bank->clk); 2517 bank->saved_masks = irq_reg_readl(gc, GPIO_INTMASK); 2518 irq_reg_writel(gc, ~gc->wake_active, GPIO_INTMASK); 2519 clk_disable(bank->clk); 2520 } 2521 2522 static void rockchip_irq_resume(struct irq_data *d) 2523 { 2524 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 2525 struct rockchip_pin_bank *bank = gc->private; 2526 2527 clk_enable(bank->clk); 2528 irq_reg_writel(gc, bank->saved_masks, GPIO_INTMASK); 2529 clk_disable(bank->clk); 2530 } 2531 2532 static void rockchip_irq_enable(struct irq_data *d) 2533 { 2534 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 2535 struct rockchip_pin_bank *bank = gc->private; 2536 2537 clk_enable(bank->clk); 2538 irq_gc_mask_clr_bit(d); 2539 } 2540 2541 static void rockchip_irq_disable(struct irq_data *d) 2542 { 2543 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 2544 struct rockchip_pin_bank *bank = gc->private; 2545 2546 irq_gc_mask_set_bit(d); 2547 clk_disable(bank->clk); 2548 } 2549 2550 static int rockchip_interrupts_register(struct platform_device *pdev, 2551 struct rockchip_pinctrl *info) 2552 { 2553 struct rockchip_pin_ctrl *ctrl = info->ctrl; 2554 struct rockchip_pin_bank *bank = ctrl->pin_banks; 2555 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; 2556 struct irq_chip_generic *gc; 2557 int ret; 2558 int i, j; 2559 2560 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 2561 if (!bank->valid) { 2562 dev_warn(&pdev->dev, "bank %s is not valid\n", 2563 bank->name); 2564 continue; 2565 } 2566 2567 ret = clk_enable(bank->clk); 2568 if (ret) { 2569 dev_err(&pdev->dev, "failed to enable clock for bank %s\n", 2570 bank->name); 2571 continue; 2572 } 2573 2574 bank->domain = irq_domain_add_linear(bank->of_node, 32, 2575 &irq_generic_chip_ops, NULL); 2576 if (!bank->domain) { 2577 dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n", 2578 bank->name); 2579 clk_disable(bank->clk); 2580 continue; 2581 } 2582 2583 ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1, 2584 "rockchip_gpio_irq", handle_level_irq, 2585 clr, 0, IRQ_GC_INIT_MASK_CACHE); 2586 if (ret) { 2587 dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n", 2588 bank->name); 2589 irq_domain_remove(bank->domain); 2590 clk_disable(bank->clk); 2591 continue; 2592 } 2593 2594 /* 2595 * Linux assumes that all interrupts start out disabled/masked. 2596 * Our driver only uses the concept of masked and always keeps 2597 * things enabled, so for us that's all masked and all enabled. 2598 */ 2599 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTMASK); 2600 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTEN); 2601 2602 gc = irq_get_domain_generic_chip(bank->domain, 0); 2603 gc->reg_base = bank->reg_base; 2604 gc->private = bank; 2605 gc->chip_types[0].regs.mask = GPIO_INTMASK; 2606 gc->chip_types[0].regs.ack = GPIO_PORTS_EOI; 2607 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit; 2608 gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit; 2609 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit; 2610 gc->chip_types[0].chip.irq_enable = rockchip_irq_enable; 2611 gc->chip_types[0].chip.irq_disable = rockchip_irq_disable; 2612 gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake; 2613 gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend; 2614 gc->chip_types[0].chip.irq_resume = rockchip_irq_resume; 2615 gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type; 2616 gc->wake_enabled = IRQ_MSK(bank->nr_pins); 2617 2618 irq_set_chained_handler_and_data(bank->irq, 2619 rockchip_irq_demux, bank); 2620 2621 /* map the gpio irqs here, when the clock is still running */ 2622 for (j = 0 ; j < 32 ; j++) 2623 irq_create_mapping(bank->domain, j); 2624 2625 clk_disable(bank->clk); 2626 } 2627 2628 return 0; 2629 } 2630 2631 static int rockchip_gpiolib_register(struct platform_device *pdev, 2632 struct rockchip_pinctrl *info) 2633 { 2634 struct rockchip_pin_ctrl *ctrl = info->ctrl; 2635 struct rockchip_pin_bank *bank = ctrl->pin_banks; 2636 struct gpio_chip *gc; 2637 int ret; 2638 int i; 2639 2640 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 2641 if (!bank->valid) { 2642 dev_warn(&pdev->dev, "bank %s is not valid\n", 2643 bank->name); 2644 continue; 2645 } 2646 2647 bank->gpio_chip = rockchip_gpiolib_chip; 2648 2649 gc = &bank->gpio_chip; 2650 gc->base = bank->pin_base; 2651 gc->ngpio = bank->nr_pins; 2652 gc->parent = &pdev->dev; 2653 gc->of_node = bank->of_node; 2654 gc->label = bank->name; 2655 2656 ret = gpiochip_add_data(gc, bank); 2657 if (ret) { 2658 dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n", 2659 gc->label, ret); 2660 goto fail; 2661 } 2662 } 2663 2664 rockchip_interrupts_register(pdev, info); 2665 2666 return 0; 2667 2668 fail: 2669 for (--i, --bank; i >= 0; --i, --bank) { 2670 if (!bank->valid) 2671 continue; 2672 gpiochip_remove(&bank->gpio_chip); 2673 } 2674 return ret; 2675 } 2676 2677 static int rockchip_gpiolib_unregister(struct platform_device *pdev, 2678 struct rockchip_pinctrl *info) 2679 { 2680 struct rockchip_pin_ctrl *ctrl = info->ctrl; 2681 struct rockchip_pin_bank *bank = ctrl->pin_banks; 2682 int i; 2683 2684 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 2685 if (!bank->valid) 2686 continue; 2687 gpiochip_remove(&bank->gpio_chip); 2688 } 2689 2690 return 0; 2691 } 2692 2693 static int rockchip_get_bank_data(struct rockchip_pin_bank *bank, 2694 struct rockchip_pinctrl *info) 2695 { 2696 struct resource res; 2697 void __iomem *base; 2698 2699 if (of_address_to_resource(bank->of_node, 0, &res)) { 2700 dev_err(info->dev, "cannot find IO resource for bank\n"); 2701 return -ENOENT; 2702 } 2703 2704 bank->reg_base = devm_ioremap_resource(info->dev, &res); 2705 if (IS_ERR(bank->reg_base)) 2706 return PTR_ERR(bank->reg_base); 2707 2708 /* 2709 * special case, where parts of the pull setting-registers are 2710 * part of the PMU register space 2711 */ 2712 if (of_device_is_compatible(bank->of_node, 2713 "rockchip,rk3188-gpio-bank0")) { 2714 struct device_node *node; 2715 2716 node = of_parse_phandle(bank->of_node->parent, 2717 "rockchip,pmu", 0); 2718 if (!node) { 2719 if (of_address_to_resource(bank->of_node, 1, &res)) { 2720 dev_err(info->dev, "cannot find IO resource for bank\n"); 2721 return -ENOENT; 2722 } 2723 2724 base = devm_ioremap_resource(info->dev, &res); 2725 if (IS_ERR(base)) 2726 return PTR_ERR(base); 2727 rockchip_regmap_config.max_register = 2728 resource_size(&res) - 4; 2729 rockchip_regmap_config.name = 2730 "rockchip,rk3188-gpio-bank0-pull"; 2731 bank->regmap_pull = devm_regmap_init_mmio(info->dev, 2732 base, 2733 &rockchip_regmap_config); 2734 } 2735 } 2736 2737 bank->irq = irq_of_parse_and_map(bank->of_node, 0); 2738 2739 bank->clk = of_clk_get(bank->of_node, 0); 2740 if (IS_ERR(bank->clk)) 2741 return PTR_ERR(bank->clk); 2742 2743 return clk_prepare(bank->clk); 2744 } 2745 2746 static const struct of_device_id rockchip_pinctrl_dt_match[]; 2747 2748 /* retrieve the soc specific data */ 2749 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data( 2750 struct rockchip_pinctrl *d, 2751 struct platform_device *pdev) 2752 { 2753 const struct of_device_id *match; 2754 struct device_node *node = pdev->dev.of_node; 2755 struct device_node *np; 2756 struct rockchip_pin_ctrl *ctrl; 2757 struct rockchip_pin_bank *bank; 2758 int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j; 2759 2760 match = of_match_node(rockchip_pinctrl_dt_match, node); 2761 ctrl = (struct rockchip_pin_ctrl *)match->data; 2762 2763 for_each_child_of_node(node, np) { 2764 if (!of_find_property(np, "gpio-controller", NULL)) 2765 continue; 2766 2767 bank = ctrl->pin_banks; 2768 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 2769 if (!strcmp(bank->name, np->name)) { 2770 bank->of_node = np; 2771 2772 if (!rockchip_get_bank_data(bank, d)) 2773 bank->valid = true; 2774 2775 break; 2776 } 2777 } 2778 } 2779 2780 grf_offs = ctrl->grf_mux_offset; 2781 pmu_offs = ctrl->pmu_mux_offset; 2782 drv_pmu_offs = ctrl->pmu_drv_offset; 2783 drv_grf_offs = ctrl->grf_drv_offset; 2784 bank = ctrl->pin_banks; 2785 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 2786 int bank_pins = 0; 2787 2788 raw_spin_lock_init(&bank->slock); 2789 bank->drvdata = d; 2790 bank->pin_base = ctrl->nr_pins; 2791 ctrl->nr_pins += bank->nr_pins; 2792 2793 /* calculate iomux and drv offsets */ 2794 for (j = 0; j < 4; j++) { 2795 struct rockchip_iomux *iom = &bank->iomux[j]; 2796 struct rockchip_drv *drv = &bank->drv[j]; 2797 int inc; 2798 2799 if (bank_pins >= bank->nr_pins) 2800 break; 2801 2802 /* preset iomux offset value, set new start value */ 2803 if (iom->offset >= 0) { 2804 if (iom->type & IOMUX_SOURCE_PMU) 2805 pmu_offs = iom->offset; 2806 else 2807 grf_offs = iom->offset; 2808 } else { /* set current iomux offset */ 2809 iom->offset = (iom->type & IOMUX_SOURCE_PMU) ? 2810 pmu_offs : grf_offs; 2811 } 2812 2813 /* preset drv offset value, set new start value */ 2814 if (drv->offset >= 0) { 2815 if (iom->type & IOMUX_SOURCE_PMU) 2816 drv_pmu_offs = drv->offset; 2817 else 2818 drv_grf_offs = drv->offset; 2819 } else { /* set current drv offset */ 2820 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ? 2821 drv_pmu_offs : drv_grf_offs; 2822 } 2823 2824 dev_dbg(d->dev, "bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n", 2825 i, j, iom->offset, drv->offset); 2826 2827 /* 2828 * Increase offset according to iomux width. 2829 * 4bit iomux'es are spread over two registers. 2830 */ 2831 inc = (iom->type & (IOMUX_WIDTH_4BIT | 2832 IOMUX_WIDTH_3BIT)) ? 8 : 4; 2833 if (iom->type & IOMUX_SOURCE_PMU) 2834 pmu_offs += inc; 2835 else 2836 grf_offs += inc; 2837 2838 /* 2839 * Increase offset according to drv width. 2840 * 3bit drive-strenth'es are spread over two registers. 2841 */ 2842 if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) || 2843 (drv->drv_type == DRV_TYPE_IO_3V3_ONLY)) 2844 inc = 8; 2845 else 2846 inc = 4; 2847 2848 if (iom->type & IOMUX_SOURCE_PMU) 2849 drv_pmu_offs += inc; 2850 else 2851 drv_grf_offs += inc; 2852 2853 bank_pins += 8; 2854 } 2855 2856 /* calculate the per-bank route_mask */ 2857 for (j = 0; j < ctrl->niomux_routes; j++) { 2858 int pin = 0; 2859 2860 if (ctrl->iomux_routes[j].bank_num == bank->bank_num) { 2861 pin = ctrl->iomux_routes[j].pin; 2862 bank->route_mask |= BIT(pin); 2863 } 2864 } 2865 } 2866 2867 return ctrl; 2868 } 2869 2870 #define RK3288_GRF_GPIO6C_IOMUX 0x64 2871 #define GPIO6C6_SEL_WRITE_ENABLE BIT(28) 2872 2873 static u32 rk3288_grf_gpio6c_iomux; 2874 2875 static int __maybe_unused rockchip_pinctrl_suspend(struct device *dev) 2876 { 2877 struct rockchip_pinctrl *info = dev_get_drvdata(dev); 2878 int ret = pinctrl_force_sleep(info->pctl_dev); 2879 2880 if (ret) 2881 return ret; 2882 2883 /* 2884 * RK3288 GPIO6_C6 mux would be modified by Maskrom when resume, so save 2885 * the setting here, and restore it at resume. 2886 */ 2887 if (info->ctrl->type == RK3288) { 2888 ret = regmap_read(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX, 2889 &rk3288_grf_gpio6c_iomux); 2890 if (ret) { 2891 pinctrl_force_default(info->pctl_dev); 2892 return ret; 2893 } 2894 } 2895 2896 return 0; 2897 } 2898 2899 static int __maybe_unused rockchip_pinctrl_resume(struct device *dev) 2900 { 2901 struct rockchip_pinctrl *info = dev_get_drvdata(dev); 2902 int ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX, 2903 rk3288_grf_gpio6c_iomux | 2904 GPIO6C6_SEL_WRITE_ENABLE); 2905 2906 if (ret) 2907 return ret; 2908 2909 return pinctrl_force_default(info->pctl_dev); 2910 } 2911 2912 static SIMPLE_DEV_PM_OPS(rockchip_pinctrl_dev_pm_ops, rockchip_pinctrl_suspend, 2913 rockchip_pinctrl_resume); 2914 2915 static int rockchip_pinctrl_probe(struct platform_device *pdev) 2916 { 2917 struct rockchip_pinctrl *info; 2918 struct device *dev = &pdev->dev; 2919 struct rockchip_pin_ctrl *ctrl; 2920 struct device_node *np = pdev->dev.of_node, *node; 2921 struct resource *res; 2922 void __iomem *base; 2923 int ret; 2924 2925 if (!dev->of_node) { 2926 dev_err(dev, "device tree node not found\n"); 2927 return -ENODEV; 2928 } 2929 2930 info = devm_kzalloc(dev, sizeof(struct rockchip_pinctrl), GFP_KERNEL); 2931 if (!info) 2932 return -ENOMEM; 2933 2934 info->dev = dev; 2935 2936 ctrl = rockchip_pinctrl_get_soc_data(info, pdev); 2937 if (!ctrl) { 2938 dev_err(dev, "driver data not available\n"); 2939 return -EINVAL; 2940 } 2941 info->ctrl = ctrl; 2942 2943 node = of_parse_phandle(np, "rockchip,grf", 0); 2944 if (node) { 2945 info->regmap_base = syscon_node_to_regmap(node); 2946 if (IS_ERR(info->regmap_base)) 2947 return PTR_ERR(info->regmap_base); 2948 } else { 2949 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2950 base = devm_ioremap_resource(&pdev->dev, res); 2951 if (IS_ERR(base)) 2952 return PTR_ERR(base); 2953 2954 rockchip_regmap_config.max_register = resource_size(res) - 4; 2955 rockchip_regmap_config.name = "rockchip,pinctrl"; 2956 info->regmap_base = devm_regmap_init_mmio(&pdev->dev, base, 2957 &rockchip_regmap_config); 2958 2959 /* to check for the old dt-bindings */ 2960 info->reg_size = resource_size(res); 2961 2962 /* Honor the old binding, with pull registers as 2nd resource */ 2963 if (ctrl->type == RK3188 && info->reg_size < 0x200) { 2964 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 2965 base = devm_ioremap_resource(&pdev->dev, res); 2966 if (IS_ERR(base)) 2967 return PTR_ERR(base); 2968 2969 rockchip_regmap_config.max_register = 2970 resource_size(res) - 4; 2971 rockchip_regmap_config.name = "rockchip,pinctrl-pull"; 2972 info->regmap_pull = devm_regmap_init_mmio(&pdev->dev, 2973 base, 2974 &rockchip_regmap_config); 2975 } 2976 } 2977 2978 /* try to find the optional reference to the pmu syscon */ 2979 node = of_parse_phandle(np, "rockchip,pmu", 0); 2980 if (node) { 2981 info->regmap_pmu = syscon_node_to_regmap(node); 2982 if (IS_ERR(info->regmap_pmu)) 2983 return PTR_ERR(info->regmap_pmu); 2984 } 2985 2986 ret = rockchip_gpiolib_register(pdev, info); 2987 if (ret) 2988 return ret; 2989 2990 ret = rockchip_pinctrl_register(pdev, info); 2991 if (ret) { 2992 rockchip_gpiolib_unregister(pdev, info); 2993 return ret; 2994 } 2995 2996 platform_set_drvdata(pdev, info); 2997 2998 return 0; 2999 } 3000 3001 static struct rockchip_pin_bank rv1108_pin_banks[] = { 3002 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, 3003 IOMUX_SOURCE_PMU, 3004 IOMUX_SOURCE_PMU, 3005 IOMUX_SOURCE_PMU), 3006 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0), 3007 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0), 3008 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0), 3009 }; 3010 3011 static struct rockchip_pin_ctrl rv1108_pin_ctrl = { 3012 .pin_banks = rv1108_pin_banks, 3013 .nr_banks = ARRAY_SIZE(rv1108_pin_banks), 3014 .label = "RV1108-GPIO", 3015 .type = RV1108, 3016 .grf_mux_offset = 0x10, 3017 .pmu_mux_offset = 0x0, 3018 .pull_calc_reg = rv1108_calc_pull_reg_and_bit, 3019 .drv_calc_reg = rv1108_calc_drv_reg_and_bit, 3020 }; 3021 3022 static struct rockchip_pin_bank rk2928_pin_banks[] = { 3023 PIN_BANK(0, 32, "gpio0"), 3024 PIN_BANK(1, 32, "gpio1"), 3025 PIN_BANK(2, 32, "gpio2"), 3026 PIN_BANK(3, 32, "gpio3"), 3027 }; 3028 3029 static struct rockchip_pin_ctrl rk2928_pin_ctrl = { 3030 .pin_banks = rk2928_pin_banks, 3031 .nr_banks = ARRAY_SIZE(rk2928_pin_banks), 3032 .label = "RK2928-GPIO", 3033 .type = RK2928, 3034 .grf_mux_offset = 0xa8, 3035 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 3036 }; 3037 3038 static struct rockchip_pin_bank rk3036_pin_banks[] = { 3039 PIN_BANK(0, 32, "gpio0"), 3040 PIN_BANK(1, 32, "gpio1"), 3041 PIN_BANK(2, 32, "gpio2"), 3042 }; 3043 3044 static struct rockchip_pin_ctrl rk3036_pin_ctrl = { 3045 .pin_banks = rk3036_pin_banks, 3046 .nr_banks = ARRAY_SIZE(rk3036_pin_banks), 3047 .label = "RK3036-GPIO", 3048 .type = RK2928, 3049 .grf_mux_offset = 0xa8, 3050 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 3051 }; 3052 3053 static struct rockchip_pin_bank rk3066a_pin_banks[] = { 3054 PIN_BANK(0, 32, "gpio0"), 3055 PIN_BANK(1, 32, "gpio1"), 3056 PIN_BANK(2, 32, "gpio2"), 3057 PIN_BANK(3, 32, "gpio3"), 3058 PIN_BANK(4, 32, "gpio4"), 3059 PIN_BANK(6, 16, "gpio6"), 3060 }; 3061 3062 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = { 3063 .pin_banks = rk3066a_pin_banks, 3064 .nr_banks = ARRAY_SIZE(rk3066a_pin_banks), 3065 .label = "RK3066a-GPIO", 3066 .type = RK2928, 3067 .grf_mux_offset = 0xa8, 3068 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 3069 }; 3070 3071 static struct rockchip_pin_bank rk3066b_pin_banks[] = { 3072 PIN_BANK(0, 32, "gpio0"), 3073 PIN_BANK(1, 32, "gpio1"), 3074 PIN_BANK(2, 32, "gpio2"), 3075 PIN_BANK(3, 32, "gpio3"), 3076 }; 3077 3078 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = { 3079 .pin_banks = rk3066b_pin_banks, 3080 .nr_banks = ARRAY_SIZE(rk3066b_pin_banks), 3081 .label = "RK3066b-GPIO", 3082 .type = RK3066B, 3083 .grf_mux_offset = 0x60, 3084 }; 3085 3086 static struct rockchip_pin_bank rk3188_pin_banks[] = { 3087 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0), 3088 PIN_BANK(1, 32, "gpio1"), 3089 PIN_BANK(2, 32, "gpio2"), 3090 PIN_BANK(3, 32, "gpio3"), 3091 }; 3092 3093 static struct rockchip_pin_ctrl rk3188_pin_ctrl = { 3094 .pin_banks = rk3188_pin_banks, 3095 .nr_banks = ARRAY_SIZE(rk3188_pin_banks), 3096 .label = "RK3188-GPIO", 3097 .type = RK3188, 3098 .grf_mux_offset = 0x60, 3099 .pull_calc_reg = rk3188_calc_pull_reg_and_bit, 3100 }; 3101 3102 static struct rockchip_pin_bank rk3228_pin_banks[] = { 3103 PIN_BANK(0, 32, "gpio0"), 3104 PIN_BANK(1, 32, "gpio1"), 3105 PIN_BANK(2, 32, "gpio2"), 3106 PIN_BANK(3, 32, "gpio3"), 3107 }; 3108 3109 static struct rockchip_pin_ctrl rk3228_pin_ctrl = { 3110 .pin_banks = rk3228_pin_banks, 3111 .nr_banks = ARRAY_SIZE(rk3228_pin_banks), 3112 .label = "RK3228-GPIO", 3113 .type = RK3288, 3114 .grf_mux_offset = 0x0, 3115 .iomux_routes = rk3228_mux_route_data, 3116 .niomux_routes = ARRAY_SIZE(rk3228_mux_route_data), 3117 .pull_calc_reg = rk3228_calc_pull_reg_and_bit, 3118 .drv_calc_reg = rk3228_calc_drv_reg_and_bit, 3119 }; 3120 3121 static struct rockchip_pin_bank rk3288_pin_banks[] = { 3122 PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU, 3123 IOMUX_SOURCE_PMU, 3124 IOMUX_SOURCE_PMU, 3125 IOMUX_UNROUTED 3126 ), 3127 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED, 3128 IOMUX_UNROUTED, 3129 IOMUX_UNROUTED, 3130 0 3131 ), 3132 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED), 3133 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT), 3134 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT, 3135 IOMUX_WIDTH_4BIT, 3136 0, 3137 0 3138 ), 3139 PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED, 3140 0, 3141 0, 3142 IOMUX_UNROUTED 3143 ), 3144 PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED), 3145 PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0, 3146 0, 3147 IOMUX_WIDTH_4BIT, 3148 IOMUX_UNROUTED 3149 ), 3150 PIN_BANK(8, 16, "gpio8"), 3151 }; 3152 3153 static struct rockchip_pin_ctrl rk3288_pin_ctrl = { 3154 .pin_banks = rk3288_pin_banks, 3155 .nr_banks = ARRAY_SIZE(rk3288_pin_banks), 3156 .label = "RK3288-GPIO", 3157 .type = RK3288, 3158 .grf_mux_offset = 0x0, 3159 .pmu_mux_offset = 0x84, 3160 .pull_calc_reg = rk3288_calc_pull_reg_and_bit, 3161 .drv_calc_reg = rk3288_calc_drv_reg_and_bit, 3162 }; 3163 3164 static struct rockchip_pin_bank rk3328_pin_banks[] = { 3165 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0), 3166 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0), 3167 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 3168 IOMUX_WIDTH_3BIT | IOMUX_RECALCED, 3169 IOMUX_WIDTH_3BIT | IOMUX_RECALCED, 3170 0), 3171 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 3172 IOMUX_WIDTH_3BIT, 3173 IOMUX_WIDTH_3BIT | IOMUX_RECALCED, 3174 0, 3175 0), 3176 }; 3177 3178 static struct rockchip_pin_ctrl rk3328_pin_ctrl = { 3179 .pin_banks = rk3328_pin_banks, 3180 .nr_banks = ARRAY_SIZE(rk3328_pin_banks), 3181 .label = "RK3328-GPIO", 3182 .type = RK3288, 3183 .grf_mux_offset = 0x0, 3184 .iomux_routes = rk3328_mux_route_data, 3185 .niomux_routes = ARRAY_SIZE(rk3328_mux_route_data), 3186 .pull_calc_reg = rk3228_calc_pull_reg_and_bit, 3187 .drv_calc_reg = rk3228_calc_drv_reg_and_bit, 3188 .iomux_recalc = rk3328_recalc_mux, 3189 .schmitt_calc_reg = rk3328_calc_schmitt_reg_and_bit, 3190 }; 3191 3192 static struct rockchip_pin_bank rk3368_pin_banks[] = { 3193 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, 3194 IOMUX_SOURCE_PMU, 3195 IOMUX_SOURCE_PMU, 3196 IOMUX_SOURCE_PMU 3197 ), 3198 PIN_BANK(1, 32, "gpio1"), 3199 PIN_BANK(2, 32, "gpio2"), 3200 PIN_BANK(3, 32, "gpio3"), 3201 }; 3202 3203 static struct rockchip_pin_ctrl rk3368_pin_ctrl = { 3204 .pin_banks = rk3368_pin_banks, 3205 .nr_banks = ARRAY_SIZE(rk3368_pin_banks), 3206 .label = "RK3368-GPIO", 3207 .type = RK3368, 3208 .grf_mux_offset = 0x0, 3209 .pmu_mux_offset = 0x0, 3210 .pull_calc_reg = rk3368_calc_pull_reg_and_bit, 3211 .drv_calc_reg = rk3368_calc_drv_reg_and_bit, 3212 }; 3213 3214 static struct rockchip_pin_bank rk3399_pin_banks[] = { 3215 PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0", 3216 IOMUX_SOURCE_PMU, 3217 IOMUX_SOURCE_PMU, 3218 IOMUX_SOURCE_PMU, 3219 IOMUX_SOURCE_PMU, 3220 DRV_TYPE_IO_1V8_ONLY, 3221 DRV_TYPE_IO_1V8_ONLY, 3222 DRV_TYPE_IO_DEFAULT, 3223 DRV_TYPE_IO_DEFAULT, 3224 0x0, 3225 0x8, 3226 -1, 3227 -1, 3228 PULL_TYPE_IO_1V8_ONLY, 3229 PULL_TYPE_IO_1V8_ONLY, 3230 PULL_TYPE_IO_DEFAULT, 3231 PULL_TYPE_IO_DEFAULT 3232 ), 3233 PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU, 3234 IOMUX_SOURCE_PMU, 3235 IOMUX_SOURCE_PMU, 3236 IOMUX_SOURCE_PMU, 3237 DRV_TYPE_IO_1V8_OR_3V0, 3238 DRV_TYPE_IO_1V8_OR_3V0, 3239 DRV_TYPE_IO_1V8_OR_3V0, 3240 DRV_TYPE_IO_1V8_OR_3V0, 3241 0x20, 3242 0x28, 3243 0x30, 3244 0x38 3245 ), 3246 PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0, 3247 DRV_TYPE_IO_1V8_OR_3V0, 3248 DRV_TYPE_IO_1V8_ONLY, 3249 DRV_TYPE_IO_1V8_ONLY, 3250 PULL_TYPE_IO_DEFAULT, 3251 PULL_TYPE_IO_DEFAULT, 3252 PULL_TYPE_IO_1V8_ONLY, 3253 PULL_TYPE_IO_1V8_ONLY 3254 ), 3255 PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY, 3256 DRV_TYPE_IO_3V3_ONLY, 3257 DRV_TYPE_IO_3V3_ONLY, 3258 DRV_TYPE_IO_1V8_OR_3V0 3259 ), 3260 PIN_BANK_DRV_FLAGS(4, 32, "gpio4", DRV_TYPE_IO_1V8_OR_3V0, 3261 DRV_TYPE_IO_1V8_3V0_AUTO, 3262 DRV_TYPE_IO_1V8_OR_3V0, 3263 DRV_TYPE_IO_1V8_OR_3V0 3264 ), 3265 }; 3266 3267 static struct rockchip_pin_ctrl rk3399_pin_ctrl = { 3268 .pin_banks = rk3399_pin_banks, 3269 .nr_banks = ARRAY_SIZE(rk3399_pin_banks), 3270 .label = "RK3399-GPIO", 3271 .type = RK3399, 3272 .grf_mux_offset = 0xe000, 3273 .pmu_mux_offset = 0x0, 3274 .grf_drv_offset = 0xe100, 3275 .pmu_drv_offset = 0x80, 3276 .iomux_routes = rk3399_mux_route_data, 3277 .niomux_routes = ARRAY_SIZE(rk3399_mux_route_data), 3278 .pull_calc_reg = rk3399_calc_pull_reg_and_bit, 3279 .drv_calc_reg = rk3399_calc_drv_reg_and_bit, 3280 }; 3281 3282 static const struct of_device_id rockchip_pinctrl_dt_match[] = { 3283 { .compatible = "rockchip,rv1108-pinctrl", 3284 .data = &rv1108_pin_ctrl }, 3285 { .compatible = "rockchip,rk2928-pinctrl", 3286 .data = &rk2928_pin_ctrl }, 3287 { .compatible = "rockchip,rk3036-pinctrl", 3288 .data = &rk3036_pin_ctrl }, 3289 { .compatible = "rockchip,rk3066a-pinctrl", 3290 .data = &rk3066a_pin_ctrl }, 3291 { .compatible = "rockchip,rk3066b-pinctrl", 3292 .data = &rk3066b_pin_ctrl }, 3293 { .compatible = "rockchip,rk3188-pinctrl", 3294 .data = &rk3188_pin_ctrl }, 3295 { .compatible = "rockchip,rk3228-pinctrl", 3296 .data = &rk3228_pin_ctrl }, 3297 { .compatible = "rockchip,rk3288-pinctrl", 3298 .data = &rk3288_pin_ctrl }, 3299 { .compatible = "rockchip,rk3328-pinctrl", 3300 .data = &rk3328_pin_ctrl }, 3301 { .compatible = "rockchip,rk3368-pinctrl", 3302 .data = &rk3368_pin_ctrl }, 3303 { .compatible = "rockchip,rk3399-pinctrl", 3304 .data = &rk3399_pin_ctrl }, 3305 {}, 3306 }; 3307 3308 static struct platform_driver rockchip_pinctrl_driver = { 3309 .probe = rockchip_pinctrl_probe, 3310 .driver = { 3311 .name = "rockchip-pinctrl", 3312 .pm = &rockchip_pinctrl_dev_pm_ops, 3313 .of_match_table = rockchip_pinctrl_dt_match, 3314 }, 3315 }; 3316 3317 static int __init rockchip_pinctrl_drv_register(void) 3318 { 3319 return platform_driver_register(&rockchip_pinctrl_driver); 3320 } 3321 postcore_initcall(rockchip_pinctrl_drv_register); 3322