1 /* 2 * Pinctrl driver for Rockchip SoCs 3 * 4 * Copyright (c) 2013 MundoReader S.L. 5 * Author: Heiko Stuebner <heiko@sntech.de> 6 * 7 * With some ideas taken from pinctrl-samsung: 8 * Copyright (c) 2012 Samsung Electronics Co., Ltd. 9 * http://www.samsung.com 10 * Copyright (c) 2012 Linaro Ltd 11 * http://www.linaro.org 12 * 13 * and pinctrl-at91: 14 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> 15 * 16 * This program is free software; you can redistribute it and/or modify 17 * it under the terms of the GNU General Public License version 2 as published 18 * by the Free Software Foundation. 19 * 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 */ 25 26 #include <linux/module.h> 27 #include <linux/platform_device.h> 28 #include <linux/io.h> 29 #include <linux/bitops.h> 30 #include <linux/gpio.h> 31 #include <linux/of_address.h> 32 #include <linux/of_irq.h> 33 #include <linux/pinctrl/machine.h> 34 #include <linux/pinctrl/pinconf.h> 35 #include <linux/pinctrl/pinctrl.h> 36 #include <linux/pinctrl/pinmux.h> 37 #include <linux/pinctrl/pinconf-generic.h> 38 #include <linux/irqchip/chained_irq.h> 39 #include <linux/clk.h> 40 #include <linux/regmap.h> 41 #include <linux/mfd/syscon.h> 42 #include <dt-bindings/pinctrl/rockchip.h> 43 44 #include "core.h" 45 #include "pinconf.h" 46 47 /* GPIO control registers */ 48 #define GPIO_SWPORT_DR 0x00 49 #define GPIO_SWPORT_DDR 0x04 50 #define GPIO_INTEN 0x30 51 #define GPIO_INTMASK 0x34 52 #define GPIO_INTTYPE_LEVEL 0x38 53 #define GPIO_INT_POLARITY 0x3c 54 #define GPIO_INT_STATUS 0x40 55 #define GPIO_INT_RAWSTATUS 0x44 56 #define GPIO_DEBOUNCE 0x48 57 #define GPIO_PORTS_EOI 0x4c 58 #define GPIO_EXT_PORT 0x50 59 #define GPIO_LS_SYNC 0x60 60 61 enum rockchip_pinctrl_type { 62 RK2928, 63 RK3066B, 64 RK3188, 65 RK3288, 66 RK3368, 67 RK3399, 68 }; 69 70 /** 71 * Encode variants of iomux registers into a type variable 72 */ 73 #define IOMUX_GPIO_ONLY BIT(0) 74 #define IOMUX_WIDTH_4BIT BIT(1) 75 #define IOMUX_SOURCE_PMU BIT(2) 76 #define IOMUX_UNROUTED BIT(3) 77 78 /** 79 * @type: iomux variant using IOMUX_* constants 80 * @offset: if initialized to -1 it will be autocalculated, by specifying 81 * an initial offset value the relevant source offset can be reset 82 * to a new value for autocalculating the following iomux registers. 83 */ 84 struct rockchip_iomux { 85 int type; 86 int offset; 87 }; 88 89 /** 90 * enum type index corresponding to rockchip_perpin_drv_list arrays index. 91 */ 92 enum rockchip_pin_drv_type { 93 DRV_TYPE_IO_DEFAULT = 0, 94 DRV_TYPE_IO_1V8_OR_3V0, 95 DRV_TYPE_IO_1V8_ONLY, 96 DRV_TYPE_IO_1V8_3V0_AUTO, 97 DRV_TYPE_IO_3V3_ONLY, 98 DRV_TYPE_MAX 99 }; 100 101 /** 102 * @drv_type: drive strength variant using rockchip_perpin_drv_type 103 * @offset: if initialized to -1 it will be autocalculated, by specifying 104 * an initial offset value the relevant source offset can be reset 105 * to a new value for autocalculating the following drive strength 106 * registers. if used chips own cal_drv func instead to calculate 107 * registers offset, the variant could be ignored. 108 */ 109 struct rockchip_drv { 110 enum rockchip_pin_drv_type drv_type; 111 int offset; 112 }; 113 114 /** 115 * @reg_base: register base of the gpio bank 116 * @reg_pull: optional separate register for additional pull settings 117 * @clk: clock of the gpio bank 118 * @irq: interrupt of the gpio bank 119 * @saved_masks: Saved content of GPIO_INTEN at suspend time. 120 * @pin_base: first pin number 121 * @nr_pins: number of pins in this bank 122 * @name: name of the bank 123 * @bank_num: number of the bank, to account for holes 124 * @iomux: array describing the 4 iomux sources of the bank 125 * @drv: array describing the 4 drive strength sources of the bank 126 * @valid: are all necessary informations present 127 * @of_node: dt node of this bank 128 * @drvdata: common pinctrl basedata 129 * @domain: irqdomain of the gpio bank 130 * @gpio_chip: gpiolib chip 131 * @grange: gpio range 132 * @slock: spinlock for the gpio bank 133 */ 134 struct rockchip_pin_bank { 135 void __iomem *reg_base; 136 struct regmap *regmap_pull; 137 struct clk *clk; 138 int irq; 139 u32 saved_masks; 140 u32 pin_base; 141 u8 nr_pins; 142 char *name; 143 u8 bank_num; 144 struct rockchip_iomux iomux[4]; 145 struct rockchip_drv drv[4]; 146 bool valid; 147 struct device_node *of_node; 148 struct rockchip_pinctrl *drvdata; 149 struct irq_domain *domain; 150 struct gpio_chip gpio_chip; 151 struct pinctrl_gpio_range grange; 152 spinlock_t slock; 153 u32 toggle_edge_mode; 154 }; 155 156 #define PIN_BANK(id, pins, label) \ 157 { \ 158 .bank_num = id, \ 159 .nr_pins = pins, \ 160 .name = label, \ 161 .iomux = { \ 162 { .offset = -1 }, \ 163 { .offset = -1 }, \ 164 { .offset = -1 }, \ 165 { .offset = -1 }, \ 166 }, \ 167 } 168 169 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \ 170 { \ 171 .bank_num = id, \ 172 .nr_pins = pins, \ 173 .name = label, \ 174 .iomux = { \ 175 { .type = iom0, .offset = -1 }, \ 176 { .type = iom1, .offset = -1 }, \ 177 { .type = iom2, .offset = -1 }, \ 178 { .type = iom3, .offset = -1 }, \ 179 }, \ 180 } 181 182 #define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \ 183 { \ 184 .bank_num = id, \ 185 .nr_pins = pins, \ 186 .name = label, \ 187 .iomux = { \ 188 { .offset = -1 }, \ 189 { .offset = -1 }, \ 190 { .offset = -1 }, \ 191 { .offset = -1 }, \ 192 }, \ 193 .drv = { \ 194 { .drv_type = type0, .offset = -1 }, \ 195 { .drv_type = type1, .offset = -1 }, \ 196 { .drv_type = type2, .offset = -1 }, \ 197 { .drv_type = type3, .offset = -1 }, \ 198 }, \ 199 } 200 201 #define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1, \ 202 iom2, iom3, drv0, drv1, drv2, \ 203 drv3, offset0, offset1, \ 204 offset2, offset3) \ 205 { \ 206 .bank_num = id, \ 207 .nr_pins = pins, \ 208 .name = label, \ 209 .iomux = { \ 210 { .type = iom0, .offset = -1 }, \ 211 { .type = iom1, .offset = -1 }, \ 212 { .type = iom2, .offset = -1 }, \ 213 { .type = iom3, .offset = -1 }, \ 214 }, \ 215 .drv = { \ 216 { .drv_type = drv0, .offset = offset0 }, \ 217 { .drv_type = drv1, .offset = offset1 }, \ 218 { .drv_type = drv2, .offset = offset2 }, \ 219 { .drv_type = drv3, .offset = offset3 }, \ 220 }, \ 221 } 222 223 /** 224 */ 225 struct rockchip_pin_ctrl { 226 struct rockchip_pin_bank *pin_banks; 227 u32 nr_banks; 228 u32 nr_pins; 229 char *label; 230 enum rockchip_pinctrl_type type; 231 int grf_mux_offset; 232 int pmu_mux_offset; 233 int grf_drv_offset; 234 int pmu_drv_offset; 235 236 void (*pull_calc_reg)(struct rockchip_pin_bank *bank, 237 int pin_num, struct regmap **regmap, 238 int *reg, u8 *bit); 239 void (*drv_calc_reg)(struct rockchip_pin_bank *bank, 240 int pin_num, struct regmap **regmap, 241 int *reg, u8 *bit); 242 }; 243 244 struct rockchip_pin_config { 245 unsigned int func; 246 unsigned long *configs; 247 unsigned int nconfigs; 248 }; 249 250 /** 251 * struct rockchip_pin_group: represent group of pins of a pinmux function. 252 * @name: name of the pin group, used to lookup the group. 253 * @pins: the pins included in this group. 254 * @npins: number of pins included in this group. 255 * @func: the mux function number to be programmed when selected. 256 * @configs: the config values to be set for each pin 257 * @nconfigs: number of configs for each pin 258 */ 259 struct rockchip_pin_group { 260 const char *name; 261 unsigned int npins; 262 unsigned int *pins; 263 struct rockchip_pin_config *data; 264 }; 265 266 /** 267 * struct rockchip_pmx_func: represent a pin function. 268 * @name: name of the pin function, used to lookup the function. 269 * @groups: one or more names of pin groups that provide this function. 270 * @num_groups: number of groups included in @groups. 271 */ 272 struct rockchip_pmx_func { 273 const char *name; 274 const char **groups; 275 u8 ngroups; 276 }; 277 278 struct rockchip_pinctrl { 279 struct regmap *regmap_base; 280 int reg_size; 281 struct regmap *regmap_pull; 282 struct regmap *regmap_pmu; 283 struct device *dev; 284 struct rockchip_pin_ctrl *ctrl; 285 struct pinctrl_desc pctl; 286 struct pinctrl_dev *pctl_dev; 287 struct rockchip_pin_group *groups; 288 unsigned int ngroups; 289 struct rockchip_pmx_func *functions; 290 unsigned int nfunctions; 291 }; 292 293 static struct regmap_config rockchip_regmap_config = { 294 .reg_bits = 32, 295 .val_bits = 32, 296 .reg_stride = 4, 297 }; 298 299 static const inline struct rockchip_pin_group *pinctrl_name_to_group( 300 const struct rockchip_pinctrl *info, 301 const char *name) 302 { 303 int i; 304 305 for (i = 0; i < info->ngroups; i++) { 306 if (!strcmp(info->groups[i].name, name)) 307 return &info->groups[i]; 308 } 309 310 return NULL; 311 } 312 313 /* 314 * given a pin number that is local to a pin controller, find out the pin bank 315 * and the register base of the pin bank. 316 */ 317 static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info, 318 unsigned pin) 319 { 320 struct rockchip_pin_bank *b = info->ctrl->pin_banks; 321 322 while (pin >= (b->pin_base + b->nr_pins)) 323 b++; 324 325 return b; 326 } 327 328 static struct rockchip_pin_bank *bank_num_to_bank( 329 struct rockchip_pinctrl *info, 330 unsigned num) 331 { 332 struct rockchip_pin_bank *b = info->ctrl->pin_banks; 333 int i; 334 335 for (i = 0; i < info->ctrl->nr_banks; i++, b++) { 336 if (b->bank_num == num) 337 return b; 338 } 339 340 return ERR_PTR(-EINVAL); 341 } 342 343 /* 344 * Pinctrl_ops handling 345 */ 346 347 static int rockchip_get_groups_count(struct pinctrl_dev *pctldev) 348 { 349 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 350 351 return info->ngroups; 352 } 353 354 static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev, 355 unsigned selector) 356 { 357 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 358 359 return info->groups[selector].name; 360 } 361 362 static int rockchip_get_group_pins(struct pinctrl_dev *pctldev, 363 unsigned selector, const unsigned **pins, 364 unsigned *npins) 365 { 366 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 367 368 if (selector >= info->ngroups) 369 return -EINVAL; 370 371 *pins = info->groups[selector].pins; 372 *npins = info->groups[selector].npins; 373 374 return 0; 375 } 376 377 static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev, 378 struct device_node *np, 379 struct pinctrl_map **map, unsigned *num_maps) 380 { 381 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 382 const struct rockchip_pin_group *grp; 383 struct pinctrl_map *new_map; 384 struct device_node *parent; 385 int map_num = 1; 386 int i; 387 388 /* 389 * first find the group of this node and check if we need to create 390 * config maps for pins 391 */ 392 grp = pinctrl_name_to_group(info, np->name); 393 if (!grp) { 394 dev_err(info->dev, "unable to find group for node %s\n", 395 np->name); 396 return -EINVAL; 397 } 398 399 map_num += grp->npins; 400 new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num, 401 GFP_KERNEL); 402 if (!new_map) 403 return -ENOMEM; 404 405 *map = new_map; 406 *num_maps = map_num; 407 408 /* create mux map */ 409 parent = of_get_parent(np); 410 if (!parent) { 411 devm_kfree(pctldev->dev, new_map); 412 return -EINVAL; 413 } 414 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP; 415 new_map[0].data.mux.function = parent->name; 416 new_map[0].data.mux.group = np->name; 417 of_node_put(parent); 418 419 /* create config map */ 420 new_map++; 421 for (i = 0; i < grp->npins; i++) { 422 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN; 423 new_map[i].data.configs.group_or_pin = 424 pin_get_name(pctldev, grp->pins[i]); 425 new_map[i].data.configs.configs = grp->data[i].configs; 426 new_map[i].data.configs.num_configs = grp->data[i].nconfigs; 427 } 428 429 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n", 430 (*map)->data.mux.function, (*map)->data.mux.group, map_num); 431 432 return 0; 433 } 434 435 static void rockchip_dt_free_map(struct pinctrl_dev *pctldev, 436 struct pinctrl_map *map, unsigned num_maps) 437 { 438 } 439 440 static const struct pinctrl_ops rockchip_pctrl_ops = { 441 .get_groups_count = rockchip_get_groups_count, 442 .get_group_name = rockchip_get_group_name, 443 .get_group_pins = rockchip_get_group_pins, 444 .dt_node_to_map = rockchip_dt_node_to_map, 445 .dt_free_map = rockchip_dt_free_map, 446 }; 447 448 /* 449 * Hardware access 450 */ 451 452 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) 453 { 454 struct rockchip_pinctrl *info = bank->drvdata; 455 int iomux_num = (pin / 8); 456 struct regmap *regmap; 457 unsigned int val; 458 int reg, ret, mask; 459 u8 bit; 460 461 if (iomux_num > 3) 462 return -EINVAL; 463 464 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { 465 dev_err(info->dev, "pin %d is unrouted\n", pin); 466 return -EINVAL; 467 } 468 469 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) 470 return RK_FUNC_GPIO; 471 472 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) 473 ? info->regmap_pmu : info->regmap_base; 474 475 /* get basic quadrupel of mux registers and the correct reg inside */ 476 mask = (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) ? 0xf : 0x3; 477 reg = bank->iomux[iomux_num].offset; 478 if (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) { 479 if ((pin % 8) >= 4) 480 reg += 0x4; 481 bit = (pin % 4) * 4; 482 } else { 483 bit = (pin % 8) * 2; 484 } 485 486 ret = regmap_read(regmap, reg, &val); 487 if (ret) 488 return ret; 489 490 return ((val >> bit) & mask); 491 } 492 493 /* 494 * Set a new mux function for a pin. 495 * 496 * The register is divided into the upper and lower 16 bit. When changing 497 * a value, the previous register value is not read and changed. Instead 498 * it seems the changed bits are marked in the upper 16 bit, while the 499 * changed value gets set in the same offset in the lower 16 bit. 500 * All pin settings seem to be 2 bit wide in both the upper and lower 501 * parts. 502 * @bank: pin bank to change 503 * @pin: pin to change 504 * @mux: new mux function to set 505 */ 506 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) 507 { 508 struct rockchip_pinctrl *info = bank->drvdata; 509 int iomux_num = (pin / 8); 510 struct regmap *regmap; 511 int reg, ret, mask; 512 unsigned long flags; 513 u8 bit; 514 u32 data, rmask; 515 516 if (iomux_num > 3) 517 return -EINVAL; 518 519 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { 520 dev_err(info->dev, "pin %d is unrouted\n", pin); 521 return -EINVAL; 522 } 523 524 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) { 525 if (mux != RK_FUNC_GPIO) { 526 dev_err(info->dev, 527 "pin %d only supports a gpio mux\n", pin); 528 return -ENOTSUPP; 529 } else { 530 return 0; 531 } 532 } 533 534 dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n", 535 bank->bank_num, pin, mux); 536 537 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) 538 ? info->regmap_pmu : info->regmap_base; 539 540 /* get basic quadrupel of mux registers and the correct reg inside */ 541 mask = (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) ? 0xf : 0x3; 542 reg = bank->iomux[iomux_num].offset; 543 if (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) { 544 if ((pin % 8) >= 4) 545 reg += 0x4; 546 bit = (pin % 4) * 4; 547 } else { 548 bit = (pin % 8) * 2; 549 } 550 551 spin_lock_irqsave(&bank->slock, flags); 552 553 data = (mask << (bit + 16)); 554 rmask = data | (data >> 16); 555 data |= (mux & mask) << bit; 556 ret = regmap_update_bits(regmap, reg, rmask, data); 557 558 spin_unlock_irqrestore(&bank->slock, flags); 559 560 return ret; 561 } 562 563 #define RK2928_PULL_OFFSET 0x118 564 #define RK2928_PULL_PINS_PER_REG 16 565 #define RK2928_PULL_BANK_STRIDE 8 566 567 static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 568 int pin_num, struct regmap **regmap, 569 int *reg, u8 *bit) 570 { 571 struct rockchip_pinctrl *info = bank->drvdata; 572 573 *regmap = info->regmap_base; 574 *reg = RK2928_PULL_OFFSET; 575 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; 576 *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4; 577 578 *bit = pin_num % RK2928_PULL_PINS_PER_REG; 579 }; 580 581 #define RK3188_PULL_OFFSET 0x164 582 #define RK3188_PULL_BITS_PER_PIN 2 583 #define RK3188_PULL_PINS_PER_REG 8 584 #define RK3188_PULL_BANK_STRIDE 16 585 #define RK3188_PULL_PMU_OFFSET 0x64 586 587 static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 588 int pin_num, struct regmap **regmap, 589 int *reg, u8 *bit) 590 { 591 struct rockchip_pinctrl *info = bank->drvdata; 592 593 /* The first 12 pins of the first bank are located elsewhere */ 594 if (bank->bank_num == 0 && pin_num < 12) { 595 *regmap = info->regmap_pmu ? info->regmap_pmu 596 : bank->regmap_pull; 597 *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0; 598 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 599 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 600 *bit *= RK3188_PULL_BITS_PER_PIN; 601 } else { 602 *regmap = info->regmap_pull ? info->regmap_pull 603 : info->regmap_base; 604 *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET; 605 606 /* correct the offset, as it is the 2nd pull register */ 607 *reg -= 4; 608 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 609 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 610 611 /* 612 * The bits in these registers have an inverse ordering 613 * with the lowest pin being in bits 15:14 and the highest 614 * pin in bits 1:0 615 */ 616 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG); 617 *bit *= RK3188_PULL_BITS_PER_PIN; 618 } 619 } 620 621 #define RK3288_PULL_OFFSET 0x140 622 static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 623 int pin_num, struct regmap **regmap, 624 int *reg, u8 *bit) 625 { 626 struct rockchip_pinctrl *info = bank->drvdata; 627 628 /* The first 24 pins of the first bank are located in PMU */ 629 if (bank->bank_num == 0) { 630 *regmap = info->regmap_pmu; 631 *reg = RK3188_PULL_PMU_OFFSET; 632 633 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 634 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 635 *bit *= RK3188_PULL_BITS_PER_PIN; 636 } else { 637 *regmap = info->regmap_base; 638 *reg = RK3288_PULL_OFFSET; 639 640 /* correct the offset, as we're starting with the 2nd bank */ 641 *reg -= 0x10; 642 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 643 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 644 645 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 646 *bit *= RK3188_PULL_BITS_PER_PIN; 647 } 648 } 649 650 #define RK3288_DRV_PMU_OFFSET 0x70 651 #define RK3288_DRV_GRF_OFFSET 0x1c0 652 #define RK3288_DRV_BITS_PER_PIN 2 653 #define RK3288_DRV_PINS_PER_REG 8 654 #define RK3288_DRV_BANK_STRIDE 16 655 656 static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 657 int pin_num, struct regmap **regmap, 658 int *reg, u8 *bit) 659 { 660 struct rockchip_pinctrl *info = bank->drvdata; 661 662 /* The first 24 pins of the first bank are located in PMU */ 663 if (bank->bank_num == 0) { 664 *regmap = info->regmap_pmu; 665 *reg = RK3288_DRV_PMU_OFFSET; 666 667 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 668 *bit = pin_num % RK3288_DRV_PINS_PER_REG; 669 *bit *= RK3288_DRV_BITS_PER_PIN; 670 } else { 671 *regmap = info->regmap_base; 672 *reg = RK3288_DRV_GRF_OFFSET; 673 674 /* correct the offset, as we're starting with the 2nd bank */ 675 *reg -= 0x10; 676 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 677 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 678 679 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 680 *bit *= RK3288_DRV_BITS_PER_PIN; 681 } 682 } 683 684 #define RK3228_PULL_OFFSET 0x100 685 686 static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 687 int pin_num, struct regmap **regmap, 688 int *reg, u8 *bit) 689 { 690 struct rockchip_pinctrl *info = bank->drvdata; 691 692 *regmap = info->regmap_base; 693 *reg = RK3228_PULL_OFFSET; 694 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 695 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 696 697 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 698 *bit *= RK3188_PULL_BITS_PER_PIN; 699 } 700 701 #define RK3228_DRV_GRF_OFFSET 0x200 702 703 static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 704 int pin_num, struct regmap **regmap, 705 int *reg, u8 *bit) 706 { 707 struct rockchip_pinctrl *info = bank->drvdata; 708 709 *regmap = info->regmap_base; 710 *reg = RK3228_DRV_GRF_OFFSET; 711 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 712 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 713 714 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 715 *bit *= RK3288_DRV_BITS_PER_PIN; 716 } 717 718 #define RK3368_PULL_GRF_OFFSET 0x100 719 #define RK3368_PULL_PMU_OFFSET 0x10 720 721 static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 722 int pin_num, struct regmap **regmap, 723 int *reg, u8 *bit) 724 { 725 struct rockchip_pinctrl *info = bank->drvdata; 726 727 /* The first 32 pins of the first bank are located in PMU */ 728 if (bank->bank_num == 0) { 729 *regmap = info->regmap_pmu; 730 *reg = RK3368_PULL_PMU_OFFSET; 731 732 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 733 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 734 *bit *= RK3188_PULL_BITS_PER_PIN; 735 } else { 736 *regmap = info->regmap_base; 737 *reg = RK3368_PULL_GRF_OFFSET; 738 739 /* correct the offset, as we're starting with the 2nd bank */ 740 *reg -= 0x10; 741 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 742 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 743 744 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 745 *bit *= RK3188_PULL_BITS_PER_PIN; 746 } 747 } 748 749 #define RK3368_DRV_PMU_OFFSET 0x20 750 #define RK3368_DRV_GRF_OFFSET 0x200 751 752 static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 753 int pin_num, struct regmap **regmap, 754 int *reg, u8 *bit) 755 { 756 struct rockchip_pinctrl *info = bank->drvdata; 757 758 /* The first 32 pins of the first bank are located in PMU */ 759 if (bank->bank_num == 0) { 760 *regmap = info->regmap_pmu; 761 *reg = RK3368_DRV_PMU_OFFSET; 762 763 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 764 *bit = pin_num % RK3288_DRV_PINS_PER_REG; 765 *bit *= RK3288_DRV_BITS_PER_PIN; 766 } else { 767 *regmap = info->regmap_base; 768 *reg = RK3368_DRV_GRF_OFFSET; 769 770 /* correct the offset, as we're starting with the 2nd bank */ 771 *reg -= 0x10; 772 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 773 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 774 775 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 776 *bit *= RK3288_DRV_BITS_PER_PIN; 777 } 778 } 779 780 #define RK3399_PULL_GRF_OFFSET 0xe040 781 #define RK3399_PULL_PMU_OFFSET 0x40 782 #define RK3399_DRV_3BITS_PER_PIN 3 783 784 static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 785 int pin_num, struct regmap **regmap, 786 int *reg, u8 *bit) 787 { 788 struct rockchip_pinctrl *info = bank->drvdata; 789 790 /* The bank0:16 and bank1:32 pins are located in PMU */ 791 if ((bank->bank_num == 0) || (bank->bank_num == 1)) { 792 *regmap = info->regmap_pmu; 793 *reg = RK3399_PULL_PMU_OFFSET; 794 795 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 796 797 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 798 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 799 *bit *= RK3188_PULL_BITS_PER_PIN; 800 } else { 801 *regmap = info->regmap_base; 802 *reg = RK3399_PULL_GRF_OFFSET; 803 804 /* correct the offset, as we're starting with the 3rd bank */ 805 *reg -= 0x20; 806 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 807 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 808 809 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 810 *bit *= RK3188_PULL_BITS_PER_PIN; 811 } 812 } 813 814 static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 815 int pin_num, struct regmap **regmap, 816 int *reg, u8 *bit) 817 { 818 struct rockchip_pinctrl *info = bank->drvdata; 819 int drv_num = (pin_num / 8); 820 821 /* The bank0:16 and bank1:32 pins are located in PMU */ 822 if ((bank->bank_num == 0) || (bank->bank_num == 1)) 823 *regmap = info->regmap_pmu; 824 else 825 *regmap = info->regmap_base; 826 827 *reg = bank->drv[drv_num].offset; 828 if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) || 829 (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY)) 830 *bit = (pin_num % 8) * 3; 831 else 832 *bit = (pin_num % 8) * 2; 833 } 834 835 static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = { 836 { 2, 4, 8, 12, -1, -1, -1, -1 }, 837 { 3, 6, 9, 12, -1, -1, -1, -1 }, 838 { 5, 10, 15, 20, -1, -1, -1, -1 }, 839 { 4, 6, 8, 10, 12, 14, 16, 18 }, 840 { 4, 7, 10, 13, 16, 19, 22, 26 } 841 }; 842 843 static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank, 844 int pin_num) 845 { 846 struct rockchip_pinctrl *info = bank->drvdata; 847 struct rockchip_pin_ctrl *ctrl = info->ctrl; 848 struct regmap *regmap; 849 int reg, ret; 850 u32 data, temp, rmask_bits; 851 u8 bit; 852 int drv_type = bank->drv[pin_num / 8].drv_type; 853 854 ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); 855 856 switch (drv_type) { 857 case DRV_TYPE_IO_1V8_3V0_AUTO: 858 case DRV_TYPE_IO_3V3_ONLY: 859 rmask_bits = RK3399_DRV_3BITS_PER_PIN; 860 switch (bit) { 861 case 0 ... 12: 862 /* regular case, nothing to do */ 863 break; 864 case 15: 865 /* 866 * drive-strength offset is special, as it is 867 * spread over 2 registers 868 */ 869 ret = regmap_read(regmap, reg, &data); 870 if (ret) 871 return ret; 872 873 ret = regmap_read(regmap, reg + 0x4, &temp); 874 if (ret) 875 return ret; 876 877 /* 878 * the bit data[15] contains bit 0 of the value 879 * while temp[1:0] contains bits 2 and 1 880 */ 881 data >>= 15; 882 temp &= 0x3; 883 temp <<= 1; 884 data |= temp; 885 886 return rockchip_perpin_drv_list[drv_type][data]; 887 case 18 ... 21: 888 /* setting fully enclosed in the second register */ 889 reg += 4; 890 bit -= 16; 891 break; 892 default: 893 dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n", 894 bit, drv_type); 895 return -EINVAL; 896 } 897 898 break; 899 case DRV_TYPE_IO_DEFAULT: 900 case DRV_TYPE_IO_1V8_OR_3V0: 901 case DRV_TYPE_IO_1V8_ONLY: 902 rmask_bits = RK3288_DRV_BITS_PER_PIN; 903 break; 904 default: 905 dev_err(info->dev, "unsupported pinctrl drive type: %d\n", 906 drv_type); 907 return -EINVAL; 908 } 909 910 ret = regmap_read(regmap, reg, &data); 911 if (ret) 912 return ret; 913 914 data >>= bit; 915 data &= (1 << rmask_bits) - 1; 916 917 return rockchip_perpin_drv_list[drv_type][data]; 918 } 919 920 static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank, 921 int pin_num, int strength) 922 { 923 struct rockchip_pinctrl *info = bank->drvdata; 924 struct rockchip_pin_ctrl *ctrl = info->ctrl; 925 struct regmap *regmap; 926 unsigned long flags; 927 int reg, ret, i; 928 u32 data, rmask, rmask_bits, temp; 929 u8 bit; 930 int drv_type = bank->drv[pin_num / 8].drv_type; 931 932 dev_dbg(info->dev, "setting drive of GPIO%d-%d to %d\n", 933 bank->bank_num, pin_num, strength); 934 935 ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); 936 937 ret = -EINVAL; 938 for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) { 939 if (rockchip_perpin_drv_list[drv_type][i] == strength) { 940 ret = i; 941 break; 942 } else if (rockchip_perpin_drv_list[drv_type][i] < 0) { 943 ret = rockchip_perpin_drv_list[drv_type][i]; 944 break; 945 } 946 } 947 948 if (ret < 0) { 949 dev_err(info->dev, "unsupported driver strength %d\n", 950 strength); 951 return ret; 952 } 953 954 spin_lock_irqsave(&bank->slock, flags); 955 956 switch (drv_type) { 957 case DRV_TYPE_IO_1V8_3V0_AUTO: 958 case DRV_TYPE_IO_3V3_ONLY: 959 rmask_bits = RK3399_DRV_3BITS_PER_PIN; 960 switch (bit) { 961 case 0 ... 12: 962 /* regular case, nothing to do */ 963 break; 964 case 15: 965 /* 966 * drive-strength offset is special, as it is spread 967 * over 2 registers, the bit data[15] contains bit 0 968 * of the value while temp[1:0] contains bits 2 and 1 969 */ 970 data = (ret & 0x1) << 15; 971 temp = (ret >> 0x1) & 0x3; 972 973 rmask = BIT(15) | BIT(31); 974 data |= BIT(31); 975 ret = regmap_update_bits(regmap, reg, rmask, data); 976 if (ret) { 977 spin_unlock_irqrestore(&bank->slock, flags); 978 return ret; 979 } 980 981 rmask = 0x3 | (0x3 << 16); 982 temp |= (0x3 << 16); 983 reg += 0x4; 984 ret = regmap_update_bits(regmap, reg, rmask, temp); 985 986 spin_unlock_irqrestore(&bank->slock, flags); 987 return ret; 988 case 18 ... 21: 989 /* setting fully enclosed in the second register */ 990 reg += 4; 991 bit -= 16; 992 break; 993 default: 994 spin_unlock_irqrestore(&bank->slock, flags); 995 dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n", 996 bit, drv_type); 997 return -EINVAL; 998 } 999 break; 1000 case DRV_TYPE_IO_DEFAULT: 1001 case DRV_TYPE_IO_1V8_OR_3V0: 1002 case DRV_TYPE_IO_1V8_ONLY: 1003 rmask_bits = RK3288_DRV_BITS_PER_PIN; 1004 break; 1005 default: 1006 spin_unlock_irqrestore(&bank->slock, flags); 1007 dev_err(info->dev, "unsupported pinctrl drive type: %d\n", 1008 drv_type); 1009 return -EINVAL; 1010 } 1011 1012 /* enable the write to the equivalent lower bits */ 1013 data = ((1 << rmask_bits) - 1) << (bit + 16); 1014 rmask = data | (data >> 16); 1015 data |= (ret << bit); 1016 1017 ret = regmap_update_bits(regmap, reg, rmask, data); 1018 spin_unlock_irqrestore(&bank->slock, flags); 1019 1020 return ret; 1021 } 1022 1023 static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num) 1024 { 1025 struct rockchip_pinctrl *info = bank->drvdata; 1026 struct rockchip_pin_ctrl *ctrl = info->ctrl; 1027 struct regmap *regmap; 1028 int reg, ret; 1029 u8 bit; 1030 u32 data; 1031 1032 /* rk3066b does support any pulls */ 1033 if (ctrl->type == RK3066B) 1034 return PIN_CONFIG_BIAS_DISABLE; 1035 1036 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); 1037 1038 ret = regmap_read(regmap, reg, &data); 1039 if (ret) 1040 return ret; 1041 1042 switch (ctrl->type) { 1043 case RK2928: 1044 return !(data & BIT(bit)) 1045 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT 1046 : PIN_CONFIG_BIAS_DISABLE; 1047 case RK3188: 1048 case RK3288: 1049 case RK3368: 1050 case RK3399: 1051 data >>= bit; 1052 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1; 1053 1054 switch (data) { 1055 case 0: 1056 return PIN_CONFIG_BIAS_DISABLE; 1057 case 1: 1058 return PIN_CONFIG_BIAS_PULL_UP; 1059 case 2: 1060 return PIN_CONFIG_BIAS_PULL_DOWN; 1061 case 3: 1062 return PIN_CONFIG_BIAS_BUS_HOLD; 1063 } 1064 1065 dev_err(info->dev, "unknown pull setting\n"); 1066 return -EIO; 1067 default: 1068 dev_err(info->dev, "unsupported pinctrl type\n"); 1069 return -EINVAL; 1070 }; 1071 } 1072 1073 static int rockchip_set_pull(struct rockchip_pin_bank *bank, 1074 int pin_num, int pull) 1075 { 1076 struct rockchip_pinctrl *info = bank->drvdata; 1077 struct rockchip_pin_ctrl *ctrl = info->ctrl; 1078 struct regmap *regmap; 1079 int reg, ret; 1080 unsigned long flags; 1081 u8 bit; 1082 u32 data, rmask; 1083 1084 dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n", 1085 bank->bank_num, pin_num, pull); 1086 1087 /* rk3066b does support any pulls */ 1088 if (ctrl->type == RK3066B) 1089 return pull ? -EINVAL : 0; 1090 1091 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); 1092 1093 switch (ctrl->type) { 1094 case RK2928: 1095 spin_lock_irqsave(&bank->slock, flags); 1096 1097 data = BIT(bit + 16); 1098 if (pull == PIN_CONFIG_BIAS_DISABLE) 1099 data |= BIT(bit); 1100 ret = regmap_write(regmap, reg, data); 1101 1102 spin_unlock_irqrestore(&bank->slock, flags); 1103 break; 1104 case RK3188: 1105 case RK3288: 1106 case RK3368: 1107 case RK3399: 1108 spin_lock_irqsave(&bank->slock, flags); 1109 1110 /* enable the write to the equivalent lower bits */ 1111 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16); 1112 rmask = data | (data >> 16); 1113 1114 switch (pull) { 1115 case PIN_CONFIG_BIAS_DISABLE: 1116 break; 1117 case PIN_CONFIG_BIAS_PULL_UP: 1118 data |= (1 << bit); 1119 break; 1120 case PIN_CONFIG_BIAS_PULL_DOWN: 1121 data |= (2 << bit); 1122 break; 1123 case PIN_CONFIG_BIAS_BUS_HOLD: 1124 data |= (3 << bit); 1125 break; 1126 default: 1127 spin_unlock_irqrestore(&bank->slock, flags); 1128 dev_err(info->dev, "unsupported pull setting %d\n", 1129 pull); 1130 return -EINVAL; 1131 } 1132 1133 ret = regmap_update_bits(regmap, reg, rmask, data); 1134 1135 spin_unlock_irqrestore(&bank->slock, flags); 1136 break; 1137 default: 1138 dev_err(info->dev, "unsupported pinctrl type\n"); 1139 return -EINVAL; 1140 } 1141 1142 return ret; 1143 } 1144 1145 /* 1146 * Pinmux_ops handling 1147 */ 1148 1149 static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev) 1150 { 1151 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1152 1153 return info->nfunctions; 1154 } 1155 1156 static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev, 1157 unsigned selector) 1158 { 1159 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1160 1161 return info->functions[selector].name; 1162 } 1163 1164 static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev, 1165 unsigned selector, const char * const **groups, 1166 unsigned * const num_groups) 1167 { 1168 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1169 1170 *groups = info->functions[selector].groups; 1171 *num_groups = info->functions[selector].ngroups; 1172 1173 return 0; 1174 } 1175 1176 static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector, 1177 unsigned group) 1178 { 1179 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1180 const unsigned int *pins = info->groups[group].pins; 1181 const struct rockchip_pin_config *data = info->groups[group].data; 1182 struct rockchip_pin_bank *bank; 1183 int cnt, ret = 0; 1184 1185 dev_dbg(info->dev, "enable function %s group %s\n", 1186 info->functions[selector].name, info->groups[group].name); 1187 1188 /* 1189 * for each pin in the pin group selected, program the correspoding pin 1190 * pin function number in the config register. 1191 */ 1192 for (cnt = 0; cnt < info->groups[group].npins; cnt++) { 1193 bank = pin_to_bank(info, pins[cnt]); 1194 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 1195 data[cnt].func); 1196 if (ret) 1197 break; 1198 } 1199 1200 if (ret) { 1201 /* revert the already done pin settings */ 1202 for (cnt--; cnt >= 0; cnt--) 1203 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0); 1204 1205 return ret; 1206 } 1207 1208 return 0; 1209 } 1210 1211 /* 1212 * The calls to gpio_direction_output() and gpio_direction_input() 1213 * leads to this function call (via the pinctrl_gpio_direction_{input|output}() 1214 * function called from the gpiolib interface). 1215 */ 1216 static int _rockchip_pmx_gpio_set_direction(struct gpio_chip *chip, 1217 int pin, bool input) 1218 { 1219 struct rockchip_pin_bank *bank; 1220 int ret; 1221 unsigned long flags; 1222 u32 data; 1223 1224 bank = gpiochip_get_data(chip); 1225 1226 ret = rockchip_set_mux(bank, pin, RK_FUNC_GPIO); 1227 if (ret < 0) 1228 return ret; 1229 1230 clk_enable(bank->clk); 1231 spin_lock_irqsave(&bank->slock, flags); 1232 1233 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); 1234 /* set bit to 1 for output, 0 for input */ 1235 if (!input) 1236 data |= BIT(pin); 1237 else 1238 data &= ~BIT(pin); 1239 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR); 1240 1241 spin_unlock_irqrestore(&bank->slock, flags); 1242 clk_disable(bank->clk); 1243 1244 return 0; 1245 } 1246 1247 static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, 1248 struct pinctrl_gpio_range *range, 1249 unsigned offset, bool input) 1250 { 1251 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1252 struct gpio_chip *chip; 1253 int pin; 1254 1255 chip = range->gc; 1256 pin = offset - chip->base; 1257 dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n", 1258 offset, range->name, pin, input ? "input" : "output"); 1259 1260 return _rockchip_pmx_gpio_set_direction(chip, offset - chip->base, 1261 input); 1262 } 1263 1264 static const struct pinmux_ops rockchip_pmx_ops = { 1265 .get_functions_count = rockchip_pmx_get_funcs_count, 1266 .get_function_name = rockchip_pmx_get_func_name, 1267 .get_function_groups = rockchip_pmx_get_groups, 1268 .set_mux = rockchip_pmx_set, 1269 .gpio_set_direction = rockchip_pmx_gpio_set_direction, 1270 }; 1271 1272 /* 1273 * Pinconf_ops handling 1274 */ 1275 1276 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl, 1277 enum pin_config_param pull) 1278 { 1279 switch (ctrl->type) { 1280 case RK2928: 1281 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT || 1282 pull == PIN_CONFIG_BIAS_DISABLE); 1283 case RK3066B: 1284 return pull ? false : true; 1285 case RK3188: 1286 case RK3288: 1287 case RK3368: 1288 case RK3399: 1289 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT); 1290 } 1291 1292 return false; 1293 } 1294 1295 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value); 1296 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset); 1297 1298 /* set the pin config settings for a specified pin */ 1299 static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 1300 unsigned long *configs, unsigned num_configs) 1301 { 1302 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1303 struct rockchip_pin_bank *bank = pin_to_bank(info, pin); 1304 enum pin_config_param param; 1305 u16 arg; 1306 int i; 1307 int rc; 1308 1309 for (i = 0; i < num_configs; i++) { 1310 param = pinconf_to_config_param(configs[i]); 1311 arg = pinconf_to_config_argument(configs[i]); 1312 1313 switch (param) { 1314 case PIN_CONFIG_BIAS_DISABLE: 1315 rc = rockchip_set_pull(bank, pin - bank->pin_base, 1316 param); 1317 if (rc) 1318 return rc; 1319 break; 1320 case PIN_CONFIG_BIAS_PULL_UP: 1321 case PIN_CONFIG_BIAS_PULL_DOWN: 1322 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: 1323 case PIN_CONFIG_BIAS_BUS_HOLD: 1324 if (!rockchip_pinconf_pull_valid(info->ctrl, param)) 1325 return -ENOTSUPP; 1326 1327 if (!arg) 1328 return -EINVAL; 1329 1330 rc = rockchip_set_pull(bank, pin - bank->pin_base, 1331 param); 1332 if (rc) 1333 return rc; 1334 break; 1335 case PIN_CONFIG_OUTPUT: 1336 rockchip_gpio_set(&bank->gpio_chip, 1337 pin - bank->pin_base, arg); 1338 rc = _rockchip_pmx_gpio_set_direction(&bank->gpio_chip, 1339 pin - bank->pin_base, false); 1340 if (rc) 1341 return rc; 1342 break; 1343 case PIN_CONFIG_DRIVE_STRENGTH: 1344 /* rk3288 is the first with per-pin drive-strength */ 1345 if (!info->ctrl->drv_calc_reg) 1346 return -ENOTSUPP; 1347 1348 rc = rockchip_set_drive_perpin(bank, 1349 pin - bank->pin_base, arg); 1350 if (rc < 0) 1351 return rc; 1352 break; 1353 default: 1354 return -ENOTSUPP; 1355 break; 1356 } 1357 } /* for each config */ 1358 1359 return 0; 1360 } 1361 1362 /* get the pin config settings for a specified pin */ 1363 static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, 1364 unsigned long *config) 1365 { 1366 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1367 struct rockchip_pin_bank *bank = pin_to_bank(info, pin); 1368 enum pin_config_param param = pinconf_to_config_param(*config); 1369 u16 arg; 1370 int rc; 1371 1372 switch (param) { 1373 case PIN_CONFIG_BIAS_DISABLE: 1374 if (rockchip_get_pull(bank, pin - bank->pin_base) != param) 1375 return -EINVAL; 1376 1377 arg = 0; 1378 break; 1379 case PIN_CONFIG_BIAS_PULL_UP: 1380 case PIN_CONFIG_BIAS_PULL_DOWN: 1381 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: 1382 case PIN_CONFIG_BIAS_BUS_HOLD: 1383 if (!rockchip_pinconf_pull_valid(info->ctrl, param)) 1384 return -ENOTSUPP; 1385 1386 if (rockchip_get_pull(bank, pin - bank->pin_base) != param) 1387 return -EINVAL; 1388 1389 arg = 1; 1390 break; 1391 case PIN_CONFIG_OUTPUT: 1392 rc = rockchip_get_mux(bank, pin - bank->pin_base); 1393 if (rc != RK_FUNC_GPIO) 1394 return -EINVAL; 1395 1396 rc = rockchip_gpio_get(&bank->gpio_chip, pin - bank->pin_base); 1397 if (rc < 0) 1398 return rc; 1399 1400 arg = rc ? 1 : 0; 1401 break; 1402 case PIN_CONFIG_DRIVE_STRENGTH: 1403 /* rk3288 is the first with per-pin drive-strength */ 1404 if (!info->ctrl->drv_calc_reg) 1405 return -ENOTSUPP; 1406 1407 rc = rockchip_get_drive_perpin(bank, pin - bank->pin_base); 1408 if (rc < 0) 1409 return rc; 1410 1411 arg = rc; 1412 break; 1413 default: 1414 return -ENOTSUPP; 1415 break; 1416 } 1417 1418 *config = pinconf_to_config_packed(param, arg); 1419 1420 return 0; 1421 } 1422 1423 static const struct pinconf_ops rockchip_pinconf_ops = { 1424 .pin_config_get = rockchip_pinconf_get, 1425 .pin_config_set = rockchip_pinconf_set, 1426 .is_generic = true, 1427 }; 1428 1429 static const struct of_device_id rockchip_bank_match[] = { 1430 { .compatible = "rockchip,gpio-bank" }, 1431 { .compatible = "rockchip,rk3188-gpio-bank0" }, 1432 {}, 1433 }; 1434 1435 static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info, 1436 struct device_node *np) 1437 { 1438 struct device_node *child; 1439 1440 for_each_child_of_node(np, child) { 1441 if (of_match_node(rockchip_bank_match, child)) 1442 continue; 1443 1444 info->nfunctions++; 1445 info->ngroups += of_get_child_count(child); 1446 } 1447 } 1448 1449 static int rockchip_pinctrl_parse_groups(struct device_node *np, 1450 struct rockchip_pin_group *grp, 1451 struct rockchip_pinctrl *info, 1452 u32 index) 1453 { 1454 struct rockchip_pin_bank *bank; 1455 int size; 1456 const __be32 *list; 1457 int num; 1458 int i, j; 1459 int ret; 1460 1461 dev_dbg(info->dev, "group(%d): %s\n", index, np->name); 1462 1463 /* Initialise group */ 1464 grp->name = np->name; 1465 1466 /* 1467 * the binding format is rockchip,pins = <bank pin mux CONFIG>, 1468 * do sanity check and calculate pins number 1469 */ 1470 list = of_get_property(np, "rockchip,pins", &size); 1471 /* we do not check return since it's safe node passed down */ 1472 size /= sizeof(*list); 1473 if (!size || size % 4) { 1474 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n"); 1475 return -EINVAL; 1476 } 1477 1478 grp->npins = size / 4; 1479 1480 grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int), 1481 GFP_KERNEL); 1482 grp->data = devm_kzalloc(info->dev, grp->npins * 1483 sizeof(struct rockchip_pin_config), 1484 GFP_KERNEL); 1485 if (!grp->pins || !grp->data) 1486 return -ENOMEM; 1487 1488 for (i = 0, j = 0; i < size; i += 4, j++) { 1489 const __be32 *phandle; 1490 struct device_node *np_config; 1491 1492 num = be32_to_cpu(*list++); 1493 bank = bank_num_to_bank(info, num); 1494 if (IS_ERR(bank)) 1495 return PTR_ERR(bank); 1496 1497 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++); 1498 grp->data[j].func = be32_to_cpu(*list++); 1499 1500 phandle = list++; 1501 if (!phandle) 1502 return -EINVAL; 1503 1504 np_config = of_find_node_by_phandle(be32_to_cpup(phandle)); 1505 ret = pinconf_generic_parse_dt_config(np_config, NULL, 1506 &grp->data[j].configs, &grp->data[j].nconfigs); 1507 if (ret) 1508 return ret; 1509 } 1510 1511 return 0; 1512 } 1513 1514 static int rockchip_pinctrl_parse_functions(struct device_node *np, 1515 struct rockchip_pinctrl *info, 1516 u32 index) 1517 { 1518 struct device_node *child; 1519 struct rockchip_pmx_func *func; 1520 struct rockchip_pin_group *grp; 1521 int ret; 1522 static u32 grp_index; 1523 u32 i = 0; 1524 1525 dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name); 1526 1527 func = &info->functions[index]; 1528 1529 /* Initialise function */ 1530 func->name = np->name; 1531 func->ngroups = of_get_child_count(np); 1532 if (func->ngroups <= 0) 1533 return 0; 1534 1535 func->groups = devm_kzalloc(info->dev, 1536 func->ngroups * sizeof(char *), GFP_KERNEL); 1537 if (!func->groups) 1538 return -ENOMEM; 1539 1540 for_each_child_of_node(np, child) { 1541 func->groups[i] = child->name; 1542 grp = &info->groups[grp_index++]; 1543 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++); 1544 if (ret) { 1545 of_node_put(child); 1546 return ret; 1547 } 1548 } 1549 1550 return 0; 1551 } 1552 1553 static int rockchip_pinctrl_parse_dt(struct platform_device *pdev, 1554 struct rockchip_pinctrl *info) 1555 { 1556 struct device *dev = &pdev->dev; 1557 struct device_node *np = dev->of_node; 1558 struct device_node *child; 1559 int ret; 1560 int i; 1561 1562 rockchip_pinctrl_child_count(info, np); 1563 1564 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions); 1565 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups); 1566 1567 info->functions = devm_kzalloc(dev, info->nfunctions * 1568 sizeof(struct rockchip_pmx_func), 1569 GFP_KERNEL); 1570 if (!info->functions) { 1571 dev_err(dev, "failed to allocate memory for function list\n"); 1572 return -EINVAL; 1573 } 1574 1575 info->groups = devm_kzalloc(dev, info->ngroups * 1576 sizeof(struct rockchip_pin_group), 1577 GFP_KERNEL); 1578 if (!info->groups) { 1579 dev_err(dev, "failed allocate memory for ping group list\n"); 1580 return -EINVAL; 1581 } 1582 1583 i = 0; 1584 1585 for_each_child_of_node(np, child) { 1586 if (of_match_node(rockchip_bank_match, child)) 1587 continue; 1588 1589 ret = rockchip_pinctrl_parse_functions(child, info, i++); 1590 if (ret) { 1591 dev_err(&pdev->dev, "failed to parse function\n"); 1592 of_node_put(child); 1593 return ret; 1594 } 1595 } 1596 1597 return 0; 1598 } 1599 1600 static int rockchip_pinctrl_register(struct platform_device *pdev, 1601 struct rockchip_pinctrl *info) 1602 { 1603 struct pinctrl_desc *ctrldesc = &info->pctl; 1604 struct pinctrl_pin_desc *pindesc, *pdesc; 1605 struct rockchip_pin_bank *pin_bank; 1606 int pin, bank, ret; 1607 int k; 1608 1609 ctrldesc->name = "rockchip-pinctrl"; 1610 ctrldesc->owner = THIS_MODULE; 1611 ctrldesc->pctlops = &rockchip_pctrl_ops; 1612 ctrldesc->pmxops = &rockchip_pmx_ops; 1613 ctrldesc->confops = &rockchip_pinconf_ops; 1614 1615 pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) * 1616 info->ctrl->nr_pins, GFP_KERNEL); 1617 if (!pindesc) { 1618 dev_err(&pdev->dev, "mem alloc for pin descriptors failed\n"); 1619 return -ENOMEM; 1620 } 1621 ctrldesc->pins = pindesc; 1622 ctrldesc->npins = info->ctrl->nr_pins; 1623 1624 pdesc = pindesc; 1625 for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) { 1626 pin_bank = &info->ctrl->pin_banks[bank]; 1627 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) { 1628 pdesc->number = k; 1629 pdesc->name = kasprintf(GFP_KERNEL, "%s-%d", 1630 pin_bank->name, pin); 1631 pdesc++; 1632 } 1633 } 1634 1635 ret = rockchip_pinctrl_parse_dt(pdev, info); 1636 if (ret) 1637 return ret; 1638 1639 info->pctl_dev = pinctrl_register(ctrldesc, &pdev->dev, info); 1640 if (IS_ERR(info->pctl_dev)) { 1641 dev_err(&pdev->dev, "could not register pinctrl driver\n"); 1642 return PTR_ERR(info->pctl_dev); 1643 } 1644 1645 for (bank = 0; bank < info->ctrl->nr_banks; ++bank) { 1646 pin_bank = &info->ctrl->pin_banks[bank]; 1647 pin_bank->grange.name = pin_bank->name; 1648 pin_bank->grange.id = bank; 1649 pin_bank->grange.pin_base = pin_bank->pin_base; 1650 pin_bank->grange.base = pin_bank->gpio_chip.base; 1651 pin_bank->grange.npins = pin_bank->gpio_chip.ngpio; 1652 pin_bank->grange.gc = &pin_bank->gpio_chip; 1653 pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange); 1654 } 1655 1656 return 0; 1657 } 1658 1659 /* 1660 * GPIO handling 1661 */ 1662 1663 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value) 1664 { 1665 struct rockchip_pin_bank *bank = gpiochip_get_data(gc); 1666 void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR; 1667 unsigned long flags; 1668 u32 data; 1669 1670 clk_enable(bank->clk); 1671 spin_lock_irqsave(&bank->slock, flags); 1672 1673 data = readl(reg); 1674 data &= ~BIT(offset); 1675 if (value) 1676 data |= BIT(offset); 1677 writel(data, reg); 1678 1679 spin_unlock_irqrestore(&bank->slock, flags); 1680 clk_disable(bank->clk); 1681 } 1682 1683 /* 1684 * Returns the level of the pin for input direction and setting of the DR 1685 * register for output gpios. 1686 */ 1687 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset) 1688 { 1689 struct rockchip_pin_bank *bank = gpiochip_get_data(gc); 1690 u32 data; 1691 1692 clk_enable(bank->clk); 1693 data = readl(bank->reg_base + GPIO_EXT_PORT); 1694 clk_disable(bank->clk); 1695 data >>= offset; 1696 data &= 1; 1697 return data; 1698 } 1699 1700 /* 1701 * gpiolib gpio_direction_input callback function. The setting of the pin 1702 * mux function as 'gpio input' will be handled by the pinctrl susbsystem 1703 * interface. 1704 */ 1705 static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset) 1706 { 1707 return pinctrl_gpio_direction_input(gc->base + offset); 1708 } 1709 1710 /* 1711 * gpiolib gpio_direction_output callback function. The setting of the pin 1712 * mux function as 'gpio output' will be handled by the pinctrl susbsystem 1713 * interface. 1714 */ 1715 static int rockchip_gpio_direction_output(struct gpio_chip *gc, 1716 unsigned offset, int value) 1717 { 1718 rockchip_gpio_set(gc, offset, value); 1719 return pinctrl_gpio_direction_output(gc->base + offset); 1720 } 1721 1722 /* 1723 * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin 1724 * and a virtual IRQ, if not already present. 1725 */ 1726 static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset) 1727 { 1728 struct rockchip_pin_bank *bank = gpiochip_get_data(gc); 1729 unsigned int virq; 1730 1731 if (!bank->domain) 1732 return -ENXIO; 1733 1734 virq = irq_create_mapping(bank->domain, offset); 1735 1736 return (virq) ? : -ENXIO; 1737 } 1738 1739 static const struct gpio_chip rockchip_gpiolib_chip = { 1740 .request = gpiochip_generic_request, 1741 .free = gpiochip_generic_free, 1742 .set = rockchip_gpio_set, 1743 .get = rockchip_gpio_get, 1744 .direction_input = rockchip_gpio_direction_input, 1745 .direction_output = rockchip_gpio_direction_output, 1746 .to_irq = rockchip_gpio_to_irq, 1747 .owner = THIS_MODULE, 1748 }; 1749 1750 /* 1751 * Interrupt handling 1752 */ 1753 1754 static void rockchip_irq_demux(struct irq_desc *desc) 1755 { 1756 struct irq_chip *chip = irq_desc_get_chip(desc); 1757 struct rockchip_pin_bank *bank = irq_desc_get_handler_data(desc); 1758 u32 pend; 1759 1760 dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name); 1761 1762 chained_irq_enter(chip, desc); 1763 1764 pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS); 1765 1766 while (pend) { 1767 unsigned int irq, virq; 1768 1769 irq = __ffs(pend); 1770 pend &= ~BIT(irq); 1771 virq = irq_linear_revmap(bank->domain, irq); 1772 1773 if (!virq) { 1774 dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq); 1775 continue; 1776 } 1777 1778 dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq); 1779 1780 /* 1781 * Triggering IRQ on both rising and falling edge 1782 * needs manual intervention. 1783 */ 1784 if (bank->toggle_edge_mode & BIT(irq)) { 1785 u32 data, data_old, polarity; 1786 unsigned long flags; 1787 1788 data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT); 1789 do { 1790 spin_lock_irqsave(&bank->slock, flags); 1791 1792 polarity = readl_relaxed(bank->reg_base + 1793 GPIO_INT_POLARITY); 1794 if (data & BIT(irq)) 1795 polarity &= ~BIT(irq); 1796 else 1797 polarity |= BIT(irq); 1798 writel(polarity, 1799 bank->reg_base + GPIO_INT_POLARITY); 1800 1801 spin_unlock_irqrestore(&bank->slock, flags); 1802 1803 data_old = data; 1804 data = readl_relaxed(bank->reg_base + 1805 GPIO_EXT_PORT); 1806 } while ((data & BIT(irq)) != (data_old & BIT(irq))); 1807 } 1808 1809 generic_handle_irq(virq); 1810 } 1811 1812 chained_irq_exit(chip, desc); 1813 } 1814 1815 static int rockchip_irq_set_type(struct irq_data *d, unsigned int type) 1816 { 1817 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 1818 struct rockchip_pin_bank *bank = gc->private; 1819 u32 mask = BIT(d->hwirq); 1820 u32 polarity; 1821 u32 level; 1822 u32 data; 1823 unsigned long flags; 1824 int ret; 1825 1826 /* make sure the pin is configured as gpio input */ 1827 ret = rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO); 1828 if (ret < 0) 1829 return ret; 1830 1831 clk_enable(bank->clk); 1832 spin_lock_irqsave(&bank->slock, flags); 1833 1834 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); 1835 data &= ~mask; 1836 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR); 1837 1838 spin_unlock_irqrestore(&bank->slock, flags); 1839 1840 if (type & IRQ_TYPE_EDGE_BOTH) 1841 irq_set_handler_locked(d, handle_edge_irq); 1842 else 1843 irq_set_handler_locked(d, handle_level_irq); 1844 1845 spin_lock_irqsave(&bank->slock, flags); 1846 irq_gc_lock(gc); 1847 1848 level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL); 1849 polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY); 1850 1851 switch (type) { 1852 case IRQ_TYPE_EDGE_BOTH: 1853 bank->toggle_edge_mode |= mask; 1854 level |= mask; 1855 1856 /* 1857 * Determine gpio state. If 1 next interrupt should be falling 1858 * otherwise rising. 1859 */ 1860 data = readl(bank->reg_base + GPIO_EXT_PORT); 1861 if (data & mask) 1862 polarity &= ~mask; 1863 else 1864 polarity |= mask; 1865 break; 1866 case IRQ_TYPE_EDGE_RISING: 1867 bank->toggle_edge_mode &= ~mask; 1868 level |= mask; 1869 polarity |= mask; 1870 break; 1871 case IRQ_TYPE_EDGE_FALLING: 1872 bank->toggle_edge_mode &= ~mask; 1873 level |= mask; 1874 polarity &= ~mask; 1875 break; 1876 case IRQ_TYPE_LEVEL_HIGH: 1877 bank->toggle_edge_mode &= ~mask; 1878 level &= ~mask; 1879 polarity |= mask; 1880 break; 1881 case IRQ_TYPE_LEVEL_LOW: 1882 bank->toggle_edge_mode &= ~mask; 1883 level &= ~mask; 1884 polarity &= ~mask; 1885 break; 1886 default: 1887 irq_gc_unlock(gc); 1888 spin_unlock_irqrestore(&bank->slock, flags); 1889 clk_disable(bank->clk); 1890 return -EINVAL; 1891 } 1892 1893 writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL); 1894 writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY); 1895 1896 irq_gc_unlock(gc); 1897 spin_unlock_irqrestore(&bank->slock, flags); 1898 clk_disable(bank->clk); 1899 1900 return 0; 1901 } 1902 1903 static void rockchip_irq_suspend(struct irq_data *d) 1904 { 1905 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 1906 struct rockchip_pin_bank *bank = gc->private; 1907 1908 clk_enable(bank->clk); 1909 bank->saved_masks = irq_reg_readl(gc, GPIO_INTMASK); 1910 irq_reg_writel(gc, ~gc->wake_active, GPIO_INTMASK); 1911 clk_disable(bank->clk); 1912 } 1913 1914 static void rockchip_irq_resume(struct irq_data *d) 1915 { 1916 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 1917 struct rockchip_pin_bank *bank = gc->private; 1918 1919 clk_enable(bank->clk); 1920 irq_reg_writel(gc, bank->saved_masks, GPIO_INTMASK); 1921 clk_disable(bank->clk); 1922 } 1923 1924 static void rockchip_irq_gc_mask_clr_bit(struct irq_data *d) 1925 { 1926 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 1927 struct rockchip_pin_bank *bank = gc->private; 1928 1929 clk_enable(bank->clk); 1930 irq_gc_mask_clr_bit(d); 1931 } 1932 1933 void rockchip_irq_gc_mask_set_bit(struct irq_data *d) 1934 { 1935 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 1936 struct rockchip_pin_bank *bank = gc->private; 1937 1938 irq_gc_mask_set_bit(d); 1939 clk_disable(bank->clk); 1940 } 1941 1942 static int rockchip_interrupts_register(struct platform_device *pdev, 1943 struct rockchip_pinctrl *info) 1944 { 1945 struct rockchip_pin_ctrl *ctrl = info->ctrl; 1946 struct rockchip_pin_bank *bank = ctrl->pin_banks; 1947 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; 1948 struct irq_chip_generic *gc; 1949 int ret; 1950 int i, j; 1951 1952 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 1953 if (!bank->valid) { 1954 dev_warn(&pdev->dev, "bank %s is not valid\n", 1955 bank->name); 1956 continue; 1957 } 1958 1959 ret = clk_enable(bank->clk); 1960 if (ret) { 1961 dev_err(&pdev->dev, "failed to enable clock for bank %s\n", 1962 bank->name); 1963 continue; 1964 } 1965 1966 bank->domain = irq_domain_add_linear(bank->of_node, 32, 1967 &irq_generic_chip_ops, NULL); 1968 if (!bank->domain) { 1969 dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n", 1970 bank->name); 1971 clk_disable(bank->clk); 1972 continue; 1973 } 1974 1975 ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1, 1976 "rockchip_gpio_irq", handle_level_irq, 1977 clr, 0, IRQ_GC_INIT_MASK_CACHE); 1978 if (ret) { 1979 dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n", 1980 bank->name); 1981 irq_domain_remove(bank->domain); 1982 clk_disable(bank->clk); 1983 continue; 1984 } 1985 1986 /* 1987 * Linux assumes that all interrupts start out disabled/masked. 1988 * Our driver only uses the concept of masked and always keeps 1989 * things enabled, so for us that's all masked and all enabled. 1990 */ 1991 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTMASK); 1992 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTEN); 1993 1994 gc = irq_get_domain_generic_chip(bank->domain, 0); 1995 gc->reg_base = bank->reg_base; 1996 gc->private = bank; 1997 gc->chip_types[0].regs.mask = GPIO_INTMASK; 1998 gc->chip_types[0].regs.ack = GPIO_PORTS_EOI; 1999 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit; 2000 gc->chip_types[0].chip.irq_mask = rockchip_irq_gc_mask_set_bit; 2001 gc->chip_types[0].chip.irq_unmask = 2002 rockchip_irq_gc_mask_clr_bit; 2003 gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake; 2004 gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend; 2005 gc->chip_types[0].chip.irq_resume = rockchip_irq_resume; 2006 gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type; 2007 gc->wake_enabled = IRQ_MSK(bank->nr_pins); 2008 2009 irq_set_chained_handler_and_data(bank->irq, 2010 rockchip_irq_demux, bank); 2011 2012 /* map the gpio irqs here, when the clock is still running */ 2013 for (j = 0 ; j < 32 ; j++) 2014 irq_create_mapping(bank->domain, j); 2015 2016 clk_disable(bank->clk); 2017 } 2018 2019 return 0; 2020 } 2021 2022 static int rockchip_gpiolib_register(struct platform_device *pdev, 2023 struct rockchip_pinctrl *info) 2024 { 2025 struct rockchip_pin_ctrl *ctrl = info->ctrl; 2026 struct rockchip_pin_bank *bank = ctrl->pin_banks; 2027 struct gpio_chip *gc; 2028 int ret; 2029 int i; 2030 2031 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 2032 if (!bank->valid) { 2033 dev_warn(&pdev->dev, "bank %s is not valid\n", 2034 bank->name); 2035 continue; 2036 } 2037 2038 bank->gpio_chip = rockchip_gpiolib_chip; 2039 2040 gc = &bank->gpio_chip; 2041 gc->base = bank->pin_base; 2042 gc->ngpio = bank->nr_pins; 2043 gc->parent = &pdev->dev; 2044 gc->of_node = bank->of_node; 2045 gc->label = bank->name; 2046 2047 ret = gpiochip_add_data(gc, bank); 2048 if (ret) { 2049 dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n", 2050 gc->label, ret); 2051 goto fail; 2052 } 2053 } 2054 2055 rockchip_interrupts_register(pdev, info); 2056 2057 return 0; 2058 2059 fail: 2060 for (--i, --bank; i >= 0; --i, --bank) { 2061 if (!bank->valid) 2062 continue; 2063 gpiochip_remove(&bank->gpio_chip); 2064 } 2065 return ret; 2066 } 2067 2068 static int rockchip_gpiolib_unregister(struct platform_device *pdev, 2069 struct rockchip_pinctrl *info) 2070 { 2071 struct rockchip_pin_ctrl *ctrl = info->ctrl; 2072 struct rockchip_pin_bank *bank = ctrl->pin_banks; 2073 int i; 2074 2075 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 2076 if (!bank->valid) 2077 continue; 2078 gpiochip_remove(&bank->gpio_chip); 2079 } 2080 2081 return 0; 2082 } 2083 2084 static int rockchip_get_bank_data(struct rockchip_pin_bank *bank, 2085 struct rockchip_pinctrl *info) 2086 { 2087 struct resource res; 2088 void __iomem *base; 2089 2090 if (of_address_to_resource(bank->of_node, 0, &res)) { 2091 dev_err(info->dev, "cannot find IO resource for bank\n"); 2092 return -ENOENT; 2093 } 2094 2095 bank->reg_base = devm_ioremap_resource(info->dev, &res); 2096 if (IS_ERR(bank->reg_base)) 2097 return PTR_ERR(bank->reg_base); 2098 2099 /* 2100 * special case, where parts of the pull setting-registers are 2101 * part of the PMU register space 2102 */ 2103 if (of_device_is_compatible(bank->of_node, 2104 "rockchip,rk3188-gpio-bank0")) { 2105 struct device_node *node; 2106 2107 node = of_parse_phandle(bank->of_node->parent, 2108 "rockchip,pmu", 0); 2109 if (!node) { 2110 if (of_address_to_resource(bank->of_node, 1, &res)) { 2111 dev_err(info->dev, "cannot find IO resource for bank\n"); 2112 return -ENOENT; 2113 } 2114 2115 base = devm_ioremap_resource(info->dev, &res); 2116 if (IS_ERR(base)) 2117 return PTR_ERR(base); 2118 rockchip_regmap_config.max_register = 2119 resource_size(&res) - 4; 2120 rockchip_regmap_config.name = 2121 "rockchip,rk3188-gpio-bank0-pull"; 2122 bank->regmap_pull = devm_regmap_init_mmio(info->dev, 2123 base, 2124 &rockchip_regmap_config); 2125 } 2126 } 2127 2128 bank->irq = irq_of_parse_and_map(bank->of_node, 0); 2129 2130 bank->clk = of_clk_get(bank->of_node, 0); 2131 if (IS_ERR(bank->clk)) 2132 return PTR_ERR(bank->clk); 2133 2134 return clk_prepare(bank->clk); 2135 } 2136 2137 static const struct of_device_id rockchip_pinctrl_dt_match[]; 2138 2139 /* retrieve the soc specific data */ 2140 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data( 2141 struct rockchip_pinctrl *d, 2142 struct platform_device *pdev) 2143 { 2144 const struct of_device_id *match; 2145 struct device_node *node = pdev->dev.of_node; 2146 struct device_node *np; 2147 struct rockchip_pin_ctrl *ctrl; 2148 struct rockchip_pin_bank *bank; 2149 int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j; 2150 2151 match = of_match_node(rockchip_pinctrl_dt_match, node); 2152 ctrl = (struct rockchip_pin_ctrl *)match->data; 2153 2154 for_each_child_of_node(node, np) { 2155 if (!of_find_property(np, "gpio-controller", NULL)) 2156 continue; 2157 2158 bank = ctrl->pin_banks; 2159 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 2160 if (!strcmp(bank->name, np->name)) { 2161 bank->of_node = np; 2162 2163 if (!rockchip_get_bank_data(bank, d)) 2164 bank->valid = true; 2165 2166 break; 2167 } 2168 } 2169 } 2170 2171 grf_offs = ctrl->grf_mux_offset; 2172 pmu_offs = ctrl->pmu_mux_offset; 2173 drv_pmu_offs = ctrl->pmu_drv_offset; 2174 drv_grf_offs = ctrl->grf_drv_offset; 2175 bank = ctrl->pin_banks; 2176 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 2177 int bank_pins = 0; 2178 2179 spin_lock_init(&bank->slock); 2180 bank->drvdata = d; 2181 bank->pin_base = ctrl->nr_pins; 2182 ctrl->nr_pins += bank->nr_pins; 2183 2184 /* calculate iomux and drv offsets */ 2185 for (j = 0; j < 4; j++) { 2186 struct rockchip_iomux *iom = &bank->iomux[j]; 2187 struct rockchip_drv *drv = &bank->drv[j]; 2188 int inc; 2189 2190 if (bank_pins >= bank->nr_pins) 2191 break; 2192 2193 /* preset iomux offset value, set new start value */ 2194 if (iom->offset >= 0) { 2195 if (iom->type & IOMUX_SOURCE_PMU) 2196 pmu_offs = iom->offset; 2197 else 2198 grf_offs = iom->offset; 2199 } else { /* set current iomux offset */ 2200 iom->offset = (iom->type & IOMUX_SOURCE_PMU) ? 2201 pmu_offs : grf_offs; 2202 } 2203 2204 /* preset drv offset value, set new start value */ 2205 if (drv->offset >= 0) { 2206 if (iom->type & IOMUX_SOURCE_PMU) 2207 drv_pmu_offs = drv->offset; 2208 else 2209 drv_grf_offs = drv->offset; 2210 } else { /* set current drv offset */ 2211 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ? 2212 drv_pmu_offs : drv_grf_offs; 2213 } 2214 2215 dev_dbg(d->dev, "bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n", 2216 i, j, iom->offset, drv->offset); 2217 2218 /* 2219 * Increase offset according to iomux width. 2220 * 4bit iomux'es are spread over two registers. 2221 */ 2222 inc = (iom->type & IOMUX_WIDTH_4BIT) ? 8 : 4; 2223 if (iom->type & IOMUX_SOURCE_PMU) 2224 pmu_offs += inc; 2225 else 2226 grf_offs += inc; 2227 2228 /* 2229 * Increase offset according to drv width. 2230 * 3bit drive-strenth'es are spread over two registers. 2231 */ 2232 if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) || 2233 (drv->drv_type == DRV_TYPE_IO_3V3_ONLY)) 2234 inc = 8; 2235 else 2236 inc = 4; 2237 2238 if (iom->type & IOMUX_SOURCE_PMU) 2239 drv_pmu_offs += inc; 2240 else 2241 drv_grf_offs += inc; 2242 2243 bank_pins += 8; 2244 } 2245 } 2246 2247 return ctrl; 2248 } 2249 2250 #define RK3288_GRF_GPIO6C_IOMUX 0x64 2251 #define GPIO6C6_SEL_WRITE_ENABLE BIT(28) 2252 2253 static u32 rk3288_grf_gpio6c_iomux; 2254 2255 static int __maybe_unused rockchip_pinctrl_suspend(struct device *dev) 2256 { 2257 struct rockchip_pinctrl *info = dev_get_drvdata(dev); 2258 int ret = pinctrl_force_sleep(info->pctl_dev); 2259 2260 if (ret) 2261 return ret; 2262 2263 /* 2264 * RK3288 GPIO6_C6 mux would be modified by Maskrom when resume, so save 2265 * the setting here, and restore it at resume. 2266 */ 2267 if (info->ctrl->type == RK3288) { 2268 ret = regmap_read(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX, 2269 &rk3288_grf_gpio6c_iomux); 2270 if (ret) { 2271 pinctrl_force_default(info->pctl_dev); 2272 return ret; 2273 } 2274 } 2275 2276 return 0; 2277 } 2278 2279 static int __maybe_unused rockchip_pinctrl_resume(struct device *dev) 2280 { 2281 struct rockchip_pinctrl *info = dev_get_drvdata(dev); 2282 int ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX, 2283 rk3288_grf_gpio6c_iomux | 2284 GPIO6C6_SEL_WRITE_ENABLE); 2285 2286 if (ret) 2287 return ret; 2288 2289 return pinctrl_force_default(info->pctl_dev); 2290 } 2291 2292 static SIMPLE_DEV_PM_OPS(rockchip_pinctrl_dev_pm_ops, rockchip_pinctrl_suspend, 2293 rockchip_pinctrl_resume); 2294 2295 static int rockchip_pinctrl_probe(struct platform_device *pdev) 2296 { 2297 struct rockchip_pinctrl *info; 2298 struct device *dev = &pdev->dev; 2299 struct rockchip_pin_ctrl *ctrl; 2300 struct device_node *np = pdev->dev.of_node, *node; 2301 struct resource *res; 2302 void __iomem *base; 2303 int ret; 2304 2305 if (!dev->of_node) { 2306 dev_err(dev, "device tree node not found\n"); 2307 return -ENODEV; 2308 } 2309 2310 info = devm_kzalloc(dev, sizeof(struct rockchip_pinctrl), GFP_KERNEL); 2311 if (!info) 2312 return -ENOMEM; 2313 2314 info->dev = dev; 2315 2316 ctrl = rockchip_pinctrl_get_soc_data(info, pdev); 2317 if (!ctrl) { 2318 dev_err(dev, "driver data not available\n"); 2319 return -EINVAL; 2320 } 2321 info->ctrl = ctrl; 2322 2323 node = of_parse_phandle(np, "rockchip,grf", 0); 2324 if (node) { 2325 info->regmap_base = syscon_node_to_regmap(node); 2326 if (IS_ERR(info->regmap_base)) 2327 return PTR_ERR(info->regmap_base); 2328 } else { 2329 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2330 base = devm_ioremap_resource(&pdev->dev, res); 2331 if (IS_ERR(base)) 2332 return PTR_ERR(base); 2333 2334 rockchip_regmap_config.max_register = resource_size(res) - 4; 2335 rockchip_regmap_config.name = "rockchip,pinctrl"; 2336 info->regmap_base = devm_regmap_init_mmio(&pdev->dev, base, 2337 &rockchip_regmap_config); 2338 2339 /* to check for the old dt-bindings */ 2340 info->reg_size = resource_size(res); 2341 2342 /* Honor the old binding, with pull registers as 2nd resource */ 2343 if (ctrl->type == RK3188 && info->reg_size < 0x200) { 2344 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 2345 base = devm_ioremap_resource(&pdev->dev, res); 2346 if (IS_ERR(base)) 2347 return PTR_ERR(base); 2348 2349 rockchip_regmap_config.max_register = 2350 resource_size(res) - 4; 2351 rockchip_regmap_config.name = "rockchip,pinctrl-pull"; 2352 info->regmap_pull = devm_regmap_init_mmio(&pdev->dev, 2353 base, 2354 &rockchip_regmap_config); 2355 } 2356 } 2357 2358 /* try to find the optional reference to the pmu syscon */ 2359 node = of_parse_phandle(np, "rockchip,pmu", 0); 2360 if (node) { 2361 info->regmap_pmu = syscon_node_to_regmap(node); 2362 if (IS_ERR(info->regmap_pmu)) 2363 return PTR_ERR(info->regmap_pmu); 2364 } 2365 2366 ret = rockchip_gpiolib_register(pdev, info); 2367 if (ret) 2368 return ret; 2369 2370 ret = rockchip_pinctrl_register(pdev, info); 2371 if (ret) { 2372 rockchip_gpiolib_unregister(pdev, info); 2373 return ret; 2374 } 2375 2376 platform_set_drvdata(pdev, info); 2377 2378 return 0; 2379 } 2380 2381 static struct rockchip_pin_bank rk2928_pin_banks[] = { 2382 PIN_BANK(0, 32, "gpio0"), 2383 PIN_BANK(1, 32, "gpio1"), 2384 PIN_BANK(2, 32, "gpio2"), 2385 PIN_BANK(3, 32, "gpio3"), 2386 }; 2387 2388 static struct rockchip_pin_ctrl rk2928_pin_ctrl = { 2389 .pin_banks = rk2928_pin_banks, 2390 .nr_banks = ARRAY_SIZE(rk2928_pin_banks), 2391 .label = "RK2928-GPIO", 2392 .type = RK2928, 2393 .grf_mux_offset = 0xa8, 2394 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 2395 }; 2396 2397 static struct rockchip_pin_bank rk3036_pin_banks[] = { 2398 PIN_BANK(0, 32, "gpio0"), 2399 PIN_BANK(1, 32, "gpio1"), 2400 PIN_BANK(2, 32, "gpio2"), 2401 }; 2402 2403 static struct rockchip_pin_ctrl rk3036_pin_ctrl = { 2404 .pin_banks = rk3036_pin_banks, 2405 .nr_banks = ARRAY_SIZE(rk3036_pin_banks), 2406 .label = "RK3036-GPIO", 2407 .type = RK2928, 2408 .grf_mux_offset = 0xa8, 2409 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 2410 }; 2411 2412 static struct rockchip_pin_bank rk3066a_pin_banks[] = { 2413 PIN_BANK(0, 32, "gpio0"), 2414 PIN_BANK(1, 32, "gpio1"), 2415 PIN_BANK(2, 32, "gpio2"), 2416 PIN_BANK(3, 32, "gpio3"), 2417 PIN_BANK(4, 32, "gpio4"), 2418 PIN_BANK(6, 16, "gpio6"), 2419 }; 2420 2421 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = { 2422 .pin_banks = rk3066a_pin_banks, 2423 .nr_banks = ARRAY_SIZE(rk3066a_pin_banks), 2424 .label = "RK3066a-GPIO", 2425 .type = RK2928, 2426 .grf_mux_offset = 0xa8, 2427 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 2428 }; 2429 2430 static struct rockchip_pin_bank rk3066b_pin_banks[] = { 2431 PIN_BANK(0, 32, "gpio0"), 2432 PIN_BANK(1, 32, "gpio1"), 2433 PIN_BANK(2, 32, "gpio2"), 2434 PIN_BANK(3, 32, "gpio3"), 2435 }; 2436 2437 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = { 2438 .pin_banks = rk3066b_pin_banks, 2439 .nr_banks = ARRAY_SIZE(rk3066b_pin_banks), 2440 .label = "RK3066b-GPIO", 2441 .type = RK3066B, 2442 .grf_mux_offset = 0x60, 2443 }; 2444 2445 static struct rockchip_pin_bank rk3188_pin_banks[] = { 2446 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0), 2447 PIN_BANK(1, 32, "gpio1"), 2448 PIN_BANK(2, 32, "gpio2"), 2449 PIN_BANK(3, 32, "gpio3"), 2450 }; 2451 2452 static struct rockchip_pin_ctrl rk3188_pin_ctrl = { 2453 .pin_banks = rk3188_pin_banks, 2454 .nr_banks = ARRAY_SIZE(rk3188_pin_banks), 2455 .label = "RK3188-GPIO", 2456 .type = RK3188, 2457 .grf_mux_offset = 0x60, 2458 .pull_calc_reg = rk3188_calc_pull_reg_and_bit, 2459 }; 2460 2461 static struct rockchip_pin_bank rk3228_pin_banks[] = { 2462 PIN_BANK(0, 32, "gpio0"), 2463 PIN_BANK(1, 32, "gpio1"), 2464 PIN_BANK(2, 32, "gpio2"), 2465 PIN_BANK(3, 32, "gpio3"), 2466 }; 2467 2468 static struct rockchip_pin_ctrl rk3228_pin_ctrl = { 2469 .pin_banks = rk3228_pin_banks, 2470 .nr_banks = ARRAY_SIZE(rk3228_pin_banks), 2471 .label = "RK3228-GPIO", 2472 .type = RK3288, 2473 .grf_mux_offset = 0x0, 2474 .pull_calc_reg = rk3228_calc_pull_reg_and_bit, 2475 .drv_calc_reg = rk3228_calc_drv_reg_and_bit, 2476 }; 2477 2478 static struct rockchip_pin_bank rk3288_pin_banks[] = { 2479 PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU, 2480 IOMUX_SOURCE_PMU, 2481 IOMUX_SOURCE_PMU, 2482 IOMUX_UNROUTED 2483 ), 2484 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED, 2485 IOMUX_UNROUTED, 2486 IOMUX_UNROUTED, 2487 0 2488 ), 2489 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED), 2490 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT), 2491 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT, 2492 IOMUX_WIDTH_4BIT, 2493 0, 2494 0 2495 ), 2496 PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED, 2497 0, 2498 0, 2499 IOMUX_UNROUTED 2500 ), 2501 PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED), 2502 PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0, 2503 0, 2504 IOMUX_WIDTH_4BIT, 2505 IOMUX_UNROUTED 2506 ), 2507 PIN_BANK(8, 16, "gpio8"), 2508 }; 2509 2510 static struct rockchip_pin_ctrl rk3288_pin_ctrl = { 2511 .pin_banks = rk3288_pin_banks, 2512 .nr_banks = ARRAY_SIZE(rk3288_pin_banks), 2513 .label = "RK3288-GPIO", 2514 .type = RK3288, 2515 .grf_mux_offset = 0x0, 2516 .pmu_mux_offset = 0x84, 2517 .pull_calc_reg = rk3288_calc_pull_reg_and_bit, 2518 .drv_calc_reg = rk3288_calc_drv_reg_and_bit, 2519 }; 2520 2521 static struct rockchip_pin_bank rk3368_pin_banks[] = { 2522 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, 2523 IOMUX_SOURCE_PMU, 2524 IOMUX_SOURCE_PMU, 2525 IOMUX_SOURCE_PMU 2526 ), 2527 PIN_BANK(1, 32, "gpio1"), 2528 PIN_BANK(2, 32, "gpio2"), 2529 PIN_BANK(3, 32, "gpio3"), 2530 }; 2531 2532 static struct rockchip_pin_ctrl rk3368_pin_ctrl = { 2533 .pin_banks = rk3368_pin_banks, 2534 .nr_banks = ARRAY_SIZE(rk3368_pin_banks), 2535 .label = "RK3368-GPIO", 2536 .type = RK3368, 2537 .grf_mux_offset = 0x0, 2538 .pmu_mux_offset = 0x0, 2539 .pull_calc_reg = rk3368_calc_pull_reg_and_bit, 2540 .drv_calc_reg = rk3368_calc_drv_reg_and_bit, 2541 }; 2542 2543 static struct rockchip_pin_bank rk3399_pin_banks[] = { 2544 PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(0, 32, "gpio0", IOMUX_SOURCE_PMU, 2545 IOMUX_SOURCE_PMU, 2546 IOMUX_SOURCE_PMU, 2547 IOMUX_SOURCE_PMU, 2548 DRV_TYPE_IO_1V8_ONLY, 2549 DRV_TYPE_IO_1V8_ONLY, 2550 DRV_TYPE_IO_DEFAULT, 2551 DRV_TYPE_IO_DEFAULT, 2552 0x0, 2553 0x8, 2554 -1, 2555 -1 2556 ), 2557 PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU, 2558 IOMUX_SOURCE_PMU, 2559 IOMUX_SOURCE_PMU, 2560 IOMUX_SOURCE_PMU, 2561 DRV_TYPE_IO_1V8_OR_3V0, 2562 DRV_TYPE_IO_1V8_OR_3V0, 2563 DRV_TYPE_IO_1V8_OR_3V0, 2564 DRV_TYPE_IO_1V8_OR_3V0, 2565 0x20, 2566 0x28, 2567 0x30, 2568 0x38 2569 ), 2570 PIN_BANK_DRV_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0, 2571 DRV_TYPE_IO_1V8_OR_3V0, 2572 DRV_TYPE_IO_1V8_ONLY, 2573 DRV_TYPE_IO_1V8_ONLY 2574 ), 2575 PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY, 2576 DRV_TYPE_IO_3V3_ONLY, 2577 DRV_TYPE_IO_3V3_ONLY, 2578 DRV_TYPE_IO_1V8_OR_3V0 2579 ), 2580 PIN_BANK_DRV_FLAGS(4, 32, "gpio4", DRV_TYPE_IO_1V8_OR_3V0, 2581 DRV_TYPE_IO_1V8_3V0_AUTO, 2582 DRV_TYPE_IO_1V8_OR_3V0, 2583 DRV_TYPE_IO_1V8_OR_3V0 2584 ), 2585 }; 2586 2587 static struct rockchip_pin_ctrl rk3399_pin_ctrl = { 2588 .pin_banks = rk3399_pin_banks, 2589 .nr_banks = ARRAY_SIZE(rk3399_pin_banks), 2590 .label = "RK3399-GPIO", 2591 .type = RK3399, 2592 .grf_mux_offset = 0xe000, 2593 .pmu_mux_offset = 0x0, 2594 .grf_drv_offset = 0xe100, 2595 .pmu_drv_offset = 0x80, 2596 .pull_calc_reg = rk3399_calc_pull_reg_and_bit, 2597 .drv_calc_reg = rk3399_calc_drv_reg_and_bit, 2598 }; 2599 2600 static const struct of_device_id rockchip_pinctrl_dt_match[] = { 2601 { .compatible = "rockchip,rk2928-pinctrl", 2602 .data = (void *)&rk2928_pin_ctrl }, 2603 { .compatible = "rockchip,rk3036-pinctrl", 2604 .data = (void *)&rk3036_pin_ctrl }, 2605 { .compatible = "rockchip,rk3066a-pinctrl", 2606 .data = (void *)&rk3066a_pin_ctrl }, 2607 { .compatible = "rockchip,rk3066b-pinctrl", 2608 .data = (void *)&rk3066b_pin_ctrl }, 2609 { .compatible = "rockchip,rk3188-pinctrl", 2610 .data = (void *)&rk3188_pin_ctrl }, 2611 { .compatible = "rockchip,rk3228-pinctrl", 2612 .data = (void *)&rk3228_pin_ctrl }, 2613 { .compatible = "rockchip,rk3288-pinctrl", 2614 .data = (void *)&rk3288_pin_ctrl }, 2615 { .compatible = "rockchip,rk3368-pinctrl", 2616 .data = (void *)&rk3368_pin_ctrl }, 2617 { .compatible = "rockchip,rk3399-pinctrl", 2618 .data = (void *)&rk3399_pin_ctrl }, 2619 {}, 2620 }; 2621 MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match); 2622 2623 static struct platform_driver rockchip_pinctrl_driver = { 2624 .probe = rockchip_pinctrl_probe, 2625 .driver = { 2626 .name = "rockchip-pinctrl", 2627 .pm = &rockchip_pinctrl_dev_pm_ops, 2628 .of_match_table = rockchip_pinctrl_dt_match, 2629 }, 2630 }; 2631 2632 static int __init rockchip_pinctrl_drv_register(void) 2633 { 2634 return platform_driver_register(&rockchip_pinctrl_driver); 2635 } 2636 postcore_initcall(rockchip_pinctrl_drv_register); 2637 2638 MODULE_AUTHOR("Heiko Stuebner <heiko@sntech.de>"); 2639 MODULE_DESCRIPTION("Rockchip pinctrl driver"); 2640 MODULE_LICENSE("GPL v2"); 2641