1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Pinctrl driver for Rockchip SoCs 4 * 5 * Copyright (c) 2013 MundoReader S.L. 6 * Author: Heiko Stuebner <heiko@sntech.de> 7 * 8 * With some ideas taken from pinctrl-samsung: 9 * Copyright (c) 2012 Samsung Electronics Co., Ltd. 10 * http://www.samsung.com 11 * Copyright (c) 2012 Linaro Ltd 12 * https://www.linaro.org 13 * 14 * and pinctrl-at91: 15 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> 16 */ 17 18 #include <linux/init.h> 19 #include <linux/module.h> 20 #include <linux/platform_device.h> 21 #include <linux/io.h> 22 #include <linux/bitops.h> 23 #include <linux/gpio/driver.h> 24 #include <linux/of_address.h> 25 #include <linux/of_device.h> 26 #include <linux/of_irq.h> 27 #include <linux/pinctrl/machine.h> 28 #include <linux/pinctrl/pinconf.h> 29 #include <linux/pinctrl/pinctrl.h> 30 #include <linux/pinctrl/pinmux.h> 31 #include <linux/pinctrl/pinconf-generic.h> 32 #include <linux/irqchip/chained_irq.h> 33 #include <linux/clk.h> 34 #include <linux/regmap.h> 35 #include <linux/mfd/syscon.h> 36 #include <linux/string_helpers.h> 37 38 #include <dt-bindings/pinctrl/rockchip.h> 39 40 #include "core.h" 41 #include "pinconf.h" 42 #include "pinctrl-rockchip.h" 43 44 /* 45 * Generate a bitmask for setting a value (v) with a write mask bit in hiword 46 * register 31:16 area. 47 */ 48 #define WRITE_MASK_VAL(h, l, v) \ 49 (GENMASK(((h) + 16), ((l) + 16)) | (((v) << (l)) & GENMASK((h), (l)))) 50 51 /* 52 * Encode variants of iomux registers into a type variable 53 */ 54 #define IOMUX_GPIO_ONLY BIT(0) 55 #define IOMUX_WIDTH_4BIT BIT(1) 56 #define IOMUX_SOURCE_PMU BIT(2) 57 #define IOMUX_UNROUTED BIT(3) 58 #define IOMUX_WIDTH_3BIT BIT(4) 59 #define IOMUX_WIDTH_2BIT BIT(5) 60 61 #define PIN_BANK(id, pins, label) \ 62 { \ 63 .bank_num = id, \ 64 .nr_pins = pins, \ 65 .name = label, \ 66 .iomux = { \ 67 { .offset = -1 }, \ 68 { .offset = -1 }, \ 69 { .offset = -1 }, \ 70 { .offset = -1 }, \ 71 }, \ 72 } 73 74 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \ 75 { \ 76 .bank_num = id, \ 77 .nr_pins = pins, \ 78 .name = label, \ 79 .iomux = { \ 80 { .type = iom0, .offset = -1 }, \ 81 { .type = iom1, .offset = -1 }, \ 82 { .type = iom2, .offset = -1 }, \ 83 { .type = iom3, .offset = -1 }, \ 84 }, \ 85 } 86 87 #define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \ 88 { \ 89 .bank_num = id, \ 90 .nr_pins = pins, \ 91 .name = label, \ 92 .iomux = { \ 93 { .offset = -1 }, \ 94 { .offset = -1 }, \ 95 { .offset = -1 }, \ 96 { .offset = -1 }, \ 97 }, \ 98 .drv = { \ 99 { .drv_type = type0, .offset = -1 }, \ 100 { .drv_type = type1, .offset = -1 }, \ 101 { .drv_type = type2, .offset = -1 }, \ 102 { .drv_type = type3, .offset = -1 }, \ 103 }, \ 104 } 105 106 #define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1, \ 107 drv2, drv3, pull0, pull1, \ 108 pull2, pull3) \ 109 { \ 110 .bank_num = id, \ 111 .nr_pins = pins, \ 112 .name = label, \ 113 .iomux = { \ 114 { .offset = -1 }, \ 115 { .offset = -1 }, \ 116 { .offset = -1 }, \ 117 { .offset = -1 }, \ 118 }, \ 119 .drv = { \ 120 { .drv_type = drv0, .offset = -1 }, \ 121 { .drv_type = drv1, .offset = -1 }, \ 122 { .drv_type = drv2, .offset = -1 }, \ 123 { .drv_type = drv3, .offset = -1 }, \ 124 }, \ 125 .pull_type[0] = pull0, \ 126 .pull_type[1] = pull1, \ 127 .pull_type[2] = pull2, \ 128 .pull_type[3] = pull3, \ 129 } 130 131 #define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1, \ 132 iom2, iom3, drv0, drv1, drv2, \ 133 drv3, offset0, offset1, \ 134 offset2, offset3) \ 135 { \ 136 .bank_num = id, \ 137 .nr_pins = pins, \ 138 .name = label, \ 139 .iomux = { \ 140 { .type = iom0, .offset = -1 }, \ 141 { .type = iom1, .offset = -1 }, \ 142 { .type = iom2, .offset = -1 }, \ 143 { .type = iom3, .offset = -1 }, \ 144 }, \ 145 .drv = { \ 146 { .drv_type = drv0, .offset = offset0 }, \ 147 { .drv_type = drv1, .offset = offset1 }, \ 148 { .drv_type = drv2, .offset = offset2 }, \ 149 { .drv_type = drv3, .offset = offset3 }, \ 150 }, \ 151 } 152 153 #define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins, \ 154 label, iom0, iom1, iom2, \ 155 iom3, drv0, drv1, drv2, \ 156 drv3, offset0, offset1, \ 157 offset2, offset3, pull0, \ 158 pull1, pull2, pull3) \ 159 { \ 160 .bank_num = id, \ 161 .nr_pins = pins, \ 162 .name = label, \ 163 .iomux = { \ 164 { .type = iom0, .offset = -1 }, \ 165 { .type = iom1, .offset = -1 }, \ 166 { .type = iom2, .offset = -1 }, \ 167 { .type = iom3, .offset = -1 }, \ 168 }, \ 169 .drv = { \ 170 { .drv_type = drv0, .offset = offset0 }, \ 171 { .drv_type = drv1, .offset = offset1 }, \ 172 { .drv_type = drv2, .offset = offset2 }, \ 173 { .drv_type = drv3, .offset = offset3 }, \ 174 }, \ 175 .pull_type[0] = pull0, \ 176 .pull_type[1] = pull1, \ 177 .pull_type[2] = pull2, \ 178 .pull_type[3] = pull3, \ 179 } 180 181 #define PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, FLAG) \ 182 { \ 183 .bank_num = ID, \ 184 .pin = PIN, \ 185 .func = FUNC, \ 186 .route_offset = REG, \ 187 .route_val = VAL, \ 188 .route_location = FLAG, \ 189 } 190 191 #define RK_MUXROUTE_SAME(ID, PIN, FUNC, REG, VAL) \ 192 PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_SAME) 193 194 #define RK_MUXROUTE_GRF(ID, PIN, FUNC, REG, VAL) \ 195 PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_GRF) 196 197 #define RK_MUXROUTE_PMU(ID, PIN, FUNC, REG, VAL) \ 198 PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_PMU) 199 200 static struct regmap_config rockchip_regmap_config = { 201 .reg_bits = 32, 202 .val_bits = 32, 203 .reg_stride = 4, 204 }; 205 206 static inline const struct rockchip_pin_group *pinctrl_name_to_group( 207 const struct rockchip_pinctrl *info, 208 const char *name) 209 { 210 int i; 211 212 for (i = 0; i < info->ngroups; i++) { 213 if (!strcmp(info->groups[i].name, name)) 214 return &info->groups[i]; 215 } 216 217 return NULL; 218 } 219 220 /* 221 * given a pin number that is local to a pin controller, find out the pin bank 222 * and the register base of the pin bank. 223 */ 224 static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info, 225 unsigned pin) 226 { 227 struct rockchip_pin_bank *b = info->ctrl->pin_banks; 228 229 while (pin >= (b->pin_base + b->nr_pins)) 230 b++; 231 232 return b; 233 } 234 235 static struct rockchip_pin_bank *bank_num_to_bank( 236 struct rockchip_pinctrl *info, 237 unsigned num) 238 { 239 struct rockchip_pin_bank *b = info->ctrl->pin_banks; 240 int i; 241 242 for (i = 0; i < info->ctrl->nr_banks; i++, b++) { 243 if (b->bank_num == num) 244 return b; 245 } 246 247 return ERR_PTR(-EINVAL); 248 } 249 250 /* 251 * Pinctrl_ops handling 252 */ 253 254 static int rockchip_get_groups_count(struct pinctrl_dev *pctldev) 255 { 256 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 257 258 return info->ngroups; 259 } 260 261 static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev, 262 unsigned selector) 263 { 264 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 265 266 return info->groups[selector].name; 267 } 268 269 static int rockchip_get_group_pins(struct pinctrl_dev *pctldev, 270 unsigned selector, const unsigned **pins, 271 unsigned *npins) 272 { 273 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 274 275 if (selector >= info->ngroups) 276 return -EINVAL; 277 278 *pins = info->groups[selector].pins; 279 *npins = info->groups[selector].npins; 280 281 return 0; 282 } 283 284 static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev, 285 struct device_node *np, 286 struct pinctrl_map **map, unsigned *num_maps) 287 { 288 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 289 const struct rockchip_pin_group *grp; 290 struct device *dev = info->dev; 291 struct pinctrl_map *new_map; 292 struct device_node *parent; 293 int map_num = 1; 294 int i; 295 296 /* 297 * first find the group of this node and check if we need to create 298 * config maps for pins 299 */ 300 grp = pinctrl_name_to_group(info, np->name); 301 if (!grp) { 302 dev_err(dev, "unable to find group for node %pOFn\n", np); 303 return -EINVAL; 304 } 305 306 map_num += grp->npins; 307 308 new_map = kcalloc(map_num, sizeof(*new_map), GFP_KERNEL); 309 if (!new_map) 310 return -ENOMEM; 311 312 *map = new_map; 313 *num_maps = map_num; 314 315 /* create mux map */ 316 parent = of_get_parent(np); 317 if (!parent) { 318 kfree(new_map); 319 return -EINVAL; 320 } 321 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP; 322 new_map[0].data.mux.function = parent->name; 323 new_map[0].data.mux.group = np->name; 324 of_node_put(parent); 325 326 /* create config map */ 327 new_map++; 328 for (i = 0; i < grp->npins; i++) { 329 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN; 330 new_map[i].data.configs.group_or_pin = 331 pin_get_name(pctldev, grp->pins[i]); 332 new_map[i].data.configs.configs = grp->data[i].configs; 333 new_map[i].data.configs.num_configs = grp->data[i].nconfigs; 334 } 335 336 dev_dbg(dev, "maps: function %s group %s num %d\n", 337 (*map)->data.mux.function, (*map)->data.mux.group, map_num); 338 339 return 0; 340 } 341 342 static void rockchip_dt_free_map(struct pinctrl_dev *pctldev, 343 struct pinctrl_map *map, unsigned num_maps) 344 { 345 kfree(map); 346 } 347 348 static const struct pinctrl_ops rockchip_pctrl_ops = { 349 .get_groups_count = rockchip_get_groups_count, 350 .get_group_name = rockchip_get_group_name, 351 .get_group_pins = rockchip_get_group_pins, 352 .dt_node_to_map = rockchip_dt_node_to_map, 353 .dt_free_map = rockchip_dt_free_map, 354 }; 355 356 /* 357 * Hardware access 358 */ 359 360 static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = { 361 { 362 .num = 1, 363 .pin = 0, 364 .reg = 0x418, 365 .bit = 0, 366 .mask = 0x3 367 }, { 368 .num = 1, 369 .pin = 1, 370 .reg = 0x418, 371 .bit = 2, 372 .mask = 0x3 373 }, { 374 .num = 1, 375 .pin = 2, 376 .reg = 0x418, 377 .bit = 4, 378 .mask = 0x3 379 }, { 380 .num = 1, 381 .pin = 3, 382 .reg = 0x418, 383 .bit = 6, 384 .mask = 0x3 385 }, { 386 .num = 1, 387 .pin = 4, 388 .reg = 0x418, 389 .bit = 8, 390 .mask = 0x3 391 }, { 392 .num = 1, 393 .pin = 5, 394 .reg = 0x418, 395 .bit = 10, 396 .mask = 0x3 397 }, { 398 .num = 1, 399 .pin = 6, 400 .reg = 0x418, 401 .bit = 12, 402 .mask = 0x3 403 }, { 404 .num = 1, 405 .pin = 7, 406 .reg = 0x418, 407 .bit = 14, 408 .mask = 0x3 409 }, { 410 .num = 1, 411 .pin = 8, 412 .reg = 0x41c, 413 .bit = 0, 414 .mask = 0x3 415 }, { 416 .num = 1, 417 .pin = 9, 418 .reg = 0x41c, 419 .bit = 2, 420 .mask = 0x3 421 }, 422 }; 423 424 static struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = { 425 { 426 .num = 2, 427 .pin = 20, 428 .reg = 0xe8, 429 .bit = 0, 430 .mask = 0x7 431 }, { 432 .num = 2, 433 .pin = 21, 434 .reg = 0xe8, 435 .bit = 4, 436 .mask = 0x7 437 }, { 438 .num = 2, 439 .pin = 22, 440 .reg = 0xe8, 441 .bit = 8, 442 .mask = 0x7 443 }, { 444 .num = 2, 445 .pin = 23, 446 .reg = 0xe8, 447 .bit = 12, 448 .mask = 0x7 449 }, { 450 .num = 2, 451 .pin = 24, 452 .reg = 0xd4, 453 .bit = 12, 454 .mask = 0x7 455 }, 456 }; 457 458 static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = { 459 { 460 .num = 1, 461 .pin = 14, 462 .reg = 0x28, 463 .bit = 12, 464 .mask = 0xf 465 }, { 466 .num = 1, 467 .pin = 15, 468 .reg = 0x2c, 469 .bit = 0, 470 .mask = 0x3 471 }, { 472 .num = 1, 473 .pin = 18, 474 .reg = 0x30, 475 .bit = 4, 476 .mask = 0xf 477 }, { 478 .num = 1, 479 .pin = 19, 480 .reg = 0x30, 481 .bit = 8, 482 .mask = 0xf 483 }, { 484 .num = 1, 485 .pin = 20, 486 .reg = 0x30, 487 .bit = 12, 488 .mask = 0xf 489 }, { 490 .num = 1, 491 .pin = 21, 492 .reg = 0x34, 493 .bit = 0, 494 .mask = 0xf 495 }, { 496 .num = 1, 497 .pin = 22, 498 .reg = 0x34, 499 .bit = 4, 500 .mask = 0xf 501 }, { 502 .num = 1, 503 .pin = 23, 504 .reg = 0x34, 505 .bit = 8, 506 .mask = 0xf 507 }, { 508 .num = 3, 509 .pin = 12, 510 .reg = 0x68, 511 .bit = 8, 512 .mask = 0xf 513 }, { 514 .num = 3, 515 .pin = 13, 516 .reg = 0x68, 517 .bit = 12, 518 .mask = 0xf 519 }, { 520 .num = 2, 521 .pin = 2, 522 .reg = 0x608, 523 .bit = 0, 524 .mask = 0x7 525 }, { 526 .num = 2, 527 .pin = 3, 528 .reg = 0x608, 529 .bit = 4, 530 .mask = 0x7 531 }, { 532 .num = 2, 533 .pin = 16, 534 .reg = 0x610, 535 .bit = 8, 536 .mask = 0x7 537 }, { 538 .num = 3, 539 .pin = 10, 540 .reg = 0x610, 541 .bit = 0, 542 .mask = 0x7 543 }, { 544 .num = 3, 545 .pin = 11, 546 .reg = 0x610, 547 .bit = 4, 548 .mask = 0x7 549 }, 550 }; 551 552 static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = { 553 { 554 .num = 2, 555 .pin = 12, 556 .reg = 0x24, 557 .bit = 8, 558 .mask = 0x3 559 }, { 560 .num = 2, 561 .pin = 15, 562 .reg = 0x28, 563 .bit = 0, 564 .mask = 0x7 565 }, { 566 .num = 2, 567 .pin = 23, 568 .reg = 0x30, 569 .bit = 14, 570 .mask = 0x3 571 }, 572 }; 573 574 static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin, 575 int *reg, u8 *bit, int *mask) 576 { 577 struct rockchip_pinctrl *info = bank->drvdata; 578 struct rockchip_pin_ctrl *ctrl = info->ctrl; 579 struct rockchip_mux_recalced_data *data; 580 int i; 581 582 for (i = 0; i < ctrl->niomux_recalced; i++) { 583 data = &ctrl->iomux_recalced[i]; 584 if (data->num == bank->bank_num && 585 data->pin == pin) 586 break; 587 } 588 589 if (i >= ctrl->niomux_recalced) 590 return; 591 592 *reg = data->reg; 593 *mask = data->mask; 594 *bit = data->bit; 595 } 596 597 static struct rockchip_mux_route_data px30_mux_route_data[] = { 598 RK_MUXROUTE_SAME(2, RK_PA0, 1, 0x184, BIT(16 + 7)), /* cif-d2m0 */ 599 RK_MUXROUTE_SAME(3, RK_PA3, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d2m1 */ 600 RK_MUXROUTE_SAME(3, RK_PC6, 2, 0x184, BIT(16 + 8)), /* pdm-m0 */ 601 RK_MUXROUTE_SAME(2, RK_PC6, 1, 0x184, BIT(16 + 8) | BIT(8)), /* pdm-m1 */ 602 RK_MUXROUTE_SAME(1, RK_PD3, 2, 0x184, BIT(16 + 10)), /* uart2-rxm0 */ 603 RK_MUXROUTE_SAME(2, RK_PB6, 2, 0x184, BIT(16 + 10) | BIT(10)), /* uart2-rxm1 */ 604 RK_MUXROUTE_SAME(0, RK_PC1, 2, 0x184, BIT(16 + 9)), /* uart3-rxm0 */ 605 RK_MUXROUTE_SAME(1, RK_PB7, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-rxm1 */ 606 }; 607 608 static struct rockchip_mux_route_data rk3128_mux_route_data[] = { 609 RK_MUXROUTE_SAME(1, RK_PB2, 1, 0x144, BIT(16 + 3) | BIT(16 + 4)), /* spi-0 */ 610 RK_MUXROUTE_SAME(1, RK_PD3, 3, 0x144, BIT(16 + 3) | BIT(16 + 4) | BIT(3)), /* spi-1 */ 611 RK_MUXROUTE_SAME(0, RK_PB5, 2, 0x144, BIT(16 + 3) | BIT(16 + 4) | BIT(4)), /* spi-2 */ 612 RK_MUXROUTE_SAME(1, RK_PA5, 1, 0x144, BIT(16 + 5)), /* i2s-0 */ 613 RK_MUXROUTE_SAME(0, RK_PB6, 1, 0x144, BIT(16 + 5) | BIT(5)), /* i2s-1 */ 614 RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x144, BIT(16 + 6)), /* emmc-0 */ 615 RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x144, BIT(16 + 6) | BIT(6)), /* emmc-1 */ 616 }; 617 618 static struct rockchip_mux_route_data rk3188_mux_route_data[] = { 619 RK_MUXROUTE_SAME(0, RK_PD0, 1, 0xa0, BIT(16 + 11)), /* non-iomuxed emmc/flash pins on flash-dqs */ 620 RK_MUXROUTE_SAME(0, RK_PD0, 2, 0xa0, BIT(16 + 11) | BIT(11)), /* non-iomuxed emmc/flash pins on emmc-clk */ 621 }; 622 623 static struct rockchip_mux_route_data rk3228_mux_route_data[] = { 624 RK_MUXROUTE_SAME(0, RK_PD2, 1, 0x50, BIT(16)), /* pwm0-0 */ 625 RK_MUXROUTE_SAME(3, RK_PC5, 1, 0x50, BIT(16) | BIT(0)), /* pwm0-1 */ 626 RK_MUXROUTE_SAME(0, RK_PD3, 1, 0x50, BIT(16 + 1)), /* pwm1-0 */ 627 RK_MUXROUTE_SAME(0, RK_PD6, 2, 0x50, BIT(16 + 1) | BIT(1)), /* pwm1-1 */ 628 RK_MUXROUTE_SAME(0, RK_PD4, 1, 0x50, BIT(16 + 2)), /* pwm2-0 */ 629 RK_MUXROUTE_SAME(1, RK_PB4, 2, 0x50, BIT(16 + 2) | BIT(2)), /* pwm2-1 */ 630 RK_MUXROUTE_SAME(3, RK_PD2, 1, 0x50, BIT(16 + 3)), /* pwm3-0 */ 631 RK_MUXROUTE_SAME(1, RK_PB3, 2, 0x50, BIT(16 + 3) | BIT(3)), /* pwm3-1 */ 632 RK_MUXROUTE_SAME(1, RK_PA1, 1, 0x50, BIT(16 + 4)), /* sdio-0_d0 */ 633 RK_MUXROUTE_SAME(3, RK_PA2, 1, 0x50, BIT(16 + 4) | BIT(4)), /* sdio-1_d0 */ 634 RK_MUXROUTE_SAME(0, RK_PB5, 2, 0x50, BIT(16 + 5)), /* spi-0_rx */ 635 RK_MUXROUTE_SAME(2, RK_PA0, 2, 0x50, BIT(16 + 5) | BIT(5)), /* spi-1_rx */ 636 RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x50, BIT(16 + 7)), /* emmc-0_cmd */ 637 RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x50, BIT(16 + 7) | BIT(7)), /* emmc-1_cmd */ 638 RK_MUXROUTE_SAME(1, RK_PC3, 2, 0x50, BIT(16 + 8)), /* uart2-0_rx */ 639 RK_MUXROUTE_SAME(1, RK_PB2, 2, 0x50, BIT(16 + 8) | BIT(8)), /* uart2-1_rx */ 640 RK_MUXROUTE_SAME(1, RK_PB2, 1, 0x50, BIT(16 + 11)), /* uart1-0_rx */ 641 RK_MUXROUTE_SAME(3, RK_PB5, 1, 0x50, BIT(16 + 11) | BIT(11)), /* uart1-1_rx */ 642 }; 643 644 static struct rockchip_mux_route_data rk3288_mux_route_data[] = { 645 RK_MUXROUTE_SAME(7, RK_PC0, 2, 0x264, BIT(16 + 12) | BIT(12)), /* edphdmi_cecinoutt1 */ 646 RK_MUXROUTE_SAME(7, RK_PC7, 4, 0x264, BIT(16 + 12)), /* edphdmi_cecinout */ 647 }; 648 649 static struct rockchip_mux_route_data rk3308_mux_route_data[] = { 650 RK_MUXROUTE_SAME(0, RK_PC3, 1, 0x314, BIT(16 + 0) | BIT(0)), /* rtc_clk */ 651 RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x314, BIT(16 + 2) | BIT(16 + 3)), /* uart2_rxm0 */ 652 RK_MUXROUTE_SAME(4, RK_PD2, 2, 0x314, BIT(16 + 2) | BIT(16 + 3) | BIT(2)), /* uart2_rxm1 */ 653 RK_MUXROUTE_SAME(0, RK_PB7, 2, 0x608, BIT(16 + 8) | BIT(16 + 9)), /* i2c3_sdam0 */ 654 RK_MUXROUTE_SAME(3, RK_PB4, 2, 0x608, BIT(16 + 8) | BIT(16 + 9) | BIT(8)), /* i2c3_sdam1 */ 655 RK_MUXROUTE_SAME(2, RK_PA0, 3, 0x608, BIT(16 + 8) | BIT(16 + 9) | BIT(9)), /* i2c3_sdam2 */ 656 RK_MUXROUTE_SAME(1, RK_PA3, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclktxm0 */ 657 RK_MUXROUTE_SAME(1, RK_PA4, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclkrxm0 */ 658 RK_MUXROUTE_SAME(1, RK_PB5, 2, 0x308, BIT(16 + 3) | BIT(3)), /* i2s-8ch-1-sclktxm1 */ 659 RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x308, BIT(16 + 3) | BIT(3)), /* i2s-8ch-1-sclkrxm1 */ 660 RK_MUXROUTE_SAME(1, RK_PA4, 3, 0x308, BIT(16 + 12) | BIT(16 + 13)), /* pdm-clkm0 */ 661 RK_MUXROUTE_SAME(1, RK_PB6, 4, 0x308, BIT(16 + 12) | BIT(16 + 13) | BIT(12)), /* pdm-clkm1 */ 662 RK_MUXROUTE_SAME(2, RK_PA6, 2, 0x308, BIT(16 + 12) | BIT(16 + 13) | BIT(13)), /* pdm-clkm2 */ 663 RK_MUXROUTE_SAME(2, RK_PA4, 3, 0x600, BIT(16 + 2) | BIT(2)), /* pdm-clkm-m2 */ 664 RK_MUXROUTE_SAME(3, RK_PB2, 3, 0x314, BIT(16 + 9)), /* spi1_miso */ 665 RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x314, BIT(16 + 9) | BIT(9)), /* spi1_miso_m1 */ 666 RK_MUXROUTE_SAME(0, RK_PB3, 3, 0x314, BIT(16 + 10) | BIT(16 + 11)), /* owire_m0 */ 667 RK_MUXROUTE_SAME(1, RK_PC6, 7, 0x314, BIT(16 + 10) | BIT(16 + 11) | BIT(10)), /* owire_m1 */ 668 RK_MUXROUTE_SAME(2, RK_PA2, 5, 0x314, BIT(16 + 10) | BIT(16 + 11) | BIT(11)), /* owire_m2 */ 669 RK_MUXROUTE_SAME(0, RK_PB3, 2, 0x314, BIT(16 + 12) | BIT(16 + 13)), /* can_rxd_m0 */ 670 RK_MUXROUTE_SAME(1, RK_PC6, 5, 0x314, BIT(16 + 12) | BIT(16 + 13) | BIT(12)), /* can_rxd_m1 */ 671 RK_MUXROUTE_SAME(2, RK_PA2, 4, 0x314, BIT(16 + 12) | BIT(16 + 13) | BIT(13)), /* can_rxd_m2 */ 672 RK_MUXROUTE_SAME(1, RK_PC4, 3, 0x314, BIT(16 + 14)), /* mac_rxd0_m0 */ 673 RK_MUXROUTE_SAME(4, RK_PA2, 2, 0x314, BIT(16 + 14) | BIT(14)), /* mac_rxd0_m1 */ 674 RK_MUXROUTE_SAME(3, RK_PB4, 4, 0x314, BIT(16 + 15)), /* uart3_rx */ 675 RK_MUXROUTE_SAME(0, RK_PC1, 3, 0x314, BIT(16 + 15) | BIT(15)), /* uart3_rx_m1 */ 676 }; 677 678 static struct rockchip_mux_route_data rk3328_mux_route_data[] = { 679 RK_MUXROUTE_SAME(1, RK_PA1, 2, 0x50, BIT(16) | BIT(16 + 1)), /* uart2dbg_rxm0 */ 680 RK_MUXROUTE_SAME(2, RK_PA1, 1, 0x50, BIT(16) | BIT(16 + 1) | BIT(0)), /* uart2dbg_rxm1 */ 681 RK_MUXROUTE_SAME(1, RK_PB3, 2, 0x50, BIT(16 + 2) | BIT(2)), /* gmac-m1_rxd0 */ 682 RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x50, BIT(16 + 10) | BIT(10)), /* gmac-m1-optimized_rxd3 */ 683 RK_MUXROUTE_SAME(2, RK_PC3, 2, 0x50, BIT(16 + 3)), /* pdm_sdi0m0 */ 684 RK_MUXROUTE_SAME(1, RK_PC7, 3, 0x50, BIT(16 + 3) | BIT(3)), /* pdm_sdi0m1 */ 685 RK_MUXROUTE_SAME(3, RK_PA2, 4, 0x50, BIT(16 + 4) | BIT(16 + 5) | BIT(5)), /* spi_rxdm2 */ 686 RK_MUXROUTE_SAME(1, RK_PD0, 1, 0x50, BIT(16 + 6)), /* i2s2_sdim0 */ 687 RK_MUXROUTE_SAME(3, RK_PA2, 6, 0x50, BIT(16 + 6) | BIT(6)), /* i2s2_sdim1 */ 688 RK_MUXROUTE_SAME(2, RK_PC6, 3, 0x50, BIT(16 + 7) | BIT(7)), /* card_iom1 */ 689 RK_MUXROUTE_SAME(2, RK_PC0, 3, 0x50, BIT(16 + 8) | BIT(8)), /* tsp_d5m1 */ 690 RK_MUXROUTE_SAME(2, RK_PC0, 4, 0x50, BIT(16 + 9) | BIT(9)), /* cif_data5m1 */ 691 }; 692 693 static struct rockchip_mux_route_data rk3399_mux_route_data[] = { 694 RK_MUXROUTE_SAME(4, RK_PB0, 2, 0xe21c, BIT(16 + 10) | BIT(16 + 11)), /* uart2dbga_rx */ 695 RK_MUXROUTE_SAME(4, RK_PC0, 2, 0xe21c, BIT(16 + 10) | BIT(16 + 11) | BIT(10)), /* uart2dbgb_rx */ 696 RK_MUXROUTE_SAME(4, RK_PC3, 1, 0xe21c, BIT(16 + 10) | BIT(16 + 11) | BIT(11)), /* uart2dbgc_rx */ 697 RK_MUXROUTE_SAME(2, RK_PD2, 2, 0xe21c, BIT(16 + 14)), /* pcie_clkreqn */ 698 RK_MUXROUTE_SAME(4, RK_PD0, 1, 0xe21c, BIT(16 + 14) | BIT(14)), /* pcie_clkreqnb */ 699 }; 700 701 static struct rockchip_mux_route_data rk3568_mux_route_data[] = { 702 RK_MUXROUTE_PMU(0, RK_PB7, 1, 0x0110, WRITE_MASK_VAL(1, 0, 0)), /* PWM0 IO mux M0 */ 703 RK_MUXROUTE_PMU(0, RK_PC7, 2, 0x0110, WRITE_MASK_VAL(1, 0, 1)), /* PWM0 IO mux M1 */ 704 RK_MUXROUTE_PMU(0, RK_PC0, 1, 0x0110, WRITE_MASK_VAL(3, 2, 0)), /* PWM1 IO mux M0 */ 705 RK_MUXROUTE_PMU(0, RK_PB5, 4, 0x0110, WRITE_MASK_VAL(3, 2, 1)), /* PWM1 IO mux M1 */ 706 RK_MUXROUTE_PMU(0, RK_PC1, 1, 0x0110, WRITE_MASK_VAL(5, 4, 0)), /* PWM2 IO mux M0 */ 707 RK_MUXROUTE_PMU(0, RK_PB6, 4, 0x0110, WRITE_MASK_VAL(5, 4, 1)), /* PWM2 IO mux M1 */ 708 RK_MUXROUTE_PMU(0, RK_PB3, 2, 0x0300, WRITE_MASK_VAL(0, 0, 0)), /* CAN0 IO mux M0 */ 709 RK_MUXROUTE_GRF(2, RK_PA1, 4, 0x0300, WRITE_MASK_VAL(0, 0, 1)), /* CAN0 IO mux M1 */ 710 RK_MUXROUTE_GRF(1, RK_PA1, 3, 0x0300, WRITE_MASK_VAL(2, 2, 0)), /* CAN1 IO mux M0 */ 711 RK_MUXROUTE_GRF(4, RK_PC3, 3, 0x0300, WRITE_MASK_VAL(2, 2, 1)), /* CAN1 IO mux M1 */ 712 RK_MUXROUTE_GRF(4, RK_PB5, 3, 0x0300, WRITE_MASK_VAL(4, 4, 0)), /* CAN2 IO mux M0 */ 713 RK_MUXROUTE_GRF(2, RK_PB2, 4, 0x0300, WRITE_MASK_VAL(4, 4, 1)), /* CAN2 IO mux M1 */ 714 RK_MUXROUTE_GRF(4, RK_PC4, 1, 0x0300, WRITE_MASK_VAL(6, 6, 0)), /* HPDIN IO mux M0 */ 715 RK_MUXROUTE_PMU(0, RK_PC2, 2, 0x0300, WRITE_MASK_VAL(6, 6, 1)), /* HPDIN IO mux M1 */ 716 RK_MUXROUTE_GRF(3, RK_PB1, 3, 0x0300, WRITE_MASK_VAL(8, 8, 0)), /* GMAC1 IO mux M0 */ 717 RK_MUXROUTE_GRF(4, RK_PA7, 3, 0x0300, WRITE_MASK_VAL(8, 8, 1)), /* GMAC1 IO mux M1 */ 718 RK_MUXROUTE_GRF(4, RK_PD1, 1, 0x0300, WRITE_MASK_VAL(10, 10, 0)), /* HDMITX IO mux M0 */ 719 RK_MUXROUTE_PMU(0, RK_PC7, 1, 0x0300, WRITE_MASK_VAL(10, 10, 1)), /* HDMITX IO mux M1 */ 720 RK_MUXROUTE_PMU(0, RK_PB6, 1, 0x0300, WRITE_MASK_VAL(14, 14, 0)), /* I2C2 IO mux M0 */ 721 RK_MUXROUTE_GRF(4, RK_PB4, 1, 0x0300, WRITE_MASK_VAL(14, 14, 1)), /* I2C2 IO mux M1 */ 722 RK_MUXROUTE_GRF(1, RK_PA0, 1, 0x0304, WRITE_MASK_VAL(0, 0, 0)), /* I2C3 IO mux M0 */ 723 RK_MUXROUTE_GRF(3, RK_PB6, 4, 0x0304, WRITE_MASK_VAL(0, 0, 1)), /* I2C3 IO mux M1 */ 724 RK_MUXROUTE_GRF(4, RK_PB2, 1, 0x0304, WRITE_MASK_VAL(2, 2, 0)), /* I2C4 IO mux M0 */ 725 RK_MUXROUTE_GRF(2, RK_PB1, 2, 0x0304, WRITE_MASK_VAL(2, 2, 1)), /* I2C4 IO mux M1 */ 726 RK_MUXROUTE_GRF(3, RK_PB4, 4, 0x0304, WRITE_MASK_VAL(4, 4, 0)), /* I2C5 IO mux M0 */ 727 RK_MUXROUTE_GRF(4, RK_PD0, 2, 0x0304, WRITE_MASK_VAL(4, 4, 1)), /* I2C5 IO mux M1 */ 728 RK_MUXROUTE_GRF(3, RK_PB1, 5, 0x0304, WRITE_MASK_VAL(14, 14, 0)), /* PWM8 IO mux M0 */ 729 RK_MUXROUTE_GRF(1, RK_PD5, 4, 0x0304, WRITE_MASK_VAL(14, 14, 1)), /* PWM8 IO mux M1 */ 730 RK_MUXROUTE_GRF(3, RK_PB2, 5, 0x0308, WRITE_MASK_VAL(0, 0, 0)), /* PWM9 IO mux M0 */ 731 RK_MUXROUTE_GRF(1, RK_PD6, 4, 0x0308, WRITE_MASK_VAL(0, 0, 1)), /* PWM9 IO mux M1 */ 732 RK_MUXROUTE_GRF(3, RK_PB5, 5, 0x0308, WRITE_MASK_VAL(2, 2, 0)), /* PWM10 IO mux M0 */ 733 RK_MUXROUTE_GRF(2, RK_PA1, 2, 0x0308, WRITE_MASK_VAL(2, 2, 1)), /* PWM10 IO mux M1 */ 734 RK_MUXROUTE_GRF(3, RK_PB6, 5, 0x0308, WRITE_MASK_VAL(4, 4, 0)), /* PWM11 IO mux M0 */ 735 RK_MUXROUTE_GRF(4, RK_PC0, 3, 0x0308, WRITE_MASK_VAL(4, 4, 1)), /* PWM11 IO mux M1 */ 736 RK_MUXROUTE_GRF(3, RK_PB7, 2, 0x0308, WRITE_MASK_VAL(6, 6, 0)), /* PWM12 IO mux M0 */ 737 RK_MUXROUTE_GRF(4, RK_PC5, 1, 0x0308, WRITE_MASK_VAL(6, 6, 1)), /* PWM12 IO mux M1 */ 738 RK_MUXROUTE_GRF(3, RK_PC0, 2, 0x0308, WRITE_MASK_VAL(8, 8, 0)), /* PWM13 IO mux M0 */ 739 RK_MUXROUTE_GRF(4, RK_PC6, 1, 0x0308, WRITE_MASK_VAL(8, 8, 1)), /* PWM13 IO mux M1 */ 740 RK_MUXROUTE_GRF(3, RK_PC4, 1, 0x0308, WRITE_MASK_VAL(10, 10, 0)), /* PWM14 IO mux M0 */ 741 RK_MUXROUTE_GRF(4, RK_PC2, 1, 0x0308, WRITE_MASK_VAL(10, 10, 1)), /* PWM14 IO mux M1 */ 742 RK_MUXROUTE_GRF(3, RK_PC5, 1, 0x0308, WRITE_MASK_VAL(12, 12, 0)), /* PWM15 IO mux M0 */ 743 RK_MUXROUTE_GRF(4, RK_PC3, 1, 0x0308, WRITE_MASK_VAL(12, 12, 1)), /* PWM15 IO mux M1 */ 744 RK_MUXROUTE_GRF(3, RK_PD2, 3, 0x0308, WRITE_MASK_VAL(14, 14, 0)), /* SDMMC2 IO mux M0 */ 745 RK_MUXROUTE_GRF(3, RK_PA5, 5, 0x0308, WRITE_MASK_VAL(14, 14, 1)), /* SDMMC2 IO mux M1 */ 746 RK_MUXROUTE_PMU(0, RK_PB5, 2, 0x030c, WRITE_MASK_VAL(0, 0, 0)), /* SPI0 IO mux M0 */ 747 RK_MUXROUTE_GRF(2, RK_PD3, 3, 0x030c, WRITE_MASK_VAL(0, 0, 1)), /* SPI0 IO mux M1 */ 748 RK_MUXROUTE_GRF(2, RK_PB5, 3, 0x030c, WRITE_MASK_VAL(2, 2, 0)), /* SPI1 IO mux M0 */ 749 RK_MUXROUTE_GRF(3, RK_PC3, 3, 0x030c, WRITE_MASK_VAL(2, 2, 1)), /* SPI1 IO mux M1 */ 750 RK_MUXROUTE_GRF(2, RK_PC1, 4, 0x030c, WRITE_MASK_VAL(4, 4, 0)), /* SPI2 IO mux M0 */ 751 RK_MUXROUTE_GRF(3, RK_PA0, 3, 0x030c, WRITE_MASK_VAL(4, 4, 1)), /* SPI2 IO mux M1 */ 752 RK_MUXROUTE_GRF(4, RK_PB3, 4, 0x030c, WRITE_MASK_VAL(6, 6, 0)), /* SPI3 IO mux M0 */ 753 RK_MUXROUTE_GRF(4, RK_PC2, 2, 0x030c, WRITE_MASK_VAL(6, 6, 1)), /* SPI3 IO mux M1 */ 754 RK_MUXROUTE_GRF(2, RK_PB4, 2, 0x030c, WRITE_MASK_VAL(8, 8, 0)), /* UART1 IO mux M0 */ 755 RK_MUXROUTE_PMU(0, RK_PD1, 1, 0x030c, WRITE_MASK_VAL(8, 8, 1)), /* UART1 IO mux M1 */ 756 RK_MUXROUTE_PMU(0, RK_PD1, 1, 0x030c, WRITE_MASK_VAL(10, 10, 0)), /* UART2 IO mux M0 */ 757 RK_MUXROUTE_GRF(1, RK_PD5, 2, 0x030c, WRITE_MASK_VAL(10, 10, 1)), /* UART2 IO mux M1 */ 758 RK_MUXROUTE_GRF(1, RK_PA1, 2, 0x030c, WRITE_MASK_VAL(12, 12, 0)), /* UART3 IO mux M0 */ 759 RK_MUXROUTE_GRF(3, RK_PB7, 4, 0x030c, WRITE_MASK_VAL(12, 12, 1)), /* UART3 IO mux M1 */ 760 RK_MUXROUTE_GRF(1, RK_PA6, 2, 0x030c, WRITE_MASK_VAL(14, 14, 0)), /* UART4 IO mux M0 */ 761 RK_MUXROUTE_GRF(3, RK_PB2, 4, 0x030c, WRITE_MASK_VAL(14, 14, 1)), /* UART4 IO mux M1 */ 762 RK_MUXROUTE_GRF(2, RK_PA2, 3, 0x0310, WRITE_MASK_VAL(0, 0, 0)), /* UART5 IO mux M0 */ 763 RK_MUXROUTE_GRF(3, RK_PC2, 4, 0x0310, WRITE_MASK_VAL(0, 0, 1)), /* UART5 IO mux M1 */ 764 RK_MUXROUTE_GRF(2, RK_PA4, 3, 0x0310, WRITE_MASK_VAL(2, 2, 0)), /* UART6 IO mux M0 */ 765 RK_MUXROUTE_GRF(1, RK_PD5, 3, 0x0310, WRITE_MASK_VAL(2, 2, 1)), /* UART6 IO mux M1 */ 766 RK_MUXROUTE_GRF(2, RK_PA6, 3, 0x0310, WRITE_MASK_VAL(5, 4, 0)), /* UART7 IO mux M0 */ 767 RK_MUXROUTE_GRF(3, RK_PC4, 4, 0x0310, WRITE_MASK_VAL(5, 4, 1)), /* UART7 IO mux M1 */ 768 RK_MUXROUTE_GRF(4, RK_PA2, 4, 0x0310, WRITE_MASK_VAL(5, 4, 2)), /* UART7 IO mux M2 */ 769 RK_MUXROUTE_GRF(2, RK_PC5, 3, 0x0310, WRITE_MASK_VAL(6, 6, 0)), /* UART8 IO mux M0 */ 770 RK_MUXROUTE_GRF(2, RK_PD7, 4, 0x0310, WRITE_MASK_VAL(6, 6, 1)), /* UART8 IO mux M1 */ 771 RK_MUXROUTE_GRF(2, RK_PB0, 3, 0x0310, WRITE_MASK_VAL(9, 8, 0)), /* UART9 IO mux M0 */ 772 RK_MUXROUTE_GRF(4, RK_PC5, 4, 0x0310, WRITE_MASK_VAL(9, 8, 1)), /* UART9 IO mux M1 */ 773 RK_MUXROUTE_GRF(4, RK_PA4, 4, 0x0310, WRITE_MASK_VAL(9, 8, 2)), /* UART9 IO mux M2 */ 774 RK_MUXROUTE_GRF(1, RK_PA2, 1, 0x0310, WRITE_MASK_VAL(11, 10, 0)), /* I2S1 IO mux M0 */ 775 RK_MUXROUTE_GRF(3, RK_PC6, 4, 0x0310, WRITE_MASK_VAL(11, 10, 1)), /* I2S1 IO mux M1 */ 776 RK_MUXROUTE_GRF(2, RK_PD0, 5, 0x0310, WRITE_MASK_VAL(11, 10, 2)), /* I2S1 IO mux M2 */ 777 RK_MUXROUTE_GRF(2, RK_PC1, 1, 0x0310, WRITE_MASK_VAL(12, 12, 0)), /* I2S2 IO mux M0 */ 778 RK_MUXROUTE_GRF(4, RK_PB6, 5, 0x0310, WRITE_MASK_VAL(12, 12, 1)), /* I2S2 IO mux M1 */ 779 RK_MUXROUTE_GRF(3, RK_PA2, 4, 0x0310, WRITE_MASK_VAL(14, 14, 0)), /* I2S3 IO mux M0 */ 780 RK_MUXROUTE_GRF(4, RK_PC2, 5, 0x0310, WRITE_MASK_VAL(14, 14, 1)), /* I2S3 IO mux M1 */ 781 RK_MUXROUTE_GRF(1, RK_PA4, 3, 0x0314, WRITE_MASK_VAL(1, 0, 0)), /* PDM IO mux M0 */ 782 RK_MUXROUTE_GRF(1, RK_PA6, 3, 0x0314, WRITE_MASK_VAL(1, 0, 0)), /* PDM IO mux M0 */ 783 RK_MUXROUTE_GRF(3, RK_PD6, 5, 0x0314, WRITE_MASK_VAL(1, 0, 1)), /* PDM IO mux M1 */ 784 RK_MUXROUTE_GRF(4, RK_PA0, 4, 0x0314, WRITE_MASK_VAL(1, 0, 1)), /* PDM IO mux M1 */ 785 RK_MUXROUTE_GRF(3, RK_PC4, 5, 0x0314, WRITE_MASK_VAL(1, 0, 2)), /* PDM IO mux M2 */ 786 RK_MUXROUTE_PMU(0, RK_PA5, 3, 0x0314, WRITE_MASK_VAL(3, 2, 0)), /* PCIE20 IO mux M0 */ 787 RK_MUXROUTE_GRF(2, RK_PD0, 4, 0x0314, WRITE_MASK_VAL(3, 2, 1)), /* PCIE20 IO mux M1 */ 788 RK_MUXROUTE_GRF(1, RK_PB0, 4, 0x0314, WRITE_MASK_VAL(3, 2, 2)), /* PCIE20 IO mux M2 */ 789 RK_MUXROUTE_PMU(0, RK_PA4, 3, 0x0314, WRITE_MASK_VAL(5, 4, 0)), /* PCIE30X1 IO mux M0 */ 790 RK_MUXROUTE_GRF(2, RK_PD2, 4, 0x0314, WRITE_MASK_VAL(5, 4, 1)), /* PCIE30X1 IO mux M1 */ 791 RK_MUXROUTE_GRF(1, RK_PA5, 4, 0x0314, WRITE_MASK_VAL(5, 4, 2)), /* PCIE30X1 IO mux M2 */ 792 RK_MUXROUTE_PMU(0, RK_PA6, 2, 0x0314, WRITE_MASK_VAL(7, 6, 0)), /* PCIE30X2 IO mux M0 */ 793 RK_MUXROUTE_GRF(2, RK_PD4, 4, 0x0314, WRITE_MASK_VAL(7, 6, 1)), /* PCIE30X2 IO mux M1 */ 794 RK_MUXROUTE_GRF(4, RK_PC2, 4, 0x0314, WRITE_MASK_VAL(7, 6, 2)), /* PCIE30X2 IO mux M2 */ 795 }; 796 797 static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin, 798 int mux, u32 *loc, u32 *reg, u32 *value) 799 { 800 struct rockchip_pinctrl *info = bank->drvdata; 801 struct rockchip_pin_ctrl *ctrl = info->ctrl; 802 struct rockchip_mux_route_data *data; 803 int i; 804 805 for (i = 0; i < ctrl->niomux_routes; i++) { 806 data = &ctrl->iomux_routes[i]; 807 if ((data->bank_num == bank->bank_num) && 808 (data->pin == pin) && (data->func == mux)) 809 break; 810 } 811 812 if (i >= ctrl->niomux_routes) 813 return false; 814 815 *loc = data->route_location; 816 *reg = data->route_offset; 817 *value = data->route_val; 818 819 return true; 820 } 821 822 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) 823 { 824 struct rockchip_pinctrl *info = bank->drvdata; 825 int iomux_num = (pin / 8); 826 struct regmap *regmap; 827 unsigned int val; 828 int reg, ret, mask, mux_type; 829 u8 bit; 830 831 if (iomux_num > 3) 832 return -EINVAL; 833 834 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { 835 dev_err(info->dev, "pin %d is unrouted\n", pin); 836 return -EINVAL; 837 } 838 839 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) 840 return RK_FUNC_GPIO; 841 842 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) 843 ? info->regmap_pmu : info->regmap_base; 844 845 /* get basic quadrupel of mux registers and the correct reg inside */ 846 mux_type = bank->iomux[iomux_num].type; 847 reg = bank->iomux[iomux_num].offset; 848 if (mux_type & IOMUX_WIDTH_4BIT) { 849 if ((pin % 8) >= 4) 850 reg += 0x4; 851 bit = (pin % 4) * 4; 852 mask = 0xf; 853 } else if (mux_type & IOMUX_WIDTH_3BIT) { 854 if ((pin % 8) >= 5) 855 reg += 0x4; 856 bit = (pin % 8 % 5) * 3; 857 mask = 0x7; 858 } else { 859 bit = (pin % 8) * 2; 860 mask = 0x3; 861 } 862 863 if (bank->recalced_mask & BIT(pin)) 864 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); 865 866 ret = regmap_read(regmap, reg, &val); 867 if (ret) 868 return ret; 869 870 return ((val >> bit) & mask); 871 } 872 873 static int rockchip_verify_mux(struct rockchip_pin_bank *bank, 874 int pin, int mux) 875 { 876 struct rockchip_pinctrl *info = bank->drvdata; 877 struct device *dev = info->dev; 878 int iomux_num = (pin / 8); 879 880 if (iomux_num > 3) 881 return -EINVAL; 882 883 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { 884 dev_err(dev, "pin %d is unrouted\n", pin); 885 return -EINVAL; 886 } 887 888 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) { 889 if (mux != RK_FUNC_GPIO) { 890 dev_err(dev, "pin %d only supports a gpio mux\n", pin); 891 return -ENOTSUPP; 892 } 893 } 894 895 return 0; 896 } 897 898 /* 899 * Set a new mux function for a pin. 900 * 901 * The register is divided into the upper and lower 16 bit. When changing 902 * a value, the previous register value is not read and changed. Instead 903 * it seems the changed bits are marked in the upper 16 bit, while the 904 * changed value gets set in the same offset in the lower 16 bit. 905 * All pin settings seem to be 2 bit wide in both the upper and lower 906 * parts. 907 * @bank: pin bank to change 908 * @pin: pin to change 909 * @mux: new mux function to set 910 */ 911 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) 912 { 913 struct rockchip_pinctrl *info = bank->drvdata; 914 struct device *dev = info->dev; 915 int iomux_num = (pin / 8); 916 struct regmap *regmap; 917 int reg, ret, mask, mux_type; 918 u8 bit; 919 u32 data, rmask, route_location, route_reg, route_val; 920 921 ret = rockchip_verify_mux(bank, pin, mux); 922 if (ret < 0) 923 return ret; 924 925 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) 926 return 0; 927 928 dev_dbg(dev, "setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux); 929 930 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) 931 ? info->regmap_pmu : info->regmap_base; 932 933 /* get basic quadrupel of mux registers and the correct reg inside */ 934 mux_type = bank->iomux[iomux_num].type; 935 reg = bank->iomux[iomux_num].offset; 936 if (mux_type & IOMUX_WIDTH_4BIT) { 937 if ((pin % 8) >= 4) 938 reg += 0x4; 939 bit = (pin % 4) * 4; 940 mask = 0xf; 941 } else if (mux_type & IOMUX_WIDTH_3BIT) { 942 if ((pin % 8) >= 5) 943 reg += 0x4; 944 bit = (pin % 8 % 5) * 3; 945 mask = 0x7; 946 } else { 947 bit = (pin % 8) * 2; 948 mask = 0x3; 949 } 950 951 if (bank->recalced_mask & BIT(pin)) 952 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); 953 954 if (bank->route_mask & BIT(pin)) { 955 if (rockchip_get_mux_route(bank, pin, mux, &route_location, 956 &route_reg, &route_val)) { 957 struct regmap *route_regmap = regmap; 958 959 /* handle special locations */ 960 switch (route_location) { 961 case ROCKCHIP_ROUTE_PMU: 962 route_regmap = info->regmap_pmu; 963 break; 964 case ROCKCHIP_ROUTE_GRF: 965 route_regmap = info->regmap_base; 966 break; 967 } 968 969 ret = regmap_write(route_regmap, route_reg, route_val); 970 if (ret) 971 return ret; 972 } 973 } 974 975 data = (mask << (bit + 16)); 976 rmask = data | (data >> 16); 977 data |= (mux & mask) << bit; 978 ret = regmap_update_bits(regmap, reg, rmask, data); 979 980 return ret; 981 } 982 983 #define PX30_PULL_PMU_OFFSET 0x10 984 #define PX30_PULL_GRF_OFFSET 0x60 985 #define PX30_PULL_BITS_PER_PIN 2 986 #define PX30_PULL_PINS_PER_REG 8 987 #define PX30_PULL_BANK_STRIDE 16 988 989 static void px30_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 990 int pin_num, struct regmap **regmap, 991 int *reg, u8 *bit) 992 { 993 struct rockchip_pinctrl *info = bank->drvdata; 994 995 /* The first 32 pins of the first bank are located in PMU */ 996 if (bank->bank_num == 0) { 997 *regmap = info->regmap_pmu; 998 *reg = PX30_PULL_PMU_OFFSET; 999 } else { 1000 *regmap = info->regmap_base; 1001 *reg = PX30_PULL_GRF_OFFSET; 1002 1003 /* correct the offset, as we're starting with the 2nd bank */ 1004 *reg -= 0x10; 1005 *reg += bank->bank_num * PX30_PULL_BANK_STRIDE; 1006 } 1007 1008 *reg += ((pin_num / PX30_PULL_PINS_PER_REG) * 4); 1009 *bit = (pin_num % PX30_PULL_PINS_PER_REG); 1010 *bit *= PX30_PULL_BITS_PER_PIN; 1011 } 1012 1013 #define PX30_DRV_PMU_OFFSET 0x20 1014 #define PX30_DRV_GRF_OFFSET 0xf0 1015 #define PX30_DRV_BITS_PER_PIN 2 1016 #define PX30_DRV_PINS_PER_REG 8 1017 #define PX30_DRV_BANK_STRIDE 16 1018 1019 static void px30_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1020 int pin_num, struct regmap **regmap, 1021 int *reg, u8 *bit) 1022 { 1023 struct rockchip_pinctrl *info = bank->drvdata; 1024 1025 /* The first 32 pins of the first bank are located in PMU */ 1026 if (bank->bank_num == 0) { 1027 *regmap = info->regmap_pmu; 1028 *reg = PX30_DRV_PMU_OFFSET; 1029 } else { 1030 *regmap = info->regmap_base; 1031 *reg = PX30_DRV_GRF_OFFSET; 1032 1033 /* correct the offset, as we're starting with the 2nd bank */ 1034 *reg -= 0x10; 1035 *reg += bank->bank_num * PX30_DRV_BANK_STRIDE; 1036 } 1037 1038 *reg += ((pin_num / PX30_DRV_PINS_PER_REG) * 4); 1039 *bit = (pin_num % PX30_DRV_PINS_PER_REG); 1040 *bit *= PX30_DRV_BITS_PER_PIN; 1041 } 1042 1043 #define PX30_SCHMITT_PMU_OFFSET 0x38 1044 #define PX30_SCHMITT_GRF_OFFSET 0xc0 1045 #define PX30_SCHMITT_PINS_PER_PMU_REG 16 1046 #define PX30_SCHMITT_BANK_STRIDE 16 1047 #define PX30_SCHMITT_PINS_PER_GRF_REG 8 1048 1049 static int px30_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1050 int pin_num, 1051 struct regmap **regmap, 1052 int *reg, u8 *bit) 1053 { 1054 struct rockchip_pinctrl *info = bank->drvdata; 1055 int pins_per_reg; 1056 1057 if (bank->bank_num == 0) { 1058 *regmap = info->regmap_pmu; 1059 *reg = PX30_SCHMITT_PMU_OFFSET; 1060 pins_per_reg = PX30_SCHMITT_PINS_PER_PMU_REG; 1061 } else { 1062 *regmap = info->regmap_base; 1063 *reg = PX30_SCHMITT_GRF_OFFSET; 1064 pins_per_reg = PX30_SCHMITT_PINS_PER_GRF_REG; 1065 *reg += (bank->bank_num - 1) * PX30_SCHMITT_BANK_STRIDE; 1066 } 1067 1068 *reg += ((pin_num / pins_per_reg) * 4); 1069 *bit = pin_num % pins_per_reg; 1070 1071 return 0; 1072 } 1073 1074 #define RV1108_PULL_PMU_OFFSET 0x10 1075 #define RV1108_PULL_OFFSET 0x110 1076 #define RV1108_PULL_PINS_PER_REG 8 1077 #define RV1108_PULL_BITS_PER_PIN 2 1078 #define RV1108_PULL_BANK_STRIDE 16 1079 1080 static void rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1081 int pin_num, struct regmap **regmap, 1082 int *reg, u8 *bit) 1083 { 1084 struct rockchip_pinctrl *info = bank->drvdata; 1085 1086 /* The first 24 pins of the first bank are located in PMU */ 1087 if (bank->bank_num == 0) { 1088 *regmap = info->regmap_pmu; 1089 *reg = RV1108_PULL_PMU_OFFSET; 1090 } else { 1091 *reg = RV1108_PULL_OFFSET; 1092 *regmap = info->regmap_base; 1093 /* correct the offset, as we're starting with the 2nd bank */ 1094 *reg -= 0x10; 1095 *reg += bank->bank_num * RV1108_PULL_BANK_STRIDE; 1096 } 1097 1098 *reg += ((pin_num / RV1108_PULL_PINS_PER_REG) * 4); 1099 *bit = (pin_num % RV1108_PULL_PINS_PER_REG); 1100 *bit *= RV1108_PULL_BITS_PER_PIN; 1101 } 1102 1103 #define RV1108_DRV_PMU_OFFSET 0x20 1104 #define RV1108_DRV_GRF_OFFSET 0x210 1105 #define RV1108_DRV_BITS_PER_PIN 2 1106 #define RV1108_DRV_PINS_PER_REG 8 1107 #define RV1108_DRV_BANK_STRIDE 16 1108 1109 static void rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1110 int pin_num, struct regmap **regmap, 1111 int *reg, u8 *bit) 1112 { 1113 struct rockchip_pinctrl *info = bank->drvdata; 1114 1115 /* The first 24 pins of the first bank are located in PMU */ 1116 if (bank->bank_num == 0) { 1117 *regmap = info->regmap_pmu; 1118 *reg = RV1108_DRV_PMU_OFFSET; 1119 } else { 1120 *regmap = info->regmap_base; 1121 *reg = RV1108_DRV_GRF_OFFSET; 1122 1123 /* correct the offset, as we're starting with the 2nd bank */ 1124 *reg -= 0x10; 1125 *reg += bank->bank_num * RV1108_DRV_BANK_STRIDE; 1126 } 1127 1128 *reg += ((pin_num / RV1108_DRV_PINS_PER_REG) * 4); 1129 *bit = pin_num % RV1108_DRV_PINS_PER_REG; 1130 *bit *= RV1108_DRV_BITS_PER_PIN; 1131 } 1132 1133 #define RV1108_SCHMITT_PMU_OFFSET 0x30 1134 #define RV1108_SCHMITT_GRF_OFFSET 0x388 1135 #define RV1108_SCHMITT_BANK_STRIDE 8 1136 #define RV1108_SCHMITT_PINS_PER_GRF_REG 16 1137 #define RV1108_SCHMITT_PINS_PER_PMU_REG 8 1138 1139 static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1140 int pin_num, 1141 struct regmap **regmap, 1142 int *reg, u8 *bit) 1143 { 1144 struct rockchip_pinctrl *info = bank->drvdata; 1145 int pins_per_reg; 1146 1147 if (bank->bank_num == 0) { 1148 *regmap = info->regmap_pmu; 1149 *reg = RV1108_SCHMITT_PMU_OFFSET; 1150 pins_per_reg = RV1108_SCHMITT_PINS_PER_PMU_REG; 1151 } else { 1152 *regmap = info->regmap_base; 1153 *reg = RV1108_SCHMITT_GRF_OFFSET; 1154 pins_per_reg = RV1108_SCHMITT_PINS_PER_GRF_REG; 1155 *reg += (bank->bank_num - 1) * RV1108_SCHMITT_BANK_STRIDE; 1156 } 1157 *reg += ((pin_num / pins_per_reg) * 4); 1158 *bit = pin_num % pins_per_reg; 1159 1160 return 0; 1161 } 1162 1163 #define RK3308_SCHMITT_PINS_PER_REG 8 1164 #define RK3308_SCHMITT_BANK_STRIDE 16 1165 #define RK3308_SCHMITT_GRF_OFFSET 0x1a0 1166 1167 static int rk3308_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1168 int pin_num, struct regmap **regmap, 1169 int *reg, u8 *bit) 1170 { 1171 struct rockchip_pinctrl *info = bank->drvdata; 1172 1173 *regmap = info->regmap_base; 1174 *reg = RK3308_SCHMITT_GRF_OFFSET; 1175 1176 *reg += bank->bank_num * RK3308_SCHMITT_BANK_STRIDE; 1177 *reg += ((pin_num / RK3308_SCHMITT_PINS_PER_REG) * 4); 1178 *bit = pin_num % RK3308_SCHMITT_PINS_PER_REG; 1179 1180 return 0; 1181 } 1182 1183 #define RK2928_PULL_OFFSET 0x118 1184 #define RK2928_PULL_PINS_PER_REG 16 1185 #define RK2928_PULL_BANK_STRIDE 8 1186 1187 static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1188 int pin_num, struct regmap **regmap, 1189 int *reg, u8 *bit) 1190 { 1191 struct rockchip_pinctrl *info = bank->drvdata; 1192 1193 *regmap = info->regmap_base; 1194 *reg = RK2928_PULL_OFFSET; 1195 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; 1196 *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4; 1197 1198 *bit = pin_num % RK2928_PULL_PINS_PER_REG; 1199 }; 1200 1201 #define RK3128_PULL_OFFSET 0x118 1202 1203 static void rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1204 int pin_num, struct regmap **regmap, 1205 int *reg, u8 *bit) 1206 { 1207 struct rockchip_pinctrl *info = bank->drvdata; 1208 1209 *regmap = info->regmap_base; 1210 *reg = RK3128_PULL_OFFSET; 1211 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; 1212 *reg += ((pin_num / RK2928_PULL_PINS_PER_REG) * 4); 1213 1214 *bit = pin_num % RK2928_PULL_PINS_PER_REG; 1215 } 1216 1217 #define RK3188_PULL_OFFSET 0x164 1218 #define RK3188_PULL_BITS_PER_PIN 2 1219 #define RK3188_PULL_PINS_PER_REG 8 1220 #define RK3188_PULL_BANK_STRIDE 16 1221 #define RK3188_PULL_PMU_OFFSET 0x64 1222 1223 static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1224 int pin_num, struct regmap **regmap, 1225 int *reg, u8 *bit) 1226 { 1227 struct rockchip_pinctrl *info = bank->drvdata; 1228 1229 /* The first 12 pins of the first bank are located elsewhere */ 1230 if (bank->bank_num == 0 && pin_num < 12) { 1231 *regmap = info->regmap_pmu ? info->regmap_pmu 1232 : bank->regmap_pull; 1233 *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0; 1234 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1235 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 1236 *bit *= RK3188_PULL_BITS_PER_PIN; 1237 } else { 1238 *regmap = info->regmap_pull ? info->regmap_pull 1239 : info->regmap_base; 1240 *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET; 1241 1242 /* correct the offset, as it is the 2nd pull register */ 1243 *reg -= 4; 1244 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1245 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1246 1247 /* 1248 * The bits in these registers have an inverse ordering 1249 * with the lowest pin being in bits 15:14 and the highest 1250 * pin in bits 1:0 1251 */ 1252 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG); 1253 *bit *= RK3188_PULL_BITS_PER_PIN; 1254 } 1255 } 1256 1257 #define RK3288_PULL_OFFSET 0x140 1258 static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1259 int pin_num, struct regmap **regmap, 1260 int *reg, u8 *bit) 1261 { 1262 struct rockchip_pinctrl *info = bank->drvdata; 1263 1264 /* The first 24 pins of the first bank are located in PMU */ 1265 if (bank->bank_num == 0) { 1266 *regmap = info->regmap_pmu; 1267 *reg = RK3188_PULL_PMU_OFFSET; 1268 1269 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1270 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 1271 *bit *= RK3188_PULL_BITS_PER_PIN; 1272 } else { 1273 *regmap = info->regmap_base; 1274 *reg = RK3288_PULL_OFFSET; 1275 1276 /* correct the offset, as we're starting with the 2nd bank */ 1277 *reg -= 0x10; 1278 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1279 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1280 1281 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1282 *bit *= RK3188_PULL_BITS_PER_PIN; 1283 } 1284 } 1285 1286 #define RK3288_DRV_PMU_OFFSET 0x70 1287 #define RK3288_DRV_GRF_OFFSET 0x1c0 1288 #define RK3288_DRV_BITS_PER_PIN 2 1289 #define RK3288_DRV_PINS_PER_REG 8 1290 #define RK3288_DRV_BANK_STRIDE 16 1291 1292 static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1293 int pin_num, struct regmap **regmap, 1294 int *reg, u8 *bit) 1295 { 1296 struct rockchip_pinctrl *info = bank->drvdata; 1297 1298 /* The first 24 pins of the first bank are located in PMU */ 1299 if (bank->bank_num == 0) { 1300 *regmap = info->regmap_pmu; 1301 *reg = RK3288_DRV_PMU_OFFSET; 1302 1303 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1304 *bit = pin_num % RK3288_DRV_PINS_PER_REG; 1305 *bit *= RK3288_DRV_BITS_PER_PIN; 1306 } else { 1307 *regmap = info->regmap_base; 1308 *reg = RK3288_DRV_GRF_OFFSET; 1309 1310 /* correct the offset, as we're starting with the 2nd bank */ 1311 *reg -= 0x10; 1312 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 1313 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1314 1315 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 1316 *bit *= RK3288_DRV_BITS_PER_PIN; 1317 } 1318 } 1319 1320 #define RK3228_PULL_OFFSET 0x100 1321 1322 static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1323 int pin_num, struct regmap **regmap, 1324 int *reg, u8 *bit) 1325 { 1326 struct rockchip_pinctrl *info = bank->drvdata; 1327 1328 *regmap = info->regmap_base; 1329 *reg = RK3228_PULL_OFFSET; 1330 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1331 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1332 1333 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1334 *bit *= RK3188_PULL_BITS_PER_PIN; 1335 } 1336 1337 #define RK3228_DRV_GRF_OFFSET 0x200 1338 1339 static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1340 int pin_num, struct regmap **regmap, 1341 int *reg, u8 *bit) 1342 { 1343 struct rockchip_pinctrl *info = bank->drvdata; 1344 1345 *regmap = info->regmap_base; 1346 *reg = RK3228_DRV_GRF_OFFSET; 1347 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 1348 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1349 1350 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 1351 *bit *= RK3288_DRV_BITS_PER_PIN; 1352 } 1353 1354 #define RK3308_PULL_OFFSET 0xa0 1355 1356 static void rk3308_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1357 int pin_num, struct regmap **regmap, 1358 int *reg, u8 *bit) 1359 { 1360 struct rockchip_pinctrl *info = bank->drvdata; 1361 1362 *regmap = info->regmap_base; 1363 *reg = RK3308_PULL_OFFSET; 1364 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1365 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1366 1367 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1368 *bit *= RK3188_PULL_BITS_PER_PIN; 1369 } 1370 1371 #define RK3308_DRV_GRF_OFFSET 0x100 1372 1373 static void rk3308_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1374 int pin_num, struct regmap **regmap, 1375 int *reg, u8 *bit) 1376 { 1377 struct rockchip_pinctrl *info = bank->drvdata; 1378 1379 *regmap = info->regmap_base; 1380 *reg = RK3308_DRV_GRF_OFFSET; 1381 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 1382 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1383 1384 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 1385 *bit *= RK3288_DRV_BITS_PER_PIN; 1386 } 1387 1388 #define RK3368_PULL_GRF_OFFSET 0x100 1389 #define RK3368_PULL_PMU_OFFSET 0x10 1390 1391 static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1392 int pin_num, struct regmap **regmap, 1393 int *reg, u8 *bit) 1394 { 1395 struct rockchip_pinctrl *info = bank->drvdata; 1396 1397 /* The first 32 pins of the first bank are located in PMU */ 1398 if (bank->bank_num == 0) { 1399 *regmap = info->regmap_pmu; 1400 *reg = RK3368_PULL_PMU_OFFSET; 1401 1402 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1403 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 1404 *bit *= RK3188_PULL_BITS_PER_PIN; 1405 } else { 1406 *regmap = info->regmap_base; 1407 *reg = RK3368_PULL_GRF_OFFSET; 1408 1409 /* correct the offset, as we're starting with the 2nd bank */ 1410 *reg -= 0x10; 1411 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1412 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1413 1414 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1415 *bit *= RK3188_PULL_BITS_PER_PIN; 1416 } 1417 } 1418 1419 #define RK3368_DRV_PMU_OFFSET 0x20 1420 #define RK3368_DRV_GRF_OFFSET 0x200 1421 1422 static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1423 int pin_num, struct regmap **regmap, 1424 int *reg, u8 *bit) 1425 { 1426 struct rockchip_pinctrl *info = bank->drvdata; 1427 1428 /* The first 32 pins of the first bank are located in PMU */ 1429 if (bank->bank_num == 0) { 1430 *regmap = info->regmap_pmu; 1431 *reg = RK3368_DRV_PMU_OFFSET; 1432 1433 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1434 *bit = pin_num % RK3288_DRV_PINS_PER_REG; 1435 *bit *= RK3288_DRV_BITS_PER_PIN; 1436 } else { 1437 *regmap = info->regmap_base; 1438 *reg = RK3368_DRV_GRF_OFFSET; 1439 1440 /* correct the offset, as we're starting with the 2nd bank */ 1441 *reg -= 0x10; 1442 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 1443 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1444 1445 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 1446 *bit *= RK3288_DRV_BITS_PER_PIN; 1447 } 1448 } 1449 1450 #define RK3399_PULL_GRF_OFFSET 0xe040 1451 #define RK3399_PULL_PMU_OFFSET 0x40 1452 #define RK3399_DRV_3BITS_PER_PIN 3 1453 1454 static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1455 int pin_num, struct regmap **regmap, 1456 int *reg, u8 *bit) 1457 { 1458 struct rockchip_pinctrl *info = bank->drvdata; 1459 1460 /* The bank0:16 and bank1:32 pins are located in PMU */ 1461 if ((bank->bank_num == 0) || (bank->bank_num == 1)) { 1462 *regmap = info->regmap_pmu; 1463 *reg = RK3399_PULL_PMU_OFFSET; 1464 1465 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1466 1467 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1468 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 1469 *bit *= RK3188_PULL_BITS_PER_PIN; 1470 } else { 1471 *regmap = info->regmap_base; 1472 *reg = RK3399_PULL_GRF_OFFSET; 1473 1474 /* correct the offset, as we're starting with the 3rd bank */ 1475 *reg -= 0x20; 1476 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1477 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1478 1479 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1480 *bit *= RK3188_PULL_BITS_PER_PIN; 1481 } 1482 } 1483 1484 static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1485 int pin_num, struct regmap **regmap, 1486 int *reg, u8 *bit) 1487 { 1488 struct rockchip_pinctrl *info = bank->drvdata; 1489 int drv_num = (pin_num / 8); 1490 1491 /* The bank0:16 and bank1:32 pins are located in PMU */ 1492 if ((bank->bank_num == 0) || (bank->bank_num == 1)) 1493 *regmap = info->regmap_pmu; 1494 else 1495 *regmap = info->regmap_base; 1496 1497 *reg = bank->drv[drv_num].offset; 1498 if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) || 1499 (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY)) 1500 *bit = (pin_num % 8) * 3; 1501 else 1502 *bit = (pin_num % 8) * 2; 1503 } 1504 1505 #define RK3568_PULL_PMU_OFFSET 0x20 1506 #define RK3568_PULL_GRF_OFFSET 0x80 1507 #define RK3568_PULL_BITS_PER_PIN 2 1508 #define RK3568_PULL_PINS_PER_REG 8 1509 #define RK3568_PULL_BANK_STRIDE 0x10 1510 1511 static void rk3568_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1512 int pin_num, struct regmap **regmap, 1513 int *reg, u8 *bit) 1514 { 1515 struct rockchip_pinctrl *info = bank->drvdata; 1516 1517 if (bank->bank_num == 0) { 1518 *regmap = info->regmap_pmu; 1519 *reg = RK3568_PULL_PMU_OFFSET; 1520 *reg += bank->bank_num * RK3568_PULL_BANK_STRIDE; 1521 *reg += ((pin_num / RK3568_PULL_PINS_PER_REG) * 4); 1522 1523 *bit = pin_num % RK3568_PULL_PINS_PER_REG; 1524 *bit *= RK3568_PULL_BITS_PER_PIN; 1525 } else { 1526 *regmap = info->regmap_base; 1527 *reg = RK3568_PULL_GRF_OFFSET; 1528 *reg += (bank->bank_num - 1) * RK3568_PULL_BANK_STRIDE; 1529 *reg += ((pin_num / RK3568_PULL_PINS_PER_REG) * 4); 1530 1531 *bit = (pin_num % RK3568_PULL_PINS_PER_REG); 1532 *bit *= RK3568_PULL_BITS_PER_PIN; 1533 } 1534 } 1535 1536 #define RK3568_DRV_PMU_OFFSET 0x70 1537 #define RK3568_DRV_GRF_OFFSET 0x200 1538 #define RK3568_DRV_BITS_PER_PIN 8 1539 #define RK3568_DRV_PINS_PER_REG 2 1540 #define RK3568_DRV_BANK_STRIDE 0x40 1541 1542 static void rk3568_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1543 int pin_num, struct regmap **regmap, 1544 int *reg, u8 *bit) 1545 { 1546 struct rockchip_pinctrl *info = bank->drvdata; 1547 1548 /* The first 32 pins of the first bank are located in PMU */ 1549 if (bank->bank_num == 0) { 1550 *regmap = info->regmap_pmu; 1551 *reg = RK3568_DRV_PMU_OFFSET; 1552 *reg += ((pin_num / RK3568_DRV_PINS_PER_REG) * 4); 1553 1554 *bit = pin_num % RK3568_DRV_PINS_PER_REG; 1555 *bit *= RK3568_DRV_BITS_PER_PIN; 1556 } else { 1557 *regmap = info->regmap_base; 1558 *reg = RK3568_DRV_GRF_OFFSET; 1559 *reg += (bank->bank_num - 1) * RK3568_DRV_BANK_STRIDE; 1560 *reg += ((pin_num / RK3568_DRV_PINS_PER_REG) * 4); 1561 1562 *bit = (pin_num % RK3568_DRV_PINS_PER_REG); 1563 *bit *= RK3568_DRV_BITS_PER_PIN; 1564 } 1565 } 1566 1567 static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = { 1568 { 2, 4, 8, 12, -1, -1, -1, -1 }, 1569 { 3, 6, 9, 12, -1, -1, -1, -1 }, 1570 { 5, 10, 15, 20, -1, -1, -1, -1 }, 1571 { 4, 6, 8, 10, 12, 14, 16, 18 }, 1572 { 4, 7, 10, 13, 16, 19, 22, 26 } 1573 }; 1574 1575 static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank, 1576 int pin_num) 1577 { 1578 struct rockchip_pinctrl *info = bank->drvdata; 1579 struct rockchip_pin_ctrl *ctrl = info->ctrl; 1580 struct device *dev = info->dev; 1581 struct regmap *regmap; 1582 int reg, ret; 1583 u32 data, temp, rmask_bits; 1584 u8 bit; 1585 int drv_type = bank->drv[pin_num / 8].drv_type; 1586 1587 ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); 1588 1589 switch (drv_type) { 1590 case DRV_TYPE_IO_1V8_3V0_AUTO: 1591 case DRV_TYPE_IO_3V3_ONLY: 1592 rmask_bits = RK3399_DRV_3BITS_PER_PIN; 1593 switch (bit) { 1594 case 0 ... 12: 1595 /* regular case, nothing to do */ 1596 break; 1597 case 15: 1598 /* 1599 * drive-strength offset is special, as it is 1600 * spread over 2 registers 1601 */ 1602 ret = regmap_read(regmap, reg, &data); 1603 if (ret) 1604 return ret; 1605 1606 ret = regmap_read(regmap, reg + 0x4, &temp); 1607 if (ret) 1608 return ret; 1609 1610 /* 1611 * the bit data[15] contains bit 0 of the value 1612 * while temp[1:0] contains bits 2 and 1 1613 */ 1614 data >>= 15; 1615 temp &= 0x3; 1616 temp <<= 1; 1617 data |= temp; 1618 1619 return rockchip_perpin_drv_list[drv_type][data]; 1620 case 18 ... 21: 1621 /* setting fully enclosed in the second register */ 1622 reg += 4; 1623 bit -= 16; 1624 break; 1625 default: 1626 dev_err(dev, "unsupported bit: %d for pinctrl drive type: %d\n", 1627 bit, drv_type); 1628 return -EINVAL; 1629 } 1630 1631 break; 1632 case DRV_TYPE_IO_DEFAULT: 1633 case DRV_TYPE_IO_1V8_OR_3V0: 1634 case DRV_TYPE_IO_1V8_ONLY: 1635 rmask_bits = RK3288_DRV_BITS_PER_PIN; 1636 break; 1637 default: 1638 dev_err(dev, "unsupported pinctrl drive type: %d\n", drv_type); 1639 return -EINVAL; 1640 } 1641 1642 ret = regmap_read(regmap, reg, &data); 1643 if (ret) 1644 return ret; 1645 1646 data >>= bit; 1647 data &= (1 << rmask_bits) - 1; 1648 1649 return rockchip_perpin_drv_list[drv_type][data]; 1650 } 1651 1652 static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank, 1653 int pin_num, int strength) 1654 { 1655 struct rockchip_pinctrl *info = bank->drvdata; 1656 struct rockchip_pin_ctrl *ctrl = info->ctrl; 1657 struct device *dev = info->dev; 1658 struct regmap *regmap; 1659 int reg, ret, i; 1660 u32 data, rmask, rmask_bits, temp; 1661 u8 bit; 1662 int drv_type = bank->drv[pin_num / 8].drv_type; 1663 1664 dev_dbg(dev, "setting drive of GPIO%d-%d to %d\n", 1665 bank->bank_num, pin_num, strength); 1666 1667 ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); 1668 if (ctrl->type == RK3568) { 1669 rmask_bits = RK3568_DRV_BITS_PER_PIN; 1670 ret = (1 << (strength + 1)) - 1; 1671 goto config; 1672 } 1673 1674 ret = -EINVAL; 1675 for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) { 1676 if (rockchip_perpin_drv_list[drv_type][i] == strength) { 1677 ret = i; 1678 break; 1679 } else if (rockchip_perpin_drv_list[drv_type][i] < 0) { 1680 ret = rockchip_perpin_drv_list[drv_type][i]; 1681 break; 1682 } 1683 } 1684 1685 if (ret < 0) { 1686 dev_err(dev, "unsupported driver strength %d\n", strength); 1687 return ret; 1688 } 1689 1690 switch (drv_type) { 1691 case DRV_TYPE_IO_1V8_3V0_AUTO: 1692 case DRV_TYPE_IO_3V3_ONLY: 1693 rmask_bits = RK3399_DRV_3BITS_PER_PIN; 1694 switch (bit) { 1695 case 0 ... 12: 1696 /* regular case, nothing to do */ 1697 break; 1698 case 15: 1699 /* 1700 * drive-strength offset is special, as it is spread 1701 * over 2 registers, the bit data[15] contains bit 0 1702 * of the value while temp[1:0] contains bits 2 and 1 1703 */ 1704 data = (ret & 0x1) << 15; 1705 temp = (ret >> 0x1) & 0x3; 1706 1707 rmask = BIT(15) | BIT(31); 1708 data |= BIT(31); 1709 ret = regmap_update_bits(regmap, reg, rmask, data); 1710 if (ret) 1711 return ret; 1712 1713 rmask = 0x3 | (0x3 << 16); 1714 temp |= (0x3 << 16); 1715 reg += 0x4; 1716 ret = regmap_update_bits(regmap, reg, rmask, temp); 1717 1718 return ret; 1719 case 18 ... 21: 1720 /* setting fully enclosed in the second register */ 1721 reg += 4; 1722 bit -= 16; 1723 break; 1724 default: 1725 dev_err(dev, "unsupported bit: %d for pinctrl drive type: %d\n", 1726 bit, drv_type); 1727 return -EINVAL; 1728 } 1729 break; 1730 case DRV_TYPE_IO_DEFAULT: 1731 case DRV_TYPE_IO_1V8_OR_3V0: 1732 case DRV_TYPE_IO_1V8_ONLY: 1733 rmask_bits = RK3288_DRV_BITS_PER_PIN; 1734 break; 1735 default: 1736 dev_err(dev, "unsupported pinctrl drive type: %d\n", drv_type); 1737 return -EINVAL; 1738 } 1739 1740 config: 1741 /* enable the write to the equivalent lower bits */ 1742 data = ((1 << rmask_bits) - 1) << (bit + 16); 1743 rmask = data | (data >> 16); 1744 data |= (ret << bit); 1745 1746 ret = regmap_update_bits(regmap, reg, rmask, data); 1747 1748 return ret; 1749 } 1750 1751 static int rockchip_pull_list[PULL_TYPE_MAX][4] = { 1752 { 1753 PIN_CONFIG_BIAS_DISABLE, 1754 PIN_CONFIG_BIAS_PULL_UP, 1755 PIN_CONFIG_BIAS_PULL_DOWN, 1756 PIN_CONFIG_BIAS_BUS_HOLD 1757 }, 1758 { 1759 PIN_CONFIG_BIAS_DISABLE, 1760 PIN_CONFIG_BIAS_PULL_DOWN, 1761 PIN_CONFIG_BIAS_DISABLE, 1762 PIN_CONFIG_BIAS_PULL_UP 1763 }, 1764 }; 1765 1766 static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num) 1767 { 1768 struct rockchip_pinctrl *info = bank->drvdata; 1769 struct rockchip_pin_ctrl *ctrl = info->ctrl; 1770 struct device *dev = info->dev; 1771 struct regmap *regmap; 1772 int reg, ret, pull_type; 1773 u8 bit; 1774 u32 data; 1775 1776 /* rk3066b does support any pulls */ 1777 if (ctrl->type == RK3066B) 1778 return PIN_CONFIG_BIAS_DISABLE; 1779 1780 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); 1781 1782 ret = regmap_read(regmap, reg, &data); 1783 if (ret) 1784 return ret; 1785 1786 switch (ctrl->type) { 1787 case RK2928: 1788 case RK3128: 1789 return !(data & BIT(bit)) 1790 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT 1791 : PIN_CONFIG_BIAS_DISABLE; 1792 case PX30: 1793 case RV1108: 1794 case RK3188: 1795 case RK3288: 1796 case RK3308: 1797 case RK3368: 1798 case RK3399: 1799 pull_type = bank->pull_type[pin_num / 8]; 1800 data >>= bit; 1801 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1; 1802 1803 return rockchip_pull_list[pull_type][data]; 1804 default: 1805 dev_err(dev, "unsupported pinctrl type\n"); 1806 return -EINVAL; 1807 }; 1808 } 1809 1810 static int rockchip_set_pull(struct rockchip_pin_bank *bank, 1811 int pin_num, int pull) 1812 { 1813 struct rockchip_pinctrl *info = bank->drvdata; 1814 struct rockchip_pin_ctrl *ctrl = info->ctrl; 1815 struct device *dev = info->dev; 1816 struct regmap *regmap; 1817 int reg, ret, i, pull_type; 1818 u8 bit; 1819 u32 data, rmask; 1820 1821 dev_dbg(dev, "setting pull of GPIO%d-%d to %d\n", bank->bank_num, pin_num, pull); 1822 1823 /* rk3066b does support any pulls */ 1824 if (ctrl->type == RK3066B) 1825 return pull ? -EINVAL : 0; 1826 1827 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); 1828 1829 switch (ctrl->type) { 1830 case RK2928: 1831 case RK3128: 1832 data = BIT(bit + 16); 1833 if (pull == PIN_CONFIG_BIAS_DISABLE) 1834 data |= BIT(bit); 1835 ret = regmap_write(regmap, reg, data); 1836 break; 1837 case PX30: 1838 case RV1108: 1839 case RK3188: 1840 case RK3288: 1841 case RK3308: 1842 case RK3368: 1843 case RK3399: 1844 case RK3568: 1845 pull_type = bank->pull_type[pin_num / 8]; 1846 ret = -EINVAL; 1847 for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]); 1848 i++) { 1849 if (rockchip_pull_list[pull_type][i] == pull) { 1850 ret = i; 1851 break; 1852 } 1853 } 1854 /* 1855 * In the TRM, pull-up being 1 for everything except the GPIO0_D0-D6, 1856 * where that pull up value becomes 3. 1857 */ 1858 if (ctrl->type == RK3568 && bank->bank_num == 0 && pin_num >= 27 && pin_num <= 30) { 1859 if (ret == 1) 1860 ret = 3; 1861 } 1862 1863 if (ret < 0) { 1864 dev_err(dev, "unsupported pull setting %d\n", pull); 1865 return ret; 1866 } 1867 1868 /* enable the write to the equivalent lower bits */ 1869 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16); 1870 rmask = data | (data >> 16); 1871 data |= (ret << bit); 1872 1873 ret = regmap_update_bits(regmap, reg, rmask, data); 1874 break; 1875 default: 1876 dev_err(dev, "unsupported pinctrl type\n"); 1877 return -EINVAL; 1878 } 1879 1880 return ret; 1881 } 1882 1883 #define RK3328_SCHMITT_BITS_PER_PIN 1 1884 #define RK3328_SCHMITT_PINS_PER_REG 16 1885 #define RK3328_SCHMITT_BANK_STRIDE 8 1886 #define RK3328_SCHMITT_GRF_OFFSET 0x380 1887 1888 static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1889 int pin_num, 1890 struct regmap **regmap, 1891 int *reg, u8 *bit) 1892 { 1893 struct rockchip_pinctrl *info = bank->drvdata; 1894 1895 *regmap = info->regmap_base; 1896 *reg = RK3328_SCHMITT_GRF_OFFSET; 1897 1898 *reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE; 1899 *reg += ((pin_num / RK3328_SCHMITT_PINS_PER_REG) * 4); 1900 *bit = pin_num % RK3328_SCHMITT_PINS_PER_REG; 1901 1902 return 0; 1903 } 1904 1905 #define RK3568_SCHMITT_BITS_PER_PIN 2 1906 #define RK3568_SCHMITT_PINS_PER_REG 8 1907 #define RK3568_SCHMITT_BANK_STRIDE 0x10 1908 #define RK3568_SCHMITT_GRF_OFFSET 0xc0 1909 #define RK3568_SCHMITT_PMUGRF_OFFSET 0x30 1910 1911 static int rk3568_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1912 int pin_num, 1913 struct regmap **regmap, 1914 int *reg, u8 *bit) 1915 { 1916 struct rockchip_pinctrl *info = bank->drvdata; 1917 1918 if (bank->bank_num == 0) { 1919 *regmap = info->regmap_pmu; 1920 *reg = RK3568_SCHMITT_PMUGRF_OFFSET; 1921 } else { 1922 *regmap = info->regmap_base; 1923 *reg = RK3568_SCHMITT_GRF_OFFSET; 1924 *reg += (bank->bank_num - 1) * RK3568_SCHMITT_BANK_STRIDE; 1925 } 1926 1927 *reg += ((pin_num / RK3568_SCHMITT_PINS_PER_REG) * 4); 1928 *bit = pin_num % RK3568_SCHMITT_PINS_PER_REG; 1929 *bit *= RK3568_SCHMITT_BITS_PER_PIN; 1930 1931 return 0; 1932 } 1933 1934 static int rockchip_get_schmitt(struct rockchip_pin_bank *bank, int pin_num) 1935 { 1936 struct rockchip_pinctrl *info = bank->drvdata; 1937 struct rockchip_pin_ctrl *ctrl = info->ctrl; 1938 struct regmap *regmap; 1939 int reg, ret; 1940 u8 bit; 1941 u32 data; 1942 1943 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit); 1944 if (ret) 1945 return ret; 1946 1947 ret = regmap_read(regmap, reg, &data); 1948 if (ret) 1949 return ret; 1950 1951 data >>= bit; 1952 switch (ctrl->type) { 1953 case RK3568: 1954 return data & ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1); 1955 default: 1956 break; 1957 } 1958 1959 return data & 0x1; 1960 } 1961 1962 static int rockchip_set_schmitt(struct rockchip_pin_bank *bank, 1963 int pin_num, int enable) 1964 { 1965 struct rockchip_pinctrl *info = bank->drvdata; 1966 struct rockchip_pin_ctrl *ctrl = info->ctrl; 1967 struct device *dev = info->dev; 1968 struct regmap *regmap; 1969 int reg, ret; 1970 u8 bit; 1971 u32 data, rmask; 1972 1973 dev_dbg(dev, "setting input schmitt of GPIO%d-%d to %d\n", 1974 bank->bank_num, pin_num, enable); 1975 1976 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit); 1977 if (ret) 1978 return ret; 1979 1980 /* enable the write to the equivalent lower bits */ 1981 switch (ctrl->type) { 1982 case RK3568: 1983 data = ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1) << (bit + 16); 1984 rmask = data | (data >> 16); 1985 data |= ((enable ? 0x2 : 0x1) << bit); 1986 break; 1987 default: 1988 data = BIT(bit + 16) | (enable << bit); 1989 rmask = BIT(bit + 16) | BIT(bit); 1990 break; 1991 } 1992 1993 return regmap_update_bits(regmap, reg, rmask, data); 1994 } 1995 1996 /* 1997 * Pinmux_ops handling 1998 */ 1999 2000 static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev) 2001 { 2002 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 2003 2004 return info->nfunctions; 2005 } 2006 2007 static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev, 2008 unsigned selector) 2009 { 2010 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 2011 2012 return info->functions[selector].name; 2013 } 2014 2015 static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev, 2016 unsigned selector, const char * const **groups, 2017 unsigned * const num_groups) 2018 { 2019 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 2020 2021 *groups = info->functions[selector].groups; 2022 *num_groups = info->functions[selector].ngroups; 2023 2024 return 0; 2025 } 2026 2027 static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector, 2028 unsigned group) 2029 { 2030 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 2031 const unsigned int *pins = info->groups[group].pins; 2032 const struct rockchip_pin_config *data = info->groups[group].data; 2033 struct device *dev = info->dev; 2034 struct rockchip_pin_bank *bank; 2035 int cnt, ret = 0; 2036 2037 dev_dbg(dev, "enable function %s group %s\n", 2038 info->functions[selector].name, info->groups[group].name); 2039 2040 /* 2041 * for each pin in the pin group selected, program the corresponding 2042 * pin function number in the config register. 2043 */ 2044 for (cnt = 0; cnt < info->groups[group].npins; cnt++) { 2045 bank = pin_to_bank(info, pins[cnt]); 2046 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 2047 data[cnt].func); 2048 if (ret) 2049 break; 2050 } 2051 2052 if (ret) { 2053 /* revert the already done pin settings */ 2054 for (cnt--; cnt >= 0; cnt--) 2055 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0); 2056 2057 return ret; 2058 } 2059 2060 return 0; 2061 } 2062 2063 static const struct pinmux_ops rockchip_pmx_ops = { 2064 .get_functions_count = rockchip_pmx_get_funcs_count, 2065 .get_function_name = rockchip_pmx_get_func_name, 2066 .get_function_groups = rockchip_pmx_get_groups, 2067 .set_mux = rockchip_pmx_set, 2068 }; 2069 2070 /* 2071 * Pinconf_ops handling 2072 */ 2073 2074 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl, 2075 enum pin_config_param pull) 2076 { 2077 switch (ctrl->type) { 2078 case RK2928: 2079 case RK3128: 2080 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT || 2081 pull == PIN_CONFIG_BIAS_DISABLE); 2082 case RK3066B: 2083 return pull ? false : true; 2084 case PX30: 2085 case RV1108: 2086 case RK3188: 2087 case RK3288: 2088 case RK3308: 2089 case RK3368: 2090 case RK3399: 2091 case RK3568: 2092 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT); 2093 } 2094 2095 return false; 2096 } 2097 2098 static int rockchip_pinconf_defer_output(struct rockchip_pin_bank *bank, 2099 unsigned int pin, u32 arg) 2100 { 2101 struct rockchip_pin_output_deferred *cfg; 2102 2103 cfg = kzalloc(sizeof(*cfg), GFP_KERNEL); 2104 if (!cfg) 2105 return -ENOMEM; 2106 2107 cfg->pin = pin; 2108 cfg->arg = arg; 2109 2110 list_add_tail(&cfg->head, &bank->deferred_output); 2111 2112 return 0; 2113 } 2114 2115 /* set the pin config settings for a specified pin */ 2116 static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 2117 unsigned long *configs, unsigned num_configs) 2118 { 2119 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 2120 struct rockchip_pin_bank *bank = pin_to_bank(info, pin); 2121 struct gpio_chip *gpio = &bank->gpio_chip; 2122 enum pin_config_param param; 2123 u32 arg; 2124 int i; 2125 int rc; 2126 2127 for (i = 0; i < num_configs; i++) { 2128 param = pinconf_to_config_param(configs[i]); 2129 arg = pinconf_to_config_argument(configs[i]); 2130 2131 switch (param) { 2132 case PIN_CONFIG_BIAS_DISABLE: 2133 rc = rockchip_set_pull(bank, pin - bank->pin_base, 2134 param); 2135 if (rc) 2136 return rc; 2137 break; 2138 case PIN_CONFIG_BIAS_PULL_UP: 2139 case PIN_CONFIG_BIAS_PULL_DOWN: 2140 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: 2141 case PIN_CONFIG_BIAS_BUS_HOLD: 2142 if (!rockchip_pinconf_pull_valid(info->ctrl, param)) 2143 return -ENOTSUPP; 2144 2145 if (!arg) 2146 return -EINVAL; 2147 2148 rc = rockchip_set_pull(bank, pin - bank->pin_base, 2149 param); 2150 if (rc) 2151 return rc; 2152 break; 2153 case PIN_CONFIG_OUTPUT: 2154 rc = rockchip_set_mux(bank, pin - bank->pin_base, 2155 RK_FUNC_GPIO); 2156 if (rc != RK_FUNC_GPIO) 2157 return -EINVAL; 2158 2159 /* 2160 * Check for gpio driver not being probed yet. 2161 * The lock makes sure that either gpio-probe has completed 2162 * or the gpio driver hasn't probed yet. 2163 */ 2164 mutex_lock(&bank->deferred_lock); 2165 if (!gpio || !gpio->direction_output) { 2166 rc = rockchip_pinconf_defer_output(bank, pin - bank->pin_base, arg); 2167 mutex_unlock(&bank->deferred_lock); 2168 if (rc) 2169 return rc; 2170 2171 break; 2172 } 2173 mutex_unlock(&bank->deferred_lock); 2174 2175 rc = gpio->direction_output(gpio, pin - bank->pin_base, 2176 arg); 2177 if (rc) 2178 return rc; 2179 break; 2180 case PIN_CONFIG_DRIVE_STRENGTH: 2181 /* rk3288 is the first with per-pin drive-strength */ 2182 if (!info->ctrl->drv_calc_reg) 2183 return -ENOTSUPP; 2184 2185 rc = rockchip_set_drive_perpin(bank, 2186 pin - bank->pin_base, arg); 2187 if (rc < 0) 2188 return rc; 2189 break; 2190 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 2191 if (!info->ctrl->schmitt_calc_reg) 2192 return -ENOTSUPP; 2193 2194 rc = rockchip_set_schmitt(bank, 2195 pin - bank->pin_base, arg); 2196 if (rc < 0) 2197 return rc; 2198 break; 2199 default: 2200 return -ENOTSUPP; 2201 break; 2202 } 2203 } /* for each config */ 2204 2205 return 0; 2206 } 2207 2208 /* get the pin config settings for a specified pin */ 2209 static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, 2210 unsigned long *config) 2211 { 2212 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 2213 struct rockchip_pin_bank *bank = pin_to_bank(info, pin); 2214 struct gpio_chip *gpio = &bank->gpio_chip; 2215 enum pin_config_param param = pinconf_to_config_param(*config); 2216 u16 arg; 2217 int rc; 2218 2219 switch (param) { 2220 case PIN_CONFIG_BIAS_DISABLE: 2221 if (rockchip_get_pull(bank, pin - bank->pin_base) != param) 2222 return -EINVAL; 2223 2224 arg = 0; 2225 break; 2226 case PIN_CONFIG_BIAS_PULL_UP: 2227 case PIN_CONFIG_BIAS_PULL_DOWN: 2228 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: 2229 case PIN_CONFIG_BIAS_BUS_HOLD: 2230 if (!rockchip_pinconf_pull_valid(info->ctrl, param)) 2231 return -ENOTSUPP; 2232 2233 if (rockchip_get_pull(bank, pin - bank->pin_base) != param) 2234 return -EINVAL; 2235 2236 arg = 1; 2237 break; 2238 case PIN_CONFIG_OUTPUT: 2239 rc = rockchip_get_mux(bank, pin - bank->pin_base); 2240 if (rc != RK_FUNC_GPIO) 2241 return -EINVAL; 2242 2243 if (!gpio || !gpio->get) { 2244 arg = 0; 2245 break; 2246 } 2247 2248 rc = gpio->get(gpio, pin - bank->pin_base); 2249 if (rc < 0) 2250 return rc; 2251 2252 arg = rc ? 1 : 0; 2253 break; 2254 case PIN_CONFIG_DRIVE_STRENGTH: 2255 /* rk3288 is the first with per-pin drive-strength */ 2256 if (!info->ctrl->drv_calc_reg) 2257 return -ENOTSUPP; 2258 2259 rc = rockchip_get_drive_perpin(bank, pin - bank->pin_base); 2260 if (rc < 0) 2261 return rc; 2262 2263 arg = rc; 2264 break; 2265 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 2266 if (!info->ctrl->schmitt_calc_reg) 2267 return -ENOTSUPP; 2268 2269 rc = rockchip_get_schmitt(bank, pin - bank->pin_base); 2270 if (rc < 0) 2271 return rc; 2272 2273 arg = rc; 2274 break; 2275 default: 2276 return -ENOTSUPP; 2277 break; 2278 } 2279 2280 *config = pinconf_to_config_packed(param, arg); 2281 2282 return 0; 2283 } 2284 2285 static const struct pinconf_ops rockchip_pinconf_ops = { 2286 .pin_config_get = rockchip_pinconf_get, 2287 .pin_config_set = rockchip_pinconf_set, 2288 .is_generic = true, 2289 }; 2290 2291 static const struct of_device_id rockchip_bank_match[] = { 2292 { .compatible = "rockchip,gpio-bank" }, 2293 { .compatible = "rockchip,rk3188-gpio-bank0" }, 2294 {}, 2295 }; 2296 2297 static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info, 2298 struct device_node *np) 2299 { 2300 struct device_node *child; 2301 2302 for_each_child_of_node(np, child) { 2303 if (of_match_node(rockchip_bank_match, child)) 2304 continue; 2305 2306 info->nfunctions++; 2307 info->ngroups += of_get_child_count(child); 2308 } 2309 } 2310 2311 static int rockchip_pinctrl_parse_groups(struct device_node *np, 2312 struct rockchip_pin_group *grp, 2313 struct rockchip_pinctrl *info, 2314 u32 index) 2315 { 2316 struct device *dev = info->dev; 2317 struct rockchip_pin_bank *bank; 2318 int size; 2319 const __be32 *list; 2320 int num; 2321 int i, j; 2322 int ret; 2323 2324 dev_dbg(dev, "group(%d): %pOFn\n", index, np); 2325 2326 /* Initialise group */ 2327 grp->name = np->name; 2328 2329 /* 2330 * the binding format is rockchip,pins = <bank pin mux CONFIG>, 2331 * do sanity check and calculate pins number 2332 */ 2333 list = of_get_property(np, "rockchip,pins", &size); 2334 /* we do not check return since it's safe node passed down */ 2335 size /= sizeof(*list); 2336 if (!size || size % 4) 2337 return dev_err_probe(dev, -EINVAL, "wrong pins number or pins and configs should be by 4\n"); 2338 2339 grp->npins = size / 4; 2340 2341 grp->pins = devm_kcalloc(dev, grp->npins, sizeof(*grp->pins), GFP_KERNEL); 2342 grp->data = devm_kcalloc(dev, grp->npins, sizeof(*grp->data), GFP_KERNEL); 2343 if (!grp->pins || !grp->data) 2344 return -ENOMEM; 2345 2346 for (i = 0, j = 0; i < size; i += 4, j++) { 2347 const __be32 *phandle; 2348 struct device_node *np_config; 2349 2350 num = be32_to_cpu(*list++); 2351 bank = bank_num_to_bank(info, num); 2352 if (IS_ERR(bank)) 2353 return PTR_ERR(bank); 2354 2355 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++); 2356 grp->data[j].func = be32_to_cpu(*list++); 2357 2358 phandle = list++; 2359 if (!phandle) 2360 return -EINVAL; 2361 2362 np_config = of_find_node_by_phandle(be32_to_cpup(phandle)); 2363 ret = pinconf_generic_parse_dt_config(np_config, NULL, 2364 &grp->data[j].configs, &grp->data[j].nconfigs); 2365 if (ret) 2366 return ret; 2367 } 2368 2369 return 0; 2370 } 2371 2372 static int rockchip_pinctrl_parse_functions(struct device_node *np, 2373 struct rockchip_pinctrl *info, 2374 u32 index) 2375 { 2376 struct device *dev = info->dev; 2377 struct device_node *child; 2378 struct rockchip_pmx_func *func; 2379 struct rockchip_pin_group *grp; 2380 int ret; 2381 static u32 grp_index; 2382 u32 i = 0; 2383 2384 dev_dbg(dev, "parse function(%d): %pOFn\n", index, np); 2385 2386 func = &info->functions[index]; 2387 2388 /* Initialise function */ 2389 func->name = np->name; 2390 func->ngroups = of_get_child_count(np); 2391 if (func->ngroups <= 0) 2392 return 0; 2393 2394 func->groups = devm_kcalloc(dev, func->ngroups, sizeof(*func->groups), GFP_KERNEL); 2395 if (!func->groups) 2396 return -ENOMEM; 2397 2398 for_each_child_of_node(np, child) { 2399 func->groups[i] = child->name; 2400 grp = &info->groups[grp_index++]; 2401 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++); 2402 if (ret) { 2403 of_node_put(child); 2404 return ret; 2405 } 2406 } 2407 2408 return 0; 2409 } 2410 2411 static int rockchip_pinctrl_parse_dt(struct platform_device *pdev, 2412 struct rockchip_pinctrl *info) 2413 { 2414 struct device *dev = &pdev->dev; 2415 struct device_node *np = dev->of_node; 2416 struct device_node *child; 2417 int ret; 2418 int i; 2419 2420 rockchip_pinctrl_child_count(info, np); 2421 2422 dev_dbg(dev, "nfunctions = %d\n", info->nfunctions); 2423 dev_dbg(dev, "ngroups = %d\n", info->ngroups); 2424 2425 info->functions = devm_kcalloc(dev, info->nfunctions, sizeof(*info->functions), GFP_KERNEL); 2426 if (!info->functions) 2427 return -ENOMEM; 2428 2429 info->groups = devm_kcalloc(dev, info->ngroups, sizeof(*info->groups), GFP_KERNEL); 2430 if (!info->groups) 2431 return -ENOMEM; 2432 2433 i = 0; 2434 2435 for_each_child_of_node(np, child) { 2436 if (of_match_node(rockchip_bank_match, child)) 2437 continue; 2438 2439 ret = rockchip_pinctrl_parse_functions(child, info, i++); 2440 if (ret) { 2441 dev_err(dev, "failed to parse function\n"); 2442 of_node_put(child); 2443 return ret; 2444 } 2445 } 2446 2447 return 0; 2448 } 2449 2450 static int rockchip_pinctrl_register(struct platform_device *pdev, 2451 struct rockchip_pinctrl *info) 2452 { 2453 struct pinctrl_desc *ctrldesc = &info->pctl; 2454 struct pinctrl_pin_desc *pindesc, *pdesc; 2455 struct rockchip_pin_bank *pin_bank; 2456 struct device *dev = &pdev->dev; 2457 char **pin_names; 2458 int pin, bank, ret; 2459 int k; 2460 2461 ctrldesc->name = "rockchip-pinctrl"; 2462 ctrldesc->owner = THIS_MODULE; 2463 ctrldesc->pctlops = &rockchip_pctrl_ops; 2464 ctrldesc->pmxops = &rockchip_pmx_ops; 2465 ctrldesc->confops = &rockchip_pinconf_ops; 2466 2467 pindesc = devm_kcalloc(dev, info->ctrl->nr_pins, sizeof(*pindesc), GFP_KERNEL); 2468 if (!pindesc) 2469 return -ENOMEM; 2470 2471 ctrldesc->pins = pindesc; 2472 ctrldesc->npins = info->ctrl->nr_pins; 2473 2474 pdesc = pindesc; 2475 for (bank = 0, k = 0; bank < info->ctrl->nr_banks; bank++) { 2476 pin_bank = &info->ctrl->pin_banks[bank]; 2477 2478 pin_names = devm_kasprintf_strarray(dev, pin_bank->name, pin_bank->nr_pins); 2479 if (IS_ERR(pin_names)) 2480 return PTR_ERR(pin_names); 2481 2482 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) { 2483 pdesc->number = k; 2484 pdesc->name = pin_names[pin]; 2485 pdesc++; 2486 } 2487 2488 INIT_LIST_HEAD(&pin_bank->deferred_output); 2489 mutex_init(&pin_bank->deferred_lock); 2490 } 2491 2492 ret = rockchip_pinctrl_parse_dt(pdev, info); 2493 if (ret) 2494 return ret; 2495 2496 info->pctl_dev = devm_pinctrl_register(dev, ctrldesc, info); 2497 if (IS_ERR(info->pctl_dev)) 2498 return dev_err_probe(dev, PTR_ERR(info->pctl_dev), "could not register pinctrl driver\n"); 2499 2500 return 0; 2501 } 2502 2503 static const struct of_device_id rockchip_pinctrl_dt_match[]; 2504 2505 /* retrieve the soc specific data */ 2506 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data( 2507 struct rockchip_pinctrl *d, 2508 struct platform_device *pdev) 2509 { 2510 struct device *dev = &pdev->dev; 2511 struct device_node *node = dev->of_node; 2512 const struct of_device_id *match; 2513 struct rockchip_pin_ctrl *ctrl; 2514 struct rockchip_pin_bank *bank; 2515 int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j; 2516 2517 match = of_match_node(rockchip_pinctrl_dt_match, node); 2518 ctrl = (struct rockchip_pin_ctrl *)match->data; 2519 2520 grf_offs = ctrl->grf_mux_offset; 2521 pmu_offs = ctrl->pmu_mux_offset; 2522 drv_pmu_offs = ctrl->pmu_drv_offset; 2523 drv_grf_offs = ctrl->grf_drv_offset; 2524 bank = ctrl->pin_banks; 2525 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 2526 int bank_pins = 0; 2527 2528 raw_spin_lock_init(&bank->slock); 2529 bank->drvdata = d; 2530 bank->pin_base = ctrl->nr_pins; 2531 ctrl->nr_pins += bank->nr_pins; 2532 2533 /* calculate iomux and drv offsets */ 2534 for (j = 0; j < 4; j++) { 2535 struct rockchip_iomux *iom = &bank->iomux[j]; 2536 struct rockchip_drv *drv = &bank->drv[j]; 2537 int inc; 2538 2539 if (bank_pins >= bank->nr_pins) 2540 break; 2541 2542 /* preset iomux offset value, set new start value */ 2543 if (iom->offset >= 0) { 2544 if (iom->type & IOMUX_SOURCE_PMU) 2545 pmu_offs = iom->offset; 2546 else 2547 grf_offs = iom->offset; 2548 } else { /* set current iomux offset */ 2549 iom->offset = (iom->type & IOMUX_SOURCE_PMU) ? 2550 pmu_offs : grf_offs; 2551 } 2552 2553 /* preset drv offset value, set new start value */ 2554 if (drv->offset >= 0) { 2555 if (iom->type & IOMUX_SOURCE_PMU) 2556 drv_pmu_offs = drv->offset; 2557 else 2558 drv_grf_offs = drv->offset; 2559 } else { /* set current drv offset */ 2560 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ? 2561 drv_pmu_offs : drv_grf_offs; 2562 } 2563 2564 dev_dbg(dev, "bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n", 2565 i, j, iom->offset, drv->offset); 2566 2567 /* 2568 * Increase offset according to iomux width. 2569 * 4bit iomux'es are spread over two registers. 2570 */ 2571 inc = (iom->type & (IOMUX_WIDTH_4BIT | 2572 IOMUX_WIDTH_3BIT | 2573 IOMUX_WIDTH_2BIT)) ? 8 : 4; 2574 if (iom->type & IOMUX_SOURCE_PMU) 2575 pmu_offs += inc; 2576 else 2577 grf_offs += inc; 2578 2579 /* 2580 * Increase offset according to drv width. 2581 * 3bit drive-strenth'es are spread over two registers. 2582 */ 2583 if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) || 2584 (drv->drv_type == DRV_TYPE_IO_3V3_ONLY)) 2585 inc = 8; 2586 else 2587 inc = 4; 2588 2589 if (iom->type & IOMUX_SOURCE_PMU) 2590 drv_pmu_offs += inc; 2591 else 2592 drv_grf_offs += inc; 2593 2594 bank_pins += 8; 2595 } 2596 2597 /* calculate the per-bank recalced_mask */ 2598 for (j = 0; j < ctrl->niomux_recalced; j++) { 2599 int pin = 0; 2600 2601 if (ctrl->iomux_recalced[j].num == bank->bank_num) { 2602 pin = ctrl->iomux_recalced[j].pin; 2603 bank->recalced_mask |= BIT(pin); 2604 } 2605 } 2606 2607 /* calculate the per-bank route_mask */ 2608 for (j = 0; j < ctrl->niomux_routes; j++) { 2609 int pin = 0; 2610 2611 if (ctrl->iomux_routes[j].bank_num == bank->bank_num) { 2612 pin = ctrl->iomux_routes[j].pin; 2613 bank->route_mask |= BIT(pin); 2614 } 2615 } 2616 } 2617 2618 return ctrl; 2619 } 2620 2621 #define RK3288_GRF_GPIO6C_IOMUX 0x64 2622 #define GPIO6C6_SEL_WRITE_ENABLE BIT(28) 2623 2624 static u32 rk3288_grf_gpio6c_iomux; 2625 2626 static int __maybe_unused rockchip_pinctrl_suspend(struct device *dev) 2627 { 2628 struct rockchip_pinctrl *info = dev_get_drvdata(dev); 2629 int ret = pinctrl_force_sleep(info->pctl_dev); 2630 2631 if (ret) 2632 return ret; 2633 2634 /* 2635 * RK3288 GPIO6_C6 mux would be modified by Maskrom when resume, so save 2636 * the setting here, and restore it at resume. 2637 */ 2638 if (info->ctrl->type == RK3288) { 2639 ret = regmap_read(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX, 2640 &rk3288_grf_gpio6c_iomux); 2641 if (ret) { 2642 pinctrl_force_default(info->pctl_dev); 2643 return ret; 2644 } 2645 } 2646 2647 return 0; 2648 } 2649 2650 static int __maybe_unused rockchip_pinctrl_resume(struct device *dev) 2651 { 2652 struct rockchip_pinctrl *info = dev_get_drvdata(dev); 2653 int ret; 2654 2655 if (info->ctrl->type == RK3288) { 2656 ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX, 2657 rk3288_grf_gpio6c_iomux | 2658 GPIO6C6_SEL_WRITE_ENABLE); 2659 if (ret) 2660 return ret; 2661 } 2662 2663 return pinctrl_force_default(info->pctl_dev); 2664 } 2665 2666 static SIMPLE_DEV_PM_OPS(rockchip_pinctrl_dev_pm_ops, rockchip_pinctrl_suspend, 2667 rockchip_pinctrl_resume); 2668 2669 static int rockchip_pinctrl_probe(struct platform_device *pdev) 2670 { 2671 struct rockchip_pinctrl *info; 2672 struct device *dev = &pdev->dev; 2673 struct device_node *np = dev->of_node, *node; 2674 struct rockchip_pin_ctrl *ctrl; 2675 struct resource *res; 2676 void __iomem *base; 2677 int ret; 2678 2679 if (!dev->of_node) 2680 return dev_err_probe(dev, -ENODEV, "device tree node not found\n"); 2681 2682 info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL); 2683 if (!info) 2684 return -ENOMEM; 2685 2686 info->dev = dev; 2687 2688 ctrl = rockchip_pinctrl_get_soc_data(info, pdev); 2689 if (!ctrl) 2690 return dev_err_probe(dev, -EINVAL, "driver data not available\n"); 2691 info->ctrl = ctrl; 2692 2693 node = of_parse_phandle(np, "rockchip,grf", 0); 2694 if (node) { 2695 info->regmap_base = syscon_node_to_regmap(node); 2696 if (IS_ERR(info->regmap_base)) 2697 return PTR_ERR(info->regmap_base); 2698 } else { 2699 base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 2700 if (IS_ERR(base)) 2701 return PTR_ERR(base); 2702 2703 rockchip_regmap_config.max_register = resource_size(res) - 4; 2704 rockchip_regmap_config.name = "rockchip,pinctrl"; 2705 info->regmap_base = 2706 devm_regmap_init_mmio(dev, base, &rockchip_regmap_config); 2707 2708 /* to check for the old dt-bindings */ 2709 info->reg_size = resource_size(res); 2710 2711 /* Honor the old binding, with pull registers as 2nd resource */ 2712 if (ctrl->type == RK3188 && info->reg_size < 0x200) { 2713 base = devm_platform_get_and_ioremap_resource(pdev, 1, &res); 2714 if (IS_ERR(base)) 2715 return PTR_ERR(base); 2716 2717 rockchip_regmap_config.max_register = resource_size(res) - 4; 2718 rockchip_regmap_config.name = "rockchip,pinctrl-pull"; 2719 info->regmap_pull = 2720 devm_regmap_init_mmio(dev, base, &rockchip_regmap_config); 2721 } 2722 } 2723 2724 /* try to find the optional reference to the pmu syscon */ 2725 node = of_parse_phandle(np, "rockchip,pmu", 0); 2726 if (node) { 2727 info->regmap_pmu = syscon_node_to_regmap(node); 2728 if (IS_ERR(info->regmap_pmu)) 2729 return PTR_ERR(info->regmap_pmu); 2730 } 2731 2732 ret = rockchip_pinctrl_register(pdev, info); 2733 if (ret) 2734 return ret; 2735 2736 platform_set_drvdata(pdev, info); 2737 2738 ret = of_platform_populate(np, NULL, NULL, &pdev->dev); 2739 if (ret) 2740 return dev_err_probe(dev, ret, "failed to register gpio device\n"); 2741 2742 return 0; 2743 } 2744 2745 static int rockchip_pinctrl_remove(struct platform_device *pdev) 2746 { 2747 struct rockchip_pinctrl *info = platform_get_drvdata(pdev); 2748 struct rockchip_pin_bank *bank; 2749 struct rockchip_pin_output_deferred *cfg; 2750 int i; 2751 2752 of_platform_depopulate(&pdev->dev); 2753 2754 for (i = 0; i < info->ctrl->nr_banks; i++) { 2755 bank = &info->ctrl->pin_banks[i]; 2756 2757 mutex_lock(&bank->deferred_lock); 2758 while (!list_empty(&bank->deferred_output)) { 2759 cfg = list_first_entry(&bank->deferred_output, 2760 struct rockchip_pin_output_deferred, head); 2761 list_del(&cfg->head); 2762 kfree(cfg); 2763 } 2764 mutex_unlock(&bank->deferred_lock); 2765 } 2766 2767 return 0; 2768 } 2769 2770 static struct rockchip_pin_bank px30_pin_banks[] = { 2771 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, 2772 IOMUX_SOURCE_PMU, 2773 IOMUX_SOURCE_PMU, 2774 IOMUX_SOURCE_PMU 2775 ), 2776 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT, 2777 IOMUX_WIDTH_4BIT, 2778 IOMUX_WIDTH_4BIT, 2779 IOMUX_WIDTH_4BIT 2780 ), 2781 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT, 2782 IOMUX_WIDTH_4BIT, 2783 IOMUX_WIDTH_4BIT, 2784 IOMUX_WIDTH_4BIT 2785 ), 2786 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT, 2787 IOMUX_WIDTH_4BIT, 2788 IOMUX_WIDTH_4BIT, 2789 IOMUX_WIDTH_4BIT 2790 ), 2791 }; 2792 2793 static struct rockchip_pin_ctrl px30_pin_ctrl = { 2794 .pin_banks = px30_pin_banks, 2795 .nr_banks = ARRAY_SIZE(px30_pin_banks), 2796 .label = "PX30-GPIO", 2797 .type = PX30, 2798 .grf_mux_offset = 0x0, 2799 .pmu_mux_offset = 0x0, 2800 .iomux_routes = px30_mux_route_data, 2801 .niomux_routes = ARRAY_SIZE(px30_mux_route_data), 2802 .pull_calc_reg = px30_calc_pull_reg_and_bit, 2803 .drv_calc_reg = px30_calc_drv_reg_and_bit, 2804 .schmitt_calc_reg = px30_calc_schmitt_reg_and_bit, 2805 }; 2806 2807 static struct rockchip_pin_bank rv1108_pin_banks[] = { 2808 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, 2809 IOMUX_SOURCE_PMU, 2810 IOMUX_SOURCE_PMU, 2811 IOMUX_SOURCE_PMU), 2812 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0), 2813 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0), 2814 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0), 2815 }; 2816 2817 static struct rockchip_pin_ctrl rv1108_pin_ctrl = { 2818 .pin_banks = rv1108_pin_banks, 2819 .nr_banks = ARRAY_SIZE(rv1108_pin_banks), 2820 .label = "RV1108-GPIO", 2821 .type = RV1108, 2822 .grf_mux_offset = 0x10, 2823 .pmu_mux_offset = 0x0, 2824 .iomux_recalced = rv1108_mux_recalced_data, 2825 .niomux_recalced = ARRAY_SIZE(rv1108_mux_recalced_data), 2826 .pull_calc_reg = rv1108_calc_pull_reg_and_bit, 2827 .drv_calc_reg = rv1108_calc_drv_reg_and_bit, 2828 .schmitt_calc_reg = rv1108_calc_schmitt_reg_and_bit, 2829 }; 2830 2831 static struct rockchip_pin_bank rk2928_pin_banks[] = { 2832 PIN_BANK(0, 32, "gpio0"), 2833 PIN_BANK(1, 32, "gpio1"), 2834 PIN_BANK(2, 32, "gpio2"), 2835 PIN_BANK(3, 32, "gpio3"), 2836 }; 2837 2838 static struct rockchip_pin_ctrl rk2928_pin_ctrl = { 2839 .pin_banks = rk2928_pin_banks, 2840 .nr_banks = ARRAY_SIZE(rk2928_pin_banks), 2841 .label = "RK2928-GPIO", 2842 .type = RK2928, 2843 .grf_mux_offset = 0xa8, 2844 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 2845 }; 2846 2847 static struct rockchip_pin_bank rk3036_pin_banks[] = { 2848 PIN_BANK(0, 32, "gpio0"), 2849 PIN_BANK(1, 32, "gpio1"), 2850 PIN_BANK(2, 32, "gpio2"), 2851 }; 2852 2853 static struct rockchip_pin_ctrl rk3036_pin_ctrl = { 2854 .pin_banks = rk3036_pin_banks, 2855 .nr_banks = ARRAY_SIZE(rk3036_pin_banks), 2856 .label = "RK3036-GPIO", 2857 .type = RK2928, 2858 .grf_mux_offset = 0xa8, 2859 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 2860 }; 2861 2862 static struct rockchip_pin_bank rk3066a_pin_banks[] = { 2863 PIN_BANK(0, 32, "gpio0"), 2864 PIN_BANK(1, 32, "gpio1"), 2865 PIN_BANK(2, 32, "gpio2"), 2866 PIN_BANK(3, 32, "gpio3"), 2867 PIN_BANK(4, 32, "gpio4"), 2868 PIN_BANK(6, 16, "gpio6"), 2869 }; 2870 2871 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = { 2872 .pin_banks = rk3066a_pin_banks, 2873 .nr_banks = ARRAY_SIZE(rk3066a_pin_banks), 2874 .label = "RK3066a-GPIO", 2875 .type = RK2928, 2876 .grf_mux_offset = 0xa8, 2877 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 2878 }; 2879 2880 static struct rockchip_pin_bank rk3066b_pin_banks[] = { 2881 PIN_BANK(0, 32, "gpio0"), 2882 PIN_BANK(1, 32, "gpio1"), 2883 PIN_BANK(2, 32, "gpio2"), 2884 PIN_BANK(3, 32, "gpio3"), 2885 }; 2886 2887 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = { 2888 .pin_banks = rk3066b_pin_banks, 2889 .nr_banks = ARRAY_SIZE(rk3066b_pin_banks), 2890 .label = "RK3066b-GPIO", 2891 .type = RK3066B, 2892 .grf_mux_offset = 0x60, 2893 }; 2894 2895 static struct rockchip_pin_bank rk3128_pin_banks[] = { 2896 PIN_BANK(0, 32, "gpio0"), 2897 PIN_BANK(1, 32, "gpio1"), 2898 PIN_BANK(2, 32, "gpio2"), 2899 PIN_BANK(3, 32, "gpio3"), 2900 }; 2901 2902 static struct rockchip_pin_ctrl rk3128_pin_ctrl = { 2903 .pin_banks = rk3128_pin_banks, 2904 .nr_banks = ARRAY_SIZE(rk3128_pin_banks), 2905 .label = "RK3128-GPIO", 2906 .type = RK3128, 2907 .grf_mux_offset = 0xa8, 2908 .iomux_recalced = rk3128_mux_recalced_data, 2909 .niomux_recalced = ARRAY_SIZE(rk3128_mux_recalced_data), 2910 .iomux_routes = rk3128_mux_route_data, 2911 .niomux_routes = ARRAY_SIZE(rk3128_mux_route_data), 2912 .pull_calc_reg = rk3128_calc_pull_reg_and_bit, 2913 }; 2914 2915 static struct rockchip_pin_bank rk3188_pin_banks[] = { 2916 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0), 2917 PIN_BANK(1, 32, "gpio1"), 2918 PIN_BANK(2, 32, "gpio2"), 2919 PIN_BANK(3, 32, "gpio3"), 2920 }; 2921 2922 static struct rockchip_pin_ctrl rk3188_pin_ctrl = { 2923 .pin_banks = rk3188_pin_banks, 2924 .nr_banks = ARRAY_SIZE(rk3188_pin_banks), 2925 .label = "RK3188-GPIO", 2926 .type = RK3188, 2927 .grf_mux_offset = 0x60, 2928 .iomux_routes = rk3188_mux_route_data, 2929 .niomux_routes = ARRAY_SIZE(rk3188_mux_route_data), 2930 .pull_calc_reg = rk3188_calc_pull_reg_and_bit, 2931 }; 2932 2933 static struct rockchip_pin_bank rk3228_pin_banks[] = { 2934 PIN_BANK(0, 32, "gpio0"), 2935 PIN_BANK(1, 32, "gpio1"), 2936 PIN_BANK(2, 32, "gpio2"), 2937 PIN_BANK(3, 32, "gpio3"), 2938 }; 2939 2940 static struct rockchip_pin_ctrl rk3228_pin_ctrl = { 2941 .pin_banks = rk3228_pin_banks, 2942 .nr_banks = ARRAY_SIZE(rk3228_pin_banks), 2943 .label = "RK3228-GPIO", 2944 .type = RK3288, 2945 .grf_mux_offset = 0x0, 2946 .iomux_routes = rk3228_mux_route_data, 2947 .niomux_routes = ARRAY_SIZE(rk3228_mux_route_data), 2948 .pull_calc_reg = rk3228_calc_pull_reg_and_bit, 2949 .drv_calc_reg = rk3228_calc_drv_reg_and_bit, 2950 }; 2951 2952 static struct rockchip_pin_bank rk3288_pin_banks[] = { 2953 PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU, 2954 IOMUX_SOURCE_PMU, 2955 IOMUX_SOURCE_PMU, 2956 IOMUX_UNROUTED 2957 ), 2958 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED, 2959 IOMUX_UNROUTED, 2960 IOMUX_UNROUTED, 2961 0 2962 ), 2963 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED), 2964 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT), 2965 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT, 2966 IOMUX_WIDTH_4BIT, 2967 0, 2968 0 2969 ), 2970 PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED, 2971 0, 2972 0, 2973 IOMUX_UNROUTED 2974 ), 2975 PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED), 2976 PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0, 2977 0, 2978 IOMUX_WIDTH_4BIT, 2979 IOMUX_UNROUTED 2980 ), 2981 PIN_BANK(8, 16, "gpio8"), 2982 }; 2983 2984 static struct rockchip_pin_ctrl rk3288_pin_ctrl = { 2985 .pin_banks = rk3288_pin_banks, 2986 .nr_banks = ARRAY_SIZE(rk3288_pin_banks), 2987 .label = "RK3288-GPIO", 2988 .type = RK3288, 2989 .grf_mux_offset = 0x0, 2990 .pmu_mux_offset = 0x84, 2991 .iomux_routes = rk3288_mux_route_data, 2992 .niomux_routes = ARRAY_SIZE(rk3288_mux_route_data), 2993 .pull_calc_reg = rk3288_calc_pull_reg_and_bit, 2994 .drv_calc_reg = rk3288_calc_drv_reg_and_bit, 2995 }; 2996 2997 static struct rockchip_pin_bank rk3308_pin_banks[] = { 2998 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_WIDTH_2BIT, 2999 IOMUX_WIDTH_2BIT, 3000 IOMUX_WIDTH_2BIT, 3001 IOMUX_WIDTH_2BIT), 3002 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_2BIT, 3003 IOMUX_WIDTH_2BIT, 3004 IOMUX_WIDTH_2BIT, 3005 IOMUX_WIDTH_2BIT), 3006 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_2BIT, 3007 IOMUX_WIDTH_2BIT, 3008 IOMUX_WIDTH_2BIT, 3009 IOMUX_WIDTH_2BIT), 3010 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_2BIT, 3011 IOMUX_WIDTH_2BIT, 3012 IOMUX_WIDTH_2BIT, 3013 IOMUX_WIDTH_2BIT), 3014 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_2BIT, 3015 IOMUX_WIDTH_2BIT, 3016 IOMUX_WIDTH_2BIT, 3017 IOMUX_WIDTH_2BIT), 3018 }; 3019 3020 static struct rockchip_pin_ctrl rk3308_pin_ctrl = { 3021 .pin_banks = rk3308_pin_banks, 3022 .nr_banks = ARRAY_SIZE(rk3308_pin_banks), 3023 .label = "RK3308-GPIO", 3024 .type = RK3308, 3025 .grf_mux_offset = 0x0, 3026 .iomux_recalced = rk3308_mux_recalced_data, 3027 .niomux_recalced = ARRAY_SIZE(rk3308_mux_recalced_data), 3028 .iomux_routes = rk3308_mux_route_data, 3029 .niomux_routes = ARRAY_SIZE(rk3308_mux_route_data), 3030 .pull_calc_reg = rk3308_calc_pull_reg_and_bit, 3031 .drv_calc_reg = rk3308_calc_drv_reg_and_bit, 3032 .schmitt_calc_reg = rk3308_calc_schmitt_reg_and_bit, 3033 }; 3034 3035 static struct rockchip_pin_bank rk3328_pin_banks[] = { 3036 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0), 3037 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0), 3038 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 3039 IOMUX_WIDTH_3BIT, 3040 IOMUX_WIDTH_3BIT, 3041 0), 3042 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 3043 IOMUX_WIDTH_3BIT, 3044 IOMUX_WIDTH_3BIT, 3045 0, 3046 0), 3047 }; 3048 3049 static struct rockchip_pin_ctrl rk3328_pin_ctrl = { 3050 .pin_banks = rk3328_pin_banks, 3051 .nr_banks = ARRAY_SIZE(rk3328_pin_banks), 3052 .label = "RK3328-GPIO", 3053 .type = RK3288, 3054 .grf_mux_offset = 0x0, 3055 .iomux_recalced = rk3328_mux_recalced_data, 3056 .niomux_recalced = ARRAY_SIZE(rk3328_mux_recalced_data), 3057 .iomux_routes = rk3328_mux_route_data, 3058 .niomux_routes = ARRAY_SIZE(rk3328_mux_route_data), 3059 .pull_calc_reg = rk3228_calc_pull_reg_and_bit, 3060 .drv_calc_reg = rk3228_calc_drv_reg_and_bit, 3061 .schmitt_calc_reg = rk3328_calc_schmitt_reg_and_bit, 3062 }; 3063 3064 static struct rockchip_pin_bank rk3368_pin_banks[] = { 3065 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, 3066 IOMUX_SOURCE_PMU, 3067 IOMUX_SOURCE_PMU, 3068 IOMUX_SOURCE_PMU 3069 ), 3070 PIN_BANK(1, 32, "gpio1"), 3071 PIN_BANK(2, 32, "gpio2"), 3072 PIN_BANK(3, 32, "gpio3"), 3073 }; 3074 3075 static struct rockchip_pin_ctrl rk3368_pin_ctrl = { 3076 .pin_banks = rk3368_pin_banks, 3077 .nr_banks = ARRAY_SIZE(rk3368_pin_banks), 3078 .label = "RK3368-GPIO", 3079 .type = RK3368, 3080 .grf_mux_offset = 0x0, 3081 .pmu_mux_offset = 0x0, 3082 .pull_calc_reg = rk3368_calc_pull_reg_and_bit, 3083 .drv_calc_reg = rk3368_calc_drv_reg_and_bit, 3084 }; 3085 3086 static struct rockchip_pin_bank rk3399_pin_banks[] = { 3087 PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0", 3088 IOMUX_SOURCE_PMU, 3089 IOMUX_SOURCE_PMU, 3090 IOMUX_SOURCE_PMU, 3091 IOMUX_SOURCE_PMU, 3092 DRV_TYPE_IO_1V8_ONLY, 3093 DRV_TYPE_IO_1V8_ONLY, 3094 DRV_TYPE_IO_DEFAULT, 3095 DRV_TYPE_IO_DEFAULT, 3096 0x80, 3097 0x88, 3098 -1, 3099 -1, 3100 PULL_TYPE_IO_1V8_ONLY, 3101 PULL_TYPE_IO_1V8_ONLY, 3102 PULL_TYPE_IO_DEFAULT, 3103 PULL_TYPE_IO_DEFAULT 3104 ), 3105 PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU, 3106 IOMUX_SOURCE_PMU, 3107 IOMUX_SOURCE_PMU, 3108 IOMUX_SOURCE_PMU, 3109 DRV_TYPE_IO_1V8_OR_3V0, 3110 DRV_TYPE_IO_1V8_OR_3V0, 3111 DRV_TYPE_IO_1V8_OR_3V0, 3112 DRV_TYPE_IO_1V8_OR_3V0, 3113 0xa0, 3114 0xa8, 3115 0xb0, 3116 0xb8 3117 ), 3118 PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0, 3119 DRV_TYPE_IO_1V8_OR_3V0, 3120 DRV_TYPE_IO_1V8_ONLY, 3121 DRV_TYPE_IO_1V8_ONLY, 3122 PULL_TYPE_IO_DEFAULT, 3123 PULL_TYPE_IO_DEFAULT, 3124 PULL_TYPE_IO_1V8_ONLY, 3125 PULL_TYPE_IO_1V8_ONLY 3126 ), 3127 PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY, 3128 DRV_TYPE_IO_3V3_ONLY, 3129 DRV_TYPE_IO_3V3_ONLY, 3130 DRV_TYPE_IO_1V8_OR_3V0 3131 ), 3132 PIN_BANK_DRV_FLAGS(4, 32, "gpio4", DRV_TYPE_IO_1V8_OR_3V0, 3133 DRV_TYPE_IO_1V8_3V0_AUTO, 3134 DRV_TYPE_IO_1V8_OR_3V0, 3135 DRV_TYPE_IO_1V8_OR_3V0 3136 ), 3137 }; 3138 3139 static struct rockchip_pin_ctrl rk3399_pin_ctrl = { 3140 .pin_banks = rk3399_pin_banks, 3141 .nr_banks = ARRAY_SIZE(rk3399_pin_banks), 3142 .label = "RK3399-GPIO", 3143 .type = RK3399, 3144 .grf_mux_offset = 0xe000, 3145 .pmu_mux_offset = 0x0, 3146 .grf_drv_offset = 0xe100, 3147 .pmu_drv_offset = 0x80, 3148 .iomux_routes = rk3399_mux_route_data, 3149 .niomux_routes = ARRAY_SIZE(rk3399_mux_route_data), 3150 .pull_calc_reg = rk3399_calc_pull_reg_and_bit, 3151 .drv_calc_reg = rk3399_calc_drv_reg_and_bit, 3152 }; 3153 3154 static struct rockchip_pin_bank rk3568_pin_banks[] = { 3155 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT, 3156 IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT, 3157 IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT, 3158 IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT), 3159 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT, 3160 IOMUX_WIDTH_4BIT, 3161 IOMUX_WIDTH_4BIT, 3162 IOMUX_WIDTH_4BIT), 3163 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT, 3164 IOMUX_WIDTH_4BIT, 3165 IOMUX_WIDTH_4BIT, 3166 IOMUX_WIDTH_4BIT), 3167 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT, 3168 IOMUX_WIDTH_4BIT, 3169 IOMUX_WIDTH_4BIT, 3170 IOMUX_WIDTH_4BIT), 3171 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT, 3172 IOMUX_WIDTH_4BIT, 3173 IOMUX_WIDTH_4BIT, 3174 IOMUX_WIDTH_4BIT), 3175 }; 3176 3177 static struct rockchip_pin_ctrl rk3568_pin_ctrl = { 3178 .pin_banks = rk3568_pin_banks, 3179 .nr_banks = ARRAY_SIZE(rk3568_pin_banks), 3180 .label = "RK3568-GPIO", 3181 .type = RK3568, 3182 .grf_mux_offset = 0x0, 3183 .pmu_mux_offset = 0x0, 3184 .grf_drv_offset = 0x0200, 3185 .pmu_drv_offset = 0x0070, 3186 .iomux_routes = rk3568_mux_route_data, 3187 .niomux_routes = ARRAY_SIZE(rk3568_mux_route_data), 3188 .pull_calc_reg = rk3568_calc_pull_reg_and_bit, 3189 .drv_calc_reg = rk3568_calc_drv_reg_and_bit, 3190 .schmitt_calc_reg = rk3568_calc_schmitt_reg_and_bit, 3191 }; 3192 3193 static const struct of_device_id rockchip_pinctrl_dt_match[] = { 3194 { .compatible = "rockchip,px30-pinctrl", 3195 .data = &px30_pin_ctrl }, 3196 { .compatible = "rockchip,rv1108-pinctrl", 3197 .data = &rv1108_pin_ctrl }, 3198 { .compatible = "rockchip,rk2928-pinctrl", 3199 .data = &rk2928_pin_ctrl }, 3200 { .compatible = "rockchip,rk3036-pinctrl", 3201 .data = &rk3036_pin_ctrl }, 3202 { .compatible = "rockchip,rk3066a-pinctrl", 3203 .data = &rk3066a_pin_ctrl }, 3204 { .compatible = "rockchip,rk3066b-pinctrl", 3205 .data = &rk3066b_pin_ctrl }, 3206 { .compatible = "rockchip,rk3128-pinctrl", 3207 .data = (void *)&rk3128_pin_ctrl }, 3208 { .compatible = "rockchip,rk3188-pinctrl", 3209 .data = &rk3188_pin_ctrl }, 3210 { .compatible = "rockchip,rk3228-pinctrl", 3211 .data = &rk3228_pin_ctrl }, 3212 { .compatible = "rockchip,rk3288-pinctrl", 3213 .data = &rk3288_pin_ctrl }, 3214 { .compatible = "rockchip,rk3308-pinctrl", 3215 .data = &rk3308_pin_ctrl }, 3216 { .compatible = "rockchip,rk3328-pinctrl", 3217 .data = &rk3328_pin_ctrl }, 3218 { .compatible = "rockchip,rk3368-pinctrl", 3219 .data = &rk3368_pin_ctrl }, 3220 { .compatible = "rockchip,rk3399-pinctrl", 3221 .data = &rk3399_pin_ctrl }, 3222 { .compatible = "rockchip,rk3568-pinctrl", 3223 .data = &rk3568_pin_ctrl }, 3224 {}, 3225 }; 3226 3227 static struct platform_driver rockchip_pinctrl_driver = { 3228 .probe = rockchip_pinctrl_probe, 3229 .remove = rockchip_pinctrl_remove, 3230 .driver = { 3231 .name = "rockchip-pinctrl", 3232 .pm = &rockchip_pinctrl_dev_pm_ops, 3233 .of_match_table = rockchip_pinctrl_dt_match, 3234 }, 3235 }; 3236 3237 static int __init rockchip_pinctrl_drv_register(void) 3238 { 3239 return platform_driver_register(&rockchip_pinctrl_driver); 3240 } 3241 postcore_initcall(rockchip_pinctrl_drv_register); 3242 3243 static void __exit rockchip_pinctrl_drv_unregister(void) 3244 { 3245 platform_driver_unregister(&rockchip_pinctrl_driver); 3246 } 3247 module_exit(rockchip_pinctrl_drv_unregister); 3248 3249 MODULE_DESCRIPTION("ROCKCHIP Pin Controller Driver"); 3250 MODULE_LICENSE("GPL"); 3251 MODULE_ALIAS("platform:pinctrl-rockchip"); 3252 MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match); 3253