1 /* 2 * Pinctrl driver for Rockchip SoCs 3 * 4 * Copyright (c) 2013 MundoReader S.L. 5 * Author: Heiko Stuebner <heiko@sntech.de> 6 * 7 * With some ideas taken from pinctrl-samsung: 8 * Copyright (c) 2012 Samsung Electronics Co., Ltd. 9 * http://www.samsung.com 10 * Copyright (c) 2012 Linaro Ltd 11 * http://www.linaro.org 12 * 13 * and pinctrl-at91: 14 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> 15 * 16 * This program is free software; you can redistribute it and/or modify 17 * it under the terms of the GNU General Public License version 2 as published 18 * by the Free Software Foundation. 19 * 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 */ 25 26 #include <linux/module.h> 27 #include <linux/platform_device.h> 28 #include <linux/io.h> 29 #include <linux/bitops.h> 30 #include <linux/gpio.h> 31 #include <linux/of_address.h> 32 #include <linux/of_irq.h> 33 #include <linux/pinctrl/machine.h> 34 #include <linux/pinctrl/pinconf.h> 35 #include <linux/pinctrl/pinctrl.h> 36 #include <linux/pinctrl/pinmux.h> 37 #include <linux/pinctrl/pinconf-generic.h> 38 #include <linux/irqchip/chained_irq.h> 39 #include <linux/clk.h> 40 #include <linux/regmap.h> 41 #include <linux/mfd/syscon.h> 42 #include <dt-bindings/pinctrl/rockchip.h> 43 44 #include "core.h" 45 #include "pinconf.h" 46 47 /* GPIO control registers */ 48 #define GPIO_SWPORT_DR 0x00 49 #define GPIO_SWPORT_DDR 0x04 50 #define GPIO_INTEN 0x30 51 #define GPIO_INTMASK 0x34 52 #define GPIO_INTTYPE_LEVEL 0x38 53 #define GPIO_INT_POLARITY 0x3c 54 #define GPIO_INT_STATUS 0x40 55 #define GPIO_INT_RAWSTATUS 0x44 56 #define GPIO_DEBOUNCE 0x48 57 #define GPIO_PORTS_EOI 0x4c 58 #define GPIO_EXT_PORT 0x50 59 #define GPIO_LS_SYNC 0x60 60 61 enum rockchip_pinctrl_type { 62 RK2928, 63 RK3066B, 64 RK3188, 65 RK3288, 66 }; 67 68 /** 69 * Encode variants of iomux registers into a type variable 70 */ 71 #define IOMUX_GPIO_ONLY BIT(0) 72 #define IOMUX_WIDTH_4BIT BIT(1) 73 #define IOMUX_SOURCE_PMU BIT(2) 74 #define IOMUX_UNROUTED BIT(3) 75 76 /** 77 * @type: iomux variant using IOMUX_* constants 78 * @offset: if initialized to -1 it will be autocalculated, by specifying 79 * an initial offset value the relevant source offset can be reset 80 * to a new value for autocalculating the following iomux registers. 81 */ 82 struct rockchip_iomux { 83 int type; 84 int offset; 85 }; 86 87 /** 88 * @reg_base: register base of the gpio bank 89 * @reg_pull: optional separate register for additional pull settings 90 * @clk: clock of the gpio bank 91 * @irq: interrupt of the gpio bank 92 * @saved_masks: Saved content of GPIO_INTEN at suspend time. 93 * @pin_base: first pin number 94 * @nr_pins: number of pins in this bank 95 * @name: name of the bank 96 * @bank_num: number of the bank, to account for holes 97 * @iomux: array describing the 4 iomux sources of the bank 98 * @valid: are all necessary informations present 99 * @of_node: dt node of this bank 100 * @drvdata: common pinctrl basedata 101 * @domain: irqdomain of the gpio bank 102 * @gpio_chip: gpiolib chip 103 * @grange: gpio range 104 * @slock: spinlock for the gpio bank 105 */ 106 struct rockchip_pin_bank { 107 void __iomem *reg_base; 108 struct regmap *regmap_pull; 109 struct clk *clk; 110 int irq; 111 u32 saved_masks; 112 u32 pin_base; 113 u8 nr_pins; 114 char *name; 115 u8 bank_num; 116 struct rockchip_iomux iomux[4]; 117 bool valid; 118 struct device_node *of_node; 119 struct rockchip_pinctrl *drvdata; 120 struct irq_domain *domain; 121 struct gpio_chip gpio_chip; 122 struct pinctrl_gpio_range grange; 123 spinlock_t slock; 124 u32 toggle_edge_mode; 125 }; 126 127 #define PIN_BANK(id, pins, label) \ 128 { \ 129 .bank_num = id, \ 130 .nr_pins = pins, \ 131 .name = label, \ 132 .iomux = { \ 133 { .offset = -1 }, \ 134 { .offset = -1 }, \ 135 { .offset = -1 }, \ 136 { .offset = -1 }, \ 137 }, \ 138 } 139 140 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \ 141 { \ 142 .bank_num = id, \ 143 .nr_pins = pins, \ 144 .name = label, \ 145 .iomux = { \ 146 { .type = iom0, .offset = -1 }, \ 147 { .type = iom1, .offset = -1 }, \ 148 { .type = iom2, .offset = -1 }, \ 149 { .type = iom3, .offset = -1 }, \ 150 }, \ 151 } 152 153 /** 154 */ 155 struct rockchip_pin_ctrl { 156 struct rockchip_pin_bank *pin_banks; 157 u32 nr_banks; 158 u32 nr_pins; 159 char *label; 160 enum rockchip_pinctrl_type type; 161 int grf_mux_offset; 162 int pmu_mux_offset; 163 void (*pull_calc_reg)(struct rockchip_pin_bank *bank, 164 int pin_num, struct regmap **regmap, 165 int *reg, u8 *bit); 166 }; 167 168 struct rockchip_pin_config { 169 unsigned int func; 170 unsigned long *configs; 171 unsigned int nconfigs; 172 }; 173 174 /** 175 * struct rockchip_pin_group: represent group of pins of a pinmux function. 176 * @name: name of the pin group, used to lookup the group. 177 * @pins: the pins included in this group. 178 * @npins: number of pins included in this group. 179 * @func: the mux function number to be programmed when selected. 180 * @configs: the config values to be set for each pin 181 * @nconfigs: number of configs for each pin 182 */ 183 struct rockchip_pin_group { 184 const char *name; 185 unsigned int npins; 186 unsigned int *pins; 187 struct rockchip_pin_config *data; 188 }; 189 190 /** 191 * struct rockchip_pmx_func: represent a pin function. 192 * @name: name of the pin function, used to lookup the function. 193 * @groups: one or more names of pin groups that provide this function. 194 * @num_groups: number of groups included in @groups. 195 */ 196 struct rockchip_pmx_func { 197 const char *name; 198 const char **groups; 199 u8 ngroups; 200 }; 201 202 struct rockchip_pinctrl { 203 struct regmap *regmap_base; 204 int reg_size; 205 struct regmap *regmap_pull; 206 struct regmap *regmap_pmu; 207 struct device *dev; 208 struct rockchip_pin_ctrl *ctrl; 209 struct pinctrl_desc pctl; 210 struct pinctrl_dev *pctl_dev; 211 struct rockchip_pin_group *groups; 212 unsigned int ngroups; 213 struct rockchip_pmx_func *functions; 214 unsigned int nfunctions; 215 }; 216 217 static struct regmap_config rockchip_regmap_config = { 218 .reg_bits = 32, 219 .val_bits = 32, 220 .reg_stride = 4, 221 }; 222 223 static inline struct rockchip_pin_bank *gc_to_pin_bank(struct gpio_chip *gc) 224 { 225 return container_of(gc, struct rockchip_pin_bank, gpio_chip); 226 } 227 228 static const inline struct rockchip_pin_group *pinctrl_name_to_group( 229 const struct rockchip_pinctrl *info, 230 const char *name) 231 { 232 int i; 233 234 for (i = 0; i < info->ngroups; i++) { 235 if (!strcmp(info->groups[i].name, name)) 236 return &info->groups[i]; 237 } 238 239 return NULL; 240 } 241 242 /* 243 * given a pin number that is local to a pin controller, find out the pin bank 244 * and the register base of the pin bank. 245 */ 246 static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info, 247 unsigned pin) 248 { 249 struct rockchip_pin_bank *b = info->ctrl->pin_banks; 250 251 while (pin >= (b->pin_base + b->nr_pins)) 252 b++; 253 254 return b; 255 } 256 257 static struct rockchip_pin_bank *bank_num_to_bank( 258 struct rockchip_pinctrl *info, 259 unsigned num) 260 { 261 struct rockchip_pin_bank *b = info->ctrl->pin_banks; 262 int i; 263 264 for (i = 0; i < info->ctrl->nr_banks; i++, b++) { 265 if (b->bank_num == num) 266 return b; 267 } 268 269 return ERR_PTR(-EINVAL); 270 } 271 272 /* 273 * Pinctrl_ops handling 274 */ 275 276 static int rockchip_get_groups_count(struct pinctrl_dev *pctldev) 277 { 278 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 279 280 return info->ngroups; 281 } 282 283 static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev, 284 unsigned selector) 285 { 286 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 287 288 return info->groups[selector].name; 289 } 290 291 static int rockchip_get_group_pins(struct pinctrl_dev *pctldev, 292 unsigned selector, const unsigned **pins, 293 unsigned *npins) 294 { 295 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 296 297 if (selector >= info->ngroups) 298 return -EINVAL; 299 300 *pins = info->groups[selector].pins; 301 *npins = info->groups[selector].npins; 302 303 return 0; 304 } 305 306 static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev, 307 struct device_node *np, 308 struct pinctrl_map **map, unsigned *num_maps) 309 { 310 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 311 const struct rockchip_pin_group *grp; 312 struct pinctrl_map *new_map; 313 struct device_node *parent; 314 int map_num = 1; 315 int i; 316 317 /* 318 * first find the group of this node and check if we need to create 319 * config maps for pins 320 */ 321 grp = pinctrl_name_to_group(info, np->name); 322 if (!grp) { 323 dev_err(info->dev, "unable to find group for node %s\n", 324 np->name); 325 return -EINVAL; 326 } 327 328 map_num += grp->npins; 329 new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num, 330 GFP_KERNEL); 331 if (!new_map) 332 return -ENOMEM; 333 334 *map = new_map; 335 *num_maps = map_num; 336 337 /* create mux map */ 338 parent = of_get_parent(np); 339 if (!parent) { 340 devm_kfree(pctldev->dev, new_map); 341 return -EINVAL; 342 } 343 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP; 344 new_map[0].data.mux.function = parent->name; 345 new_map[0].data.mux.group = np->name; 346 of_node_put(parent); 347 348 /* create config map */ 349 new_map++; 350 for (i = 0; i < grp->npins; i++) { 351 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN; 352 new_map[i].data.configs.group_or_pin = 353 pin_get_name(pctldev, grp->pins[i]); 354 new_map[i].data.configs.configs = grp->data[i].configs; 355 new_map[i].data.configs.num_configs = grp->data[i].nconfigs; 356 } 357 358 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n", 359 (*map)->data.mux.function, (*map)->data.mux.group, map_num); 360 361 return 0; 362 } 363 364 static void rockchip_dt_free_map(struct pinctrl_dev *pctldev, 365 struct pinctrl_map *map, unsigned num_maps) 366 { 367 } 368 369 static const struct pinctrl_ops rockchip_pctrl_ops = { 370 .get_groups_count = rockchip_get_groups_count, 371 .get_group_name = rockchip_get_group_name, 372 .get_group_pins = rockchip_get_group_pins, 373 .dt_node_to_map = rockchip_dt_node_to_map, 374 .dt_free_map = rockchip_dt_free_map, 375 }; 376 377 /* 378 * Hardware access 379 */ 380 381 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) 382 { 383 struct rockchip_pinctrl *info = bank->drvdata; 384 int iomux_num = (pin / 8); 385 struct regmap *regmap; 386 unsigned int val; 387 int reg, ret, mask; 388 u8 bit; 389 390 if (iomux_num > 3) 391 return -EINVAL; 392 393 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { 394 dev_err(info->dev, "pin %d is unrouted\n", pin); 395 return -EINVAL; 396 } 397 398 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) 399 return RK_FUNC_GPIO; 400 401 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) 402 ? info->regmap_pmu : info->regmap_base; 403 404 /* get basic quadrupel of mux registers and the correct reg inside */ 405 mask = (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) ? 0xf : 0x3; 406 reg = bank->iomux[iomux_num].offset; 407 if (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) { 408 if ((pin % 8) >= 4) 409 reg += 0x4; 410 bit = (pin % 4) * 4; 411 } else { 412 bit = (pin % 8) * 2; 413 } 414 415 ret = regmap_read(regmap, reg, &val); 416 if (ret) 417 return ret; 418 419 return ((val >> bit) & mask); 420 } 421 422 /* 423 * Set a new mux function for a pin. 424 * 425 * The register is divided into the upper and lower 16 bit. When changing 426 * a value, the previous register value is not read and changed. Instead 427 * it seems the changed bits are marked in the upper 16 bit, while the 428 * changed value gets set in the same offset in the lower 16 bit. 429 * All pin settings seem to be 2 bit wide in both the upper and lower 430 * parts. 431 * @bank: pin bank to change 432 * @pin: pin to change 433 * @mux: new mux function to set 434 */ 435 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) 436 { 437 struct rockchip_pinctrl *info = bank->drvdata; 438 int iomux_num = (pin / 8); 439 struct regmap *regmap; 440 int reg, ret, mask; 441 unsigned long flags; 442 u8 bit; 443 u32 data, rmask; 444 445 if (iomux_num > 3) 446 return -EINVAL; 447 448 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { 449 dev_err(info->dev, "pin %d is unrouted\n", pin); 450 return -EINVAL; 451 } 452 453 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) { 454 if (mux != RK_FUNC_GPIO) { 455 dev_err(info->dev, 456 "pin %d only supports a gpio mux\n", pin); 457 return -ENOTSUPP; 458 } else { 459 return 0; 460 } 461 } 462 463 dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n", 464 bank->bank_num, pin, mux); 465 466 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) 467 ? info->regmap_pmu : info->regmap_base; 468 469 /* get basic quadrupel of mux registers and the correct reg inside */ 470 mask = (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) ? 0xf : 0x3; 471 reg = bank->iomux[iomux_num].offset; 472 if (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) { 473 if ((pin % 8) >= 4) 474 reg += 0x4; 475 bit = (pin % 4) * 4; 476 } else { 477 bit = (pin % 8) * 2; 478 } 479 480 spin_lock_irqsave(&bank->slock, flags); 481 482 data = (mask << (bit + 16)); 483 rmask = data | (data >> 16); 484 data |= (mux & mask) << bit; 485 ret = regmap_update_bits(regmap, reg, rmask, data); 486 487 spin_unlock_irqrestore(&bank->slock, flags); 488 489 return ret; 490 } 491 492 #define RK2928_PULL_OFFSET 0x118 493 #define RK2928_PULL_PINS_PER_REG 16 494 #define RK2928_PULL_BANK_STRIDE 8 495 496 static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 497 int pin_num, struct regmap **regmap, 498 int *reg, u8 *bit) 499 { 500 struct rockchip_pinctrl *info = bank->drvdata; 501 502 *regmap = info->regmap_base; 503 *reg = RK2928_PULL_OFFSET; 504 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; 505 *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4; 506 507 *bit = pin_num % RK2928_PULL_PINS_PER_REG; 508 }; 509 510 #define RK3188_PULL_OFFSET 0x164 511 #define RK3188_PULL_BITS_PER_PIN 2 512 #define RK3188_PULL_PINS_PER_REG 8 513 #define RK3188_PULL_BANK_STRIDE 16 514 #define RK3188_PULL_PMU_OFFSET 0x64 515 516 static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 517 int pin_num, struct regmap **regmap, 518 int *reg, u8 *bit) 519 { 520 struct rockchip_pinctrl *info = bank->drvdata; 521 522 /* The first 12 pins of the first bank are located elsewhere */ 523 if (bank->bank_num == 0 && pin_num < 12) { 524 *regmap = info->regmap_pmu ? info->regmap_pmu 525 : bank->regmap_pull; 526 *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0; 527 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 528 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 529 *bit *= RK3188_PULL_BITS_PER_PIN; 530 } else { 531 *regmap = info->regmap_pull ? info->regmap_pull 532 : info->regmap_base; 533 *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET; 534 535 /* correct the offset, as it is the 2nd pull register */ 536 *reg -= 4; 537 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 538 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 539 540 /* 541 * The bits in these registers have an inverse ordering 542 * with the lowest pin being in bits 15:14 and the highest 543 * pin in bits 1:0 544 */ 545 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG); 546 *bit *= RK3188_PULL_BITS_PER_PIN; 547 } 548 } 549 550 #define RK3288_PULL_OFFSET 0x140 551 static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 552 int pin_num, struct regmap **regmap, 553 int *reg, u8 *bit) 554 { 555 struct rockchip_pinctrl *info = bank->drvdata; 556 557 /* The first 24 pins of the first bank are located in PMU */ 558 if (bank->bank_num == 0) { 559 *regmap = info->regmap_pmu; 560 *reg = RK3188_PULL_PMU_OFFSET; 561 562 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 563 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 564 *bit *= RK3188_PULL_BITS_PER_PIN; 565 } else { 566 *regmap = info->regmap_base; 567 *reg = RK3288_PULL_OFFSET; 568 569 /* correct the offset, as we're starting with the 2nd bank */ 570 *reg -= 0x10; 571 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 572 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 573 574 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 575 *bit *= RK3188_PULL_BITS_PER_PIN; 576 } 577 } 578 579 #define RK3288_DRV_PMU_OFFSET 0x70 580 #define RK3288_DRV_GRF_OFFSET 0x1c0 581 #define RK3288_DRV_BITS_PER_PIN 2 582 #define RK3288_DRV_PINS_PER_REG 8 583 #define RK3288_DRV_BANK_STRIDE 16 584 static int rk3288_drv_list[] = { 2, 4, 8, 12 }; 585 586 static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 587 int pin_num, struct regmap **regmap, 588 int *reg, u8 *bit) 589 { 590 struct rockchip_pinctrl *info = bank->drvdata; 591 592 /* The first 24 pins of the first bank are located in PMU */ 593 if (bank->bank_num == 0) { 594 *regmap = info->regmap_pmu; 595 *reg = RK3288_DRV_PMU_OFFSET; 596 597 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 598 *bit = pin_num % RK3288_DRV_PINS_PER_REG; 599 *bit *= RK3288_DRV_BITS_PER_PIN; 600 } else { 601 *regmap = info->regmap_base; 602 *reg = RK3288_DRV_GRF_OFFSET; 603 604 /* correct the offset, as we're starting with the 2nd bank */ 605 *reg -= 0x10; 606 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 607 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 608 609 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 610 *bit *= RK3288_DRV_BITS_PER_PIN; 611 } 612 } 613 614 static int rk3288_get_drive(struct rockchip_pin_bank *bank, int pin_num) 615 { 616 struct regmap *regmap; 617 int reg, ret; 618 u32 data; 619 u8 bit; 620 621 rk3288_calc_drv_reg_and_bit(bank, pin_num, ®map, ®, &bit); 622 623 ret = regmap_read(regmap, reg, &data); 624 if (ret) 625 return ret; 626 627 data >>= bit; 628 data &= (1 << RK3288_DRV_BITS_PER_PIN) - 1; 629 630 return rk3288_drv_list[data]; 631 } 632 633 static int rk3288_set_drive(struct rockchip_pin_bank *bank, int pin_num, 634 int strength) 635 { 636 struct rockchip_pinctrl *info = bank->drvdata; 637 struct regmap *regmap; 638 unsigned long flags; 639 int reg, ret, i; 640 u32 data, rmask; 641 u8 bit; 642 643 rk3288_calc_drv_reg_and_bit(bank, pin_num, ®map, ®, &bit); 644 645 ret = -EINVAL; 646 for (i = 0; i < ARRAY_SIZE(rk3288_drv_list); i++) { 647 if (rk3288_drv_list[i] == strength) { 648 ret = i; 649 break; 650 } 651 } 652 653 if (ret < 0) { 654 dev_err(info->dev, "unsupported driver strength %d\n", 655 strength); 656 return ret; 657 } 658 659 spin_lock_irqsave(&bank->slock, flags); 660 661 /* enable the write to the equivalent lower bits */ 662 data = ((1 << RK3288_DRV_BITS_PER_PIN) - 1) << (bit + 16); 663 rmask = data | (data >> 16); 664 data |= (ret << bit); 665 666 ret = regmap_update_bits(regmap, reg, rmask, data); 667 spin_unlock_irqrestore(&bank->slock, flags); 668 669 return ret; 670 } 671 672 static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num) 673 { 674 struct rockchip_pinctrl *info = bank->drvdata; 675 struct rockchip_pin_ctrl *ctrl = info->ctrl; 676 struct regmap *regmap; 677 int reg, ret; 678 u8 bit; 679 u32 data; 680 681 /* rk3066b does support any pulls */ 682 if (ctrl->type == RK3066B) 683 return PIN_CONFIG_BIAS_DISABLE; 684 685 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); 686 687 ret = regmap_read(regmap, reg, &data); 688 if (ret) 689 return ret; 690 691 switch (ctrl->type) { 692 case RK2928: 693 return !(data & BIT(bit)) 694 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT 695 : PIN_CONFIG_BIAS_DISABLE; 696 case RK3188: 697 case RK3288: 698 data >>= bit; 699 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1; 700 701 switch (data) { 702 case 0: 703 return PIN_CONFIG_BIAS_DISABLE; 704 case 1: 705 return PIN_CONFIG_BIAS_PULL_UP; 706 case 2: 707 return PIN_CONFIG_BIAS_PULL_DOWN; 708 case 3: 709 return PIN_CONFIG_BIAS_BUS_HOLD; 710 } 711 712 dev_err(info->dev, "unknown pull setting\n"); 713 return -EIO; 714 default: 715 dev_err(info->dev, "unsupported pinctrl type\n"); 716 return -EINVAL; 717 }; 718 } 719 720 static int rockchip_set_pull(struct rockchip_pin_bank *bank, 721 int pin_num, int pull) 722 { 723 struct rockchip_pinctrl *info = bank->drvdata; 724 struct rockchip_pin_ctrl *ctrl = info->ctrl; 725 struct regmap *regmap; 726 int reg, ret; 727 unsigned long flags; 728 u8 bit; 729 u32 data, rmask; 730 731 dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n", 732 bank->bank_num, pin_num, pull); 733 734 /* rk3066b does support any pulls */ 735 if (ctrl->type == RK3066B) 736 return pull ? -EINVAL : 0; 737 738 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); 739 740 switch (ctrl->type) { 741 case RK2928: 742 spin_lock_irqsave(&bank->slock, flags); 743 744 data = BIT(bit + 16); 745 if (pull == PIN_CONFIG_BIAS_DISABLE) 746 data |= BIT(bit); 747 ret = regmap_write(regmap, reg, data); 748 749 spin_unlock_irqrestore(&bank->slock, flags); 750 break; 751 case RK3188: 752 case RK3288: 753 spin_lock_irqsave(&bank->slock, flags); 754 755 /* enable the write to the equivalent lower bits */ 756 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16); 757 rmask = data | (data >> 16); 758 759 switch (pull) { 760 case PIN_CONFIG_BIAS_DISABLE: 761 break; 762 case PIN_CONFIG_BIAS_PULL_UP: 763 data |= (1 << bit); 764 break; 765 case PIN_CONFIG_BIAS_PULL_DOWN: 766 data |= (2 << bit); 767 break; 768 case PIN_CONFIG_BIAS_BUS_HOLD: 769 data |= (3 << bit); 770 break; 771 default: 772 spin_unlock_irqrestore(&bank->slock, flags); 773 dev_err(info->dev, "unsupported pull setting %d\n", 774 pull); 775 return -EINVAL; 776 } 777 778 ret = regmap_update_bits(regmap, reg, rmask, data); 779 780 spin_unlock_irqrestore(&bank->slock, flags); 781 break; 782 default: 783 dev_err(info->dev, "unsupported pinctrl type\n"); 784 return -EINVAL; 785 } 786 787 return ret; 788 } 789 790 /* 791 * Pinmux_ops handling 792 */ 793 794 static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev) 795 { 796 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 797 798 return info->nfunctions; 799 } 800 801 static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev, 802 unsigned selector) 803 { 804 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 805 806 return info->functions[selector].name; 807 } 808 809 static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev, 810 unsigned selector, const char * const **groups, 811 unsigned * const num_groups) 812 { 813 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 814 815 *groups = info->functions[selector].groups; 816 *num_groups = info->functions[selector].ngroups; 817 818 return 0; 819 } 820 821 static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector, 822 unsigned group) 823 { 824 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 825 const unsigned int *pins = info->groups[group].pins; 826 const struct rockchip_pin_config *data = info->groups[group].data; 827 struct rockchip_pin_bank *bank; 828 int cnt, ret = 0; 829 830 dev_dbg(info->dev, "enable function %s group %s\n", 831 info->functions[selector].name, info->groups[group].name); 832 833 /* 834 * for each pin in the pin group selected, program the correspoding pin 835 * pin function number in the config register. 836 */ 837 for (cnt = 0; cnt < info->groups[group].npins; cnt++) { 838 bank = pin_to_bank(info, pins[cnt]); 839 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 840 data[cnt].func); 841 if (ret) 842 break; 843 } 844 845 if (ret) { 846 /* revert the already done pin settings */ 847 for (cnt--; cnt >= 0; cnt--) 848 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0); 849 850 return ret; 851 } 852 853 return 0; 854 } 855 856 /* 857 * The calls to gpio_direction_output() and gpio_direction_input() 858 * leads to this function call (via the pinctrl_gpio_direction_{input|output}() 859 * function called from the gpiolib interface). 860 */ 861 static int _rockchip_pmx_gpio_set_direction(struct gpio_chip *chip, 862 int pin, bool input) 863 { 864 struct rockchip_pin_bank *bank; 865 int ret; 866 unsigned long flags; 867 u32 data; 868 869 bank = gc_to_pin_bank(chip); 870 871 ret = rockchip_set_mux(bank, pin, RK_FUNC_GPIO); 872 if (ret < 0) 873 return ret; 874 875 spin_lock_irqsave(&bank->slock, flags); 876 877 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); 878 /* set bit to 1 for output, 0 for input */ 879 if (!input) 880 data |= BIT(pin); 881 else 882 data &= ~BIT(pin); 883 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR); 884 885 spin_unlock_irqrestore(&bank->slock, flags); 886 887 return 0; 888 } 889 890 static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, 891 struct pinctrl_gpio_range *range, 892 unsigned offset, bool input) 893 { 894 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 895 struct gpio_chip *chip; 896 int pin; 897 898 chip = range->gc; 899 pin = offset - chip->base; 900 dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n", 901 offset, range->name, pin, input ? "input" : "output"); 902 903 return _rockchip_pmx_gpio_set_direction(chip, offset - chip->base, 904 input); 905 } 906 907 static const struct pinmux_ops rockchip_pmx_ops = { 908 .get_functions_count = rockchip_pmx_get_funcs_count, 909 .get_function_name = rockchip_pmx_get_func_name, 910 .get_function_groups = rockchip_pmx_get_groups, 911 .set_mux = rockchip_pmx_set, 912 .gpio_set_direction = rockchip_pmx_gpio_set_direction, 913 }; 914 915 /* 916 * Pinconf_ops handling 917 */ 918 919 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl, 920 enum pin_config_param pull) 921 { 922 switch (ctrl->type) { 923 case RK2928: 924 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT || 925 pull == PIN_CONFIG_BIAS_DISABLE); 926 case RK3066B: 927 return pull ? false : true; 928 case RK3188: 929 case RK3288: 930 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT); 931 } 932 933 return false; 934 } 935 936 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value); 937 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset); 938 939 /* set the pin config settings for a specified pin */ 940 static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 941 unsigned long *configs, unsigned num_configs) 942 { 943 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 944 struct rockchip_pin_bank *bank = pin_to_bank(info, pin); 945 enum pin_config_param param; 946 u16 arg; 947 int i; 948 int rc; 949 950 for (i = 0; i < num_configs; i++) { 951 param = pinconf_to_config_param(configs[i]); 952 arg = pinconf_to_config_argument(configs[i]); 953 954 switch (param) { 955 case PIN_CONFIG_BIAS_DISABLE: 956 rc = rockchip_set_pull(bank, pin - bank->pin_base, 957 param); 958 if (rc) 959 return rc; 960 break; 961 case PIN_CONFIG_BIAS_PULL_UP: 962 case PIN_CONFIG_BIAS_PULL_DOWN: 963 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: 964 case PIN_CONFIG_BIAS_BUS_HOLD: 965 if (!rockchip_pinconf_pull_valid(info->ctrl, param)) 966 return -ENOTSUPP; 967 968 if (!arg) 969 return -EINVAL; 970 971 rc = rockchip_set_pull(bank, pin - bank->pin_base, 972 param); 973 if (rc) 974 return rc; 975 break; 976 case PIN_CONFIG_OUTPUT: 977 rockchip_gpio_set(&bank->gpio_chip, 978 pin - bank->pin_base, arg); 979 rc = _rockchip_pmx_gpio_set_direction(&bank->gpio_chip, 980 pin - bank->pin_base, false); 981 if (rc) 982 return rc; 983 break; 984 case PIN_CONFIG_DRIVE_STRENGTH: 985 /* rk3288 is the first with per-pin drive-strength */ 986 if (info->ctrl->type != RK3288) 987 return -ENOTSUPP; 988 989 rc = rk3288_set_drive(bank, pin - bank->pin_base, arg); 990 if (rc < 0) 991 return rc; 992 break; 993 default: 994 return -ENOTSUPP; 995 break; 996 } 997 } /* for each config */ 998 999 return 0; 1000 } 1001 1002 /* get the pin config settings for a specified pin */ 1003 static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, 1004 unsigned long *config) 1005 { 1006 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1007 struct rockchip_pin_bank *bank = pin_to_bank(info, pin); 1008 enum pin_config_param param = pinconf_to_config_param(*config); 1009 u16 arg; 1010 int rc; 1011 1012 switch (param) { 1013 case PIN_CONFIG_BIAS_DISABLE: 1014 if (rockchip_get_pull(bank, pin - bank->pin_base) != param) 1015 return -EINVAL; 1016 1017 arg = 0; 1018 break; 1019 case PIN_CONFIG_BIAS_PULL_UP: 1020 case PIN_CONFIG_BIAS_PULL_DOWN: 1021 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: 1022 case PIN_CONFIG_BIAS_BUS_HOLD: 1023 if (!rockchip_pinconf_pull_valid(info->ctrl, param)) 1024 return -ENOTSUPP; 1025 1026 if (rockchip_get_pull(bank, pin - bank->pin_base) != param) 1027 return -EINVAL; 1028 1029 arg = 1; 1030 break; 1031 case PIN_CONFIG_OUTPUT: 1032 rc = rockchip_get_mux(bank, pin - bank->pin_base); 1033 if (rc != RK_FUNC_GPIO) 1034 return -EINVAL; 1035 1036 rc = rockchip_gpio_get(&bank->gpio_chip, pin - bank->pin_base); 1037 if (rc < 0) 1038 return rc; 1039 1040 arg = rc ? 1 : 0; 1041 break; 1042 case PIN_CONFIG_DRIVE_STRENGTH: 1043 /* rk3288 is the first with per-pin drive-strength */ 1044 if (info->ctrl->type != RK3288) 1045 return -ENOTSUPP; 1046 1047 rc = rk3288_get_drive(bank, pin - bank->pin_base); 1048 if (rc < 0) 1049 return rc; 1050 1051 arg = rc; 1052 break; 1053 default: 1054 return -ENOTSUPP; 1055 break; 1056 } 1057 1058 *config = pinconf_to_config_packed(param, arg); 1059 1060 return 0; 1061 } 1062 1063 static const struct pinconf_ops rockchip_pinconf_ops = { 1064 .pin_config_get = rockchip_pinconf_get, 1065 .pin_config_set = rockchip_pinconf_set, 1066 .is_generic = true, 1067 }; 1068 1069 static const struct of_device_id rockchip_bank_match[] = { 1070 { .compatible = "rockchip,gpio-bank" }, 1071 { .compatible = "rockchip,rk3188-gpio-bank0" }, 1072 {}, 1073 }; 1074 1075 static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info, 1076 struct device_node *np) 1077 { 1078 struct device_node *child; 1079 1080 for_each_child_of_node(np, child) { 1081 if (of_match_node(rockchip_bank_match, child)) 1082 continue; 1083 1084 info->nfunctions++; 1085 info->ngroups += of_get_child_count(child); 1086 } 1087 } 1088 1089 static int rockchip_pinctrl_parse_groups(struct device_node *np, 1090 struct rockchip_pin_group *grp, 1091 struct rockchip_pinctrl *info, 1092 u32 index) 1093 { 1094 struct rockchip_pin_bank *bank; 1095 int size; 1096 const __be32 *list; 1097 int num; 1098 int i, j; 1099 int ret; 1100 1101 dev_dbg(info->dev, "group(%d): %s\n", index, np->name); 1102 1103 /* Initialise group */ 1104 grp->name = np->name; 1105 1106 /* 1107 * the binding format is rockchip,pins = <bank pin mux CONFIG>, 1108 * do sanity check and calculate pins number 1109 */ 1110 list = of_get_property(np, "rockchip,pins", &size); 1111 /* we do not check return since it's safe node passed down */ 1112 size /= sizeof(*list); 1113 if (!size || size % 4) { 1114 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n"); 1115 return -EINVAL; 1116 } 1117 1118 grp->npins = size / 4; 1119 1120 grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int), 1121 GFP_KERNEL); 1122 grp->data = devm_kzalloc(info->dev, grp->npins * 1123 sizeof(struct rockchip_pin_config), 1124 GFP_KERNEL); 1125 if (!grp->pins || !grp->data) 1126 return -ENOMEM; 1127 1128 for (i = 0, j = 0; i < size; i += 4, j++) { 1129 const __be32 *phandle; 1130 struct device_node *np_config; 1131 1132 num = be32_to_cpu(*list++); 1133 bank = bank_num_to_bank(info, num); 1134 if (IS_ERR(bank)) 1135 return PTR_ERR(bank); 1136 1137 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++); 1138 grp->data[j].func = be32_to_cpu(*list++); 1139 1140 phandle = list++; 1141 if (!phandle) 1142 return -EINVAL; 1143 1144 np_config = of_find_node_by_phandle(be32_to_cpup(phandle)); 1145 ret = pinconf_generic_parse_dt_config(np_config, NULL, 1146 &grp->data[j].configs, &grp->data[j].nconfigs); 1147 if (ret) 1148 return ret; 1149 } 1150 1151 return 0; 1152 } 1153 1154 static int rockchip_pinctrl_parse_functions(struct device_node *np, 1155 struct rockchip_pinctrl *info, 1156 u32 index) 1157 { 1158 struct device_node *child; 1159 struct rockchip_pmx_func *func; 1160 struct rockchip_pin_group *grp; 1161 int ret; 1162 static u32 grp_index; 1163 u32 i = 0; 1164 1165 dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name); 1166 1167 func = &info->functions[index]; 1168 1169 /* Initialise function */ 1170 func->name = np->name; 1171 func->ngroups = of_get_child_count(np); 1172 if (func->ngroups <= 0) 1173 return 0; 1174 1175 func->groups = devm_kzalloc(info->dev, 1176 func->ngroups * sizeof(char *), GFP_KERNEL); 1177 if (!func->groups) 1178 return -ENOMEM; 1179 1180 for_each_child_of_node(np, child) { 1181 func->groups[i] = child->name; 1182 grp = &info->groups[grp_index++]; 1183 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++); 1184 if (ret) 1185 return ret; 1186 } 1187 1188 return 0; 1189 } 1190 1191 static int rockchip_pinctrl_parse_dt(struct platform_device *pdev, 1192 struct rockchip_pinctrl *info) 1193 { 1194 struct device *dev = &pdev->dev; 1195 struct device_node *np = dev->of_node; 1196 struct device_node *child; 1197 int ret; 1198 int i; 1199 1200 rockchip_pinctrl_child_count(info, np); 1201 1202 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions); 1203 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups); 1204 1205 info->functions = devm_kzalloc(dev, info->nfunctions * 1206 sizeof(struct rockchip_pmx_func), 1207 GFP_KERNEL); 1208 if (!info->functions) { 1209 dev_err(dev, "failed to allocate memory for function list\n"); 1210 return -EINVAL; 1211 } 1212 1213 info->groups = devm_kzalloc(dev, info->ngroups * 1214 sizeof(struct rockchip_pin_group), 1215 GFP_KERNEL); 1216 if (!info->groups) { 1217 dev_err(dev, "failed allocate memory for ping group list\n"); 1218 return -EINVAL; 1219 } 1220 1221 i = 0; 1222 1223 for_each_child_of_node(np, child) { 1224 if (of_match_node(rockchip_bank_match, child)) 1225 continue; 1226 1227 ret = rockchip_pinctrl_parse_functions(child, info, i++); 1228 if (ret) { 1229 dev_err(&pdev->dev, "failed to parse function\n"); 1230 return ret; 1231 } 1232 } 1233 1234 return 0; 1235 } 1236 1237 static int rockchip_pinctrl_register(struct platform_device *pdev, 1238 struct rockchip_pinctrl *info) 1239 { 1240 struct pinctrl_desc *ctrldesc = &info->pctl; 1241 struct pinctrl_pin_desc *pindesc, *pdesc; 1242 struct rockchip_pin_bank *pin_bank; 1243 int pin, bank, ret; 1244 int k; 1245 1246 ctrldesc->name = "rockchip-pinctrl"; 1247 ctrldesc->owner = THIS_MODULE; 1248 ctrldesc->pctlops = &rockchip_pctrl_ops; 1249 ctrldesc->pmxops = &rockchip_pmx_ops; 1250 ctrldesc->confops = &rockchip_pinconf_ops; 1251 1252 pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) * 1253 info->ctrl->nr_pins, GFP_KERNEL); 1254 if (!pindesc) { 1255 dev_err(&pdev->dev, "mem alloc for pin descriptors failed\n"); 1256 return -ENOMEM; 1257 } 1258 ctrldesc->pins = pindesc; 1259 ctrldesc->npins = info->ctrl->nr_pins; 1260 1261 pdesc = pindesc; 1262 for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) { 1263 pin_bank = &info->ctrl->pin_banks[bank]; 1264 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) { 1265 pdesc->number = k; 1266 pdesc->name = kasprintf(GFP_KERNEL, "%s-%d", 1267 pin_bank->name, pin); 1268 pdesc++; 1269 } 1270 } 1271 1272 ret = rockchip_pinctrl_parse_dt(pdev, info); 1273 if (ret) 1274 return ret; 1275 1276 info->pctl_dev = pinctrl_register(ctrldesc, &pdev->dev, info); 1277 if (!info->pctl_dev) { 1278 dev_err(&pdev->dev, "could not register pinctrl driver\n"); 1279 return -EINVAL; 1280 } 1281 1282 for (bank = 0; bank < info->ctrl->nr_banks; ++bank) { 1283 pin_bank = &info->ctrl->pin_banks[bank]; 1284 pin_bank->grange.name = pin_bank->name; 1285 pin_bank->grange.id = bank; 1286 pin_bank->grange.pin_base = pin_bank->pin_base; 1287 pin_bank->grange.base = pin_bank->gpio_chip.base; 1288 pin_bank->grange.npins = pin_bank->gpio_chip.ngpio; 1289 pin_bank->grange.gc = &pin_bank->gpio_chip; 1290 pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange); 1291 } 1292 1293 return 0; 1294 } 1295 1296 /* 1297 * GPIO handling 1298 */ 1299 1300 static int rockchip_gpio_request(struct gpio_chip *chip, unsigned offset) 1301 { 1302 return pinctrl_request_gpio(chip->base + offset); 1303 } 1304 1305 static void rockchip_gpio_free(struct gpio_chip *chip, unsigned offset) 1306 { 1307 pinctrl_free_gpio(chip->base + offset); 1308 } 1309 1310 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value) 1311 { 1312 struct rockchip_pin_bank *bank = gc_to_pin_bank(gc); 1313 void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR; 1314 unsigned long flags; 1315 u32 data; 1316 1317 spin_lock_irqsave(&bank->slock, flags); 1318 1319 data = readl(reg); 1320 data &= ~BIT(offset); 1321 if (value) 1322 data |= BIT(offset); 1323 writel(data, reg); 1324 1325 spin_unlock_irqrestore(&bank->slock, flags); 1326 } 1327 1328 /* 1329 * Returns the level of the pin for input direction and setting of the DR 1330 * register for output gpios. 1331 */ 1332 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset) 1333 { 1334 struct rockchip_pin_bank *bank = gc_to_pin_bank(gc); 1335 u32 data; 1336 1337 data = readl(bank->reg_base + GPIO_EXT_PORT); 1338 data >>= offset; 1339 data &= 1; 1340 return data; 1341 } 1342 1343 /* 1344 * gpiolib gpio_direction_input callback function. The setting of the pin 1345 * mux function as 'gpio input' will be handled by the pinctrl susbsystem 1346 * interface. 1347 */ 1348 static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset) 1349 { 1350 return pinctrl_gpio_direction_input(gc->base + offset); 1351 } 1352 1353 /* 1354 * gpiolib gpio_direction_output callback function. The setting of the pin 1355 * mux function as 'gpio output' will be handled by the pinctrl susbsystem 1356 * interface. 1357 */ 1358 static int rockchip_gpio_direction_output(struct gpio_chip *gc, 1359 unsigned offset, int value) 1360 { 1361 rockchip_gpio_set(gc, offset, value); 1362 return pinctrl_gpio_direction_output(gc->base + offset); 1363 } 1364 1365 /* 1366 * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin 1367 * and a virtual IRQ, if not already present. 1368 */ 1369 static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset) 1370 { 1371 struct rockchip_pin_bank *bank = gc_to_pin_bank(gc); 1372 unsigned int virq; 1373 1374 if (!bank->domain) 1375 return -ENXIO; 1376 1377 virq = irq_create_mapping(bank->domain, offset); 1378 1379 return (virq) ? : -ENXIO; 1380 } 1381 1382 static const struct gpio_chip rockchip_gpiolib_chip = { 1383 .request = rockchip_gpio_request, 1384 .free = rockchip_gpio_free, 1385 .set = rockchip_gpio_set, 1386 .get = rockchip_gpio_get, 1387 .direction_input = rockchip_gpio_direction_input, 1388 .direction_output = rockchip_gpio_direction_output, 1389 .to_irq = rockchip_gpio_to_irq, 1390 .owner = THIS_MODULE, 1391 }; 1392 1393 /* 1394 * Interrupt handling 1395 */ 1396 1397 static void rockchip_irq_demux(unsigned int irq, struct irq_desc *desc) 1398 { 1399 struct irq_chip *chip = irq_get_chip(irq); 1400 struct rockchip_pin_bank *bank = irq_get_handler_data(irq); 1401 u32 pend; 1402 1403 dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name); 1404 1405 chained_irq_enter(chip, desc); 1406 1407 pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS); 1408 1409 while (pend) { 1410 unsigned int virq; 1411 1412 irq = __ffs(pend); 1413 pend &= ~BIT(irq); 1414 virq = irq_linear_revmap(bank->domain, irq); 1415 1416 if (!virq) { 1417 dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq); 1418 continue; 1419 } 1420 1421 dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq); 1422 1423 /* 1424 * Triggering IRQ on both rising and falling edge 1425 * needs manual intervention. 1426 */ 1427 if (bank->toggle_edge_mode & BIT(irq)) { 1428 u32 data, data_old, polarity; 1429 unsigned long flags; 1430 1431 data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT); 1432 do { 1433 spin_lock_irqsave(&bank->slock, flags); 1434 1435 polarity = readl_relaxed(bank->reg_base + 1436 GPIO_INT_POLARITY); 1437 if (data & BIT(irq)) 1438 polarity &= ~BIT(irq); 1439 else 1440 polarity |= BIT(irq); 1441 writel(polarity, 1442 bank->reg_base + GPIO_INT_POLARITY); 1443 1444 spin_unlock_irqrestore(&bank->slock, flags); 1445 1446 data_old = data; 1447 data = readl_relaxed(bank->reg_base + 1448 GPIO_EXT_PORT); 1449 } while ((data & BIT(irq)) != (data_old & BIT(irq))); 1450 } 1451 1452 generic_handle_irq(virq); 1453 } 1454 1455 chained_irq_exit(chip, desc); 1456 } 1457 1458 static int rockchip_irq_set_type(struct irq_data *d, unsigned int type) 1459 { 1460 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 1461 struct rockchip_pin_bank *bank = gc->private; 1462 u32 mask = BIT(d->hwirq); 1463 u32 polarity; 1464 u32 level; 1465 u32 data; 1466 unsigned long flags; 1467 int ret; 1468 1469 /* make sure the pin is configured as gpio input */ 1470 ret = rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO); 1471 if (ret < 0) 1472 return ret; 1473 1474 spin_lock_irqsave(&bank->slock, flags); 1475 1476 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); 1477 data &= ~mask; 1478 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR); 1479 1480 spin_unlock_irqrestore(&bank->slock, flags); 1481 1482 if (type & IRQ_TYPE_EDGE_BOTH) 1483 __irq_set_handler_locked(d->irq, handle_edge_irq); 1484 else 1485 __irq_set_handler_locked(d->irq, handle_level_irq); 1486 1487 spin_lock_irqsave(&bank->slock, flags); 1488 irq_gc_lock(gc); 1489 1490 level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL); 1491 polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY); 1492 1493 switch (type) { 1494 case IRQ_TYPE_EDGE_BOTH: 1495 bank->toggle_edge_mode |= mask; 1496 level |= mask; 1497 1498 /* 1499 * Determine gpio state. If 1 next interrupt should be falling 1500 * otherwise rising. 1501 */ 1502 data = readl(bank->reg_base + GPIO_EXT_PORT); 1503 if (data & mask) 1504 polarity &= ~mask; 1505 else 1506 polarity |= mask; 1507 break; 1508 case IRQ_TYPE_EDGE_RISING: 1509 bank->toggle_edge_mode &= ~mask; 1510 level |= mask; 1511 polarity |= mask; 1512 break; 1513 case IRQ_TYPE_EDGE_FALLING: 1514 bank->toggle_edge_mode &= ~mask; 1515 level |= mask; 1516 polarity &= ~mask; 1517 break; 1518 case IRQ_TYPE_LEVEL_HIGH: 1519 bank->toggle_edge_mode &= ~mask; 1520 level &= ~mask; 1521 polarity |= mask; 1522 break; 1523 case IRQ_TYPE_LEVEL_LOW: 1524 bank->toggle_edge_mode &= ~mask; 1525 level &= ~mask; 1526 polarity &= ~mask; 1527 break; 1528 default: 1529 irq_gc_unlock(gc); 1530 spin_unlock_irqrestore(&bank->slock, flags); 1531 return -EINVAL; 1532 } 1533 1534 writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL); 1535 writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY); 1536 1537 irq_gc_unlock(gc); 1538 spin_unlock_irqrestore(&bank->slock, flags); 1539 1540 return 0; 1541 } 1542 1543 static void rockchip_irq_suspend(struct irq_data *d) 1544 { 1545 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 1546 struct rockchip_pin_bank *bank = gc->private; 1547 1548 bank->saved_masks = irq_reg_readl(gc, GPIO_INTMASK); 1549 irq_reg_writel(gc, ~gc->wake_active, GPIO_INTMASK); 1550 } 1551 1552 static void rockchip_irq_resume(struct irq_data *d) 1553 { 1554 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 1555 struct rockchip_pin_bank *bank = gc->private; 1556 1557 irq_reg_writel(gc, bank->saved_masks, GPIO_INTMASK); 1558 } 1559 1560 static int rockchip_interrupts_register(struct platform_device *pdev, 1561 struct rockchip_pinctrl *info) 1562 { 1563 struct rockchip_pin_ctrl *ctrl = info->ctrl; 1564 struct rockchip_pin_bank *bank = ctrl->pin_banks; 1565 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; 1566 struct irq_chip_generic *gc; 1567 int ret; 1568 int i; 1569 1570 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 1571 if (!bank->valid) { 1572 dev_warn(&pdev->dev, "bank %s is not valid\n", 1573 bank->name); 1574 continue; 1575 } 1576 1577 bank->domain = irq_domain_add_linear(bank->of_node, 32, 1578 &irq_generic_chip_ops, NULL); 1579 if (!bank->domain) { 1580 dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n", 1581 bank->name); 1582 continue; 1583 } 1584 1585 ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1, 1586 "rockchip_gpio_irq", handle_level_irq, 1587 clr, 0, IRQ_GC_INIT_MASK_CACHE); 1588 if (ret) { 1589 dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n", 1590 bank->name); 1591 irq_domain_remove(bank->domain); 1592 continue; 1593 } 1594 1595 /* 1596 * Linux assumes that all interrupts start out disabled/masked. 1597 * Our driver only uses the concept of masked and always keeps 1598 * things enabled, so for us that's all masked and all enabled. 1599 */ 1600 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTMASK); 1601 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTEN); 1602 1603 gc = irq_get_domain_generic_chip(bank->domain, 0); 1604 gc->reg_base = bank->reg_base; 1605 gc->private = bank; 1606 gc->chip_types[0].regs.mask = GPIO_INTMASK; 1607 gc->chip_types[0].regs.ack = GPIO_PORTS_EOI; 1608 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit; 1609 gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit; 1610 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit; 1611 gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake; 1612 gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend; 1613 gc->chip_types[0].chip.irq_resume = rockchip_irq_resume; 1614 gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type; 1615 gc->wake_enabled = IRQ_MSK(bank->nr_pins); 1616 1617 irq_set_handler_data(bank->irq, bank); 1618 irq_set_chained_handler(bank->irq, rockchip_irq_demux); 1619 } 1620 1621 return 0; 1622 } 1623 1624 static int rockchip_gpiolib_register(struct platform_device *pdev, 1625 struct rockchip_pinctrl *info) 1626 { 1627 struct rockchip_pin_ctrl *ctrl = info->ctrl; 1628 struct rockchip_pin_bank *bank = ctrl->pin_banks; 1629 struct gpio_chip *gc; 1630 int ret; 1631 int i; 1632 1633 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 1634 if (!bank->valid) { 1635 dev_warn(&pdev->dev, "bank %s is not valid\n", 1636 bank->name); 1637 continue; 1638 } 1639 1640 bank->gpio_chip = rockchip_gpiolib_chip; 1641 1642 gc = &bank->gpio_chip; 1643 gc->base = bank->pin_base; 1644 gc->ngpio = bank->nr_pins; 1645 gc->dev = &pdev->dev; 1646 gc->of_node = bank->of_node; 1647 gc->label = bank->name; 1648 1649 ret = gpiochip_add(gc); 1650 if (ret) { 1651 dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n", 1652 gc->label, ret); 1653 goto fail; 1654 } 1655 } 1656 1657 rockchip_interrupts_register(pdev, info); 1658 1659 return 0; 1660 1661 fail: 1662 for (--i, --bank; i >= 0; --i, --bank) { 1663 if (!bank->valid) 1664 continue; 1665 gpiochip_remove(&bank->gpio_chip); 1666 } 1667 return ret; 1668 } 1669 1670 static int rockchip_gpiolib_unregister(struct platform_device *pdev, 1671 struct rockchip_pinctrl *info) 1672 { 1673 struct rockchip_pin_ctrl *ctrl = info->ctrl; 1674 struct rockchip_pin_bank *bank = ctrl->pin_banks; 1675 int i; 1676 1677 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 1678 if (!bank->valid) 1679 continue; 1680 gpiochip_remove(&bank->gpio_chip); 1681 } 1682 1683 return 0; 1684 } 1685 1686 static int rockchip_get_bank_data(struct rockchip_pin_bank *bank, 1687 struct rockchip_pinctrl *info) 1688 { 1689 struct resource res; 1690 void __iomem *base; 1691 1692 if (of_address_to_resource(bank->of_node, 0, &res)) { 1693 dev_err(info->dev, "cannot find IO resource for bank\n"); 1694 return -ENOENT; 1695 } 1696 1697 bank->reg_base = devm_ioremap_resource(info->dev, &res); 1698 if (IS_ERR(bank->reg_base)) 1699 return PTR_ERR(bank->reg_base); 1700 1701 /* 1702 * special case, where parts of the pull setting-registers are 1703 * part of the PMU register space 1704 */ 1705 if (of_device_is_compatible(bank->of_node, 1706 "rockchip,rk3188-gpio-bank0")) { 1707 struct device_node *node; 1708 1709 node = of_parse_phandle(bank->of_node->parent, 1710 "rockchip,pmu", 0); 1711 if (!node) { 1712 if (of_address_to_resource(bank->of_node, 1, &res)) { 1713 dev_err(info->dev, "cannot find IO resource for bank\n"); 1714 return -ENOENT; 1715 } 1716 1717 base = devm_ioremap_resource(info->dev, &res); 1718 if (IS_ERR(base)) 1719 return PTR_ERR(base); 1720 rockchip_regmap_config.max_register = 1721 resource_size(&res) - 4; 1722 rockchip_regmap_config.name = 1723 "rockchip,rk3188-gpio-bank0-pull"; 1724 bank->regmap_pull = devm_regmap_init_mmio(info->dev, 1725 base, 1726 &rockchip_regmap_config); 1727 } 1728 } 1729 1730 bank->irq = irq_of_parse_and_map(bank->of_node, 0); 1731 1732 bank->clk = of_clk_get(bank->of_node, 0); 1733 if (IS_ERR(bank->clk)) 1734 return PTR_ERR(bank->clk); 1735 1736 return clk_prepare_enable(bank->clk); 1737 } 1738 1739 static const struct of_device_id rockchip_pinctrl_dt_match[]; 1740 1741 /* retrieve the soc specific data */ 1742 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data( 1743 struct rockchip_pinctrl *d, 1744 struct platform_device *pdev) 1745 { 1746 const struct of_device_id *match; 1747 struct device_node *node = pdev->dev.of_node; 1748 struct device_node *np; 1749 struct rockchip_pin_ctrl *ctrl; 1750 struct rockchip_pin_bank *bank; 1751 int grf_offs, pmu_offs, i, j; 1752 1753 match = of_match_node(rockchip_pinctrl_dt_match, node); 1754 ctrl = (struct rockchip_pin_ctrl *)match->data; 1755 1756 for_each_child_of_node(node, np) { 1757 if (!of_find_property(np, "gpio-controller", NULL)) 1758 continue; 1759 1760 bank = ctrl->pin_banks; 1761 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 1762 if (!strcmp(bank->name, np->name)) { 1763 bank->of_node = np; 1764 1765 if (!rockchip_get_bank_data(bank, d)) 1766 bank->valid = true; 1767 1768 break; 1769 } 1770 } 1771 } 1772 1773 grf_offs = ctrl->grf_mux_offset; 1774 pmu_offs = ctrl->pmu_mux_offset; 1775 bank = ctrl->pin_banks; 1776 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 1777 int bank_pins = 0; 1778 1779 spin_lock_init(&bank->slock); 1780 bank->drvdata = d; 1781 bank->pin_base = ctrl->nr_pins; 1782 ctrl->nr_pins += bank->nr_pins; 1783 1784 /* calculate iomux offsets */ 1785 for (j = 0; j < 4; j++) { 1786 struct rockchip_iomux *iom = &bank->iomux[j]; 1787 int inc; 1788 1789 if (bank_pins >= bank->nr_pins) 1790 break; 1791 1792 /* preset offset value, set new start value */ 1793 if (iom->offset >= 0) { 1794 if (iom->type & IOMUX_SOURCE_PMU) 1795 pmu_offs = iom->offset; 1796 else 1797 grf_offs = iom->offset; 1798 } else { /* set current offset */ 1799 iom->offset = (iom->type & IOMUX_SOURCE_PMU) ? 1800 pmu_offs : grf_offs; 1801 } 1802 1803 dev_dbg(d->dev, "bank %d, iomux %d has offset 0x%x\n", 1804 i, j, iom->offset); 1805 1806 /* 1807 * Increase offset according to iomux width. 1808 * 4bit iomux'es are spread over two registers. 1809 */ 1810 inc = (iom->type & IOMUX_WIDTH_4BIT) ? 8 : 4; 1811 if (iom->type & IOMUX_SOURCE_PMU) 1812 pmu_offs += inc; 1813 else 1814 grf_offs += inc; 1815 1816 bank_pins += 8; 1817 } 1818 } 1819 1820 return ctrl; 1821 } 1822 1823 #define RK3288_GRF_GPIO6C_IOMUX 0x64 1824 #define GPIO6C6_SEL_WRITE_ENABLE BIT(28) 1825 1826 static u32 rk3288_grf_gpio6c_iomux; 1827 1828 static int __maybe_unused rockchip_pinctrl_suspend(struct device *dev) 1829 { 1830 struct rockchip_pinctrl *info = dev_get_drvdata(dev); 1831 int ret = pinctrl_force_sleep(info->pctl_dev); 1832 1833 if (ret) 1834 return ret; 1835 1836 /* 1837 * RK3288 GPIO6_C6 mux would be modified by Maskrom when resume, so save 1838 * the setting here, and restore it at resume. 1839 */ 1840 if (info->ctrl->type == RK3288) { 1841 ret = regmap_read(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX, 1842 &rk3288_grf_gpio6c_iomux); 1843 if (ret) { 1844 pinctrl_force_default(info->pctl_dev); 1845 return ret; 1846 } 1847 } 1848 1849 return 0; 1850 } 1851 1852 static int __maybe_unused rockchip_pinctrl_resume(struct device *dev) 1853 { 1854 struct rockchip_pinctrl *info = dev_get_drvdata(dev); 1855 int ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX, 1856 rk3288_grf_gpio6c_iomux | 1857 GPIO6C6_SEL_WRITE_ENABLE); 1858 1859 if (ret) 1860 return ret; 1861 1862 return pinctrl_force_default(info->pctl_dev); 1863 } 1864 1865 static SIMPLE_DEV_PM_OPS(rockchip_pinctrl_dev_pm_ops, rockchip_pinctrl_suspend, 1866 rockchip_pinctrl_resume); 1867 1868 static int rockchip_pinctrl_probe(struct platform_device *pdev) 1869 { 1870 struct rockchip_pinctrl *info; 1871 struct device *dev = &pdev->dev; 1872 struct rockchip_pin_ctrl *ctrl; 1873 struct device_node *np = pdev->dev.of_node, *node; 1874 struct resource *res; 1875 void __iomem *base; 1876 int ret; 1877 1878 if (!dev->of_node) { 1879 dev_err(dev, "device tree node not found\n"); 1880 return -ENODEV; 1881 } 1882 1883 info = devm_kzalloc(dev, sizeof(struct rockchip_pinctrl), GFP_KERNEL); 1884 if (!info) 1885 return -ENOMEM; 1886 1887 info->dev = dev; 1888 1889 ctrl = rockchip_pinctrl_get_soc_data(info, pdev); 1890 if (!ctrl) { 1891 dev_err(dev, "driver data not available\n"); 1892 return -EINVAL; 1893 } 1894 info->ctrl = ctrl; 1895 1896 node = of_parse_phandle(np, "rockchip,grf", 0); 1897 if (node) { 1898 info->regmap_base = syscon_node_to_regmap(node); 1899 if (IS_ERR(info->regmap_base)) 1900 return PTR_ERR(info->regmap_base); 1901 } else { 1902 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1903 base = devm_ioremap_resource(&pdev->dev, res); 1904 if (IS_ERR(base)) 1905 return PTR_ERR(base); 1906 1907 rockchip_regmap_config.max_register = resource_size(res) - 4; 1908 rockchip_regmap_config.name = "rockchip,pinctrl"; 1909 info->regmap_base = devm_regmap_init_mmio(&pdev->dev, base, 1910 &rockchip_regmap_config); 1911 1912 /* to check for the old dt-bindings */ 1913 info->reg_size = resource_size(res); 1914 1915 /* Honor the old binding, with pull registers as 2nd resource */ 1916 if (ctrl->type == RK3188 && info->reg_size < 0x200) { 1917 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 1918 base = devm_ioremap_resource(&pdev->dev, res); 1919 if (IS_ERR(base)) 1920 return PTR_ERR(base); 1921 1922 rockchip_regmap_config.max_register = 1923 resource_size(res) - 4; 1924 rockchip_regmap_config.name = "rockchip,pinctrl-pull"; 1925 info->regmap_pull = devm_regmap_init_mmio(&pdev->dev, 1926 base, 1927 &rockchip_regmap_config); 1928 } 1929 } 1930 1931 /* try to find the optional reference to the pmu syscon */ 1932 node = of_parse_phandle(np, "rockchip,pmu", 0); 1933 if (node) { 1934 info->regmap_pmu = syscon_node_to_regmap(node); 1935 if (IS_ERR(info->regmap_pmu)) 1936 return PTR_ERR(info->regmap_pmu); 1937 } 1938 1939 ret = rockchip_gpiolib_register(pdev, info); 1940 if (ret) 1941 return ret; 1942 1943 ret = rockchip_pinctrl_register(pdev, info); 1944 if (ret) { 1945 rockchip_gpiolib_unregister(pdev, info); 1946 return ret; 1947 } 1948 1949 platform_set_drvdata(pdev, info); 1950 1951 return 0; 1952 } 1953 1954 static struct rockchip_pin_bank rk2928_pin_banks[] = { 1955 PIN_BANK(0, 32, "gpio0"), 1956 PIN_BANK(1, 32, "gpio1"), 1957 PIN_BANK(2, 32, "gpio2"), 1958 PIN_BANK(3, 32, "gpio3"), 1959 }; 1960 1961 static struct rockchip_pin_ctrl rk2928_pin_ctrl = { 1962 .pin_banks = rk2928_pin_banks, 1963 .nr_banks = ARRAY_SIZE(rk2928_pin_banks), 1964 .label = "RK2928-GPIO", 1965 .type = RK2928, 1966 .grf_mux_offset = 0xa8, 1967 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 1968 }; 1969 1970 static struct rockchip_pin_bank rk3066a_pin_banks[] = { 1971 PIN_BANK(0, 32, "gpio0"), 1972 PIN_BANK(1, 32, "gpio1"), 1973 PIN_BANK(2, 32, "gpio2"), 1974 PIN_BANK(3, 32, "gpio3"), 1975 PIN_BANK(4, 32, "gpio4"), 1976 PIN_BANK(6, 16, "gpio6"), 1977 }; 1978 1979 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = { 1980 .pin_banks = rk3066a_pin_banks, 1981 .nr_banks = ARRAY_SIZE(rk3066a_pin_banks), 1982 .label = "RK3066a-GPIO", 1983 .type = RK2928, 1984 .grf_mux_offset = 0xa8, 1985 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 1986 }; 1987 1988 static struct rockchip_pin_bank rk3066b_pin_banks[] = { 1989 PIN_BANK(0, 32, "gpio0"), 1990 PIN_BANK(1, 32, "gpio1"), 1991 PIN_BANK(2, 32, "gpio2"), 1992 PIN_BANK(3, 32, "gpio3"), 1993 }; 1994 1995 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = { 1996 .pin_banks = rk3066b_pin_banks, 1997 .nr_banks = ARRAY_SIZE(rk3066b_pin_banks), 1998 .label = "RK3066b-GPIO", 1999 .type = RK3066B, 2000 .grf_mux_offset = 0x60, 2001 }; 2002 2003 static struct rockchip_pin_bank rk3188_pin_banks[] = { 2004 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0), 2005 PIN_BANK(1, 32, "gpio1"), 2006 PIN_BANK(2, 32, "gpio2"), 2007 PIN_BANK(3, 32, "gpio3"), 2008 }; 2009 2010 static struct rockchip_pin_ctrl rk3188_pin_ctrl = { 2011 .pin_banks = rk3188_pin_banks, 2012 .nr_banks = ARRAY_SIZE(rk3188_pin_banks), 2013 .label = "RK3188-GPIO", 2014 .type = RK3188, 2015 .grf_mux_offset = 0x60, 2016 .pull_calc_reg = rk3188_calc_pull_reg_and_bit, 2017 }; 2018 2019 static struct rockchip_pin_bank rk3288_pin_banks[] = { 2020 PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU, 2021 IOMUX_SOURCE_PMU, 2022 IOMUX_SOURCE_PMU, 2023 IOMUX_UNROUTED 2024 ), 2025 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED, 2026 IOMUX_UNROUTED, 2027 IOMUX_UNROUTED, 2028 0 2029 ), 2030 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED), 2031 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT), 2032 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT, 2033 IOMUX_WIDTH_4BIT, 2034 0, 2035 0 2036 ), 2037 PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED, 2038 0, 2039 0, 2040 IOMUX_UNROUTED 2041 ), 2042 PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED), 2043 PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0, 2044 0, 2045 IOMUX_WIDTH_4BIT, 2046 IOMUX_UNROUTED 2047 ), 2048 PIN_BANK(8, 16, "gpio8"), 2049 }; 2050 2051 static struct rockchip_pin_ctrl rk3288_pin_ctrl = { 2052 .pin_banks = rk3288_pin_banks, 2053 .nr_banks = ARRAY_SIZE(rk3288_pin_banks), 2054 .label = "RK3288-GPIO", 2055 .type = RK3288, 2056 .grf_mux_offset = 0x0, 2057 .pmu_mux_offset = 0x84, 2058 .pull_calc_reg = rk3288_calc_pull_reg_and_bit, 2059 }; 2060 2061 static const struct of_device_id rockchip_pinctrl_dt_match[] = { 2062 { .compatible = "rockchip,rk2928-pinctrl", 2063 .data = (void *)&rk2928_pin_ctrl }, 2064 { .compatible = "rockchip,rk3066a-pinctrl", 2065 .data = (void *)&rk3066a_pin_ctrl }, 2066 { .compatible = "rockchip,rk3066b-pinctrl", 2067 .data = (void *)&rk3066b_pin_ctrl }, 2068 { .compatible = "rockchip,rk3188-pinctrl", 2069 .data = (void *)&rk3188_pin_ctrl }, 2070 { .compatible = "rockchip,rk3288-pinctrl", 2071 .data = (void *)&rk3288_pin_ctrl }, 2072 {}, 2073 }; 2074 MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match); 2075 2076 static struct platform_driver rockchip_pinctrl_driver = { 2077 .probe = rockchip_pinctrl_probe, 2078 .driver = { 2079 .name = "rockchip-pinctrl", 2080 .pm = &rockchip_pinctrl_dev_pm_ops, 2081 .of_match_table = rockchip_pinctrl_dt_match, 2082 }, 2083 }; 2084 2085 static int __init rockchip_pinctrl_drv_register(void) 2086 { 2087 return platform_driver_register(&rockchip_pinctrl_driver); 2088 } 2089 postcore_initcall(rockchip_pinctrl_drv_register); 2090 2091 MODULE_AUTHOR("Heiko Stuebner <heiko@sntech.de>"); 2092 MODULE_DESCRIPTION("Rockchip pinctrl driver"); 2093 MODULE_LICENSE("GPL v2"); 2094