1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Pinctrl driver for Rockchip SoCs 4 * 5 * Copyright (c) 2013 MundoReader S.L. 6 * Author: Heiko Stuebner <heiko@sntech.de> 7 * 8 * With some ideas taken from pinctrl-samsung: 9 * Copyright (c) 2012 Samsung Electronics Co., Ltd. 10 * http://www.samsung.com 11 * Copyright (c) 2012 Linaro Ltd 12 * https://www.linaro.org 13 * 14 * and pinctrl-at91: 15 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> 16 */ 17 18 #include <linux/init.h> 19 #include <linux/module.h> 20 #include <linux/platform_device.h> 21 #include <linux/io.h> 22 #include <linux/bitops.h> 23 #include <linux/gpio/driver.h> 24 #include <linux/of_device.h> 25 #include <linux/of_address.h> 26 #include <linux/of_irq.h> 27 #include <linux/pinctrl/machine.h> 28 #include <linux/pinctrl/pinconf.h> 29 #include <linux/pinctrl/pinctrl.h> 30 #include <linux/pinctrl/pinmux.h> 31 #include <linux/pinctrl/pinconf-generic.h> 32 #include <linux/irqchip/chained_irq.h> 33 #include <linux/clk.h> 34 #include <linux/regmap.h> 35 #include <linux/mfd/syscon.h> 36 #include <dt-bindings/pinctrl/rockchip.h> 37 38 #include "core.h" 39 #include "pinconf.h" 40 41 /* GPIO control registers */ 42 #define GPIO_SWPORT_DR 0x00 43 #define GPIO_SWPORT_DDR 0x04 44 #define GPIO_INTEN 0x30 45 #define GPIO_INTMASK 0x34 46 #define GPIO_INTTYPE_LEVEL 0x38 47 #define GPIO_INT_POLARITY 0x3c 48 #define GPIO_INT_STATUS 0x40 49 #define GPIO_INT_RAWSTATUS 0x44 50 #define GPIO_DEBOUNCE 0x48 51 #define GPIO_PORTS_EOI 0x4c 52 #define GPIO_EXT_PORT 0x50 53 #define GPIO_LS_SYNC 0x60 54 55 enum rockchip_pinctrl_type { 56 PX30, 57 RV1108, 58 RK2928, 59 RK3066B, 60 RK3128, 61 RK3188, 62 RK3288, 63 RK3308, 64 RK3368, 65 RK3399, 66 RK3568, 67 }; 68 69 70 /** 71 * Generate a bitmask for setting a value (v) with a write mask bit in hiword 72 * register 31:16 area. 73 */ 74 #define WRITE_MASK_VAL(h, l, v) \ 75 (GENMASK(((h) + 16), ((l) + 16)) | (((v) << (l)) & GENMASK((h), (l)))) 76 77 /* 78 * Encode variants of iomux registers into a type variable 79 */ 80 #define IOMUX_GPIO_ONLY BIT(0) 81 #define IOMUX_WIDTH_4BIT BIT(1) 82 #define IOMUX_SOURCE_PMU BIT(2) 83 #define IOMUX_UNROUTED BIT(3) 84 #define IOMUX_WIDTH_3BIT BIT(4) 85 #define IOMUX_WIDTH_2BIT BIT(5) 86 87 /** 88 * struct rockchip_iomux 89 * @type: iomux variant using IOMUX_* constants 90 * @offset: if initialized to -1 it will be autocalculated, by specifying 91 * an initial offset value the relevant source offset can be reset 92 * to a new value for autocalculating the following iomux registers. 93 */ 94 struct rockchip_iomux { 95 int type; 96 int offset; 97 }; 98 99 /* 100 * enum type index corresponding to rockchip_perpin_drv_list arrays index. 101 */ 102 enum rockchip_pin_drv_type { 103 DRV_TYPE_IO_DEFAULT = 0, 104 DRV_TYPE_IO_1V8_OR_3V0, 105 DRV_TYPE_IO_1V8_ONLY, 106 DRV_TYPE_IO_1V8_3V0_AUTO, 107 DRV_TYPE_IO_3V3_ONLY, 108 DRV_TYPE_MAX 109 }; 110 111 /* 112 * enum type index corresponding to rockchip_pull_list arrays index. 113 */ 114 enum rockchip_pin_pull_type { 115 PULL_TYPE_IO_DEFAULT = 0, 116 PULL_TYPE_IO_1V8_ONLY, 117 PULL_TYPE_MAX 118 }; 119 120 /** 121 * struct rockchip_drv 122 * @drv_type: drive strength variant using rockchip_perpin_drv_type 123 * @offset: if initialized to -1 it will be autocalculated, by specifying 124 * an initial offset value the relevant source offset can be reset 125 * to a new value for autocalculating the following drive strength 126 * registers. if used chips own cal_drv func instead to calculate 127 * registers offset, the variant could be ignored. 128 */ 129 struct rockchip_drv { 130 enum rockchip_pin_drv_type drv_type; 131 int offset; 132 }; 133 134 /** 135 * struct rockchip_pin_bank 136 * @reg_base: register base of the gpio bank 137 * @regmap_pull: optional separate register for additional pull settings 138 * @clk: clock of the gpio bank 139 * @irq: interrupt of the gpio bank 140 * @saved_masks: Saved content of GPIO_INTEN at suspend time. 141 * @pin_base: first pin number 142 * @nr_pins: number of pins in this bank 143 * @name: name of the bank 144 * @bank_num: number of the bank, to account for holes 145 * @iomux: array describing the 4 iomux sources of the bank 146 * @drv: array describing the 4 drive strength sources of the bank 147 * @pull_type: array describing the 4 pull type sources of the bank 148 * @valid: is all necessary information present 149 * @of_node: dt node of this bank 150 * @drvdata: common pinctrl basedata 151 * @domain: irqdomain of the gpio bank 152 * @gpio_chip: gpiolib chip 153 * @grange: gpio range 154 * @slock: spinlock for the gpio bank 155 * @toggle_edge_mode: bit mask to toggle (falling/rising) edge mode 156 * @recalced_mask: bit mask to indicate a need to recalulate the mask 157 * @route_mask: bits describing the routing pins of per bank 158 */ 159 struct rockchip_pin_bank { 160 void __iomem *reg_base; 161 struct regmap *regmap_pull; 162 struct clk *clk; 163 int irq; 164 u32 saved_masks; 165 u32 pin_base; 166 u8 nr_pins; 167 char *name; 168 u8 bank_num; 169 struct rockchip_iomux iomux[4]; 170 struct rockchip_drv drv[4]; 171 enum rockchip_pin_pull_type pull_type[4]; 172 bool valid; 173 struct device_node *of_node; 174 struct rockchip_pinctrl *drvdata; 175 struct irq_domain *domain; 176 struct gpio_chip gpio_chip; 177 struct pinctrl_gpio_range grange; 178 raw_spinlock_t slock; 179 u32 toggle_edge_mode; 180 u32 recalced_mask; 181 u32 route_mask; 182 }; 183 184 #define PIN_BANK(id, pins, label) \ 185 { \ 186 .bank_num = id, \ 187 .nr_pins = pins, \ 188 .name = label, \ 189 .iomux = { \ 190 { .offset = -1 }, \ 191 { .offset = -1 }, \ 192 { .offset = -1 }, \ 193 { .offset = -1 }, \ 194 }, \ 195 } 196 197 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \ 198 { \ 199 .bank_num = id, \ 200 .nr_pins = pins, \ 201 .name = label, \ 202 .iomux = { \ 203 { .type = iom0, .offset = -1 }, \ 204 { .type = iom1, .offset = -1 }, \ 205 { .type = iom2, .offset = -1 }, \ 206 { .type = iom3, .offset = -1 }, \ 207 }, \ 208 } 209 210 #define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \ 211 { \ 212 .bank_num = id, \ 213 .nr_pins = pins, \ 214 .name = label, \ 215 .iomux = { \ 216 { .offset = -1 }, \ 217 { .offset = -1 }, \ 218 { .offset = -1 }, \ 219 { .offset = -1 }, \ 220 }, \ 221 .drv = { \ 222 { .drv_type = type0, .offset = -1 }, \ 223 { .drv_type = type1, .offset = -1 }, \ 224 { .drv_type = type2, .offset = -1 }, \ 225 { .drv_type = type3, .offset = -1 }, \ 226 }, \ 227 } 228 229 #define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1, \ 230 drv2, drv3, pull0, pull1, \ 231 pull2, pull3) \ 232 { \ 233 .bank_num = id, \ 234 .nr_pins = pins, \ 235 .name = label, \ 236 .iomux = { \ 237 { .offset = -1 }, \ 238 { .offset = -1 }, \ 239 { .offset = -1 }, \ 240 { .offset = -1 }, \ 241 }, \ 242 .drv = { \ 243 { .drv_type = drv0, .offset = -1 }, \ 244 { .drv_type = drv1, .offset = -1 }, \ 245 { .drv_type = drv2, .offset = -1 }, \ 246 { .drv_type = drv3, .offset = -1 }, \ 247 }, \ 248 .pull_type[0] = pull0, \ 249 .pull_type[1] = pull1, \ 250 .pull_type[2] = pull2, \ 251 .pull_type[3] = pull3, \ 252 } 253 254 #define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1, \ 255 iom2, iom3, drv0, drv1, drv2, \ 256 drv3, offset0, offset1, \ 257 offset2, offset3) \ 258 { \ 259 .bank_num = id, \ 260 .nr_pins = pins, \ 261 .name = label, \ 262 .iomux = { \ 263 { .type = iom0, .offset = -1 }, \ 264 { .type = iom1, .offset = -1 }, \ 265 { .type = iom2, .offset = -1 }, \ 266 { .type = iom3, .offset = -1 }, \ 267 }, \ 268 .drv = { \ 269 { .drv_type = drv0, .offset = offset0 }, \ 270 { .drv_type = drv1, .offset = offset1 }, \ 271 { .drv_type = drv2, .offset = offset2 }, \ 272 { .drv_type = drv3, .offset = offset3 }, \ 273 }, \ 274 } 275 276 #define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins, \ 277 label, iom0, iom1, iom2, \ 278 iom3, drv0, drv1, drv2, \ 279 drv3, offset0, offset1, \ 280 offset2, offset3, pull0, \ 281 pull1, pull2, pull3) \ 282 { \ 283 .bank_num = id, \ 284 .nr_pins = pins, \ 285 .name = label, \ 286 .iomux = { \ 287 { .type = iom0, .offset = -1 }, \ 288 { .type = iom1, .offset = -1 }, \ 289 { .type = iom2, .offset = -1 }, \ 290 { .type = iom3, .offset = -1 }, \ 291 }, \ 292 .drv = { \ 293 { .drv_type = drv0, .offset = offset0 }, \ 294 { .drv_type = drv1, .offset = offset1 }, \ 295 { .drv_type = drv2, .offset = offset2 }, \ 296 { .drv_type = drv3, .offset = offset3 }, \ 297 }, \ 298 .pull_type[0] = pull0, \ 299 .pull_type[1] = pull1, \ 300 .pull_type[2] = pull2, \ 301 .pull_type[3] = pull3, \ 302 } 303 304 #define PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, FLAG) \ 305 { \ 306 .bank_num = ID, \ 307 .pin = PIN, \ 308 .func = FUNC, \ 309 .route_offset = REG, \ 310 .route_val = VAL, \ 311 .route_location = FLAG, \ 312 } 313 314 #define RK_MUXROUTE_SAME(ID, PIN, FUNC, REG, VAL) \ 315 PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_SAME) 316 317 #define RK_MUXROUTE_GRF(ID, PIN, FUNC, REG, VAL) \ 318 PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_GRF) 319 320 #define RK_MUXROUTE_PMU(ID, PIN, FUNC, REG, VAL) \ 321 PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_PMU) 322 323 /** 324 * struct rockchip_mux_recalced_data: represent a pin iomux data. 325 * @num: bank number. 326 * @pin: pin number. 327 * @bit: index at register. 328 * @reg: register offset. 329 * @mask: mask bit 330 */ 331 struct rockchip_mux_recalced_data { 332 u8 num; 333 u8 pin; 334 u32 reg; 335 u8 bit; 336 u8 mask; 337 }; 338 339 enum rockchip_mux_route_location { 340 ROCKCHIP_ROUTE_SAME = 0, 341 ROCKCHIP_ROUTE_PMU, 342 ROCKCHIP_ROUTE_GRF, 343 }; 344 345 /** 346 * struct rockchip_mux_recalced_data: represent a pin iomux data. 347 * @bank_num: bank number. 348 * @pin: index at register or used to calc index. 349 * @func: the min pin. 350 * @route_location: the mux route location (same, pmu, grf). 351 * @route_offset: the max pin. 352 * @route_val: the register offset. 353 */ 354 struct rockchip_mux_route_data { 355 u8 bank_num; 356 u8 pin; 357 u8 func; 358 enum rockchip_mux_route_location route_location; 359 u32 route_offset; 360 u32 route_val; 361 }; 362 363 struct rockchip_pin_ctrl { 364 struct rockchip_pin_bank *pin_banks; 365 u32 nr_banks; 366 u32 nr_pins; 367 char *label; 368 enum rockchip_pinctrl_type type; 369 int grf_mux_offset; 370 int pmu_mux_offset; 371 int grf_drv_offset; 372 int pmu_drv_offset; 373 struct rockchip_mux_recalced_data *iomux_recalced; 374 u32 niomux_recalced; 375 struct rockchip_mux_route_data *iomux_routes; 376 u32 niomux_routes; 377 378 void (*pull_calc_reg)(struct rockchip_pin_bank *bank, 379 int pin_num, struct regmap **regmap, 380 int *reg, u8 *bit); 381 void (*drv_calc_reg)(struct rockchip_pin_bank *bank, 382 int pin_num, struct regmap **regmap, 383 int *reg, u8 *bit); 384 int (*schmitt_calc_reg)(struct rockchip_pin_bank *bank, 385 int pin_num, struct regmap **regmap, 386 int *reg, u8 *bit); 387 }; 388 389 struct rockchip_pin_config { 390 unsigned int func; 391 unsigned long *configs; 392 unsigned int nconfigs; 393 }; 394 395 /** 396 * struct rockchip_pin_group: represent group of pins of a pinmux function. 397 * @name: name of the pin group, used to lookup the group. 398 * @pins: the pins included in this group. 399 * @npins: number of pins included in this group. 400 * @data: local pin configuration 401 */ 402 struct rockchip_pin_group { 403 const char *name; 404 unsigned int npins; 405 unsigned int *pins; 406 struct rockchip_pin_config *data; 407 }; 408 409 /** 410 * struct rockchip_pmx_func: represent a pin function. 411 * @name: name of the pin function, used to lookup the function. 412 * @groups: one or more names of pin groups that provide this function. 413 * @ngroups: number of groups included in @groups. 414 */ 415 struct rockchip_pmx_func { 416 const char *name; 417 const char **groups; 418 u8 ngroups; 419 }; 420 421 struct rockchip_pinctrl { 422 struct regmap *regmap_base; 423 int reg_size; 424 struct regmap *regmap_pull; 425 struct regmap *regmap_pmu; 426 struct device *dev; 427 struct rockchip_pin_ctrl *ctrl; 428 struct pinctrl_desc pctl; 429 struct pinctrl_dev *pctl_dev; 430 struct rockchip_pin_group *groups; 431 unsigned int ngroups; 432 struct rockchip_pmx_func *functions; 433 unsigned int nfunctions; 434 }; 435 436 static struct regmap_config rockchip_regmap_config = { 437 .reg_bits = 32, 438 .val_bits = 32, 439 .reg_stride = 4, 440 }; 441 442 static inline const struct rockchip_pin_group *pinctrl_name_to_group( 443 const struct rockchip_pinctrl *info, 444 const char *name) 445 { 446 int i; 447 448 for (i = 0; i < info->ngroups; i++) { 449 if (!strcmp(info->groups[i].name, name)) 450 return &info->groups[i]; 451 } 452 453 return NULL; 454 } 455 456 /* 457 * given a pin number that is local to a pin controller, find out the pin bank 458 * and the register base of the pin bank. 459 */ 460 static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info, 461 unsigned pin) 462 { 463 struct rockchip_pin_bank *b = info->ctrl->pin_banks; 464 465 while (pin >= (b->pin_base + b->nr_pins)) 466 b++; 467 468 return b; 469 } 470 471 static struct rockchip_pin_bank *bank_num_to_bank( 472 struct rockchip_pinctrl *info, 473 unsigned num) 474 { 475 struct rockchip_pin_bank *b = info->ctrl->pin_banks; 476 int i; 477 478 for (i = 0; i < info->ctrl->nr_banks; i++, b++) { 479 if (b->bank_num == num) 480 return b; 481 } 482 483 return ERR_PTR(-EINVAL); 484 } 485 486 /* 487 * Pinctrl_ops handling 488 */ 489 490 static int rockchip_get_groups_count(struct pinctrl_dev *pctldev) 491 { 492 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 493 494 return info->ngroups; 495 } 496 497 static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev, 498 unsigned selector) 499 { 500 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 501 502 return info->groups[selector].name; 503 } 504 505 static int rockchip_get_group_pins(struct pinctrl_dev *pctldev, 506 unsigned selector, const unsigned **pins, 507 unsigned *npins) 508 { 509 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 510 511 if (selector >= info->ngroups) 512 return -EINVAL; 513 514 *pins = info->groups[selector].pins; 515 *npins = info->groups[selector].npins; 516 517 return 0; 518 } 519 520 static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev, 521 struct device_node *np, 522 struct pinctrl_map **map, unsigned *num_maps) 523 { 524 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 525 const struct rockchip_pin_group *grp; 526 struct pinctrl_map *new_map; 527 struct device_node *parent; 528 int map_num = 1; 529 int i; 530 531 /* 532 * first find the group of this node and check if we need to create 533 * config maps for pins 534 */ 535 grp = pinctrl_name_to_group(info, np->name); 536 if (!grp) { 537 dev_err(info->dev, "unable to find group for node %pOFn\n", 538 np); 539 return -EINVAL; 540 } 541 542 map_num += grp->npins; 543 544 new_map = kcalloc(map_num, sizeof(*new_map), GFP_KERNEL); 545 if (!new_map) 546 return -ENOMEM; 547 548 *map = new_map; 549 *num_maps = map_num; 550 551 /* create mux map */ 552 parent = of_get_parent(np); 553 if (!parent) { 554 kfree(new_map); 555 return -EINVAL; 556 } 557 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP; 558 new_map[0].data.mux.function = parent->name; 559 new_map[0].data.mux.group = np->name; 560 of_node_put(parent); 561 562 /* create config map */ 563 new_map++; 564 for (i = 0; i < grp->npins; i++) { 565 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN; 566 new_map[i].data.configs.group_or_pin = 567 pin_get_name(pctldev, grp->pins[i]); 568 new_map[i].data.configs.configs = grp->data[i].configs; 569 new_map[i].data.configs.num_configs = grp->data[i].nconfigs; 570 } 571 572 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n", 573 (*map)->data.mux.function, (*map)->data.mux.group, map_num); 574 575 return 0; 576 } 577 578 static void rockchip_dt_free_map(struct pinctrl_dev *pctldev, 579 struct pinctrl_map *map, unsigned num_maps) 580 { 581 kfree(map); 582 } 583 584 static const struct pinctrl_ops rockchip_pctrl_ops = { 585 .get_groups_count = rockchip_get_groups_count, 586 .get_group_name = rockchip_get_group_name, 587 .get_group_pins = rockchip_get_group_pins, 588 .dt_node_to_map = rockchip_dt_node_to_map, 589 .dt_free_map = rockchip_dt_free_map, 590 }; 591 592 /* 593 * Hardware access 594 */ 595 596 static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = { 597 { 598 .num = 1, 599 .pin = 0, 600 .reg = 0x418, 601 .bit = 0, 602 .mask = 0x3 603 }, { 604 .num = 1, 605 .pin = 1, 606 .reg = 0x418, 607 .bit = 2, 608 .mask = 0x3 609 }, { 610 .num = 1, 611 .pin = 2, 612 .reg = 0x418, 613 .bit = 4, 614 .mask = 0x3 615 }, { 616 .num = 1, 617 .pin = 3, 618 .reg = 0x418, 619 .bit = 6, 620 .mask = 0x3 621 }, { 622 .num = 1, 623 .pin = 4, 624 .reg = 0x418, 625 .bit = 8, 626 .mask = 0x3 627 }, { 628 .num = 1, 629 .pin = 5, 630 .reg = 0x418, 631 .bit = 10, 632 .mask = 0x3 633 }, { 634 .num = 1, 635 .pin = 6, 636 .reg = 0x418, 637 .bit = 12, 638 .mask = 0x3 639 }, { 640 .num = 1, 641 .pin = 7, 642 .reg = 0x418, 643 .bit = 14, 644 .mask = 0x3 645 }, { 646 .num = 1, 647 .pin = 8, 648 .reg = 0x41c, 649 .bit = 0, 650 .mask = 0x3 651 }, { 652 .num = 1, 653 .pin = 9, 654 .reg = 0x41c, 655 .bit = 2, 656 .mask = 0x3 657 }, 658 }; 659 660 static struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = { 661 { 662 .num = 2, 663 .pin = 20, 664 .reg = 0xe8, 665 .bit = 0, 666 .mask = 0x7 667 }, { 668 .num = 2, 669 .pin = 21, 670 .reg = 0xe8, 671 .bit = 4, 672 .mask = 0x7 673 }, { 674 .num = 2, 675 .pin = 22, 676 .reg = 0xe8, 677 .bit = 8, 678 .mask = 0x7 679 }, { 680 .num = 2, 681 .pin = 23, 682 .reg = 0xe8, 683 .bit = 12, 684 .mask = 0x7 685 }, { 686 .num = 2, 687 .pin = 24, 688 .reg = 0xd4, 689 .bit = 12, 690 .mask = 0x7 691 }, 692 }; 693 694 static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = { 695 { 696 .num = 1, 697 .pin = 14, 698 .reg = 0x28, 699 .bit = 12, 700 .mask = 0xf 701 }, { 702 .num = 1, 703 .pin = 15, 704 .reg = 0x2c, 705 .bit = 0, 706 .mask = 0x3 707 }, { 708 .num = 1, 709 .pin = 18, 710 .reg = 0x30, 711 .bit = 4, 712 .mask = 0xf 713 }, { 714 .num = 1, 715 .pin = 19, 716 .reg = 0x30, 717 .bit = 8, 718 .mask = 0xf 719 }, { 720 .num = 1, 721 .pin = 20, 722 .reg = 0x30, 723 .bit = 12, 724 .mask = 0xf 725 }, { 726 .num = 1, 727 .pin = 21, 728 .reg = 0x34, 729 .bit = 0, 730 .mask = 0xf 731 }, { 732 .num = 1, 733 .pin = 22, 734 .reg = 0x34, 735 .bit = 4, 736 .mask = 0xf 737 }, { 738 .num = 1, 739 .pin = 23, 740 .reg = 0x34, 741 .bit = 8, 742 .mask = 0xf 743 }, { 744 .num = 3, 745 .pin = 12, 746 .reg = 0x68, 747 .bit = 8, 748 .mask = 0xf 749 }, { 750 .num = 3, 751 .pin = 13, 752 .reg = 0x68, 753 .bit = 12, 754 .mask = 0xf 755 }, { 756 .num = 2, 757 .pin = 2, 758 .reg = 0x608, 759 .bit = 0, 760 .mask = 0x7 761 }, { 762 .num = 2, 763 .pin = 3, 764 .reg = 0x608, 765 .bit = 4, 766 .mask = 0x7 767 }, { 768 .num = 2, 769 .pin = 16, 770 .reg = 0x610, 771 .bit = 8, 772 .mask = 0x7 773 }, { 774 .num = 3, 775 .pin = 10, 776 .reg = 0x610, 777 .bit = 0, 778 .mask = 0x7 779 }, { 780 .num = 3, 781 .pin = 11, 782 .reg = 0x610, 783 .bit = 4, 784 .mask = 0x7 785 }, 786 }; 787 788 static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = { 789 { 790 .num = 2, 791 .pin = 12, 792 .reg = 0x24, 793 .bit = 8, 794 .mask = 0x3 795 }, { 796 .num = 2, 797 .pin = 15, 798 .reg = 0x28, 799 .bit = 0, 800 .mask = 0x7 801 }, { 802 .num = 2, 803 .pin = 23, 804 .reg = 0x30, 805 .bit = 14, 806 .mask = 0x3 807 }, 808 }; 809 810 static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin, 811 int *reg, u8 *bit, int *mask) 812 { 813 struct rockchip_pinctrl *info = bank->drvdata; 814 struct rockchip_pin_ctrl *ctrl = info->ctrl; 815 struct rockchip_mux_recalced_data *data; 816 int i; 817 818 for (i = 0; i < ctrl->niomux_recalced; i++) { 819 data = &ctrl->iomux_recalced[i]; 820 if (data->num == bank->bank_num && 821 data->pin == pin) 822 break; 823 } 824 825 if (i >= ctrl->niomux_recalced) 826 return; 827 828 *reg = data->reg; 829 *mask = data->mask; 830 *bit = data->bit; 831 } 832 833 static struct rockchip_mux_route_data px30_mux_route_data[] = { 834 RK_MUXROUTE_SAME(2, RK_PA0, 1, 0x184, BIT(16 + 7)), /* cif-d2m0 */ 835 RK_MUXROUTE_SAME(3, RK_PA3, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d2m1 */ 836 RK_MUXROUTE_SAME(3, RK_PC6, 2, 0x184, BIT(16 + 8)), /* pdm-m0 */ 837 RK_MUXROUTE_SAME(2, RK_PC6, 1, 0x184, BIT(16 + 8) | BIT(8)), /* pdm-m1 */ 838 RK_MUXROUTE_SAME(1, RK_PD3, 2, 0x184, BIT(16 + 10)), /* uart2-rxm0 */ 839 RK_MUXROUTE_SAME(2, RK_PB6, 2, 0x184, BIT(16 + 10) | BIT(10)), /* uart2-rxm1 */ 840 RK_MUXROUTE_SAME(0, RK_PC1, 2, 0x184, BIT(16 + 9)), /* uart3-rxm0 */ 841 RK_MUXROUTE_SAME(1, RK_PB7, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-rxm1 */ 842 }; 843 844 static struct rockchip_mux_route_data rk3128_mux_route_data[] = { 845 RK_MUXROUTE_SAME(1, RK_PB2, 1, 0x144, BIT(16 + 3) | BIT(16 + 4)), /* spi-0 */ 846 RK_MUXROUTE_SAME(1, RK_PD3, 3, 0x144, BIT(16 + 3) | BIT(16 + 4) | BIT(3)), /* spi-1 */ 847 RK_MUXROUTE_SAME(0, RK_PB5, 2, 0x144, BIT(16 + 3) | BIT(16 + 4) | BIT(4)), /* spi-2 */ 848 RK_MUXROUTE_SAME(1, RK_PA5, 1, 0x144, BIT(16 + 5)), /* i2s-0 */ 849 RK_MUXROUTE_SAME(0, RK_PB6, 1, 0x144, BIT(16 + 5) | BIT(5)), /* i2s-1 */ 850 RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x144, BIT(16 + 6)), /* emmc-0 */ 851 RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x144, BIT(16 + 6) | BIT(6)), /* emmc-1 */ 852 }; 853 854 static struct rockchip_mux_route_data rk3188_mux_route_data[] = { 855 RK_MUXROUTE_SAME(0, RK_PD0, 1, 0xa0, BIT(16 + 11)), /* non-iomuxed emmc/flash pins on flash-dqs */ 856 RK_MUXROUTE_SAME(0, RK_PD0, 2, 0xa0, BIT(16 + 11) | BIT(11)), /* non-iomuxed emmc/flash pins on emmc-clk */ 857 }; 858 859 static struct rockchip_mux_route_data rk3228_mux_route_data[] = { 860 RK_MUXROUTE_SAME(0, RK_PD2, 1, 0x50, BIT(16)), /* pwm0-0 */ 861 RK_MUXROUTE_SAME(3, RK_PC5, 1, 0x50, BIT(16) | BIT(0)), /* pwm0-1 */ 862 RK_MUXROUTE_SAME(0, RK_PD3, 1, 0x50, BIT(16 + 1)), /* pwm1-0 */ 863 RK_MUXROUTE_SAME(0, RK_PD6, 2, 0x50, BIT(16 + 1) | BIT(1)), /* pwm1-1 */ 864 RK_MUXROUTE_SAME(0, RK_PD4, 1, 0x50, BIT(16 + 2)), /* pwm2-0 */ 865 RK_MUXROUTE_SAME(1, RK_PB4, 2, 0x50, BIT(16 + 2) | BIT(2)), /* pwm2-1 */ 866 RK_MUXROUTE_SAME(3, RK_PD2, 1, 0x50, BIT(16 + 3)), /* pwm3-0 */ 867 RK_MUXROUTE_SAME(1, RK_PB3, 2, 0x50, BIT(16 + 3) | BIT(3)), /* pwm3-1 */ 868 RK_MUXROUTE_SAME(1, RK_PA1, 1, 0x50, BIT(16 + 4)), /* sdio-0_d0 */ 869 RK_MUXROUTE_SAME(3, RK_PA2, 1, 0x50, BIT(16 + 4) | BIT(4)), /* sdio-1_d0 */ 870 RK_MUXROUTE_SAME(0, RK_PB5, 2, 0x50, BIT(16 + 5)), /* spi-0_rx */ 871 RK_MUXROUTE_SAME(2, RK_PA0, 2, 0x50, BIT(16 + 5) | BIT(5)), /* spi-1_rx */ 872 RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x50, BIT(16 + 7)), /* emmc-0_cmd */ 873 RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x50, BIT(16 + 7) | BIT(7)), /* emmc-1_cmd */ 874 RK_MUXROUTE_SAME(1, RK_PC3, 2, 0x50, BIT(16 + 8)), /* uart2-0_rx */ 875 RK_MUXROUTE_SAME(1, RK_PB2, 2, 0x50, BIT(16 + 8) | BIT(8)), /* uart2-1_rx */ 876 RK_MUXROUTE_SAME(1, RK_PB2, 1, 0x50, BIT(16 + 11)), /* uart1-0_rx */ 877 RK_MUXROUTE_SAME(3, RK_PB5, 1, 0x50, BIT(16 + 11) | BIT(11)), /* uart1-1_rx */ 878 }; 879 880 static struct rockchip_mux_route_data rk3288_mux_route_data[] = { 881 RK_MUXROUTE_SAME(7, RK_PC0, 2, 0x264, BIT(16 + 12) | BIT(12)), /* edphdmi_cecinoutt1 */ 882 RK_MUXROUTE_SAME(7, RK_PC7, 4, 0x264, BIT(16 + 12)), /* edphdmi_cecinout */ 883 }; 884 885 static struct rockchip_mux_route_data rk3308_mux_route_data[] = { 886 RK_MUXROUTE_SAME(0, RK_PC3, 1, 0x314, BIT(16 + 0) | BIT(0)), /* rtc_clk */ 887 RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x314, BIT(16 + 2) | BIT(16 + 3)), /* uart2_rxm0 */ 888 RK_MUXROUTE_SAME(4, RK_PD2, 2, 0x314, BIT(16 + 2) | BIT(16 + 3) | BIT(2)), /* uart2_rxm1 */ 889 RK_MUXROUTE_SAME(0, RK_PB7, 2, 0x608, BIT(16 + 8) | BIT(16 + 9)), /* i2c3_sdam0 */ 890 RK_MUXROUTE_SAME(3, RK_PB4, 2, 0x608, BIT(16 + 8) | BIT(16 + 9) | BIT(8)), /* i2c3_sdam1 */ 891 RK_MUXROUTE_SAME(2, RK_PA0, 3, 0x608, BIT(16 + 8) | BIT(16 + 9) | BIT(9)), /* i2c3_sdam2 */ 892 RK_MUXROUTE_SAME(1, RK_PA3, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclktxm0 */ 893 RK_MUXROUTE_SAME(1, RK_PA4, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclkrxm0 */ 894 RK_MUXROUTE_SAME(1, RK_PB5, 2, 0x308, BIT(16 + 3) | BIT(3)), /* i2s-8ch-1-sclktxm1 */ 895 RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x308, BIT(16 + 3) | BIT(3)), /* i2s-8ch-1-sclkrxm1 */ 896 RK_MUXROUTE_SAME(1, RK_PA4, 3, 0x308, BIT(16 + 12) | BIT(16 + 13)), /* pdm-clkm0 */ 897 RK_MUXROUTE_SAME(1, RK_PB6, 4, 0x308, BIT(16 + 12) | BIT(16 + 13) | BIT(12)), /* pdm-clkm1 */ 898 RK_MUXROUTE_SAME(2, RK_PA6, 2, 0x308, BIT(16 + 12) | BIT(16 + 13) | BIT(13)), /* pdm-clkm2 */ 899 RK_MUXROUTE_SAME(2, RK_PA4, 3, 0x600, BIT(16 + 2) | BIT(2)), /* pdm-clkm-m2 */ 900 RK_MUXROUTE_SAME(3, RK_PB2, 3, 0x314, BIT(16 + 9)), /* spi1_miso */ 901 RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x314, BIT(16 + 9) | BIT(9)), /* spi1_miso_m1 */ 902 RK_MUXROUTE_SAME(0, RK_PB3, 3, 0x314, BIT(16 + 10) | BIT(16 + 11)), /* owire_m0 */ 903 RK_MUXROUTE_SAME(1, RK_PC6, 7, 0x314, BIT(16 + 10) | BIT(16 + 11) | BIT(10)), /* owire_m1 */ 904 RK_MUXROUTE_SAME(2, RK_PA2, 5, 0x314, BIT(16 + 10) | BIT(16 + 11) | BIT(11)), /* owire_m2 */ 905 RK_MUXROUTE_SAME(0, RK_PB3, 2, 0x314, BIT(16 + 12) | BIT(16 + 13)), /* can_rxd_m0 */ 906 RK_MUXROUTE_SAME(1, RK_PC6, 5, 0x314, BIT(16 + 12) | BIT(16 + 13) | BIT(12)), /* can_rxd_m1 */ 907 RK_MUXROUTE_SAME(2, RK_PA2, 4, 0x314, BIT(16 + 12) | BIT(16 + 13) | BIT(13)), /* can_rxd_m2 */ 908 RK_MUXROUTE_SAME(1, RK_PC4, 3, 0x314, BIT(16 + 14)), /* mac_rxd0_m0 */ 909 RK_MUXROUTE_SAME(4, RK_PA2, 2, 0x314, BIT(16 + 14) | BIT(14)), /* mac_rxd0_m1 */ 910 RK_MUXROUTE_SAME(3, RK_PB4, 4, 0x314, BIT(16 + 15)), /* uart3_rx */ 911 RK_MUXROUTE_SAME(0, RK_PC1, 3, 0x314, BIT(16 + 15) | BIT(15)), /* uart3_rx_m1 */ 912 }; 913 914 static struct rockchip_mux_route_data rk3328_mux_route_data[] = { 915 RK_MUXROUTE_SAME(1, RK_PA1, 2, 0x50, BIT(16) | BIT(16 + 1)), /* uart2dbg_rxm0 */ 916 RK_MUXROUTE_SAME(2, RK_PA1, 1, 0x50, BIT(16) | BIT(16 + 1) | BIT(0)), /* uart2dbg_rxm1 */ 917 RK_MUXROUTE_SAME(1, RK_PB3, 2, 0x50, BIT(16 + 2) | BIT(2)), /* gmac-m1_rxd0 */ 918 RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x50, BIT(16 + 10) | BIT(10)), /* gmac-m1-optimized_rxd3 */ 919 RK_MUXROUTE_SAME(2, RK_PC3, 2, 0x50, BIT(16 + 3)), /* pdm_sdi0m0 */ 920 RK_MUXROUTE_SAME(1, RK_PC7, 3, 0x50, BIT(16 + 3) | BIT(3)), /* pdm_sdi0m1 */ 921 RK_MUXROUTE_SAME(3, RK_PA2, 4, 0x50, BIT(16 + 4) | BIT(16 + 5) | BIT(5)), /* spi_rxdm2 */ 922 RK_MUXROUTE_SAME(1, RK_PD0, 1, 0x50, BIT(16 + 6)), /* i2s2_sdim0 */ 923 RK_MUXROUTE_SAME(3, RK_PA2, 6, 0x50, BIT(16 + 6) | BIT(6)), /* i2s2_sdim1 */ 924 RK_MUXROUTE_SAME(2, RK_PC6, 3, 0x50, BIT(16 + 7) | BIT(7)), /* card_iom1 */ 925 RK_MUXROUTE_SAME(2, RK_PC0, 3, 0x50, BIT(16 + 8) | BIT(8)), /* tsp_d5m1 */ 926 RK_MUXROUTE_SAME(2, RK_PC0, 4, 0x50, BIT(16 + 9) | BIT(9)), /* cif_data5m1 */ 927 }; 928 929 static struct rockchip_mux_route_data rk3399_mux_route_data[] = { 930 RK_MUXROUTE_SAME(4, RK_PB0, 2, 0xe21c, BIT(16 + 10) | BIT(16 + 11)), /* uart2dbga_rx */ 931 RK_MUXROUTE_SAME(4, RK_PC0, 2, 0xe21c, BIT(16 + 10) | BIT(16 + 11) | BIT(10)), /* uart2dbgb_rx */ 932 RK_MUXROUTE_SAME(4, RK_PC3, 1, 0xe21c, BIT(16 + 10) | BIT(16 + 11) | BIT(11)), /* uart2dbgc_rx */ 933 RK_MUXROUTE_SAME(2, RK_PD2, 2, 0xe21c, BIT(16 + 14)), /* pcie_clkreqn */ 934 RK_MUXROUTE_SAME(4, RK_PD0, 1, 0xe21c, BIT(16 + 14) | BIT(14)), /* pcie_clkreqnb */ 935 }; 936 937 static struct rockchip_mux_route_data rk3568_mux_route_data[] = { 938 RK_MUXROUTE_PMU(0, RK_PB7, 1, 0x0110, WRITE_MASK_VAL(1, 0, 0)), /* PWM0 IO mux M0 */ 939 RK_MUXROUTE_PMU(0, RK_PC7, 2, 0x0110, WRITE_MASK_VAL(1, 0, 1)), /* PWM0 IO mux M1 */ 940 RK_MUXROUTE_PMU(0, RK_PC0, 1, 0x0110, WRITE_MASK_VAL(3, 2, 0)), /* PWM1 IO mux M0 */ 941 RK_MUXROUTE_PMU(0, RK_PB5, 4, 0x0110, WRITE_MASK_VAL(3, 2, 1)), /* PWM1 IO mux M1 */ 942 RK_MUXROUTE_PMU(0, RK_PC1, 1, 0x0110, WRITE_MASK_VAL(5, 4, 0)), /* PWM2 IO mux M0 */ 943 RK_MUXROUTE_PMU(0, RK_PB6, 4, 0x0110, WRITE_MASK_VAL(5, 4, 1)), /* PWM2 IO mux M1 */ 944 RK_MUXROUTE_PMU(0, RK_PB3, 2, 0x0300, WRITE_MASK_VAL(0, 0, 0)), /* CAN0 IO mux M0 */ 945 RK_MUXROUTE_GRF(2, RK_PA1, 4, 0x0300, WRITE_MASK_VAL(0, 0, 1)), /* CAN0 IO mux M1 */ 946 RK_MUXROUTE_GRF(1, RK_PA1, 3, 0x0300, WRITE_MASK_VAL(2, 2, 0)), /* CAN1 IO mux M0 */ 947 RK_MUXROUTE_GRF(4, RK_PC3, 3, 0x0300, WRITE_MASK_VAL(2, 2, 1)), /* CAN1 IO mux M1 */ 948 RK_MUXROUTE_GRF(4, RK_PB5, 3, 0x0300, WRITE_MASK_VAL(4, 4, 0)), /* CAN2 IO mux M0 */ 949 RK_MUXROUTE_GRF(2, RK_PB2, 4, 0x0300, WRITE_MASK_VAL(4, 4, 1)), /* CAN2 IO mux M1 */ 950 RK_MUXROUTE_GRF(4, RK_PC4, 1, 0x0300, WRITE_MASK_VAL(6, 6, 0)), /* HPDIN IO mux M0 */ 951 RK_MUXROUTE_PMU(0, RK_PC2, 2, 0x0300, WRITE_MASK_VAL(6, 6, 1)), /* HPDIN IO mux M1 */ 952 RK_MUXROUTE_GRF(3, RK_PB1, 3, 0x0300, WRITE_MASK_VAL(8, 8, 0)), /* GMAC1 IO mux M0 */ 953 RK_MUXROUTE_GRF(4, RK_PA7, 3, 0x0300, WRITE_MASK_VAL(8, 8, 1)), /* GMAC1 IO mux M1 */ 954 RK_MUXROUTE_GRF(4, RK_PD1, 1, 0x0300, WRITE_MASK_VAL(10, 10, 0)), /* HDMITX IO mux M0 */ 955 RK_MUXROUTE_PMU(0, RK_PC7, 1, 0x0300, WRITE_MASK_VAL(10, 10, 1)), /* HDMITX IO mux M1 */ 956 RK_MUXROUTE_PMU(0, RK_PB6, 1, 0x0300, WRITE_MASK_VAL(14, 14, 0)), /* I2C2 IO mux M0 */ 957 RK_MUXROUTE_GRF(4, RK_PB4, 1, 0x0300, WRITE_MASK_VAL(14, 14, 1)), /* I2C2 IO mux M1 */ 958 RK_MUXROUTE_GRF(1, RK_PA0, 1, 0x0304, WRITE_MASK_VAL(0, 0, 0)), /* I2C3 IO mux M0 */ 959 RK_MUXROUTE_GRF(3, RK_PB6, 4, 0x0304, WRITE_MASK_VAL(0, 0, 1)), /* I2C3 IO mux M1 */ 960 RK_MUXROUTE_GRF(4, RK_PB2, 1, 0x0304, WRITE_MASK_VAL(2, 2, 0)), /* I2C4 IO mux M0 */ 961 RK_MUXROUTE_GRF(2, RK_PB1, 2, 0x0304, WRITE_MASK_VAL(2, 2, 1)), /* I2C4 IO mux M1 */ 962 RK_MUXROUTE_GRF(3, RK_PB4, 4, 0x0304, WRITE_MASK_VAL(4, 4, 0)), /* I2C5 IO mux M0 */ 963 RK_MUXROUTE_GRF(4, RK_PD0, 2, 0x0304, WRITE_MASK_VAL(4, 4, 1)), /* I2C5 IO mux M1 */ 964 RK_MUXROUTE_GRF(3, RK_PB1, 5, 0x0304, WRITE_MASK_VAL(14, 14, 0)), /* PWM8 IO mux M0 */ 965 RK_MUXROUTE_GRF(1, RK_PD5, 4, 0x0304, WRITE_MASK_VAL(14, 14, 1)), /* PWM8 IO mux M1 */ 966 RK_MUXROUTE_GRF(3, RK_PB2, 5, 0x0308, WRITE_MASK_VAL(0, 0, 0)), /* PWM9 IO mux M0 */ 967 RK_MUXROUTE_GRF(1, RK_PD6, 4, 0x0308, WRITE_MASK_VAL(0, 0, 1)), /* PWM9 IO mux M1 */ 968 RK_MUXROUTE_GRF(3, RK_PB5, 5, 0x0308, WRITE_MASK_VAL(2, 2, 0)), /* PWM10 IO mux M0 */ 969 RK_MUXROUTE_GRF(2, RK_PA1, 2, 0x0308, WRITE_MASK_VAL(2, 2, 1)), /* PWM10 IO mux M1 */ 970 RK_MUXROUTE_GRF(3, RK_PB6, 5, 0x0308, WRITE_MASK_VAL(4, 4, 0)), /* PWM11 IO mux M0 */ 971 RK_MUXROUTE_GRF(4, RK_PC0, 3, 0x0308, WRITE_MASK_VAL(4, 4, 1)), /* PWM11 IO mux M1 */ 972 RK_MUXROUTE_GRF(3, RK_PB7, 2, 0x0308, WRITE_MASK_VAL(6, 6, 0)), /* PWM12 IO mux M0 */ 973 RK_MUXROUTE_GRF(4, RK_PC5, 1, 0x0308, WRITE_MASK_VAL(6, 6, 1)), /* PWM12 IO mux M1 */ 974 RK_MUXROUTE_GRF(3, RK_PC0, 2, 0x0308, WRITE_MASK_VAL(8, 8, 0)), /* PWM13 IO mux M0 */ 975 RK_MUXROUTE_GRF(4, RK_PC6, 1, 0x0308, WRITE_MASK_VAL(8, 8, 1)), /* PWM13 IO mux M1 */ 976 RK_MUXROUTE_GRF(3, RK_PC4, 1, 0x0308, WRITE_MASK_VAL(10, 10, 0)), /* PWM14 IO mux M0 */ 977 RK_MUXROUTE_GRF(4, RK_PC2, 1, 0x0308, WRITE_MASK_VAL(10, 10, 1)), /* PWM14 IO mux M1 */ 978 RK_MUXROUTE_GRF(3, RK_PC5, 1, 0x0308, WRITE_MASK_VAL(12, 12, 0)), /* PWM15 IO mux M0 */ 979 RK_MUXROUTE_GRF(4, RK_PC3, 1, 0x0308, WRITE_MASK_VAL(12, 12, 1)), /* PWM15 IO mux M1 */ 980 RK_MUXROUTE_GRF(3, RK_PD2, 3, 0x0308, WRITE_MASK_VAL(14, 14, 0)), /* SDMMC2 IO mux M0 */ 981 RK_MUXROUTE_GRF(3, RK_PA5, 5, 0x0308, WRITE_MASK_VAL(14, 14, 1)), /* SDMMC2 IO mux M1 */ 982 RK_MUXROUTE_PMU(0, RK_PB5, 2, 0x030c, WRITE_MASK_VAL(0, 0, 0)), /* SPI0 IO mux M0 */ 983 RK_MUXROUTE_GRF(2, RK_PD3, 3, 0x030c, WRITE_MASK_VAL(0, 0, 1)), /* SPI0 IO mux M1 */ 984 RK_MUXROUTE_GRF(2, RK_PB5, 3, 0x030c, WRITE_MASK_VAL(2, 2, 0)), /* SPI1 IO mux M0 */ 985 RK_MUXROUTE_GRF(3, RK_PC3, 3, 0x030c, WRITE_MASK_VAL(2, 2, 1)), /* SPI1 IO mux M1 */ 986 RK_MUXROUTE_GRF(2, RK_PC1, 4, 0x030c, WRITE_MASK_VAL(4, 4, 0)), /* SPI2 IO mux M0 */ 987 RK_MUXROUTE_GRF(3, RK_PA0, 3, 0x030c, WRITE_MASK_VAL(4, 4, 1)), /* SPI2 IO mux M1 */ 988 RK_MUXROUTE_GRF(4, RK_PB3, 4, 0x030c, WRITE_MASK_VAL(6, 6, 0)), /* SPI3 IO mux M0 */ 989 RK_MUXROUTE_GRF(4, RK_PC2, 2, 0x030c, WRITE_MASK_VAL(6, 6, 1)), /* SPI3 IO mux M1 */ 990 RK_MUXROUTE_GRF(2, RK_PB4, 2, 0x030c, WRITE_MASK_VAL(8, 8, 0)), /* UART1 IO mux M0 */ 991 RK_MUXROUTE_PMU(0, RK_PD1, 1, 0x030c, WRITE_MASK_VAL(8, 8, 1)), /* UART1 IO mux M1 */ 992 RK_MUXROUTE_PMU(0, RK_PD1, 1, 0x030c, WRITE_MASK_VAL(10, 10, 0)), /* UART2 IO mux M0 */ 993 RK_MUXROUTE_GRF(1, RK_PD5, 2, 0x030c, WRITE_MASK_VAL(10, 10, 1)), /* UART2 IO mux M1 */ 994 RK_MUXROUTE_GRF(1, RK_PA1, 2, 0x030c, WRITE_MASK_VAL(12, 12, 0)), /* UART3 IO mux M0 */ 995 RK_MUXROUTE_GRF(3, RK_PB7, 4, 0x030c, WRITE_MASK_VAL(12, 12, 1)), /* UART3 IO mux M1 */ 996 RK_MUXROUTE_GRF(1, RK_PA6, 2, 0x030c, WRITE_MASK_VAL(14, 14, 0)), /* UART4 IO mux M0 */ 997 RK_MUXROUTE_GRF(3, RK_PB2, 4, 0x030c, WRITE_MASK_VAL(14, 14, 1)), /* UART4 IO mux M1 */ 998 RK_MUXROUTE_GRF(2, RK_PA2, 3, 0x0310, WRITE_MASK_VAL(0, 0, 0)), /* UART5 IO mux M0 */ 999 RK_MUXROUTE_GRF(3, RK_PC2, 4, 0x0310, WRITE_MASK_VAL(0, 0, 1)), /* UART5 IO mux M1 */ 1000 RK_MUXROUTE_GRF(2, RK_PA4, 3, 0x0310, WRITE_MASK_VAL(2, 2, 0)), /* UART6 IO mux M0 */ 1001 RK_MUXROUTE_GRF(1, RK_PD5, 3, 0x0310, WRITE_MASK_VAL(2, 2, 1)), /* UART6 IO mux M1 */ 1002 RK_MUXROUTE_GRF(2, RK_PA6, 3, 0x0310, WRITE_MASK_VAL(5, 4, 0)), /* UART7 IO mux M0 */ 1003 RK_MUXROUTE_GRF(3, RK_PC4, 4, 0x0310, WRITE_MASK_VAL(5, 4, 1)), /* UART7 IO mux M1 */ 1004 RK_MUXROUTE_GRF(4, RK_PA2, 4, 0x0310, WRITE_MASK_VAL(5, 4, 2)), /* UART7 IO mux M2 */ 1005 RK_MUXROUTE_GRF(2, RK_PC5, 3, 0x0310, WRITE_MASK_VAL(6, 6, 0)), /* UART8 IO mux M0 */ 1006 RK_MUXROUTE_GRF(2, RK_PD7, 4, 0x0310, WRITE_MASK_VAL(6, 6, 1)), /* UART8 IO mux M1 */ 1007 RK_MUXROUTE_GRF(2, RK_PB0, 3, 0x0310, WRITE_MASK_VAL(9, 8, 0)), /* UART9 IO mux M0 */ 1008 RK_MUXROUTE_GRF(4, RK_PC5, 4, 0x0310, WRITE_MASK_VAL(9, 8, 1)), /* UART9 IO mux M1 */ 1009 RK_MUXROUTE_GRF(4, RK_PA4, 4, 0x0310, WRITE_MASK_VAL(9, 8, 2)), /* UART9 IO mux M2 */ 1010 RK_MUXROUTE_GRF(1, RK_PA2, 1, 0x0310, WRITE_MASK_VAL(11, 10, 0)), /* I2S1 IO mux M0 */ 1011 RK_MUXROUTE_GRF(3, RK_PC6, 4, 0x0310, WRITE_MASK_VAL(11, 10, 1)), /* I2S1 IO mux M1 */ 1012 RK_MUXROUTE_GRF(2, RK_PD0, 5, 0x0310, WRITE_MASK_VAL(11, 10, 2)), /* I2S1 IO mux M2 */ 1013 RK_MUXROUTE_GRF(2, RK_PC1, 1, 0x0310, WRITE_MASK_VAL(12, 12, 0)), /* I2S2 IO mux M0 */ 1014 RK_MUXROUTE_GRF(4, RK_PB6, 5, 0x0310, WRITE_MASK_VAL(12, 12, 1)), /* I2S2 IO mux M1 */ 1015 RK_MUXROUTE_GRF(3, RK_PA2, 4, 0x0310, WRITE_MASK_VAL(14, 14, 0)), /* I2S3 IO mux M0 */ 1016 RK_MUXROUTE_GRF(4, RK_PC2, 5, 0x0310, WRITE_MASK_VAL(14, 14, 1)), /* I2S3 IO mux M1 */ 1017 RK_MUXROUTE_GRF(1, RK_PA4, 3, 0x0314, WRITE_MASK_VAL(1, 0, 0)), /* PDM IO mux M0 */ 1018 RK_MUXROUTE_GRF(1, RK_PA6, 3, 0x0314, WRITE_MASK_VAL(1, 0, 0)), /* PDM IO mux M0 */ 1019 RK_MUXROUTE_GRF(3, RK_PD6, 5, 0x0314, WRITE_MASK_VAL(1, 0, 1)), /* PDM IO mux M1 */ 1020 RK_MUXROUTE_GRF(4, RK_PA0, 4, 0x0314, WRITE_MASK_VAL(1, 0, 1)), /* PDM IO mux M1 */ 1021 RK_MUXROUTE_GRF(3, RK_PC4, 5, 0x0314, WRITE_MASK_VAL(1, 0, 2)), /* PDM IO mux M2 */ 1022 RK_MUXROUTE_PMU(0, RK_PA5, 3, 0x0314, WRITE_MASK_VAL(3, 2, 0)), /* PCIE20 IO mux M0 */ 1023 RK_MUXROUTE_GRF(2, RK_PD0, 4, 0x0314, WRITE_MASK_VAL(3, 2, 1)), /* PCIE20 IO mux M1 */ 1024 RK_MUXROUTE_GRF(1, RK_PB0, 4, 0x0314, WRITE_MASK_VAL(3, 2, 2)), /* PCIE20 IO mux M2 */ 1025 RK_MUXROUTE_PMU(0, RK_PA4, 3, 0x0314, WRITE_MASK_VAL(5, 4, 0)), /* PCIE30X1 IO mux M0 */ 1026 RK_MUXROUTE_GRF(2, RK_PD2, 4, 0x0314, WRITE_MASK_VAL(5, 4, 1)), /* PCIE30X1 IO mux M1 */ 1027 RK_MUXROUTE_GRF(1, RK_PA5, 4, 0x0314, WRITE_MASK_VAL(5, 4, 2)), /* PCIE30X1 IO mux M2 */ 1028 RK_MUXROUTE_PMU(0, RK_PA6, 2, 0x0314, WRITE_MASK_VAL(7, 6, 0)), /* PCIE30X2 IO mux M0 */ 1029 RK_MUXROUTE_GRF(2, RK_PD4, 4, 0x0314, WRITE_MASK_VAL(7, 6, 1)), /* PCIE30X2 IO mux M1 */ 1030 RK_MUXROUTE_GRF(4, RK_PC2, 4, 0x0314, WRITE_MASK_VAL(7, 6, 2)), /* PCIE30X2 IO mux M2 */ 1031 }; 1032 1033 static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin, 1034 int mux, u32 *loc, u32 *reg, u32 *value) 1035 { 1036 struct rockchip_pinctrl *info = bank->drvdata; 1037 struct rockchip_pin_ctrl *ctrl = info->ctrl; 1038 struct rockchip_mux_route_data *data; 1039 int i; 1040 1041 for (i = 0; i < ctrl->niomux_routes; i++) { 1042 data = &ctrl->iomux_routes[i]; 1043 if ((data->bank_num == bank->bank_num) && 1044 (data->pin == pin) && (data->func == mux)) 1045 break; 1046 } 1047 1048 if (i >= ctrl->niomux_routes) 1049 return false; 1050 1051 *loc = data->route_location; 1052 *reg = data->route_offset; 1053 *value = data->route_val; 1054 1055 return true; 1056 } 1057 1058 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) 1059 { 1060 struct rockchip_pinctrl *info = bank->drvdata; 1061 int iomux_num = (pin / 8); 1062 struct regmap *regmap; 1063 unsigned int val; 1064 int reg, ret, mask, mux_type; 1065 u8 bit; 1066 1067 if (iomux_num > 3) 1068 return -EINVAL; 1069 1070 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { 1071 dev_err(info->dev, "pin %d is unrouted\n", pin); 1072 return -EINVAL; 1073 } 1074 1075 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) 1076 return RK_FUNC_GPIO; 1077 1078 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) 1079 ? info->regmap_pmu : info->regmap_base; 1080 1081 /* get basic quadrupel of mux registers and the correct reg inside */ 1082 mux_type = bank->iomux[iomux_num].type; 1083 reg = bank->iomux[iomux_num].offset; 1084 if (mux_type & IOMUX_WIDTH_4BIT) { 1085 if ((pin % 8) >= 4) 1086 reg += 0x4; 1087 bit = (pin % 4) * 4; 1088 mask = 0xf; 1089 } else if (mux_type & IOMUX_WIDTH_3BIT) { 1090 if ((pin % 8) >= 5) 1091 reg += 0x4; 1092 bit = (pin % 8 % 5) * 3; 1093 mask = 0x7; 1094 } else { 1095 bit = (pin % 8) * 2; 1096 mask = 0x3; 1097 } 1098 1099 if (bank->recalced_mask & BIT(pin)) 1100 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); 1101 1102 ret = regmap_read(regmap, reg, &val); 1103 if (ret) 1104 return ret; 1105 1106 return ((val >> bit) & mask); 1107 } 1108 1109 static int rockchip_verify_mux(struct rockchip_pin_bank *bank, 1110 int pin, int mux) 1111 { 1112 struct rockchip_pinctrl *info = bank->drvdata; 1113 int iomux_num = (pin / 8); 1114 1115 if (iomux_num > 3) 1116 return -EINVAL; 1117 1118 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { 1119 dev_err(info->dev, "pin %d is unrouted\n", pin); 1120 return -EINVAL; 1121 } 1122 1123 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) { 1124 if (mux != RK_FUNC_GPIO) { 1125 dev_err(info->dev, 1126 "pin %d only supports a gpio mux\n", pin); 1127 return -ENOTSUPP; 1128 } 1129 } 1130 1131 return 0; 1132 } 1133 1134 /* 1135 * Set a new mux function for a pin. 1136 * 1137 * The register is divided into the upper and lower 16 bit. When changing 1138 * a value, the previous register value is not read and changed. Instead 1139 * it seems the changed bits are marked in the upper 16 bit, while the 1140 * changed value gets set in the same offset in the lower 16 bit. 1141 * All pin settings seem to be 2 bit wide in both the upper and lower 1142 * parts. 1143 * @bank: pin bank to change 1144 * @pin: pin to change 1145 * @mux: new mux function to set 1146 */ 1147 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) 1148 { 1149 struct rockchip_pinctrl *info = bank->drvdata; 1150 int iomux_num = (pin / 8); 1151 struct regmap *regmap; 1152 int reg, ret, mask, mux_type; 1153 u8 bit; 1154 u32 data, rmask, route_location, route_reg, route_val; 1155 1156 ret = rockchip_verify_mux(bank, pin, mux); 1157 if (ret < 0) 1158 return ret; 1159 1160 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) 1161 return 0; 1162 1163 dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n", 1164 bank->bank_num, pin, mux); 1165 1166 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) 1167 ? info->regmap_pmu : info->regmap_base; 1168 1169 /* get basic quadrupel of mux registers and the correct reg inside */ 1170 mux_type = bank->iomux[iomux_num].type; 1171 reg = bank->iomux[iomux_num].offset; 1172 if (mux_type & IOMUX_WIDTH_4BIT) { 1173 if ((pin % 8) >= 4) 1174 reg += 0x4; 1175 bit = (pin % 4) * 4; 1176 mask = 0xf; 1177 } else if (mux_type & IOMUX_WIDTH_3BIT) { 1178 if ((pin % 8) >= 5) 1179 reg += 0x4; 1180 bit = (pin % 8 % 5) * 3; 1181 mask = 0x7; 1182 } else { 1183 bit = (pin % 8) * 2; 1184 mask = 0x3; 1185 } 1186 1187 if (bank->recalced_mask & BIT(pin)) 1188 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); 1189 1190 if (bank->route_mask & BIT(pin)) { 1191 if (rockchip_get_mux_route(bank, pin, mux, &route_location, 1192 &route_reg, &route_val)) { 1193 struct regmap *route_regmap = regmap; 1194 1195 /* handle special locations */ 1196 switch (route_location) { 1197 case ROCKCHIP_ROUTE_PMU: 1198 route_regmap = info->regmap_pmu; 1199 break; 1200 case ROCKCHIP_ROUTE_GRF: 1201 route_regmap = info->regmap_base; 1202 break; 1203 } 1204 1205 ret = regmap_write(route_regmap, route_reg, route_val); 1206 if (ret) 1207 return ret; 1208 } 1209 } 1210 1211 data = (mask << (bit + 16)); 1212 rmask = data | (data >> 16); 1213 data |= (mux & mask) << bit; 1214 ret = regmap_update_bits(regmap, reg, rmask, data); 1215 1216 return ret; 1217 } 1218 1219 #define PX30_PULL_PMU_OFFSET 0x10 1220 #define PX30_PULL_GRF_OFFSET 0x60 1221 #define PX30_PULL_BITS_PER_PIN 2 1222 #define PX30_PULL_PINS_PER_REG 8 1223 #define PX30_PULL_BANK_STRIDE 16 1224 1225 static void px30_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1226 int pin_num, struct regmap **regmap, 1227 int *reg, u8 *bit) 1228 { 1229 struct rockchip_pinctrl *info = bank->drvdata; 1230 1231 /* The first 32 pins of the first bank are located in PMU */ 1232 if (bank->bank_num == 0) { 1233 *regmap = info->regmap_pmu; 1234 *reg = PX30_PULL_PMU_OFFSET; 1235 } else { 1236 *regmap = info->regmap_base; 1237 *reg = PX30_PULL_GRF_OFFSET; 1238 1239 /* correct the offset, as we're starting with the 2nd bank */ 1240 *reg -= 0x10; 1241 *reg += bank->bank_num * PX30_PULL_BANK_STRIDE; 1242 } 1243 1244 *reg += ((pin_num / PX30_PULL_PINS_PER_REG) * 4); 1245 *bit = (pin_num % PX30_PULL_PINS_PER_REG); 1246 *bit *= PX30_PULL_BITS_PER_PIN; 1247 } 1248 1249 #define PX30_DRV_PMU_OFFSET 0x20 1250 #define PX30_DRV_GRF_OFFSET 0xf0 1251 #define PX30_DRV_BITS_PER_PIN 2 1252 #define PX30_DRV_PINS_PER_REG 8 1253 #define PX30_DRV_BANK_STRIDE 16 1254 1255 static void px30_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1256 int pin_num, struct regmap **regmap, 1257 int *reg, u8 *bit) 1258 { 1259 struct rockchip_pinctrl *info = bank->drvdata; 1260 1261 /* The first 32 pins of the first bank are located in PMU */ 1262 if (bank->bank_num == 0) { 1263 *regmap = info->regmap_pmu; 1264 *reg = PX30_DRV_PMU_OFFSET; 1265 } else { 1266 *regmap = info->regmap_base; 1267 *reg = PX30_DRV_GRF_OFFSET; 1268 1269 /* correct the offset, as we're starting with the 2nd bank */ 1270 *reg -= 0x10; 1271 *reg += bank->bank_num * PX30_DRV_BANK_STRIDE; 1272 } 1273 1274 *reg += ((pin_num / PX30_DRV_PINS_PER_REG) * 4); 1275 *bit = (pin_num % PX30_DRV_PINS_PER_REG); 1276 *bit *= PX30_DRV_BITS_PER_PIN; 1277 } 1278 1279 #define PX30_SCHMITT_PMU_OFFSET 0x38 1280 #define PX30_SCHMITT_GRF_OFFSET 0xc0 1281 #define PX30_SCHMITT_PINS_PER_PMU_REG 16 1282 #define PX30_SCHMITT_BANK_STRIDE 16 1283 #define PX30_SCHMITT_PINS_PER_GRF_REG 8 1284 1285 static int px30_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1286 int pin_num, 1287 struct regmap **regmap, 1288 int *reg, u8 *bit) 1289 { 1290 struct rockchip_pinctrl *info = bank->drvdata; 1291 int pins_per_reg; 1292 1293 if (bank->bank_num == 0) { 1294 *regmap = info->regmap_pmu; 1295 *reg = PX30_SCHMITT_PMU_OFFSET; 1296 pins_per_reg = PX30_SCHMITT_PINS_PER_PMU_REG; 1297 } else { 1298 *regmap = info->regmap_base; 1299 *reg = PX30_SCHMITT_GRF_OFFSET; 1300 pins_per_reg = PX30_SCHMITT_PINS_PER_GRF_REG; 1301 *reg += (bank->bank_num - 1) * PX30_SCHMITT_BANK_STRIDE; 1302 } 1303 1304 *reg += ((pin_num / pins_per_reg) * 4); 1305 *bit = pin_num % pins_per_reg; 1306 1307 return 0; 1308 } 1309 1310 #define RV1108_PULL_PMU_OFFSET 0x10 1311 #define RV1108_PULL_OFFSET 0x110 1312 #define RV1108_PULL_PINS_PER_REG 8 1313 #define RV1108_PULL_BITS_PER_PIN 2 1314 #define RV1108_PULL_BANK_STRIDE 16 1315 1316 static void rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1317 int pin_num, struct regmap **regmap, 1318 int *reg, u8 *bit) 1319 { 1320 struct rockchip_pinctrl *info = bank->drvdata; 1321 1322 /* The first 24 pins of the first bank are located in PMU */ 1323 if (bank->bank_num == 0) { 1324 *regmap = info->regmap_pmu; 1325 *reg = RV1108_PULL_PMU_OFFSET; 1326 } else { 1327 *reg = RV1108_PULL_OFFSET; 1328 *regmap = info->regmap_base; 1329 /* correct the offset, as we're starting with the 2nd bank */ 1330 *reg -= 0x10; 1331 *reg += bank->bank_num * RV1108_PULL_BANK_STRIDE; 1332 } 1333 1334 *reg += ((pin_num / RV1108_PULL_PINS_PER_REG) * 4); 1335 *bit = (pin_num % RV1108_PULL_PINS_PER_REG); 1336 *bit *= RV1108_PULL_BITS_PER_PIN; 1337 } 1338 1339 #define RV1108_DRV_PMU_OFFSET 0x20 1340 #define RV1108_DRV_GRF_OFFSET 0x210 1341 #define RV1108_DRV_BITS_PER_PIN 2 1342 #define RV1108_DRV_PINS_PER_REG 8 1343 #define RV1108_DRV_BANK_STRIDE 16 1344 1345 static void rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1346 int pin_num, struct regmap **regmap, 1347 int *reg, u8 *bit) 1348 { 1349 struct rockchip_pinctrl *info = bank->drvdata; 1350 1351 /* The first 24 pins of the first bank are located in PMU */ 1352 if (bank->bank_num == 0) { 1353 *regmap = info->regmap_pmu; 1354 *reg = RV1108_DRV_PMU_OFFSET; 1355 } else { 1356 *regmap = info->regmap_base; 1357 *reg = RV1108_DRV_GRF_OFFSET; 1358 1359 /* correct the offset, as we're starting with the 2nd bank */ 1360 *reg -= 0x10; 1361 *reg += bank->bank_num * RV1108_DRV_BANK_STRIDE; 1362 } 1363 1364 *reg += ((pin_num / RV1108_DRV_PINS_PER_REG) * 4); 1365 *bit = pin_num % RV1108_DRV_PINS_PER_REG; 1366 *bit *= RV1108_DRV_BITS_PER_PIN; 1367 } 1368 1369 #define RV1108_SCHMITT_PMU_OFFSET 0x30 1370 #define RV1108_SCHMITT_GRF_OFFSET 0x388 1371 #define RV1108_SCHMITT_BANK_STRIDE 8 1372 #define RV1108_SCHMITT_PINS_PER_GRF_REG 16 1373 #define RV1108_SCHMITT_PINS_PER_PMU_REG 8 1374 1375 static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1376 int pin_num, 1377 struct regmap **regmap, 1378 int *reg, u8 *bit) 1379 { 1380 struct rockchip_pinctrl *info = bank->drvdata; 1381 int pins_per_reg; 1382 1383 if (bank->bank_num == 0) { 1384 *regmap = info->regmap_pmu; 1385 *reg = RV1108_SCHMITT_PMU_OFFSET; 1386 pins_per_reg = RV1108_SCHMITT_PINS_PER_PMU_REG; 1387 } else { 1388 *regmap = info->regmap_base; 1389 *reg = RV1108_SCHMITT_GRF_OFFSET; 1390 pins_per_reg = RV1108_SCHMITT_PINS_PER_GRF_REG; 1391 *reg += (bank->bank_num - 1) * RV1108_SCHMITT_BANK_STRIDE; 1392 } 1393 *reg += ((pin_num / pins_per_reg) * 4); 1394 *bit = pin_num % pins_per_reg; 1395 1396 return 0; 1397 } 1398 1399 #define RK3308_SCHMITT_PINS_PER_REG 8 1400 #define RK3308_SCHMITT_BANK_STRIDE 16 1401 #define RK3308_SCHMITT_GRF_OFFSET 0x1a0 1402 1403 static int rk3308_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1404 int pin_num, struct regmap **regmap, 1405 int *reg, u8 *bit) 1406 { 1407 struct rockchip_pinctrl *info = bank->drvdata; 1408 1409 *regmap = info->regmap_base; 1410 *reg = RK3308_SCHMITT_GRF_OFFSET; 1411 1412 *reg += bank->bank_num * RK3308_SCHMITT_BANK_STRIDE; 1413 *reg += ((pin_num / RK3308_SCHMITT_PINS_PER_REG) * 4); 1414 *bit = pin_num % RK3308_SCHMITT_PINS_PER_REG; 1415 1416 return 0; 1417 } 1418 1419 #define RK2928_PULL_OFFSET 0x118 1420 #define RK2928_PULL_PINS_PER_REG 16 1421 #define RK2928_PULL_BANK_STRIDE 8 1422 1423 static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1424 int pin_num, struct regmap **regmap, 1425 int *reg, u8 *bit) 1426 { 1427 struct rockchip_pinctrl *info = bank->drvdata; 1428 1429 *regmap = info->regmap_base; 1430 *reg = RK2928_PULL_OFFSET; 1431 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; 1432 *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4; 1433 1434 *bit = pin_num % RK2928_PULL_PINS_PER_REG; 1435 }; 1436 1437 #define RK3128_PULL_OFFSET 0x118 1438 1439 static void rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1440 int pin_num, struct regmap **regmap, 1441 int *reg, u8 *bit) 1442 { 1443 struct rockchip_pinctrl *info = bank->drvdata; 1444 1445 *regmap = info->regmap_base; 1446 *reg = RK3128_PULL_OFFSET; 1447 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; 1448 *reg += ((pin_num / RK2928_PULL_PINS_PER_REG) * 4); 1449 1450 *bit = pin_num % RK2928_PULL_PINS_PER_REG; 1451 } 1452 1453 #define RK3188_PULL_OFFSET 0x164 1454 #define RK3188_PULL_BITS_PER_PIN 2 1455 #define RK3188_PULL_PINS_PER_REG 8 1456 #define RK3188_PULL_BANK_STRIDE 16 1457 #define RK3188_PULL_PMU_OFFSET 0x64 1458 1459 static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1460 int pin_num, struct regmap **regmap, 1461 int *reg, u8 *bit) 1462 { 1463 struct rockchip_pinctrl *info = bank->drvdata; 1464 1465 /* The first 12 pins of the first bank are located elsewhere */ 1466 if (bank->bank_num == 0 && pin_num < 12) { 1467 *regmap = info->regmap_pmu ? info->regmap_pmu 1468 : bank->regmap_pull; 1469 *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0; 1470 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1471 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 1472 *bit *= RK3188_PULL_BITS_PER_PIN; 1473 } else { 1474 *regmap = info->regmap_pull ? info->regmap_pull 1475 : info->regmap_base; 1476 *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET; 1477 1478 /* correct the offset, as it is the 2nd pull register */ 1479 *reg -= 4; 1480 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1481 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1482 1483 /* 1484 * The bits in these registers have an inverse ordering 1485 * with the lowest pin being in bits 15:14 and the highest 1486 * pin in bits 1:0 1487 */ 1488 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG); 1489 *bit *= RK3188_PULL_BITS_PER_PIN; 1490 } 1491 } 1492 1493 #define RK3288_PULL_OFFSET 0x140 1494 static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1495 int pin_num, struct regmap **regmap, 1496 int *reg, u8 *bit) 1497 { 1498 struct rockchip_pinctrl *info = bank->drvdata; 1499 1500 /* The first 24 pins of the first bank are located in PMU */ 1501 if (bank->bank_num == 0) { 1502 *regmap = info->regmap_pmu; 1503 *reg = RK3188_PULL_PMU_OFFSET; 1504 1505 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1506 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 1507 *bit *= RK3188_PULL_BITS_PER_PIN; 1508 } else { 1509 *regmap = info->regmap_base; 1510 *reg = RK3288_PULL_OFFSET; 1511 1512 /* correct the offset, as we're starting with the 2nd bank */ 1513 *reg -= 0x10; 1514 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1515 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1516 1517 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1518 *bit *= RK3188_PULL_BITS_PER_PIN; 1519 } 1520 } 1521 1522 #define RK3288_DRV_PMU_OFFSET 0x70 1523 #define RK3288_DRV_GRF_OFFSET 0x1c0 1524 #define RK3288_DRV_BITS_PER_PIN 2 1525 #define RK3288_DRV_PINS_PER_REG 8 1526 #define RK3288_DRV_BANK_STRIDE 16 1527 1528 static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1529 int pin_num, struct regmap **regmap, 1530 int *reg, u8 *bit) 1531 { 1532 struct rockchip_pinctrl *info = bank->drvdata; 1533 1534 /* The first 24 pins of the first bank are located in PMU */ 1535 if (bank->bank_num == 0) { 1536 *regmap = info->regmap_pmu; 1537 *reg = RK3288_DRV_PMU_OFFSET; 1538 1539 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1540 *bit = pin_num % RK3288_DRV_PINS_PER_REG; 1541 *bit *= RK3288_DRV_BITS_PER_PIN; 1542 } else { 1543 *regmap = info->regmap_base; 1544 *reg = RK3288_DRV_GRF_OFFSET; 1545 1546 /* correct the offset, as we're starting with the 2nd bank */ 1547 *reg -= 0x10; 1548 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 1549 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1550 1551 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 1552 *bit *= RK3288_DRV_BITS_PER_PIN; 1553 } 1554 } 1555 1556 #define RK3228_PULL_OFFSET 0x100 1557 1558 static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1559 int pin_num, struct regmap **regmap, 1560 int *reg, u8 *bit) 1561 { 1562 struct rockchip_pinctrl *info = bank->drvdata; 1563 1564 *regmap = info->regmap_base; 1565 *reg = RK3228_PULL_OFFSET; 1566 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1567 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1568 1569 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1570 *bit *= RK3188_PULL_BITS_PER_PIN; 1571 } 1572 1573 #define RK3228_DRV_GRF_OFFSET 0x200 1574 1575 static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1576 int pin_num, struct regmap **regmap, 1577 int *reg, u8 *bit) 1578 { 1579 struct rockchip_pinctrl *info = bank->drvdata; 1580 1581 *regmap = info->regmap_base; 1582 *reg = RK3228_DRV_GRF_OFFSET; 1583 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 1584 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1585 1586 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 1587 *bit *= RK3288_DRV_BITS_PER_PIN; 1588 } 1589 1590 #define RK3308_PULL_OFFSET 0xa0 1591 1592 static void rk3308_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1593 int pin_num, struct regmap **regmap, 1594 int *reg, u8 *bit) 1595 { 1596 struct rockchip_pinctrl *info = bank->drvdata; 1597 1598 *regmap = info->regmap_base; 1599 *reg = RK3308_PULL_OFFSET; 1600 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1601 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1602 1603 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1604 *bit *= RK3188_PULL_BITS_PER_PIN; 1605 } 1606 1607 #define RK3308_DRV_GRF_OFFSET 0x100 1608 1609 static void rk3308_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1610 int pin_num, struct regmap **regmap, 1611 int *reg, u8 *bit) 1612 { 1613 struct rockchip_pinctrl *info = bank->drvdata; 1614 1615 *regmap = info->regmap_base; 1616 *reg = RK3308_DRV_GRF_OFFSET; 1617 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 1618 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1619 1620 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 1621 *bit *= RK3288_DRV_BITS_PER_PIN; 1622 } 1623 1624 #define RK3368_PULL_GRF_OFFSET 0x100 1625 #define RK3368_PULL_PMU_OFFSET 0x10 1626 1627 static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1628 int pin_num, struct regmap **regmap, 1629 int *reg, u8 *bit) 1630 { 1631 struct rockchip_pinctrl *info = bank->drvdata; 1632 1633 /* The first 32 pins of the first bank are located in PMU */ 1634 if (bank->bank_num == 0) { 1635 *regmap = info->regmap_pmu; 1636 *reg = RK3368_PULL_PMU_OFFSET; 1637 1638 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1639 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 1640 *bit *= RK3188_PULL_BITS_PER_PIN; 1641 } else { 1642 *regmap = info->regmap_base; 1643 *reg = RK3368_PULL_GRF_OFFSET; 1644 1645 /* correct the offset, as we're starting with the 2nd bank */ 1646 *reg -= 0x10; 1647 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1648 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1649 1650 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1651 *bit *= RK3188_PULL_BITS_PER_PIN; 1652 } 1653 } 1654 1655 #define RK3368_DRV_PMU_OFFSET 0x20 1656 #define RK3368_DRV_GRF_OFFSET 0x200 1657 1658 static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1659 int pin_num, struct regmap **regmap, 1660 int *reg, u8 *bit) 1661 { 1662 struct rockchip_pinctrl *info = bank->drvdata; 1663 1664 /* The first 32 pins of the first bank are located in PMU */ 1665 if (bank->bank_num == 0) { 1666 *regmap = info->regmap_pmu; 1667 *reg = RK3368_DRV_PMU_OFFSET; 1668 1669 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1670 *bit = pin_num % RK3288_DRV_PINS_PER_REG; 1671 *bit *= RK3288_DRV_BITS_PER_PIN; 1672 } else { 1673 *regmap = info->regmap_base; 1674 *reg = RK3368_DRV_GRF_OFFSET; 1675 1676 /* correct the offset, as we're starting with the 2nd bank */ 1677 *reg -= 0x10; 1678 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 1679 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1680 1681 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 1682 *bit *= RK3288_DRV_BITS_PER_PIN; 1683 } 1684 } 1685 1686 #define RK3399_PULL_GRF_OFFSET 0xe040 1687 #define RK3399_PULL_PMU_OFFSET 0x40 1688 #define RK3399_DRV_3BITS_PER_PIN 3 1689 1690 static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1691 int pin_num, struct regmap **regmap, 1692 int *reg, u8 *bit) 1693 { 1694 struct rockchip_pinctrl *info = bank->drvdata; 1695 1696 /* The bank0:16 and bank1:32 pins are located in PMU */ 1697 if ((bank->bank_num == 0) || (bank->bank_num == 1)) { 1698 *regmap = info->regmap_pmu; 1699 *reg = RK3399_PULL_PMU_OFFSET; 1700 1701 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1702 1703 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1704 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 1705 *bit *= RK3188_PULL_BITS_PER_PIN; 1706 } else { 1707 *regmap = info->regmap_base; 1708 *reg = RK3399_PULL_GRF_OFFSET; 1709 1710 /* correct the offset, as we're starting with the 3rd bank */ 1711 *reg -= 0x20; 1712 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1713 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1714 1715 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1716 *bit *= RK3188_PULL_BITS_PER_PIN; 1717 } 1718 } 1719 1720 static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1721 int pin_num, struct regmap **regmap, 1722 int *reg, u8 *bit) 1723 { 1724 struct rockchip_pinctrl *info = bank->drvdata; 1725 int drv_num = (pin_num / 8); 1726 1727 /* The bank0:16 and bank1:32 pins are located in PMU */ 1728 if ((bank->bank_num == 0) || (bank->bank_num == 1)) 1729 *regmap = info->regmap_pmu; 1730 else 1731 *regmap = info->regmap_base; 1732 1733 *reg = bank->drv[drv_num].offset; 1734 if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) || 1735 (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY)) 1736 *bit = (pin_num % 8) * 3; 1737 else 1738 *bit = (pin_num % 8) * 2; 1739 } 1740 1741 #define RK3568_PULL_PMU_OFFSET 0x20 1742 #define RK3568_PULL_GRF_OFFSET 0x80 1743 #define RK3568_PULL_BITS_PER_PIN 2 1744 #define RK3568_PULL_PINS_PER_REG 8 1745 #define RK3568_PULL_BANK_STRIDE 0x10 1746 1747 static void rk3568_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1748 int pin_num, struct regmap **regmap, 1749 int *reg, u8 *bit) 1750 { 1751 struct rockchip_pinctrl *info = bank->drvdata; 1752 1753 if (bank->bank_num == 0) { 1754 *regmap = info->regmap_pmu; 1755 *reg = RK3568_PULL_PMU_OFFSET; 1756 *reg += bank->bank_num * RK3568_PULL_BANK_STRIDE; 1757 *reg += ((pin_num / RK3568_PULL_PINS_PER_REG) * 4); 1758 1759 *bit = pin_num % RK3568_PULL_PINS_PER_REG; 1760 *bit *= RK3568_PULL_BITS_PER_PIN; 1761 } else { 1762 *regmap = info->regmap_base; 1763 *reg = RK3568_PULL_GRF_OFFSET; 1764 *reg += (bank->bank_num - 1) * RK3568_PULL_BANK_STRIDE; 1765 *reg += ((pin_num / RK3568_PULL_PINS_PER_REG) * 4); 1766 1767 *bit = (pin_num % RK3568_PULL_PINS_PER_REG); 1768 *bit *= RK3568_PULL_BITS_PER_PIN; 1769 } 1770 } 1771 1772 #define RK3568_DRV_PMU_OFFSET 0x70 1773 #define RK3568_DRV_GRF_OFFSET 0x200 1774 #define RK3568_DRV_BITS_PER_PIN 8 1775 #define RK3568_DRV_PINS_PER_REG 2 1776 #define RK3568_DRV_BANK_STRIDE 0x40 1777 1778 static void rk3568_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1779 int pin_num, struct regmap **regmap, 1780 int *reg, u8 *bit) 1781 { 1782 struct rockchip_pinctrl *info = bank->drvdata; 1783 1784 /* The first 32 pins of the first bank are located in PMU */ 1785 if (bank->bank_num == 0) { 1786 *regmap = info->regmap_pmu; 1787 *reg = RK3568_DRV_PMU_OFFSET; 1788 *reg += ((pin_num / RK3568_DRV_PINS_PER_REG) * 4); 1789 1790 *bit = pin_num % RK3568_DRV_PINS_PER_REG; 1791 *bit *= RK3568_DRV_BITS_PER_PIN; 1792 } else { 1793 *regmap = info->regmap_base; 1794 *reg = RK3568_DRV_GRF_OFFSET; 1795 *reg += (bank->bank_num - 1) * RK3568_DRV_BANK_STRIDE; 1796 *reg += ((pin_num / RK3568_DRV_PINS_PER_REG) * 4); 1797 1798 *bit = (pin_num % RK3568_DRV_PINS_PER_REG); 1799 *bit *= RK3568_DRV_BITS_PER_PIN; 1800 } 1801 } 1802 1803 static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = { 1804 { 2, 4, 8, 12, -1, -1, -1, -1 }, 1805 { 3, 6, 9, 12, -1, -1, -1, -1 }, 1806 { 5, 10, 15, 20, -1, -1, -1, -1 }, 1807 { 4, 6, 8, 10, 12, 14, 16, 18 }, 1808 { 4, 7, 10, 13, 16, 19, 22, 26 } 1809 }; 1810 1811 static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank, 1812 int pin_num) 1813 { 1814 struct rockchip_pinctrl *info = bank->drvdata; 1815 struct rockchip_pin_ctrl *ctrl = info->ctrl; 1816 struct regmap *regmap; 1817 int reg, ret; 1818 u32 data, temp, rmask_bits; 1819 u8 bit; 1820 int drv_type = bank->drv[pin_num / 8].drv_type; 1821 1822 ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); 1823 1824 switch (drv_type) { 1825 case DRV_TYPE_IO_1V8_3V0_AUTO: 1826 case DRV_TYPE_IO_3V3_ONLY: 1827 rmask_bits = RK3399_DRV_3BITS_PER_PIN; 1828 switch (bit) { 1829 case 0 ... 12: 1830 /* regular case, nothing to do */ 1831 break; 1832 case 15: 1833 /* 1834 * drive-strength offset is special, as it is 1835 * spread over 2 registers 1836 */ 1837 ret = regmap_read(regmap, reg, &data); 1838 if (ret) 1839 return ret; 1840 1841 ret = regmap_read(regmap, reg + 0x4, &temp); 1842 if (ret) 1843 return ret; 1844 1845 /* 1846 * the bit data[15] contains bit 0 of the value 1847 * while temp[1:0] contains bits 2 and 1 1848 */ 1849 data >>= 15; 1850 temp &= 0x3; 1851 temp <<= 1; 1852 data |= temp; 1853 1854 return rockchip_perpin_drv_list[drv_type][data]; 1855 case 18 ... 21: 1856 /* setting fully enclosed in the second register */ 1857 reg += 4; 1858 bit -= 16; 1859 break; 1860 default: 1861 dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n", 1862 bit, drv_type); 1863 return -EINVAL; 1864 } 1865 1866 break; 1867 case DRV_TYPE_IO_DEFAULT: 1868 case DRV_TYPE_IO_1V8_OR_3V0: 1869 case DRV_TYPE_IO_1V8_ONLY: 1870 rmask_bits = RK3288_DRV_BITS_PER_PIN; 1871 break; 1872 default: 1873 dev_err(info->dev, "unsupported pinctrl drive type: %d\n", 1874 drv_type); 1875 return -EINVAL; 1876 } 1877 1878 ret = regmap_read(regmap, reg, &data); 1879 if (ret) 1880 return ret; 1881 1882 data >>= bit; 1883 data &= (1 << rmask_bits) - 1; 1884 1885 return rockchip_perpin_drv_list[drv_type][data]; 1886 } 1887 1888 static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank, 1889 int pin_num, int strength) 1890 { 1891 struct rockchip_pinctrl *info = bank->drvdata; 1892 struct rockchip_pin_ctrl *ctrl = info->ctrl; 1893 struct regmap *regmap; 1894 int reg, ret, i; 1895 u32 data, rmask, rmask_bits, temp; 1896 u8 bit; 1897 int drv_type = bank->drv[pin_num / 8].drv_type; 1898 1899 dev_dbg(info->dev, "setting drive of GPIO%d-%d to %d\n", 1900 bank->bank_num, pin_num, strength); 1901 1902 ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); 1903 if (ctrl->type == RK3568) { 1904 rmask_bits = RK3568_DRV_BITS_PER_PIN; 1905 ret = (1 << (strength + 1)) - 1; 1906 goto config; 1907 } 1908 1909 ret = -EINVAL; 1910 for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) { 1911 if (rockchip_perpin_drv_list[drv_type][i] == strength) { 1912 ret = i; 1913 break; 1914 } else if (rockchip_perpin_drv_list[drv_type][i] < 0) { 1915 ret = rockchip_perpin_drv_list[drv_type][i]; 1916 break; 1917 } 1918 } 1919 1920 if (ret < 0) { 1921 dev_err(info->dev, "unsupported driver strength %d\n", 1922 strength); 1923 return ret; 1924 } 1925 1926 switch (drv_type) { 1927 case DRV_TYPE_IO_1V8_3V0_AUTO: 1928 case DRV_TYPE_IO_3V3_ONLY: 1929 rmask_bits = RK3399_DRV_3BITS_PER_PIN; 1930 switch (bit) { 1931 case 0 ... 12: 1932 /* regular case, nothing to do */ 1933 break; 1934 case 15: 1935 /* 1936 * drive-strength offset is special, as it is spread 1937 * over 2 registers, the bit data[15] contains bit 0 1938 * of the value while temp[1:0] contains bits 2 and 1 1939 */ 1940 data = (ret & 0x1) << 15; 1941 temp = (ret >> 0x1) & 0x3; 1942 1943 rmask = BIT(15) | BIT(31); 1944 data |= BIT(31); 1945 ret = regmap_update_bits(regmap, reg, rmask, data); 1946 if (ret) 1947 return ret; 1948 1949 rmask = 0x3 | (0x3 << 16); 1950 temp |= (0x3 << 16); 1951 reg += 0x4; 1952 ret = regmap_update_bits(regmap, reg, rmask, temp); 1953 1954 return ret; 1955 case 18 ... 21: 1956 /* setting fully enclosed in the second register */ 1957 reg += 4; 1958 bit -= 16; 1959 break; 1960 default: 1961 dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n", 1962 bit, drv_type); 1963 return -EINVAL; 1964 } 1965 break; 1966 case DRV_TYPE_IO_DEFAULT: 1967 case DRV_TYPE_IO_1V8_OR_3V0: 1968 case DRV_TYPE_IO_1V8_ONLY: 1969 rmask_bits = RK3288_DRV_BITS_PER_PIN; 1970 break; 1971 default: 1972 dev_err(info->dev, "unsupported pinctrl drive type: %d\n", 1973 drv_type); 1974 return -EINVAL; 1975 } 1976 1977 config: 1978 /* enable the write to the equivalent lower bits */ 1979 data = ((1 << rmask_bits) - 1) << (bit + 16); 1980 rmask = data | (data >> 16); 1981 data |= (ret << bit); 1982 1983 ret = regmap_update_bits(regmap, reg, rmask, data); 1984 1985 return ret; 1986 } 1987 1988 static int rockchip_pull_list[PULL_TYPE_MAX][4] = { 1989 { 1990 PIN_CONFIG_BIAS_DISABLE, 1991 PIN_CONFIG_BIAS_PULL_UP, 1992 PIN_CONFIG_BIAS_PULL_DOWN, 1993 PIN_CONFIG_BIAS_BUS_HOLD 1994 }, 1995 { 1996 PIN_CONFIG_BIAS_DISABLE, 1997 PIN_CONFIG_BIAS_PULL_DOWN, 1998 PIN_CONFIG_BIAS_DISABLE, 1999 PIN_CONFIG_BIAS_PULL_UP 2000 }, 2001 }; 2002 2003 static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num) 2004 { 2005 struct rockchip_pinctrl *info = bank->drvdata; 2006 struct rockchip_pin_ctrl *ctrl = info->ctrl; 2007 struct regmap *regmap; 2008 int reg, ret, pull_type; 2009 u8 bit; 2010 u32 data; 2011 2012 /* rk3066b does support any pulls */ 2013 if (ctrl->type == RK3066B) 2014 return PIN_CONFIG_BIAS_DISABLE; 2015 2016 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); 2017 2018 ret = regmap_read(regmap, reg, &data); 2019 if (ret) 2020 return ret; 2021 2022 switch (ctrl->type) { 2023 case RK2928: 2024 case RK3128: 2025 return !(data & BIT(bit)) 2026 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT 2027 : PIN_CONFIG_BIAS_DISABLE; 2028 case PX30: 2029 case RV1108: 2030 case RK3188: 2031 case RK3288: 2032 case RK3308: 2033 case RK3368: 2034 case RK3399: 2035 pull_type = bank->pull_type[pin_num / 8]; 2036 data >>= bit; 2037 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1; 2038 2039 return rockchip_pull_list[pull_type][data]; 2040 default: 2041 dev_err(info->dev, "unsupported pinctrl type\n"); 2042 return -EINVAL; 2043 }; 2044 } 2045 2046 static int rockchip_set_pull(struct rockchip_pin_bank *bank, 2047 int pin_num, int pull) 2048 { 2049 struct rockchip_pinctrl *info = bank->drvdata; 2050 struct rockchip_pin_ctrl *ctrl = info->ctrl; 2051 struct regmap *regmap; 2052 int reg, ret, i, pull_type; 2053 u8 bit; 2054 u32 data, rmask; 2055 2056 dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n", 2057 bank->bank_num, pin_num, pull); 2058 2059 /* rk3066b does support any pulls */ 2060 if (ctrl->type == RK3066B) 2061 return pull ? -EINVAL : 0; 2062 2063 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); 2064 2065 switch (ctrl->type) { 2066 case RK2928: 2067 case RK3128: 2068 data = BIT(bit + 16); 2069 if (pull == PIN_CONFIG_BIAS_DISABLE) 2070 data |= BIT(bit); 2071 ret = regmap_write(regmap, reg, data); 2072 break; 2073 case PX30: 2074 case RV1108: 2075 case RK3188: 2076 case RK3288: 2077 case RK3308: 2078 case RK3368: 2079 case RK3399: 2080 case RK3568: 2081 pull_type = bank->pull_type[pin_num / 8]; 2082 ret = -EINVAL; 2083 for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]); 2084 i++) { 2085 if (rockchip_pull_list[pull_type][i] == pull) { 2086 ret = i; 2087 break; 2088 } 2089 } 2090 /* 2091 * In the TRM, pull-up being 1 for everything except the GPIO0_D0-D6, 2092 * where that pull up value becomes 3. 2093 */ 2094 if (ctrl->type == RK3568 && bank->bank_num == 0 && pin_num >= 27 && pin_num <= 30) { 2095 if (ret == 1) 2096 ret = 3; 2097 } 2098 2099 if (ret < 0) { 2100 dev_err(info->dev, "unsupported pull setting %d\n", 2101 pull); 2102 return ret; 2103 } 2104 2105 /* enable the write to the equivalent lower bits */ 2106 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16); 2107 rmask = data | (data >> 16); 2108 data |= (ret << bit); 2109 2110 ret = regmap_update_bits(regmap, reg, rmask, data); 2111 break; 2112 default: 2113 dev_err(info->dev, "unsupported pinctrl type\n"); 2114 return -EINVAL; 2115 } 2116 2117 return ret; 2118 } 2119 2120 #define RK3328_SCHMITT_BITS_PER_PIN 1 2121 #define RK3328_SCHMITT_PINS_PER_REG 16 2122 #define RK3328_SCHMITT_BANK_STRIDE 8 2123 #define RK3328_SCHMITT_GRF_OFFSET 0x380 2124 2125 static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 2126 int pin_num, 2127 struct regmap **regmap, 2128 int *reg, u8 *bit) 2129 { 2130 struct rockchip_pinctrl *info = bank->drvdata; 2131 2132 *regmap = info->regmap_base; 2133 *reg = RK3328_SCHMITT_GRF_OFFSET; 2134 2135 *reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE; 2136 *reg += ((pin_num / RK3328_SCHMITT_PINS_PER_REG) * 4); 2137 *bit = pin_num % RK3328_SCHMITT_PINS_PER_REG; 2138 2139 return 0; 2140 } 2141 2142 #define RK3568_SCHMITT_BITS_PER_PIN 2 2143 #define RK3568_SCHMITT_PINS_PER_REG 8 2144 #define RK3568_SCHMITT_BANK_STRIDE 0x10 2145 #define RK3568_SCHMITT_GRF_OFFSET 0xc0 2146 #define RK3568_SCHMITT_PMUGRF_OFFSET 0x30 2147 2148 static int rk3568_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 2149 int pin_num, 2150 struct regmap **regmap, 2151 int *reg, u8 *bit) 2152 { 2153 struct rockchip_pinctrl *info = bank->drvdata; 2154 2155 if (bank->bank_num == 0) { 2156 *regmap = info->regmap_pmu; 2157 *reg = RK3568_SCHMITT_PMUGRF_OFFSET; 2158 } else { 2159 *regmap = info->regmap_base; 2160 *reg = RK3568_SCHMITT_GRF_OFFSET; 2161 *reg += (bank->bank_num - 1) * RK3568_SCHMITT_BANK_STRIDE; 2162 } 2163 2164 *reg += ((pin_num / RK3568_SCHMITT_PINS_PER_REG) * 4); 2165 *bit = pin_num % RK3568_SCHMITT_PINS_PER_REG; 2166 *bit *= RK3568_SCHMITT_BITS_PER_PIN; 2167 2168 return 0; 2169 } 2170 2171 static int rockchip_get_schmitt(struct rockchip_pin_bank *bank, int pin_num) 2172 { 2173 struct rockchip_pinctrl *info = bank->drvdata; 2174 struct rockchip_pin_ctrl *ctrl = info->ctrl; 2175 struct regmap *regmap; 2176 int reg, ret; 2177 u8 bit; 2178 u32 data; 2179 2180 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit); 2181 if (ret) 2182 return ret; 2183 2184 ret = regmap_read(regmap, reg, &data); 2185 if (ret) 2186 return ret; 2187 2188 data >>= bit; 2189 switch (ctrl->type) { 2190 case RK3568: 2191 return data & ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1); 2192 default: 2193 break; 2194 } 2195 2196 return data & 0x1; 2197 } 2198 2199 static int rockchip_set_schmitt(struct rockchip_pin_bank *bank, 2200 int pin_num, int enable) 2201 { 2202 struct rockchip_pinctrl *info = bank->drvdata; 2203 struct rockchip_pin_ctrl *ctrl = info->ctrl; 2204 struct regmap *regmap; 2205 int reg, ret; 2206 u8 bit; 2207 u32 data, rmask; 2208 2209 dev_dbg(info->dev, "setting input schmitt of GPIO%d-%d to %d\n", 2210 bank->bank_num, pin_num, enable); 2211 2212 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit); 2213 if (ret) 2214 return ret; 2215 2216 /* enable the write to the equivalent lower bits */ 2217 switch (ctrl->type) { 2218 case RK3568: 2219 data = ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1) << (bit + 16); 2220 rmask = data | (data >> 16); 2221 data |= ((enable ? 0x2 : 0x1) << bit); 2222 break; 2223 default: 2224 data = BIT(bit + 16) | (enable << bit); 2225 rmask = BIT(bit + 16) | BIT(bit); 2226 break; 2227 } 2228 2229 return regmap_update_bits(regmap, reg, rmask, data); 2230 } 2231 2232 /* 2233 * Pinmux_ops handling 2234 */ 2235 2236 static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev) 2237 { 2238 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 2239 2240 return info->nfunctions; 2241 } 2242 2243 static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev, 2244 unsigned selector) 2245 { 2246 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 2247 2248 return info->functions[selector].name; 2249 } 2250 2251 static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev, 2252 unsigned selector, const char * const **groups, 2253 unsigned * const num_groups) 2254 { 2255 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 2256 2257 *groups = info->functions[selector].groups; 2258 *num_groups = info->functions[selector].ngroups; 2259 2260 return 0; 2261 } 2262 2263 static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector, 2264 unsigned group) 2265 { 2266 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 2267 const unsigned int *pins = info->groups[group].pins; 2268 const struct rockchip_pin_config *data = info->groups[group].data; 2269 struct rockchip_pin_bank *bank; 2270 int cnt, ret = 0; 2271 2272 dev_dbg(info->dev, "enable function %s group %s\n", 2273 info->functions[selector].name, info->groups[group].name); 2274 2275 /* 2276 * for each pin in the pin group selected, program the corresponding 2277 * pin function number in the config register. 2278 */ 2279 for (cnt = 0; cnt < info->groups[group].npins; cnt++) { 2280 bank = pin_to_bank(info, pins[cnt]); 2281 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 2282 data[cnt].func); 2283 if (ret) 2284 break; 2285 } 2286 2287 if (ret) { 2288 /* revert the already done pin settings */ 2289 for (cnt--; cnt >= 0; cnt--) 2290 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0); 2291 2292 return ret; 2293 } 2294 2295 return 0; 2296 } 2297 2298 static int rockchip_gpio_get_direction(struct gpio_chip *chip, unsigned offset) 2299 { 2300 struct rockchip_pin_bank *bank = gpiochip_get_data(chip); 2301 u32 data; 2302 int ret; 2303 2304 ret = clk_enable(bank->clk); 2305 if (ret < 0) { 2306 dev_err(bank->drvdata->dev, 2307 "failed to enable clock for bank %s\n", bank->name); 2308 return ret; 2309 } 2310 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); 2311 clk_disable(bank->clk); 2312 2313 if (data & BIT(offset)) 2314 return GPIO_LINE_DIRECTION_OUT; 2315 2316 return GPIO_LINE_DIRECTION_IN; 2317 } 2318 2319 /* 2320 * The calls to gpio_direction_output() and gpio_direction_input() 2321 * leads to this function call (via the pinctrl_gpio_direction_{input|output}() 2322 * function called from the gpiolib interface). 2323 */ 2324 static int _rockchip_pmx_gpio_set_direction(struct gpio_chip *chip, 2325 int pin, bool input) 2326 { 2327 struct rockchip_pin_bank *bank; 2328 int ret; 2329 unsigned long flags; 2330 u32 data; 2331 2332 bank = gpiochip_get_data(chip); 2333 2334 ret = rockchip_set_mux(bank, pin, RK_FUNC_GPIO); 2335 if (ret < 0) 2336 return ret; 2337 2338 clk_enable(bank->clk); 2339 raw_spin_lock_irqsave(&bank->slock, flags); 2340 2341 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); 2342 /* set bit to 1 for output, 0 for input */ 2343 if (!input) 2344 data |= BIT(pin); 2345 else 2346 data &= ~BIT(pin); 2347 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR); 2348 2349 raw_spin_unlock_irqrestore(&bank->slock, flags); 2350 clk_disable(bank->clk); 2351 2352 return 0; 2353 } 2354 2355 static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, 2356 struct pinctrl_gpio_range *range, 2357 unsigned offset, bool input) 2358 { 2359 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 2360 struct gpio_chip *chip; 2361 int pin; 2362 2363 chip = range->gc; 2364 pin = offset - chip->base; 2365 dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n", 2366 offset, range->name, pin, input ? "input" : "output"); 2367 2368 return _rockchip_pmx_gpio_set_direction(chip, offset - chip->base, 2369 input); 2370 } 2371 2372 static const struct pinmux_ops rockchip_pmx_ops = { 2373 .get_functions_count = rockchip_pmx_get_funcs_count, 2374 .get_function_name = rockchip_pmx_get_func_name, 2375 .get_function_groups = rockchip_pmx_get_groups, 2376 .set_mux = rockchip_pmx_set, 2377 .gpio_set_direction = rockchip_pmx_gpio_set_direction, 2378 }; 2379 2380 /* 2381 * Pinconf_ops handling 2382 */ 2383 2384 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl, 2385 enum pin_config_param pull) 2386 { 2387 switch (ctrl->type) { 2388 case RK2928: 2389 case RK3128: 2390 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT || 2391 pull == PIN_CONFIG_BIAS_DISABLE); 2392 case RK3066B: 2393 return pull ? false : true; 2394 case PX30: 2395 case RV1108: 2396 case RK3188: 2397 case RK3288: 2398 case RK3308: 2399 case RK3368: 2400 case RK3399: 2401 case RK3568: 2402 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT); 2403 } 2404 2405 return false; 2406 } 2407 2408 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value); 2409 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset); 2410 2411 /* set the pin config settings for a specified pin */ 2412 static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 2413 unsigned long *configs, unsigned num_configs) 2414 { 2415 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 2416 struct rockchip_pin_bank *bank = pin_to_bank(info, pin); 2417 enum pin_config_param param; 2418 u32 arg; 2419 int i; 2420 int rc; 2421 2422 for (i = 0; i < num_configs; i++) { 2423 param = pinconf_to_config_param(configs[i]); 2424 arg = pinconf_to_config_argument(configs[i]); 2425 2426 switch (param) { 2427 case PIN_CONFIG_BIAS_DISABLE: 2428 rc = rockchip_set_pull(bank, pin - bank->pin_base, 2429 param); 2430 if (rc) 2431 return rc; 2432 break; 2433 case PIN_CONFIG_BIAS_PULL_UP: 2434 case PIN_CONFIG_BIAS_PULL_DOWN: 2435 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: 2436 case PIN_CONFIG_BIAS_BUS_HOLD: 2437 if (!rockchip_pinconf_pull_valid(info->ctrl, param)) 2438 return -ENOTSUPP; 2439 2440 if (!arg) 2441 return -EINVAL; 2442 2443 rc = rockchip_set_pull(bank, pin - bank->pin_base, 2444 param); 2445 if (rc) 2446 return rc; 2447 break; 2448 case PIN_CONFIG_OUTPUT: 2449 rockchip_gpio_set(&bank->gpio_chip, 2450 pin - bank->pin_base, arg); 2451 rc = _rockchip_pmx_gpio_set_direction(&bank->gpio_chip, 2452 pin - bank->pin_base, false); 2453 if (rc) 2454 return rc; 2455 break; 2456 case PIN_CONFIG_DRIVE_STRENGTH: 2457 /* rk3288 is the first with per-pin drive-strength */ 2458 if (!info->ctrl->drv_calc_reg) 2459 return -ENOTSUPP; 2460 2461 rc = rockchip_set_drive_perpin(bank, 2462 pin - bank->pin_base, arg); 2463 if (rc < 0) 2464 return rc; 2465 break; 2466 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 2467 if (!info->ctrl->schmitt_calc_reg) 2468 return -ENOTSUPP; 2469 2470 rc = rockchip_set_schmitt(bank, 2471 pin - bank->pin_base, arg); 2472 if (rc < 0) 2473 return rc; 2474 break; 2475 default: 2476 return -ENOTSUPP; 2477 break; 2478 } 2479 } /* for each config */ 2480 2481 return 0; 2482 } 2483 2484 /* get the pin config settings for a specified pin */ 2485 static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, 2486 unsigned long *config) 2487 { 2488 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 2489 struct rockchip_pin_bank *bank = pin_to_bank(info, pin); 2490 enum pin_config_param param = pinconf_to_config_param(*config); 2491 u16 arg; 2492 int rc; 2493 2494 switch (param) { 2495 case PIN_CONFIG_BIAS_DISABLE: 2496 if (rockchip_get_pull(bank, pin - bank->pin_base) != param) 2497 return -EINVAL; 2498 2499 arg = 0; 2500 break; 2501 case PIN_CONFIG_BIAS_PULL_UP: 2502 case PIN_CONFIG_BIAS_PULL_DOWN: 2503 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: 2504 case PIN_CONFIG_BIAS_BUS_HOLD: 2505 if (!rockchip_pinconf_pull_valid(info->ctrl, param)) 2506 return -ENOTSUPP; 2507 2508 if (rockchip_get_pull(bank, pin - bank->pin_base) != param) 2509 return -EINVAL; 2510 2511 arg = 1; 2512 break; 2513 case PIN_CONFIG_OUTPUT: 2514 rc = rockchip_get_mux(bank, pin - bank->pin_base); 2515 if (rc != RK_FUNC_GPIO) 2516 return -EINVAL; 2517 2518 rc = rockchip_gpio_get(&bank->gpio_chip, pin - bank->pin_base); 2519 if (rc < 0) 2520 return rc; 2521 2522 arg = rc ? 1 : 0; 2523 break; 2524 case PIN_CONFIG_DRIVE_STRENGTH: 2525 /* rk3288 is the first with per-pin drive-strength */ 2526 if (!info->ctrl->drv_calc_reg) 2527 return -ENOTSUPP; 2528 2529 rc = rockchip_get_drive_perpin(bank, pin - bank->pin_base); 2530 if (rc < 0) 2531 return rc; 2532 2533 arg = rc; 2534 break; 2535 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 2536 if (!info->ctrl->schmitt_calc_reg) 2537 return -ENOTSUPP; 2538 2539 rc = rockchip_get_schmitt(bank, pin - bank->pin_base); 2540 if (rc < 0) 2541 return rc; 2542 2543 arg = rc; 2544 break; 2545 default: 2546 return -ENOTSUPP; 2547 break; 2548 } 2549 2550 *config = pinconf_to_config_packed(param, arg); 2551 2552 return 0; 2553 } 2554 2555 static const struct pinconf_ops rockchip_pinconf_ops = { 2556 .pin_config_get = rockchip_pinconf_get, 2557 .pin_config_set = rockchip_pinconf_set, 2558 .is_generic = true, 2559 }; 2560 2561 static const struct of_device_id rockchip_bank_match[] = { 2562 { .compatible = "rockchip,gpio-bank" }, 2563 { .compatible = "rockchip,rk3188-gpio-bank0" }, 2564 {}, 2565 }; 2566 2567 static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info, 2568 struct device_node *np) 2569 { 2570 struct device_node *child; 2571 2572 for_each_child_of_node(np, child) { 2573 if (of_match_node(rockchip_bank_match, child)) 2574 continue; 2575 2576 info->nfunctions++; 2577 info->ngroups += of_get_child_count(child); 2578 } 2579 } 2580 2581 static int rockchip_pinctrl_parse_groups(struct device_node *np, 2582 struct rockchip_pin_group *grp, 2583 struct rockchip_pinctrl *info, 2584 u32 index) 2585 { 2586 struct rockchip_pin_bank *bank; 2587 int size; 2588 const __be32 *list; 2589 int num; 2590 int i, j; 2591 int ret; 2592 2593 dev_dbg(info->dev, "group(%d): %pOFn\n", index, np); 2594 2595 /* Initialise group */ 2596 grp->name = np->name; 2597 2598 /* 2599 * the binding format is rockchip,pins = <bank pin mux CONFIG>, 2600 * do sanity check and calculate pins number 2601 */ 2602 list = of_get_property(np, "rockchip,pins", &size); 2603 /* we do not check return since it's safe node passed down */ 2604 size /= sizeof(*list); 2605 if (!size || size % 4) { 2606 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n"); 2607 return -EINVAL; 2608 } 2609 2610 grp->npins = size / 4; 2611 2612 grp->pins = devm_kcalloc(info->dev, grp->npins, sizeof(unsigned int), 2613 GFP_KERNEL); 2614 grp->data = devm_kcalloc(info->dev, 2615 grp->npins, 2616 sizeof(struct rockchip_pin_config), 2617 GFP_KERNEL); 2618 if (!grp->pins || !grp->data) 2619 return -ENOMEM; 2620 2621 for (i = 0, j = 0; i < size; i += 4, j++) { 2622 const __be32 *phandle; 2623 struct device_node *np_config; 2624 2625 num = be32_to_cpu(*list++); 2626 bank = bank_num_to_bank(info, num); 2627 if (IS_ERR(bank)) 2628 return PTR_ERR(bank); 2629 2630 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++); 2631 grp->data[j].func = be32_to_cpu(*list++); 2632 2633 phandle = list++; 2634 if (!phandle) 2635 return -EINVAL; 2636 2637 np_config = of_find_node_by_phandle(be32_to_cpup(phandle)); 2638 ret = pinconf_generic_parse_dt_config(np_config, NULL, 2639 &grp->data[j].configs, &grp->data[j].nconfigs); 2640 if (ret) 2641 return ret; 2642 } 2643 2644 return 0; 2645 } 2646 2647 static int rockchip_pinctrl_parse_functions(struct device_node *np, 2648 struct rockchip_pinctrl *info, 2649 u32 index) 2650 { 2651 struct device_node *child; 2652 struct rockchip_pmx_func *func; 2653 struct rockchip_pin_group *grp; 2654 int ret; 2655 static u32 grp_index; 2656 u32 i = 0; 2657 2658 dev_dbg(info->dev, "parse function(%d): %pOFn\n", index, np); 2659 2660 func = &info->functions[index]; 2661 2662 /* Initialise function */ 2663 func->name = np->name; 2664 func->ngroups = of_get_child_count(np); 2665 if (func->ngroups <= 0) 2666 return 0; 2667 2668 func->groups = devm_kcalloc(info->dev, 2669 func->ngroups, sizeof(char *), GFP_KERNEL); 2670 if (!func->groups) 2671 return -ENOMEM; 2672 2673 for_each_child_of_node(np, child) { 2674 func->groups[i] = child->name; 2675 grp = &info->groups[grp_index++]; 2676 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++); 2677 if (ret) { 2678 of_node_put(child); 2679 return ret; 2680 } 2681 } 2682 2683 return 0; 2684 } 2685 2686 static int rockchip_pinctrl_parse_dt(struct platform_device *pdev, 2687 struct rockchip_pinctrl *info) 2688 { 2689 struct device *dev = &pdev->dev; 2690 struct device_node *np = dev->of_node; 2691 struct device_node *child; 2692 int ret; 2693 int i; 2694 2695 rockchip_pinctrl_child_count(info, np); 2696 2697 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions); 2698 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups); 2699 2700 info->functions = devm_kcalloc(dev, 2701 info->nfunctions, 2702 sizeof(struct rockchip_pmx_func), 2703 GFP_KERNEL); 2704 if (!info->functions) 2705 return -ENOMEM; 2706 2707 info->groups = devm_kcalloc(dev, 2708 info->ngroups, 2709 sizeof(struct rockchip_pin_group), 2710 GFP_KERNEL); 2711 if (!info->groups) 2712 return -ENOMEM; 2713 2714 i = 0; 2715 2716 for_each_child_of_node(np, child) { 2717 if (of_match_node(rockchip_bank_match, child)) 2718 continue; 2719 2720 ret = rockchip_pinctrl_parse_functions(child, info, i++); 2721 if (ret) { 2722 dev_err(&pdev->dev, "failed to parse function\n"); 2723 of_node_put(child); 2724 return ret; 2725 } 2726 } 2727 2728 return 0; 2729 } 2730 2731 static int rockchip_pinctrl_register(struct platform_device *pdev, 2732 struct rockchip_pinctrl *info) 2733 { 2734 struct pinctrl_desc *ctrldesc = &info->pctl; 2735 struct pinctrl_pin_desc *pindesc, *pdesc; 2736 struct rockchip_pin_bank *pin_bank; 2737 int pin, bank, ret; 2738 int k; 2739 2740 ctrldesc->name = "rockchip-pinctrl"; 2741 ctrldesc->owner = THIS_MODULE; 2742 ctrldesc->pctlops = &rockchip_pctrl_ops; 2743 ctrldesc->pmxops = &rockchip_pmx_ops; 2744 ctrldesc->confops = &rockchip_pinconf_ops; 2745 2746 pindesc = devm_kcalloc(&pdev->dev, 2747 info->ctrl->nr_pins, sizeof(*pindesc), 2748 GFP_KERNEL); 2749 if (!pindesc) 2750 return -ENOMEM; 2751 2752 ctrldesc->pins = pindesc; 2753 ctrldesc->npins = info->ctrl->nr_pins; 2754 2755 pdesc = pindesc; 2756 for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) { 2757 pin_bank = &info->ctrl->pin_banks[bank]; 2758 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) { 2759 pdesc->number = k; 2760 pdesc->name = kasprintf(GFP_KERNEL, "%s-%d", 2761 pin_bank->name, pin); 2762 pdesc++; 2763 } 2764 } 2765 2766 ret = rockchip_pinctrl_parse_dt(pdev, info); 2767 if (ret) 2768 return ret; 2769 2770 info->pctl_dev = devm_pinctrl_register(&pdev->dev, ctrldesc, info); 2771 if (IS_ERR(info->pctl_dev)) { 2772 dev_err(&pdev->dev, "could not register pinctrl driver\n"); 2773 return PTR_ERR(info->pctl_dev); 2774 } 2775 2776 for (bank = 0; bank < info->ctrl->nr_banks; ++bank) { 2777 pin_bank = &info->ctrl->pin_banks[bank]; 2778 pin_bank->grange.name = pin_bank->name; 2779 pin_bank->grange.id = bank; 2780 pin_bank->grange.pin_base = pin_bank->pin_base; 2781 pin_bank->grange.base = pin_bank->gpio_chip.base; 2782 pin_bank->grange.npins = pin_bank->gpio_chip.ngpio; 2783 pin_bank->grange.gc = &pin_bank->gpio_chip; 2784 pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange); 2785 } 2786 2787 return 0; 2788 } 2789 2790 /* 2791 * GPIO handling 2792 */ 2793 2794 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value) 2795 { 2796 struct rockchip_pin_bank *bank = gpiochip_get_data(gc); 2797 void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR; 2798 unsigned long flags; 2799 u32 data; 2800 2801 clk_enable(bank->clk); 2802 raw_spin_lock_irqsave(&bank->slock, flags); 2803 2804 data = readl(reg); 2805 data &= ~BIT(offset); 2806 if (value) 2807 data |= BIT(offset); 2808 writel(data, reg); 2809 2810 raw_spin_unlock_irqrestore(&bank->slock, flags); 2811 clk_disable(bank->clk); 2812 } 2813 2814 /* 2815 * Returns the level of the pin for input direction and setting of the DR 2816 * register for output gpios. 2817 */ 2818 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset) 2819 { 2820 struct rockchip_pin_bank *bank = gpiochip_get_data(gc); 2821 u32 data; 2822 2823 clk_enable(bank->clk); 2824 data = readl(bank->reg_base + GPIO_EXT_PORT); 2825 clk_disable(bank->clk); 2826 data >>= offset; 2827 data &= 1; 2828 return data; 2829 } 2830 2831 /* 2832 * gpiolib gpio_direction_input callback function. The setting of the pin 2833 * mux function as 'gpio input' will be handled by the pinctrl subsystem 2834 * interface. 2835 */ 2836 static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset) 2837 { 2838 return pinctrl_gpio_direction_input(gc->base + offset); 2839 } 2840 2841 /* 2842 * gpiolib gpio_direction_output callback function. The setting of the pin 2843 * mux function as 'gpio output' will be handled by the pinctrl subsystem 2844 * interface. 2845 */ 2846 static int rockchip_gpio_direction_output(struct gpio_chip *gc, 2847 unsigned offset, int value) 2848 { 2849 rockchip_gpio_set(gc, offset, value); 2850 return pinctrl_gpio_direction_output(gc->base + offset); 2851 } 2852 2853 static void rockchip_gpio_set_debounce(struct gpio_chip *gc, 2854 unsigned int offset, bool enable) 2855 { 2856 struct rockchip_pin_bank *bank = gpiochip_get_data(gc); 2857 void __iomem *reg = bank->reg_base + GPIO_DEBOUNCE; 2858 unsigned long flags; 2859 u32 data; 2860 2861 clk_enable(bank->clk); 2862 raw_spin_lock_irqsave(&bank->slock, flags); 2863 2864 data = readl(reg); 2865 if (enable) 2866 data |= BIT(offset); 2867 else 2868 data &= ~BIT(offset); 2869 writel(data, reg); 2870 2871 raw_spin_unlock_irqrestore(&bank->slock, flags); 2872 clk_disable(bank->clk); 2873 } 2874 2875 /* 2876 * gpiolib set_config callback function. The setting of the pin 2877 * mux function as 'gpio output' will be handled by the pinctrl subsystem 2878 * interface. 2879 */ 2880 static int rockchip_gpio_set_config(struct gpio_chip *gc, unsigned int offset, 2881 unsigned long config) 2882 { 2883 enum pin_config_param param = pinconf_to_config_param(config); 2884 2885 switch (param) { 2886 case PIN_CONFIG_INPUT_DEBOUNCE: 2887 rockchip_gpio_set_debounce(gc, offset, true); 2888 /* 2889 * Rockchip's gpio could only support up to one period 2890 * of the debounce clock(pclk), which is far away from 2891 * satisftying the requirement, as pclk is usually near 2892 * 100MHz shared by all peripherals. So the fact is it 2893 * has crippled debounce capability could only be useful 2894 * to prevent any spurious glitches from waking up the system 2895 * if the gpio is conguired as wakeup interrupt source. Let's 2896 * still return -ENOTSUPP as before, to make sure the caller 2897 * of gpiod_set_debounce won't change its behaviour. 2898 */ 2899 return -ENOTSUPP; 2900 default: 2901 return -ENOTSUPP; 2902 } 2903 } 2904 2905 /* 2906 * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin 2907 * and a virtual IRQ, if not already present. 2908 */ 2909 static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset) 2910 { 2911 struct rockchip_pin_bank *bank = gpiochip_get_data(gc); 2912 unsigned int virq; 2913 2914 if (!bank->domain) 2915 return -ENXIO; 2916 2917 clk_enable(bank->clk); 2918 virq = irq_create_mapping(bank->domain, offset); 2919 clk_disable(bank->clk); 2920 2921 return (virq) ? : -ENXIO; 2922 } 2923 2924 static const struct gpio_chip rockchip_gpiolib_chip = { 2925 .request = gpiochip_generic_request, 2926 .free = gpiochip_generic_free, 2927 .set = rockchip_gpio_set, 2928 .get = rockchip_gpio_get, 2929 .get_direction = rockchip_gpio_get_direction, 2930 .direction_input = rockchip_gpio_direction_input, 2931 .direction_output = rockchip_gpio_direction_output, 2932 .set_config = rockchip_gpio_set_config, 2933 .to_irq = rockchip_gpio_to_irq, 2934 .owner = THIS_MODULE, 2935 }; 2936 2937 /* 2938 * Interrupt handling 2939 */ 2940 2941 static void rockchip_irq_demux(struct irq_desc *desc) 2942 { 2943 struct irq_chip *chip = irq_desc_get_chip(desc); 2944 struct rockchip_pin_bank *bank = irq_desc_get_handler_data(desc); 2945 u32 pend; 2946 2947 dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name); 2948 2949 chained_irq_enter(chip, desc); 2950 2951 pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS); 2952 2953 while (pend) { 2954 unsigned int irq; 2955 int ret; 2956 2957 irq = __ffs(pend); 2958 pend &= ~BIT(irq); 2959 2960 /* 2961 * Triggering IRQ on both rising and falling edge 2962 * needs manual intervention. 2963 */ 2964 if (bank->toggle_edge_mode & BIT(irq)) { 2965 u32 data, data_old, polarity; 2966 unsigned long flags; 2967 2968 data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT); 2969 do { 2970 raw_spin_lock_irqsave(&bank->slock, flags); 2971 2972 polarity = readl_relaxed(bank->reg_base + 2973 GPIO_INT_POLARITY); 2974 if (data & BIT(irq)) 2975 polarity &= ~BIT(irq); 2976 else 2977 polarity |= BIT(irq); 2978 writel(polarity, 2979 bank->reg_base + GPIO_INT_POLARITY); 2980 2981 raw_spin_unlock_irqrestore(&bank->slock, flags); 2982 2983 data_old = data; 2984 data = readl_relaxed(bank->reg_base + 2985 GPIO_EXT_PORT); 2986 } while ((data & BIT(irq)) != (data_old & BIT(irq))); 2987 } 2988 2989 ret = generic_handle_domain_irq(bank->domain, irq); 2990 if (unlikely(ret)) 2991 dev_err_ratelimited(bank->drvdata->dev, "unmapped irq %d\n", irq); 2992 } 2993 2994 chained_irq_exit(chip, desc); 2995 } 2996 2997 static int rockchip_irq_set_type(struct irq_data *d, unsigned int type) 2998 { 2999 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 3000 struct rockchip_pin_bank *bank = gc->private; 3001 u32 mask = BIT(d->hwirq); 3002 u32 polarity; 3003 u32 level; 3004 u32 data; 3005 unsigned long flags; 3006 int ret; 3007 3008 /* make sure the pin is configured as gpio input */ 3009 ret = rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO); 3010 if (ret < 0) 3011 return ret; 3012 3013 clk_enable(bank->clk); 3014 raw_spin_lock_irqsave(&bank->slock, flags); 3015 3016 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); 3017 data &= ~mask; 3018 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR); 3019 3020 raw_spin_unlock_irqrestore(&bank->slock, flags); 3021 3022 if (type & IRQ_TYPE_EDGE_BOTH) 3023 irq_set_handler_locked(d, handle_edge_irq); 3024 else 3025 irq_set_handler_locked(d, handle_level_irq); 3026 3027 raw_spin_lock_irqsave(&bank->slock, flags); 3028 irq_gc_lock(gc); 3029 3030 level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL); 3031 polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY); 3032 3033 switch (type) { 3034 case IRQ_TYPE_EDGE_BOTH: 3035 bank->toggle_edge_mode |= mask; 3036 level |= mask; 3037 3038 /* 3039 * Determine gpio state. If 1 next interrupt should be falling 3040 * otherwise rising. 3041 */ 3042 data = readl(bank->reg_base + GPIO_EXT_PORT); 3043 if (data & mask) 3044 polarity &= ~mask; 3045 else 3046 polarity |= mask; 3047 break; 3048 case IRQ_TYPE_EDGE_RISING: 3049 bank->toggle_edge_mode &= ~mask; 3050 level |= mask; 3051 polarity |= mask; 3052 break; 3053 case IRQ_TYPE_EDGE_FALLING: 3054 bank->toggle_edge_mode &= ~mask; 3055 level |= mask; 3056 polarity &= ~mask; 3057 break; 3058 case IRQ_TYPE_LEVEL_HIGH: 3059 bank->toggle_edge_mode &= ~mask; 3060 level &= ~mask; 3061 polarity |= mask; 3062 break; 3063 case IRQ_TYPE_LEVEL_LOW: 3064 bank->toggle_edge_mode &= ~mask; 3065 level &= ~mask; 3066 polarity &= ~mask; 3067 break; 3068 default: 3069 irq_gc_unlock(gc); 3070 raw_spin_unlock_irqrestore(&bank->slock, flags); 3071 clk_disable(bank->clk); 3072 return -EINVAL; 3073 } 3074 3075 writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL); 3076 writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY); 3077 3078 irq_gc_unlock(gc); 3079 raw_spin_unlock_irqrestore(&bank->slock, flags); 3080 clk_disable(bank->clk); 3081 3082 return 0; 3083 } 3084 3085 static void rockchip_irq_suspend(struct irq_data *d) 3086 { 3087 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 3088 struct rockchip_pin_bank *bank = gc->private; 3089 3090 clk_enable(bank->clk); 3091 bank->saved_masks = irq_reg_readl(gc, GPIO_INTMASK); 3092 irq_reg_writel(gc, ~gc->wake_active, GPIO_INTMASK); 3093 clk_disable(bank->clk); 3094 } 3095 3096 static void rockchip_irq_resume(struct irq_data *d) 3097 { 3098 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 3099 struct rockchip_pin_bank *bank = gc->private; 3100 3101 clk_enable(bank->clk); 3102 irq_reg_writel(gc, bank->saved_masks, GPIO_INTMASK); 3103 clk_disable(bank->clk); 3104 } 3105 3106 static void rockchip_irq_enable(struct irq_data *d) 3107 { 3108 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 3109 struct rockchip_pin_bank *bank = gc->private; 3110 3111 clk_enable(bank->clk); 3112 irq_gc_mask_clr_bit(d); 3113 } 3114 3115 static void rockchip_irq_disable(struct irq_data *d) 3116 { 3117 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 3118 struct rockchip_pin_bank *bank = gc->private; 3119 3120 irq_gc_mask_set_bit(d); 3121 clk_disable(bank->clk); 3122 } 3123 3124 static int rockchip_interrupts_register(struct platform_device *pdev, 3125 struct rockchip_pinctrl *info) 3126 { 3127 struct rockchip_pin_ctrl *ctrl = info->ctrl; 3128 struct rockchip_pin_bank *bank = ctrl->pin_banks; 3129 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; 3130 struct irq_chip_generic *gc; 3131 int ret; 3132 int i; 3133 3134 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 3135 if (!bank->valid) { 3136 dev_warn(&pdev->dev, "bank %s is not valid\n", 3137 bank->name); 3138 continue; 3139 } 3140 3141 ret = clk_enable(bank->clk); 3142 if (ret) { 3143 dev_err(&pdev->dev, "failed to enable clock for bank %s\n", 3144 bank->name); 3145 continue; 3146 } 3147 3148 bank->domain = irq_domain_add_linear(bank->of_node, 32, 3149 &irq_generic_chip_ops, NULL); 3150 if (!bank->domain) { 3151 dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n", 3152 bank->name); 3153 clk_disable(bank->clk); 3154 continue; 3155 } 3156 3157 ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1, 3158 "rockchip_gpio_irq", handle_level_irq, 3159 clr, 0, 0); 3160 if (ret) { 3161 dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n", 3162 bank->name); 3163 irq_domain_remove(bank->domain); 3164 clk_disable(bank->clk); 3165 continue; 3166 } 3167 3168 gc = irq_get_domain_generic_chip(bank->domain, 0); 3169 gc->reg_base = bank->reg_base; 3170 gc->private = bank; 3171 gc->chip_types[0].regs.mask = GPIO_INTMASK; 3172 gc->chip_types[0].regs.ack = GPIO_PORTS_EOI; 3173 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit; 3174 gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit; 3175 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit; 3176 gc->chip_types[0].chip.irq_enable = rockchip_irq_enable; 3177 gc->chip_types[0].chip.irq_disable = rockchip_irq_disable; 3178 gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake; 3179 gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend; 3180 gc->chip_types[0].chip.irq_resume = rockchip_irq_resume; 3181 gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type; 3182 gc->wake_enabled = IRQ_MSK(bank->nr_pins); 3183 3184 /* 3185 * Linux assumes that all interrupts start out disabled/masked. 3186 * Our driver only uses the concept of masked and always keeps 3187 * things enabled, so for us that's all masked and all enabled. 3188 */ 3189 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTMASK); 3190 writel_relaxed(0xffffffff, bank->reg_base + GPIO_PORTS_EOI); 3191 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTEN); 3192 gc->mask_cache = 0xffffffff; 3193 3194 irq_set_chained_handler_and_data(bank->irq, 3195 rockchip_irq_demux, bank); 3196 clk_disable(bank->clk); 3197 } 3198 3199 return 0; 3200 } 3201 3202 static int rockchip_gpiolib_register(struct platform_device *pdev, 3203 struct rockchip_pinctrl *info) 3204 { 3205 struct rockchip_pin_ctrl *ctrl = info->ctrl; 3206 struct rockchip_pin_bank *bank = ctrl->pin_banks; 3207 struct gpio_chip *gc; 3208 int ret; 3209 int i; 3210 3211 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 3212 if (!bank->valid) { 3213 dev_warn(&pdev->dev, "bank %s is not valid\n", 3214 bank->name); 3215 continue; 3216 } 3217 3218 bank->gpio_chip = rockchip_gpiolib_chip; 3219 3220 gc = &bank->gpio_chip; 3221 gc->base = bank->pin_base; 3222 gc->ngpio = bank->nr_pins; 3223 gc->parent = &pdev->dev; 3224 gc->of_node = bank->of_node; 3225 gc->label = bank->name; 3226 3227 ret = gpiochip_add_data(gc, bank); 3228 if (ret) { 3229 dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n", 3230 gc->label, ret); 3231 goto fail; 3232 } 3233 } 3234 3235 rockchip_interrupts_register(pdev, info); 3236 3237 return 0; 3238 3239 fail: 3240 for (--i, --bank; i >= 0; --i, --bank) { 3241 if (!bank->valid) 3242 continue; 3243 gpiochip_remove(&bank->gpio_chip); 3244 } 3245 return ret; 3246 } 3247 3248 static int rockchip_gpiolib_unregister(struct platform_device *pdev, 3249 struct rockchip_pinctrl *info) 3250 { 3251 struct rockchip_pin_ctrl *ctrl = info->ctrl; 3252 struct rockchip_pin_bank *bank = ctrl->pin_banks; 3253 int i; 3254 3255 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 3256 if (!bank->valid) 3257 continue; 3258 gpiochip_remove(&bank->gpio_chip); 3259 } 3260 3261 return 0; 3262 } 3263 3264 static int rockchip_get_bank_data(struct rockchip_pin_bank *bank, 3265 struct rockchip_pinctrl *info) 3266 { 3267 struct resource res; 3268 void __iomem *base; 3269 3270 if (of_address_to_resource(bank->of_node, 0, &res)) { 3271 dev_err(info->dev, "cannot find IO resource for bank\n"); 3272 return -ENOENT; 3273 } 3274 3275 bank->reg_base = devm_ioremap_resource(info->dev, &res); 3276 if (IS_ERR(bank->reg_base)) 3277 return PTR_ERR(bank->reg_base); 3278 3279 /* 3280 * special case, where parts of the pull setting-registers are 3281 * part of the PMU register space 3282 */ 3283 if (of_device_is_compatible(bank->of_node, 3284 "rockchip,rk3188-gpio-bank0")) { 3285 struct device_node *node; 3286 3287 node = of_parse_phandle(bank->of_node->parent, 3288 "rockchip,pmu", 0); 3289 if (!node) { 3290 if (of_address_to_resource(bank->of_node, 1, &res)) { 3291 dev_err(info->dev, "cannot find IO resource for bank\n"); 3292 return -ENOENT; 3293 } 3294 3295 base = devm_ioremap_resource(info->dev, &res); 3296 if (IS_ERR(base)) 3297 return PTR_ERR(base); 3298 rockchip_regmap_config.max_register = 3299 resource_size(&res) - 4; 3300 rockchip_regmap_config.name = 3301 "rockchip,rk3188-gpio-bank0-pull"; 3302 bank->regmap_pull = devm_regmap_init_mmio(info->dev, 3303 base, 3304 &rockchip_regmap_config); 3305 } 3306 of_node_put(node); 3307 } 3308 3309 bank->irq = irq_of_parse_and_map(bank->of_node, 0); 3310 3311 bank->clk = of_clk_get(bank->of_node, 0); 3312 if (IS_ERR(bank->clk)) 3313 return PTR_ERR(bank->clk); 3314 3315 return clk_prepare(bank->clk); 3316 } 3317 3318 static const struct of_device_id rockchip_pinctrl_dt_match[]; 3319 3320 /* retrieve the soc specific data */ 3321 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data( 3322 struct rockchip_pinctrl *d, 3323 struct platform_device *pdev) 3324 { 3325 const struct of_device_id *match; 3326 struct device_node *node = pdev->dev.of_node; 3327 struct device_node *np; 3328 struct rockchip_pin_ctrl *ctrl; 3329 struct rockchip_pin_bank *bank; 3330 int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j; 3331 3332 match = of_match_node(rockchip_pinctrl_dt_match, node); 3333 ctrl = (struct rockchip_pin_ctrl *)match->data; 3334 3335 for_each_child_of_node(node, np) { 3336 if (!of_find_property(np, "gpio-controller", NULL)) 3337 continue; 3338 3339 bank = ctrl->pin_banks; 3340 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 3341 if (!strcmp(bank->name, np->name)) { 3342 bank->of_node = np; 3343 3344 if (!rockchip_get_bank_data(bank, d)) 3345 bank->valid = true; 3346 3347 break; 3348 } 3349 } 3350 } 3351 3352 grf_offs = ctrl->grf_mux_offset; 3353 pmu_offs = ctrl->pmu_mux_offset; 3354 drv_pmu_offs = ctrl->pmu_drv_offset; 3355 drv_grf_offs = ctrl->grf_drv_offset; 3356 bank = ctrl->pin_banks; 3357 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 3358 int bank_pins = 0; 3359 3360 raw_spin_lock_init(&bank->slock); 3361 bank->drvdata = d; 3362 bank->pin_base = ctrl->nr_pins; 3363 ctrl->nr_pins += bank->nr_pins; 3364 3365 /* calculate iomux and drv offsets */ 3366 for (j = 0; j < 4; j++) { 3367 struct rockchip_iomux *iom = &bank->iomux[j]; 3368 struct rockchip_drv *drv = &bank->drv[j]; 3369 int inc; 3370 3371 if (bank_pins >= bank->nr_pins) 3372 break; 3373 3374 /* preset iomux offset value, set new start value */ 3375 if (iom->offset >= 0) { 3376 if (iom->type & IOMUX_SOURCE_PMU) 3377 pmu_offs = iom->offset; 3378 else 3379 grf_offs = iom->offset; 3380 } else { /* set current iomux offset */ 3381 iom->offset = (iom->type & IOMUX_SOURCE_PMU) ? 3382 pmu_offs : grf_offs; 3383 } 3384 3385 /* preset drv offset value, set new start value */ 3386 if (drv->offset >= 0) { 3387 if (iom->type & IOMUX_SOURCE_PMU) 3388 drv_pmu_offs = drv->offset; 3389 else 3390 drv_grf_offs = drv->offset; 3391 } else { /* set current drv offset */ 3392 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ? 3393 drv_pmu_offs : drv_grf_offs; 3394 } 3395 3396 dev_dbg(d->dev, "bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n", 3397 i, j, iom->offset, drv->offset); 3398 3399 /* 3400 * Increase offset according to iomux width. 3401 * 4bit iomux'es are spread over two registers. 3402 */ 3403 inc = (iom->type & (IOMUX_WIDTH_4BIT | 3404 IOMUX_WIDTH_3BIT | 3405 IOMUX_WIDTH_2BIT)) ? 8 : 4; 3406 if (iom->type & IOMUX_SOURCE_PMU) 3407 pmu_offs += inc; 3408 else 3409 grf_offs += inc; 3410 3411 /* 3412 * Increase offset according to drv width. 3413 * 3bit drive-strenth'es are spread over two registers. 3414 */ 3415 if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) || 3416 (drv->drv_type == DRV_TYPE_IO_3V3_ONLY)) 3417 inc = 8; 3418 else 3419 inc = 4; 3420 3421 if (iom->type & IOMUX_SOURCE_PMU) 3422 drv_pmu_offs += inc; 3423 else 3424 drv_grf_offs += inc; 3425 3426 bank_pins += 8; 3427 } 3428 3429 /* calculate the per-bank recalced_mask */ 3430 for (j = 0; j < ctrl->niomux_recalced; j++) { 3431 int pin = 0; 3432 3433 if (ctrl->iomux_recalced[j].num == bank->bank_num) { 3434 pin = ctrl->iomux_recalced[j].pin; 3435 bank->recalced_mask |= BIT(pin); 3436 } 3437 } 3438 3439 /* calculate the per-bank route_mask */ 3440 for (j = 0; j < ctrl->niomux_routes; j++) { 3441 int pin = 0; 3442 3443 if (ctrl->iomux_routes[j].bank_num == bank->bank_num) { 3444 pin = ctrl->iomux_routes[j].pin; 3445 bank->route_mask |= BIT(pin); 3446 } 3447 } 3448 } 3449 3450 return ctrl; 3451 } 3452 3453 #define RK3288_GRF_GPIO6C_IOMUX 0x64 3454 #define GPIO6C6_SEL_WRITE_ENABLE BIT(28) 3455 3456 static u32 rk3288_grf_gpio6c_iomux; 3457 3458 static int __maybe_unused rockchip_pinctrl_suspend(struct device *dev) 3459 { 3460 struct rockchip_pinctrl *info = dev_get_drvdata(dev); 3461 int ret = pinctrl_force_sleep(info->pctl_dev); 3462 3463 if (ret) 3464 return ret; 3465 3466 /* 3467 * RK3288 GPIO6_C6 mux would be modified by Maskrom when resume, so save 3468 * the setting here, and restore it at resume. 3469 */ 3470 if (info->ctrl->type == RK3288) { 3471 ret = regmap_read(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX, 3472 &rk3288_grf_gpio6c_iomux); 3473 if (ret) { 3474 pinctrl_force_default(info->pctl_dev); 3475 return ret; 3476 } 3477 } 3478 3479 return 0; 3480 } 3481 3482 static int __maybe_unused rockchip_pinctrl_resume(struct device *dev) 3483 { 3484 struct rockchip_pinctrl *info = dev_get_drvdata(dev); 3485 int ret; 3486 3487 if (info->ctrl->type == RK3288) { 3488 ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX, 3489 rk3288_grf_gpio6c_iomux | 3490 GPIO6C6_SEL_WRITE_ENABLE); 3491 if (ret) 3492 return ret; 3493 } 3494 3495 return pinctrl_force_default(info->pctl_dev); 3496 } 3497 3498 static SIMPLE_DEV_PM_OPS(rockchip_pinctrl_dev_pm_ops, rockchip_pinctrl_suspend, 3499 rockchip_pinctrl_resume); 3500 3501 static int rockchip_pinctrl_probe(struct platform_device *pdev) 3502 { 3503 struct rockchip_pinctrl *info; 3504 struct device *dev = &pdev->dev; 3505 struct rockchip_pin_ctrl *ctrl; 3506 struct device_node *np = pdev->dev.of_node, *node; 3507 struct resource *res; 3508 void __iomem *base; 3509 int ret; 3510 3511 if (!dev->of_node) { 3512 dev_err(dev, "device tree node not found\n"); 3513 return -ENODEV; 3514 } 3515 3516 info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL); 3517 if (!info) 3518 return -ENOMEM; 3519 3520 info->dev = dev; 3521 3522 ctrl = rockchip_pinctrl_get_soc_data(info, pdev); 3523 if (!ctrl) { 3524 dev_err(dev, "driver data not available\n"); 3525 return -EINVAL; 3526 } 3527 info->ctrl = ctrl; 3528 3529 node = of_parse_phandle(np, "rockchip,grf", 0); 3530 if (node) { 3531 info->regmap_base = syscon_node_to_regmap(node); 3532 if (IS_ERR(info->regmap_base)) 3533 return PTR_ERR(info->regmap_base); 3534 } else { 3535 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 3536 base = devm_ioremap_resource(&pdev->dev, res); 3537 if (IS_ERR(base)) 3538 return PTR_ERR(base); 3539 3540 rockchip_regmap_config.max_register = resource_size(res) - 4; 3541 rockchip_regmap_config.name = "rockchip,pinctrl"; 3542 info->regmap_base = devm_regmap_init_mmio(&pdev->dev, base, 3543 &rockchip_regmap_config); 3544 3545 /* to check for the old dt-bindings */ 3546 info->reg_size = resource_size(res); 3547 3548 /* Honor the old binding, with pull registers as 2nd resource */ 3549 if (ctrl->type == RK3188 && info->reg_size < 0x200) { 3550 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 3551 base = devm_ioremap_resource(&pdev->dev, res); 3552 if (IS_ERR(base)) 3553 return PTR_ERR(base); 3554 3555 rockchip_regmap_config.max_register = 3556 resource_size(res) - 4; 3557 rockchip_regmap_config.name = "rockchip,pinctrl-pull"; 3558 info->regmap_pull = devm_regmap_init_mmio(&pdev->dev, 3559 base, 3560 &rockchip_regmap_config); 3561 } 3562 } 3563 3564 /* try to find the optional reference to the pmu syscon */ 3565 node = of_parse_phandle(np, "rockchip,pmu", 0); 3566 if (node) { 3567 info->regmap_pmu = syscon_node_to_regmap(node); 3568 if (IS_ERR(info->regmap_pmu)) 3569 return PTR_ERR(info->regmap_pmu); 3570 } 3571 3572 ret = rockchip_gpiolib_register(pdev, info); 3573 if (ret) 3574 return ret; 3575 3576 ret = rockchip_pinctrl_register(pdev, info); 3577 if (ret) { 3578 rockchip_gpiolib_unregister(pdev, info); 3579 return ret; 3580 } 3581 3582 platform_set_drvdata(pdev, info); 3583 3584 return 0; 3585 } 3586 3587 static struct rockchip_pin_bank px30_pin_banks[] = { 3588 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, 3589 IOMUX_SOURCE_PMU, 3590 IOMUX_SOURCE_PMU, 3591 IOMUX_SOURCE_PMU 3592 ), 3593 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT, 3594 IOMUX_WIDTH_4BIT, 3595 IOMUX_WIDTH_4BIT, 3596 IOMUX_WIDTH_4BIT 3597 ), 3598 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT, 3599 IOMUX_WIDTH_4BIT, 3600 IOMUX_WIDTH_4BIT, 3601 IOMUX_WIDTH_4BIT 3602 ), 3603 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT, 3604 IOMUX_WIDTH_4BIT, 3605 IOMUX_WIDTH_4BIT, 3606 IOMUX_WIDTH_4BIT 3607 ), 3608 }; 3609 3610 static struct rockchip_pin_ctrl px30_pin_ctrl = { 3611 .pin_banks = px30_pin_banks, 3612 .nr_banks = ARRAY_SIZE(px30_pin_banks), 3613 .label = "PX30-GPIO", 3614 .type = PX30, 3615 .grf_mux_offset = 0x0, 3616 .pmu_mux_offset = 0x0, 3617 .iomux_routes = px30_mux_route_data, 3618 .niomux_routes = ARRAY_SIZE(px30_mux_route_data), 3619 .pull_calc_reg = px30_calc_pull_reg_and_bit, 3620 .drv_calc_reg = px30_calc_drv_reg_and_bit, 3621 .schmitt_calc_reg = px30_calc_schmitt_reg_and_bit, 3622 }; 3623 3624 static struct rockchip_pin_bank rv1108_pin_banks[] = { 3625 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, 3626 IOMUX_SOURCE_PMU, 3627 IOMUX_SOURCE_PMU, 3628 IOMUX_SOURCE_PMU), 3629 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0), 3630 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0), 3631 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0), 3632 }; 3633 3634 static struct rockchip_pin_ctrl rv1108_pin_ctrl = { 3635 .pin_banks = rv1108_pin_banks, 3636 .nr_banks = ARRAY_SIZE(rv1108_pin_banks), 3637 .label = "RV1108-GPIO", 3638 .type = RV1108, 3639 .grf_mux_offset = 0x10, 3640 .pmu_mux_offset = 0x0, 3641 .iomux_recalced = rv1108_mux_recalced_data, 3642 .niomux_recalced = ARRAY_SIZE(rv1108_mux_recalced_data), 3643 .pull_calc_reg = rv1108_calc_pull_reg_and_bit, 3644 .drv_calc_reg = rv1108_calc_drv_reg_and_bit, 3645 .schmitt_calc_reg = rv1108_calc_schmitt_reg_and_bit, 3646 }; 3647 3648 static struct rockchip_pin_bank rk2928_pin_banks[] = { 3649 PIN_BANK(0, 32, "gpio0"), 3650 PIN_BANK(1, 32, "gpio1"), 3651 PIN_BANK(2, 32, "gpio2"), 3652 PIN_BANK(3, 32, "gpio3"), 3653 }; 3654 3655 static struct rockchip_pin_ctrl rk2928_pin_ctrl = { 3656 .pin_banks = rk2928_pin_banks, 3657 .nr_banks = ARRAY_SIZE(rk2928_pin_banks), 3658 .label = "RK2928-GPIO", 3659 .type = RK2928, 3660 .grf_mux_offset = 0xa8, 3661 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 3662 }; 3663 3664 static struct rockchip_pin_bank rk3036_pin_banks[] = { 3665 PIN_BANK(0, 32, "gpio0"), 3666 PIN_BANK(1, 32, "gpio1"), 3667 PIN_BANK(2, 32, "gpio2"), 3668 }; 3669 3670 static struct rockchip_pin_ctrl rk3036_pin_ctrl = { 3671 .pin_banks = rk3036_pin_banks, 3672 .nr_banks = ARRAY_SIZE(rk3036_pin_banks), 3673 .label = "RK3036-GPIO", 3674 .type = RK2928, 3675 .grf_mux_offset = 0xa8, 3676 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 3677 }; 3678 3679 static struct rockchip_pin_bank rk3066a_pin_banks[] = { 3680 PIN_BANK(0, 32, "gpio0"), 3681 PIN_BANK(1, 32, "gpio1"), 3682 PIN_BANK(2, 32, "gpio2"), 3683 PIN_BANK(3, 32, "gpio3"), 3684 PIN_BANK(4, 32, "gpio4"), 3685 PIN_BANK(6, 16, "gpio6"), 3686 }; 3687 3688 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = { 3689 .pin_banks = rk3066a_pin_banks, 3690 .nr_banks = ARRAY_SIZE(rk3066a_pin_banks), 3691 .label = "RK3066a-GPIO", 3692 .type = RK2928, 3693 .grf_mux_offset = 0xa8, 3694 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 3695 }; 3696 3697 static struct rockchip_pin_bank rk3066b_pin_banks[] = { 3698 PIN_BANK(0, 32, "gpio0"), 3699 PIN_BANK(1, 32, "gpio1"), 3700 PIN_BANK(2, 32, "gpio2"), 3701 PIN_BANK(3, 32, "gpio3"), 3702 }; 3703 3704 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = { 3705 .pin_banks = rk3066b_pin_banks, 3706 .nr_banks = ARRAY_SIZE(rk3066b_pin_banks), 3707 .label = "RK3066b-GPIO", 3708 .type = RK3066B, 3709 .grf_mux_offset = 0x60, 3710 }; 3711 3712 static struct rockchip_pin_bank rk3128_pin_banks[] = { 3713 PIN_BANK(0, 32, "gpio0"), 3714 PIN_BANK(1, 32, "gpio1"), 3715 PIN_BANK(2, 32, "gpio2"), 3716 PIN_BANK(3, 32, "gpio3"), 3717 }; 3718 3719 static struct rockchip_pin_ctrl rk3128_pin_ctrl = { 3720 .pin_banks = rk3128_pin_banks, 3721 .nr_banks = ARRAY_SIZE(rk3128_pin_banks), 3722 .label = "RK3128-GPIO", 3723 .type = RK3128, 3724 .grf_mux_offset = 0xa8, 3725 .iomux_recalced = rk3128_mux_recalced_data, 3726 .niomux_recalced = ARRAY_SIZE(rk3128_mux_recalced_data), 3727 .iomux_routes = rk3128_mux_route_data, 3728 .niomux_routes = ARRAY_SIZE(rk3128_mux_route_data), 3729 .pull_calc_reg = rk3128_calc_pull_reg_and_bit, 3730 }; 3731 3732 static struct rockchip_pin_bank rk3188_pin_banks[] = { 3733 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0), 3734 PIN_BANK(1, 32, "gpio1"), 3735 PIN_BANK(2, 32, "gpio2"), 3736 PIN_BANK(3, 32, "gpio3"), 3737 }; 3738 3739 static struct rockchip_pin_ctrl rk3188_pin_ctrl = { 3740 .pin_banks = rk3188_pin_banks, 3741 .nr_banks = ARRAY_SIZE(rk3188_pin_banks), 3742 .label = "RK3188-GPIO", 3743 .type = RK3188, 3744 .grf_mux_offset = 0x60, 3745 .iomux_routes = rk3188_mux_route_data, 3746 .niomux_routes = ARRAY_SIZE(rk3188_mux_route_data), 3747 .pull_calc_reg = rk3188_calc_pull_reg_and_bit, 3748 }; 3749 3750 static struct rockchip_pin_bank rk3228_pin_banks[] = { 3751 PIN_BANK(0, 32, "gpio0"), 3752 PIN_BANK(1, 32, "gpio1"), 3753 PIN_BANK(2, 32, "gpio2"), 3754 PIN_BANK(3, 32, "gpio3"), 3755 }; 3756 3757 static struct rockchip_pin_ctrl rk3228_pin_ctrl = { 3758 .pin_banks = rk3228_pin_banks, 3759 .nr_banks = ARRAY_SIZE(rk3228_pin_banks), 3760 .label = "RK3228-GPIO", 3761 .type = RK3288, 3762 .grf_mux_offset = 0x0, 3763 .iomux_routes = rk3228_mux_route_data, 3764 .niomux_routes = ARRAY_SIZE(rk3228_mux_route_data), 3765 .pull_calc_reg = rk3228_calc_pull_reg_and_bit, 3766 .drv_calc_reg = rk3228_calc_drv_reg_and_bit, 3767 }; 3768 3769 static struct rockchip_pin_bank rk3288_pin_banks[] = { 3770 PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU, 3771 IOMUX_SOURCE_PMU, 3772 IOMUX_SOURCE_PMU, 3773 IOMUX_UNROUTED 3774 ), 3775 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED, 3776 IOMUX_UNROUTED, 3777 IOMUX_UNROUTED, 3778 0 3779 ), 3780 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED), 3781 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT), 3782 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT, 3783 IOMUX_WIDTH_4BIT, 3784 0, 3785 0 3786 ), 3787 PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED, 3788 0, 3789 0, 3790 IOMUX_UNROUTED 3791 ), 3792 PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED), 3793 PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0, 3794 0, 3795 IOMUX_WIDTH_4BIT, 3796 IOMUX_UNROUTED 3797 ), 3798 PIN_BANK(8, 16, "gpio8"), 3799 }; 3800 3801 static struct rockchip_pin_ctrl rk3288_pin_ctrl = { 3802 .pin_banks = rk3288_pin_banks, 3803 .nr_banks = ARRAY_SIZE(rk3288_pin_banks), 3804 .label = "RK3288-GPIO", 3805 .type = RK3288, 3806 .grf_mux_offset = 0x0, 3807 .pmu_mux_offset = 0x84, 3808 .iomux_routes = rk3288_mux_route_data, 3809 .niomux_routes = ARRAY_SIZE(rk3288_mux_route_data), 3810 .pull_calc_reg = rk3288_calc_pull_reg_and_bit, 3811 .drv_calc_reg = rk3288_calc_drv_reg_and_bit, 3812 }; 3813 3814 static struct rockchip_pin_bank rk3308_pin_banks[] = { 3815 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_WIDTH_2BIT, 3816 IOMUX_WIDTH_2BIT, 3817 IOMUX_WIDTH_2BIT, 3818 IOMUX_WIDTH_2BIT), 3819 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_2BIT, 3820 IOMUX_WIDTH_2BIT, 3821 IOMUX_WIDTH_2BIT, 3822 IOMUX_WIDTH_2BIT), 3823 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_2BIT, 3824 IOMUX_WIDTH_2BIT, 3825 IOMUX_WIDTH_2BIT, 3826 IOMUX_WIDTH_2BIT), 3827 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_2BIT, 3828 IOMUX_WIDTH_2BIT, 3829 IOMUX_WIDTH_2BIT, 3830 IOMUX_WIDTH_2BIT), 3831 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_2BIT, 3832 IOMUX_WIDTH_2BIT, 3833 IOMUX_WIDTH_2BIT, 3834 IOMUX_WIDTH_2BIT), 3835 }; 3836 3837 static struct rockchip_pin_ctrl rk3308_pin_ctrl = { 3838 .pin_banks = rk3308_pin_banks, 3839 .nr_banks = ARRAY_SIZE(rk3308_pin_banks), 3840 .label = "RK3308-GPIO", 3841 .type = RK3308, 3842 .grf_mux_offset = 0x0, 3843 .iomux_recalced = rk3308_mux_recalced_data, 3844 .niomux_recalced = ARRAY_SIZE(rk3308_mux_recalced_data), 3845 .iomux_routes = rk3308_mux_route_data, 3846 .niomux_routes = ARRAY_SIZE(rk3308_mux_route_data), 3847 .pull_calc_reg = rk3308_calc_pull_reg_and_bit, 3848 .drv_calc_reg = rk3308_calc_drv_reg_and_bit, 3849 .schmitt_calc_reg = rk3308_calc_schmitt_reg_and_bit, 3850 }; 3851 3852 static struct rockchip_pin_bank rk3328_pin_banks[] = { 3853 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0), 3854 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0), 3855 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 3856 IOMUX_WIDTH_3BIT, 3857 IOMUX_WIDTH_3BIT, 3858 0), 3859 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 3860 IOMUX_WIDTH_3BIT, 3861 IOMUX_WIDTH_3BIT, 3862 0, 3863 0), 3864 }; 3865 3866 static struct rockchip_pin_ctrl rk3328_pin_ctrl = { 3867 .pin_banks = rk3328_pin_banks, 3868 .nr_banks = ARRAY_SIZE(rk3328_pin_banks), 3869 .label = "RK3328-GPIO", 3870 .type = RK3288, 3871 .grf_mux_offset = 0x0, 3872 .iomux_recalced = rk3328_mux_recalced_data, 3873 .niomux_recalced = ARRAY_SIZE(rk3328_mux_recalced_data), 3874 .iomux_routes = rk3328_mux_route_data, 3875 .niomux_routes = ARRAY_SIZE(rk3328_mux_route_data), 3876 .pull_calc_reg = rk3228_calc_pull_reg_and_bit, 3877 .drv_calc_reg = rk3228_calc_drv_reg_and_bit, 3878 .schmitt_calc_reg = rk3328_calc_schmitt_reg_and_bit, 3879 }; 3880 3881 static struct rockchip_pin_bank rk3368_pin_banks[] = { 3882 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, 3883 IOMUX_SOURCE_PMU, 3884 IOMUX_SOURCE_PMU, 3885 IOMUX_SOURCE_PMU 3886 ), 3887 PIN_BANK(1, 32, "gpio1"), 3888 PIN_BANK(2, 32, "gpio2"), 3889 PIN_BANK(3, 32, "gpio3"), 3890 }; 3891 3892 static struct rockchip_pin_ctrl rk3368_pin_ctrl = { 3893 .pin_banks = rk3368_pin_banks, 3894 .nr_banks = ARRAY_SIZE(rk3368_pin_banks), 3895 .label = "RK3368-GPIO", 3896 .type = RK3368, 3897 .grf_mux_offset = 0x0, 3898 .pmu_mux_offset = 0x0, 3899 .pull_calc_reg = rk3368_calc_pull_reg_and_bit, 3900 .drv_calc_reg = rk3368_calc_drv_reg_and_bit, 3901 }; 3902 3903 static struct rockchip_pin_bank rk3399_pin_banks[] = { 3904 PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0", 3905 IOMUX_SOURCE_PMU, 3906 IOMUX_SOURCE_PMU, 3907 IOMUX_SOURCE_PMU, 3908 IOMUX_SOURCE_PMU, 3909 DRV_TYPE_IO_1V8_ONLY, 3910 DRV_TYPE_IO_1V8_ONLY, 3911 DRV_TYPE_IO_DEFAULT, 3912 DRV_TYPE_IO_DEFAULT, 3913 0x80, 3914 0x88, 3915 -1, 3916 -1, 3917 PULL_TYPE_IO_1V8_ONLY, 3918 PULL_TYPE_IO_1V8_ONLY, 3919 PULL_TYPE_IO_DEFAULT, 3920 PULL_TYPE_IO_DEFAULT 3921 ), 3922 PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU, 3923 IOMUX_SOURCE_PMU, 3924 IOMUX_SOURCE_PMU, 3925 IOMUX_SOURCE_PMU, 3926 DRV_TYPE_IO_1V8_OR_3V0, 3927 DRV_TYPE_IO_1V8_OR_3V0, 3928 DRV_TYPE_IO_1V8_OR_3V0, 3929 DRV_TYPE_IO_1V8_OR_3V0, 3930 0xa0, 3931 0xa8, 3932 0xb0, 3933 0xb8 3934 ), 3935 PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0, 3936 DRV_TYPE_IO_1V8_OR_3V0, 3937 DRV_TYPE_IO_1V8_ONLY, 3938 DRV_TYPE_IO_1V8_ONLY, 3939 PULL_TYPE_IO_DEFAULT, 3940 PULL_TYPE_IO_DEFAULT, 3941 PULL_TYPE_IO_1V8_ONLY, 3942 PULL_TYPE_IO_1V8_ONLY 3943 ), 3944 PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY, 3945 DRV_TYPE_IO_3V3_ONLY, 3946 DRV_TYPE_IO_3V3_ONLY, 3947 DRV_TYPE_IO_1V8_OR_3V0 3948 ), 3949 PIN_BANK_DRV_FLAGS(4, 32, "gpio4", DRV_TYPE_IO_1V8_OR_3V0, 3950 DRV_TYPE_IO_1V8_3V0_AUTO, 3951 DRV_TYPE_IO_1V8_OR_3V0, 3952 DRV_TYPE_IO_1V8_OR_3V0 3953 ), 3954 }; 3955 3956 static struct rockchip_pin_ctrl rk3399_pin_ctrl = { 3957 .pin_banks = rk3399_pin_banks, 3958 .nr_banks = ARRAY_SIZE(rk3399_pin_banks), 3959 .label = "RK3399-GPIO", 3960 .type = RK3399, 3961 .grf_mux_offset = 0xe000, 3962 .pmu_mux_offset = 0x0, 3963 .grf_drv_offset = 0xe100, 3964 .pmu_drv_offset = 0x80, 3965 .iomux_routes = rk3399_mux_route_data, 3966 .niomux_routes = ARRAY_SIZE(rk3399_mux_route_data), 3967 .pull_calc_reg = rk3399_calc_pull_reg_and_bit, 3968 .drv_calc_reg = rk3399_calc_drv_reg_and_bit, 3969 }; 3970 3971 static struct rockchip_pin_bank rk3568_pin_banks[] = { 3972 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT, 3973 IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT, 3974 IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT, 3975 IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT), 3976 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT, 3977 IOMUX_WIDTH_4BIT, 3978 IOMUX_WIDTH_4BIT, 3979 IOMUX_WIDTH_4BIT), 3980 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT, 3981 IOMUX_WIDTH_4BIT, 3982 IOMUX_WIDTH_4BIT, 3983 IOMUX_WIDTH_4BIT), 3984 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT, 3985 IOMUX_WIDTH_4BIT, 3986 IOMUX_WIDTH_4BIT, 3987 IOMUX_WIDTH_4BIT), 3988 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT, 3989 IOMUX_WIDTH_4BIT, 3990 IOMUX_WIDTH_4BIT, 3991 IOMUX_WIDTH_4BIT), 3992 }; 3993 3994 static struct rockchip_pin_ctrl rk3568_pin_ctrl = { 3995 .pin_banks = rk3568_pin_banks, 3996 .nr_banks = ARRAY_SIZE(rk3568_pin_banks), 3997 .label = "RK3568-GPIO", 3998 .type = RK3568, 3999 .grf_mux_offset = 0x0, 4000 .pmu_mux_offset = 0x0, 4001 .grf_drv_offset = 0x0200, 4002 .pmu_drv_offset = 0x0070, 4003 .iomux_routes = rk3568_mux_route_data, 4004 .niomux_routes = ARRAY_SIZE(rk3568_mux_route_data), 4005 .pull_calc_reg = rk3568_calc_pull_reg_and_bit, 4006 .drv_calc_reg = rk3568_calc_drv_reg_and_bit, 4007 .schmitt_calc_reg = rk3568_calc_schmitt_reg_and_bit, 4008 }; 4009 4010 static const struct of_device_id rockchip_pinctrl_dt_match[] = { 4011 { .compatible = "rockchip,px30-pinctrl", 4012 .data = &px30_pin_ctrl }, 4013 { .compatible = "rockchip,rv1108-pinctrl", 4014 .data = &rv1108_pin_ctrl }, 4015 { .compatible = "rockchip,rk2928-pinctrl", 4016 .data = &rk2928_pin_ctrl }, 4017 { .compatible = "rockchip,rk3036-pinctrl", 4018 .data = &rk3036_pin_ctrl }, 4019 { .compatible = "rockchip,rk3066a-pinctrl", 4020 .data = &rk3066a_pin_ctrl }, 4021 { .compatible = "rockchip,rk3066b-pinctrl", 4022 .data = &rk3066b_pin_ctrl }, 4023 { .compatible = "rockchip,rk3128-pinctrl", 4024 .data = (void *)&rk3128_pin_ctrl }, 4025 { .compatible = "rockchip,rk3188-pinctrl", 4026 .data = &rk3188_pin_ctrl }, 4027 { .compatible = "rockchip,rk3228-pinctrl", 4028 .data = &rk3228_pin_ctrl }, 4029 { .compatible = "rockchip,rk3288-pinctrl", 4030 .data = &rk3288_pin_ctrl }, 4031 { .compatible = "rockchip,rk3308-pinctrl", 4032 .data = &rk3308_pin_ctrl }, 4033 { .compatible = "rockchip,rk3328-pinctrl", 4034 .data = &rk3328_pin_ctrl }, 4035 { .compatible = "rockchip,rk3368-pinctrl", 4036 .data = &rk3368_pin_ctrl }, 4037 { .compatible = "rockchip,rk3399-pinctrl", 4038 .data = &rk3399_pin_ctrl }, 4039 { .compatible = "rockchip,rk3568-pinctrl", 4040 .data = &rk3568_pin_ctrl }, 4041 {}, 4042 }; 4043 4044 static struct platform_driver rockchip_pinctrl_driver = { 4045 .probe = rockchip_pinctrl_probe, 4046 .driver = { 4047 .name = "rockchip-pinctrl", 4048 .pm = &rockchip_pinctrl_dev_pm_ops, 4049 .of_match_table = rockchip_pinctrl_dt_match, 4050 }, 4051 }; 4052 4053 static int __init rockchip_pinctrl_drv_register(void) 4054 { 4055 return platform_driver_register(&rockchip_pinctrl_driver); 4056 } 4057 postcore_initcall(rockchip_pinctrl_drv_register); 4058 4059 static void __exit rockchip_pinctrl_drv_unregister(void) 4060 { 4061 platform_driver_unregister(&rockchip_pinctrl_driver); 4062 } 4063 module_exit(rockchip_pinctrl_drv_unregister); 4064 4065 MODULE_DESCRIPTION("ROCKCHIP Pin Controller Driver"); 4066 MODULE_LICENSE("GPL"); 4067 MODULE_ALIAS("platform:pinctrl-rockchip"); 4068 MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match); 4069