1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* 3 * Microsemi SoCs pinctrl driver 4 * 5 * Author: <alexandre.belloni@free-electrons.com> 6 * License: Dual MIT/GPL 7 * Copyright (c) 2017 Microsemi Corporation 8 */ 9 10 #include <linux/gpio/driver.h> 11 #include <linux/interrupt.h> 12 #include <linux/io.h> 13 #include <linux/of_device.h> 14 #include <linux/of_irq.h> 15 #include <linux/of_platform.h> 16 #include <linux/pinctrl/pinctrl.h> 17 #include <linux/pinctrl/pinmux.h> 18 #include <linux/pinctrl/pinconf.h> 19 #include <linux/pinctrl/pinconf-generic.h> 20 #include <linux/platform_device.h> 21 #include <linux/regmap.h> 22 #include <linux/slab.h> 23 24 #include "core.h" 25 #include "pinconf.h" 26 #include "pinmux.h" 27 28 #define OCELOT_GPIO_OUT_SET 0x0 29 #define OCELOT_GPIO_OUT_CLR 0x4 30 #define OCELOT_GPIO_OUT 0x8 31 #define OCELOT_GPIO_IN 0xc 32 #define OCELOT_GPIO_OE 0x10 33 #define OCELOT_GPIO_INTR 0x14 34 #define OCELOT_GPIO_INTR_ENA 0x18 35 #define OCELOT_GPIO_INTR_IDENT 0x1c 36 #define OCELOT_GPIO_ALT0 0x20 37 #define OCELOT_GPIO_ALT1 0x24 38 #define OCELOT_GPIO_SD_MAP 0x28 39 40 #define OCELOT_FUNC_PER_PIN 4 41 42 enum { 43 FUNC_NONE, 44 FUNC_GPIO, 45 FUNC_IRQ0_IN, 46 FUNC_IRQ0_OUT, 47 FUNC_IRQ1_IN, 48 FUNC_IRQ1_OUT, 49 FUNC_MIIM, 50 FUNC_PCI_WAKE, 51 FUNC_PTP0, 52 FUNC_PTP1, 53 FUNC_PTP2, 54 FUNC_PTP3, 55 FUNC_PWM, 56 FUNC_RECO_CLK, 57 FUNC_SFP, 58 FUNC_SG0, 59 FUNC_SG1, 60 FUNC_SG2, 61 FUNC_SI, 62 FUNC_TACHO, 63 FUNC_TWI, 64 FUNC_TWI2, 65 FUNC_TWI_SCL_M, 66 FUNC_UART, 67 FUNC_UART2, 68 FUNC_MAX 69 }; 70 71 static const char *const ocelot_function_names[] = { 72 [FUNC_NONE] = "none", 73 [FUNC_GPIO] = "gpio", 74 [FUNC_IRQ0_IN] = "irq0_in", 75 [FUNC_IRQ0_OUT] = "irq0_out", 76 [FUNC_IRQ1_IN] = "irq1_in", 77 [FUNC_IRQ1_OUT] = "irq1_out", 78 [FUNC_MIIM] = "miim", 79 [FUNC_PCI_WAKE] = "pci_wake", 80 [FUNC_PTP0] = "ptp0", 81 [FUNC_PTP1] = "ptp1", 82 [FUNC_PTP2] = "ptp2", 83 [FUNC_PTP3] = "ptp3", 84 [FUNC_PWM] = "pwm", 85 [FUNC_RECO_CLK] = "reco_clk", 86 [FUNC_SFP] = "sfp", 87 [FUNC_SG0] = "sg0", 88 [FUNC_SG1] = "sg1", 89 [FUNC_SG2] = "sg2", 90 [FUNC_SI] = "si", 91 [FUNC_TACHO] = "tacho", 92 [FUNC_TWI] = "twi", 93 [FUNC_TWI2] = "twi2", 94 [FUNC_TWI_SCL_M] = "twi_scl_m", 95 [FUNC_UART] = "uart", 96 [FUNC_UART2] = "uart2", 97 }; 98 99 struct ocelot_pmx_func { 100 const char **groups; 101 unsigned int ngroups; 102 }; 103 104 struct ocelot_pin_caps { 105 unsigned int pin; 106 unsigned char functions[OCELOT_FUNC_PER_PIN]; 107 }; 108 109 struct ocelot_pinctrl { 110 struct device *dev; 111 struct pinctrl_dev *pctl; 112 struct gpio_chip gpio_chip; 113 struct regmap *map; 114 struct pinctrl_desc *desc; 115 struct ocelot_pmx_func func[FUNC_MAX]; 116 u8 stride; 117 }; 118 119 #define OCELOT_P(p, f0, f1, f2) \ 120 static struct ocelot_pin_caps ocelot_pin_##p = { \ 121 .pin = p, \ 122 .functions = { \ 123 FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2, \ 124 }, \ 125 } 126 127 OCELOT_P(0, SG0, NONE, NONE); 128 OCELOT_P(1, SG0, NONE, NONE); 129 OCELOT_P(2, SG0, NONE, NONE); 130 OCELOT_P(3, SG0, NONE, NONE); 131 OCELOT_P(4, IRQ0_IN, IRQ0_OUT, TWI_SCL_M); 132 OCELOT_P(5, IRQ1_IN, IRQ1_OUT, PCI_WAKE); 133 OCELOT_P(6, UART, TWI_SCL_M, NONE); 134 OCELOT_P(7, UART, TWI_SCL_M, NONE); 135 OCELOT_P(8, SI, TWI_SCL_M, IRQ0_OUT); 136 OCELOT_P(9, SI, TWI_SCL_M, IRQ1_OUT); 137 OCELOT_P(10, PTP2, TWI_SCL_M, SFP); 138 OCELOT_P(11, PTP3, TWI_SCL_M, SFP); 139 OCELOT_P(12, UART2, TWI_SCL_M, SFP); 140 OCELOT_P(13, UART2, TWI_SCL_M, SFP); 141 OCELOT_P(14, MIIM, TWI_SCL_M, SFP); 142 OCELOT_P(15, MIIM, TWI_SCL_M, SFP); 143 OCELOT_P(16, TWI, NONE, SI); 144 OCELOT_P(17, TWI, TWI_SCL_M, SI); 145 OCELOT_P(18, PTP0, TWI_SCL_M, NONE); 146 OCELOT_P(19, PTP1, TWI_SCL_M, NONE); 147 OCELOT_P(20, RECO_CLK, TACHO, TWI_SCL_M); 148 OCELOT_P(21, RECO_CLK, PWM, TWI_SCL_M); 149 150 #define OCELOT_PIN(n) { \ 151 .number = n, \ 152 .name = "GPIO_"#n, \ 153 .drv_data = &ocelot_pin_##n \ 154 } 155 156 static const struct pinctrl_pin_desc ocelot_pins[] = { 157 OCELOT_PIN(0), 158 OCELOT_PIN(1), 159 OCELOT_PIN(2), 160 OCELOT_PIN(3), 161 OCELOT_PIN(4), 162 OCELOT_PIN(5), 163 OCELOT_PIN(6), 164 OCELOT_PIN(7), 165 OCELOT_PIN(8), 166 OCELOT_PIN(9), 167 OCELOT_PIN(10), 168 OCELOT_PIN(11), 169 OCELOT_PIN(12), 170 OCELOT_PIN(13), 171 OCELOT_PIN(14), 172 OCELOT_PIN(15), 173 OCELOT_PIN(16), 174 OCELOT_PIN(17), 175 OCELOT_PIN(18), 176 OCELOT_PIN(19), 177 OCELOT_PIN(20), 178 OCELOT_PIN(21), 179 }; 180 181 #define JAGUAR2_P(p, f0, f1) \ 182 static struct ocelot_pin_caps jaguar2_pin_##p = { \ 183 .pin = p, \ 184 .functions = { \ 185 FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_NONE \ 186 }, \ 187 } 188 189 JAGUAR2_P(0, SG0, NONE); 190 JAGUAR2_P(1, SG0, NONE); 191 JAGUAR2_P(2, SG0, NONE); 192 JAGUAR2_P(3, SG0, NONE); 193 JAGUAR2_P(4, SG1, NONE); 194 JAGUAR2_P(5, SG1, NONE); 195 JAGUAR2_P(6, IRQ0_IN, IRQ0_OUT); 196 JAGUAR2_P(7, IRQ1_IN, IRQ1_OUT); 197 JAGUAR2_P(8, PTP0, NONE); 198 JAGUAR2_P(9, PTP1, NONE); 199 JAGUAR2_P(10, UART, NONE); 200 JAGUAR2_P(11, UART, NONE); 201 JAGUAR2_P(12, SG1, NONE); 202 JAGUAR2_P(13, SG1, NONE); 203 JAGUAR2_P(14, TWI, TWI_SCL_M); 204 JAGUAR2_P(15, TWI, NONE); 205 JAGUAR2_P(16, SI, TWI_SCL_M); 206 JAGUAR2_P(17, SI, TWI_SCL_M); 207 JAGUAR2_P(18, SI, TWI_SCL_M); 208 JAGUAR2_P(19, PCI_WAKE, NONE); 209 JAGUAR2_P(20, IRQ0_OUT, TWI_SCL_M); 210 JAGUAR2_P(21, IRQ1_OUT, TWI_SCL_M); 211 JAGUAR2_P(22, TACHO, NONE); 212 JAGUAR2_P(23, PWM, NONE); 213 JAGUAR2_P(24, UART2, NONE); 214 JAGUAR2_P(25, UART2, SI); 215 JAGUAR2_P(26, PTP2, SI); 216 JAGUAR2_P(27, PTP3, SI); 217 JAGUAR2_P(28, TWI2, SI); 218 JAGUAR2_P(29, TWI2, SI); 219 JAGUAR2_P(30, SG2, SI); 220 JAGUAR2_P(31, SG2, SI); 221 JAGUAR2_P(32, SG2, SI); 222 JAGUAR2_P(33, SG2, SI); 223 JAGUAR2_P(34, NONE, TWI_SCL_M); 224 JAGUAR2_P(35, NONE, TWI_SCL_M); 225 JAGUAR2_P(36, NONE, TWI_SCL_M); 226 JAGUAR2_P(37, NONE, TWI_SCL_M); 227 JAGUAR2_P(38, NONE, TWI_SCL_M); 228 JAGUAR2_P(39, NONE, TWI_SCL_M); 229 JAGUAR2_P(40, NONE, TWI_SCL_M); 230 JAGUAR2_P(41, NONE, TWI_SCL_M); 231 JAGUAR2_P(42, NONE, TWI_SCL_M); 232 JAGUAR2_P(43, NONE, TWI_SCL_M); 233 JAGUAR2_P(44, NONE, SFP); 234 JAGUAR2_P(45, NONE, SFP); 235 JAGUAR2_P(46, NONE, SFP); 236 JAGUAR2_P(47, NONE, SFP); 237 JAGUAR2_P(48, SFP, NONE); 238 JAGUAR2_P(49, SFP, SI); 239 JAGUAR2_P(50, SFP, SI); 240 JAGUAR2_P(51, SFP, SI); 241 JAGUAR2_P(52, SFP, NONE); 242 JAGUAR2_P(53, SFP, NONE); 243 JAGUAR2_P(54, SFP, NONE); 244 JAGUAR2_P(55, SFP, NONE); 245 JAGUAR2_P(56, MIIM, SFP); 246 JAGUAR2_P(57, MIIM, SFP); 247 JAGUAR2_P(58, MIIM, SFP); 248 JAGUAR2_P(59, MIIM, SFP); 249 JAGUAR2_P(60, NONE, NONE); 250 JAGUAR2_P(61, NONE, NONE); 251 JAGUAR2_P(62, NONE, NONE); 252 JAGUAR2_P(63, NONE, NONE); 253 254 #define JAGUAR2_PIN(n) { \ 255 .number = n, \ 256 .name = "GPIO_"#n, \ 257 .drv_data = &jaguar2_pin_##n \ 258 } 259 260 static const struct pinctrl_pin_desc jaguar2_pins[] = { 261 JAGUAR2_PIN(0), 262 JAGUAR2_PIN(1), 263 JAGUAR2_PIN(2), 264 JAGUAR2_PIN(3), 265 JAGUAR2_PIN(4), 266 JAGUAR2_PIN(5), 267 JAGUAR2_PIN(6), 268 JAGUAR2_PIN(7), 269 JAGUAR2_PIN(8), 270 JAGUAR2_PIN(9), 271 JAGUAR2_PIN(10), 272 JAGUAR2_PIN(11), 273 JAGUAR2_PIN(12), 274 JAGUAR2_PIN(13), 275 JAGUAR2_PIN(14), 276 JAGUAR2_PIN(15), 277 JAGUAR2_PIN(16), 278 JAGUAR2_PIN(17), 279 JAGUAR2_PIN(18), 280 JAGUAR2_PIN(19), 281 JAGUAR2_PIN(20), 282 JAGUAR2_PIN(21), 283 JAGUAR2_PIN(22), 284 JAGUAR2_PIN(23), 285 JAGUAR2_PIN(24), 286 JAGUAR2_PIN(25), 287 JAGUAR2_PIN(26), 288 JAGUAR2_PIN(27), 289 JAGUAR2_PIN(28), 290 JAGUAR2_PIN(29), 291 JAGUAR2_PIN(30), 292 JAGUAR2_PIN(31), 293 JAGUAR2_PIN(32), 294 JAGUAR2_PIN(33), 295 JAGUAR2_PIN(34), 296 JAGUAR2_PIN(35), 297 JAGUAR2_PIN(36), 298 JAGUAR2_PIN(37), 299 JAGUAR2_PIN(38), 300 JAGUAR2_PIN(39), 301 JAGUAR2_PIN(40), 302 JAGUAR2_PIN(41), 303 JAGUAR2_PIN(42), 304 JAGUAR2_PIN(43), 305 JAGUAR2_PIN(44), 306 JAGUAR2_PIN(45), 307 JAGUAR2_PIN(46), 308 JAGUAR2_PIN(47), 309 JAGUAR2_PIN(48), 310 JAGUAR2_PIN(49), 311 JAGUAR2_PIN(50), 312 JAGUAR2_PIN(51), 313 JAGUAR2_PIN(52), 314 JAGUAR2_PIN(53), 315 JAGUAR2_PIN(54), 316 JAGUAR2_PIN(55), 317 JAGUAR2_PIN(56), 318 JAGUAR2_PIN(57), 319 JAGUAR2_PIN(58), 320 JAGUAR2_PIN(59), 321 JAGUAR2_PIN(60), 322 JAGUAR2_PIN(61), 323 JAGUAR2_PIN(62), 324 JAGUAR2_PIN(63), 325 }; 326 327 static int ocelot_get_functions_count(struct pinctrl_dev *pctldev) 328 { 329 return ARRAY_SIZE(ocelot_function_names); 330 } 331 332 static const char *ocelot_get_function_name(struct pinctrl_dev *pctldev, 333 unsigned int function) 334 { 335 return ocelot_function_names[function]; 336 } 337 338 static int ocelot_get_function_groups(struct pinctrl_dev *pctldev, 339 unsigned int function, 340 const char *const **groups, 341 unsigned *const num_groups) 342 { 343 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 344 345 *groups = info->func[function].groups; 346 *num_groups = info->func[function].ngroups; 347 348 return 0; 349 } 350 351 static int ocelot_pin_function_idx(struct ocelot_pinctrl *info, 352 unsigned int pin, unsigned int function) 353 { 354 struct ocelot_pin_caps *p = info->desc->pins[pin].drv_data; 355 int i; 356 357 for (i = 0; i < OCELOT_FUNC_PER_PIN; i++) { 358 if (function == p->functions[i]) 359 return i; 360 } 361 362 return -1; 363 } 364 365 #define REG_ALT(msb, info, p) (OCELOT_GPIO_ALT0 * (info)->stride + 4 * ((msb) + ((info)->stride * ((p) / 32)))) 366 367 static int ocelot_pinmux_set_mux(struct pinctrl_dev *pctldev, 368 unsigned int selector, unsigned int group) 369 { 370 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 371 struct ocelot_pin_caps *pin = info->desc->pins[group].drv_data; 372 unsigned int p = pin->pin % 32; 373 int f; 374 375 f = ocelot_pin_function_idx(info, group, selector); 376 if (f < 0) 377 return -EINVAL; 378 379 /* 380 * f is encoded on two bits. 381 * bit 0 of f goes in BIT(pin) of ALT[0], bit 1 of f goes in BIT(pin) of 382 * ALT[1] 383 * This is racy because both registers can't be updated at the same time 384 * but it doesn't matter much for now. 385 */ 386 regmap_update_bits(info->map, REG_ALT(0, info, pin->pin), 387 BIT(p), f << p); 388 regmap_update_bits(info->map, REG_ALT(1, info, pin->pin), 389 BIT(p), f << (p - 1)); 390 391 return 0; 392 } 393 394 #define REG(r, info, p) ((r) * (info)->stride + (4 * ((p) / 32))) 395 396 static int ocelot_gpio_set_direction(struct pinctrl_dev *pctldev, 397 struct pinctrl_gpio_range *range, 398 unsigned int pin, bool input) 399 { 400 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 401 unsigned int p = pin % 32; 402 403 regmap_update_bits(info->map, REG(OCELOT_GPIO_OE, info, pin), BIT(p), 404 input ? 0 : BIT(p)); 405 406 return 0; 407 } 408 409 static int ocelot_gpio_request_enable(struct pinctrl_dev *pctldev, 410 struct pinctrl_gpio_range *range, 411 unsigned int offset) 412 { 413 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 414 unsigned int p = offset % 32; 415 416 regmap_update_bits(info->map, REG_ALT(0, info, offset), 417 BIT(p), 0); 418 regmap_update_bits(info->map, REG_ALT(1, info, offset), 419 BIT(p), 0); 420 421 return 0; 422 } 423 424 static const struct pinmux_ops ocelot_pmx_ops = { 425 .get_functions_count = ocelot_get_functions_count, 426 .get_function_name = ocelot_get_function_name, 427 .get_function_groups = ocelot_get_function_groups, 428 .set_mux = ocelot_pinmux_set_mux, 429 .gpio_set_direction = ocelot_gpio_set_direction, 430 .gpio_request_enable = ocelot_gpio_request_enable, 431 }; 432 433 static int ocelot_pctl_get_groups_count(struct pinctrl_dev *pctldev) 434 { 435 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 436 437 return info->desc->npins; 438 } 439 440 static const char *ocelot_pctl_get_group_name(struct pinctrl_dev *pctldev, 441 unsigned int group) 442 { 443 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 444 445 return info->desc->pins[group].name; 446 } 447 448 static int ocelot_pctl_get_group_pins(struct pinctrl_dev *pctldev, 449 unsigned int group, 450 const unsigned int **pins, 451 unsigned int *num_pins) 452 { 453 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 454 455 *pins = &info->desc->pins[group].number; 456 *num_pins = 1; 457 458 return 0; 459 } 460 461 static const struct pinctrl_ops ocelot_pctl_ops = { 462 .get_groups_count = ocelot_pctl_get_groups_count, 463 .get_group_name = ocelot_pctl_get_group_name, 464 .get_group_pins = ocelot_pctl_get_group_pins, 465 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, 466 .dt_free_map = pinconf_generic_dt_free_map, 467 }; 468 469 static struct pinctrl_desc ocelot_desc = { 470 .name = "ocelot-pinctrl", 471 .pins = ocelot_pins, 472 .npins = ARRAY_SIZE(ocelot_pins), 473 .pctlops = &ocelot_pctl_ops, 474 .pmxops = &ocelot_pmx_ops, 475 .owner = THIS_MODULE, 476 }; 477 478 static struct pinctrl_desc jaguar2_desc = { 479 .name = "jaguar2-pinctrl", 480 .pins = jaguar2_pins, 481 .npins = ARRAY_SIZE(jaguar2_pins), 482 .pctlops = &ocelot_pctl_ops, 483 .pmxops = &ocelot_pmx_ops, 484 .owner = THIS_MODULE, 485 }; 486 487 static int ocelot_create_group_func_map(struct device *dev, 488 struct ocelot_pinctrl *info) 489 { 490 int f, npins, i; 491 u8 *pins = kcalloc(info->desc->npins, sizeof(u8), GFP_KERNEL); 492 493 if (!pins) 494 return -ENOMEM; 495 496 for (f = 0; f < FUNC_MAX; f++) { 497 for (npins = 0, i = 0; i < info->desc->npins; i++) { 498 if (ocelot_pin_function_idx(info, i, f) >= 0) 499 pins[npins++] = i; 500 } 501 502 if (!npins) 503 continue; 504 505 info->func[f].ngroups = npins; 506 info->func[f].groups = devm_kcalloc(dev, npins, sizeof(char *), 507 GFP_KERNEL); 508 if (!info->func[f].groups) { 509 kfree(pins); 510 return -ENOMEM; 511 } 512 513 for (i = 0; i < npins; i++) 514 info->func[f].groups[i] = info->desc->pins[pins[i]].name; 515 } 516 517 kfree(pins); 518 519 return 0; 520 } 521 522 static int ocelot_pinctrl_register(struct platform_device *pdev, 523 struct ocelot_pinctrl *info) 524 { 525 int ret; 526 527 ret = ocelot_create_group_func_map(&pdev->dev, info); 528 if (ret) { 529 dev_err(&pdev->dev, "Unable to create group func map.\n"); 530 return ret; 531 } 532 533 info->pctl = devm_pinctrl_register(&pdev->dev, info->desc, info); 534 if (IS_ERR(info->pctl)) { 535 dev_err(&pdev->dev, "Failed to register pinctrl\n"); 536 return PTR_ERR(info->pctl); 537 } 538 539 return 0; 540 } 541 542 static int ocelot_gpio_get(struct gpio_chip *chip, unsigned int offset) 543 { 544 struct ocelot_pinctrl *info = gpiochip_get_data(chip); 545 unsigned int val; 546 547 regmap_read(info->map, REG(OCELOT_GPIO_IN, info, offset), &val); 548 549 return !!(val & BIT(offset % 32)); 550 } 551 552 static void ocelot_gpio_set(struct gpio_chip *chip, unsigned int offset, 553 int value) 554 { 555 struct ocelot_pinctrl *info = gpiochip_get_data(chip); 556 557 if (value) 558 regmap_write(info->map, REG(OCELOT_GPIO_OUT_SET, info, offset), 559 BIT(offset % 32)); 560 else 561 regmap_write(info->map, REG(OCELOT_GPIO_OUT_CLR, info, offset), 562 BIT(offset % 32)); 563 } 564 565 static int ocelot_gpio_get_direction(struct gpio_chip *chip, 566 unsigned int offset) 567 { 568 struct ocelot_pinctrl *info = gpiochip_get_data(chip); 569 unsigned int val; 570 571 regmap_read(info->map, REG(OCELOT_GPIO_OE, info, offset), &val); 572 573 if (val & BIT(offset % 32)) 574 return GPIO_LINE_DIRECTION_OUT; 575 576 return GPIO_LINE_DIRECTION_IN; 577 } 578 579 static int ocelot_gpio_direction_input(struct gpio_chip *chip, 580 unsigned int offset) 581 { 582 return pinctrl_gpio_direction_input(chip->base + offset); 583 } 584 585 static int ocelot_gpio_direction_output(struct gpio_chip *chip, 586 unsigned int offset, int value) 587 { 588 struct ocelot_pinctrl *info = gpiochip_get_data(chip); 589 unsigned int pin = BIT(offset % 32); 590 591 if (value) 592 regmap_write(info->map, REG(OCELOT_GPIO_OUT_SET, info, offset), 593 pin); 594 else 595 regmap_write(info->map, REG(OCELOT_GPIO_OUT_CLR, info, offset), 596 pin); 597 598 return pinctrl_gpio_direction_output(chip->base + offset); 599 } 600 601 static const struct gpio_chip ocelot_gpiolib_chip = { 602 .request = gpiochip_generic_request, 603 .free = gpiochip_generic_free, 604 .set = ocelot_gpio_set, 605 .get = ocelot_gpio_get, 606 .get_direction = ocelot_gpio_get_direction, 607 .direction_input = ocelot_gpio_direction_input, 608 .direction_output = ocelot_gpio_direction_output, 609 .owner = THIS_MODULE, 610 }; 611 612 static void ocelot_irq_mask(struct irq_data *data) 613 { 614 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 615 struct ocelot_pinctrl *info = gpiochip_get_data(chip); 616 unsigned int gpio = irqd_to_hwirq(data); 617 618 regmap_update_bits(info->map, REG(OCELOT_GPIO_INTR_ENA, info, gpio), 619 BIT(gpio % 32), 0); 620 } 621 622 static void ocelot_irq_unmask(struct irq_data *data) 623 { 624 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 625 struct ocelot_pinctrl *info = gpiochip_get_data(chip); 626 unsigned int gpio = irqd_to_hwirq(data); 627 628 regmap_update_bits(info->map, REG(OCELOT_GPIO_INTR_ENA, info, gpio), 629 BIT(gpio % 32), BIT(gpio % 32)); 630 } 631 632 static void ocelot_irq_ack(struct irq_data *data) 633 { 634 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 635 struct ocelot_pinctrl *info = gpiochip_get_data(chip); 636 unsigned int gpio = irqd_to_hwirq(data); 637 638 regmap_write_bits(info->map, REG(OCELOT_GPIO_INTR, info, gpio), 639 BIT(gpio % 32), BIT(gpio % 32)); 640 } 641 642 static int ocelot_irq_set_type(struct irq_data *data, unsigned int type); 643 644 static struct irq_chip ocelot_eoi_irqchip = { 645 .name = "gpio", 646 .irq_mask = ocelot_irq_mask, 647 .irq_eoi = ocelot_irq_ack, 648 .irq_unmask = ocelot_irq_unmask, 649 .flags = IRQCHIP_EOI_THREADED | IRQCHIP_EOI_IF_HANDLED, 650 .irq_set_type = ocelot_irq_set_type, 651 }; 652 653 static struct irq_chip ocelot_irqchip = { 654 .name = "gpio", 655 .irq_mask = ocelot_irq_mask, 656 .irq_ack = ocelot_irq_ack, 657 .irq_unmask = ocelot_irq_unmask, 658 .irq_set_type = ocelot_irq_set_type, 659 }; 660 661 static int ocelot_irq_set_type(struct irq_data *data, unsigned int type) 662 { 663 type &= IRQ_TYPE_SENSE_MASK; 664 665 if (!(type & (IRQ_TYPE_EDGE_BOTH | IRQ_TYPE_LEVEL_HIGH))) 666 return -EINVAL; 667 668 if (type & IRQ_TYPE_LEVEL_HIGH) 669 irq_set_chip_handler_name_locked(data, &ocelot_eoi_irqchip, 670 handle_fasteoi_irq, NULL); 671 if (type & IRQ_TYPE_EDGE_BOTH) 672 irq_set_chip_handler_name_locked(data, &ocelot_irqchip, 673 handle_edge_irq, NULL); 674 675 return 0; 676 } 677 678 static void ocelot_irq_handler(struct irq_desc *desc) 679 { 680 struct irq_chip *parent_chip = irq_desc_get_chip(desc); 681 struct gpio_chip *chip = irq_desc_get_handler_data(desc); 682 struct ocelot_pinctrl *info = gpiochip_get_data(chip); 683 unsigned int id_reg = OCELOT_GPIO_INTR_IDENT * info->stride; 684 unsigned int reg = 0, irq, i; 685 unsigned long irqs; 686 687 for (i = 0; i < info->stride; i++) { 688 regmap_read(info->map, id_reg + 4 * i, ®); 689 if (!reg) 690 continue; 691 692 chained_irq_enter(parent_chip, desc); 693 694 irqs = reg; 695 696 for_each_set_bit(irq, &irqs, 697 min(32U, info->desc->npins - 32 * i)) 698 generic_handle_irq(irq_linear_revmap(chip->irq.domain, 699 irq + 32 * i)); 700 701 chained_irq_exit(parent_chip, desc); 702 } 703 } 704 705 static int ocelot_gpiochip_register(struct platform_device *pdev, 706 struct ocelot_pinctrl *info) 707 { 708 struct gpio_chip *gc; 709 struct gpio_irq_chip *girq; 710 int ret, irq; 711 712 info->gpio_chip = ocelot_gpiolib_chip; 713 714 gc = &info->gpio_chip; 715 gc->ngpio = info->desc->npins; 716 gc->parent = &pdev->dev; 717 gc->base = 0; 718 gc->of_node = info->dev->of_node; 719 gc->label = "ocelot-gpio"; 720 721 irq = irq_of_parse_and_map(gc->of_node, 0); 722 if (irq) { 723 girq = &gc->irq; 724 girq->chip = &ocelot_irqchip; 725 girq->parent_handler = ocelot_irq_handler; 726 girq->num_parents = 1; 727 girq->parents = devm_kcalloc(&pdev->dev, 1, 728 sizeof(*girq->parents), 729 GFP_KERNEL); 730 if (!girq->parents) 731 return -ENOMEM; 732 girq->parents[0] = irq; 733 girq->default_type = IRQ_TYPE_NONE; 734 girq->handler = handle_edge_irq; 735 } 736 737 ret = devm_gpiochip_add_data(&pdev->dev, gc, info); 738 if (ret) 739 return ret; 740 741 return 0; 742 } 743 744 static const struct of_device_id ocelot_pinctrl_of_match[] = { 745 { .compatible = "mscc,ocelot-pinctrl", .data = &ocelot_desc }, 746 { .compatible = "mscc,jaguar2-pinctrl", .data = &jaguar2_desc }, 747 {}, 748 }; 749 750 static int ocelot_pinctrl_probe(struct platform_device *pdev) 751 { 752 struct device *dev = &pdev->dev; 753 struct ocelot_pinctrl *info; 754 void __iomem *base; 755 int ret; 756 struct regmap_config regmap_config = { 757 .reg_bits = 32, 758 .val_bits = 32, 759 .reg_stride = 4, 760 }; 761 762 info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL); 763 if (!info) 764 return -ENOMEM; 765 766 info->desc = (struct pinctrl_desc *)device_get_match_data(dev); 767 768 base = devm_ioremap_resource(dev, 769 platform_get_resource(pdev, IORESOURCE_MEM, 0)); 770 if (IS_ERR(base)) { 771 dev_err(dev, "Failed to ioremap registers\n"); 772 return PTR_ERR(base); 773 } 774 775 info->stride = 1 + (info->desc->npins - 1) / 32; 776 regmap_config.max_register = OCELOT_GPIO_SD_MAP * info->stride + 15 * 4; 777 778 info->map = devm_regmap_init_mmio(dev, base, ®map_config); 779 if (IS_ERR(info->map)) { 780 dev_err(dev, "Failed to create regmap\n"); 781 return PTR_ERR(info->map); 782 } 783 dev_set_drvdata(dev, info->map); 784 info->dev = dev; 785 786 ret = ocelot_pinctrl_register(pdev, info); 787 if (ret) 788 return ret; 789 790 ret = ocelot_gpiochip_register(pdev, info); 791 if (ret) 792 return ret; 793 794 return 0; 795 } 796 797 static struct platform_driver ocelot_pinctrl_driver = { 798 .driver = { 799 .name = "pinctrl-ocelot", 800 .of_match_table = of_match_ptr(ocelot_pinctrl_of_match), 801 .suppress_bind_attrs = true, 802 }, 803 .probe = ocelot_pinctrl_probe, 804 }; 805 builtin_platform_driver(ocelot_pinctrl_driver); 806