1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* 3 * Microsemi SoCs pinctrl driver 4 * 5 * Author: <alexandre.belloni@free-electrons.com> 6 * License: Dual MIT/GPL 7 * Copyright (c) 2017 Microsemi Corporation 8 */ 9 10 #include <linux/gpio/driver.h> 11 #include <linux/interrupt.h> 12 #include <linux/io.h> 13 #include <linux/of_device.h> 14 #include <linux/of_irq.h> 15 #include <linux/of_platform.h> 16 #include <linux/pinctrl/pinctrl.h> 17 #include <linux/pinctrl/pinmux.h> 18 #include <linux/pinctrl/pinconf.h> 19 #include <linux/pinctrl/pinconf-generic.h> 20 #include <linux/platform_device.h> 21 #include <linux/regmap.h> 22 #include <linux/slab.h> 23 24 #include "core.h" 25 #include "pinconf.h" 26 #include "pinmux.h" 27 28 #define ocelot_clrsetbits(addr, clear, set) \ 29 writel((readl(addr) & ~(clear)) | (set), (addr)) 30 31 /* PINCONFIG bits (sparx5 only) */ 32 enum { 33 PINCONF_BIAS, 34 PINCONF_SCHMITT, 35 PINCONF_DRIVE_STRENGTH, 36 }; 37 38 #define BIAS_PD_BIT BIT(4) 39 #define BIAS_PU_BIT BIT(3) 40 #define BIAS_BITS (BIAS_PD_BIT|BIAS_PU_BIT) 41 #define SCHMITT_BIT BIT(2) 42 #define DRIVE_BITS GENMASK(1, 0) 43 44 /* GPIO standard registers */ 45 #define OCELOT_GPIO_OUT_SET 0x0 46 #define OCELOT_GPIO_OUT_CLR 0x4 47 #define OCELOT_GPIO_OUT 0x8 48 #define OCELOT_GPIO_IN 0xc 49 #define OCELOT_GPIO_OE 0x10 50 #define OCELOT_GPIO_INTR 0x14 51 #define OCELOT_GPIO_INTR_ENA 0x18 52 #define OCELOT_GPIO_INTR_IDENT 0x1c 53 #define OCELOT_GPIO_ALT0 0x20 54 #define OCELOT_GPIO_ALT1 0x24 55 #define OCELOT_GPIO_SD_MAP 0x28 56 57 #define OCELOT_FUNC_PER_PIN 4 58 59 enum { 60 FUNC_CAN0_a, 61 FUNC_CAN0_b, 62 FUNC_CAN1, 63 FUNC_NONE, 64 FUNC_FC0_a, 65 FUNC_FC0_b, 66 FUNC_FC0_c, 67 FUNC_FC1_a, 68 FUNC_FC1_b, 69 FUNC_FC1_c, 70 FUNC_FC2_a, 71 FUNC_FC2_b, 72 FUNC_FC3_a, 73 FUNC_FC3_b, 74 FUNC_FC3_c, 75 FUNC_FC4_a, 76 FUNC_FC4_b, 77 FUNC_FC4_c, 78 FUNC_FC_SHRD0, 79 FUNC_FC_SHRD1, 80 FUNC_FC_SHRD2, 81 FUNC_FC_SHRD3, 82 FUNC_FC_SHRD4, 83 FUNC_FC_SHRD5, 84 FUNC_FC_SHRD6, 85 FUNC_FC_SHRD7, 86 FUNC_FC_SHRD8, 87 FUNC_FC_SHRD9, 88 FUNC_FC_SHRD10, 89 FUNC_FC_SHRD11, 90 FUNC_FC_SHRD12, 91 FUNC_FC_SHRD13, 92 FUNC_FC_SHRD14, 93 FUNC_FC_SHRD15, 94 FUNC_FC_SHRD16, 95 FUNC_FC_SHRD17, 96 FUNC_FC_SHRD18, 97 FUNC_FC_SHRD19, 98 FUNC_FC_SHRD20, 99 FUNC_GPIO, 100 FUNC_IB_TRG_a, 101 FUNC_IB_TRG_b, 102 FUNC_IB_TRG_c, 103 FUNC_IRQ0, 104 FUNC_IRQ_IN_a, 105 FUNC_IRQ_IN_b, 106 FUNC_IRQ_IN_c, 107 FUNC_IRQ0_IN, 108 FUNC_IRQ_OUT_a, 109 FUNC_IRQ_OUT_b, 110 FUNC_IRQ_OUT_c, 111 FUNC_IRQ0_OUT, 112 FUNC_IRQ1, 113 FUNC_IRQ1_IN, 114 FUNC_IRQ1_OUT, 115 FUNC_EXT_IRQ, 116 FUNC_MIIM, 117 FUNC_MIIM_a, 118 FUNC_MIIM_b, 119 FUNC_MIIM_c, 120 FUNC_MIIM_Sa, 121 FUNC_MIIM_Sb, 122 FUNC_OB_TRG, 123 FUNC_OB_TRG_a, 124 FUNC_OB_TRG_b, 125 FUNC_PHY_LED, 126 FUNC_PCI_WAKE, 127 FUNC_MD, 128 FUNC_PTP0, 129 FUNC_PTP1, 130 FUNC_PTP2, 131 FUNC_PTP3, 132 FUNC_PTPSYNC_1, 133 FUNC_PTPSYNC_2, 134 FUNC_PTPSYNC_3, 135 FUNC_PTPSYNC_4, 136 FUNC_PTPSYNC_5, 137 FUNC_PTPSYNC_6, 138 FUNC_PTPSYNC_7, 139 FUNC_PWM, 140 FUNC_QSPI1, 141 FUNC_QSPI2, 142 FUNC_R, 143 FUNC_RECO_a, 144 FUNC_RECO_b, 145 FUNC_RECO_CLK, 146 FUNC_SD, 147 FUNC_SFP, 148 FUNC_SFP_SD, 149 FUNC_SG0, 150 FUNC_SG1, 151 FUNC_SG2, 152 FUNC_SGPIO_a, 153 FUNC_SGPIO_b, 154 FUNC_SI, 155 FUNC_SI2, 156 FUNC_TACHO, 157 FUNC_TACHO_a, 158 FUNC_TACHO_b, 159 FUNC_TWI, 160 FUNC_TWI2, 161 FUNC_TWI3, 162 FUNC_TWI_SCL_M, 163 FUNC_TWI_SLC_GATE, 164 FUNC_TWI_SLC_GATE_AD, 165 FUNC_UART, 166 FUNC_UART2, 167 FUNC_UART3, 168 FUNC_USB_H_a, 169 FUNC_USB_H_b, 170 FUNC_USB_H_c, 171 FUNC_USB_S_a, 172 FUNC_USB_S_b, 173 FUNC_USB_S_c, 174 FUNC_PLL_STAT, 175 FUNC_EMMC, 176 FUNC_EMMC_SD, 177 FUNC_REF_CLK, 178 FUNC_RCVRD_CLK, 179 FUNC_MAX 180 }; 181 182 static const char *const ocelot_function_names[] = { 183 [FUNC_CAN0_a] = "can0_a", 184 [FUNC_CAN0_b] = "can0_b", 185 [FUNC_CAN1] = "can1", 186 [FUNC_NONE] = "none", 187 [FUNC_FC0_a] = "fc0_a", 188 [FUNC_FC0_b] = "fc0_b", 189 [FUNC_FC0_c] = "fc0_c", 190 [FUNC_FC1_a] = "fc1_a", 191 [FUNC_FC1_b] = "fc1_b", 192 [FUNC_FC1_c] = "fc1_c", 193 [FUNC_FC2_a] = "fc2_a", 194 [FUNC_FC2_b] = "fc2_b", 195 [FUNC_FC3_a] = "fc3_a", 196 [FUNC_FC3_b] = "fc3_b", 197 [FUNC_FC3_c] = "fc3_c", 198 [FUNC_FC4_a] = "fc4_a", 199 [FUNC_FC4_b] = "fc4_b", 200 [FUNC_FC4_c] = "fc4_c", 201 [FUNC_FC_SHRD0] = "fc_shrd0", 202 [FUNC_FC_SHRD1] = "fc_shrd1", 203 [FUNC_FC_SHRD2] = "fc_shrd2", 204 [FUNC_FC_SHRD3] = "fc_shrd3", 205 [FUNC_FC_SHRD4] = "fc_shrd4", 206 [FUNC_FC_SHRD5] = "fc_shrd5", 207 [FUNC_FC_SHRD6] = "fc_shrd6", 208 [FUNC_FC_SHRD7] = "fc_shrd7", 209 [FUNC_FC_SHRD8] = "fc_shrd8", 210 [FUNC_FC_SHRD9] = "fc_shrd9", 211 [FUNC_FC_SHRD10] = "fc_shrd10", 212 [FUNC_FC_SHRD11] = "fc_shrd11", 213 [FUNC_FC_SHRD12] = "fc_shrd12", 214 [FUNC_FC_SHRD13] = "fc_shrd13", 215 [FUNC_FC_SHRD14] = "fc_shrd14", 216 [FUNC_FC_SHRD15] = "fc_shrd15", 217 [FUNC_FC_SHRD16] = "fc_shrd16", 218 [FUNC_FC_SHRD17] = "fc_shrd17", 219 [FUNC_FC_SHRD18] = "fc_shrd18", 220 [FUNC_FC_SHRD19] = "fc_shrd19", 221 [FUNC_FC_SHRD20] = "fc_shrd20", 222 [FUNC_GPIO] = "gpio", 223 [FUNC_IB_TRG_a] = "ib_trig_a", 224 [FUNC_IB_TRG_b] = "ib_trig_b", 225 [FUNC_IB_TRG_c] = "ib_trig_c", 226 [FUNC_IRQ0] = "irq0", 227 [FUNC_IRQ_IN_a] = "irq_in_a", 228 [FUNC_IRQ_IN_b] = "irq_in_b", 229 [FUNC_IRQ_IN_c] = "irq_in_c", 230 [FUNC_IRQ0_IN] = "irq0_in", 231 [FUNC_IRQ_OUT_a] = "irq_out_a", 232 [FUNC_IRQ_OUT_b] = "irq_out_b", 233 [FUNC_IRQ_OUT_c] = "irq_out_c", 234 [FUNC_IRQ0_OUT] = "irq0_out", 235 [FUNC_IRQ1] = "irq1", 236 [FUNC_IRQ1_IN] = "irq1_in", 237 [FUNC_IRQ1_OUT] = "irq1_out", 238 [FUNC_EXT_IRQ] = "ext_irq", 239 [FUNC_MIIM] = "miim", 240 [FUNC_MIIM_a] = "miim_a", 241 [FUNC_MIIM_b] = "miim_b", 242 [FUNC_MIIM_c] = "miim_c", 243 [FUNC_MIIM_Sa] = "miim_slave_a", 244 [FUNC_MIIM_Sb] = "miim_slave_b", 245 [FUNC_PHY_LED] = "phy_led", 246 [FUNC_PCI_WAKE] = "pci_wake", 247 [FUNC_MD] = "md", 248 [FUNC_OB_TRG] = "ob_trig", 249 [FUNC_OB_TRG_a] = "ob_trig_a", 250 [FUNC_OB_TRG_b] = "ob_trig_b", 251 [FUNC_PTP0] = "ptp0", 252 [FUNC_PTP1] = "ptp1", 253 [FUNC_PTP2] = "ptp2", 254 [FUNC_PTP3] = "ptp3", 255 [FUNC_PTPSYNC_1] = "ptpsync_1", 256 [FUNC_PTPSYNC_2] = "ptpsync_2", 257 [FUNC_PTPSYNC_3] = "ptpsync_3", 258 [FUNC_PTPSYNC_4] = "ptpsync_4", 259 [FUNC_PTPSYNC_5] = "ptpsync_5", 260 [FUNC_PTPSYNC_6] = "ptpsync_6", 261 [FUNC_PTPSYNC_7] = "ptpsync_7", 262 [FUNC_PWM] = "pwm", 263 [FUNC_QSPI1] = "qspi1", 264 [FUNC_QSPI2] = "qspi2", 265 [FUNC_R] = "reserved", 266 [FUNC_RECO_a] = "reco_a", 267 [FUNC_RECO_b] = "reco_b", 268 [FUNC_RECO_CLK] = "reco_clk", 269 [FUNC_SD] = "sd", 270 [FUNC_SFP] = "sfp", 271 [FUNC_SFP_SD] = "sfp_sd", 272 [FUNC_SG0] = "sg0", 273 [FUNC_SG1] = "sg1", 274 [FUNC_SG2] = "sg2", 275 [FUNC_SGPIO_a] = "sgpio_a", 276 [FUNC_SGPIO_b] = "sgpio_b", 277 [FUNC_SI] = "si", 278 [FUNC_SI2] = "si2", 279 [FUNC_TACHO] = "tacho", 280 [FUNC_TACHO_a] = "tacho_a", 281 [FUNC_TACHO_b] = "tacho_b", 282 [FUNC_TWI] = "twi", 283 [FUNC_TWI2] = "twi2", 284 [FUNC_TWI3] = "twi3", 285 [FUNC_TWI_SCL_M] = "twi_scl_m", 286 [FUNC_TWI_SLC_GATE] = "twi_slc_gate", 287 [FUNC_TWI_SLC_GATE_AD] = "twi_slc_gate_ad", 288 [FUNC_USB_H_a] = "usb_host_a", 289 [FUNC_USB_H_b] = "usb_host_b", 290 [FUNC_USB_H_c] = "usb_host_c", 291 [FUNC_USB_S_a] = "usb_slave_a", 292 [FUNC_USB_S_b] = "usb_slave_b", 293 [FUNC_USB_S_c] = "usb_slave_c", 294 [FUNC_UART] = "uart", 295 [FUNC_UART2] = "uart2", 296 [FUNC_UART3] = "uart3", 297 [FUNC_PLL_STAT] = "pll_stat", 298 [FUNC_EMMC] = "emmc", 299 [FUNC_EMMC_SD] = "emmc_sd", 300 [FUNC_REF_CLK] = "ref_clk", 301 [FUNC_RCVRD_CLK] = "rcvrd_clk", 302 }; 303 304 struct ocelot_pmx_func { 305 const char **groups; 306 unsigned int ngroups; 307 }; 308 309 struct ocelot_pin_caps { 310 unsigned int pin; 311 unsigned char functions[OCELOT_FUNC_PER_PIN]; 312 unsigned char a_functions[OCELOT_FUNC_PER_PIN]; /* Additional functions */ 313 }; 314 315 struct ocelot_pinctrl { 316 struct device *dev; 317 struct pinctrl_dev *pctl; 318 struct gpio_chip gpio_chip; 319 struct regmap *map; 320 struct regmap *pincfg; 321 struct pinctrl_desc *desc; 322 struct ocelot_pmx_func func[FUNC_MAX]; 323 u8 stride; 324 }; 325 326 #define LUTON_P(p, f0, f1) \ 327 static struct ocelot_pin_caps luton_pin_##p = { \ 328 .pin = p, \ 329 .functions = { \ 330 FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_NONE, \ 331 }, \ 332 } 333 334 LUTON_P(0, SG0, NONE); 335 LUTON_P(1, SG0, NONE); 336 LUTON_P(2, SG0, NONE); 337 LUTON_P(3, SG0, NONE); 338 LUTON_P(4, TACHO, NONE); 339 LUTON_P(5, TWI, PHY_LED); 340 LUTON_P(6, TWI, PHY_LED); 341 LUTON_P(7, NONE, PHY_LED); 342 LUTON_P(8, EXT_IRQ, PHY_LED); 343 LUTON_P(9, EXT_IRQ, PHY_LED); 344 LUTON_P(10, SFP, PHY_LED); 345 LUTON_P(11, SFP, PHY_LED); 346 LUTON_P(12, SFP, PHY_LED); 347 LUTON_P(13, SFP, PHY_LED); 348 LUTON_P(14, SI, PHY_LED); 349 LUTON_P(15, SI, PHY_LED); 350 LUTON_P(16, SI, PHY_LED); 351 LUTON_P(17, SFP, PHY_LED); 352 LUTON_P(18, SFP, PHY_LED); 353 LUTON_P(19, SFP, PHY_LED); 354 LUTON_P(20, SFP, PHY_LED); 355 LUTON_P(21, SFP, PHY_LED); 356 LUTON_P(22, SFP, PHY_LED); 357 LUTON_P(23, SFP, PHY_LED); 358 LUTON_P(24, SFP, PHY_LED); 359 LUTON_P(25, SFP, PHY_LED); 360 LUTON_P(26, SFP, PHY_LED); 361 LUTON_P(27, SFP, PHY_LED); 362 LUTON_P(28, SFP, PHY_LED); 363 LUTON_P(29, PWM, NONE); 364 LUTON_P(30, UART, NONE); 365 LUTON_P(31, UART, NONE); 366 367 #define LUTON_PIN(n) { \ 368 .number = n, \ 369 .name = "GPIO_"#n, \ 370 .drv_data = &luton_pin_##n \ 371 } 372 373 static const struct pinctrl_pin_desc luton_pins[] = { 374 LUTON_PIN(0), 375 LUTON_PIN(1), 376 LUTON_PIN(2), 377 LUTON_PIN(3), 378 LUTON_PIN(4), 379 LUTON_PIN(5), 380 LUTON_PIN(6), 381 LUTON_PIN(7), 382 LUTON_PIN(8), 383 LUTON_PIN(9), 384 LUTON_PIN(10), 385 LUTON_PIN(11), 386 LUTON_PIN(12), 387 LUTON_PIN(13), 388 LUTON_PIN(14), 389 LUTON_PIN(15), 390 LUTON_PIN(16), 391 LUTON_PIN(17), 392 LUTON_PIN(18), 393 LUTON_PIN(19), 394 LUTON_PIN(20), 395 LUTON_PIN(21), 396 LUTON_PIN(22), 397 LUTON_PIN(23), 398 LUTON_PIN(24), 399 LUTON_PIN(25), 400 LUTON_PIN(26), 401 LUTON_PIN(27), 402 LUTON_PIN(28), 403 LUTON_PIN(29), 404 LUTON_PIN(30), 405 LUTON_PIN(31), 406 }; 407 408 #define SERVAL_P(p, f0, f1, f2) \ 409 static struct ocelot_pin_caps serval_pin_##p = { \ 410 .pin = p, \ 411 .functions = { \ 412 FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2, \ 413 }, \ 414 } 415 416 SERVAL_P(0, SG0, NONE, NONE); 417 SERVAL_P(1, SG0, NONE, NONE); 418 SERVAL_P(2, SG0, NONE, NONE); 419 SERVAL_P(3, SG0, NONE, NONE); 420 SERVAL_P(4, TACHO, NONE, NONE); 421 SERVAL_P(5, PWM, NONE, NONE); 422 SERVAL_P(6, TWI, NONE, NONE); 423 SERVAL_P(7, TWI, NONE, NONE); 424 SERVAL_P(8, SI, NONE, NONE); 425 SERVAL_P(9, SI, MD, NONE); 426 SERVAL_P(10, SI, MD, NONE); 427 SERVAL_P(11, SFP, MD, TWI_SCL_M); 428 SERVAL_P(12, SFP, MD, TWI_SCL_M); 429 SERVAL_P(13, SFP, UART2, TWI_SCL_M); 430 SERVAL_P(14, SFP, UART2, TWI_SCL_M); 431 SERVAL_P(15, SFP, PTP0, TWI_SCL_M); 432 SERVAL_P(16, SFP, PTP0, TWI_SCL_M); 433 SERVAL_P(17, SFP, PCI_WAKE, TWI_SCL_M); 434 SERVAL_P(18, SFP, NONE, TWI_SCL_M); 435 SERVAL_P(19, SFP, NONE, TWI_SCL_M); 436 SERVAL_P(20, SFP, NONE, TWI_SCL_M); 437 SERVAL_P(21, SFP, NONE, TWI_SCL_M); 438 SERVAL_P(22, NONE, NONE, NONE); 439 SERVAL_P(23, NONE, NONE, NONE); 440 SERVAL_P(24, NONE, NONE, NONE); 441 SERVAL_P(25, NONE, NONE, NONE); 442 SERVAL_P(26, UART, NONE, NONE); 443 SERVAL_P(27, UART, NONE, NONE); 444 SERVAL_P(28, IRQ0, NONE, NONE); 445 SERVAL_P(29, IRQ1, NONE, NONE); 446 SERVAL_P(30, PTP0, NONE, NONE); 447 SERVAL_P(31, PTP0, NONE, NONE); 448 449 #define SERVAL_PIN(n) { \ 450 .number = n, \ 451 .name = "GPIO_"#n, \ 452 .drv_data = &serval_pin_##n \ 453 } 454 455 static const struct pinctrl_pin_desc serval_pins[] = { 456 SERVAL_PIN(0), 457 SERVAL_PIN(1), 458 SERVAL_PIN(2), 459 SERVAL_PIN(3), 460 SERVAL_PIN(4), 461 SERVAL_PIN(5), 462 SERVAL_PIN(6), 463 SERVAL_PIN(7), 464 SERVAL_PIN(8), 465 SERVAL_PIN(9), 466 SERVAL_PIN(10), 467 SERVAL_PIN(11), 468 SERVAL_PIN(12), 469 SERVAL_PIN(13), 470 SERVAL_PIN(14), 471 SERVAL_PIN(15), 472 SERVAL_PIN(16), 473 SERVAL_PIN(17), 474 SERVAL_PIN(18), 475 SERVAL_PIN(19), 476 SERVAL_PIN(20), 477 SERVAL_PIN(21), 478 SERVAL_PIN(22), 479 SERVAL_PIN(23), 480 SERVAL_PIN(24), 481 SERVAL_PIN(25), 482 SERVAL_PIN(26), 483 SERVAL_PIN(27), 484 SERVAL_PIN(28), 485 SERVAL_PIN(29), 486 SERVAL_PIN(30), 487 SERVAL_PIN(31), 488 }; 489 490 #define OCELOT_P(p, f0, f1, f2) \ 491 static struct ocelot_pin_caps ocelot_pin_##p = { \ 492 .pin = p, \ 493 .functions = { \ 494 FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2, \ 495 }, \ 496 } 497 498 OCELOT_P(0, SG0, NONE, NONE); 499 OCELOT_P(1, SG0, NONE, NONE); 500 OCELOT_P(2, SG0, NONE, NONE); 501 OCELOT_P(3, SG0, NONE, NONE); 502 OCELOT_P(4, IRQ0_IN, IRQ0_OUT, TWI_SCL_M); 503 OCELOT_P(5, IRQ1_IN, IRQ1_OUT, PCI_WAKE); 504 OCELOT_P(6, UART, TWI_SCL_M, NONE); 505 OCELOT_P(7, UART, TWI_SCL_M, NONE); 506 OCELOT_P(8, SI, TWI_SCL_M, IRQ0_OUT); 507 OCELOT_P(9, SI, TWI_SCL_M, IRQ1_OUT); 508 OCELOT_P(10, PTP2, TWI_SCL_M, SFP); 509 OCELOT_P(11, PTP3, TWI_SCL_M, SFP); 510 OCELOT_P(12, UART2, TWI_SCL_M, SFP); 511 OCELOT_P(13, UART2, TWI_SCL_M, SFP); 512 OCELOT_P(14, MIIM, TWI_SCL_M, SFP); 513 OCELOT_P(15, MIIM, TWI_SCL_M, SFP); 514 OCELOT_P(16, TWI, NONE, SI); 515 OCELOT_P(17, TWI, TWI_SCL_M, SI); 516 OCELOT_P(18, PTP0, TWI_SCL_M, NONE); 517 OCELOT_P(19, PTP1, TWI_SCL_M, NONE); 518 OCELOT_P(20, RECO_CLK, TACHO, TWI_SCL_M); 519 OCELOT_P(21, RECO_CLK, PWM, TWI_SCL_M); 520 521 #define OCELOT_PIN(n) { \ 522 .number = n, \ 523 .name = "GPIO_"#n, \ 524 .drv_data = &ocelot_pin_##n \ 525 } 526 527 static const struct pinctrl_pin_desc ocelot_pins[] = { 528 OCELOT_PIN(0), 529 OCELOT_PIN(1), 530 OCELOT_PIN(2), 531 OCELOT_PIN(3), 532 OCELOT_PIN(4), 533 OCELOT_PIN(5), 534 OCELOT_PIN(6), 535 OCELOT_PIN(7), 536 OCELOT_PIN(8), 537 OCELOT_PIN(9), 538 OCELOT_PIN(10), 539 OCELOT_PIN(11), 540 OCELOT_PIN(12), 541 OCELOT_PIN(13), 542 OCELOT_PIN(14), 543 OCELOT_PIN(15), 544 OCELOT_PIN(16), 545 OCELOT_PIN(17), 546 OCELOT_PIN(18), 547 OCELOT_PIN(19), 548 OCELOT_PIN(20), 549 OCELOT_PIN(21), 550 }; 551 552 #define JAGUAR2_P(p, f0, f1) \ 553 static struct ocelot_pin_caps jaguar2_pin_##p = { \ 554 .pin = p, \ 555 .functions = { \ 556 FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_NONE \ 557 }, \ 558 } 559 560 JAGUAR2_P(0, SG0, NONE); 561 JAGUAR2_P(1, SG0, NONE); 562 JAGUAR2_P(2, SG0, NONE); 563 JAGUAR2_P(3, SG0, NONE); 564 JAGUAR2_P(4, SG1, NONE); 565 JAGUAR2_P(5, SG1, NONE); 566 JAGUAR2_P(6, IRQ0_IN, IRQ0_OUT); 567 JAGUAR2_P(7, IRQ1_IN, IRQ1_OUT); 568 JAGUAR2_P(8, PTP0, NONE); 569 JAGUAR2_P(9, PTP1, NONE); 570 JAGUAR2_P(10, UART, NONE); 571 JAGUAR2_P(11, UART, NONE); 572 JAGUAR2_P(12, SG1, NONE); 573 JAGUAR2_P(13, SG1, NONE); 574 JAGUAR2_P(14, TWI, TWI_SCL_M); 575 JAGUAR2_P(15, TWI, NONE); 576 JAGUAR2_P(16, SI, TWI_SCL_M); 577 JAGUAR2_P(17, SI, TWI_SCL_M); 578 JAGUAR2_P(18, SI, TWI_SCL_M); 579 JAGUAR2_P(19, PCI_WAKE, NONE); 580 JAGUAR2_P(20, IRQ0_OUT, TWI_SCL_M); 581 JAGUAR2_P(21, IRQ1_OUT, TWI_SCL_M); 582 JAGUAR2_P(22, TACHO, NONE); 583 JAGUAR2_P(23, PWM, NONE); 584 JAGUAR2_P(24, UART2, NONE); 585 JAGUAR2_P(25, UART2, SI); 586 JAGUAR2_P(26, PTP2, SI); 587 JAGUAR2_P(27, PTP3, SI); 588 JAGUAR2_P(28, TWI2, SI); 589 JAGUAR2_P(29, TWI2, SI); 590 JAGUAR2_P(30, SG2, SI); 591 JAGUAR2_P(31, SG2, SI); 592 JAGUAR2_P(32, SG2, SI); 593 JAGUAR2_P(33, SG2, SI); 594 JAGUAR2_P(34, NONE, TWI_SCL_M); 595 JAGUAR2_P(35, NONE, TWI_SCL_M); 596 JAGUAR2_P(36, NONE, TWI_SCL_M); 597 JAGUAR2_P(37, NONE, TWI_SCL_M); 598 JAGUAR2_P(38, NONE, TWI_SCL_M); 599 JAGUAR2_P(39, NONE, TWI_SCL_M); 600 JAGUAR2_P(40, NONE, TWI_SCL_M); 601 JAGUAR2_P(41, NONE, TWI_SCL_M); 602 JAGUAR2_P(42, NONE, TWI_SCL_M); 603 JAGUAR2_P(43, NONE, TWI_SCL_M); 604 JAGUAR2_P(44, NONE, SFP); 605 JAGUAR2_P(45, NONE, SFP); 606 JAGUAR2_P(46, NONE, SFP); 607 JAGUAR2_P(47, NONE, SFP); 608 JAGUAR2_P(48, SFP, NONE); 609 JAGUAR2_P(49, SFP, SI); 610 JAGUAR2_P(50, SFP, SI); 611 JAGUAR2_P(51, SFP, SI); 612 JAGUAR2_P(52, SFP, NONE); 613 JAGUAR2_P(53, SFP, NONE); 614 JAGUAR2_P(54, SFP, NONE); 615 JAGUAR2_P(55, SFP, NONE); 616 JAGUAR2_P(56, MIIM, SFP); 617 JAGUAR2_P(57, MIIM, SFP); 618 JAGUAR2_P(58, MIIM, SFP); 619 JAGUAR2_P(59, MIIM, SFP); 620 JAGUAR2_P(60, NONE, NONE); 621 JAGUAR2_P(61, NONE, NONE); 622 JAGUAR2_P(62, NONE, NONE); 623 JAGUAR2_P(63, NONE, NONE); 624 625 #define JAGUAR2_PIN(n) { \ 626 .number = n, \ 627 .name = "GPIO_"#n, \ 628 .drv_data = &jaguar2_pin_##n \ 629 } 630 631 static const struct pinctrl_pin_desc jaguar2_pins[] = { 632 JAGUAR2_PIN(0), 633 JAGUAR2_PIN(1), 634 JAGUAR2_PIN(2), 635 JAGUAR2_PIN(3), 636 JAGUAR2_PIN(4), 637 JAGUAR2_PIN(5), 638 JAGUAR2_PIN(6), 639 JAGUAR2_PIN(7), 640 JAGUAR2_PIN(8), 641 JAGUAR2_PIN(9), 642 JAGUAR2_PIN(10), 643 JAGUAR2_PIN(11), 644 JAGUAR2_PIN(12), 645 JAGUAR2_PIN(13), 646 JAGUAR2_PIN(14), 647 JAGUAR2_PIN(15), 648 JAGUAR2_PIN(16), 649 JAGUAR2_PIN(17), 650 JAGUAR2_PIN(18), 651 JAGUAR2_PIN(19), 652 JAGUAR2_PIN(20), 653 JAGUAR2_PIN(21), 654 JAGUAR2_PIN(22), 655 JAGUAR2_PIN(23), 656 JAGUAR2_PIN(24), 657 JAGUAR2_PIN(25), 658 JAGUAR2_PIN(26), 659 JAGUAR2_PIN(27), 660 JAGUAR2_PIN(28), 661 JAGUAR2_PIN(29), 662 JAGUAR2_PIN(30), 663 JAGUAR2_PIN(31), 664 JAGUAR2_PIN(32), 665 JAGUAR2_PIN(33), 666 JAGUAR2_PIN(34), 667 JAGUAR2_PIN(35), 668 JAGUAR2_PIN(36), 669 JAGUAR2_PIN(37), 670 JAGUAR2_PIN(38), 671 JAGUAR2_PIN(39), 672 JAGUAR2_PIN(40), 673 JAGUAR2_PIN(41), 674 JAGUAR2_PIN(42), 675 JAGUAR2_PIN(43), 676 JAGUAR2_PIN(44), 677 JAGUAR2_PIN(45), 678 JAGUAR2_PIN(46), 679 JAGUAR2_PIN(47), 680 JAGUAR2_PIN(48), 681 JAGUAR2_PIN(49), 682 JAGUAR2_PIN(50), 683 JAGUAR2_PIN(51), 684 JAGUAR2_PIN(52), 685 JAGUAR2_PIN(53), 686 JAGUAR2_PIN(54), 687 JAGUAR2_PIN(55), 688 JAGUAR2_PIN(56), 689 JAGUAR2_PIN(57), 690 JAGUAR2_PIN(58), 691 JAGUAR2_PIN(59), 692 JAGUAR2_PIN(60), 693 JAGUAR2_PIN(61), 694 JAGUAR2_PIN(62), 695 JAGUAR2_PIN(63), 696 }; 697 698 #define SPARX5_P(p, f0, f1, f2) \ 699 static struct ocelot_pin_caps sparx5_pin_##p = { \ 700 .pin = p, \ 701 .functions = { \ 702 FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2 \ 703 }, \ 704 } 705 706 SPARX5_P(0, SG0, PLL_STAT, NONE); 707 SPARX5_P(1, SG0, NONE, NONE); 708 SPARX5_P(2, SG0, NONE, NONE); 709 SPARX5_P(3, SG0, NONE, NONE); 710 SPARX5_P(4, SG1, NONE, NONE); 711 SPARX5_P(5, SG1, NONE, NONE); 712 SPARX5_P(6, IRQ0_IN, IRQ0_OUT, SFP); 713 SPARX5_P(7, IRQ1_IN, IRQ1_OUT, SFP); 714 SPARX5_P(8, PTP0, NONE, SFP); 715 SPARX5_P(9, PTP1, SFP, TWI_SCL_M); 716 SPARX5_P(10, UART, NONE, NONE); 717 SPARX5_P(11, UART, NONE, NONE); 718 SPARX5_P(12, SG1, NONE, NONE); 719 SPARX5_P(13, SG1, NONE, NONE); 720 SPARX5_P(14, TWI, TWI_SCL_M, NONE); 721 SPARX5_P(15, TWI, NONE, NONE); 722 SPARX5_P(16, SI, TWI_SCL_M, SFP); 723 SPARX5_P(17, SI, TWI_SCL_M, SFP); 724 SPARX5_P(18, SI, TWI_SCL_M, SFP); 725 SPARX5_P(19, PCI_WAKE, TWI_SCL_M, SFP); 726 SPARX5_P(20, IRQ0_OUT, TWI_SCL_M, SFP); 727 SPARX5_P(21, IRQ1_OUT, TACHO, SFP); 728 SPARX5_P(22, TACHO, IRQ0_OUT, TWI_SCL_M); 729 SPARX5_P(23, PWM, UART3, TWI_SCL_M); 730 SPARX5_P(24, PTP2, UART3, TWI_SCL_M); 731 SPARX5_P(25, PTP3, SI, TWI_SCL_M); 732 SPARX5_P(26, UART2, SI, TWI_SCL_M); 733 SPARX5_P(27, UART2, SI, TWI_SCL_M); 734 SPARX5_P(28, TWI2, SI, SFP); 735 SPARX5_P(29, TWI2, SI, SFP); 736 SPARX5_P(30, SG2, SI, PWM); 737 SPARX5_P(31, SG2, SI, TWI_SCL_M); 738 SPARX5_P(32, SG2, SI, TWI_SCL_M); 739 SPARX5_P(33, SG2, SI, SFP); 740 SPARX5_P(34, NONE, TWI_SCL_M, EMMC); 741 SPARX5_P(35, SFP, TWI_SCL_M, EMMC); 742 SPARX5_P(36, SFP, TWI_SCL_M, EMMC); 743 SPARX5_P(37, SFP, NONE, EMMC); 744 SPARX5_P(38, NONE, TWI_SCL_M, EMMC); 745 SPARX5_P(39, SI2, TWI_SCL_M, EMMC); 746 SPARX5_P(40, SI2, TWI_SCL_M, EMMC); 747 SPARX5_P(41, SI2, TWI_SCL_M, EMMC); 748 SPARX5_P(42, SI2, TWI_SCL_M, EMMC); 749 SPARX5_P(43, SI2, TWI_SCL_M, EMMC); 750 SPARX5_P(44, SI, SFP, EMMC); 751 SPARX5_P(45, SI, SFP, EMMC); 752 SPARX5_P(46, NONE, SFP, EMMC); 753 SPARX5_P(47, NONE, SFP, EMMC); 754 SPARX5_P(48, TWI3, SI, SFP); 755 SPARX5_P(49, TWI3, NONE, SFP); 756 SPARX5_P(50, SFP, NONE, TWI_SCL_M); 757 SPARX5_P(51, SFP, SI, TWI_SCL_M); 758 SPARX5_P(52, SFP, MIIM, TWI_SCL_M); 759 SPARX5_P(53, SFP, MIIM, TWI_SCL_M); 760 SPARX5_P(54, SFP, PTP2, TWI_SCL_M); 761 SPARX5_P(55, SFP, PTP3, PCI_WAKE); 762 SPARX5_P(56, MIIM, SFP, TWI_SCL_M); 763 SPARX5_P(57, MIIM, SFP, TWI_SCL_M); 764 SPARX5_P(58, MIIM, SFP, TWI_SCL_M); 765 SPARX5_P(59, MIIM, SFP, NONE); 766 SPARX5_P(60, RECO_CLK, NONE, NONE); 767 SPARX5_P(61, RECO_CLK, NONE, NONE); 768 SPARX5_P(62, RECO_CLK, PLL_STAT, NONE); 769 SPARX5_P(63, RECO_CLK, NONE, NONE); 770 771 #define SPARX5_PIN(n) { \ 772 .number = n, \ 773 .name = "GPIO_"#n, \ 774 .drv_data = &sparx5_pin_##n \ 775 } 776 777 static const struct pinctrl_pin_desc sparx5_pins[] = { 778 SPARX5_PIN(0), 779 SPARX5_PIN(1), 780 SPARX5_PIN(2), 781 SPARX5_PIN(3), 782 SPARX5_PIN(4), 783 SPARX5_PIN(5), 784 SPARX5_PIN(6), 785 SPARX5_PIN(7), 786 SPARX5_PIN(8), 787 SPARX5_PIN(9), 788 SPARX5_PIN(10), 789 SPARX5_PIN(11), 790 SPARX5_PIN(12), 791 SPARX5_PIN(13), 792 SPARX5_PIN(14), 793 SPARX5_PIN(15), 794 SPARX5_PIN(16), 795 SPARX5_PIN(17), 796 SPARX5_PIN(18), 797 SPARX5_PIN(19), 798 SPARX5_PIN(20), 799 SPARX5_PIN(21), 800 SPARX5_PIN(22), 801 SPARX5_PIN(23), 802 SPARX5_PIN(24), 803 SPARX5_PIN(25), 804 SPARX5_PIN(26), 805 SPARX5_PIN(27), 806 SPARX5_PIN(28), 807 SPARX5_PIN(29), 808 SPARX5_PIN(30), 809 SPARX5_PIN(31), 810 SPARX5_PIN(32), 811 SPARX5_PIN(33), 812 SPARX5_PIN(34), 813 SPARX5_PIN(35), 814 SPARX5_PIN(36), 815 SPARX5_PIN(37), 816 SPARX5_PIN(38), 817 SPARX5_PIN(39), 818 SPARX5_PIN(40), 819 SPARX5_PIN(41), 820 SPARX5_PIN(42), 821 SPARX5_PIN(43), 822 SPARX5_PIN(44), 823 SPARX5_PIN(45), 824 SPARX5_PIN(46), 825 SPARX5_PIN(47), 826 SPARX5_PIN(48), 827 SPARX5_PIN(49), 828 SPARX5_PIN(50), 829 SPARX5_PIN(51), 830 SPARX5_PIN(52), 831 SPARX5_PIN(53), 832 SPARX5_PIN(54), 833 SPARX5_PIN(55), 834 SPARX5_PIN(56), 835 SPARX5_PIN(57), 836 SPARX5_PIN(58), 837 SPARX5_PIN(59), 838 SPARX5_PIN(60), 839 SPARX5_PIN(61), 840 SPARX5_PIN(62), 841 SPARX5_PIN(63), 842 }; 843 844 #define LAN966X_P(p, f0, f1, f2, f3, f4, f5, f6, f7) \ 845 static struct ocelot_pin_caps lan966x_pin_##p = { \ 846 .pin = p, \ 847 .functions = { \ 848 FUNC_##f0, FUNC_##f1, FUNC_##f2, \ 849 FUNC_##f3 \ 850 }, \ 851 .a_functions = { \ 852 FUNC_##f4, FUNC_##f5, FUNC_##f6, \ 853 FUNC_##f7 \ 854 }, \ 855 } 856 857 /* Pinmuxing table taken from data sheet */ 858 /* Pin FUNC0 FUNC1 FUNC2 FUNC3 FUNC4 FUNC5 FUNC6 FUNC7 */ 859 LAN966X_P(0, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 860 LAN966X_P(1, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 861 LAN966X_P(2, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 862 LAN966X_P(3, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 863 LAN966X_P(4, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 864 LAN966X_P(5, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 865 LAN966X_P(6, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 866 LAN966X_P(7, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 867 LAN966X_P(8, GPIO, FC0_a, USB_H_b, NONE, USB_S_b, NONE, NONE, R); 868 LAN966X_P(9, GPIO, FC0_a, USB_H_b, NONE, NONE, NONE, NONE, R); 869 LAN966X_P(10, GPIO, FC0_a, NONE, NONE, NONE, NONE, NONE, R); 870 LAN966X_P(11, GPIO, FC1_a, NONE, NONE, NONE, NONE, NONE, R); 871 LAN966X_P(12, GPIO, FC1_a, NONE, NONE, NONE, NONE, NONE, R); 872 LAN966X_P(13, GPIO, FC1_a, NONE, NONE, NONE, NONE, NONE, R); 873 LAN966X_P(14, GPIO, FC2_a, NONE, NONE, NONE, NONE, NONE, R); 874 LAN966X_P(15, GPIO, FC2_a, NONE, NONE, NONE, NONE, NONE, R); 875 LAN966X_P(16, GPIO, FC2_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, IRQ_OUT_c, R); 876 LAN966X_P(17, GPIO, FC3_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, IRQ_OUT_c, R); 877 LAN966X_P(18, GPIO, FC3_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, IRQ_OUT_c, R); 878 LAN966X_P(19, GPIO, FC3_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, IRQ_OUT_c, R); 879 LAN966X_P(20, GPIO, FC4_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, NONE, R); 880 LAN966X_P(21, GPIO, FC4_a, NONE, NONE, OB_TRG_a, NONE, NONE, R); 881 LAN966X_P(22, GPIO, FC4_a, NONE, NONE, OB_TRG_a, NONE, NONE, R); 882 LAN966X_P(23, GPIO, NONE, NONE, NONE, OB_TRG_a, NONE, NONE, R); 883 LAN966X_P(24, GPIO, FC0_b, IB_TRG_a, USB_H_c, OB_TRG_a, IRQ_IN_c, TACHO_a, R); 884 LAN966X_P(25, GPIO, FC0_b, IB_TRG_a, USB_H_c, OB_TRG_a, IRQ_OUT_c, SFP_SD, R); 885 LAN966X_P(26, GPIO, FC0_b, IB_TRG_a, USB_S_c, OB_TRG_a, CAN0_a, SFP_SD, R); 886 LAN966X_P(27, GPIO, NONE, NONE, NONE, OB_TRG_a, CAN0_a, NONE, R); 887 LAN966X_P(28, GPIO, MIIM_a, NONE, NONE, OB_TRG_a, IRQ_OUT_c, SFP_SD, R); 888 LAN966X_P(29, GPIO, MIIM_a, NONE, NONE, OB_TRG_a, NONE, NONE, R); 889 LAN966X_P(30, GPIO, FC3_c, CAN1, NONE, OB_TRG, RECO_b, NONE, R); 890 LAN966X_P(31, GPIO, FC3_c, CAN1, NONE, OB_TRG, RECO_b, NONE, R); 891 LAN966X_P(32, GPIO, FC3_c, NONE, SGPIO_a, NONE, MIIM_Sa, NONE, R); 892 LAN966X_P(33, GPIO, FC1_b, NONE, SGPIO_a, NONE, MIIM_Sa, MIIM_b, R); 893 LAN966X_P(34, GPIO, FC1_b, NONE, SGPIO_a, NONE, MIIM_Sa, MIIM_b, R); 894 LAN966X_P(35, GPIO, FC1_b, NONE, SGPIO_a, CAN0_b, NONE, NONE, R); 895 LAN966X_P(36, GPIO, NONE, PTPSYNC_1, NONE, CAN0_b, NONE, NONE, R); 896 LAN966X_P(37, GPIO, FC_SHRD0, PTPSYNC_2, TWI_SLC_GATE_AD, NONE, NONE, NONE, R); 897 LAN966X_P(38, GPIO, NONE, PTPSYNC_3, NONE, NONE, NONE, NONE, R); 898 LAN966X_P(39, GPIO, NONE, PTPSYNC_4, NONE, NONE, NONE, NONE, R); 899 LAN966X_P(40, GPIO, FC_SHRD1, PTPSYNC_5, NONE, NONE, NONE, NONE, R); 900 LAN966X_P(41, GPIO, FC_SHRD2, PTPSYNC_6, TWI_SLC_GATE_AD, NONE, NONE, NONE, R); 901 LAN966X_P(42, GPIO, FC_SHRD3, PTPSYNC_7, TWI_SLC_GATE_AD, NONE, NONE, NONE, R); 902 LAN966X_P(43, GPIO, FC2_b, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, RECO_a, IRQ_IN_a, R); 903 LAN966X_P(44, GPIO, FC2_b, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, RECO_a, IRQ_IN_a, R); 904 LAN966X_P(45, GPIO, FC2_b, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, NONE, IRQ_IN_a, R); 905 LAN966X_P(46, GPIO, FC1_c, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, FC_SHRD4, IRQ_IN_a, R); 906 LAN966X_P(47, GPIO, FC1_c, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, FC_SHRD5, IRQ_IN_a, R); 907 LAN966X_P(48, GPIO, FC1_c, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, FC_SHRD6, IRQ_IN_a, R); 908 LAN966X_P(49, GPIO, FC_SHRD7, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, TWI_SLC_GATE, IRQ_IN_a, R); 909 LAN966X_P(50, GPIO, FC_SHRD16, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, TWI_SLC_GATE, NONE, R); 910 LAN966X_P(51, GPIO, FC3_b, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, NONE, IRQ_IN_b, R); 911 LAN966X_P(52, GPIO, FC3_b, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, TACHO_b, IRQ_IN_b, R); 912 LAN966X_P(53, GPIO, FC3_b, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, NONE, IRQ_IN_b, R); 913 LAN966X_P(54, GPIO, FC_SHRD8, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, TWI_SLC_GATE, IRQ_IN_b, R); 914 LAN966X_P(55, GPIO, FC_SHRD9, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, TWI_SLC_GATE, IRQ_IN_b, R); 915 LAN966X_P(56, GPIO, FC4_b, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, FC_SHRD10, IRQ_IN_b, R); 916 LAN966X_P(57, GPIO, FC4_b, TWI_SLC_GATE, IB_TRG_c, IRQ_OUT_b, FC_SHRD11, IRQ_IN_b, R); 917 LAN966X_P(58, GPIO, FC4_b, TWI_SLC_GATE, IB_TRG_c, IRQ_OUT_b, FC_SHRD12, IRQ_IN_b, R); 918 LAN966X_P(59, GPIO, QSPI1, MIIM_c, NONE, NONE, MIIM_Sb, NONE, R); 919 LAN966X_P(60, GPIO, QSPI1, MIIM_c, NONE, NONE, MIIM_Sb, NONE, R); 920 LAN966X_P(61, GPIO, QSPI1, NONE, SGPIO_b, FC0_c, MIIM_Sb, NONE, R); 921 LAN966X_P(62, GPIO, QSPI1, FC_SHRD13, SGPIO_b, FC0_c, TWI_SLC_GATE, SFP_SD, R); 922 LAN966X_P(63, GPIO, QSPI1, FC_SHRD14, SGPIO_b, FC0_c, TWI_SLC_GATE, SFP_SD, R); 923 LAN966X_P(64, GPIO, QSPI1, FC4_c, SGPIO_b, FC_SHRD15, TWI_SLC_GATE, SFP_SD, R); 924 LAN966X_P(65, GPIO, USB_H_a, FC4_c, NONE, IRQ_OUT_c, TWI_SLC_GATE_AD, NONE, R); 925 LAN966X_P(66, GPIO, USB_H_a, FC4_c, USB_S_a, IRQ_OUT_c, IRQ_IN_c, NONE, R); 926 LAN966X_P(67, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R); 927 LAN966X_P(68, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R); 928 LAN966X_P(69, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R); 929 LAN966X_P(70, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R); 930 LAN966X_P(71, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R); 931 LAN966X_P(72, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R); 932 LAN966X_P(73, GPIO, EMMC, NONE, NONE, SD, NONE, NONE, R); 933 LAN966X_P(74, GPIO, EMMC, NONE, FC_SHRD17, SD, TWI_SLC_GATE, NONE, R); 934 LAN966X_P(75, GPIO, EMMC, NONE, FC_SHRD18, SD, TWI_SLC_GATE, NONE, R); 935 LAN966X_P(76, GPIO, EMMC, NONE, FC_SHRD19, SD, TWI_SLC_GATE, NONE, R); 936 LAN966X_P(77, GPIO, EMMC_SD, NONE, FC_SHRD20, NONE, TWI_SLC_GATE, NONE, R); 937 938 #define LAN966X_PIN(n) { \ 939 .number = n, \ 940 .name = "GPIO_"#n, \ 941 .drv_data = &lan966x_pin_##n \ 942 } 943 944 static const struct pinctrl_pin_desc lan966x_pins[] = { 945 LAN966X_PIN(0), 946 LAN966X_PIN(1), 947 LAN966X_PIN(2), 948 LAN966X_PIN(3), 949 LAN966X_PIN(4), 950 LAN966X_PIN(5), 951 LAN966X_PIN(6), 952 LAN966X_PIN(7), 953 LAN966X_PIN(8), 954 LAN966X_PIN(9), 955 LAN966X_PIN(10), 956 LAN966X_PIN(11), 957 LAN966X_PIN(12), 958 LAN966X_PIN(13), 959 LAN966X_PIN(14), 960 LAN966X_PIN(15), 961 LAN966X_PIN(16), 962 LAN966X_PIN(17), 963 LAN966X_PIN(18), 964 LAN966X_PIN(19), 965 LAN966X_PIN(20), 966 LAN966X_PIN(21), 967 LAN966X_PIN(22), 968 LAN966X_PIN(23), 969 LAN966X_PIN(24), 970 LAN966X_PIN(25), 971 LAN966X_PIN(26), 972 LAN966X_PIN(27), 973 LAN966X_PIN(28), 974 LAN966X_PIN(29), 975 LAN966X_PIN(30), 976 LAN966X_PIN(31), 977 LAN966X_PIN(32), 978 LAN966X_PIN(33), 979 LAN966X_PIN(34), 980 LAN966X_PIN(35), 981 LAN966X_PIN(36), 982 LAN966X_PIN(37), 983 LAN966X_PIN(38), 984 LAN966X_PIN(39), 985 LAN966X_PIN(40), 986 LAN966X_PIN(41), 987 LAN966X_PIN(42), 988 LAN966X_PIN(43), 989 LAN966X_PIN(44), 990 LAN966X_PIN(45), 991 LAN966X_PIN(46), 992 LAN966X_PIN(47), 993 LAN966X_PIN(48), 994 LAN966X_PIN(49), 995 LAN966X_PIN(50), 996 LAN966X_PIN(51), 997 LAN966X_PIN(52), 998 LAN966X_PIN(53), 999 LAN966X_PIN(54), 1000 LAN966X_PIN(55), 1001 LAN966X_PIN(56), 1002 LAN966X_PIN(57), 1003 LAN966X_PIN(58), 1004 LAN966X_PIN(59), 1005 LAN966X_PIN(60), 1006 LAN966X_PIN(61), 1007 LAN966X_PIN(62), 1008 LAN966X_PIN(63), 1009 LAN966X_PIN(64), 1010 LAN966X_PIN(65), 1011 LAN966X_PIN(66), 1012 LAN966X_PIN(67), 1013 LAN966X_PIN(68), 1014 LAN966X_PIN(69), 1015 LAN966X_PIN(70), 1016 LAN966X_PIN(71), 1017 LAN966X_PIN(72), 1018 LAN966X_PIN(73), 1019 LAN966X_PIN(74), 1020 LAN966X_PIN(75), 1021 LAN966X_PIN(76), 1022 LAN966X_PIN(77), 1023 }; 1024 1025 static int ocelot_get_functions_count(struct pinctrl_dev *pctldev) 1026 { 1027 return ARRAY_SIZE(ocelot_function_names); 1028 } 1029 1030 static const char *ocelot_get_function_name(struct pinctrl_dev *pctldev, 1031 unsigned int function) 1032 { 1033 return ocelot_function_names[function]; 1034 } 1035 1036 static int ocelot_get_function_groups(struct pinctrl_dev *pctldev, 1037 unsigned int function, 1038 const char *const **groups, 1039 unsigned *const num_groups) 1040 { 1041 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1042 1043 *groups = info->func[function].groups; 1044 *num_groups = info->func[function].ngroups; 1045 1046 return 0; 1047 } 1048 1049 static int ocelot_pin_function_idx(struct ocelot_pinctrl *info, 1050 unsigned int pin, unsigned int function) 1051 { 1052 struct ocelot_pin_caps *p = info->desc->pins[pin].drv_data; 1053 int i; 1054 1055 for (i = 0; i < OCELOT_FUNC_PER_PIN; i++) { 1056 if (function == p->functions[i]) 1057 return i; 1058 1059 if (function == p->a_functions[i]) 1060 return i + OCELOT_FUNC_PER_PIN; 1061 } 1062 1063 return -1; 1064 } 1065 1066 #define REG_ALT(msb, info, p) (OCELOT_GPIO_ALT0 * (info)->stride + 4 * ((msb) + ((info)->stride * ((p) / 32)))) 1067 1068 static int ocelot_pinmux_set_mux(struct pinctrl_dev *pctldev, 1069 unsigned int selector, unsigned int group) 1070 { 1071 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1072 struct ocelot_pin_caps *pin = info->desc->pins[group].drv_data; 1073 unsigned int p = pin->pin % 32; 1074 int f; 1075 1076 f = ocelot_pin_function_idx(info, group, selector); 1077 if (f < 0) 1078 return -EINVAL; 1079 1080 /* 1081 * f is encoded on two bits. 1082 * bit 0 of f goes in BIT(pin) of ALT[0], bit 1 of f goes in BIT(pin) of 1083 * ALT[1] 1084 * This is racy because both registers can't be updated at the same time 1085 * but it doesn't matter much for now. 1086 * Note: ALT0/ALT1 are organized specially for 64 gpio targets 1087 */ 1088 regmap_update_bits(info->map, REG_ALT(0, info, pin->pin), 1089 BIT(p), f << p); 1090 regmap_update_bits(info->map, REG_ALT(1, info, pin->pin), 1091 BIT(p), f << (p - 1)); 1092 1093 return 0; 1094 } 1095 1096 static int lan966x_pinmux_set_mux(struct pinctrl_dev *pctldev, 1097 unsigned int selector, unsigned int group) 1098 { 1099 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1100 struct ocelot_pin_caps *pin = info->desc->pins[group].drv_data; 1101 unsigned int p = pin->pin % 32; 1102 int f; 1103 1104 f = ocelot_pin_function_idx(info, group, selector); 1105 if (f < 0) 1106 return -EINVAL; 1107 1108 /* 1109 * f is encoded on three bits. 1110 * bit 0 of f goes in BIT(pin) of ALT[0], bit 1 of f goes in BIT(pin) of 1111 * ALT[1], bit 2 of f goes in BIT(pin) of ALT[2] 1112 * This is racy because three registers can't be updated at the same time 1113 * but it doesn't matter much for now. 1114 * Note: ALT0/ALT1/ALT2 are organized specially for 78 gpio targets 1115 */ 1116 regmap_update_bits(info->map, REG_ALT(0, info, pin->pin), 1117 BIT(p), f << p); 1118 regmap_update_bits(info->map, REG_ALT(1, info, pin->pin), 1119 BIT(p), (f >> 1) << p); 1120 regmap_update_bits(info->map, REG_ALT(2, info, pin->pin), 1121 BIT(p), (f >> 2) << p); 1122 1123 return 0; 1124 } 1125 1126 #define REG(r, info, p) ((r) * (info)->stride + (4 * ((p) / 32))) 1127 1128 static int ocelot_gpio_set_direction(struct pinctrl_dev *pctldev, 1129 struct pinctrl_gpio_range *range, 1130 unsigned int pin, bool input) 1131 { 1132 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1133 unsigned int p = pin % 32; 1134 1135 regmap_update_bits(info->map, REG(OCELOT_GPIO_OE, info, pin), BIT(p), 1136 input ? 0 : BIT(p)); 1137 1138 return 0; 1139 } 1140 1141 static int ocelot_gpio_request_enable(struct pinctrl_dev *pctldev, 1142 struct pinctrl_gpio_range *range, 1143 unsigned int offset) 1144 { 1145 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1146 unsigned int p = offset % 32; 1147 1148 regmap_update_bits(info->map, REG_ALT(0, info, offset), 1149 BIT(p), 0); 1150 regmap_update_bits(info->map, REG_ALT(1, info, offset), 1151 BIT(p), 0); 1152 1153 return 0; 1154 } 1155 1156 static int lan966x_gpio_request_enable(struct pinctrl_dev *pctldev, 1157 struct pinctrl_gpio_range *range, 1158 unsigned int offset) 1159 { 1160 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1161 unsigned int p = offset % 32; 1162 1163 regmap_update_bits(info->map, REG_ALT(0, info, offset), 1164 BIT(p), 0); 1165 regmap_update_bits(info->map, REG_ALT(1, info, offset), 1166 BIT(p), 0); 1167 regmap_update_bits(info->map, REG_ALT(2, info, offset), 1168 BIT(p), 0); 1169 1170 return 0; 1171 } 1172 1173 static const struct pinmux_ops ocelot_pmx_ops = { 1174 .get_functions_count = ocelot_get_functions_count, 1175 .get_function_name = ocelot_get_function_name, 1176 .get_function_groups = ocelot_get_function_groups, 1177 .set_mux = ocelot_pinmux_set_mux, 1178 .gpio_set_direction = ocelot_gpio_set_direction, 1179 .gpio_request_enable = ocelot_gpio_request_enable, 1180 }; 1181 1182 static const struct pinmux_ops lan966x_pmx_ops = { 1183 .get_functions_count = ocelot_get_functions_count, 1184 .get_function_name = ocelot_get_function_name, 1185 .get_function_groups = ocelot_get_function_groups, 1186 .set_mux = lan966x_pinmux_set_mux, 1187 .gpio_set_direction = ocelot_gpio_set_direction, 1188 .gpio_request_enable = lan966x_gpio_request_enable, 1189 }; 1190 1191 static int ocelot_pctl_get_groups_count(struct pinctrl_dev *pctldev) 1192 { 1193 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1194 1195 return info->desc->npins; 1196 } 1197 1198 static const char *ocelot_pctl_get_group_name(struct pinctrl_dev *pctldev, 1199 unsigned int group) 1200 { 1201 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1202 1203 return info->desc->pins[group].name; 1204 } 1205 1206 static int ocelot_pctl_get_group_pins(struct pinctrl_dev *pctldev, 1207 unsigned int group, 1208 const unsigned int **pins, 1209 unsigned int *num_pins) 1210 { 1211 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1212 1213 *pins = &info->desc->pins[group].number; 1214 *num_pins = 1; 1215 1216 return 0; 1217 } 1218 1219 static int ocelot_hw_get_value(struct ocelot_pinctrl *info, 1220 unsigned int pin, 1221 unsigned int reg, 1222 int *val) 1223 { 1224 int ret = -EOPNOTSUPP; 1225 1226 if (info->pincfg) { 1227 u32 regcfg; 1228 1229 ret = regmap_read(info->pincfg, pin, ®cfg); 1230 if (ret) 1231 return ret; 1232 1233 ret = 0; 1234 switch (reg) { 1235 case PINCONF_BIAS: 1236 *val = regcfg & BIAS_BITS; 1237 break; 1238 1239 case PINCONF_SCHMITT: 1240 *val = regcfg & SCHMITT_BIT; 1241 break; 1242 1243 case PINCONF_DRIVE_STRENGTH: 1244 *val = regcfg & DRIVE_BITS; 1245 break; 1246 1247 default: 1248 ret = -EOPNOTSUPP; 1249 break; 1250 } 1251 } 1252 return ret; 1253 } 1254 1255 static int ocelot_pincfg_clrsetbits(struct ocelot_pinctrl *info, u32 regaddr, 1256 u32 clrbits, u32 setbits) 1257 { 1258 u32 val; 1259 int ret; 1260 1261 ret = regmap_read(info->pincfg, regaddr, &val); 1262 if (ret) 1263 return ret; 1264 1265 val &= ~clrbits; 1266 val |= setbits; 1267 1268 ret = regmap_write(info->pincfg, regaddr, val); 1269 1270 return ret; 1271 } 1272 1273 static int ocelot_hw_set_value(struct ocelot_pinctrl *info, 1274 unsigned int pin, 1275 unsigned int reg, 1276 int val) 1277 { 1278 int ret = -EOPNOTSUPP; 1279 1280 if (info->pincfg) { 1281 1282 ret = 0; 1283 switch (reg) { 1284 case PINCONF_BIAS: 1285 ret = ocelot_pincfg_clrsetbits(info, pin, BIAS_BITS, 1286 val); 1287 break; 1288 1289 case PINCONF_SCHMITT: 1290 ret = ocelot_pincfg_clrsetbits(info, pin, SCHMITT_BIT, 1291 val); 1292 break; 1293 1294 case PINCONF_DRIVE_STRENGTH: 1295 if (val <= 3) 1296 ret = ocelot_pincfg_clrsetbits(info, pin, 1297 DRIVE_BITS, val); 1298 else 1299 ret = -EINVAL; 1300 break; 1301 1302 default: 1303 ret = -EOPNOTSUPP; 1304 break; 1305 } 1306 } 1307 return ret; 1308 } 1309 1310 static int ocelot_pinconf_get(struct pinctrl_dev *pctldev, 1311 unsigned int pin, unsigned long *config) 1312 { 1313 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1314 u32 param = pinconf_to_config_param(*config); 1315 int val, err; 1316 1317 switch (param) { 1318 case PIN_CONFIG_BIAS_DISABLE: 1319 case PIN_CONFIG_BIAS_PULL_UP: 1320 case PIN_CONFIG_BIAS_PULL_DOWN: 1321 err = ocelot_hw_get_value(info, pin, PINCONF_BIAS, &val); 1322 if (err) 1323 return err; 1324 if (param == PIN_CONFIG_BIAS_DISABLE) 1325 val = (val == 0); 1326 else if (param == PIN_CONFIG_BIAS_PULL_DOWN) 1327 val = (val & BIAS_PD_BIT ? true : false); 1328 else /* PIN_CONFIG_BIAS_PULL_UP */ 1329 val = (val & BIAS_PU_BIT ? true : false); 1330 break; 1331 1332 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 1333 err = ocelot_hw_get_value(info, pin, PINCONF_SCHMITT, &val); 1334 if (err) 1335 return err; 1336 1337 val = (val & SCHMITT_BIT ? true : false); 1338 break; 1339 1340 case PIN_CONFIG_DRIVE_STRENGTH: 1341 err = ocelot_hw_get_value(info, pin, PINCONF_DRIVE_STRENGTH, 1342 &val); 1343 if (err) 1344 return err; 1345 break; 1346 1347 case PIN_CONFIG_OUTPUT: 1348 err = regmap_read(info->map, REG(OCELOT_GPIO_OUT, info, pin), 1349 &val); 1350 if (err) 1351 return err; 1352 val = !!(val & BIT(pin % 32)); 1353 break; 1354 1355 case PIN_CONFIG_INPUT_ENABLE: 1356 case PIN_CONFIG_OUTPUT_ENABLE: 1357 err = regmap_read(info->map, REG(OCELOT_GPIO_OE, info, pin), 1358 &val); 1359 if (err) 1360 return err; 1361 val = val & BIT(pin % 32); 1362 if (param == PIN_CONFIG_OUTPUT_ENABLE) 1363 val = !!val; 1364 else 1365 val = !val; 1366 break; 1367 1368 default: 1369 return -EOPNOTSUPP; 1370 } 1371 1372 *config = pinconf_to_config_packed(param, val); 1373 1374 return 0; 1375 } 1376 1377 static int ocelot_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 1378 unsigned long *configs, unsigned int num_configs) 1379 { 1380 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1381 u32 param, arg, p; 1382 int cfg, err = 0; 1383 1384 for (cfg = 0; cfg < num_configs; cfg++) { 1385 param = pinconf_to_config_param(configs[cfg]); 1386 arg = pinconf_to_config_argument(configs[cfg]); 1387 1388 switch (param) { 1389 case PIN_CONFIG_BIAS_DISABLE: 1390 case PIN_CONFIG_BIAS_PULL_UP: 1391 case PIN_CONFIG_BIAS_PULL_DOWN: 1392 arg = (param == PIN_CONFIG_BIAS_DISABLE) ? 0 : 1393 (param == PIN_CONFIG_BIAS_PULL_UP) ? BIAS_PU_BIT : 1394 BIAS_PD_BIT; 1395 1396 err = ocelot_hw_set_value(info, pin, PINCONF_BIAS, arg); 1397 if (err) 1398 goto err; 1399 1400 break; 1401 1402 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 1403 arg = arg ? SCHMITT_BIT : 0; 1404 err = ocelot_hw_set_value(info, pin, PINCONF_SCHMITT, 1405 arg); 1406 if (err) 1407 goto err; 1408 1409 break; 1410 1411 case PIN_CONFIG_DRIVE_STRENGTH: 1412 err = ocelot_hw_set_value(info, pin, 1413 PINCONF_DRIVE_STRENGTH, 1414 arg); 1415 if (err) 1416 goto err; 1417 1418 break; 1419 1420 case PIN_CONFIG_OUTPUT_ENABLE: 1421 case PIN_CONFIG_INPUT_ENABLE: 1422 case PIN_CONFIG_OUTPUT: 1423 p = pin % 32; 1424 if (arg) 1425 regmap_write(info->map, 1426 REG(OCELOT_GPIO_OUT_SET, info, 1427 pin), 1428 BIT(p)); 1429 else 1430 regmap_write(info->map, 1431 REG(OCELOT_GPIO_OUT_CLR, info, 1432 pin), 1433 BIT(p)); 1434 regmap_update_bits(info->map, 1435 REG(OCELOT_GPIO_OE, info, pin), 1436 BIT(p), 1437 param == PIN_CONFIG_INPUT_ENABLE ? 1438 0 : BIT(p)); 1439 break; 1440 1441 default: 1442 err = -EOPNOTSUPP; 1443 } 1444 } 1445 err: 1446 return err; 1447 } 1448 1449 static const struct pinconf_ops ocelot_confops = { 1450 .is_generic = true, 1451 .pin_config_get = ocelot_pinconf_get, 1452 .pin_config_set = ocelot_pinconf_set, 1453 .pin_config_config_dbg_show = pinconf_generic_dump_config, 1454 }; 1455 1456 static const struct pinctrl_ops ocelot_pctl_ops = { 1457 .get_groups_count = ocelot_pctl_get_groups_count, 1458 .get_group_name = ocelot_pctl_get_group_name, 1459 .get_group_pins = ocelot_pctl_get_group_pins, 1460 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, 1461 .dt_free_map = pinconf_generic_dt_free_map, 1462 }; 1463 1464 static struct pinctrl_desc luton_desc = { 1465 .name = "luton-pinctrl", 1466 .pins = luton_pins, 1467 .npins = ARRAY_SIZE(luton_pins), 1468 .pctlops = &ocelot_pctl_ops, 1469 .pmxops = &ocelot_pmx_ops, 1470 .owner = THIS_MODULE, 1471 }; 1472 1473 static struct pinctrl_desc serval_desc = { 1474 .name = "serval-pinctrl", 1475 .pins = serval_pins, 1476 .npins = ARRAY_SIZE(serval_pins), 1477 .pctlops = &ocelot_pctl_ops, 1478 .pmxops = &ocelot_pmx_ops, 1479 .owner = THIS_MODULE, 1480 }; 1481 1482 static struct pinctrl_desc ocelot_desc = { 1483 .name = "ocelot-pinctrl", 1484 .pins = ocelot_pins, 1485 .npins = ARRAY_SIZE(ocelot_pins), 1486 .pctlops = &ocelot_pctl_ops, 1487 .pmxops = &ocelot_pmx_ops, 1488 .owner = THIS_MODULE, 1489 }; 1490 1491 static struct pinctrl_desc jaguar2_desc = { 1492 .name = "jaguar2-pinctrl", 1493 .pins = jaguar2_pins, 1494 .npins = ARRAY_SIZE(jaguar2_pins), 1495 .pctlops = &ocelot_pctl_ops, 1496 .pmxops = &ocelot_pmx_ops, 1497 .owner = THIS_MODULE, 1498 }; 1499 1500 static struct pinctrl_desc sparx5_desc = { 1501 .name = "sparx5-pinctrl", 1502 .pins = sparx5_pins, 1503 .npins = ARRAY_SIZE(sparx5_pins), 1504 .pctlops = &ocelot_pctl_ops, 1505 .pmxops = &ocelot_pmx_ops, 1506 .confops = &ocelot_confops, 1507 .owner = THIS_MODULE, 1508 }; 1509 1510 static struct pinctrl_desc lan966x_desc = { 1511 .name = "lan966x-pinctrl", 1512 .pins = lan966x_pins, 1513 .npins = ARRAY_SIZE(lan966x_pins), 1514 .pctlops = &ocelot_pctl_ops, 1515 .pmxops = &lan966x_pmx_ops, 1516 .confops = &ocelot_confops, 1517 .owner = THIS_MODULE, 1518 }; 1519 1520 static int ocelot_create_group_func_map(struct device *dev, 1521 struct ocelot_pinctrl *info) 1522 { 1523 int f, npins, i; 1524 u8 *pins = kcalloc(info->desc->npins, sizeof(u8), GFP_KERNEL); 1525 1526 if (!pins) 1527 return -ENOMEM; 1528 1529 for (f = 0; f < FUNC_MAX; f++) { 1530 for (npins = 0, i = 0; i < info->desc->npins; i++) { 1531 if (ocelot_pin_function_idx(info, i, f) >= 0) 1532 pins[npins++] = i; 1533 } 1534 1535 if (!npins) 1536 continue; 1537 1538 info->func[f].ngroups = npins; 1539 info->func[f].groups = devm_kcalloc(dev, npins, sizeof(char *), 1540 GFP_KERNEL); 1541 if (!info->func[f].groups) { 1542 kfree(pins); 1543 return -ENOMEM; 1544 } 1545 1546 for (i = 0; i < npins; i++) 1547 info->func[f].groups[i] = 1548 info->desc->pins[pins[i]].name; 1549 } 1550 1551 kfree(pins); 1552 1553 return 0; 1554 } 1555 1556 static int ocelot_pinctrl_register(struct platform_device *pdev, 1557 struct ocelot_pinctrl *info) 1558 { 1559 int ret; 1560 1561 ret = ocelot_create_group_func_map(&pdev->dev, info); 1562 if (ret) { 1563 dev_err(&pdev->dev, "Unable to create group func map.\n"); 1564 return ret; 1565 } 1566 1567 info->pctl = devm_pinctrl_register(&pdev->dev, info->desc, info); 1568 if (IS_ERR(info->pctl)) { 1569 dev_err(&pdev->dev, "Failed to register pinctrl\n"); 1570 return PTR_ERR(info->pctl); 1571 } 1572 1573 return 0; 1574 } 1575 1576 static int ocelot_gpio_get(struct gpio_chip *chip, unsigned int offset) 1577 { 1578 struct ocelot_pinctrl *info = gpiochip_get_data(chip); 1579 unsigned int val; 1580 1581 regmap_read(info->map, REG(OCELOT_GPIO_IN, info, offset), &val); 1582 1583 return !!(val & BIT(offset % 32)); 1584 } 1585 1586 static void ocelot_gpio_set(struct gpio_chip *chip, unsigned int offset, 1587 int value) 1588 { 1589 struct ocelot_pinctrl *info = gpiochip_get_data(chip); 1590 1591 if (value) 1592 regmap_write(info->map, REG(OCELOT_GPIO_OUT_SET, info, offset), 1593 BIT(offset % 32)); 1594 else 1595 regmap_write(info->map, REG(OCELOT_GPIO_OUT_CLR, info, offset), 1596 BIT(offset % 32)); 1597 } 1598 1599 static int ocelot_gpio_get_direction(struct gpio_chip *chip, 1600 unsigned int offset) 1601 { 1602 struct ocelot_pinctrl *info = gpiochip_get_data(chip); 1603 unsigned int val; 1604 1605 regmap_read(info->map, REG(OCELOT_GPIO_OE, info, offset), &val); 1606 1607 if (val & BIT(offset % 32)) 1608 return GPIO_LINE_DIRECTION_OUT; 1609 1610 return GPIO_LINE_DIRECTION_IN; 1611 } 1612 1613 static int ocelot_gpio_direction_input(struct gpio_chip *chip, 1614 unsigned int offset) 1615 { 1616 return pinctrl_gpio_direction_input(chip->base + offset); 1617 } 1618 1619 static int ocelot_gpio_direction_output(struct gpio_chip *chip, 1620 unsigned int offset, int value) 1621 { 1622 struct ocelot_pinctrl *info = gpiochip_get_data(chip); 1623 unsigned int pin = BIT(offset % 32); 1624 1625 if (value) 1626 regmap_write(info->map, REG(OCELOT_GPIO_OUT_SET, info, offset), 1627 pin); 1628 else 1629 regmap_write(info->map, REG(OCELOT_GPIO_OUT_CLR, info, offset), 1630 pin); 1631 1632 return pinctrl_gpio_direction_output(chip->base + offset); 1633 } 1634 1635 static const struct gpio_chip ocelot_gpiolib_chip = { 1636 .request = gpiochip_generic_request, 1637 .free = gpiochip_generic_free, 1638 .set = ocelot_gpio_set, 1639 .get = ocelot_gpio_get, 1640 .get_direction = ocelot_gpio_get_direction, 1641 .direction_input = ocelot_gpio_direction_input, 1642 .direction_output = ocelot_gpio_direction_output, 1643 .owner = THIS_MODULE, 1644 }; 1645 1646 static void ocelot_irq_mask(struct irq_data *data) 1647 { 1648 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 1649 struct ocelot_pinctrl *info = gpiochip_get_data(chip); 1650 unsigned int gpio = irqd_to_hwirq(data); 1651 1652 regmap_update_bits(info->map, REG(OCELOT_GPIO_INTR_ENA, info, gpio), 1653 BIT(gpio % 32), 0); 1654 } 1655 1656 static void ocelot_irq_unmask(struct irq_data *data) 1657 { 1658 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 1659 struct ocelot_pinctrl *info = gpiochip_get_data(chip); 1660 unsigned int gpio = irqd_to_hwirq(data); 1661 1662 regmap_update_bits(info->map, REG(OCELOT_GPIO_INTR_ENA, info, gpio), 1663 BIT(gpio % 32), BIT(gpio % 32)); 1664 } 1665 1666 static void ocelot_irq_ack(struct irq_data *data) 1667 { 1668 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 1669 struct ocelot_pinctrl *info = gpiochip_get_data(chip); 1670 unsigned int gpio = irqd_to_hwirq(data); 1671 1672 regmap_write_bits(info->map, REG(OCELOT_GPIO_INTR, info, gpio), 1673 BIT(gpio % 32), BIT(gpio % 32)); 1674 } 1675 1676 static int ocelot_irq_set_type(struct irq_data *data, unsigned int type); 1677 1678 static struct irq_chip ocelot_eoi_irqchip = { 1679 .name = "gpio", 1680 .irq_mask = ocelot_irq_mask, 1681 .irq_eoi = ocelot_irq_ack, 1682 .irq_unmask = ocelot_irq_unmask, 1683 .flags = IRQCHIP_EOI_THREADED | IRQCHIP_EOI_IF_HANDLED, 1684 .irq_set_type = ocelot_irq_set_type, 1685 }; 1686 1687 static struct irq_chip ocelot_irqchip = { 1688 .name = "gpio", 1689 .irq_mask = ocelot_irq_mask, 1690 .irq_ack = ocelot_irq_ack, 1691 .irq_unmask = ocelot_irq_unmask, 1692 .irq_set_type = ocelot_irq_set_type, 1693 }; 1694 1695 static int ocelot_irq_set_type(struct irq_data *data, unsigned int type) 1696 { 1697 type &= IRQ_TYPE_SENSE_MASK; 1698 1699 if (!(type & (IRQ_TYPE_EDGE_BOTH | IRQ_TYPE_LEVEL_HIGH))) 1700 return -EINVAL; 1701 1702 if (type & IRQ_TYPE_LEVEL_HIGH) 1703 irq_set_chip_handler_name_locked(data, &ocelot_eoi_irqchip, 1704 handle_fasteoi_irq, NULL); 1705 if (type & IRQ_TYPE_EDGE_BOTH) 1706 irq_set_chip_handler_name_locked(data, &ocelot_irqchip, 1707 handle_edge_irq, NULL); 1708 1709 return 0; 1710 } 1711 1712 static void ocelot_irq_handler(struct irq_desc *desc) 1713 { 1714 struct irq_chip *parent_chip = irq_desc_get_chip(desc); 1715 struct gpio_chip *chip = irq_desc_get_handler_data(desc); 1716 struct ocelot_pinctrl *info = gpiochip_get_data(chip); 1717 unsigned int id_reg = OCELOT_GPIO_INTR_IDENT * info->stride; 1718 unsigned int reg = 0, irq, i; 1719 unsigned long irqs; 1720 1721 for (i = 0; i < info->stride; i++) { 1722 regmap_read(info->map, id_reg + 4 * i, ®); 1723 if (!reg) 1724 continue; 1725 1726 chained_irq_enter(parent_chip, desc); 1727 1728 irqs = reg; 1729 1730 for_each_set_bit(irq, &irqs, 1731 min(32U, info->desc->npins - 32 * i)) 1732 generic_handle_domain_irq(chip->irq.domain, irq + 32 * i); 1733 1734 chained_irq_exit(parent_chip, desc); 1735 } 1736 } 1737 1738 static int ocelot_gpiochip_register(struct platform_device *pdev, 1739 struct ocelot_pinctrl *info) 1740 { 1741 struct gpio_chip *gc; 1742 struct gpio_irq_chip *girq; 1743 int irq; 1744 1745 info->gpio_chip = ocelot_gpiolib_chip; 1746 1747 gc = &info->gpio_chip; 1748 gc->ngpio = info->desc->npins; 1749 gc->parent = &pdev->dev; 1750 gc->base = -1; 1751 gc->label = "ocelot-gpio"; 1752 1753 irq = irq_of_parse_and_map(gc->of_node, 0); 1754 if (irq) { 1755 girq = &gc->irq; 1756 girq->chip = &ocelot_irqchip; 1757 girq->parent_handler = ocelot_irq_handler; 1758 girq->num_parents = 1; 1759 girq->parents = devm_kcalloc(&pdev->dev, 1, 1760 sizeof(*girq->parents), 1761 GFP_KERNEL); 1762 if (!girq->parents) 1763 return -ENOMEM; 1764 girq->parents[0] = irq; 1765 girq->default_type = IRQ_TYPE_NONE; 1766 girq->handler = handle_edge_irq; 1767 } 1768 1769 return devm_gpiochip_add_data(&pdev->dev, gc, info); 1770 } 1771 1772 static const struct of_device_id ocelot_pinctrl_of_match[] = { 1773 { .compatible = "mscc,luton-pinctrl", .data = &luton_desc }, 1774 { .compatible = "mscc,serval-pinctrl", .data = &serval_desc }, 1775 { .compatible = "mscc,ocelot-pinctrl", .data = &ocelot_desc }, 1776 { .compatible = "mscc,jaguar2-pinctrl", .data = &jaguar2_desc }, 1777 { .compatible = "microchip,sparx5-pinctrl", .data = &sparx5_desc }, 1778 { .compatible = "microchip,lan966x-pinctrl", .data = &lan966x_desc }, 1779 {}, 1780 }; 1781 1782 static struct regmap *ocelot_pinctrl_create_pincfg(struct platform_device *pdev) 1783 { 1784 void __iomem *base; 1785 1786 const struct regmap_config regmap_config = { 1787 .reg_bits = 32, 1788 .val_bits = 32, 1789 .reg_stride = 4, 1790 .max_register = 32, 1791 }; 1792 1793 base = devm_platform_ioremap_resource(pdev, 0); 1794 if (IS_ERR(base)) { 1795 dev_dbg(&pdev->dev, "Failed to ioremap config registers (no extended pinconf)\n"); 1796 return NULL; 1797 } 1798 1799 return devm_regmap_init_mmio(&pdev->dev, base, ®map_config); 1800 } 1801 1802 static int ocelot_pinctrl_probe(struct platform_device *pdev) 1803 { 1804 struct device *dev = &pdev->dev; 1805 struct ocelot_pinctrl *info; 1806 struct regmap *pincfg; 1807 void __iomem *base; 1808 int ret; 1809 struct regmap_config regmap_config = { 1810 .reg_bits = 32, 1811 .val_bits = 32, 1812 .reg_stride = 4, 1813 }; 1814 1815 info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL); 1816 if (!info) 1817 return -ENOMEM; 1818 1819 info->desc = (struct pinctrl_desc *)device_get_match_data(dev); 1820 1821 base = devm_ioremap_resource(dev, 1822 platform_get_resource(pdev, IORESOURCE_MEM, 0)); 1823 if (IS_ERR(base)) 1824 return PTR_ERR(base); 1825 1826 info->stride = 1 + (info->desc->npins - 1) / 32; 1827 1828 regmap_config.max_register = OCELOT_GPIO_SD_MAP * info->stride + 15 * 4; 1829 1830 info->map = devm_regmap_init_mmio(dev, base, ®map_config); 1831 if (IS_ERR(info->map)) { 1832 dev_err(dev, "Failed to create regmap\n"); 1833 return PTR_ERR(info->map); 1834 } 1835 dev_set_drvdata(dev, info->map); 1836 info->dev = dev; 1837 1838 /* Pinconf registers */ 1839 if (info->desc->confops) { 1840 pincfg = ocelot_pinctrl_create_pincfg(pdev); 1841 if (IS_ERR(pincfg)) 1842 dev_dbg(dev, "Failed to create pincfg regmap\n"); 1843 else 1844 info->pincfg = pincfg; 1845 } 1846 1847 ret = ocelot_pinctrl_register(pdev, info); 1848 if (ret) 1849 return ret; 1850 1851 ret = ocelot_gpiochip_register(pdev, info); 1852 if (ret) 1853 return ret; 1854 1855 dev_info(dev, "driver registered\n"); 1856 1857 return 0; 1858 } 1859 1860 static struct platform_driver ocelot_pinctrl_driver = { 1861 .driver = { 1862 .name = "pinctrl-ocelot", 1863 .of_match_table = of_match_ptr(ocelot_pinctrl_of_match), 1864 .suppress_bind_attrs = true, 1865 }, 1866 .probe = ocelot_pinctrl_probe, 1867 }; 1868 builtin_platform_driver(ocelot_pinctrl_driver); 1869