1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* 3 * Microsemi SoCs pinctrl driver 4 * 5 * Author: <alexandre.belloni@free-electrons.com> 6 * License: Dual MIT/GPL 7 * Copyright (c) 2017 Microsemi Corporation 8 */ 9 10 #include <linux/gpio/driver.h> 11 #include <linux/interrupt.h> 12 #include <linux/io.h> 13 #include <linux/of_device.h> 14 #include <linux/of_irq.h> 15 #include <linux/of_platform.h> 16 #include <linux/pinctrl/pinctrl.h> 17 #include <linux/pinctrl/pinmux.h> 18 #include <linux/pinctrl/pinconf.h> 19 #include <linux/pinctrl/pinconf-generic.h> 20 #include <linux/platform_device.h> 21 #include <linux/regmap.h> 22 #include <linux/reset.h> 23 #include <linux/slab.h> 24 25 #include "core.h" 26 #include "pinconf.h" 27 #include "pinmux.h" 28 29 #define ocelot_clrsetbits(addr, clear, set) \ 30 writel((readl(addr) & ~(clear)) | (set), (addr)) 31 32 /* PINCONFIG bits (sparx5 only) */ 33 enum { 34 PINCONF_BIAS, 35 PINCONF_SCHMITT, 36 PINCONF_DRIVE_STRENGTH, 37 }; 38 39 #define BIAS_PD_BIT BIT(4) 40 #define BIAS_PU_BIT BIT(3) 41 #define BIAS_BITS (BIAS_PD_BIT|BIAS_PU_BIT) 42 #define SCHMITT_BIT BIT(2) 43 #define DRIVE_BITS GENMASK(1, 0) 44 45 /* GPIO standard registers */ 46 #define OCELOT_GPIO_OUT_SET 0x0 47 #define OCELOT_GPIO_OUT_CLR 0x4 48 #define OCELOT_GPIO_OUT 0x8 49 #define OCELOT_GPIO_IN 0xc 50 #define OCELOT_GPIO_OE 0x10 51 #define OCELOT_GPIO_INTR 0x14 52 #define OCELOT_GPIO_INTR_ENA 0x18 53 #define OCELOT_GPIO_INTR_IDENT 0x1c 54 #define OCELOT_GPIO_ALT0 0x20 55 #define OCELOT_GPIO_ALT1 0x24 56 #define OCELOT_GPIO_SD_MAP 0x28 57 58 #define OCELOT_FUNC_PER_PIN 4 59 60 enum { 61 FUNC_CAN0_a, 62 FUNC_CAN0_b, 63 FUNC_CAN1, 64 FUNC_CLKMON, 65 FUNC_NONE, 66 FUNC_FC0_a, 67 FUNC_FC0_b, 68 FUNC_FC0_c, 69 FUNC_FC1_a, 70 FUNC_FC1_b, 71 FUNC_FC1_c, 72 FUNC_FC2_a, 73 FUNC_FC2_b, 74 FUNC_FC3_a, 75 FUNC_FC3_b, 76 FUNC_FC3_c, 77 FUNC_FC4_a, 78 FUNC_FC4_b, 79 FUNC_FC4_c, 80 FUNC_FC_SHRD0, 81 FUNC_FC_SHRD1, 82 FUNC_FC_SHRD2, 83 FUNC_FC_SHRD3, 84 FUNC_FC_SHRD4, 85 FUNC_FC_SHRD5, 86 FUNC_FC_SHRD6, 87 FUNC_FC_SHRD7, 88 FUNC_FC_SHRD8, 89 FUNC_FC_SHRD9, 90 FUNC_FC_SHRD10, 91 FUNC_FC_SHRD11, 92 FUNC_FC_SHRD12, 93 FUNC_FC_SHRD13, 94 FUNC_FC_SHRD14, 95 FUNC_FC_SHRD15, 96 FUNC_FC_SHRD16, 97 FUNC_FC_SHRD17, 98 FUNC_FC_SHRD18, 99 FUNC_FC_SHRD19, 100 FUNC_FC_SHRD20, 101 FUNC_GPIO, 102 FUNC_IB_TRG_a, 103 FUNC_IB_TRG_b, 104 FUNC_IB_TRG_c, 105 FUNC_IRQ0, 106 FUNC_IRQ_IN_a, 107 FUNC_IRQ_IN_b, 108 FUNC_IRQ_IN_c, 109 FUNC_IRQ0_IN, 110 FUNC_IRQ_OUT_a, 111 FUNC_IRQ_OUT_b, 112 FUNC_IRQ_OUT_c, 113 FUNC_IRQ0_OUT, 114 FUNC_IRQ1, 115 FUNC_IRQ1_IN, 116 FUNC_IRQ1_OUT, 117 FUNC_EXT_IRQ, 118 FUNC_MIIM, 119 FUNC_MIIM_a, 120 FUNC_MIIM_b, 121 FUNC_MIIM_c, 122 FUNC_MIIM_Sa, 123 FUNC_MIIM_Sb, 124 FUNC_OB_TRG, 125 FUNC_OB_TRG_a, 126 FUNC_OB_TRG_b, 127 FUNC_PHY_LED, 128 FUNC_PCI_WAKE, 129 FUNC_MD, 130 FUNC_PTP0, 131 FUNC_PTP1, 132 FUNC_PTP2, 133 FUNC_PTP3, 134 FUNC_PTPSYNC_0, 135 FUNC_PTPSYNC_1, 136 FUNC_PTPSYNC_2, 137 FUNC_PTPSYNC_3, 138 FUNC_PTPSYNC_4, 139 FUNC_PTPSYNC_5, 140 FUNC_PTPSYNC_6, 141 FUNC_PTPSYNC_7, 142 FUNC_PWM, 143 FUNC_PWM_a, 144 FUNC_PWM_b, 145 FUNC_QSPI1, 146 FUNC_QSPI2, 147 FUNC_R, 148 FUNC_RECO_a, 149 FUNC_RECO_b, 150 FUNC_RECO_CLK, 151 FUNC_SD, 152 FUNC_SFP, 153 FUNC_SFP_SD, 154 FUNC_SG0, 155 FUNC_SG1, 156 FUNC_SG2, 157 FUNC_SGPIO_a, 158 FUNC_SGPIO_b, 159 FUNC_SI, 160 FUNC_SI2, 161 FUNC_TACHO, 162 FUNC_TACHO_a, 163 FUNC_TACHO_b, 164 FUNC_TWI, 165 FUNC_TWI2, 166 FUNC_TWI3, 167 FUNC_TWI_SCL_M, 168 FUNC_TWI_SLC_GATE, 169 FUNC_TWI_SLC_GATE_AD, 170 FUNC_UART, 171 FUNC_UART2, 172 FUNC_UART3, 173 FUNC_USB_H_a, 174 FUNC_USB_H_b, 175 FUNC_USB_H_c, 176 FUNC_USB_S_a, 177 FUNC_USB_S_b, 178 FUNC_USB_S_c, 179 FUNC_PLL_STAT, 180 FUNC_EMMC, 181 FUNC_EMMC_SD, 182 FUNC_REF_CLK, 183 FUNC_RCVRD_CLK, 184 FUNC_MAX 185 }; 186 187 static const char *const ocelot_function_names[] = { 188 [FUNC_CAN0_a] = "can0_a", 189 [FUNC_CAN0_b] = "can0_b", 190 [FUNC_CAN1] = "can1", 191 [FUNC_CLKMON] = "clkmon", 192 [FUNC_NONE] = "none", 193 [FUNC_FC0_a] = "fc0_a", 194 [FUNC_FC0_b] = "fc0_b", 195 [FUNC_FC0_c] = "fc0_c", 196 [FUNC_FC1_a] = "fc1_a", 197 [FUNC_FC1_b] = "fc1_b", 198 [FUNC_FC1_c] = "fc1_c", 199 [FUNC_FC2_a] = "fc2_a", 200 [FUNC_FC2_b] = "fc2_b", 201 [FUNC_FC3_a] = "fc3_a", 202 [FUNC_FC3_b] = "fc3_b", 203 [FUNC_FC3_c] = "fc3_c", 204 [FUNC_FC4_a] = "fc4_a", 205 [FUNC_FC4_b] = "fc4_b", 206 [FUNC_FC4_c] = "fc4_c", 207 [FUNC_FC_SHRD0] = "fc_shrd0", 208 [FUNC_FC_SHRD1] = "fc_shrd1", 209 [FUNC_FC_SHRD2] = "fc_shrd2", 210 [FUNC_FC_SHRD3] = "fc_shrd3", 211 [FUNC_FC_SHRD4] = "fc_shrd4", 212 [FUNC_FC_SHRD5] = "fc_shrd5", 213 [FUNC_FC_SHRD6] = "fc_shrd6", 214 [FUNC_FC_SHRD7] = "fc_shrd7", 215 [FUNC_FC_SHRD8] = "fc_shrd8", 216 [FUNC_FC_SHRD9] = "fc_shrd9", 217 [FUNC_FC_SHRD10] = "fc_shrd10", 218 [FUNC_FC_SHRD11] = "fc_shrd11", 219 [FUNC_FC_SHRD12] = "fc_shrd12", 220 [FUNC_FC_SHRD13] = "fc_shrd13", 221 [FUNC_FC_SHRD14] = "fc_shrd14", 222 [FUNC_FC_SHRD15] = "fc_shrd15", 223 [FUNC_FC_SHRD16] = "fc_shrd16", 224 [FUNC_FC_SHRD17] = "fc_shrd17", 225 [FUNC_FC_SHRD18] = "fc_shrd18", 226 [FUNC_FC_SHRD19] = "fc_shrd19", 227 [FUNC_FC_SHRD20] = "fc_shrd20", 228 [FUNC_GPIO] = "gpio", 229 [FUNC_IB_TRG_a] = "ib_trig_a", 230 [FUNC_IB_TRG_b] = "ib_trig_b", 231 [FUNC_IB_TRG_c] = "ib_trig_c", 232 [FUNC_IRQ0] = "irq0", 233 [FUNC_IRQ_IN_a] = "irq_in_a", 234 [FUNC_IRQ_IN_b] = "irq_in_b", 235 [FUNC_IRQ_IN_c] = "irq_in_c", 236 [FUNC_IRQ0_IN] = "irq0_in", 237 [FUNC_IRQ_OUT_a] = "irq_out_a", 238 [FUNC_IRQ_OUT_b] = "irq_out_b", 239 [FUNC_IRQ_OUT_c] = "irq_out_c", 240 [FUNC_IRQ0_OUT] = "irq0_out", 241 [FUNC_IRQ1] = "irq1", 242 [FUNC_IRQ1_IN] = "irq1_in", 243 [FUNC_IRQ1_OUT] = "irq1_out", 244 [FUNC_EXT_IRQ] = "ext_irq", 245 [FUNC_MIIM] = "miim", 246 [FUNC_MIIM_a] = "miim_a", 247 [FUNC_MIIM_b] = "miim_b", 248 [FUNC_MIIM_c] = "miim_c", 249 [FUNC_MIIM_Sa] = "miim_slave_a", 250 [FUNC_MIIM_Sb] = "miim_slave_b", 251 [FUNC_PHY_LED] = "phy_led", 252 [FUNC_PCI_WAKE] = "pci_wake", 253 [FUNC_MD] = "md", 254 [FUNC_OB_TRG] = "ob_trig", 255 [FUNC_OB_TRG_a] = "ob_trig_a", 256 [FUNC_OB_TRG_b] = "ob_trig_b", 257 [FUNC_PTP0] = "ptp0", 258 [FUNC_PTP1] = "ptp1", 259 [FUNC_PTP2] = "ptp2", 260 [FUNC_PTP3] = "ptp3", 261 [FUNC_PTPSYNC_0] = "ptpsync_0", 262 [FUNC_PTPSYNC_1] = "ptpsync_1", 263 [FUNC_PTPSYNC_2] = "ptpsync_2", 264 [FUNC_PTPSYNC_3] = "ptpsync_3", 265 [FUNC_PTPSYNC_4] = "ptpsync_4", 266 [FUNC_PTPSYNC_5] = "ptpsync_5", 267 [FUNC_PTPSYNC_6] = "ptpsync_6", 268 [FUNC_PTPSYNC_7] = "ptpsync_7", 269 [FUNC_PWM] = "pwm", 270 [FUNC_PWM_a] = "pwm_a", 271 [FUNC_PWM_b] = "pwm_b", 272 [FUNC_QSPI1] = "qspi1", 273 [FUNC_QSPI2] = "qspi2", 274 [FUNC_R] = "reserved", 275 [FUNC_RECO_a] = "reco_a", 276 [FUNC_RECO_b] = "reco_b", 277 [FUNC_RECO_CLK] = "reco_clk", 278 [FUNC_SD] = "sd", 279 [FUNC_SFP] = "sfp", 280 [FUNC_SFP_SD] = "sfp_sd", 281 [FUNC_SG0] = "sg0", 282 [FUNC_SG1] = "sg1", 283 [FUNC_SG2] = "sg2", 284 [FUNC_SGPIO_a] = "sgpio_a", 285 [FUNC_SGPIO_b] = "sgpio_b", 286 [FUNC_SI] = "si", 287 [FUNC_SI2] = "si2", 288 [FUNC_TACHO] = "tacho", 289 [FUNC_TACHO_a] = "tacho_a", 290 [FUNC_TACHO_b] = "tacho_b", 291 [FUNC_TWI] = "twi", 292 [FUNC_TWI2] = "twi2", 293 [FUNC_TWI3] = "twi3", 294 [FUNC_TWI_SCL_M] = "twi_scl_m", 295 [FUNC_TWI_SLC_GATE] = "twi_slc_gate", 296 [FUNC_TWI_SLC_GATE_AD] = "twi_slc_gate_ad", 297 [FUNC_USB_H_a] = "usb_host_a", 298 [FUNC_USB_H_b] = "usb_host_b", 299 [FUNC_USB_H_c] = "usb_host_c", 300 [FUNC_USB_S_a] = "usb_slave_a", 301 [FUNC_USB_S_b] = "usb_slave_b", 302 [FUNC_USB_S_c] = "usb_slave_c", 303 [FUNC_UART] = "uart", 304 [FUNC_UART2] = "uart2", 305 [FUNC_UART3] = "uart3", 306 [FUNC_PLL_STAT] = "pll_stat", 307 [FUNC_EMMC] = "emmc", 308 [FUNC_EMMC_SD] = "emmc_sd", 309 [FUNC_REF_CLK] = "ref_clk", 310 [FUNC_RCVRD_CLK] = "rcvrd_clk", 311 }; 312 313 struct ocelot_pmx_func { 314 const char **groups; 315 unsigned int ngroups; 316 }; 317 318 struct ocelot_pin_caps { 319 unsigned int pin; 320 unsigned char functions[OCELOT_FUNC_PER_PIN]; 321 unsigned char a_functions[OCELOT_FUNC_PER_PIN]; /* Additional functions */ 322 }; 323 324 struct ocelot_pinctrl { 325 struct device *dev; 326 struct pinctrl_dev *pctl; 327 struct gpio_chip gpio_chip; 328 struct regmap *map; 329 struct regmap *pincfg; 330 struct pinctrl_desc *desc; 331 struct ocelot_pmx_func func[FUNC_MAX]; 332 u8 stride; 333 }; 334 335 #define LUTON_P(p, f0, f1) \ 336 static struct ocelot_pin_caps luton_pin_##p = { \ 337 .pin = p, \ 338 .functions = { \ 339 FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_NONE, \ 340 }, \ 341 } 342 343 LUTON_P(0, SG0, NONE); 344 LUTON_P(1, SG0, NONE); 345 LUTON_P(2, SG0, NONE); 346 LUTON_P(3, SG0, NONE); 347 LUTON_P(4, TACHO, NONE); 348 LUTON_P(5, TWI, PHY_LED); 349 LUTON_P(6, TWI, PHY_LED); 350 LUTON_P(7, NONE, PHY_LED); 351 LUTON_P(8, EXT_IRQ, PHY_LED); 352 LUTON_P(9, EXT_IRQ, PHY_LED); 353 LUTON_P(10, SFP, PHY_LED); 354 LUTON_P(11, SFP, PHY_LED); 355 LUTON_P(12, SFP, PHY_LED); 356 LUTON_P(13, SFP, PHY_LED); 357 LUTON_P(14, SI, PHY_LED); 358 LUTON_P(15, SI, PHY_LED); 359 LUTON_P(16, SI, PHY_LED); 360 LUTON_P(17, SFP, PHY_LED); 361 LUTON_P(18, SFP, PHY_LED); 362 LUTON_P(19, SFP, PHY_LED); 363 LUTON_P(20, SFP, PHY_LED); 364 LUTON_P(21, SFP, PHY_LED); 365 LUTON_P(22, SFP, PHY_LED); 366 LUTON_P(23, SFP, PHY_LED); 367 LUTON_P(24, SFP, PHY_LED); 368 LUTON_P(25, SFP, PHY_LED); 369 LUTON_P(26, SFP, PHY_LED); 370 LUTON_P(27, SFP, PHY_LED); 371 LUTON_P(28, SFP, PHY_LED); 372 LUTON_P(29, PWM, NONE); 373 LUTON_P(30, UART, NONE); 374 LUTON_P(31, UART, NONE); 375 376 #define LUTON_PIN(n) { \ 377 .number = n, \ 378 .name = "GPIO_"#n, \ 379 .drv_data = &luton_pin_##n \ 380 } 381 382 static const struct pinctrl_pin_desc luton_pins[] = { 383 LUTON_PIN(0), 384 LUTON_PIN(1), 385 LUTON_PIN(2), 386 LUTON_PIN(3), 387 LUTON_PIN(4), 388 LUTON_PIN(5), 389 LUTON_PIN(6), 390 LUTON_PIN(7), 391 LUTON_PIN(8), 392 LUTON_PIN(9), 393 LUTON_PIN(10), 394 LUTON_PIN(11), 395 LUTON_PIN(12), 396 LUTON_PIN(13), 397 LUTON_PIN(14), 398 LUTON_PIN(15), 399 LUTON_PIN(16), 400 LUTON_PIN(17), 401 LUTON_PIN(18), 402 LUTON_PIN(19), 403 LUTON_PIN(20), 404 LUTON_PIN(21), 405 LUTON_PIN(22), 406 LUTON_PIN(23), 407 LUTON_PIN(24), 408 LUTON_PIN(25), 409 LUTON_PIN(26), 410 LUTON_PIN(27), 411 LUTON_PIN(28), 412 LUTON_PIN(29), 413 LUTON_PIN(30), 414 LUTON_PIN(31), 415 }; 416 417 #define SERVAL_P(p, f0, f1, f2) \ 418 static struct ocelot_pin_caps serval_pin_##p = { \ 419 .pin = p, \ 420 .functions = { \ 421 FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2, \ 422 }, \ 423 } 424 425 SERVAL_P(0, SG0, NONE, NONE); 426 SERVAL_P(1, SG0, NONE, NONE); 427 SERVAL_P(2, SG0, NONE, NONE); 428 SERVAL_P(3, SG0, NONE, NONE); 429 SERVAL_P(4, TACHO, NONE, NONE); 430 SERVAL_P(5, PWM, NONE, NONE); 431 SERVAL_P(6, TWI, NONE, NONE); 432 SERVAL_P(7, TWI, NONE, NONE); 433 SERVAL_P(8, SI, NONE, NONE); 434 SERVAL_P(9, SI, MD, NONE); 435 SERVAL_P(10, SI, MD, NONE); 436 SERVAL_P(11, SFP, MD, TWI_SCL_M); 437 SERVAL_P(12, SFP, MD, TWI_SCL_M); 438 SERVAL_P(13, SFP, UART2, TWI_SCL_M); 439 SERVAL_P(14, SFP, UART2, TWI_SCL_M); 440 SERVAL_P(15, SFP, PTP0, TWI_SCL_M); 441 SERVAL_P(16, SFP, PTP0, TWI_SCL_M); 442 SERVAL_P(17, SFP, PCI_WAKE, TWI_SCL_M); 443 SERVAL_P(18, SFP, NONE, TWI_SCL_M); 444 SERVAL_P(19, SFP, NONE, TWI_SCL_M); 445 SERVAL_P(20, SFP, NONE, TWI_SCL_M); 446 SERVAL_P(21, SFP, NONE, TWI_SCL_M); 447 SERVAL_P(22, NONE, NONE, NONE); 448 SERVAL_P(23, NONE, NONE, NONE); 449 SERVAL_P(24, NONE, NONE, NONE); 450 SERVAL_P(25, NONE, NONE, NONE); 451 SERVAL_P(26, UART, NONE, NONE); 452 SERVAL_P(27, UART, NONE, NONE); 453 SERVAL_P(28, IRQ0, NONE, NONE); 454 SERVAL_P(29, IRQ1, NONE, NONE); 455 SERVAL_P(30, PTP0, NONE, NONE); 456 SERVAL_P(31, PTP0, NONE, NONE); 457 458 #define SERVAL_PIN(n) { \ 459 .number = n, \ 460 .name = "GPIO_"#n, \ 461 .drv_data = &serval_pin_##n \ 462 } 463 464 static const struct pinctrl_pin_desc serval_pins[] = { 465 SERVAL_PIN(0), 466 SERVAL_PIN(1), 467 SERVAL_PIN(2), 468 SERVAL_PIN(3), 469 SERVAL_PIN(4), 470 SERVAL_PIN(5), 471 SERVAL_PIN(6), 472 SERVAL_PIN(7), 473 SERVAL_PIN(8), 474 SERVAL_PIN(9), 475 SERVAL_PIN(10), 476 SERVAL_PIN(11), 477 SERVAL_PIN(12), 478 SERVAL_PIN(13), 479 SERVAL_PIN(14), 480 SERVAL_PIN(15), 481 SERVAL_PIN(16), 482 SERVAL_PIN(17), 483 SERVAL_PIN(18), 484 SERVAL_PIN(19), 485 SERVAL_PIN(20), 486 SERVAL_PIN(21), 487 SERVAL_PIN(22), 488 SERVAL_PIN(23), 489 SERVAL_PIN(24), 490 SERVAL_PIN(25), 491 SERVAL_PIN(26), 492 SERVAL_PIN(27), 493 SERVAL_PIN(28), 494 SERVAL_PIN(29), 495 SERVAL_PIN(30), 496 SERVAL_PIN(31), 497 }; 498 499 #define OCELOT_P(p, f0, f1, f2) \ 500 static struct ocelot_pin_caps ocelot_pin_##p = { \ 501 .pin = p, \ 502 .functions = { \ 503 FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2, \ 504 }, \ 505 } 506 507 OCELOT_P(0, SG0, NONE, NONE); 508 OCELOT_P(1, SG0, NONE, NONE); 509 OCELOT_P(2, SG0, NONE, NONE); 510 OCELOT_P(3, SG0, NONE, NONE); 511 OCELOT_P(4, IRQ0_IN, IRQ0_OUT, TWI_SCL_M); 512 OCELOT_P(5, IRQ1_IN, IRQ1_OUT, PCI_WAKE); 513 OCELOT_P(6, UART, TWI_SCL_M, NONE); 514 OCELOT_P(7, UART, TWI_SCL_M, NONE); 515 OCELOT_P(8, SI, TWI_SCL_M, IRQ0_OUT); 516 OCELOT_P(9, SI, TWI_SCL_M, IRQ1_OUT); 517 OCELOT_P(10, PTP2, TWI_SCL_M, SFP); 518 OCELOT_P(11, PTP3, TWI_SCL_M, SFP); 519 OCELOT_P(12, UART2, TWI_SCL_M, SFP); 520 OCELOT_P(13, UART2, TWI_SCL_M, SFP); 521 OCELOT_P(14, MIIM, TWI_SCL_M, SFP); 522 OCELOT_P(15, MIIM, TWI_SCL_M, SFP); 523 OCELOT_P(16, TWI, NONE, SI); 524 OCELOT_P(17, TWI, TWI_SCL_M, SI); 525 OCELOT_P(18, PTP0, TWI_SCL_M, NONE); 526 OCELOT_P(19, PTP1, TWI_SCL_M, NONE); 527 OCELOT_P(20, RECO_CLK, TACHO, TWI_SCL_M); 528 OCELOT_P(21, RECO_CLK, PWM, TWI_SCL_M); 529 530 #define OCELOT_PIN(n) { \ 531 .number = n, \ 532 .name = "GPIO_"#n, \ 533 .drv_data = &ocelot_pin_##n \ 534 } 535 536 static const struct pinctrl_pin_desc ocelot_pins[] = { 537 OCELOT_PIN(0), 538 OCELOT_PIN(1), 539 OCELOT_PIN(2), 540 OCELOT_PIN(3), 541 OCELOT_PIN(4), 542 OCELOT_PIN(5), 543 OCELOT_PIN(6), 544 OCELOT_PIN(7), 545 OCELOT_PIN(8), 546 OCELOT_PIN(9), 547 OCELOT_PIN(10), 548 OCELOT_PIN(11), 549 OCELOT_PIN(12), 550 OCELOT_PIN(13), 551 OCELOT_PIN(14), 552 OCELOT_PIN(15), 553 OCELOT_PIN(16), 554 OCELOT_PIN(17), 555 OCELOT_PIN(18), 556 OCELOT_PIN(19), 557 OCELOT_PIN(20), 558 OCELOT_PIN(21), 559 }; 560 561 #define JAGUAR2_P(p, f0, f1) \ 562 static struct ocelot_pin_caps jaguar2_pin_##p = { \ 563 .pin = p, \ 564 .functions = { \ 565 FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_NONE \ 566 }, \ 567 } 568 569 JAGUAR2_P(0, SG0, NONE); 570 JAGUAR2_P(1, SG0, NONE); 571 JAGUAR2_P(2, SG0, NONE); 572 JAGUAR2_P(3, SG0, NONE); 573 JAGUAR2_P(4, SG1, NONE); 574 JAGUAR2_P(5, SG1, NONE); 575 JAGUAR2_P(6, IRQ0_IN, IRQ0_OUT); 576 JAGUAR2_P(7, IRQ1_IN, IRQ1_OUT); 577 JAGUAR2_P(8, PTP0, NONE); 578 JAGUAR2_P(9, PTP1, NONE); 579 JAGUAR2_P(10, UART, NONE); 580 JAGUAR2_P(11, UART, NONE); 581 JAGUAR2_P(12, SG1, NONE); 582 JAGUAR2_P(13, SG1, NONE); 583 JAGUAR2_P(14, TWI, TWI_SCL_M); 584 JAGUAR2_P(15, TWI, NONE); 585 JAGUAR2_P(16, SI, TWI_SCL_M); 586 JAGUAR2_P(17, SI, TWI_SCL_M); 587 JAGUAR2_P(18, SI, TWI_SCL_M); 588 JAGUAR2_P(19, PCI_WAKE, NONE); 589 JAGUAR2_P(20, IRQ0_OUT, TWI_SCL_M); 590 JAGUAR2_P(21, IRQ1_OUT, TWI_SCL_M); 591 JAGUAR2_P(22, TACHO, NONE); 592 JAGUAR2_P(23, PWM, NONE); 593 JAGUAR2_P(24, UART2, NONE); 594 JAGUAR2_P(25, UART2, SI); 595 JAGUAR2_P(26, PTP2, SI); 596 JAGUAR2_P(27, PTP3, SI); 597 JAGUAR2_P(28, TWI2, SI); 598 JAGUAR2_P(29, TWI2, SI); 599 JAGUAR2_P(30, SG2, SI); 600 JAGUAR2_P(31, SG2, SI); 601 JAGUAR2_P(32, SG2, SI); 602 JAGUAR2_P(33, SG2, SI); 603 JAGUAR2_P(34, NONE, TWI_SCL_M); 604 JAGUAR2_P(35, NONE, TWI_SCL_M); 605 JAGUAR2_P(36, NONE, TWI_SCL_M); 606 JAGUAR2_P(37, NONE, TWI_SCL_M); 607 JAGUAR2_P(38, NONE, TWI_SCL_M); 608 JAGUAR2_P(39, NONE, TWI_SCL_M); 609 JAGUAR2_P(40, NONE, TWI_SCL_M); 610 JAGUAR2_P(41, NONE, TWI_SCL_M); 611 JAGUAR2_P(42, NONE, TWI_SCL_M); 612 JAGUAR2_P(43, NONE, TWI_SCL_M); 613 JAGUAR2_P(44, NONE, SFP); 614 JAGUAR2_P(45, NONE, SFP); 615 JAGUAR2_P(46, NONE, SFP); 616 JAGUAR2_P(47, NONE, SFP); 617 JAGUAR2_P(48, SFP, NONE); 618 JAGUAR2_P(49, SFP, SI); 619 JAGUAR2_P(50, SFP, SI); 620 JAGUAR2_P(51, SFP, SI); 621 JAGUAR2_P(52, SFP, NONE); 622 JAGUAR2_P(53, SFP, NONE); 623 JAGUAR2_P(54, SFP, NONE); 624 JAGUAR2_P(55, SFP, NONE); 625 JAGUAR2_P(56, MIIM, SFP); 626 JAGUAR2_P(57, MIIM, SFP); 627 JAGUAR2_P(58, MIIM, SFP); 628 JAGUAR2_P(59, MIIM, SFP); 629 JAGUAR2_P(60, NONE, NONE); 630 JAGUAR2_P(61, NONE, NONE); 631 JAGUAR2_P(62, NONE, NONE); 632 JAGUAR2_P(63, NONE, NONE); 633 634 #define JAGUAR2_PIN(n) { \ 635 .number = n, \ 636 .name = "GPIO_"#n, \ 637 .drv_data = &jaguar2_pin_##n \ 638 } 639 640 static const struct pinctrl_pin_desc jaguar2_pins[] = { 641 JAGUAR2_PIN(0), 642 JAGUAR2_PIN(1), 643 JAGUAR2_PIN(2), 644 JAGUAR2_PIN(3), 645 JAGUAR2_PIN(4), 646 JAGUAR2_PIN(5), 647 JAGUAR2_PIN(6), 648 JAGUAR2_PIN(7), 649 JAGUAR2_PIN(8), 650 JAGUAR2_PIN(9), 651 JAGUAR2_PIN(10), 652 JAGUAR2_PIN(11), 653 JAGUAR2_PIN(12), 654 JAGUAR2_PIN(13), 655 JAGUAR2_PIN(14), 656 JAGUAR2_PIN(15), 657 JAGUAR2_PIN(16), 658 JAGUAR2_PIN(17), 659 JAGUAR2_PIN(18), 660 JAGUAR2_PIN(19), 661 JAGUAR2_PIN(20), 662 JAGUAR2_PIN(21), 663 JAGUAR2_PIN(22), 664 JAGUAR2_PIN(23), 665 JAGUAR2_PIN(24), 666 JAGUAR2_PIN(25), 667 JAGUAR2_PIN(26), 668 JAGUAR2_PIN(27), 669 JAGUAR2_PIN(28), 670 JAGUAR2_PIN(29), 671 JAGUAR2_PIN(30), 672 JAGUAR2_PIN(31), 673 JAGUAR2_PIN(32), 674 JAGUAR2_PIN(33), 675 JAGUAR2_PIN(34), 676 JAGUAR2_PIN(35), 677 JAGUAR2_PIN(36), 678 JAGUAR2_PIN(37), 679 JAGUAR2_PIN(38), 680 JAGUAR2_PIN(39), 681 JAGUAR2_PIN(40), 682 JAGUAR2_PIN(41), 683 JAGUAR2_PIN(42), 684 JAGUAR2_PIN(43), 685 JAGUAR2_PIN(44), 686 JAGUAR2_PIN(45), 687 JAGUAR2_PIN(46), 688 JAGUAR2_PIN(47), 689 JAGUAR2_PIN(48), 690 JAGUAR2_PIN(49), 691 JAGUAR2_PIN(50), 692 JAGUAR2_PIN(51), 693 JAGUAR2_PIN(52), 694 JAGUAR2_PIN(53), 695 JAGUAR2_PIN(54), 696 JAGUAR2_PIN(55), 697 JAGUAR2_PIN(56), 698 JAGUAR2_PIN(57), 699 JAGUAR2_PIN(58), 700 JAGUAR2_PIN(59), 701 JAGUAR2_PIN(60), 702 JAGUAR2_PIN(61), 703 JAGUAR2_PIN(62), 704 JAGUAR2_PIN(63), 705 }; 706 707 #define SERVALT_P(p, f0, f1, f2) \ 708 static struct ocelot_pin_caps servalt_pin_##p = { \ 709 .pin = p, \ 710 .functions = { \ 711 FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2 \ 712 }, \ 713 } 714 715 SERVALT_P(0, SG0, NONE, NONE); 716 SERVALT_P(1, SG0, NONE, NONE); 717 SERVALT_P(2, SG0, NONE, NONE); 718 SERVALT_P(3, SG0, NONE, NONE); 719 SERVALT_P(4, IRQ0_IN, IRQ0_OUT, TWI_SCL_M); 720 SERVALT_P(5, IRQ1_IN, IRQ1_OUT, TWI_SCL_M); 721 SERVALT_P(6, UART, NONE, NONE); 722 SERVALT_P(7, UART, NONE, NONE); 723 SERVALT_P(8, SI, SFP, TWI_SCL_M); 724 SERVALT_P(9, PCI_WAKE, SFP, SI); 725 SERVALT_P(10, PTP0, SFP, TWI_SCL_M); 726 SERVALT_P(11, PTP1, SFP, TWI_SCL_M); 727 SERVALT_P(12, REF_CLK, SFP, TWI_SCL_M); 728 SERVALT_P(13, REF_CLK, SFP, TWI_SCL_M); 729 SERVALT_P(14, REF_CLK, IRQ0_OUT, SI); 730 SERVALT_P(15, REF_CLK, IRQ1_OUT, SI); 731 SERVALT_P(16, TACHO, SFP, SI); 732 SERVALT_P(17, PWM, NONE, TWI_SCL_M); 733 SERVALT_P(18, PTP2, SFP, SI); 734 SERVALT_P(19, PTP3, SFP, SI); 735 SERVALT_P(20, UART2, SFP, SI); 736 SERVALT_P(21, UART2, NONE, NONE); 737 SERVALT_P(22, MIIM, SFP, TWI2); 738 SERVALT_P(23, MIIM, SFP, TWI2); 739 SERVALT_P(24, TWI, NONE, NONE); 740 SERVALT_P(25, TWI, SFP, TWI_SCL_M); 741 SERVALT_P(26, TWI_SCL_M, SFP, SI); 742 SERVALT_P(27, TWI_SCL_M, SFP, SI); 743 SERVALT_P(28, TWI_SCL_M, SFP, SI); 744 SERVALT_P(29, TWI_SCL_M, NONE, NONE); 745 SERVALT_P(30, TWI_SCL_M, NONE, NONE); 746 SERVALT_P(31, TWI_SCL_M, NONE, NONE); 747 SERVALT_P(32, TWI_SCL_M, NONE, NONE); 748 SERVALT_P(33, RCVRD_CLK, NONE, NONE); 749 SERVALT_P(34, RCVRD_CLK, NONE, NONE); 750 SERVALT_P(35, RCVRD_CLK, NONE, NONE); 751 SERVALT_P(36, RCVRD_CLK, NONE, NONE); 752 753 #define SERVALT_PIN(n) { \ 754 .number = n, \ 755 .name = "GPIO_"#n, \ 756 .drv_data = &servalt_pin_##n \ 757 } 758 759 static const struct pinctrl_pin_desc servalt_pins[] = { 760 SERVALT_PIN(0), 761 SERVALT_PIN(1), 762 SERVALT_PIN(2), 763 SERVALT_PIN(3), 764 SERVALT_PIN(4), 765 SERVALT_PIN(5), 766 SERVALT_PIN(6), 767 SERVALT_PIN(7), 768 SERVALT_PIN(8), 769 SERVALT_PIN(9), 770 SERVALT_PIN(10), 771 SERVALT_PIN(11), 772 SERVALT_PIN(12), 773 SERVALT_PIN(13), 774 SERVALT_PIN(14), 775 SERVALT_PIN(15), 776 SERVALT_PIN(16), 777 SERVALT_PIN(17), 778 SERVALT_PIN(18), 779 SERVALT_PIN(19), 780 SERVALT_PIN(20), 781 SERVALT_PIN(21), 782 SERVALT_PIN(22), 783 SERVALT_PIN(23), 784 SERVALT_PIN(24), 785 SERVALT_PIN(25), 786 SERVALT_PIN(26), 787 SERVALT_PIN(27), 788 SERVALT_PIN(28), 789 SERVALT_PIN(29), 790 SERVALT_PIN(30), 791 SERVALT_PIN(31), 792 SERVALT_PIN(32), 793 SERVALT_PIN(33), 794 SERVALT_PIN(34), 795 SERVALT_PIN(35), 796 SERVALT_PIN(36), 797 }; 798 799 #define SPARX5_P(p, f0, f1, f2) \ 800 static struct ocelot_pin_caps sparx5_pin_##p = { \ 801 .pin = p, \ 802 .functions = { \ 803 FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2 \ 804 }, \ 805 } 806 807 SPARX5_P(0, SG0, PLL_STAT, NONE); 808 SPARX5_P(1, SG0, NONE, NONE); 809 SPARX5_P(2, SG0, NONE, NONE); 810 SPARX5_P(3, SG0, NONE, NONE); 811 SPARX5_P(4, SG1, NONE, NONE); 812 SPARX5_P(5, SG1, NONE, NONE); 813 SPARX5_P(6, IRQ0_IN, IRQ0_OUT, SFP); 814 SPARX5_P(7, IRQ1_IN, IRQ1_OUT, SFP); 815 SPARX5_P(8, PTP0, NONE, SFP); 816 SPARX5_P(9, PTP1, SFP, TWI_SCL_M); 817 SPARX5_P(10, UART, NONE, NONE); 818 SPARX5_P(11, UART, NONE, NONE); 819 SPARX5_P(12, SG1, NONE, NONE); 820 SPARX5_P(13, SG1, NONE, NONE); 821 SPARX5_P(14, TWI, TWI_SCL_M, NONE); 822 SPARX5_P(15, TWI, NONE, NONE); 823 SPARX5_P(16, SI, TWI_SCL_M, SFP); 824 SPARX5_P(17, SI, TWI_SCL_M, SFP); 825 SPARX5_P(18, SI, TWI_SCL_M, SFP); 826 SPARX5_P(19, PCI_WAKE, TWI_SCL_M, SFP); 827 SPARX5_P(20, IRQ0_OUT, TWI_SCL_M, SFP); 828 SPARX5_P(21, IRQ1_OUT, TACHO, SFP); 829 SPARX5_P(22, TACHO, IRQ0_OUT, TWI_SCL_M); 830 SPARX5_P(23, PWM, UART3, TWI_SCL_M); 831 SPARX5_P(24, PTP2, UART3, TWI_SCL_M); 832 SPARX5_P(25, PTP3, SI, TWI_SCL_M); 833 SPARX5_P(26, UART2, SI, TWI_SCL_M); 834 SPARX5_P(27, UART2, SI, TWI_SCL_M); 835 SPARX5_P(28, TWI2, SI, SFP); 836 SPARX5_P(29, TWI2, SI, SFP); 837 SPARX5_P(30, SG2, SI, PWM); 838 SPARX5_P(31, SG2, SI, TWI_SCL_M); 839 SPARX5_P(32, SG2, SI, TWI_SCL_M); 840 SPARX5_P(33, SG2, SI, SFP); 841 SPARX5_P(34, NONE, TWI_SCL_M, EMMC); 842 SPARX5_P(35, SFP, TWI_SCL_M, EMMC); 843 SPARX5_P(36, SFP, TWI_SCL_M, EMMC); 844 SPARX5_P(37, SFP, NONE, EMMC); 845 SPARX5_P(38, NONE, TWI_SCL_M, EMMC); 846 SPARX5_P(39, SI2, TWI_SCL_M, EMMC); 847 SPARX5_P(40, SI2, TWI_SCL_M, EMMC); 848 SPARX5_P(41, SI2, TWI_SCL_M, EMMC); 849 SPARX5_P(42, SI2, TWI_SCL_M, EMMC); 850 SPARX5_P(43, SI2, TWI_SCL_M, EMMC); 851 SPARX5_P(44, SI, SFP, EMMC); 852 SPARX5_P(45, SI, SFP, EMMC); 853 SPARX5_P(46, NONE, SFP, EMMC); 854 SPARX5_P(47, NONE, SFP, EMMC); 855 SPARX5_P(48, TWI3, SI, SFP); 856 SPARX5_P(49, TWI3, NONE, SFP); 857 SPARX5_P(50, SFP, NONE, TWI_SCL_M); 858 SPARX5_P(51, SFP, SI, TWI_SCL_M); 859 SPARX5_P(52, SFP, MIIM, TWI_SCL_M); 860 SPARX5_P(53, SFP, MIIM, TWI_SCL_M); 861 SPARX5_P(54, SFP, PTP2, TWI_SCL_M); 862 SPARX5_P(55, SFP, PTP3, PCI_WAKE); 863 SPARX5_P(56, MIIM, SFP, TWI_SCL_M); 864 SPARX5_P(57, MIIM, SFP, TWI_SCL_M); 865 SPARX5_P(58, MIIM, SFP, TWI_SCL_M); 866 SPARX5_P(59, MIIM, SFP, NONE); 867 SPARX5_P(60, RECO_CLK, NONE, NONE); 868 SPARX5_P(61, RECO_CLK, NONE, NONE); 869 SPARX5_P(62, RECO_CLK, PLL_STAT, NONE); 870 SPARX5_P(63, RECO_CLK, NONE, NONE); 871 872 #define SPARX5_PIN(n) { \ 873 .number = n, \ 874 .name = "GPIO_"#n, \ 875 .drv_data = &sparx5_pin_##n \ 876 } 877 878 static const struct pinctrl_pin_desc sparx5_pins[] = { 879 SPARX5_PIN(0), 880 SPARX5_PIN(1), 881 SPARX5_PIN(2), 882 SPARX5_PIN(3), 883 SPARX5_PIN(4), 884 SPARX5_PIN(5), 885 SPARX5_PIN(6), 886 SPARX5_PIN(7), 887 SPARX5_PIN(8), 888 SPARX5_PIN(9), 889 SPARX5_PIN(10), 890 SPARX5_PIN(11), 891 SPARX5_PIN(12), 892 SPARX5_PIN(13), 893 SPARX5_PIN(14), 894 SPARX5_PIN(15), 895 SPARX5_PIN(16), 896 SPARX5_PIN(17), 897 SPARX5_PIN(18), 898 SPARX5_PIN(19), 899 SPARX5_PIN(20), 900 SPARX5_PIN(21), 901 SPARX5_PIN(22), 902 SPARX5_PIN(23), 903 SPARX5_PIN(24), 904 SPARX5_PIN(25), 905 SPARX5_PIN(26), 906 SPARX5_PIN(27), 907 SPARX5_PIN(28), 908 SPARX5_PIN(29), 909 SPARX5_PIN(30), 910 SPARX5_PIN(31), 911 SPARX5_PIN(32), 912 SPARX5_PIN(33), 913 SPARX5_PIN(34), 914 SPARX5_PIN(35), 915 SPARX5_PIN(36), 916 SPARX5_PIN(37), 917 SPARX5_PIN(38), 918 SPARX5_PIN(39), 919 SPARX5_PIN(40), 920 SPARX5_PIN(41), 921 SPARX5_PIN(42), 922 SPARX5_PIN(43), 923 SPARX5_PIN(44), 924 SPARX5_PIN(45), 925 SPARX5_PIN(46), 926 SPARX5_PIN(47), 927 SPARX5_PIN(48), 928 SPARX5_PIN(49), 929 SPARX5_PIN(50), 930 SPARX5_PIN(51), 931 SPARX5_PIN(52), 932 SPARX5_PIN(53), 933 SPARX5_PIN(54), 934 SPARX5_PIN(55), 935 SPARX5_PIN(56), 936 SPARX5_PIN(57), 937 SPARX5_PIN(58), 938 SPARX5_PIN(59), 939 SPARX5_PIN(60), 940 SPARX5_PIN(61), 941 SPARX5_PIN(62), 942 SPARX5_PIN(63), 943 }; 944 945 #define LAN966X_P(p, f0, f1, f2, f3, f4, f5, f6, f7) \ 946 static struct ocelot_pin_caps lan966x_pin_##p = { \ 947 .pin = p, \ 948 .functions = { \ 949 FUNC_##f0, FUNC_##f1, FUNC_##f2, \ 950 FUNC_##f3 \ 951 }, \ 952 .a_functions = { \ 953 FUNC_##f4, FUNC_##f5, FUNC_##f6, \ 954 FUNC_##f7 \ 955 }, \ 956 } 957 958 /* Pinmuxing table taken from data sheet */ 959 /* Pin FUNC0 FUNC1 FUNC2 FUNC3 FUNC4 FUNC5 FUNC6 FUNC7 */ 960 LAN966X_P(0, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 961 LAN966X_P(1, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 962 LAN966X_P(2, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 963 LAN966X_P(3, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 964 LAN966X_P(4, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 965 LAN966X_P(5, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 966 LAN966X_P(6, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 967 LAN966X_P(7, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 968 LAN966X_P(8, GPIO, FC0_a, USB_H_b, NONE, USB_S_b, NONE, NONE, R); 969 LAN966X_P(9, GPIO, FC0_a, USB_H_b, NONE, NONE, NONE, NONE, R); 970 LAN966X_P(10, GPIO, FC0_a, NONE, NONE, NONE, NONE, NONE, R); 971 LAN966X_P(11, GPIO, FC1_a, NONE, NONE, NONE, NONE, NONE, R); 972 LAN966X_P(12, GPIO, FC1_a, NONE, NONE, NONE, NONE, NONE, R); 973 LAN966X_P(13, GPIO, FC1_a, NONE, NONE, NONE, NONE, NONE, R); 974 LAN966X_P(14, GPIO, FC2_a, NONE, NONE, NONE, NONE, NONE, R); 975 LAN966X_P(15, GPIO, FC2_a, NONE, NONE, NONE, NONE, NONE, R); 976 LAN966X_P(16, GPIO, FC2_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, IRQ_OUT_c, R); 977 LAN966X_P(17, GPIO, FC3_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, IRQ_OUT_c, R); 978 LAN966X_P(18, GPIO, FC3_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, IRQ_OUT_c, R); 979 LAN966X_P(19, GPIO, FC3_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, IRQ_OUT_c, R); 980 LAN966X_P(20, GPIO, FC4_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, NONE, R); 981 LAN966X_P(21, GPIO, FC4_a, NONE, NONE, OB_TRG_a, NONE, NONE, R); 982 LAN966X_P(22, GPIO, FC4_a, NONE, NONE, OB_TRG_a, NONE, NONE, R); 983 LAN966X_P(23, GPIO, NONE, NONE, NONE, OB_TRG_a, NONE, NONE, R); 984 LAN966X_P(24, GPIO, FC0_b, IB_TRG_a, USB_H_c, OB_TRG_a, IRQ_IN_c, TACHO_a, R); 985 LAN966X_P(25, GPIO, FC0_b, IB_TRG_a, USB_H_c, OB_TRG_a, IRQ_OUT_c, SFP_SD, R); 986 LAN966X_P(26, GPIO, FC0_b, IB_TRG_a, USB_S_c, OB_TRG_a, CAN0_a, SFP_SD, R); 987 LAN966X_P(27, GPIO, NONE, NONE, NONE, OB_TRG_a, CAN0_a, PWM_a, R); 988 LAN966X_P(28, GPIO, MIIM_a, NONE, NONE, OB_TRG_a, IRQ_OUT_c, SFP_SD, R); 989 LAN966X_P(29, GPIO, MIIM_a, NONE, NONE, OB_TRG_a, NONE, NONE, R); 990 LAN966X_P(30, GPIO, FC3_c, CAN1, CLKMON, OB_TRG, RECO_b, NONE, R); 991 LAN966X_P(31, GPIO, FC3_c, CAN1, CLKMON, OB_TRG, RECO_b, NONE, R); 992 LAN966X_P(32, GPIO, FC3_c, NONE, SGPIO_a, NONE, MIIM_Sa, NONE, R); 993 LAN966X_P(33, GPIO, FC1_b, NONE, SGPIO_a, NONE, MIIM_Sa, MIIM_b, R); 994 LAN966X_P(34, GPIO, FC1_b, NONE, SGPIO_a, NONE, MIIM_Sa, MIIM_b, R); 995 LAN966X_P(35, GPIO, FC1_b, PTPSYNC_0, SGPIO_a, CAN0_b, NONE, NONE, R); 996 LAN966X_P(36, GPIO, NONE, PTPSYNC_1, NONE, CAN0_b, NONE, NONE, R); 997 LAN966X_P(37, GPIO, FC_SHRD0, PTPSYNC_2, TWI_SLC_GATE_AD, NONE, NONE, NONE, R); 998 LAN966X_P(38, GPIO, NONE, PTPSYNC_3, NONE, NONE, NONE, NONE, R); 999 LAN966X_P(39, GPIO, NONE, PTPSYNC_4, NONE, NONE, NONE, NONE, R); 1000 LAN966X_P(40, GPIO, FC_SHRD1, PTPSYNC_5, NONE, NONE, NONE, NONE, R); 1001 LAN966X_P(41, GPIO, FC_SHRD2, PTPSYNC_6, TWI_SLC_GATE_AD, NONE, NONE, NONE, R); 1002 LAN966X_P(42, GPIO, FC_SHRD3, PTPSYNC_7, TWI_SLC_GATE_AD, NONE, NONE, NONE, R); 1003 LAN966X_P(43, GPIO, FC2_b, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, RECO_a, IRQ_IN_a, R); 1004 LAN966X_P(44, GPIO, FC2_b, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, RECO_a, IRQ_IN_a, R); 1005 LAN966X_P(45, GPIO, FC2_b, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, NONE, IRQ_IN_a, R); 1006 LAN966X_P(46, GPIO, FC1_c, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, FC_SHRD4, IRQ_IN_a, R); 1007 LAN966X_P(47, GPIO, FC1_c, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, FC_SHRD5, IRQ_IN_a, R); 1008 LAN966X_P(48, GPIO, FC1_c, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, FC_SHRD6, IRQ_IN_a, R); 1009 LAN966X_P(49, GPIO, FC_SHRD7, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, TWI_SLC_GATE, IRQ_IN_a, R); 1010 LAN966X_P(50, GPIO, FC_SHRD16, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, TWI_SLC_GATE, NONE, R); 1011 LAN966X_P(51, GPIO, FC3_b, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, PWM_b, IRQ_IN_b, R); 1012 LAN966X_P(52, GPIO, FC3_b, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, TACHO_b, IRQ_IN_b, R); 1013 LAN966X_P(53, GPIO, FC3_b, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, NONE, IRQ_IN_b, R); 1014 LAN966X_P(54, GPIO, FC_SHRD8, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, TWI_SLC_GATE, IRQ_IN_b, R); 1015 LAN966X_P(55, GPIO, FC_SHRD9, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, TWI_SLC_GATE, IRQ_IN_b, R); 1016 LAN966X_P(56, GPIO, FC4_b, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, FC_SHRD10, IRQ_IN_b, R); 1017 LAN966X_P(57, GPIO, FC4_b, TWI_SLC_GATE, IB_TRG_c, IRQ_OUT_b, FC_SHRD11, IRQ_IN_b, R); 1018 LAN966X_P(58, GPIO, FC4_b, TWI_SLC_GATE, IB_TRG_c, IRQ_OUT_b, FC_SHRD12, IRQ_IN_b, R); 1019 LAN966X_P(59, GPIO, QSPI1, MIIM_c, NONE, NONE, MIIM_Sb, NONE, R); 1020 LAN966X_P(60, GPIO, QSPI1, MIIM_c, NONE, NONE, MIIM_Sb, NONE, R); 1021 LAN966X_P(61, GPIO, QSPI1, NONE, SGPIO_b, FC0_c, MIIM_Sb, NONE, R); 1022 LAN966X_P(62, GPIO, QSPI1, FC_SHRD13, SGPIO_b, FC0_c, TWI_SLC_GATE, SFP_SD, R); 1023 LAN966X_P(63, GPIO, QSPI1, FC_SHRD14, SGPIO_b, FC0_c, TWI_SLC_GATE, SFP_SD, R); 1024 LAN966X_P(64, GPIO, QSPI1, FC4_c, SGPIO_b, FC_SHRD15, TWI_SLC_GATE, SFP_SD, R); 1025 LAN966X_P(65, GPIO, USB_H_a, FC4_c, NONE, IRQ_OUT_c, TWI_SLC_GATE_AD, NONE, R); 1026 LAN966X_P(66, GPIO, USB_H_a, FC4_c, USB_S_a, IRQ_OUT_c, IRQ_IN_c, NONE, R); 1027 LAN966X_P(67, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R); 1028 LAN966X_P(68, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R); 1029 LAN966X_P(69, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R); 1030 LAN966X_P(70, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R); 1031 LAN966X_P(71, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R); 1032 LAN966X_P(72, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R); 1033 LAN966X_P(73, GPIO, EMMC, NONE, NONE, SD, NONE, NONE, R); 1034 LAN966X_P(74, GPIO, EMMC, NONE, FC_SHRD17, SD, TWI_SLC_GATE, NONE, R); 1035 LAN966X_P(75, GPIO, EMMC, NONE, FC_SHRD18, SD, TWI_SLC_GATE, NONE, R); 1036 LAN966X_P(76, GPIO, EMMC, NONE, FC_SHRD19, SD, TWI_SLC_GATE, NONE, R); 1037 LAN966X_P(77, GPIO, EMMC_SD, NONE, FC_SHRD20, NONE, TWI_SLC_GATE, NONE, R); 1038 1039 #define LAN966X_PIN(n) { \ 1040 .number = n, \ 1041 .name = "GPIO_"#n, \ 1042 .drv_data = &lan966x_pin_##n \ 1043 } 1044 1045 static const struct pinctrl_pin_desc lan966x_pins[] = { 1046 LAN966X_PIN(0), 1047 LAN966X_PIN(1), 1048 LAN966X_PIN(2), 1049 LAN966X_PIN(3), 1050 LAN966X_PIN(4), 1051 LAN966X_PIN(5), 1052 LAN966X_PIN(6), 1053 LAN966X_PIN(7), 1054 LAN966X_PIN(8), 1055 LAN966X_PIN(9), 1056 LAN966X_PIN(10), 1057 LAN966X_PIN(11), 1058 LAN966X_PIN(12), 1059 LAN966X_PIN(13), 1060 LAN966X_PIN(14), 1061 LAN966X_PIN(15), 1062 LAN966X_PIN(16), 1063 LAN966X_PIN(17), 1064 LAN966X_PIN(18), 1065 LAN966X_PIN(19), 1066 LAN966X_PIN(20), 1067 LAN966X_PIN(21), 1068 LAN966X_PIN(22), 1069 LAN966X_PIN(23), 1070 LAN966X_PIN(24), 1071 LAN966X_PIN(25), 1072 LAN966X_PIN(26), 1073 LAN966X_PIN(27), 1074 LAN966X_PIN(28), 1075 LAN966X_PIN(29), 1076 LAN966X_PIN(30), 1077 LAN966X_PIN(31), 1078 LAN966X_PIN(32), 1079 LAN966X_PIN(33), 1080 LAN966X_PIN(34), 1081 LAN966X_PIN(35), 1082 LAN966X_PIN(36), 1083 LAN966X_PIN(37), 1084 LAN966X_PIN(38), 1085 LAN966X_PIN(39), 1086 LAN966X_PIN(40), 1087 LAN966X_PIN(41), 1088 LAN966X_PIN(42), 1089 LAN966X_PIN(43), 1090 LAN966X_PIN(44), 1091 LAN966X_PIN(45), 1092 LAN966X_PIN(46), 1093 LAN966X_PIN(47), 1094 LAN966X_PIN(48), 1095 LAN966X_PIN(49), 1096 LAN966X_PIN(50), 1097 LAN966X_PIN(51), 1098 LAN966X_PIN(52), 1099 LAN966X_PIN(53), 1100 LAN966X_PIN(54), 1101 LAN966X_PIN(55), 1102 LAN966X_PIN(56), 1103 LAN966X_PIN(57), 1104 LAN966X_PIN(58), 1105 LAN966X_PIN(59), 1106 LAN966X_PIN(60), 1107 LAN966X_PIN(61), 1108 LAN966X_PIN(62), 1109 LAN966X_PIN(63), 1110 LAN966X_PIN(64), 1111 LAN966X_PIN(65), 1112 LAN966X_PIN(66), 1113 LAN966X_PIN(67), 1114 LAN966X_PIN(68), 1115 LAN966X_PIN(69), 1116 LAN966X_PIN(70), 1117 LAN966X_PIN(71), 1118 LAN966X_PIN(72), 1119 LAN966X_PIN(73), 1120 LAN966X_PIN(74), 1121 LAN966X_PIN(75), 1122 LAN966X_PIN(76), 1123 LAN966X_PIN(77), 1124 }; 1125 1126 static int ocelot_get_functions_count(struct pinctrl_dev *pctldev) 1127 { 1128 return ARRAY_SIZE(ocelot_function_names); 1129 } 1130 1131 static const char *ocelot_get_function_name(struct pinctrl_dev *pctldev, 1132 unsigned int function) 1133 { 1134 return ocelot_function_names[function]; 1135 } 1136 1137 static int ocelot_get_function_groups(struct pinctrl_dev *pctldev, 1138 unsigned int function, 1139 const char *const **groups, 1140 unsigned *const num_groups) 1141 { 1142 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1143 1144 *groups = info->func[function].groups; 1145 *num_groups = info->func[function].ngroups; 1146 1147 return 0; 1148 } 1149 1150 static int ocelot_pin_function_idx(struct ocelot_pinctrl *info, 1151 unsigned int pin, unsigned int function) 1152 { 1153 struct ocelot_pin_caps *p = info->desc->pins[pin].drv_data; 1154 int i; 1155 1156 for (i = 0; i < OCELOT_FUNC_PER_PIN; i++) { 1157 if (function == p->functions[i]) 1158 return i; 1159 1160 if (function == p->a_functions[i]) 1161 return i + OCELOT_FUNC_PER_PIN; 1162 } 1163 1164 return -1; 1165 } 1166 1167 #define REG_ALT(msb, info, p) (OCELOT_GPIO_ALT0 * (info)->stride + 4 * ((msb) + ((info)->stride * ((p) / 32)))) 1168 1169 static int ocelot_pinmux_set_mux(struct pinctrl_dev *pctldev, 1170 unsigned int selector, unsigned int group) 1171 { 1172 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1173 struct ocelot_pin_caps *pin = info->desc->pins[group].drv_data; 1174 unsigned int p = pin->pin % 32; 1175 int f; 1176 1177 f = ocelot_pin_function_idx(info, group, selector); 1178 if (f < 0) 1179 return -EINVAL; 1180 1181 /* 1182 * f is encoded on two bits. 1183 * bit 0 of f goes in BIT(pin) of ALT[0], bit 1 of f goes in BIT(pin) of 1184 * ALT[1] 1185 * This is racy because both registers can't be updated at the same time 1186 * but it doesn't matter much for now. 1187 * Note: ALT0/ALT1 are organized specially for 64 gpio targets 1188 */ 1189 regmap_update_bits(info->map, REG_ALT(0, info, pin->pin), 1190 BIT(p), f << p); 1191 regmap_update_bits(info->map, REG_ALT(1, info, pin->pin), 1192 BIT(p), f << (p - 1)); 1193 1194 return 0; 1195 } 1196 1197 static int lan966x_pinmux_set_mux(struct pinctrl_dev *pctldev, 1198 unsigned int selector, unsigned int group) 1199 { 1200 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1201 struct ocelot_pin_caps *pin = info->desc->pins[group].drv_data; 1202 unsigned int p = pin->pin % 32; 1203 int f; 1204 1205 f = ocelot_pin_function_idx(info, group, selector); 1206 if (f < 0) 1207 return -EINVAL; 1208 1209 /* 1210 * f is encoded on three bits. 1211 * bit 0 of f goes in BIT(pin) of ALT[0], bit 1 of f goes in BIT(pin) of 1212 * ALT[1], bit 2 of f goes in BIT(pin) of ALT[2] 1213 * This is racy because three registers can't be updated at the same time 1214 * but it doesn't matter much for now. 1215 * Note: ALT0/ALT1/ALT2 are organized specially for 78 gpio targets 1216 */ 1217 regmap_update_bits(info->map, REG_ALT(0, info, pin->pin), 1218 BIT(p), f << p); 1219 regmap_update_bits(info->map, REG_ALT(1, info, pin->pin), 1220 BIT(p), (f >> 1) << p); 1221 regmap_update_bits(info->map, REG_ALT(2, info, pin->pin), 1222 BIT(p), (f >> 2) << p); 1223 1224 return 0; 1225 } 1226 1227 #define REG(r, info, p) ((r) * (info)->stride + (4 * ((p) / 32))) 1228 1229 static int ocelot_gpio_set_direction(struct pinctrl_dev *pctldev, 1230 struct pinctrl_gpio_range *range, 1231 unsigned int pin, bool input) 1232 { 1233 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1234 unsigned int p = pin % 32; 1235 1236 regmap_update_bits(info->map, REG(OCELOT_GPIO_OE, info, pin), BIT(p), 1237 input ? 0 : BIT(p)); 1238 1239 return 0; 1240 } 1241 1242 static int ocelot_gpio_request_enable(struct pinctrl_dev *pctldev, 1243 struct pinctrl_gpio_range *range, 1244 unsigned int offset) 1245 { 1246 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1247 unsigned int p = offset % 32; 1248 1249 regmap_update_bits(info->map, REG_ALT(0, info, offset), 1250 BIT(p), 0); 1251 regmap_update_bits(info->map, REG_ALT(1, info, offset), 1252 BIT(p), 0); 1253 1254 return 0; 1255 } 1256 1257 static int lan966x_gpio_request_enable(struct pinctrl_dev *pctldev, 1258 struct pinctrl_gpio_range *range, 1259 unsigned int offset) 1260 { 1261 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1262 unsigned int p = offset % 32; 1263 1264 regmap_update_bits(info->map, REG_ALT(0, info, offset), 1265 BIT(p), 0); 1266 regmap_update_bits(info->map, REG_ALT(1, info, offset), 1267 BIT(p), 0); 1268 regmap_update_bits(info->map, REG_ALT(2, info, offset), 1269 BIT(p), 0); 1270 1271 return 0; 1272 } 1273 1274 static const struct pinmux_ops ocelot_pmx_ops = { 1275 .get_functions_count = ocelot_get_functions_count, 1276 .get_function_name = ocelot_get_function_name, 1277 .get_function_groups = ocelot_get_function_groups, 1278 .set_mux = ocelot_pinmux_set_mux, 1279 .gpio_set_direction = ocelot_gpio_set_direction, 1280 .gpio_request_enable = ocelot_gpio_request_enable, 1281 }; 1282 1283 static const struct pinmux_ops lan966x_pmx_ops = { 1284 .get_functions_count = ocelot_get_functions_count, 1285 .get_function_name = ocelot_get_function_name, 1286 .get_function_groups = ocelot_get_function_groups, 1287 .set_mux = lan966x_pinmux_set_mux, 1288 .gpio_set_direction = ocelot_gpio_set_direction, 1289 .gpio_request_enable = lan966x_gpio_request_enable, 1290 }; 1291 1292 static int ocelot_pctl_get_groups_count(struct pinctrl_dev *pctldev) 1293 { 1294 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1295 1296 return info->desc->npins; 1297 } 1298 1299 static const char *ocelot_pctl_get_group_name(struct pinctrl_dev *pctldev, 1300 unsigned int group) 1301 { 1302 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1303 1304 return info->desc->pins[group].name; 1305 } 1306 1307 static int ocelot_pctl_get_group_pins(struct pinctrl_dev *pctldev, 1308 unsigned int group, 1309 const unsigned int **pins, 1310 unsigned int *num_pins) 1311 { 1312 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1313 1314 *pins = &info->desc->pins[group].number; 1315 *num_pins = 1; 1316 1317 return 0; 1318 } 1319 1320 static int ocelot_hw_get_value(struct ocelot_pinctrl *info, 1321 unsigned int pin, 1322 unsigned int reg, 1323 int *val) 1324 { 1325 int ret = -EOPNOTSUPP; 1326 1327 if (info->pincfg) { 1328 u32 regcfg; 1329 1330 ret = regmap_read(info->pincfg, pin, ®cfg); 1331 if (ret) 1332 return ret; 1333 1334 ret = 0; 1335 switch (reg) { 1336 case PINCONF_BIAS: 1337 *val = regcfg & BIAS_BITS; 1338 break; 1339 1340 case PINCONF_SCHMITT: 1341 *val = regcfg & SCHMITT_BIT; 1342 break; 1343 1344 case PINCONF_DRIVE_STRENGTH: 1345 *val = regcfg & DRIVE_BITS; 1346 break; 1347 1348 default: 1349 ret = -EOPNOTSUPP; 1350 break; 1351 } 1352 } 1353 return ret; 1354 } 1355 1356 static int ocelot_pincfg_clrsetbits(struct ocelot_pinctrl *info, u32 regaddr, 1357 u32 clrbits, u32 setbits) 1358 { 1359 u32 val; 1360 int ret; 1361 1362 ret = regmap_read(info->pincfg, regaddr, &val); 1363 if (ret) 1364 return ret; 1365 1366 val &= ~clrbits; 1367 val |= setbits; 1368 1369 ret = regmap_write(info->pincfg, regaddr, val); 1370 1371 return ret; 1372 } 1373 1374 static int ocelot_hw_set_value(struct ocelot_pinctrl *info, 1375 unsigned int pin, 1376 unsigned int reg, 1377 int val) 1378 { 1379 int ret = -EOPNOTSUPP; 1380 1381 if (info->pincfg) { 1382 1383 ret = 0; 1384 switch (reg) { 1385 case PINCONF_BIAS: 1386 ret = ocelot_pincfg_clrsetbits(info, pin, BIAS_BITS, 1387 val); 1388 break; 1389 1390 case PINCONF_SCHMITT: 1391 ret = ocelot_pincfg_clrsetbits(info, pin, SCHMITT_BIT, 1392 val); 1393 break; 1394 1395 case PINCONF_DRIVE_STRENGTH: 1396 if (val <= 3) 1397 ret = ocelot_pincfg_clrsetbits(info, pin, 1398 DRIVE_BITS, val); 1399 else 1400 ret = -EINVAL; 1401 break; 1402 1403 default: 1404 ret = -EOPNOTSUPP; 1405 break; 1406 } 1407 } 1408 return ret; 1409 } 1410 1411 static int ocelot_pinconf_get(struct pinctrl_dev *pctldev, 1412 unsigned int pin, unsigned long *config) 1413 { 1414 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1415 u32 param = pinconf_to_config_param(*config); 1416 int val, err; 1417 1418 switch (param) { 1419 case PIN_CONFIG_BIAS_DISABLE: 1420 case PIN_CONFIG_BIAS_PULL_UP: 1421 case PIN_CONFIG_BIAS_PULL_DOWN: 1422 err = ocelot_hw_get_value(info, pin, PINCONF_BIAS, &val); 1423 if (err) 1424 return err; 1425 if (param == PIN_CONFIG_BIAS_DISABLE) 1426 val = (val == 0); 1427 else if (param == PIN_CONFIG_BIAS_PULL_DOWN) 1428 val = (val & BIAS_PD_BIT ? true : false); 1429 else /* PIN_CONFIG_BIAS_PULL_UP */ 1430 val = (val & BIAS_PU_BIT ? true : false); 1431 break; 1432 1433 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 1434 err = ocelot_hw_get_value(info, pin, PINCONF_SCHMITT, &val); 1435 if (err) 1436 return err; 1437 1438 val = (val & SCHMITT_BIT ? true : false); 1439 break; 1440 1441 case PIN_CONFIG_DRIVE_STRENGTH: 1442 err = ocelot_hw_get_value(info, pin, PINCONF_DRIVE_STRENGTH, 1443 &val); 1444 if (err) 1445 return err; 1446 break; 1447 1448 case PIN_CONFIG_OUTPUT: 1449 err = regmap_read(info->map, REG(OCELOT_GPIO_OUT, info, pin), 1450 &val); 1451 if (err) 1452 return err; 1453 val = !!(val & BIT(pin % 32)); 1454 break; 1455 1456 case PIN_CONFIG_INPUT_ENABLE: 1457 case PIN_CONFIG_OUTPUT_ENABLE: 1458 err = regmap_read(info->map, REG(OCELOT_GPIO_OE, info, pin), 1459 &val); 1460 if (err) 1461 return err; 1462 val = val & BIT(pin % 32); 1463 if (param == PIN_CONFIG_OUTPUT_ENABLE) 1464 val = !!val; 1465 else 1466 val = !val; 1467 break; 1468 1469 default: 1470 return -EOPNOTSUPP; 1471 } 1472 1473 *config = pinconf_to_config_packed(param, val); 1474 1475 return 0; 1476 } 1477 1478 static int ocelot_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 1479 unsigned long *configs, unsigned int num_configs) 1480 { 1481 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1482 u32 param, arg, p; 1483 int cfg, err = 0; 1484 1485 for (cfg = 0; cfg < num_configs; cfg++) { 1486 param = pinconf_to_config_param(configs[cfg]); 1487 arg = pinconf_to_config_argument(configs[cfg]); 1488 1489 switch (param) { 1490 case PIN_CONFIG_BIAS_DISABLE: 1491 case PIN_CONFIG_BIAS_PULL_UP: 1492 case PIN_CONFIG_BIAS_PULL_DOWN: 1493 arg = (param == PIN_CONFIG_BIAS_DISABLE) ? 0 : 1494 (param == PIN_CONFIG_BIAS_PULL_UP) ? BIAS_PU_BIT : 1495 BIAS_PD_BIT; 1496 1497 err = ocelot_hw_set_value(info, pin, PINCONF_BIAS, arg); 1498 if (err) 1499 goto err; 1500 1501 break; 1502 1503 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 1504 arg = arg ? SCHMITT_BIT : 0; 1505 err = ocelot_hw_set_value(info, pin, PINCONF_SCHMITT, 1506 arg); 1507 if (err) 1508 goto err; 1509 1510 break; 1511 1512 case PIN_CONFIG_DRIVE_STRENGTH: 1513 err = ocelot_hw_set_value(info, pin, 1514 PINCONF_DRIVE_STRENGTH, 1515 arg); 1516 if (err) 1517 goto err; 1518 1519 break; 1520 1521 case PIN_CONFIG_OUTPUT_ENABLE: 1522 case PIN_CONFIG_INPUT_ENABLE: 1523 case PIN_CONFIG_OUTPUT: 1524 p = pin % 32; 1525 if (arg) 1526 regmap_write(info->map, 1527 REG(OCELOT_GPIO_OUT_SET, info, 1528 pin), 1529 BIT(p)); 1530 else 1531 regmap_write(info->map, 1532 REG(OCELOT_GPIO_OUT_CLR, info, 1533 pin), 1534 BIT(p)); 1535 regmap_update_bits(info->map, 1536 REG(OCELOT_GPIO_OE, info, pin), 1537 BIT(p), 1538 param == PIN_CONFIG_INPUT_ENABLE ? 1539 0 : BIT(p)); 1540 break; 1541 1542 default: 1543 err = -EOPNOTSUPP; 1544 } 1545 } 1546 err: 1547 return err; 1548 } 1549 1550 static const struct pinconf_ops ocelot_confops = { 1551 .is_generic = true, 1552 .pin_config_get = ocelot_pinconf_get, 1553 .pin_config_set = ocelot_pinconf_set, 1554 .pin_config_config_dbg_show = pinconf_generic_dump_config, 1555 }; 1556 1557 static const struct pinctrl_ops ocelot_pctl_ops = { 1558 .get_groups_count = ocelot_pctl_get_groups_count, 1559 .get_group_name = ocelot_pctl_get_group_name, 1560 .get_group_pins = ocelot_pctl_get_group_pins, 1561 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, 1562 .dt_free_map = pinconf_generic_dt_free_map, 1563 }; 1564 1565 static struct pinctrl_desc luton_desc = { 1566 .name = "luton-pinctrl", 1567 .pins = luton_pins, 1568 .npins = ARRAY_SIZE(luton_pins), 1569 .pctlops = &ocelot_pctl_ops, 1570 .pmxops = &ocelot_pmx_ops, 1571 .owner = THIS_MODULE, 1572 }; 1573 1574 static struct pinctrl_desc serval_desc = { 1575 .name = "serval-pinctrl", 1576 .pins = serval_pins, 1577 .npins = ARRAY_SIZE(serval_pins), 1578 .pctlops = &ocelot_pctl_ops, 1579 .pmxops = &ocelot_pmx_ops, 1580 .owner = THIS_MODULE, 1581 }; 1582 1583 static struct pinctrl_desc ocelot_desc = { 1584 .name = "ocelot-pinctrl", 1585 .pins = ocelot_pins, 1586 .npins = ARRAY_SIZE(ocelot_pins), 1587 .pctlops = &ocelot_pctl_ops, 1588 .pmxops = &ocelot_pmx_ops, 1589 .owner = THIS_MODULE, 1590 }; 1591 1592 static struct pinctrl_desc jaguar2_desc = { 1593 .name = "jaguar2-pinctrl", 1594 .pins = jaguar2_pins, 1595 .npins = ARRAY_SIZE(jaguar2_pins), 1596 .pctlops = &ocelot_pctl_ops, 1597 .pmxops = &ocelot_pmx_ops, 1598 .owner = THIS_MODULE, 1599 }; 1600 1601 static struct pinctrl_desc servalt_desc = { 1602 .name = "servalt-pinctrl", 1603 .pins = servalt_pins, 1604 .npins = ARRAY_SIZE(servalt_pins), 1605 .pctlops = &ocelot_pctl_ops, 1606 .pmxops = &ocelot_pmx_ops, 1607 .owner = THIS_MODULE, 1608 }; 1609 1610 static struct pinctrl_desc sparx5_desc = { 1611 .name = "sparx5-pinctrl", 1612 .pins = sparx5_pins, 1613 .npins = ARRAY_SIZE(sparx5_pins), 1614 .pctlops = &ocelot_pctl_ops, 1615 .pmxops = &ocelot_pmx_ops, 1616 .confops = &ocelot_confops, 1617 .owner = THIS_MODULE, 1618 }; 1619 1620 static struct pinctrl_desc lan966x_desc = { 1621 .name = "lan966x-pinctrl", 1622 .pins = lan966x_pins, 1623 .npins = ARRAY_SIZE(lan966x_pins), 1624 .pctlops = &ocelot_pctl_ops, 1625 .pmxops = &lan966x_pmx_ops, 1626 .confops = &ocelot_confops, 1627 .owner = THIS_MODULE, 1628 }; 1629 1630 static int ocelot_create_group_func_map(struct device *dev, 1631 struct ocelot_pinctrl *info) 1632 { 1633 int f, npins, i; 1634 u8 *pins = kcalloc(info->desc->npins, sizeof(u8), GFP_KERNEL); 1635 1636 if (!pins) 1637 return -ENOMEM; 1638 1639 for (f = 0; f < FUNC_MAX; f++) { 1640 for (npins = 0, i = 0; i < info->desc->npins; i++) { 1641 if (ocelot_pin_function_idx(info, i, f) >= 0) 1642 pins[npins++] = i; 1643 } 1644 1645 if (!npins) 1646 continue; 1647 1648 info->func[f].ngroups = npins; 1649 info->func[f].groups = devm_kcalloc(dev, npins, sizeof(char *), 1650 GFP_KERNEL); 1651 if (!info->func[f].groups) { 1652 kfree(pins); 1653 return -ENOMEM; 1654 } 1655 1656 for (i = 0; i < npins; i++) 1657 info->func[f].groups[i] = 1658 info->desc->pins[pins[i]].name; 1659 } 1660 1661 kfree(pins); 1662 1663 return 0; 1664 } 1665 1666 static int ocelot_pinctrl_register(struct platform_device *pdev, 1667 struct ocelot_pinctrl *info) 1668 { 1669 int ret; 1670 1671 ret = ocelot_create_group_func_map(&pdev->dev, info); 1672 if (ret) { 1673 dev_err(&pdev->dev, "Unable to create group func map.\n"); 1674 return ret; 1675 } 1676 1677 info->pctl = devm_pinctrl_register(&pdev->dev, info->desc, info); 1678 if (IS_ERR(info->pctl)) { 1679 dev_err(&pdev->dev, "Failed to register pinctrl\n"); 1680 return PTR_ERR(info->pctl); 1681 } 1682 1683 return 0; 1684 } 1685 1686 static int ocelot_gpio_get(struct gpio_chip *chip, unsigned int offset) 1687 { 1688 struct ocelot_pinctrl *info = gpiochip_get_data(chip); 1689 unsigned int val; 1690 1691 regmap_read(info->map, REG(OCELOT_GPIO_IN, info, offset), &val); 1692 1693 return !!(val & BIT(offset % 32)); 1694 } 1695 1696 static void ocelot_gpio_set(struct gpio_chip *chip, unsigned int offset, 1697 int value) 1698 { 1699 struct ocelot_pinctrl *info = gpiochip_get_data(chip); 1700 1701 if (value) 1702 regmap_write(info->map, REG(OCELOT_GPIO_OUT_SET, info, offset), 1703 BIT(offset % 32)); 1704 else 1705 regmap_write(info->map, REG(OCELOT_GPIO_OUT_CLR, info, offset), 1706 BIT(offset % 32)); 1707 } 1708 1709 static int ocelot_gpio_get_direction(struct gpio_chip *chip, 1710 unsigned int offset) 1711 { 1712 struct ocelot_pinctrl *info = gpiochip_get_data(chip); 1713 unsigned int val; 1714 1715 regmap_read(info->map, REG(OCELOT_GPIO_OE, info, offset), &val); 1716 1717 if (val & BIT(offset % 32)) 1718 return GPIO_LINE_DIRECTION_OUT; 1719 1720 return GPIO_LINE_DIRECTION_IN; 1721 } 1722 1723 static int ocelot_gpio_direction_input(struct gpio_chip *chip, 1724 unsigned int offset) 1725 { 1726 return pinctrl_gpio_direction_input(chip->base + offset); 1727 } 1728 1729 static int ocelot_gpio_direction_output(struct gpio_chip *chip, 1730 unsigned int offset, int value) 1731 { 1732 struct ocelot_pinctrl *info = gpiochip_get_data(chip); 1733 unsigned int pin = BIT(offset % 32); 1734 1735 if (value) 1736 regmap_write(info->map, REG(OCELOT_GPIO_OUT_SET, info, offset), 1737 pin); 1738 else 1739 regmap_write(info->map, REG(OCELOT_GPIO_OUT_CLR, info, offset), 1740 pin); 1741 1742 return pinctrl_gpio_direction_output(chip->base + offset); 1743 } 1744 1745 static const struct gpio_chip ocelot_gpiolib_chip = { 1746 .request = gpiochip_generic_request, 1747 .free = gpiochip_generic_free, 1748 .set = ocelot_gpio_set, 1749 .get = ocelot_gpio_get, 1750 .get_direction = ocelot_gpio_get_direction, 1751 .direction_input = ocelot_gpio_direction_input, 1752 .direction_output = ocelot_gpio_direction_output, 1753 .owner = THIS_MODULE, 1754 }; 1755 1756 static void ocelot_irq_mask(struct irq_data *data) 1757 { 1758 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 1759 struct ocelot_pinctrl *info = gpiochip_get_data(chip); 1760 unsigned int gpio = irqd_to_hwirq(data); 1761 1762 regmap_update_bits(info->map, REG(OCELOT_GPIO_INTR_ENA, info, gpio), 1763 BIT(gpio % 32), 0); 1764 } 1765 1766 static void ocelot_irq_unmask(struct irq_data *data) 1767 { 1768 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 1769 struct ocelot_pinctrl *info = gpiochip_get_data(chip); 1770 unsigned int gpio = irqd_to_hwirq(data); 1771 1772 regmap_update_bits(info->map, REG(OCELOT_GPIO_INTR_ENA, info, gpio), 1773 BIT(gpio % 32), BIT(gpio % 32)); 1774 } 1775 1776 static void ocelot_irq_ack(struct irq_data *data) 1777 { 1778 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 1779 struct ocelot_pinctrl *info = gpiochip_get_data(chip); 1780 unsigned int gpio = irqd_to_hwirq(data); 1781 1782 regmap_write_bits(info->map, REG(OCELOT_GPIO_INTR, info, gpio), 1783 BIT(gpio % 32), BIT(gpio % 32)); 1784 } 1785 1786 static int ocelot_irq_set_type(struct irq_data *data, unsigned int type); 1787 1788 static struct irq_chip ocelot_eoi_irqchip = { 1789 .name = "gpio", 1790 .irq_mask = ocelot_irq_mask, 1791 .irq_eoi = ocelot_irq_ack, 1792 .irq_unmask = ocelot_irq_unmask, 1793 .flags = IRQCHIP_EOI_THREADED | IRQCHIP_EOI_IF_HANDLED, 1794 .irq_set_type = ocelot_irq_set_type, 1795 }; 1796 1797 static struct irq_chip ocelot_irqchip = { 1798 .name = "gpio", 1799 .irq_mask = ocelot_irq_mask, 1800 .irq_ack = ocelot_irq_ack, 1801 .irq_unmask = ocelot_irq_unmask, 1802 .irq_set_type = ocelot_irq_set_type, 1803 }; 1804 1805 static int ocelot_irq_set_type(struct irq_data *data, unsigned int type) 1806 { 1807 type &= IRQ_TYPE_SENSE_MASK; 1808 1809 if (!(type & (IRQ_TYPE_EDGE_BOTH | IRQ_TYPE_LEVEL_HIGH))) 1810 return -EINVAL; 1811 1812 if (type & IRQ_TYPE_LEVEL_HIGH) 1813 irq_set_chip_handler_name_locked(data, &ocelot_eoi_irqchip, 1814 handle_fasteoi_irq, NULL); 1815 if (type & IRQ_TYPE_EDGE_BOTH) 1816 irq_set_chip_handler_name_locked(data, &ocelot_irqchip, 1817 handle_edge_irq, NULL); 1818 1819 return 0; 1820 } 1821 1822 static void ocelot_irq_handler(struct irq_desc *desc) 1823 { 1824 struct irq_chip *parent_chip = irq_desc_get_chip(desc); 1825 struct gpio_chip *chip = irq_desc_get_handler_data(desc); 1826 struct ocelot_pinctrl *info = gpiochip_get_data(chip); 1827 unsigned int id_reg = OCELOT_GPIO_INTR_IDENT * info->stride; 1828 unsigned int reg = 0, irq, i; 1829 unsigned long irqs; 1830 1831 for (i = 0; i < info->stride; i++) { 1832 regmap_read(info->map, id_reg + 4 * i, ®); 1833 if (!reg) 1834 continue; 1835 1836 chained_irq_enter(parent_chip, desc); 1837 1838 irqs = reg; 1839 1840 for_each_set_bit(irq, &irqs, 1841 min(32U, info->desc->npins - 32 * i)) 1842 generic_handle_domain_irq(chip->irq.domain, irq + 32 * i); 1843 1844 chained_irq_exit(parent_chip, desc); 1845 } 1846 } 1847 1848 static int ocelot_gpiochip_register(struct platform_device *pdev, 1849 struct ocelot_pinctrl *info) 1850 { 1851 struct gpio_chip *gc; 1852 struct gpio_irq_chip *girq; 1853 int irq; 1854 1855 info->gpio_chip = ocelot_gpiolib_chip; 1856 1857 gc = &info->gpio_chip; 1858 gc->ngpio = info->desc->npins; 1859 gc->parent = &pdev->dev; 1860 gc->base = -1; 1861 gc->label = "ocelot-gpio"; 1862 1863 irq = platform_get_irq_optional(pdev, 0); 1864 if (irq > 0) { 1865 girq = &gc->irq; 1866 girq->chip = &ocelot_irqchip; 1867 girq->parent_handler = ocelot_irq_handler; 1868 girq->num_parents = 1; 1869 girq->parents = devm_kcalloc(&pdev->dev, 1, 1870 sizeof(*girq->parents), 1871 GFP_KERNEL); 1872 if (!girq->parents) 1873 return -ENOMEM; 1874 girq->parents[0] = irq; 1875 girq->default_type = IRQ_TYPE_NONE; 1876 girq->handler = handle_edge_irq; 1877 } 1878 1879 return devm_gpiochip_add_data(&pdev->dev, gc, info); 1880 } 1881 1882 static const struct of_device_id ocelot_pinctrl_of_match[] = { 1883 { .compatible = "mscc,luton-pinctrl", .data = &luton_desc }, 1884 { .compatible = "mscc,serval-pinctrl", .data = &serval_desc }, 1885 { .compatible = "mscc,ocelot-pinctrl", .data = &ocelot_desc }, 1886 { .compatible = "mscc,jaguar2-pinctrl", .data = &jaguar2_desc }, 1887 { .compatible = "mscc,servalt-pinctrl", .data = &servalt_desc }, 1888 { .compatible = "microchip,sparx5-pinctrl", .data = &sparx5_desc }, 1889 { .compatible = "microchip,lan966x-pinctrl", .data = &lan966x_desc }, 1890 {}, 1891 }; 1892 1893 static struct regmap *ocelot_pinctrl_create_pincfg(struct platform_device *pdev) 1894 { 1895 void __iomem *base; 1896 1897 const struct regmap_config regmap_config = { 1898 .reg_bits = 32, 1899 .val_bits = 32, 1900 .reg_stride = 4, 1901 .max_register = 32, 1902 .name = "pincfg", 1903 }; 1904 1905 base = devm_platform_ioremap_resource(pdev, 1); 1906 if (IS_ERR(base)) { 1907 dev_dbg(&pdev->dev, "Failed to ioremap config registers (no extended pinconf)\n"); 1908 return NULL; 1909 } 1910 1911 return devm_regmap_init_mmio(&pdev->dev, base, ®map_config); 1912 } 1913 1914 static int ocelot_pinctrl_probe(struct platform_device *pdev) 1915 { 1916 struct device *dev = &pdev->dev; 1917 struct ocelot_pinctrl *info; 1918 struct reset_control *reset; 1919 struct regmap *pincfg; 1920 void __iomem *base; 1921 int ret; 1922 struct regmap_config regmap_config = { 1923 .reg_bits = 32, 1924 .val_bits = 32, 1925 .reg_stride = 4, 1926 }; 1927 1928 info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL); 1929 if (!info) 1930 return -ENOMEM; 1931 1932 info->desc = (struct pinctrl_desc *)device_get_match_data(dev); 1933 1934 reset = devm_reset_control_get_optional_shared(dev, "switch"); 1935 if (IS_ERR(reset)) 1936 return dev_err_probe(dev, PTR_ERR(reset), 1937 "Failed to get reset\n"); 1938 reset_control_reset(reset); 1939 1940 base = devm_ioremap_resource(dev, 1941 platform_get_resource(pdev, IORESOURCE_MEM, 0)); 1942 if (IS_ERR(base)) 1943 return PTR_ERR(base); 1944 1945 info->stride = 1 + (info->desc->npins - 1) / 32; 1946 1947 regmap_config.max_register = OCELOT_GPIO_SD_MAP * info->stride + 15 * 4; 1948 1949 info->map = devm_regmap_init_mmio(dev, base, ®map_config); 1950 if (IS_ERR(info->map)) { 1951 dev_err(dev, "Failed to create regmap\n"); 1952 return PTR_ERR(info->map); 1953 } 1954 dev_set_drvdata(dev, info->map); 1955 info->dev = dev; 1956 1957 /* Pinconf registers */ 1958 if (info->desc->confops) { 1959 pincfg = ocelot_pinctrl_create_pincfg(pdev); 1960 if (IS_ERR(pincfg)) 1961 dev_dbg(dev, "Failed to create pincfg regmap\n"); 1962 else 1963 info->pincfg = pincfg; 1964 } 1965 1966 ret = ocelot_pinctrl_register(pdev, info); 1967 if (ret) 1968 return ret; 1969 1970 ret = ocelot_gpiochip_register(pdev, info); 1971 if (ret) 1972 return ret; 1973 1974 dev_info(dev, "driver registered\n"); 1975 1976 return 0; 1977 } 1978 1979 static struct platform_driver ocelot_pinctrl_driver = { 1980 .driver = { 1981 .name = "pinctrl-ocelot", 1982 .of_match_table = of_match_ptr(ocelot_pinctrl_of_match), 1983 .suppress_bind_attrs = true, 1984 }, 1985 .probe = ocelot_pinctrl_probe, 1986 }; 1987 builtin_platform_driver(ocelot_pinctrl_driver); 1988