1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* 3 * Microsemi SoCs pinctrl driver 4 * 5 * Author: <alexandre.belloni@free-electrons.com> 6 * License: Dual MIT/GPL 7 * Copyright (c) 2017 Microsemi Corporation 8 */ 9 10 #include <linux/gpio/driver.h> 11 #include <linux/interrupt.h> 12 #include <linux/io.h> 13 #include <linux/of_device.h> 14 #include <linux/of_irq.h> 15 #include <linux/of_platform.h> 16 #include <linux/pinctrl/pinctrl.h> 17 #include <linux/pinctrl/pinmux.h> 18 #include <linux/pinctrl/pinconf.h> 19 #include <linux/pinctrl/pinconf-generic.h> 20 #include <linux/platform_device.h> 21 #include <linux/regmap.h> 22 #include <linux/reset.h> 23 #include <linux/slab.h> 24 25 #include "core.h" 26 #include "pinconf.h" 27 #include "pinmux.h" 28 29 #define ocelot_clrsetbits(addr, clear, set) \ 30 writel((readl(addr) & ~(clear)) | (set), (addr)) 31 32 enum { 33 PINCONF_BIAS, 34 PINCONF_SCHMITT, 35 PINCONF_DRIVE_STRENGTH, 36 }; 37 38 /* GPIO standard registers */ 39 #define OCELOT_GPIO_OUT_SET 0x0 40 #define OCELOT_GPIO_OUT_CLR 0x4 41 #define OCELOT_GPIO_OUT 0x8 42 #define OCELOT_GPIO_IN 0xc 43 #define OCELOT_GPIO_OE 0x10 44 #define OCELOT_GPIO_INTR 0x14 45 #define OCELOT_GPIO_INTR_ENA 0x18 46 #define OCELOT_GPIO_INTR_IDENT 0x1c 47 #define OCELOT_GPIO_ALT0 0x20 48 #define OCELOT_GPIO_ALT1 0x24 49 #define OCELOT_GPIO_SD_MAP 0x28 50 51 #define OCELOT_FUNC_PER_PIN 4 52 53 enum { 54 FUNC_CAN0_a, 55 FUNC_CAN0_b, 56 FUNC_CAN1, 57 FUNC_CLKMON, 58 FUNC_NONE, 59 FUNC_FC0_a, 60 FUNC_FC0_b, 61 FUNC_FC0_c, 62 FUNC_FC1_a, 63 FUNC_FC1_b, 64 FUNC_FC1_c, 65 FUNC_FC2_a, 66 FUNC_FC2_b, 67 FUNC_FC3_a, 68 FUNC_FC3_b, 69 FUNC_FC3_c, 70 FUNC_FC4_a, 71 FUNC_FC4_b, 72 FUNC_FC4_c, 73 FUNC_FC_SHRD0, 74 FUNC_FC_SHRD1, 75 FUNC_FC_SHRD2, 76 FUNC_FC_SHRD3, 77 FUNC_FC_SHRD4, 78 FUNC_FC_SHRD5, 79 FUNC_FC_SHRD6, 80 FUNC_FC_SHRD7, 81 FUNC_FC_SHRD8, 82 FUNC_FC_SHRD9, 83 FUNC_FC_SHRD10, 84 FUNC_FC_SHRD11, 85 FUNC_FC_SHRD12, 86 FUNC_FC_SHRD13, 87 FUNC_FC_SHRD14, 88 FUNC_FC_SHRD15, 89 FUNC_FC_SHRD16, 90 FUNC_FC_SHRD17, 91 FUNC_FC_SHRD18, 92 FUNC_FC_SHRD19, 93 FUNC_FC_SHRD20, 94 FUNC_GPIO, 95 FUNC_IB_TRG_a, 96 FUNC_IB_TRG_b, 97 FUNC_IB_TRG_c, 98 FUNC_IRQ0, 99 FUNC_IRQ_IN_a, 100 FUNC_IRQ_IN_b, 101 FUNC_IRQ_IN_c, 102 FUNC_IRQ0_IN, 103 FUNC_IRQ_OUT_a, 104 FUNC_IRQ_OUT_b, 105 FUNC_IRQ_OUT_c, 106 FUNC_IRQ0_OUT, 107 FUNC_IRQ1, 108 FUNC_IRQ1_IN, 109 FUNC_IRQ1_OUT, 110 FUNC_EXT_IRQ, 111 FUNC_MIIM, 112 FUNC_MIIM_a, 113 FUNC_MIIM_b, 114 FUNC_MIIM_c, 115 FUNC_MIIM_Sa, 116 FUNC_MIIM_Sb, 117 FUNC_OB_TRG, 118 FUNC_OB_TRG_a, 119 FUNC_OB_TRG_b, 120 FUNC_PHY_LED, 121 FUNC_PCI_WAKE, 122 FUNC_MD, 123 FUNC_PTP0, 124 FUNC_PTP1, 125 FUNC_PTP2, 126 FUNC_PTP3, 127 FUNC_PTPSYNC_0, 128 FUNC_PTPSYNC_1, 129 FUNC_PTPSYNC_2, 130 FUNC_PTPSYNC_3, 131 FUNC_PTPSYNC_4, 132 FUNC_PTPSYNC_5, 133 FUNC_PTPSYNC_6, 134 FUNC_PTPSYNC_7, 135 FUNC_PWM, 136 FUNC_PWM_a, 137 FUNC_PWM_b, 138 FUNC_QSPI1, 139 FUNC_QSPI2, 140 FUNC_R, 141 FUNC_RECO_a, 142 FUNC_RECO_b, 143 FUNC_RECO_CLK, 144 FUNC_SD, 145 FUNC_SFP, 146 FUNC_SFP_SD, 147 FUNC_SG0, 148 FUNC_SG1, 149 FUNC_SG2, 150 FUNC_SGPIO_a, 151 FUNC_SGPIO_b, 152 FUNC_SI, 153 FUNC_SI2, 154 FUNC_TACHO, 155 FUNC_TACHO_a, 156 FUNC_TACHO_b, 157 FUNC_TWI, 158 FUNC_TWI2, 159 FUNC_TWI3, 160 FUNC_TWI_SCL_M, 161 FUNC_TWI_SLC_GATE, 162 FUNC_TWI_SLC_GATE_AD, 163 FUNC_UART, 164 FUNC_UART2, 165 FUNC_UART3, 166 FUNC_USB_H_a, 167 FUNC_USB_H_b, 168 FUNC_USB_H_c, 169 FUNC_USB_S_a, 170 FUNC_USB_S_b, 171 FUNC_USB_S_c, 172 FUNC_PLL_STAT, 173 FUNC_EMMC, 174 FUNC_EMMC_SD, 175 FUNC_REF_CLK, 176 FUNC_RCVRD_CLK, 177 FUNC_MAX 178 }; 179 180 static const char *const ocelot_function_names[] = { 181 [FUNC_CAN0_a] = "can0_a", 182 [FUNC_CAN0_b] = "can0_b", 183 [FUNC_CAN1] = "can1", 184 [FUNC_CLKMON] = "clkmon", 185 [FUNC_NONE] = "none", 186 [FUNC_FC0_a] = "fc0_a", 187 [FUNC_FC0_b] = "fc0_b", 188 [FUNC_FC0_c] = "fc0_c", 189 [FUNC_FC1_a] = "fc1_a", 190 [FUNC_FC1_b] = "fc1_b", 191 [FUNC_FC1_c] = "fc1_c", 192 [FUNC_FC2_a] = "fc2_a", 193 [FUNC_FC2_b] = "fc2_b", 194 [FUNC_FC3_a] = "fc3_a", 195 [FUNC_FC3_b] = "fc3_b", 196 [FUNC_FC3_c] = "fc3_c", 197 [FUNC_FC4_a] = "fc4_a", 198 [FUNC_FC4_b] = "fc4_b", 199 [FUNC_FC4_c] = "fc4_c", 200 [FUNC_FC_SHRD0] = "fc_shrd0", 201 [FUNC_FC_SHRD1] = "fc_shrd1", 202 [FUNC_FC_SHRD2] = "fc_shrd2", 203 [FUNC_FC_SHRD3] = "fc_shrd3", 204 [FUNC_FC_SHRD4] = "fc_shrd4", 205 [FUNC_FC_SHRD5] = "fc_shrd5", 206 [FUNC_FC_SHRD6] = "fc_shrd6", 207 [FUNC_FC_SHRD7] = "fc_shrd7", 208 [FUNC_FC_SHRD8] = "fc_shrd8", 209 [FUNC_FC_SHRD9] = "fc_shrd9", 210 [FUNC_FC_SHRD10] = "fc_shrd10", 211 [FUNC_FC_SHRD11] = "fc_shrd11", 212 [FUNC_FC_SHRD12] = "fc_shrd12", 213 [FUNC_FC_SHRD13] = "fc_shrd13", 214 [FUNC_FC_SHRD14] = "fc_shrd14", 215 [FUNC_FC_SHRD15] = "fc_shrd15", 216 [FUNC_FC_SHRD16] = "fc_shrd16", 217 [FUNC_FC_SHRD17] = "fc_shrd17", 218 [FUNC_FC_SHRD18] = "fc_shrd18", 219 [FUNC_FC_SHRD19] = "fc_shrd19", 220 [FUNC_FC_SHRD20] = "fc_shrd20", 221 [FUNC_GPIO] = "gpio", 222 [FUNC_IB_TRG_a] = "ib_trig_a", 223 [FUNC_IB_TRG_b] = "ib_trig_b", 224 [FUNC_IB_TRG_c] = "ib_trig_c", 225 [FUNC_IRQ0] = "irq0", 226 [FUNC_IRQ_IN_a] = "irq_in_a", 227 [FUNC_IRQ_IN_b] = "irq_in_b", 228 [FUNC_IRQ_IN_c] = "irq_in_c", 229 [FUNC_IRQ0_IN] = "irq0_in", 230 [FUNC_IRQ_OUT_a] = "irq_out_a", 231 [FUNC_IRQ_OUT_b] = "irq_out_b", 232 [FUNC_IRQ_OUT_c] = "irq_out_c", 233 [FUNC_IRQ0_OUT] = "irq0_out", 234 [FUNC_IRQ1] = "irq1", 235 [FUNC_IRQ1_IN] = "irq1_in", 236 [FUNC_IRQ1_OUT] = "irq1_out", 237 [FUNC_EXT_IRQ] = "ext_irq", 238 [FUNC_MIIM] = "miim", 239 [FUNC_MIIM_a] = "miim_a", 240 [FUNC_MIIM_b] = "miim_b", 241 [FUNC_MIIM_c] = "miim_c", 242 [FUNC_MIIM_Sa] = "miim_slave_a", 243 [FUNC_MIIM_Sb] = "miim_slave_b", 244 [FUNC_PHY_LED] = "phy_led", 245 [FUNC_PCI_WAKE] = "pci_wake", 246 [FUNC_MD] = "md", 247 [FUNC_OB_TRG] = "ob_trig", 248 [FUNC_OB_TRG_a] = "ob_trig_a", 249 [FUNC_OB_TRG_b] = "ob_trig_b", 250 [FUNC_PTP0] = "ptp0", 251 [FUNC_PTP1] = "ptp1", 252 [FUNC_PTP2] = "ptp2", 253 [FUNC_PTP3] = "ptp3", 254 [FUNC_PTPSYNC_0] = "ptpsync_0", 255 [FUNC_PTPSYNC_1] = "ptpsync_1", 256 [FUNC_PTPSYNC_2] = "ptpsync_2", 257 [FUNC_PTPSYNC_3] = "ptpsync_3", 258 [FUNC_PTPSYNC_4] = "ptpsync_4", 259 [FUNC_PTPSYNC_5] = "ptpsync_5", 260 [FUNC_PTPSYNC_6] = "ptpsync_6", 261 [FUNC_PTPSYNC_7] = "ptpsync_7", 262 [FUNC_PWM] = "pwm", 263 [FUNC_PWM_a] = "pwm_a", 264 [FUNC_PWM_b] = "pwm_b", 265 [FUNC_QSPI1] = "qspi1", 266 [FUNC_QSPI2] = "qspi2", 267 [FUNC_R] = "reserved", 268 [FUNC_RECO_a] = "reco_a", 269 [FUNC_RECO_b] = "reco_b", 270 [FUNC_RECO_CLK] = "reco_clk", 271 [FUNC_SD] = "sd", 272 [FUNC_SFP] = "sfp", 273 [FUNC_SFP_SD] = "sfp_sd", 274 [FUNC_SG0] = "sg0", 275 [FUNC_SG1] = "sg1", 276 [FUNC_SG2] = "sg2", 277 [FUNC_SGPIO_a] = "sgpio_a", 278 [FUNC_SGPIO_b] = "sgpio_b", 279 [FUNC_SI] = "si", 280 [FUNC_SI2] = "si2", 281 [FUNC_TACHO] = "tacho", 282 [FUNC_TACHO_a] = "tacho_a", 283 [FUNC_TACHO_b] = "tacho_b", 284 [FUNC_TWI] = "twi", 285 [FUNC_TWI2] = "twi2", 286 [FUNC_TWI3] = "twi3", 287 [FUNC_TWI_SCL_M] = "twi_scl_m", 288 [FUNC_TWI_SLC_GATE] = "twi_slc_gate", 289 [FUNC_TWI_SLC_GATE_AD] = "twi_slc_gate_ad", 290 [FUNC_USB_H_a] = "usb_host_a", 291 [FUNC_USB_H_b] = "usb_host_b", 292 [FUNC_USB_H_c] = "usb_host_c", 293 [FUNC_USB_S_a] = "usb_slave_a", 294 [FUNC_USB_S_b] = "usb_slave_b", 295 [FUNC_USB_S_c] = "usb_slave_c", 296 [FUNC_UART] = "uart", 297 [FUNC_UART2] = "uart2", 298 [FUNC_UART3] = "uart3", 299 [FUNC_PLL_STAT] = "pll_stat", 300 [FUNC_EMMC] = "emmc", 301 [FUNC_EMMC_SD] = "emmc_sd", 302 [FUNC_REF_CLK] = "ref_clk", 303 [FUNC_RCVRD_CLK] = "rcvrd_clk", 304 }; 305 306 struct ocelot_pmx_func { 307 const char **groups; 308 unsigned int ngroups; 309 }; 310 311 struct ocelot_pin_caps { 312 unsigned int pin; 313 unsigned char functions[OCELOT_FUNC_PER_PIN]; 314 unsigned char a_functions[OCELOT_FUNC_PER_PIN]; /* Additional functions */ 315 }; 316 317 struct ocelot_pincfg_data { 318 u8 pd_bit; 319 u8 pu_bit; 320 u8 drive_bits; 321 u8 schmitt_bit; 322 }; 323 324 struct ocelot_pinctrl { 325 struct device *dev; 326 struct pinctrl_dev *pctl; 327 struct gpio_chip gpio_chip; 328 struct regmap *map; 329 struct regmap *pincfg; 330 struct pinctrl_desc *desc; 331 const struct ocelot_pincfg_data *pincfg_data; 332 struct ocelot_pmx_func func[FUNC_MAX]; 333 u8 stride; 334 }; 335 336 struct ocelot_match_data { 337 struct pinctrl_desc desc; 338 struct ocelot_pincfg_data pincfg_data; 339 }; 340 341 #define LUTON_P(p, f0, f1) \ 342 static struct ocelot_pin_caps luton_pin_##p = { \ 343 .pin = p, \ 344 .functions = { \ 345 FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_NONE, \ 346 }, \ 347 } 348 349 LUTON_P(0, SG0, NONE); 350 LUTON_P(1, SG0, NONE); 351 LUTON_P(2, SG0, NONE); 352 LUTON_P(3, SG0, NONE); 353 LUTON_P(4, TACHO, NONE); 354 LUTON_P(5, TWI, PHY_LED); 355 LUTON_P(6, TWI, PHY_LED); 356 LUTON_P(7, NONE, PHY_LED); 357 LUTON_P(8, EXT_IRQ, PHY_LED); 358 LUTON_P(9, EXT_IRQ, PHY_LED); 359 LUTON_P(10, SFP, PHY_LED); 360 LUTON_P(11, SFP, PHY_LED); 361 LUTON_P(12, SFP, PHY_LED); 362 LUTON_P(13, SFP, PHY_LED); 363 LUTON_P(14, SI, PHY_LED); 364 LUTON_P(15, SI, PHY_LED); 365 LUTON_P(16, SI, PHY_LED); 366 LUTON_P(17, SFP, PHY_LED); 367 LUTON_P(18, SFP, PHY_LED); 368 LUTON_P(19, SFP, PHY_LED); 369 LUTON_P(20, SFP, PHY_LED); 370 LUTON_P(21, SFP, PHY_LED); 371 LUTON_P(22, SFP, PHY_LED); 372 LUTON_P(23, SFP, PHY_LED); 373 LUTON_P(24, SFP, PHY_LED); 374 LUTON_P(25, SFP, PHY_LED); 375 LUTON_P(26, SFP, PHY_LED); 376 LUTON_P(27, SFP, PHY_LED); 377 LUTON_P(28, SFP, PHY_LED); 378 LUTON_P(29, PWM, NONE); 379 LUTON_P(30, UART, NONE); 380 LUTON_P(31, UART, NONE); 381 382 #define LUTON_PIN(n) { \ 383 .number = n, \ 384 .name = "GPIO_"#n, \ 385 .drv_data = &luton_pin_##n \ 386 } 387 388 static const struct pinctrl_pin_desc luton_pins[] = { 389 LUTON_PIN(0), 390 LUTON_PIN(1), 391 LUTON_PIN(2), 392 LUTON_PIN(3), 393 LUTON_PIN(4), 394 LUTON_PIN(5), 395 LUTON_PIN(6), 396 LUTON_PIN(7), 397 LUTON_PIN(8), 398 LUTON_PIN(9), 399 LUTON_PIN(10), 400 LUTON_PIN(11), 401 LUTON_PIN(12), 402 LUTON_PIN(13), 403 LUTON_PIN(14), 404 LUTON_PIN(15), 405 LUTON_PIN(16), 406 LUTON_PIN(17), 407 LUTON_PIN(18), 408 LUTON_PIN(19), 409 LUTON_PIN(20), 410 LUTON_PIN(21), 411 LUTON_PIN(22), 412 LUTON_PIN(23), 413 LUTON_PIN(24), 414 LUTON_PIN(25), 415 LUTON_PIN(26), 416 LUTON_PIN(27), 417 LUTON_PIN(28), 418 LUTON_PIN(29), 419 LUTON_PIN(30), 420 LUTON_PIN(31), 421 }; 422 423 #define SERVAL_P(p, f0, f1, f2) \ 424 static struct ocelot_pin_caps serval_pin_##p = { \ 425 .pin = p, \ 426 .functions = { \ 427 FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2, \ 428 }, \ 429 } 430 431 SERVAL_P(0, SG0, NONE, NONE); 432 SERVAL_P(1, SG0, NONE, NONE); 433 SERVAL_P(2, SG0, NONE, NONE); 434 SERVAL_P(3, SG0, NONE, NONE); 435 SERVAL_P(4, TACHO, NONE, NONE); 436 SERVAL_P(5, PWM, NONE, NONE); 437 SERVAL_P(6, TWI, NONE, NONE); 438 SERVAL_P(7, TWI, NONE, NONE); 439 SERVAL_P(8, SI, NONE, NONE); 440 SERVAL_P(9, SI, MD, NONE); 441 SERVAL_P(10, SI, MD, NONE); 442 SERVAL_P(11, SFP, MD, TWI_SCL_M); 443 SERVAL_P(12, SFP, MD, TWI_SCL_M); 444 SERVAL_P(13, SFP, UART2, TWI_SCL_M); 445 SERVAL_P(14, SFP, UART2, TWI_SCL_M); 446 SERVAL_P(15, SFP, PTP0, TWI_SCL_M); 447 SERVAL_P(16, SFP, PTP0, TWI_SCL_M); 448 SERVAL_P(17, SFP, PCI_WAKE, TWI_SCL_M); 449 SERVAL_P(18, SFP, NONE, TWI_SCL_M); 450 SERVAL_P(19, SFP, NONE, TWI_SCL_M); 451 SERVAL_P(20, SFP, NONE, TWI_SCL_M); 452 SERVAL_P(21, SFP, NONE, TWI_SCL_M); 453 SERVAL_P(22, NONE, NONE, NONE); 454 SERVAL_P(23, NONE, NONE, NONE); 455 SERVAL_P(24, NONE, NONE, NONE); 456 SERVAL_P(25, NONE, NONE, NONE); 457 SERVAL_P(26, UART, NONE, NONE); 458 SERVAL_P(27, UART, NONE, NONE); 459 SERVAL_P(28, IRQ0, NONE, NONE); 460 SERVAL_P(29, IRQ1, NONE, NONE); 461 SERVAL_P(30, PTP0, NONE, NONE); 462 SERVAL_P(31, PTP0, NONE, NONE); 463 464 #define SERVAL_PIN(n) { \ 465 .number = n, \ 466 .name = "GPIO_"#n, \ 467 .drv_data = &serval_pin_##n \ 468 } 469 470 static const struct pinctrl_pin_desc serval_pins[] = { 471 SERVAL_PIN(0), 472 SERVAL_PIN(1), 473 SERVAL_PIN(2), 474 SERVAL_PIN(3), 475 SERVAL_PIN(4), 476 SERVAL_PIN(5), 477 SERVAL_PIN(6), 478 SERVAL_PIN(7), 479 SERVAL_PIN(8), 480 SERVAL_PIN(9), 481 SERVAL_PIN(10), 482 SERVAL_PIN(11), 483 SERVAL_PIN(12), 484 SERVAL_PIN(13), 485 SERVAL_PIN(14), 486 SERVAL_PIN(15), 487 SERVAL_PIN(16), 488 SERVAL_PIN(17), 489 SERVAL_PIN(18), 490 SERVAL_PIN(19), 491 SERVAL_PIN(20), 492 SERVAL_PIN(21), 493 SERVAL_PIN(22), 494 SERVAL_PIN(23), 495 SERVAL_PIN(24), 496 SERVAL_PIN(25), 497 SERVAL_PIN(26), 498 SERVAL_PIN(27), 499 SERVAL_PIN(28), 500 SERVAL_PIN(29), 501 SERVAL_PIN(30), 502 SERVAL_PIN(31), 503 }; 504 505 #define OCELOT_P(p, f0, f1, f2) \ 506 static struct ocelot_pin_caps ocelot_pin_##p = { \ 507 .pin = p, \ 508 .functions = { \ 509 FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2, \ 510 }, \ 511 } 512 513 OCELOT_P(0, SG0, NONE, NONE); 514 OCELOT_P(1, SG0, NONE, NONE); 515 OCELOT_P(2, SG0, NONE, NONE); 516 OCELOT_P(3, SG0, NONE, NONE); 517 OCELOT_P(4, IRQ0_IN, IRQ0_OUT, TWI_SCL_M); 518 OCELOT_P(5, IRQ1_IN, IRQ1_OUT, PCI_WAKE); 519 OCELOT_P(6, UART, TWI_SCL_M, NONE); 520 OCELOT_P(7, UART, TWI_SCL_M, NONE); 521 OCELOT_P(8, SI, TWI_SCL_M, IRQ0_OUT); 522 OCELOT_P(9, SI, TWI_SCL_M, IRQ1_OUT); 523 OCELOT_P(10, PTP2, TWI_SCL_M, SFP); 524 OCELOT_P(11, PTP3, TWI_SCL_M, SFP); 525 OCELOT_P(12, UART2, TWI_SCL_M, SFP); 526 OCELOT_P(13, UART2, TWI_SCL_M, SFP); 527 OCELOT_P(14, MIIM, TWI_SCL_M, SFP); 528 OCELOT_P(15, MIIM, TWI_SCL_M, SFP); 529 OCELOT_P(16, TWI, NONE, SI); 530 OCELOT_P(17, TWI, TWI_SCL_M, SI); 531 OCELOT_P(18, PTP0, TWI_SCL_M, NONE); 532 OCELOT_P(19, PTP1, TWI_SCL_M, NONE); 533 OCELOT_P(20, RECO_CLK, TACHO, TWI_SCL_M); 534 OCELOT_P(21, RECO_CLK, PWM, TWI_SCL_M); 535 536 #define OCELOT_PIN(n) { \ 537 .number = n, \ 538 .name = "GPIO_"#n, \ 539 .drv_data = &ocelot_pin_##n \ 540 } 541 542 static const struct pinctrl_pin_desc ocelot_pins[] = { 543 OCELOT_PIN(0), 544 OCELOT_PIN(1), 545 OCELOT_PIN(2), 546 OCELOT_PIN(3), 547 OCELOT_PIN(4), 548 OCELOT_PIN(5), 549 OCELOT_PIN(6), 550 OCELOT_PIN(7), 551 OCELOT_PIN(8), 552 OCELOT_PIN(9), 553 OCELOT_PIN(10), 554 OCELOT_PIN(11), 555 OCELOT_PIN(12), 556 OCELOT_PIN(13), 557 OCELOT_PIN(14), 558 OCELOT_PIN(15), 559 OCELOT_PIN(16), 560 OCELOT_PIN(17), 561 OCELOT_PIN(18), 562 OCELOT_PIN(19), 563 OCELOT_PIN(20), 564 OCELOT_PIN(21), 565 }; 566 567 #define JAGUAR2_P(p, f0, f1) \ 568 static struct ocelot_pin_caps jaguar2_pin_##p = { \ 569 .pin = p, \ 570 .functions = { \ 571 FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_NONE \ 572 }, \ 573 } 574 575 JAGUAR2_P(0, SG0, NONE); 576 JAGUAR2_P(1, SG0, NONE); 577 JAGUAR2_P(2, SG0, NONE); 578 JAGUAR2_P(3, SG0, NONE); 579 JAGUAR2_P(4, SG1, NONE); 580 JAGUAR2_P(5, SG1, NONE); 581 JAGUAR2_P(6, IRQ0_IN, IRQ0_OUT); 582 JAGUAR2_P(7, IRQ1_IN, IRQ1_OUT); 583 JAGUAR2_P(8, PTP0, NONE); 584 JAGUAR2_P(9, PTP1, NONE); 585 JAGUAR2_P(10, UART, NONE); 586 JAGUAR2_P(11, UART, NONE); 587 JAGUAR2_P(12, SG1, NONE); 588 JAGUAR2_P(13, SG1, NONE); 589 JAGUAR2_P(14, TWI, TWI_SCL_M); 590 JAGUAR2_P(15, TWI, NONE); 591 JAGUAR2_P(16, SI, TWI_SCL_M); 592 JAGUAR2_P(17, SI, TWI_SCL_M); 593 JAGUAR2_P(18, SI, TWI_SCL_M); 594 JAGUAR2_P(19, PCI_WAKE, NONE); 595 JAGUAR2_P(20, IRQ0_OUT, TWI_SCL_M); 596 JAGUAR2_P(21, IRQ1_OUT, TWI_SCL_M); 597 JAGUAR2_P(22, TACHO, NONE); 598 JAGUAR2_P(23, PWM, NONE); 599 JAGUAR2_P(24, UART2, NONE); 600 JAGUAR2_P(25, UART2, SI); 601 JAGUAR2_P(26, PTP2, SI); 602 JAGUAR2_P(27, PTP3, SI); 603 JAGUAR2_P(28, TWI2, SI); 604 JAGUAR2_P(29, TWI2, SI); 605 JAGUAR2_P(30, SG2, SI); 606 JAGUAR2_P(31, SG2, SI); 607 JAGUAR2_P(32, SG2, SI); 608 JAGUAR2_P(33, SG2, SI); 609 JAGUAR2_P(34, NONE, TWI_SCL_M); 610 JAGUAR2_P(35, NONE, TWI_SCL_M); 611 JAGUAR2_P(36, NONE, TWI_SCL_M); 612 JAGUAR2_P(37, NONE, TWI_SCL_M); 613 JAGUAR2_P(38, NONE, TWI_SCL_M); 614 JAGUAR2_P(39, NONE, TWI_SCL_M); 615 JAGUAR2_P(40, NONE, TWI_SCL_M); 616 JAGUAR2_P(41, NONE, TWI_SCL_M); 617 JAGUAR2_P(42, NONE, TWI_SCL_M); 618 JAGUAR2_P(43, NONE, TWI_SCL_M); 619 JAGUAR2_P(44, NONE, SFP); 620 JAGUAR2_P(45, NONE, SFP); 621 JAGUAR2_P(46, NONE, SFP); 622 JAGUAR2_P(47, NONE, SFP); 623 JAGUAR2_P(48, SFP, NONE); 624 JAGUAR2_P(49, SFP, SI); 625 JAGUAR2_P(50, SFP, SI); 626 JAGUAR2_P(51, SFP, SI); 627 JAGUAR2_P(52, SFP, NONE); 628 JAGUAR2_P(53, SFP, NONE); 629 JAGUAR2_P(54, SFP, NONE); 630 JAGUAR2_P(55, SFP, NONE); 631 JAGUAR2_P(56, MIIM, SFP); 632 JAGUAR2_P(57, MIIM, SFP); 633 JAGUAR2_P(58, MIIM, SFP); 634 JAGUAR2_P(59, MIIM, SFP); 635 JAGUAR2_P(60, NONE, NONE); 636 JAGUAR2_P(61, NONE, NONE); 637 JAGUAR2_P(62, NONE, NONE); 638 JAGUAR2_P(63, NONE, NONE); 639 640 #define JAGUAR2_PIN(n) { \ 641 .number = n, \ 642 .name = "GPIO_"#n, \ 643 .drv_data = &jaguar2_pin_##n \ 644 } 645 646 static const struct pinctrl_pin_desc jaguar2_pins[] = { 647 JAGUAR2_PIN(0), 648 JAGUAR2_PIN(1), 649 JAGUAR2_PIN(2), 650 JAGUAR2_PIN(3), 651 JAGUAR2_PIN(4), 652 JAGUAR2_PIN(5), 653 JAGUAR2_PIN(6), 654 JAGUAR2_PIN(7), 655 JAGUAR2_PIN(8), 656 JAGUAR2_PIN(9), 657 JAGUAR2_PIN(10), 658 JAGUAR2_PIN(11), 659 JAGUAR2_PIN(12), 660 JAGUAR2_PIN(13), 661 JAGUAR2_PIN(14), 662 JAGUAR2_PIN(15), 663 JAGUAR2_PIN(16), 664 JAGUAR2_PIN(17), 665 JAGUAR2_PIN(18), 666 JAGUAR2_PIN(19), 667 JAGUAR2_PIN(20), 668 JAGUAR2_PIN(21), 669 JAGUAR2_PIN(22), 670 JAGUAR2_PIN(23), 671 JAGUAR2_PIN(24), 672 JAGUAR2_PIN(25), 673 JAGUAR2_PIN(26), 674 JAGUAR2_PIN(27), 675 JAGUAR2_PIN(28), 676 JAGUAR2_PIN(29), 677 JAGUAR2_PIN(30), 678 JAGUAR2_PIN(31), 679 JAGUAR2_PIN(32), 680 JAGUAR2_PIN(33), 681 JAGUAR2_PIN(34), 682 JAGUAR2_PIN(35), 683 JAGUAR2_PIN(36), 684 JAGUAR2_PIN(37), 685 JAGUAR2_PIN(38), 686 JAGUAR2_PIN(39), 687 JAGUAR2_PIN(40), 688 JAGUAR2_PIN(41), 689 JAGUAR2_PIN(42), 690 JAGUAR2_PIN(43), 691 JAGUAR2_PIN(44), 692 JAGUAR2_PIN(45), 693 JAGUAR2_PIN(46), 694 JAGUAR2_PIN(47), 695 JAGUAR2_PIN(48), 696 JAGUAR2_PIN(49), 697 JAGUAR2_PIN(50), 698 JAGUAR2_PIN(51), 699 JAGUAR2_PIN(52), 700 JAGUAR2_PIN(53), 701 JAGUAR2_PIN(54), 702 JAGUAR2_PIN(55), 703 JAGUAR2_PIN(56), 704 JAGUAR2_PIN(57), 705 JAGUAR2_PIN(58), 706 JAGUAR2_PIN(59), 707 JAGUAR2_PIN(60), 708 JAGUAR2_PIN(61), 709 JAGUAR2_PIN(62), 710 JAGUAR2_PIN(63), 711 }; 712 713 #define SERVALT_P(p, f0, f1, f2) \ 714 static struct ocelot_pin_caps servalt_pin_##p = { \ 715 .pin = p, \ 716 .functions = { \ 717 FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2 \ 718 }, \ 719 } 720 721 SERVALT_P(0, SG0, NONE, NONE); 722 SERVALT_P(1, SG0, NONE, NONE); 723 SERVALT_P(2, SG0, NONE, NONE); 724 SERVALT_P(3, SG0, NONE, NONE); 725 SERVALT_P(4, IRQ0_IN, IRQ0_OUT, TWI_SCL_M); 726 SERVALT_P(5, IRQ1_IN, IRQ1_OUT, TWI_SCL_M); 727 SERVALT_P(6, UART, NONE, NONE); 728 SERVALT_P(7, UART, NONE, NONE); 729 SERVALT_P(8, SI, SFP, TWI_SCL_M); 730 SERVALT_P(9, PCI_WAKE, SFP, SI); 731 SERVALT_P(10, PTP0, SFP, TWI_SCL_M); 732 SERVALT_P(11, PTP1, SFP, TWI_SCL_M); 733 SERVALT_P(12, REF_CLK, SFP, TWI_SCL_M); 734 SERVALT_P(13, REF_CLK, SFP, TWI_SCL_M); 735 SERVALT_P(14, REF_CLK, IRQ0_OUT, SI); 736 SERVALT_P(15, REF_CLK, IRQ1_OUT, SI); 737 SERVALT_P(16, TACHO, SFP, SI); 738 SERVALT_P(17, PWM, NONE, TWI_SCL_M); 739 SERVALT_P(18, PTP2, SFP, SI); 740 SERVALT_P(19, PTP3, SFP, SI); 741 SERVALT_P(20, UART2, SFP, SI); 742 SERVALT_P(21, UART2, NONE, NONE); 743 SERVALT_P(22, MIIM, SFP, TWI2); 744 SERVALT_P(23, MIIM, SFP, TWI2); 745 SERVALT_P(24, TWI, NONE, NONE); 746 SERVALT_P(25, TWI, SFP, TWI_SCL_M); 747 SERVALT_P(26, TWI_SCL_M, SFP, SI); 748 SERVALT_P(27, TWI_SCL_M, SFP, SI); 749 SERVALT_P(28, TWI_SCL_M, SFP, SI); 750 SERVALT_P(29, TWI_SCL_M, NONE, NONE); 751 SERVALT_P(30, TWI_SCL_M, NONE, NONE); 752 SERVALT_P(31, TWI_SCL_M, NONE, NONE); 753 SERVALT_P(32, TWI_SCL_M, NONE, NONE); 754 SERVALT_P(33, RCVRD_CLK, NONE, NONE); 755 SERVALT_P(34, RCVRD_CLK, NONE, NONE); 756 SERVALT_P(35, RCVRD_CLK, NONE, NONE); 757 SERVALT_P(36, RCVRD_CLK, NONE, NONE); 758 759 #define SERVALT_PIN(n) { \ 760 .number = n, \ 761 .name = "GPIO_"#n, \ 762 .drv_data = &servalt_pin_##n \ 763 } 764 765 static const struct pinctrl_pin_desc servalt_pins[] = { 766 SERVALT_PIN(0), 767 SERVALT_PIN(1), 768 SERVALT_PIN(2), 769 SERVALT_PIN(3), 770 SERVALT_PIN(4), 771 SERVALT_PIN(5), 772 SERVALT_PIN(6), 773 SERVALT_PIN(7), 774 SERVALT_PIN(8), 775 SERVALT_PIN(9), 776 SERVALT_PIN(10), 777 SERVALT_PIN(11), 778 SERVALT_PIN(12), 779 SERVALT_PIN(13), 780 SERVALT_PIN(14), 781 SERVALT_PIN(15), 782 SERVALT_PIN(16), 783 SERVALT_PIN(17), 784 SERVALT_PIN(18), 785 SERVALT_PIN(19), 786 SERVALT_PIN(20), 787 SERVALT_PIN(21), 788 SERVALT_PIN(22), 789 SERVALT_PIN(23), 790 SERVALT_PIN(24), 791 SERVALT_PIN(25), 792 SERVALT_PIN(26), 793 SERVALT_PIN(27), 794 SERVALT_PIN(28), 795 SERVALT_PIN(29), 796 SERVALT_PIN(30), 797 SERVALT_PIN(31), 798 SERVALT_PIN(32), 799 SERVALT_PIN(33), 800 SERVALT_PIN(34), 801 SERVALT_PIN(35), 802 SERVALT_PIN(36), 803 }; 804 805 #define SPARX5_P(p, f0, f1, f2) \ 806 static struct ocelot_pin_caps sparx5_pin_##p = { \ 807 .pin = p, \ 808 .functions = { \ 809 FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2 \ 810 }, \ 811 } 812 813 SPARX5_P(0, SG0, PLL_STAT, NONE); 814 SPARX5_P(1, SG0, NONE, NONE); 815 SPARX5_P(2, SG0, NONE, NONE); 816 SPARX5_P(3, SG0, NONE, NONE); 817 SPARX5_P(4, SG1, NONE, NONE); 818 SPARX5_P(5, SG1, NONE, NONE); 819 SPARX5_P(6, IRQ0_IN, IRQ0_OUT, SFP); 820 SPARX5_P(7, IRQ1_IN, IRQ1_OUT, SFP); 821 SPARX5_P(8, PTP0, NONE, SFP); 822 SPARX5_P(9, PTP1, SFP, TWI_SCL_M); 823 SPARX5_P(10, UART, NONE, NONE); 824 SPARX5_P(11, UART, NONE, NONE); 825 SPARX5_P(12, SG1, NONE, NONE); 826 SPARX5_P(13, SG1, NONE, NONE); 827 SPARX5_P(14, TWI, TWI_SCL_M, NONE); 828 SPARX5_P(15, TWI, NONE, NONE); 829 SPARX5_P(16, SI, TWI_SCL_M, SFP); 830 SPARX5_P(17, SI, TWI_SCL_M, SFP); 831 SPARX5_P(18, SI, TWI_SCL_M, SFP); 832 SPARX5_P(19, PCI_WAKE, TWI_SCL_M, SFP); 833 SPARX5_P(20, IRQ0_OUT, TWI_SCL_M, SFP); 834 SPARX5_P(21, IRQ1_OUT, TACHO, SFP); 835 SPARX5_P(22, TACHO, IRQ0_OUT, TWI_SCL_M); 836 SPARX5_P(23, PWM, UART3, TWI_SCL_M); 837 SPARX5_P(24, PTP2, UART3, TWI_SCL_M); 838 SPARX5_P(25, PTP3, SI, TWI_SCL_M); 839 SPARX5_P(26, UART2, SI, TWI_SCL_M); 840 SPARX5_P(27, UART2, SI, TWI_SCL_M); 841 SPARX5_P(28, TWI2, SI, SFP); 842 SPARX5_P(29, TWI2, SI, SFP); 843 SPARX5_P(30, SG2, SI, PWM); 844 SPARX5_P(31, SG2, SI, TWI_SCL_M); 845 SPARX5_P(32, SG2, SI, TWI_SCL_M); 846 SPARX5_P(33, SG2, SI, SFP); 847 SPARX5_P(34, NONE, TWI_SCL_M, EMMC); 848 SPARX5_P(35, SFP, TWI_SCL_M, EMMC); 849 SPARX5_P(36, SFP, TWI_SCL_M, EMMC); 850 SPARX5_P(37, SFP, NONE, EMMC); 851 SPARX5_P(38, NONE, TWI_SCL_M, EMMC); 852 SPARX5_P(39, SI2, TWI_SCL_M, EMMC); 853 SPARX5_P(40, SI2, TWI_SCL_M, EMMC); 854 SPARX5_P(41, SI2, TWI_SCL_M, EMMC); 855 SPARX5_P(42, SI2, TWI_SCL_M, EMMC); 856 SPARX5_P(43, SI2, TWI_SCL_M, EMMC); 857 SPARX5_P(44, SI, SFP, EMMC); 858 SPARX5_P(45, SI, SFP, EMMC); 859 SPARX5_P(46, NONE, SFP, EMMC); 860 SPARX5_P(47, NONE, SFP, EMMC); 861 SPARX5_P(48, TWI3, SI, SFP); 862 SPARX5_P(49, TWI3, NONE, SFP); 863 SPARX5_P(50, SFP, NONE, TWI_SCL_M); 864 SPARX5_P(51, SFP, SI, TWI_SCL_M); 865 SPARX5_P(52, SFP, MIIM, TWI_SCL_M); 866 SPARX5_P(53, SFP, MIIM, TWI_SCL_M); 867 SPARX5_P(54, SFP, PTP2, TWI_SCL_M); 868 SPARX5_P(55, SFP, PTP3, PCI_WAKE); 869 SPARX5_P(56, MIIM, SFP, TWI_SCL_M); 870 SPARX5_P(57, MIIM, SFP, TWI_SCL_M); 871 SPARX5_P(58, MIIM, SFP, TWI_SCL_M); 872 SPARX5_P(59, MIIM, SFP, NONE); 873 SPARX5_P(60, RECO_CLK, NONE, NONE); 874 SPARX5_P(61, RECO_CLK, NONE, NONE); 875 SPARX5_P(62, RECO_CLK, PLL_STAT, NONE); 876 SPARX5_P(63, RECO_CLK, NONE, NONE); 877 878 #define SPARX5_PIN(n) { \ 879 .number = n, \ 880 .name = "GPIO_"#n, \ 881 .drv_data = &sparx5_pin_##n \ 882 } 883 884 static const struct pinctrl_pin_desc sparx5_pins[] = { 885 SPARX5_PIN(0), 886 SPARX5_PIN(1), 887 SPARX5_PIN(2), 888 SPARX5_PIN(3), 889 SPARX5_PIN(4), 890 SPARX5_PIN(5), 891 SPARX5_PIN(6), 892 SPARX5_PIN(7), 893 SPARX5_PIN(8), 894 SPARX5_PIN(9), 895 SPARX5_PIN(10), 896 SPARX5_PIN(11), 897 SPARX5_PIN(12), 898 SPARX5_PIN(13), 899 SPARX5_PIN(14), 900 SPARX5_PIN(15), 901 SPARX5_PIN(16), 902 SPARX5_PIN(17), 903 SPARX5_PIN(18), 904 SPARX5_PIN(19), 905 SPARX5_PIN(20), 906 SPARX5_PIN(21), 907 SPARX5_PIN(22), 908 SPARX5_PIN(23), 909 SPARX5_PIN(24), 910 SPARX5_PIN(25), 911 SPARX5_PIN(26), 912 SPARX5_PIN(27), 913 SPARX5_PIN(28), 914 SPARX5_PIN(29), 915 SPARX5_PIN(30), 916 SPARX5_PIN(31), 917 SPARX5_PIN(32), 918 SPARX5_PIN(33), 919 SPARX5_PIN(34), 920 SPARX5_PIN(35), 921 SPARX5_PIN(36), 922 SPARX5_PIN(37), 923 SPARX5_PIN(38), 924 SPARX5_PIN(39), 925 SPARX5_PIN(40), 926 SPARX5_PIN(41), 927 SPARX5_PIN(42), 928 SPARX5_PIN(43), 929 SPARX5_PIN(44), 930 SPARX5_PIN(45), 931 SPARX5_PIN(46), 932 SPARX5_PIN(47), 933 SPARX5_PIN(48), 934 SPARX5_PIN(49), 935 SPARX5_PIN(50), 936 SPARX5_PIN(51), 937 SPARX5_PIN(52), 938 SPARX5_PIN(53), 939 SPARX5_PIN(54), 940 SPARX5_PIN(55), 941 SPARX5_PIN(56), 942 SPARX5_PIN(57), 943 SPARX5_PIN(58), 944 SPARX5_PIN(59), 945 SPARX5_PIN(60), 946 SPARX5_PIN(61), 947 SPARX5_PIN(62), 948 SPARX5_PIN(63), 949 }; 950 951 #define LAN966X_P(p, f0, f1, f2, f3, f4, f5, f6, f7) \ 952 static struct ocelot_pin_caps lan966x_pin_##p = { \ 953 .pin = p, \ 954 .functions = { \ 955 FUNC_##f0, FUNC_##f1, FUNC_##f2, \ 956 FUNC_##f3 \ 957 }, \ 958 .a_functions = { \ 959 FUNC_##f4, FUNC_##f5, FUNC_##f6, \ 960 FUNC_##f7 \ 961 }, \ 962 } 963 964 /* Pinmuxing table taken from data sheet */ 965 /* Pin FUNC0 FUNC1 FUNC2 FUNC3 FUNC4 FUNC5 FUNC6 FUNC7 */ 966 LAN966X_P(0, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 967 LAN966X_P(1, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 968 LAN966X_P(2, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 969 LAN966X_P(3, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 970 LAN966X_P(4, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 971 LAN966X_P(5, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 972 LAN966X_P(6, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 973 LAN966X_P(7, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 974 LAN966X_P(8, GPIO, FC0_a, USB_H_b, NONE, USB_S_b, NONE, NONE, R); 975 LAN966X_P(9, GPIO, FC0_a, USB_H_b, NONE, NONE, NONE, NONE, R); 976 LAN966X_P(10, GPIO, FC0_a, NONE, NONE, NONE, NONE, NONE, R); 977 LAN966X_P(11, GPIO, FC1_a, NONE, NONE, NONE, NONE, NONE, R); 978 LAN966X_P(12, GPIO, FC1_a, NONE, NONE, NONE, NONE, NONE, R); 979 LAN966X_P(13, GPIO, FC1_a, NONE, NONE, NONE, NONE, NONE, R); 980 LAN966X_P(14, GPIO, FC2_a, NONE, NONE, NONE, NONE, NONE, R); 981 LAN966X_P(15, GPIO, FC2_a, NONE, NONE, NONE, NONE, NONE, R); 982 LAN966X_P(16, GPIO, FC2_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, IRQ_OUT_c, R); 983 LAN966X_P(17, GPIO, FC3_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, IRQ_OUT_c, R); 984 LAN966X_P(18, GPIO, FC3_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, IRQ_OUT_c, R); 985 LAN966X_P(19, GPIO, FC3_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, IRQ_OUT_c, R); 986 LAN966X_P(20, GPIO, FC4_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, NONE, R); 987 LAN966X_P(21, GPIO, FC4_a, NONE, NONE, OB_TRG_a, NONE, NONE, R); 988 LAN966X_P(22, GPIO, FC4_a, NONE, NONE, OB_TRG_a, NONE, NONE, R); 989 LAN966X_P(23, GPIO, NONE, NONE, NONE, OB_TRG_a, NONE, NONE, R); 990 LAN966X_P(24, GPIO, FC0_b, IB_TRG_a, USB_H_c, OB_TRG_a, IRQ_IN_c, TACHO_a, R); 991 LAN966X_P(25, GPIO, FC0_b, IB_TRG_a, USB_H_c, OB_TRG_a, IRQ_OUT_c, SFP_SD, R); 992 LAN966X_P(26, GPIO, FC0_b, IB_TRG_a, USB_S_c, OB_TRG_a, CAN0_a, SFP_SD, R); 993 LAN966X_P(27, GPIO, NONE, NONE, NONE, OB_TRG_a, CAN0_a, PWM_a, R); 994 LAN966X_P(28, GPIO, MIIM_a, NONE, NONE, OB_TRG_a, IRQ_OUT_c, SFP_SD, R); 995 LAN966X_P(29, GPIO, MIIM_a, NONE, NONE, OB_TRG_a, NONE, NONE, R); 996 LAN966X_P(30, GPIO, FC3_c, CAN1, CLKMON, OB_TRG, RECO_b, NONE, R); 997 LAN966X_P(31, GPIO, FC3_c, CAN1, CLKMON, OB_TRG, RECO_b, NONE, R); 998 LAN966X_P(32, GPIO, FC3_c, NONE, SGPIO_a, NONE, MIIM_Sa, NONE, R); 999 LAN966X_P(33, GPIO, FC1_b, NONE, SGPIO_a, NONE, MIIM_Sa, MIIM_b, R); 1000 LAN966X_P(34, GPIO, FC1_b, NONE, SGPIO_a, NONE, MIIM_Sa, MIIM_b, R); 1001 LAN966X_P(35, GPIO, FC1_b, PTPSYNC_0, SGPIO_a, CAN0_b, NONE, NONE, R); 1002 LAN966X_P(36, GPIO, NONE, PTPSYNC_1, NONE, CAN0_b, NONE, NONE, R); 1003 LAN966X_P(37, GPIO, FC_SHRD0, PTPSYNC_2, TWI_SLC_GATE_AD, NONE, NONE, NONE, R); 1004 LAN966X_P(38, GPIO, NONE, PTPSYNC_3, NONE, NONE, NONE, NONE, R); 1005 LAN966X_P(39, GPIO, NONE, PTPSYNC_4, NONE, NONE, NONE, NONE, R); 1006 LAN966X_P(40, GPIO, FC_SHRD1, PTPSYNC_5, NONE, NONE, NONE, NONE, R); 1007 LAN966X_P(41, GPIO, FC_SHRD2, PTPSYNC_6, TWI_SLC_GATE_AD, NONE, NONE, NONE, R); 1008 LAN966X_P(42, GPIO, FC_SHRD3, PTPSYNC_7, TWI_SLC_GATE_AD, NONE, NONE, NONE, R); 1009 LAN966X_P(43, GPIO, FC2_b, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, RECO_a, IRQ_IN_a, R); 1010 LAN966X_P(44, GPIO, FC2_b, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, RECO_a, IRQ_IN_a, R); 1011 LAN966X_P(45, GPIO, FC2_b, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, NONE, IRQ_IN_a, R); 1012 LAN966X_P(46, GPIO, FC1_c, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, FC_SHRD4, IRQ_IN_a, R); 1013 LAN966X_P(47, GPIO, FC1_c, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, FC_SHRD5, IRQ_IN_a, R); 1014 LAN966X_P(48, GPIO, FC1_c, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, FC_SHRD6, IRQ_IN_a, R); 1015 LAN966X_P(49, GPIO, FC_SHRD7, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, TWI_SLC_GATE, IRQ_IN_a, R); 1016 LAN966X_P(50, GPIO, FC_SHRD16, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, TWI_SLC_GATE, NONE, R); 1017 LAN966X_P(51, GPIO, FC3_b, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, PWM_b, IRQ_IN_b, R); 1018 LAN966X_P(52, GPIO, FC3_b, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, TACHO_b, IRQ_IN_b, R); 1019 LAN966X_P(53, GPIO, FC3_b, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, NONE, IRQ_IN_b, R); 1020 LAN966X_P(54, GPIO, FC_SHRD8, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, TWI_SLC_GATE, IRQ_IN_b, R); 1021 LAN966X_P(55, GPIO, FC_SHRD9, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, TWI_SLC_GATE, IRQ_IN_b, R); 1022 LAN966X_P(56, GPIO, FC4_b, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, FC_SHRD10, IRQ_IN_b, R); 1023 LAN966X_P(57, GPIO, FC4_b, TWI_SLC_GATE, IB_TRG_c, IRQ_OUT_b, FC_SHRD11, IRQ_IN_b, R); 1024 LAN966X_P(58, GPIO, FC4_b, TWI_SLC_GATE, IB_TRG_c, IRQ_OUT_b, FC_SHRD12, IRQ_IN_b, R); 1025 LAN966X_P(59, GPIO, QSPI1, MIIM_c, NONE, NONE, MIIM_Sb, NONE, R); 1026 LAN966X_P(60, GPIO, QSPI1, MIIM_c, NONE, NONE, MIIM_Sb, NONE, R); 1027 LAN966X_P(61, GPIO, QSPI1, NONE, SGPIO_b, FC0_c, MIIM_Sb, NONE, R); 1028 LAN966X_P(62, GPIO, QSPI1, FC_SHRD13, SGPIO_b, FC0_c, TWI_SLC_GATE, SFP_SD, R); 1029 LAN966X_P(63, GPIO, QSPI1, FC_SHRD14, SGPIO_b, FC0_c, TWI_SLC_GATE, SFP_SD, R); 1030 LAN966X_P(64, GPIO, QSPI1, FC4_c, SGPIO_b, FC_SHRD15, TWI_SLC_GATE, SFP_SD, R); 1031 LAN966X_P(65, GPIO, USB_H_a, FC4_c, NONE, IRQ_OUT_c, TWI_SLC_GATE_AD, NONE, R); 1032 LAN966X_P(66, GPIO, USB_H_a, FC4_c, USB_S_a, IRQ_OUT_c, IRQ_IN_c, NONE, R); 1033 LAN966X_P(67, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R); 1034 LAN966X_P(68, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R); 1035 LAN966X_P(69, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R); 1036 LAN966X_P(70, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R); 1037 LAN966X_P(71, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R); 1038 LAN966X_P(72, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R); 1039 LAN966X_P(73, GPIO, EMMC, NONE, NONE, SD, NONE, NONE, R); 1040 LAN966X_P(74, GPIO, EMMC, NONE, FC_SHRD17, SD, TWI_SLC_GATE, NONE, R); 1041 LAN966X_P(75, GPIO, EMMC, NONE, FC_SHRD18, SD, TWI_SLC_GATE, NONE, R); 1042 LAN966X_P(76, GPIO, EMMC, NONE, FC_SHRD19, SD, TWI_SLC_GATE, NONE, R); 1043 LAN966X_P(77, GPIO, EMMC_SD, NONE, FC_SHRD20, NONE, TWI_SLC_GATE, NONE, R); 1044 1045 #define LAN966X_PIN(n) { \ 1046 .number = n, \ 1047 .name = "GPIO_"#n, \ 1048 .drv_data = &lan966x_pin_##n \ 1049 } 1050 1051 static const struct pinctrl_pin_desc lan966x_pins[] = { 1052 LAN966X_PIN(0), 1053 LAN966X_PIN(1), 1054 LAN966X_PIN(2), 1055 LAN966X_PIN(3), 1056 LAN966X_PIN(4), 1057 LAN966X_PIN(5), 1058 LAN966X_PIN(6), 1059 LAN966X_PIN(7), 1060 LAN966X_PIN(8), 1061 LAN966X_PIN(9), 1062 LAN966X_PIN(10), 1063 LAN966X_PIN(11), 1064 LAN966X_PIN(12), 1065 LAN966X_PIN(13), 1066 LAN966X_PIN(14), 1067 LAN966X_PIN(15), 1068 LAN966X_PIN(16), 1069 LAN966X_PIN(17), 1070 LAN966X_PIN(18), 1071 LAN966X_PIN(19), 1072 LAN966X_PIN(20), 1073 LAN966X_PIN(21), 1074 LAN966X_PIN(22), 1075 LAN966X_PIN(23), 1076 LAN966X_PIN(24), 1077 LAN966X_PIN(25), 1078 LAN966X_PIN(26), 1079 LAN966X_PIN(27), 1080 LAN966X_PIN(28), 1081 LAN966X_PIN(29), 1082 LAN966X_PIN(30), 1083 LAN966X_PIN(31), 1084 LAN966X_PIN(32), 1085 LAN966X_PIN(33), 1086 LAN966X_PIN(34), 1087 LAN966X_PIN(35), 1088 LAN966X_PIN(36), 1089 LAN966X_PIN(37), 1090 LAN966X_PIN(38), 1091 LAN966X_PIN(39), 1092 LAN966X_PIN(40), 1093 LAN966X_PIN(41), 1094 LAN966X_PIN(42), 1095 LAN966X_PIN(43), 1096 LAN966X_PIN(44), 1097 LAN966X_PIN(45), 1098 LAN966X_PIN(46), 1099 LAN966X_PIN(47), 1100 LAN966X_PIN(48), 1101 LAN966X_PIN(49), 1102 LAN966X_PIN(50), 1103 LAN966X_PIN(51), 1104 LAN966X_PIN(52), 1105 LAN966X_PIN(53), 1106 LAN966X_PIN(54), 1107 LAN966X_PIN(55), 1108 LAN966X_PIN(56), 1109 LAN966X_PIN(57), 1110 LAN966X_PIN(58), 1111 LAN966X_PIN(59), 1112 LAN966X_PIN(60), 1113 LAN966X_PIN(61), 1114 LAN966X_PIN(62), 1115 LAN966X_PIN(63), 1116 LAN966X_PIN(64), 1117 LAN966X_PIN(65), 1118 LAN966X_PIN(66), 1119 LAN966X_PIN(67), 1120 LAN966X_PIN(68), 1121 LAN966X_PIN(69), 1122 LAN966X_PIN(70), 1123 LAN966X_PIN(71), 1124 LAN966X_PIN(72), 1125 LAN966X_PIN(73), 1126 LAN966X_PIN(74), 1127 LAN966X_PIN(75), 1128 LAN966X_PIN(76), 1129 LAN966X_PIN(77), 1130 }; 1131 1132 static int ocelot_get_functions_count(struct pinctrl_dev *pctldev) 1133 { 1134 return ARRAY_SIZE(ocelot_function_names); 1135 } 1136 1137 static const char *ocelot_get_function_name(struct pinctrl_dev *pctldev, 1138 unsigned int function) 1139 { 1140 return ocelot_function_names[function]; 1141 } 1142 1143 static int ocelot_get_function_groups(struct pinctrl_dev *pctldev, 1144 unsigned int function, 1145 const char *const **groups, 1146 unsigned *const num_groups) 1147 { 1148 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1149 1150 *groups = info->func[function].groups; 1151 *num_groups = info->func[function].ngroups; 1152 1153 return 0; 1154 } 1155 1156 static int ocelot_pin_function_idx(struct ocelot_pinctrl *info, 1157 unsigned int pin, unsigned int function) 1158 { 1159 struct ocelot_pin_caps *p = info->desc->pins[pin].drv_data; 1160 int i; 1161 1162 for (i = 0; i < OCELOT_FUNC_PER_PIN; i++) { 1163 if (function == p->functions[i]) 1164 return i; 1165 1166 if (function == p->a_functions[i]) 1167 return i + OCELOT_FUNC_PER_PIN; 1168 } 1169 1170 return -1; 1171 } 1172 1173 #define REG_ALT(msb, info, p) (OCELOT_GPIO_ALT0 * (info)->stride + 4 * ((msb) + ((info)->stride * ((p) / 32)))) 1174 1175 static int ocelot_pinmux_set_mux(struct pinctrl_dev *pctldev, 1176 unsigned int selector, unsigned int group) 1177 { 1178 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1179 struct ocelot_pin_caps *pin = info->desc->pins[group].drv_data; 1180 unsigned int p = pin->pin % 32; 1181 int f; 1182 1183 f = ocelot_pin_function_idx(info, group, selector); 1184 if (f < 0) 1185 return -EINVAL; 1186 1187 /* 1188 * f is encoded on two bits. 1189 * bit 0 of f goes in BIT(pin) of ALT[0], bit 1 of f goes in BIT(pin) of 1190 * ALT[1] 1191 * This is racy because both registers can't be updated at the same time 1192 * but it doesn't matter much for now. 1193 * Note: ALT0/ALT1 are organized specially for 64 gpio targets 1194 */ 1195 regmap_update_bits(info->map, REG_ALT(0, info, pin->pin), 1196 BIT(p), f << p); 1197 regmap_update_bits(info->map, REG_ALT(1, info, pin->pin), 1198 BIT(p), f << (p - 1)); 1199 1200 return 0; 1201 } 1202 1203 static int lan966x_pinmux_set_mux(struct pinctrl_dev *pctldev, 1204 unsigned int selector, unsigned int group) 1205 { 1206 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1207 struct ocelot_pin_caps *pin = info->desc->pins[group].drv_data; 1208 unsigned int p = pin->pin % 32; 1209 int f; 1210 1211 f = ocelot_pin_function_idx(info, group, selector); 1212 if (f < 0) 1213 return -EINVAL; 1214 1215 /* 1216 * f is encoded on three bits. 1217 * bit 0 of f goes in BIT(pin) of ALT[0], bit 1 of f goes in BIT(pin) of 1218 * ALT[1], bit 2 of f goes in BIT(pin) of ALT[2] 1219 * This is racy because three registers can't be updated at the same time 1220 * but it doesn't matter much for now. 1221 * Note: ALT0/ALT1/ALT2 are organized specially for 78 gpio targets 1222 */ 1223 regmap_update_bits(info->map, REG_ALT(0, info, pin->pin), 1224 BIT(p), f << p); 1225 regmap_update_bits(info->map, REG_ALT(1, info, pin->pin), 1226 BIT(p), (f >> 1) << p); 1227 regmap_update_bits(info->map, REG_ALT(2, info, pin->pin), 1228 BIT(p), (f >> 2) << p); 1229 1230 return 0; 1231 } 1232 1233 #define REG(r, info, p) ((r) * (info)->stride + (4 * ((p) / 32))) 1234 1235 static int ocelot_gpio_set_direction(struct pinctrl_dev *pctldev, 1236 struct pinctrl_gpio_range *range, 1237 unsigned int pin, bool input) 1238 { 1239 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1240 unsigned int p = pin % 32; 1241 1242 regmap_update_bits(info->map, REG(OCELOT_GPIO_OE, info, pin), BIT(p), 1243 input ? 0 : BIT(p)); 1244 1245 return 0; 1246 } 1247 1248 static int ocelot_gpio_request_enable(struct pinctrl_dev *pctldev, 1249 struct pinctrl_gpio_range *range, 1250 unsigned int offset) 1251 { 1252 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1253 unsigned int p = offset % 32; 1254 1255 regmap_update_bits(info->map, REG_ALT(0, info, offset), 1256 BIT(p), 0); 1257 regmap_update_bits(info->map, REG_ALT(1, info, offset), 1258 BIT(p), 0); 1259 1260 return 0; 1261 } 1262 1263 static int lan966x_gpio_request_enable(struct pinctrl_dev *pctldev, 1264 struct pinctrl_gpio_range *range, 1265 unsigned int offset) 1266 { 1267 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1268 unsigned int p = offset % 32; 1269 1270 regmap_update_bits(info->map, REG_ALT(0, info, offset), 1271 BIT(p), 0); 1272 regmap_update_bits(info->map, REG_ALT(1, info, offset), 1273 BIT(p), 0); 1274 regmap_update_bits(info->map, REG_ALT(2, info, offset), 1275 BIT(p), 0); 1276 1277 return 0; 1278 } 1279 1280 static const struct pinmux_ops ocelot_pmx_ops = { 1281 .get_functions_count = ocelot_get_functions_count, 1282 .get_function_name = ocelot_get_function_name, 1283 .get_function_groups = ocelot_get_function_groups, 1284 .set_mux = ocelot_pinmux_set_mux, 1285 .gpio_set_direction = ocelot_gpio_set_direction, 1286 .gpio_request_enable = ocelot_gpio_request_enable, 1287 }; 1288 1289 static const struct pinmux_ops lan966x_pmx_ops = { 1290 .get_functions_count = ocelot_get_functions_count, 1291 .get_function_name = ocelot_get_function_name, 1292 .get_function_groups = ocelot_get_function_groups, 1293 .set_mux = lan966x_pinmux_set_mux, 1294 .gpio_set_direction = ocelot_gpio_set_direction, 1295 .gpio_request_enable = lan966x_gpio_request_enable, 1296 }; 1297 1298 static int ocelot_pctl_get_groups_count(struct pinctrl_dev *pctldev) 1299 { 1300 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1301 1302 return info->desc->npins; 1303 } 1304 1305 static const char *ocelot_pctl_get_group_name(struct pinctrl_dev *pctldev, 1306 unsigned int group) 1307 { 1308 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1309 1310 return info->desc->pins[group].name; 1311 } 1312 1313 static int ocelot_pctl_get_group_pins(struct pinctrl_dev *pctldev, 1314 unsigned int group, 1315 const unsigned int **pins, 1316 unsigned int *num_pins) 1317 { 1318 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1319 1320 *pins = &info->desc->pins[group].number; 1321 *num_pins = 1; 1322 1323 return 0; 1324 } 1325 1326 static int ocelot_hw_get_value(struct ocelot_pinctrl *info, 1327 unsigned int pin, 1328 unsigned int reg, 1329 int *val) 1330 { 1331 int ret = -EOPNOTSUPP; 1332 1333 if (info->pincfg) { 1334 const struct ocelot_pincfg_data *opd = info->pincfg_data; 1335 u32 regcfg; 1336 1337 ret = regmap_read(info->pincfg, 1338 pin * regmap_get_reg_stride(info->pincfg), 1339 ®cfg); 1340 if (ret) 1341 return ret; 1342 1343 ret = 0; 1344 switch (reg) { 1345 case PINCONF_BIAS: 1346 *val = regcfg & (opd->pd_bit | opd->pu_bit); 1347 break; 1348 1349 case PINCONF_SCHMITT: 1350 *val = regcfg & opd->schmitt_bit; 1351 break; 1352 1353 case PINCONF_DRIVE_STRENGTH: 1354 *val = regcfg & opd->drive_bits; 1355 break; 1356 1357 default: 1358 ret = -EOPNOTSUPP; 1359 break; 1360 } 1361 } 1362 return ret; 1363 } 1364 1365 static int ocelot_pincfg_clrsetbits(struct ocelot_pinctrl *info, u32 regaddr, 1366 u32 clrbits, u32 setbits) 1367 { 1368 u32 val; 1369 int ret; 1370 1371 ret = regmap_read(info->pincfg, 1372 regaddr * regmap_get_reg_stride(info->pincfg), 1373 &val); 1374 if (ret) 1375 return ret; 1376 1377 val &= ~clrbits; 1378 val |= setbits; 1379 1380 ret = regmap_write(info->pincfg, 1381 regaddr * regmap_get_reg_stride(info->pincfg), 1382 val); 1383 1384 return ret; 1385 } 1386 1387 static int ocelot_hw_set_value(struct ocelot_pinctrl *info, 1388 unsigned int pin, 1389 unsigned int reg, 1390 int val) 1391 { 1392 int ret = -EOPNOTSUPP; 1393 1394 if (info->pincfg) { 1395 const struct ocelot_pincfg_data *opd = info->pincfg_data; 1396 1397 ret = 0; 1398 switch (reg) { 1399 case PINCONF_BIAS: 1400 ret = ocelot_pincfg_clrsetbits(info, pin, 1401 opd->pd_bit | opd->pu_bit, 1402 val); 1403 break; 1404 1405 case PINCONF_SCHMITT: 1406 ret = ocelot_pincfg_clrsetbits(info, pin, 1407 opd->schmitt_bit, 1408 val); 1409 break; 1410 1411 case PINCONF_DRIVE_STRENGTH: 1412 if (val <= 3) 1413 ret = ocelot_pincfg_clrsetbits(info, pin, 1414 opd->drive_bits, 1415 val); 1416 else 1417 ret = -EINVAL; 1418 break; 1419 1420 default: 1421 ret = -EOPNOTSUPP; 1422 break; 1423 } 1424 } 1425 return ret; 1426 } 1427 1428 static int ocelot_pinconf_get(struct pinctrl_dev *pctldev, 1429 unsigned int pin, unsigned long *config) 1430 { 1431 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1432 u32 param = pinconf_to_config_param(*config); 1433 int val, err; 1434 1435 switch (param) { 1436 case PIN_CONFIG_BIAS_DISABLE: 1437 case PIN_CONFIG_BIAS_PULL_UP: 1438 case PIN_CONFIG_BIAS_PULL_DOWN: 1439 err = ocelot_hw_get_value(info, pin, PINCONF_BIAS, &val); 1440 if (err) 1441 return err; 1442 if (param == PIN_CONFIG_BIAS_DISABLE) 1443 val = (val == 0); 1444 else if (param == PIN_CONFIG_BIAS_PULL_DOWN) 1445 val = !!(val & info->pincfg_data->pd_bit); 1446 else /* PIN_CONFIG_BIAS_PULL_UP */ 1447 val = !!(val & info->pincfg_data->pu_bit); 1448 break; 1449 1450 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 1451 if (!info->pincfg_data->schmitt_bit) 1452 return -EOPNOTSUPP; 1453 1454 err = ocelot_hw_get_value(info, pin, PINCONF_SCHMITT, &val); 1455 if (err) 1456 return err; 1457 1458 val = !!(val & info->pincfg_data->schmitt_bit); 1459 break; 1460 1461 case PIN_CONFIG_DRIVE_STRENGTH: 1462 err = ocelot_hw_get_value(info, pin, PINCONF_DRIVE_STRENGTH, 1463 &val); 1464 if (err) 1465 return err; 1466 break; 1467 1468 case PIN_CONFIG_OUTPUT: 1469 err = regmap_read(info->map, REG(OCELOT_GPIO_OUT, info, pin), 1470 &val); 1471 if (err) 1472 return err; 1473 val = !!(val & BIT(pin % 32)); 1474 break; 1475 1476 case PIN_CONFIG_INPUT_ENABLE: 1477 case PIN_CONFIG_OUTPUT_ENABLE: 1478 err = regmap_read(info->map, REG(OCELOT_GPIO_OE, info, pin), 1479 &val); 1480 if (err) 1481 return err; 1482 val = val & BIT(pin % 32); 1483 if (param == PIN_CONFIG_OUTPUT_ENABLE) 1484 val = !!val; 1485 else 1486 val = !val; 1487 break; 1488 1489 default: 1490 return -EOPNOTSUPP; 1491 } 1492 1493 *config = pinconf_to_config_packed(param, val); 1494 1495 return 0; 1496 } 1497 1498 static int ocelot_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 1499 unsigned long *configs, unsigned int num_configs) 1500 { 1501 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1502 const struct ocelot_pincfg_data *opd = info->pincfg_data; 1503 u32 param, arg, p; 1504 int cfg, err = 0; 1505 1506 for (cfg = 0; cfg < num_configs; cfg++) { 1507 param = pinconf_to_config_param(configs[cfg]); 1508 arg = pinconf_to_config_argument(configs[cfg]); 1509 1510 switch (param) { 1511 case PIN_CONFIG_BIAS_DISABLE: 1512 case PIN_CONFIG_BIAS_PULL_UP: 1513 case PIN_CONFIG_BIAS_PULL_DOWN: 1514 arg = (param == PIN_CONFIG_BIAS_DISABLE) ? 0 : 1515 (param == PIN_CONFIG_BIAS_PULL_UP) ? 1516 opd->pu_bit : opd->pd_bit; 1517 1518 err = ocelot_hw_set_value(info, pin, PINCONF_BIAS, arg); 1519 if (err) 1520 goto err; 1521 1522 break; 1523 1524 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 1525 if (!opd->schmitt_bit) 1526 return -EOPNOTSUPP; 1527 1528 arg = arg ? opd->schmitt_bit : 0; 1529 err = ocelot_hw_set_value(info, pin, PINCONF_SCHMITT, 1530 arg); 1531 if (err) 1532 goto err; 1533 1534 break; 1535 1536 case PIN_CONFIG_DRIVE_STRENGTH: 1537 err = ocelot_hw_set_value(info, pin, 1538 PINCONF_DRIVE_STRENGTH, 1539 arg); 1540 if (err) 1541 goto err; 1542 1543 break; 1544 1545 case PIN_CONFIG_OUTPUT_ENABLE: 1546 case PIN_CONFIG_INPUT_ENABLE: 1547 case PIN_CONFIG_OUTPUT: 1548 p = pin % 32; 1549 if (arg) 1550 regmap_write(info->map, 1551 REG(OCELOT_GPIO_OUT_SET, info, 1552 pin), 1553 BIT(p)); 1554 else 1555 regmap_write(info->map, 1556 REG(OCELOT_GPIO_OUT_CLR, info, 1557 pin), 1558 BIT(p)); 1559 regmap_update_bits(info->map, 1560 REG(OCELOT_GPIO_OE, info, pin), 1561 BIT(p), 1562 param == PIN_CONFIG_INPUT_ENABLE ? 1563 0 : BIT(p)); 1564 break; 1565 1566 default: 1567 err = -EOPNOTSUPP; 1568 } 1569 } 1570 err: 1571 return err; 1572 } 1573 1574 static const struct pinconf_ops ocelot_confops = { 1575 .is_generic = true, 1576 .pin_config_get = ocelot_pinconf_get, 1577 .pin_config_set = ocelot_pinconf_set, 1578 .pin_config_config_dbg_show = pinconf_generic_dump_config, 1579 }; 1580 1581 static const struct pinctrl_ops ocelot_pctl_ops = { 1582 .get_groups_count = ocelot_pctl_get_groups_count, 1583 .get_group_name = ocelot_pctl_get_group_name, 1584 .get_group_pins = ocelot_pctl_get_group_pins, 1585 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, 1586 .dt_free_map = pinconf_generic_dt_free_map, 1587 }; 1588 1589 static struct ocelot_match_data luton_desc = { 1590 .desc = { 1591 .name = "luton-pinctrl", 1592 .pins = luton_pins, 1593 .npins = ARRAY_SIZE(luton_pins), 1594 .pctlops = &ocelot_pctl_ops, 1595 .pmxops = &ocelot_pmx_ops, 1596 .owner = THIS_MODULE, 1597 }, 1598 }; 1599 1600 static struct ocelot_match_data serval_desc = { 1601 .desc = { 1602 .name = "serval-pinctrl", 1603 .pins = serval_pins, 1604 .npins = ARRAY_SIZE(serval_pins), 1605 .pctlops = &ocelot_pctl_ops, 1606 .pmxops = &ocelot_pmx_ops, 1607 .owner = THIS_MODULE, 1608 }, 1609 }; 1610 1611 static struct ocelot_match_data ocelot_desc = { 1612 .desc = { 1613 .name = "ocelot-pinctrl", 1614 .pins = ocelot_pins, 1615 .npins = ARRAY_SIZE(ocelot_pins), 1616 .pctlops = &ocelot_pctl_ops, 1617 .pmxops = &ocelot_pmx_ops, 1618 .owner = THIS_MODULE, 1619 }, 1620 }; 1621 1622 static struct ocelot_match_data jaguar2_desc = { 1623 .desc = { 1624 .name = "jaguar2-pinctrl", 1625 .pins = jaguar2_pins, 1626 .npins = ARRAY_SIZE(jaguar2_pins), 1627 .pctlops = &ocelot_pctl_ops, 1628 .pmxops = &ocelot_pmx_ops, 1629 .owner = THIS_MODULE, 1630 }, 1631 }; 1632 1633 static struct ocelot_match_data servalt_desc = { 1634 .desc = { 1635 .name = "servalt-pinctrl", 1636 .pins = servalt_pins, 1637 .npins = ARRAY_SIZE(servalt_pins), 1638 .pctlops = &ocelot_pctl_ops, 1639 .pmxops = &ocelot_pmx_ops, 1640 .owner = THIS_MODULE, 1641 }, 1642 }; 1643 1644 static struct ocelot_match_data sparx5_desc = { 1645 .desc = { 1646 .name = "sparx5-pinctrl", 1647 .pins = sparx5_pins, 1648 .npins = ARRAY_SIZE(sparx5_pins), 1649 .pctlops = &ocelot_pctl_ops, 1650 .pmxops = &ocelot_pmx_ops, 1651 .confops = &ocelot_confops, 1652 .owner = THIS_MODULE, 1653 }, 1654 .pincfg_data = { 1655 .pd_bit = BIT(4), 1656 .pu_bit = BIT(3), 1657 .drive_bits = GENMASK(1, 0), 1658 .schmitt_bit = BIT(2), 1659 }, 1660 }; 1661 1662 static struct ocelot_match_data lan966x_desc = { 1663 .desc = { 1664 .name = "lan966x-pinctrl", 1665 .pins = lan966x_pins, 1666 .npins = ARRAY_SIZE(lan966x_pins), 1667 .pctlops = &ocelot_pctl_ops, 1668 .pmxops = &lan966x_pmx_ops, 1669 .confops = &ocelot_confops, 1670 .owner = THIS_MODULE, 1671 }, 1672 .pincfg_data = { 1673 .pd_bit = BIT(3), 1674 .pu_bit = BIT(2), 1675 .drive_bits = GENMASK(1, 0), 1676 }, 1677 }; 1678 1679 static int ocelot_create_group_func_map(struct device *dev, 1680 struct ocelot_pinctrl *info) 1681 { 1682 int f, npins, i; 1683 u8 *pins = kcalloc(info->desc->npins, sizeof(u8), GFP_KERNEL); 1684 1685 if (!pins) 1686 return -ENOMEM; 1687 1688 for (f = 0; f < FUNC_MAX; f++) { 1689 for (npins = 0, i = 0; i < info->desc->npins; i++) { 1690 if (ocelot_pin_function_idx(info, i, f) >= 0) 1691 pins[npins++] = i; 1692 } 1693 1694 if (!npins) 1695 continue; 1696 1697 info->func[f].ngroups = npins; 1698 info->func[f].groups = devm_kcalloc(dev, npins, sizeof(char *), 1699 GFP_KERNEL); 1700 if (!info->func[f].groups) { 1701 kfree(pins); 1702 return -ENOMEM; 1703 } 1704 1705 for (i = 0; i < npins; i++) 1706 info->func[f].groups[i] = 1707 info->desc->pins[pins[i]].name; 1708 } 1709 1710 kfree(pins); 1711 1712 return 0; 1713 } 1714 1715 static int ocelot_pinctrl_register(struct platform_device *pdev, 1716 struct ocelot_pinctrl *info) 1717 { 1718 int ret; 1719 1720 ret = ocelot_create_group_func_map(&pdev->dev, info); 1721 if (ret) { 1722 dev_err(&pdev->dev, "Unable to create group func map.\n"); 1723 return ret; 1724 } 1725 1726 info->pctl = devm_pinctrl_register(&pdev->dev, info->desc, info); 1727 if (IS_ERR(info->pctl)) { 1728 dev_err(&pdev->dev, "Failed to register pinctrl\n"); 1729 return PTR_ERR(info->pctl); 1730 } 1731 1732 return 0; 1733 } 1734 1735 static int ocelot_gpio_get(struct gpio_chip *chip, unsigned int offset) 1736 { 1737 struct ocelot_pinctrl *info = gpiochip_get_data(chip); 1738 unsigned int val; 1739 1740 regmap_read(info->map, REG(OCELOT_GPIO_IN, info, offset), &val); 1741 1742 return !!(val & BIT(offset % 32)); 1743 } 1744 1745 static void ocelot_gpio_set(struct gpio_chip *chip, unsigned int offset, 1746 int value) 1747 { 1748 struct ocelot_pinctrl *info = gpiochip_get_data(chip); 1749 1750 if (value) 1751 regmap_write(info->map, REG(OCELOT_GPIO_OUT_SET, info, offset), 1752 BIT(offset % 32)); 1753 else 1754 regmap_write(info->map, REG(OCELOT_GPIO_OUT_CLR, info, offset), 1755 BIT(offset % 32)); 1756 } 1757 1758 static int ocelot_gpio_get_direction(struct gpio_chip *chip, 1759 unsigned int offset) 1760 { 1761 struct ocelot_pinctrl *info = gpiochip_get_data(chip); 1762 unsigned int val; 1763 1764 regmap_read(info->map, REG(OCELOT_GPIO_OE, info, offset), &val); 1765 1766 if (val & BIT(offset % 32)) 1767 return GPIO_LINE_DIRECTION_OUT; 1768 1769 return GPIO_LINE_DIRECTION_IN; 1770 } 1771 1772 static int ocelot_gpio_direction_input(struct gpio_chip *chip, 1773 unsigned int offset) 1774 { 1775 return pinctrl_gpio_direction_input(chip->base + offset); 1776 } 1777 1778 static int ocelot_gpio_direction_output(struct gpio_chip *chip, 1779 unsigned int offset, int value) 1780 { 1781 struct ocelot_pinctrl *info = gpiochip_get_data(chip); 1782 unsigned int pin = BIT(offset % 32); 1783 1784 if (value) 1785 regmap_write(info->map, REG(OCELOT_GPIO_OUT_SET, info, offset), 1786 pin); 1787 else 1788 regmap_write(info->map, REG(OCELOT_GPIO_OUT_CLR, info, offset), 1789 pin); 1790 1791 return pinctrl_gpio_direction_output(chip->base + offset); 1792 } 1793 1794 static const struct gpio_chip ocelot_gpiolib_chip = { 1795 .request = gpiochip_generic_request, 1796 .free = gpiochip_generic_free, 1797 .set = ocelot_gpio_set, 1798 .get = ocelot_gpio_get, 1799 .get_direction = ocelot_gpio_get_direction, 1800 .direction_input = ocelot_gpio_direction_input, 1801 .direction_output = ocelot_gpio_direction_output, 1802 .owner = THIS_MODULE, 1803 }; 1804 1805 static void ocelot_irq_mask(struct irq_data *data) 1806 { 1807 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 1808 struct ocelot_pinctrl *info = gpiochip_get_data(chip); 1809 unsigned int gpio = irqd_to_hwirq(data); 1810 1811 regmap_update_bits(info->map, REG(OCELOT_GPIO_INTR_ENA, info, gpio), 1812 BIT(gpio % 32), 0); 1813 gpiochip_disable_irq(chip, gpio); 1814 } 1815 1816 static void ocelot_irq_unmask(struct irq_data *data) 1817 { 1818 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 1819 struct ocelot_pinctrl *info = gpiochip_get_data(chip); 1820 unsigned int gpio = irqd_to_hwirq(data); 1821 1822 gpiochip_enable_irq(chip, gpio); 1823 regmap_update_bits(info->map, REG(OCELOT_GPIO_INTR_ENA, info, gpio), 1824 BIT(gpio % 32), BIT(gpio % 32)); 1825 } 1826 1827 static void ocelot_irq_ack(struct irq_data *data) 1828 { 1829 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 1830 struct ocelot_pinctrl *info = gpiochip_get_data(chip); 1831 unsigned int gpio = irqd_to_hwirq(data); 1832 1833 regmap_write_bits(info->map, REG(OCELOT_GPIO_INTR, info, gpio), 1834 BIT(gpio % 32), BIT(gpio % 32)); 1835 } 1836 1837 static int ocelot_irq_set_type(struct irq_data *data, unsigned int type); 1838 1839 static struct irq_chip ocelot_eoi_irqchip = { 1840 .name = "gpio", 1841 .irq_mask = ocelot_irq_mask, 1842 .irq_eoi = ocelot_irq_ack, 1843 .irq_unmask = ocelot_irq_unmask, 1844 .flags = IRQCHIP_EOI_THREADED | IRQCHIP_EOI_IF_HANDLED | 1845 IRQCHIP_IMMUTABLE, 1846 .irq_set_type = ocelot_irq_set_type, 1847 GPIOCHIP_IRQ_RESOURCE_HELPERS 1848 }; 1849 1850 static struct irq_chip ocelot_irqchip = { 1851 .name = "gpio", 1852 .irq_mask = ocelot_irq_mask, 1853 .irq_ack = ocelot_irq_ack, 1854 .irq_unmask = ocelot_irq_unmask, 1855 .irq_set_type = ocelot_irq_set_type, 1856 .flags = IRQCHIP_IMMUTABLE, 1857 GPIOCHIP_IRQ_RESOURCE_HELPERS 1858 }; 1859 1860 static int ocelot_irq_set_type(struct irq_data *data, unsigned int type) 1861 { 1862 type &= IRQ_TYPE_SENSE_MASK; 1863 1864 if (!(type & (IRQ_TYPE_EDGE_BOTH | IRQ_TYPE_LEVEL_HIGH))) 1865 return -EINVAL; 1866 1867 if (type & IRQ_TYPE_LEVEL_HIGH) 1868 irq_set_chip_handler_name_locked(data, &ocelot_eoi_irqchip, 1869 handle_fasteoi_irq, NULL); 1870 if (type & IRQ_TYPE_EDGE_BOTH) 1871 irq_set_chip_handler_name_locked(data, &ocelot_irqchip, 1872 handle_edge_irq, NULL); 1873 1874 return 0; 1875 } 1876 1877 static void ocelot_irq_handler(struct irq_desc *desc) 1878 { 1879 struct irq_chip *parent_chip = irq_desc_get_chip(desc); 1880 struct gpio_chip *chip = irq_desc_get_handler_data(desc); 1881 struct ocelot_pinctrl *info = gpiochip_get_data(chip); 1882 unsigned int id_reg = OCELOT_GPIO_INTR_IDENT * info->stride; 1883 unsigned int reg = 0, irq, i; 1884 unsigned long irqs; 1885 1886 for (i = 0; i < info->stride; i++) { 1887 regmap_read(info->map, id_reg + 4 * i, ®); 1888 if (!reg) 1889 continue; 1890 1891 chained_irq_enter(parent_chip, desc); 1892 1893 irqs = reg; 1894 1895 for_each_set_bit(irq, &irqs, 1896 min(32U, info->desc->npins - 32 * i)) 1897 generic_handle_domain_irq(chip->irq.domain, irq + 32 * i); 1898 1899 chained_irq_exit(parent_chip, desc); 1900 } 1901 } 1902 1903 static int ocelot_gpiochip_register(struct platform_device *pdev, 1904 struct ocelot_pinctrl *info) 1905 { 1906 struct gpio_chip *gc; 1907 struct gpio_irq_chip *girq; 1908 int irq; 1909 1910 info->gpio_chip = ocelot_gpiolib_chip; 1911 1912 gc = &info->gpio_chip; 1913 gc->ngpio = info->desc->npins; 1914 gc->parent = &pdev->dev; 1915 gc->base = -1; 1916 gc->label = "ocelot-gpio"; 1917 1918 irq = platform_get_irq_optional(pdev, 0); 1919 if (irq > 0) { 1920 girq = &gc->irq; 1921 gpio_irq_chip_set_chip(girq, &ocelot_irqchip); 1922 girq->parent_handler = ocelot_irq_handler; 1923 girq->num_parents = 1; 1924 girq->parents = devm_kcalloc(&pdev->dev, 1, 1925 sizeof(*girq->parents), 1926 GFP_KERNEL); 1927 if (!girq->parents) 1928 return -ENOMEM; 1929 girq->parents[0] = irq; 1930 girq->default_type = IRQ_TYPE_NONE; 1931 girq->handler = handle_edge_irq; 1932 } 1933 1934 return devm_gpiochip_add_data(&pdev->dev, gc, info); 1935 } 1936 1937 static const struct of_device_id ocelot_pinctrl_of_match[] = { 1938 { .compatible = "mscc,luton-pinctrl", .data = &luton_desc }, 1939 { .compatible = "mscc,serval-pinctrl", .data = &serval_desc }, 1940 { .compatible = "mscc,ocelot-pinctrl", .data = &ocelot_desc }, 1941 { .compatible = "mscc,jaguar2-pinctrl", .data = &jaguar2_desc }, 1942 { .compatible = "mscc,servalt-pinctrl", .data = &servalt_desc }, 1943 { .compatible = "microchip,sparx5-pinctrl", .data = &sparx5_desc }, 1944 { .compatible = "microchip,lan966x-pinctrl", .data = &lan966x_desc }, 1945 {}, 1946 }; 1947 MODULE_DEVICE_TABLE(of, ocelot_pinctrl_of_match); 1948 1949 static struct regmap *ocelot_pinctrl_create_pincfg(struct platform_device *pdev, 1950 const struct ocelot_pinctrl *info) 1951 { 1952 void __iomem *base; 1953 1954 const struct regmap_config regmap_config = { 1955 .reg_bits = 32, 1956 .val_bits = 32, 1957 .reg_stride = 4, 1958 .max_register = info->desc->npins * 4, 1959 .name = "pincfg", 1960 }; 1961 1962 base = devm_platform_ioremap_resource(pdev, 1); 1963 if (IS_ERR(base)) { 1964 dev_dbg(&pdev->dev, "Failed to ioremap config registers (no extended pinconf)\n"); 1965 return NULL; 1966 } 1967 1968 return devm_regmap_init_mmio(&pdev->dev, base, ®map_config); 1969 } 1970 1971 static int ocelot_pinctrl_probe(struct platform_device *pdev) 1972 { 1973 const struct ocelot_match_data *data; 1974 struct device *dev = &pdev->dev; 1975 struct ocelot_pinctrl *info; 1976 struct reset_control *reset; 1977 struct regmap *pincfg; 1978 void __iomem *base; 1979 int ret; 1980 struct regmap_config regmap_config = { 1981 .reg_bits = 32, 1982 .val_bits = 32, 1983 .reg_stride = 4, 1984 }; 1985 1986 info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL); 1987 if (!info) 1988 return -ENOMEM; 1989 1990 data = device_get_match_data(dev); 1991 if (!data) 1992 return -EINVAL; 1993 1994 info->desc = devm_kmemdup(dev, &data->desc, sizeof(*info->desc), 1995 GFP_KERNEL); 1996 if (!info->desc) 1997 return -ENOMEM; 1998 1999 info->pincfg_data = &data->pincfg_data; 2000 2001 reset = devm_reset_control_get_optional_shared(dev, "switch"); 2002 if (IS_ERR(reset)) 2003 return dev_err_probe(dev, PTR_ERR(reset), 2004 "Failed to get reset\n"); 2005 reset_control_reset(reset); 2006 2007 base = devm_ioremap_resource(dev, 2008 platform_get_resource(pdev, IORESOURCE_MEM, 0)); 2009 if (IS_ERR(base)) 2010 return PTR_ERR(base); 2011 2012 info->stride = 1 + (info->desc->npins - 1) / 32; 2013 2014 regmap_config.max_register = OCELOT_GPIO_SD_MAP * info->stride + 15 * 4; 2015 2016 info->map = devm_regmap_init_mmio(dev, base, ®map_config); 2017 if (IS_ERR(info->map)) { 2018 dev_err(dev, "Failed to create regmap\n"); 2019 return PTR_ERR(info->map); 2020 } 2021 dev_set_drvdata(dev, info->map); 2022 info->dev = dev; 2023 2024 /* Pinconf registers */ 2025 if (info->desc->confops) { 2026 pincfg = ocelot_pinctrl_create_pincfg(pdev, info); 2027 if (IS_ERR(pincfg)) 2028 dev_dbg(dev, "Failed to create pincfg regmap\n"); 2029 else 2030 info->pincfg = pincfg; 2031 } 2032 2033 ret = ocelot_pinctrl_register(pdev, info); 2034 if (ret) 2035 return ret; 2036 2037 ret = ocelot_gpiochip_register(pdev, info); 2038 if (ret) 2039 return ret; 2040 2041 dev_info(dev, "driver registered\n"); 2042 2043 return 0; 2044 } 2045 2046 static struct platform_driver ocelot_pinctrl_driver = { 2047 .driver = { 2048 .name = "pinctrl-ocelot", 2049 .of_match_table = of_match_ptr(ocelot_pinctrl_of_match), 2050 .suppress_bind_attrs = true, 2051 }, 2052 .probe = ocelot_pinctrl_probe, 2053 }; 2054 module_platform_driver(ocelot_pinctrl_driver); 2055 MODULE_LICENSE("Dual MIT/GPL"); 2056