1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* 3 * Microsemi SoCs pinctrl driver 4 * 5 * Author: <alexandre.belloni@free-electrons.com> 6 * License: Dual MIT/GPL 7 * Copyright (c) 2017 Microsemi Corporation 8 */ 9 10 #include <linux/gpio/driver.h> 11 #include <linux/interrupt.h> 12 #include <linux/io.h> 13 #include <linux/mfd/ocelot.h> 14 #include <linux/of_device.h> 15 #include <linux/of_irq.h> 16 #include <linux/of_platform.h> 17 #include <linux/pinctrl/pinctrl.h> 18 #include <linux/pinctrl/pinmux.h> 19 #include <linux/pinctrl/pinconf.h> 20 #include <linux/pinctrl/pinconf-generic.h> 21 #include <linux/platform_device.h> 22 #include <linux/regmap.h> 23 #include <linux/reset.h> 24 #include <linux/slab.h> 25 26 #include "core.h" 27 #include "pinconf.h" 28 #include "pinmux.h" 29 30 #define ocelot_clrsetbits(addr, clear, set) \ 31 writel((readl(addr) & ~(clear)) | (set), (addr)) 32 33 enum { 34 PINCONF_BIAS, 35 PINCONF_SCHMITT, 36 PINCONF_DRIVE_STRENGTH, 37 }; 38 39 /* GPIO standard registers */ 40 #define OCELOT_GPIO_OUT_SET 0x0 41 #define OCELOT_GPIO_OUT_CLR 0x4 42 #define OCELOT_GPIO_OUT 0x8 43 #define OCELOT_GPIO_IN 0xc 44 #define OCELOT_GPIO_OE 0x10 45 #define OCELOT_GPIO_INTR 0x14 46 #define OCELOT_GPIO_INTR_ENA 0x18 47 #define OCELOT_GPIO_INTR_IDENT 0x1c 48 #define OCELOT_GPIO_ALT0 0x20 49 #define OCELOT_GPIO_ALT1 0x24 50 #define OCELOT_GPIO_SD_MAP 0x28 51 52 #define OCELOT_FUNC_PER_PIN 4 53 54 enum { 55 FUNC_CAN0_a, 56 FUNC_CAN0_b, 57 FUNC_CAN1, 58 FUNC_CLKMON, 59 FUNC_NONE, 60 FUNC_FC0_a, 61 FUNC_FC0_b, 62 FUNC_FC0_c, 63 FUNC_FC1_a, 64 FUNC_FC1_b, 65 FUNC_FC1_c, 66 FUNC_FC2_a, 67 FUNC_FC2_b, 68 FUNC_FC3_a, 69 FUNC_FC3_b, 70 FUNC_FC3_c, 71 FUNC_FC4_a, 72 FUNC_FC4_b, 73 FUNC_FC4_c, 74 FUNC_FC_SHRD0, 75 FUNC_FC_SHRD1, 76 FUNC_FC_SHRD2, 77 FUNC_FC_SHRD3, 78 FUNC_FC_SHRD4, 79 FUNC_FC_SHRD5, 80 FUNC_FC_SHRD6, 81 FUNC_FC_SHRD7, 82 FUNC_FC_SHRD8, 83 FUNC_FC_SHRD9, 84 FUNC_FC_SHRD10, 85 FUNC_FC_SHRD11, 86 FUNC_FC_SHRD12, 87 FUNC_FC_SHRD13, 88 FUNC_FC_SHRD14, 89 FUNC_FC_SHRD15, 90 FUNC_FC_SHRD16, 91 FUNC_FC_SHRD17, 92 FUNC_FC_SHRD18, 93 FUNC_FC_SHRD19, 94 FUNC_FC_SHRD20, 95 FUNC_GPIO, 96 FUNC_IB_TRG_a, 97 FUNC_IB_TRG_b, 98 FUNC_IB_TRG_c, 99 FUNC_IRQ0, 100 FUNC_IRQ_IN_a, 101 FUNC_IRQ_IN_b, 102 FUNC_IRQ_IN_c, 103 FUNC_IRQ0_IN, 104 FUNC_IRQ_OUT_a, 105 FUNC_IRQ_OUT_b, 106 FUNC_IRQ_OUT_c, 107 FUNC_IRQ0_OUT, 108 FUNC_IRQ1, 109 FUNC_IRQ1_IN, 110 FUNC_IRQ1_OUT, 111 FUNC_EXT_IRQ, 112 FUNC_MIIM, 113 FUNC_MIIM_a, 114 FUNC_MIIM_b, 115 FUNC_MIIM_c, 116 FUNC_MIIM_Sa, 117 FUNC_MIIM_Sb, 118 FUNC_OB_TRG, 119 FUNC_OB_TRG_a, 120 FUNC_OB_TRG_b, 121 FUNC_PHY_LED, 122 FUNC_PCI_WAKE, 123 FUNC_MD, 124 FUNC_PTP0, 125 FUNC_PTP1, 126 FUNC_PTP2, 127 FUNC_PTP3, 128 FUNC_PTPSYNC_0, 129 FUNC_PTPSYNC_1, 130 FUNC_PTPSYNC_2, 131 FUNC_PTPSYNC_3, 132 FUNC_PTPSYNC_4, 133 FUNC_PTPSYNC_5, 134 FUNC_PTPSYNC_6, 135 FUNC_PTPSYNC_7, 136 FUNC_PWM, 137 FUNC_PWM_a, 138 FUNC_PWM_b, 139 FUNC_QSPI1, 140 FUNC_QSPI2, 141 FUNC_R, 142 FUNC_RECO_a, 143 FUNC_RECO_b, 144 FUNC_RECO_CLK, 145 FUNC_SD, 146 FUNC_SFP, 147 FUNC_SFP_SD, 148 FUNC_SG0, 149 FUNC_SG1, 150 FUNC_SG2, 151 FUNC_SGPIO_a, 152 FUNC_SGPIO_b, 153 FUNC_SI, 154 FUNC_SI2, 155 FUNC_TACHO, 156 FUNC_TACHO_a, 157 FUNC_TACHO_b, 158 FUNC_TWI, 159 FUNC_TWI2, 160 FUNC_TWI3, 161 FUNC_TWI_SCL_M, 162 FUNC_TWI_SLC_GATE, 163 FUNC_TWI_SLC_GATE_AD, 164 FUNC_UART, 165 FUNC_UART2, 166 FUNC_UART3, 167 FUNC_USB_H_a, 168 FUNC_USB_H_b, 169 FUNC_USB_H_c, 170 FUNC_USB_S_a, 171 FUNC_USB_S_b, 172 FUNC_USB_S_c, 173 FUNC_PLL_STAT, 174 FUNC_EMMC, 175 FUNC_EMMC_SD, 176 FUNC_REF_CLK, 177 FUNC_RCVRD_CLK, 178 FUNC_MAX 179 }; 180 181 static const char *const ocelot_function_names[] = { 182 [FUNC_CAN0_a] = "can0_a", 183 [FUNC_CAN0_b] = "can0_b", 184 [FUNC_CAN1] = "can1", 185 [FUNC_CLKMON] = "clkmon", 186 [FUNC_NONE] = "none", 187 [FUNC_FC0_a] = "fc0_a", 188 [FUNC_FC0_b] = "fc0_b", 189 [FUNC_FC0_c] = "fc0_c", 190 [FUNC_FC1_a] = "fc1_a", 191 [FUNC_FC1_b] = "fc1_b", 192 [FUNC_FC1_c] = "fc1_c", 193 [FUNC_FC2_a] = "fc2_a", 194 [FUNC_FC2_b] = "fc2_b", 195 [FUNC_FC3_a] = "fc3_a", 196 [FUNC_FC3_b] = "fc3_b", 197 [FUNC_FC3_c] = "fc3_c", 198 [FUNC_FC4_a] = "fc4_a", 199 [FUNC_FC4_b] = "fc4_b", 200 [FUNC_FC4_c] = "fc4_c", 201 [FUNC_FC_SHRD0] = "fc_shrd0", 202 [FUNC_FC_SHRD1] = "fc_shrd1", 203 [FUNC_FC_SHRD2] = "fc_shrd2", 204 [FUNC_FC_SHRD3] = "fc_shrd3", 205 [FUNC_FC_SHRD4] = "fc_shrd4", 206 [FUNC_FC_SHRD5] = "fc_shrd5", 207 [FUNC_FC_SHRD6] = "fc_shrd6", 208 [FUNC_FC_SHRD7] = "fc_shrd7", 209 [FUNC_FC_SHRD8] = "fc_shrd8", 210 [FUNC_FC_SHRD9] = "fc_shrd9", 211 [FUNC_FC_SHRD10] = "fc_shrd10", 212 [FUNC_FC_SHRD11] = "fc_shrd11", 213 [FUNC_FC_SHRD12] = "fc_shrd12", 214 [FUNC_FC_SHRD13] = "fc_shrd13", 215 [FUNC_FC_SHRD14] = "fc_shrd14", 216 [FUNC_FC_SHRD15] = "fc_shrd15", 217 [FUNC_FC_SHRD16] = "fc_shrd16", 218 [FUNC_FC_SHRD17] = "fc_shrd17", 219 [FUNC_FC_SHRD18] = "fc_shrd18", 220 [FUNC_FC_SHRD19] = "fc_shrd19", 221 [FUNC_FC_SHRD20] = "fc_shrd20", 222 [FUNC_GPIO] = "gpio", 223 [FUNC_IB_TRG_a] = "ib_trig_a", 224 [FUNC_IB_TRG_b] = "ib_trig_b", 225 [FUNC_IB_TRG_c] = "ib_trig_c", 226 [FUNC_IRQ0] = "irq0", 227 [FUNC_IRQ_IN_a] = "irq_in_a", 228 [FUNC_IRQ_IN_b] = "irq_in_b", 229 [FUNC_IRQ_IN_c] = "irq_in_c", 230 [FUNC_IRQ0_IN] = "irq0_in", 231 [FUNC_IRQ_OUT_a] = "irq_out_a", 232 [FUNC_IRQ_OUT_b] = "irq_out_b", 233 [FUNC_IRQ_OUT_c] = "irq_out_c", 234 [FUNC_IRQ0_OUT] = "irq0_out", 235 [FUNC_IRQ1] = "irq1", 236 [FUNC_IRQ1_IN] = "irq1_in", 237 [FUNC_IRQ1_OUT] = "irq1_out", 238 [FUNC_EXT_IRQ] = "ext_irq", 239 [FUNC_MIIM] = "miim", 240 [FUNC_MIIM_a] = "miim_a", 241 [FUNC_MIIM_b] = "miim_b", 242 [FUNC_MIIM_c] = "miim_c", 243 [FUNC_MIIM_Sa] = "miim_slave_a", 244 [FUNC_MIIM_Sb] = "miim_slave_b", 245 [FUNC_PHY_LED] = "phy_led", 246 [FUNC_PCI_WAKE] = "pci_wake", 247 [FUNC_MD] = "md", 248 [FUNC_OB_TRG] = "ob_trig", 249 [FUNC_OB_TRG_a] = "ob_trig_a", 250 [FUNC_OB_TRG_b] = "ob_trig_b", 251 [FUNC_PTP0] = "ptp0", 252 [FUNC_PTP1] = "ptp1", 253 [FUNC_PTP2] = "ptp2", 254 [FUNC_PTP3] = "ptp3", 255 [FUNC_PTPSYNC_0] = "ptpsync_0", 256 [FUNC_PTPSYNC_1] = "ptpsync_1", 257 [FUNC_PTPSYNC_2] = "ptpsync_2", 258 [FUNC_PTPSYNC_3] = "ptpsync_3", 259 [FUNC_PTPSYNC_4] = "ptpsync_4", 260 [FUNC_PTPSYNC_5] = "ptpsync_5", 261 [FUNC_PTPSYNC_6] = "ptpsync_6", 262 [FUNC_PTPSYNC_7] = "ptpsync_7", 263 [FUNC_PWM] = "pwm", 264 [FUNC_PWM_a] = "pwm_a", 265 [FUNC_PWM_b] = "pwm_b", 266 [FUNC_QSPI1] = "qspi1", 267 [FUNC_QSPI2] = "qspi2", 268 [FUNC_R] = "reserved", 269 [FUNC_RECO_a] = "reco_a", 270 [FUNC_RECO_b] = "reco_b", 271 [FUNC_RECO_CLK] = "reco_clk", 272 [FUNC_SD] = "sd", 273 [FUNC_SFP] = "sfp", 274 [FUNC_SFP_SD] = "sfp_sd", 275 [FUNC_SG0] = "sg0", 276 [FUNC_SG1] = "sg1", 277 [FUNC_SG2] = "sg2", 278 [FUNC_SGPIO_a] = "sgpio_a", 279 [FUNC_SGPIO_b] = "sgpio_b", 280 [FUNC_SI] = "si", 281 [FUNC_SI2] = "si2", 282 [FUNC_TACHO] = "tacho", 283 [FUNC_TACHO_a] = "tacho_a", 284 [FUNC_TACHO_b] = "tacho_b", 285 [FUNC_TWI] = "twi", 286 [FUNC_TWI2] = "twi2", 287 [FUNC_TWI3] = "twi3", 288 [FUNC_TWI_SCL_M] = "twi_scl_m", 289 [FUNC_TWI_SLC_GATE] = "twi_slc_gate", 290 [FUNC_TWI_SLC_GATE_AD] = "twi_slc_gate_ad", 291 [FUNC_USB_H_a] = "usb_host_a", 292 [FUNC_USB_H_b] = "usb_host_b", 293 [FUNC_USB_H_c] = "usb_host_c", 294 [FUNC_USB_S_a] = "usb_slave_a", 295 [FUNC_USB_S_b] = "usb_slave_b", 296 [FUNC_USB_S_c] = "usb_slave_c", 297 [FUNC_UART] = "uart", 298 [FUNC_UART2] = "uart2", 299 [FUNC_UART3] = "uart3", 300 [FUNC_PLL_STAT] = "pll_stat", 301 [FUNC_EMMC] = "emmc", 302 [FUNC_EMMC_SD] = "emmc_sd", 303 [FUNC_REF_CLK] = "ref_clk", 304 [FUNC_RCVRD_CLK] = "rcvrd_clk", 305 }; 306 307 struct ocelot_pmx_func { 308 const char **groups; 309 unsigned int ngroups; 310 }; 311 312 struct ocelot_pin_caps { 313 unsigned int pin; 314 unsigned char functions[OCELOT_FUNC_PER_PIN]; 315 unsigned char a_functions[OCELOT_FUNC_PER_PIN]; /* Additional functions */ 316 }; 317 318 struct ocelot_pincfg_data { 319 u8 pd_bit; 320 u8 pu_bit; 321 u8 drive_bits; 322 u8 schmitt_bit; 323 }; 324 325 struct ocelot_pinctrl { 326 struct device *dev; 327 struct pinctrl_dev *pctl; 328 struct gpio_chip gpio_chip; 329 struct regmap *map; 330 struct regmap *pincfg; 331 struct pinctrl_desc *desc; 332 const struct ocelot_pincfg_data *pincfg_data; 333 struct ocelot_pmx_func func[FUNC_MAX]; 334 u8 stride; 335 }; 336 337 struct ocelot_match_data { 338 struct pinctrl_desc desc; 339 struct ocelot_pincfg_data pincfg_data; 340 }; 341 342 #define LUTON_P(p, f0, f1) \ 343 static struct ocelot_pin_caps luton_pin_##p = { \ 344 .pin = p, \ 345 .functions = { \ 346 FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_NONE, \ 347 }, \ 348 } 349 350 LUTON_P(0, SG0, NONE); 351 LUTON_P(1, SG0, NONE); 352 LUTON_P(2, SG0, NONE); 353 LUTON_P(3, SG0, NONE); 354 LUTON_P(4, TACHO, NONE); 355 LUTON_P(5, TWI, PHY_LED); 356 LUTON_P(6, TWI, PHY_LED); 357 LUTON_P(7, NONE, PHY_LED); 358 LUTON_P(8, EXT_IRQ, PHY_LED); 359 LUTON_P(9, EXT_IRQ, PHY_LED); 360 LUTON_P(10, SFP, PHY_LED); 361 LUTON_P(11, SFP, PHY_LED); 362 LUTON_P(12, SFP, PHY_LED); 363 LUTON_P(13, SFP, PHY_LED); 364 LUTON_P(14, SI, PHY_LED); 365 LUTON_P(15, SI, PHY_LED); 366 LUTON_P(16, SI, PHY_LED); 367 LUTON_P(17, SFP, PHY_LED); 368 LUTON_P(18, SFP, PHY_LED); 369 LUTON_P(19, SFP, PHY_LED); 370 LUTON_P(20, SFP, PHY_LED); 371 LUTON_P(21, SFP, PHY_LED); 372 LUTON_P(22, SFP, PHY_LED); 373 LUTON_P(23, SFP, PHY_LED); 374 LUTON_P(24, SFP, PHY_LED); 375 LUTON_P(25, SFP, PHY_LED); 376 LUTON_P(26, SFP, PHY_LED); 377 LUTON_P(27, SFP, PHY_LED); 378 LUTON_P(28, SFP, PHY_LED); 379 LUTON_P(29, PWM, NONE); 380 LUTON_P(30, UART, NONE); 381 LUTON_P(31, UART, NONE); 382 383 #define LUTON_PIN(n) { \ 384 .number = n, \ 385 .name = "GPIO_"#n, \ 386 .drv_data = &luton_pin_##n \ 387 } 388 389 static const struct pinctrl_pin_desc luton_pins[] = { 390 LUTON_PIN(0), 391 LUTON_PIN(1), 392 LUTON_PIN(2), 393 LUTON_PIN(3), 394 LUTON_PIN(4), 395 LUTON_PIN(5), 396 LUTON_PIN(6), 397 LUTON_PIN(7), 398 LUTON_PIN(8), 399 LUTON_PIN(9), 400 LUTON_PIN(10), 401 LUTON_PIN(11), 402 LUTON_PIN(12), 403 LUTON_PIN(13), 404 LUTON_PIN(14), 405 LUTON_PIN(15), 406 LUTON_PIN(16), 407 LUTON_PIN(17), 408 LUTON_PIN(18), 409 LUTON_PIN(19), 410 LUTON_PIN(20), 411 LUTON_PIN(21), 412 LUTON_PIN(22), 413 LUTON_PIN(23), 414 LUTON_PIN(24), 415 LUTON_PIN(25), 416 LUTON_PIN(26), 417 LUTON_PIN(27), 418 LUTON_PIN(28), 419 LUTON_PIN(29), 420 LUTON_PIN(30), 421 LUTON_PIN(31), 422 }; 423 424 #define SERVAL_P(p, f0, f1, f2) \ 425 static struct ocelot_pin_caps serval_pin_##p = { \ 426 .pin = p, \ 427 .functions = { \ 428 FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2, \ 429 }, \ 430 } 431 432 SERVAL_P(0, SG0, NONE, NONE); 433 SERVAL_P(1, SG0, NONE, NONE); 434 SERVAL_P(2, SG0, NONE, NONE); 435 SERVAL_P(3, SG0, NONE, NONE); 436 SERVAL_P(4, TACHO, NONE, NONE); 437 SERVAL_P(5, PWM, NONE, NONE); 438 SERVAL_P(6, TWI, NONE, NONE); 439 SERVAL_P(7, TWI, NONE, NONE); 440 SERVAL_P(8, SI, NONE, NONE); 441 SERVAL_P(9, SI, MD, NONE); 442 SERVAL_P(10, SI, MD, NONE); 443 SERVAL_P(11, SFP, MD, TWI_SCL_M); 444 SERVAL_P(12, SFP, MD, TWI_SCL_M); 445 SERVAL_P(13, SFP, UART2, TWI_SCL_M); 446 SERVAL_P(14, SFP, UART2, TWI_SCL_M); 447 SERVAL_P(15, SFP, PTP0, TWI_SCL_M); 448 SERVAL_P(16, SFP, PTP0, TWI_SCL_M); 449 SERVAL_P(17, SFP, PCI_WAKE, TWI_SCL_M); 450 SERVAL_P(18, SFP, NONE, TWI_SCL_M); 451 SERVAL_P(19, SFP, NONE, TWI_SCL_M); 452 SERVAL_P(20, SFP, NONE, TWI_SCL_M); 453 SERVAL_P(21, SFP, NONE, TWI_SCL_M); 454 SERVAL_P(22, NONE, NONE, NONE); 455 SERVAL_P(23, NONE, NONE, NONE); 456 SERVAL_P(24, NONE, NONE, NONE); 457 SERVAL_P(25, NONE, NONE, NONE); 458 SERVAL_P(26, UART, NONE, NONE); 459 SERVAL_P(27, UART, NONE, NONE); 460 SERVAL_P(28, IRQ0, NONE, NONE); 461 SERVAL_P(29, IRQ1, NONE, NONE); 462 SERVAL_P(30, PTP0, NONE, NONE); 463 SERVAL_P(31, PTP0, NONE, NONE); 464 465 #define SERVAL_PIN(n) { \ 466 .number = n, \ 467 .name = "GPIO_"#n, \ 468 .drv_data = &serval_pin_##n \ 469 } 470 471 static const struct pinctrl_pin_desc serval_pins[] = { 472 SERVAL_PIN(0), 473 SERVAL_PIN(1), 474 SERVAL_PIN(2), 475 SERVAL_PIN(3), 476 SERVAL_PIN(4), 477 SERVAL_PIN(5), 478 SERVAL_PIN(6), 479 SERVAL_PIN(7), 480 SERVAL_PIN(8), 481 SERVAL_PIN(9), 482 SERVAL_PIN(10), 483 SERVAL_PIN(11), 484 SERVAL_PIN(12), 485 SERVAL_PIN(13), 486 SERVAL_PIN(14), 487 SERVAL_PIN(15), 488 SERVAL_PIN(16), 489 SERVAL_PIN(17), 490 SERVAL_PIN(18), 491 SERVAL_PIN(19), 492 SERVAL_PIN(20), 493 SERVAL_PIN(21), 494 SERVAL_PIN(22), 495 SERVAL_PIN(23), 496 SERVAL_PIN(24), 497 SERVAL_PIN(25), 498 SERVAL_PIN(26), 499 SERVAL_PIN(27), 500 SERVAL_PIN(28), 501 SERVAL_PIN(29), 502 SERVAL_PIN(30), 503 SERVAL_PIN(31), 504 }; 505 506 #define OCELOT_P(p, f0, f1, f2) \ 507 static struct ocelot_pin_caps ocelot_pin_##p = { \ 508 .pin = p, \ 509 .functions = { \ 510 FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2, \ 511 }, \ 512 } 513 514 OCELOT_P(0, SG0, NONE, NONE); 515 OCELOT_P(1, SG0, NONE, NONE); 516 OCELOT_P(2, SG0, NONE, NONE); 517 OCELOT_P(3, SG0, NONE, NONE); 518 OCELOT_P(4, IRQ0_IN, IRQ0_OUT, TWI_SCL_M); 519 OCELOT_P(5, IRQ1_IN, IRQ1_OUT, PCI_WAKE); 520 OCELOT_P(6, UART, TWI_SCL_M, NONE); 521 OCELOT_P(7, UART, TWI_SCL_M, NONE); 522 OCELOT_P(8, SI, TWI_SCL_M, IRQ0_OUT); 523 OCELOT_P(9, SI, TWI_SCL_M, IRQ1_OUT); 524 OCELOT_P(10, PTP2, TWI_SCL_M, SFP); 525 OCELOT_P(11, PTP3, TWI_SCL_M, SFP); 526 OCELOT_P(12, UART2, TWI_SCL_M, SFP); 527 OCELOT_P(13, UART2, TWI_SCL_M, SFP); 528 OCELOT_P(14, MIIM, TWI_SCL_M, SFP); 529 OCELOT_P(15, MIIM, TWI_SCL_M, SFP); 530 OCELOT_P(16, TWI, NONE, SI); 531 OCELOT_P(17, TWI, TWI_SCL_M, SI); 532 OCELOT_P(18, PTP0, TWI_SCL_M, NONE); 533 OCELOT_P(19, PTP1, TWI_SCL_M, NONE); 534 OCELOT_P(20, RECO_CLK, TACHO, TWI_SCL_M); 535 OCELOT_P(21, RECO_CLK, PWM, TWI_SCL_M); 536 537 #define OCELOT_PIN(n) { \ 538 .number = n, \ 539 .name = "GPIO_"#n, \ 540 .drv_data = &ocelot_pin_##n \ 541 } 542 543 static const struct pinctrl_pin_desc ocelot_pins[] = { 544 OCELOT_PIN(0), 545 OCELOT_PIN(1), 546 OCELOT_PIN(2), 547 OCELOT_PIN(3), 548 OCELOT_PIN(4), 549 OCELOT_PIN(5), 550 OCELOT_PIN(6), 551 OCELOT_PIN(7), 552 OCELOT_PIN(8), 553 OCELOT_PIN(9), 554 OCELOT_PIN(10), 555 OCELOT_PIN(11), 556 OCELOT_PIN(12), 557 OCELOT_PIN(13), 558 OCELOT_PIN(14), 559 OCELOT_PIN(15), 560 OCELOT_PIN(16), 561 OCELOT_PIN(17), 562 OCELOT_PIN(18), 563 OCELOT_PIN(19), 564 OCELOT_PIN(20), 565 OCELOT_PIN(21), 566 }; 567 568 #define JAGUAR2_P(p, f0, f1) \ 569 static struct ocelot_pin_caps jaguar2_pin_##p = { \ 570 .pin = p, \ 571 .functions = { \ 572 FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_NONE \ 573 }, \ 574 } 575 576 JAGUAR2_P(0, SG0, NONE); 577 JAGUAR2_P(1, SG0, NONE); 578 JAGUAR2_P(2, SG0, NONE); 579 JAGUAR2_P(3, SG0, NONE); 580 JAGUAR2_P(4, SG1, NONE); 581 JAGUAR2_P(5, SG1, NONE); 582 JAGUAR2_P(6, IRQ0_IN, IRQ0_OUT); 583 JAGUAR2_P(7, IRQ1_IN, IRQ1_OUT); 584 JAGUAR2_P(8, PTP0, NONE); 585 JAGUAR2_P(9, PTP1, NONE); 586 JAGUAR2_P(10, UART, NONE); 587 JAGUAR2_P(11, UART, NONE); 588 JAGUAR2_P(12, SG1, NONE); 589 JAGUAR2_P(13, SG1, NONE); 590 JAGUAR2_P(14, TWI, TWI_SCL_M); 591 JAGUAR2_P(15, TWI, NONE); 592 JAGUAR2_P(16, SI, TWI_SCL_M); 593 JAGUAR2_P(17, SI, TWI_SCL_M); 594 JAGUAR2_P(18, SI, TWI_SCL_M); 595 JAGUAR2_P(19, PCI_WAKE, NONE); 596 JAGUAR2_P(20, IRQ0_OUT, TWI_SCL_M); 597 JAGUAR2_P(21, IRQ1_OUT, TWI_SCL_M); 598 JAGUAR2_P(22, TACHO, NONE); 599 JAGUAR2_P(23, PWM, NONE); 600 JAGUAR2_P(24, UART2, NONE); 601 JAGUAR2_P(25, UART2, SI); 602 JAGUAR2_P(26, PTP2, SI); 603 JAGUAR2_P(27, PTP3, SI); 604 JAGUAR2_P(28, TWI2, SI); 605 JAGUAR2_P(29, TWI2, SI); 606 JAGUAR2_P(30, SG2, SI); 607 JAGUAR2_P(31, SG2, SI); 608 JAGUAR2_P(32, SG2, SI); 609 JAGUAR2_P(33, SG2, SI); 610 JAGUAR2_P(34, NONE, TWI_SCL_M); 611 JAGUAR2_P(35, NONE, TWI_SCL_M); 612 JAGUAR2_P(36, NONE, TWI_SCL_M); 613 JAGUAR2_P(37, NONE, TWI_SCL_M); 614 JAGUAR2_P(38, NONE, TWI_SCL_M); 615 JAGUAR2_P(39, NONE, TWI_SCL_M); 616 JAGUAR2_P(40, NONE, TWI_SCL_M); 617 JAGUAR2_P(41, NONE, TWI_SCL_M); 618 JAGUAR2_P(42, NONE, TWI_SCL_M); 619 JAGUAR2_P(43, NONE, TWI_SCL_M); 620 JAGUAR2_P(44, NONE, SFP); 621 JAGUAR2_P(45, NONE, SFP); 622 JAGUAR2_P(46, NONE, SFP); 623 JAGUAR2_P(47, NONE, SFP); 624 JAGUAR2_P(48, SFP, NONE); 625 JAGUAR2_P(49, SFP, SI); 626 JAGUAR2_P(50, SFP, SI); 627 JAGUAR2_P(51, SFP, SI); 628 JAGUAR2_P(52, SFP, NONE); 629 JAGUAR2_P(53, SFP, NONE); 630 JAGUAR2_P(54, SFP, NONE); 631 JAGUAR2_P(55, SFP, NONE); 632 JAGUAR2_P(56, MIIM, SFP); 633 JAGUAR2_P(57, MIIM, SFP); 634 JAGUAR2_P(58, MIIM, SFP); 635 JAGUAR2_P(59, MIIM, SFP); 636 JAGUAR2_P(60, NONE, NONE); 637 JAGUAR2_P(61, NONE, NONE); 638 JAGUAR2_P(62, NONE, NONE); 639 JAGUAR2_P(63, NONE, NONE); 640 641 #define JAGUAR2_PIN(n) { \ 642 .number = n, \ 643 .name = "GPIO_"#n, \ 644 .drv_data = &jaguar2_pin_##n \ 645 } 646 647 static const struct pinctrl_pin_desc jaguar2_pins[] = { 648 JAGUAR2_PIN(0), 649 JAGUAR2_PIN(1), 650 JAGUAR2_PIN(2), 651 JAGUAR2_PIN(3), 652 JAGUAR2_PIN(4), 653 JAGUAR2_PIN(5), 654 JAGUAR2_PIN(6), 655 JAGUAR2_PIN(7), 656 JAGUAR2_PIN(8), 657 JAGUAR2_PIN(9), 658 JAGUAR2_PIN(10), 659 JAGUAR2_PIN(11), 660 JAGUAR2_PIN(12), 661 JAGUAR2_PIN(13), 662 JAGUAR2_PIN(14), 663 JAGUAR2_PIN(15), 664 JAGUAR2_PIN(16), 665 JAGUAR2_PIN(17), 666 JAGUAR2_PIN(18), 667 JAGUAR2_PIN(19), 668 JAGUAR2_PIN(20), 669 JAGUAR2_PIN(21), 670 JAGUAR2_PIN(22), 671 JAGUAR2_PIN(23), 672 JAGUAR2_PIN(24), 673 JAGUAR2_PIN(25), 674 JAGUAR2_PIN(26), 675 JAGUAR2_PIN(27), 676 JAGUAR2_PIN(28), 677 JAGUAR2_PIN(29), 678 JAGUAR2_PIN(30), 679 JAGUAR2_PIN(31), 680 JAGUAR2_PIN(32), 681 JAGUAR2_PIN(33), 682 JAGUAR2_PIN(34), 683 JAGUAR2_PIN(35), 684 JAGUAR2_PIN(36), 685 JAGUAR2_PIN(37), 686 JAGUAR2_PIN(38), 687 JAGUAR2_PIN(39), 688 JAGUAR2_PIN(40), 689 JAGUAR2_PIN(41), 690 JAGUAR2_PIN(42), 691 JAGUAR2_PIN(43), 692 JAGUAR2_PIN(44), 693 JAGUAR2_PIN(45), 694 JAGUAR2_PIN(46), 695 JAGUAR2_PIN(47), 696 JAGUAR2_PIN(48), 697 JAGUAR2_PIN(49), 698 JAGUAR2_PIN(50), 699 JAGUAR2_PIN(51), 700 JAGUAR2_PIN(52), 701 JAGUAR2_PIN(53), 702 JAGUAR2_PIN(54), 703 JAGUAR2_PIN(55), 704 JAGUAR2_PIN(56), 705 JAGUAR2_PIN(57), 706 JAGUAR2_PIN(58), 707 JAGUAR2_PIN(59), 708 JAGUAR2_PIN(60), 709 JAGUAR2_PIN(61), 710 JAGUAR2_PIN(62), 711 JAGUAR2_PIN(63), 712 }; 713 714 #define SERVALT_P(p, f0, f1, f2) \ 715 static struct ocelot_pin_caps servalt_pin_##p = { \ 716 .pin = p, \ 717 .functions = { \ 718 FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2 \ 719 }, \ 720 } 721 722 SERVALT_P(0, SG0, NONE, NONE); 723 SERVALT_P(1, SG0, NONE, NONE); 724 SERVALT_P(2, SG0, NONE, NONE); 725 SERVALT_P(3, SG0, NONE, NONE); 726 SERVALT_P(4, IRQ0_IN, IRQ0_OUT, TWI_SCL_M); 727 SERVALT_P(5, IRQ1_IN, IRQ1_OUT, TWI_SCL_M); 728 SERVALT_P(6, UART, NONE, NONE); 729 SERVALT_P(7, UART, NONE, NONE); 730 SERVALT_P(8, SI, SFP, TWI_SCL_M); 731 SERVALT_P(9, PCI_WAKE, SFP, SI); 732 SERVALT_P(10, PTP0, SFP, TWI_SCL_M); 733 SERVALT_P(11, PTP1, SFP, TWI_SCL_M); 734 SERVALT_P(12, REF_CLK, SFP, TWI_SCL_M); 735 SERVALT_P(13, REF_CLK, SFP, TWI_SCL_M); 736 SERVALT_P(14, REF_CLK, IRQ0_OUT, SI); 737 SERVALT_P(15, REF_CLK, IRQ1_OUT, SI); 738 SERVALT_P(16, TACHO, SFP, SI); 739 SERVALT_P(17, PWM, NONE, TWI_SCL_M); 740 SERVALT_P(18, PTP2, SFP, SI); 741 SERVALT_P(19, PTP3, SFP, SI); 742 SERVALT_P(20, UART2, SFP, SI); 743 SERVALT_P(21, UART2, NONE, NONE); 744 SERVALT_P(22, MIIM, SFP, TWI2); 745 SERVALT_P(23, MIIM, SFP, TWI2); 746 SERVALT_P(24, TWI, NONE, NONE); 747 SERVALT_P(25, TWI, SFP, TWI_SCL_M); 748 SERVALT_P(26, TWI_SCL_M, SFP, SI); 749 SERVALT_P(27, TWI_SCL_M, SFP, SI); 750 SERVALT_P(28, TWI_SCL_M, SFP, SI); 751 SERVALT_P(29, TWI_SCL_M, NONE, NONE); 752 SERVALT_P(30, TWI_SCL_M, NONE, NONE); 753 SERVALT_P(31, TWI_SCL_M, NONE, NONE); 754 SERVALT_P(32, TWI_SCL_M, NONE, NONE); 755 SERVALT_P(33, RCVRD_CLK, NONE, NONE); 756 SERVALT_P(34, RCVRD_CLK, NONE, NONE); 757 SERVALT_P(35, RCVRD_CLK, NONE, NONE); 758 SERVALT_P(36, RCVRD_CLK, NONE, NONE); 759 760 #define SERVALT_PIN(n) { \ 761 .number = n, \ 762 .name = "GPIO_"#n, \ 763 .drv_data = &servalt_pin_##n \ 764 } 765 766 static const struct pinctrl_pin_desc servalt_pins[] = { 767 SERVALT_PIN(0), 768 SERVALT_PIN(1), 769 SERVALT_PIN(2), 770 SERVALT_PIN(3), 771 SERVALT_PIN(4), 772 SERVALT_PIN(5), 773 SERVALT_PIN(6), 774 SERVALT_PIN(7), 775 SERVALT_PIN(8), 776 SERVALT_PIN(9), 777 SERVALT_PIN(10), 778 SERVALT_PIN(11), 779 SERVALT_PIN(12), 780 SERVALT_PIN(13), 781 SERVALT_PIN(14), 782 SERVALT_PIN(15), 783 SERVALT_PIN(16), 784 SERVALT_PIN(17), 785 SERVALT_PIN(18), 786 SERVALT_PIN(19), 787 SERVALT_PIN(20), 788 SERVALT_PIN(21), 789 SERVALT_PIN(22), 790 SERVALT_PIN(23), 791 SERVALT_PIN(24), 792 SERVALT_PIN(25), 793 SERVALT_PIN(26), 794 SERVALT_PIN(27), 795 SERVALT_PIN(28), 796 SERVALT_PIN(29), 797 SERVALT_PIN(30), 798 SERVALT_PIN(31), 799 SERVALT_PIN(32), 800 SERVALT_PIN(33), 801 SERVALT_PIN(34), 802 SERVALT_PIN(35), 803 SERVALT_PIN(36), 804 }; 805 806 #define SPARX5_P(p, f0, f1, f2) \ 807 static struct ocelot_pin_caps sparx5_pin_##p = { \ 808 .pin = p, \ 809 .functions = { \ 810 FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2 \ 811 }, \ 812 } 813 814 SPARX5_P(0, SG0, PLL_STAT, NONE); 815 SPARX5_P(1, SG0, NONE, NONE); 816 SPARX5_P(2, SG0, NONE, NONE); 817 SPARX5_P(3, SG0, NONE, NONE); 818 SPARX5_P(4, SG1, NONE, NONE); 819 SPARX5_P(5, SG1, NONE, NONE); 820 SPARX5_P(6, IRQ0_IN, IRQ0_OUT, SFP); 821 SPARX5_P(7, IRQ1_IN, IRQ1_OUT, SFP); 822 SPARX5_P(8, PTP0, NONE, SFP); 823 SPARX5_P(9, PTP1, SFP, TWI_SCL_M); 824 SPARX5_P(10, UART, NONE, NONE); 825 SPARX5_P(11, UART, NONE, NONE); 826 SPARX5_P(12, SG1, NONE, NONE); 827 SPARX5_P(13, SG1, NONE, NONE); 828 SPARX5_P(14, TWI, TWI_SCL_M, NONE); 829 SPARX5_P(15, TWI, NONE, NONE); 830 SPARX5_P(16, SI, TWI_SCL_M, SFP); 831 SPARX5_P(17, SI, TWI_SCL_M, SFP); 832 SPARX5_P(18, SI, TWI_SCL_M, SFP); 833 SPARX5_P(19, PCI_WAKE, TWI_SCL_M, SFP); 834 SPARX5_P(20, IRQ0_OUT, TWI_SCL_M, SFP); 835 SPARX5_P(21, IRQ1_OUT, TACHO, SFP); 836 SPARX5_P(22, TACHO, IRQ0_OUT, TWI_SCL_M); 837 SPARX5_P(23, PWM, UART3, TWI_SCL_M); 838 SPARX5_P(24, PTP2, UART3, TWI_SCL_M); 839 SPARX5_P(25, PTP3, SI, TWI_SCL_M); 840 SPARX5_P(26, UART2, SI, TWI_SCL_M); 841 SPARX5_P(27, UART2, SI, TWI_SCL_M); 842 SPARX5_P(28, TWI2, SI, SFP); 843 SPARX5_P(29, TWI2, SI, SFP); 844 SPARX5_P(30, SG2, SI, PWM); 845 SPARX5_P(31, SG2, SI, TWI_SCL_M); 846 SPARX5_P(32, SG2, SI, TWI_SCL_M); 847 SPARX5_P(33, SG2, SI, SFP); 848 SPARX5_P(34, NONE, TWI_SCL_M, EMMC); 849 SPARX5_P(35, SFP, TWI_SCL_M, EMMC); 850 SPARX5_P(36, SFP, TWI_SCL_M, EMMC); 851 SPARX5_P(37, SFP, NONE, EMMC); 852 SPARX5_P(38, NONE, TWI_SCL_M, EMMC); 853 SPARX5_P(39, SI2, TWI_SCL_M, EMMC); 854 SPARX5_P(40, SI2, TWI_SCL_M, EMMC); 855 SPARX5_P(41, SI2, TWI_SCL_M, EMMC); 856 SPARX5_P(42, SI2, TWI_SCL_M, EMMC); 857 SPARX5_P(43, SI2, TWI_SCL_M, EMMC); 858 SPARX5_P(44, SI, SFP, EMMC); 859 SPARX5_P(45, SI, SFP, EMMC); 860 SPARX5_P(46, NONE, SFP, EMMC); 861 SPARX5_P(47, NONE, SFP, EMMC); 862 SPARX5_P(48, TWI3, SI, SFP); 863 SPARX5_P(49, TWI3, NONE, SFP); 864 SPARX5_P(50, SFP, NONE, TWI_SCL_M); 865 SPARX5_P(51, SFP, SI, TWI_SCL_M); 866 SPARX5_P(52, SFP, MIIM, TWI_SCL_M); 867 SPARX5_P(53, SFP, MIIM, TWI_SCL_M); 868 SPARX5_P(54, SFP, PTP2, TWI_SCL_M); 869 SPARX5_P(55, SFP, PTP3, PCI_WAKE); 870 SPARX5_P(56, MIIM, SFP, TWI_SCL_M); 871 SPARX5_P(57, MIIM, SFP, TWI_SCL_M); 872 SPARX5_P(58, MIIM, SFP, TWI_SCL_M); 873 SPARX5_P(59, MIIM, SFP, NONE); 874 SPARX5_P(60, RECO_CLK, NONE, NONE); 875 SPARX5_P(61, RECO_CLK, NONE, NONE); 876 SPARX5_P(62, RECO_CLK, PLL_STAT, NONE); 877 SPARX5_P(63, RECO_CLK, NONE, NONE); 878 879 #define SPARX5_PIN(n) { \ 880 .number = n, \ 881 .name = "GPIO_"#n, \ 882 .drv_data = &sparx5_pin_##n \ 883 } 884 885 static const struct pinctrl_pin_desc sparx5_pins[] = { 886 SPARX5_PIN(0), 887 SPARX5_PIN(1), 888 SPARX5_PIN(2), 889 SPARX5_PIN(3), 890 SPARX5_PIN(4), 891 SPARX5_PIN(5), 892 SPARX5_PIN(6), 893 SPARX5_PIN(7), 894 SPARX5_PIN(8), 895 SPARX5_PIN(9), 896 SPARX5_PIN(10), 897 SPARX5_PIN(11), 898 SPARX5_PIN(12), 899 SPARX5_PIN(13), 900 SPARX5_PIN(14), 901 SPARX5_PIN(15), 902 SPARX5_PIN(16), 903 SPARX5_PIN(17), 904 SPARX5_PIN(18), 905 SPARX5_PIN(19), 906 SPARX5_PIN(20), 907 SPARX5_PIN(21), 908 SPARX5_PIN(22), 909 SPARX5_PIN(23), 910 SPARX5_PIN(24), 911 SPARX5_PIN(25), 912 SPARX5_PIN(26), 913 SPARX5_PIN(27), 914 SPARX5_PIN(28), 915 SPARX5_PIN(29), 916 SPARX5_PIN(30), 917 SPARX5_PIN(31), 918 SPARX5_PIN(32), 919 SPARX5_PIN(33), 920 SPARX5_PIN(34), 921 SPARX5_PIN(35), 922 SPARX5_PIN(36), 923 SPARX5_PIN(37), 924 SPARX5_PIN(38), 925 SPARX5_PIN(39), 926 SPARX5_PIN(40), 927 SPARX5_PIN(41), 928 SPARX5_PIN(42), 929 SPARX5_PIN(43), 930 SPARX5_PIN(44), 931 SPARX5_PIN(45), 932 SPARX5_PIN(46), 933 SPARX5_PIN(47), 934 SPARX5_PIN(48), 935 SPARX5_PIN(49), 936 SPARX5_PIN(50), 937 SPARX5_PIN(51), 938 SPARX5_PIN(52), 939 SPARX5_PIN(53), 940 SPARX5_PIN(54), 941 SPARX5_PIN(55), 942 SPARX5_PIN(56), 943 SPARX5_PIN(57), 944 SPARX5_PIN(58), 945 SPARX5_PIN(59), 946 SPARX5_PIN(60), 947 SPARX5_PIN(61), 948 SPARX5_PIN(62), 949 SPARX5_PIN(63), 950 }; 951 952 #define LAN966X_P(p, f0, f1, f2, f3, f4, f5, f6, f7) \ 953 static struct ocelot_pin_caps lan966x_pin_##p = { \ 954 .pin = p, \ 955 .functions = { \ 956 FUNC_##f0, FUNC_##f1, FUNC_##f2, \ 957 FUNC_##f3 \ 958 }, \ 959 .a_functions = { \ 960 FUNC_##f4, FUNC_##f5, FUNC_##f6, \ 961 FUNC_##f7 \ 962 }, \ 963 } 964 965 /* Pinmuxing table taken from data sheet */ 966 /* Pin FUNC0 FUNC1 FUNC2 FUNC3 FUNC4 FUNC5 FUNC6 FUNC7 */ 967 LAN966X_P(0, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 968 LAN966X_P(1, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 969 LAN966X_P(2, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 970 LAN966X_P(3, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 971 LAN966X_P(4, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 972 LAN966X_P(5, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 973 LAN966X_P(6, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 974 LAN966X_P(7, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 975 LAN966X_P(8, GPIO, FC0_a, USB_H_b, NONE, USB_S_b, NONE, NONE, R); 976 LAN966X_P(9, GPIO, FC0_a, USB_H_b, NONE, NONE, NONE, NONE, R); 977 LAN966X_P(10, GPIO, FC0_a, NONE, NONE, NONE, NONE, NONE, R); 978 LAN966X_P(11, GPIO, FC1_a, NONE, NONE, NONE, NONE, NONE, R); 979 LAN966X_P(12, GPIO, FC1_a, NONE, NONE, NONE, NONE, NONE, R); 980 LAN966X_P(13, GPIO, FC1_a, NONE, NONE, NONE, NONE, NONE, R); 981 LAN966X_P(14, GPIO, FC2_a, NONE, NONE, NONE, NONE, NONE, R); 982 LAN966X_P(15, GPIO, FC2_a, NONE, NONE, NONE, NONE, NONE, R); 983 LAN966X_P(16, GPIO, FC2_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, IRQ_OUT_c, R); 984 LAN966X_P(17, GPIO, FC3_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, IRQ_OUT_c, R); 985 LAN966X_P(18, GPIO, FC3_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, IRQ_OUT_c, R); 986 LAN966X_P(19, GPIO, FC3_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, IRQ_OUT_c, R); 987 LAN966X_P(20, GPIO, FC4_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, NONE, R); 988 LAN966X_P(21, GPIO, FC4_a, NONE, NONE, OB_TRG_a, NONE, NONE, R); 989 LAN966X_P(22, GPIO, FC4_a, NONE, NONE, OB_TRG_a, NONE, NONE, R); 990 LAN966X_P(23, GPIO, NONE, NONE, NONE, OB_TRG_a, NONE, NONE, R); 991 LAN966X_P(24, GPIO, FC0_b, IB_TRG_a, USB_H_c, OB_TRG_a, IRQ_IN_c, TACHO_a, R); 992 LAN966X_P(25, GPIO, FC0_b, IB_TRG_a, USB_H_c, OB_TRG_a, IRQ_OUT_c, SFP_SD, R); 993 LAN966X_P(26, GPIO, FC0_b, IB_TRG_a, USB_S_c, OB_TRG_a, CAN0_a, SFP_SD, R); 994 LAN966X_P(27, GPIO, NONE, NONE, NONE, OB_TRG_a, CAN0_a, PWM_a, R); 995 LAN966X_P(28, GPIO, MIIM_a, NONE, NONE, OB_TRG_a, IRQ_OUT_c, SFP_SD, R); 996 LAN966X_P(29, GPIO, MIIM_a, NONE, NONE, OB_TRG_a, NONE, NONE, R); 997 LAN966X_P(30, GPIO, FC3_c, CAN1, CLKMON, OB_TRG, RECO_b, NONE, R); 998 LAN966X_P(31, GPIO, FC3_c, CAN1, CLKMON, OB_TRG, RECO_b, NONE, R); 999 LAN966X_P(32, GPIO, FC3_c, NONE, SGPIO_a, NONE, MIIM_Sa, NONE, R); 1000 LAN966X_P(33, GPIO, FC1_b, NONE, SGPIO_a, NONE, MIIM_Sa, MIIM_b, R); 1001 LAN966X_P(34, GPIO, FC1_b, NONE, SGPIO_a, NONE, MIIM_Sa, MIIM_b, R); 1002 LAN966X_P(35, GPIO, FC1_b, PTPSYNC_0, SGPIO_a, CAN0_b, NONE, NONE, R); 1003 LAN966X_P(36, GPIO, NONE, PTPSYNC_1, NONE, CAN0_b, NONE, NONE, R); 1004 LAN966X_P(37, GPIO, FC_SHRD0, PTPSYNC_2, TWI_SLC_GATE_AD, NONE, NONE, NONE, R); 1005 LAN966X_P(38, GPIO, NONE, PTPSYNC_3, NONE, NONE, NONE, NONE, R); 1006 LAN966X_P(39, GPIO, NONE, PTPSYNC_4, NONE, NONE, NONE, NONE, R); 1007 LAN966X_P(40, GPIO, FC_SHRD1, PTPSYNC_5, NONE, NONE, NONE, NONE, R); 1008 LAN966X_P(41, GPIO, FC_SHRD2, PTPSYNC_6, TWI_SLC_GATE_AD, NONE, NONE, NONE, R); 1009 LAN966X_P(42, GPIO, FC_SHRD3, PTPSYNC_7, TWI_SLC_GATE_AD, NONE, NONE, NONE, R); 1010 LAN966X_P(43, GPIO, FC2_b, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, RECO_a, IRQ_IN_a, R); 1011 LAN966X_P(44, GPIO, FC2_b, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, RECO_a, IRQ_IN_a, R); 1012 LAN966X_P(45, GPIO, FC2_b, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, NONE, IRQ_IN_a, R); 1013 LAN966X_P(46, GPIO, FC1_c, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, FC_SHRD4, IRQ_IN_a, R); 1014 LAN966X_P(47, GPIO, FC1_c, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, FC_SHRD5, IRQ_IN_a, R); 1015 LAN966X_P(48, GPIO, FC1_c, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, FC_SHRD6, IRQ_IN_a, R); 1016 LAN966X_P(49, GPIO, FC_SHRD7, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, TWI_SLC_GATE, IRQ_IN_a, R); 1017 LAN966X_P(50, GPIO, FC_SHRD16, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, TWI_SLC_GATE, NONE, R); 1018 LAN966X_P(51, GPIO, FC3_b, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, PWM_b, IRQ_IN_b, R); 1019 LAN966X_P(52, GPIO, FC3_b, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, TACHO_b, IRQ_IN_b, R); 1020 LAN966X_P(53, GPIO, FC3_b, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, NONE, IRQ_IN_b, R); 1021 LAN966X_P(54, GPIO, FC_SHRD8, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, TWI_SLC_GATE, IRQ_IN_b, R); 1022 LAN966X_P(55, GPIO, FC_SHRD9, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, TWI_SLC_GATE, IRQ_IN_b, R); 1023 LAN966X_P(56, GPIO, FC4_b, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, FC_SHRD10, IRQ_IN_b, R); 1024 LAN966X_P(57, GPIO, FC4_b, TWI_SLC_GATE, IB_TRG_c, IRQ_OUT_b, FC_SHRD11, IRQ_IN_b, R); 1025 LAN966X_P(58, GPIO, FC4_b, TWI_SLC_GATE, IB_TRG_c, IRQ_OUT_b, FC_SHRD12, IRQ_IN_b, R); 1026 LAN966X_P(59, GPIO, QSPI1, MIIM_c, NONE, NONE, MIIM_Sb, NONE, R); 1027 LAN966X_P(60, GPIO, QSPI1, MIIM_c, NONE, NONE, MIIM_Sb, NONE, R); 1028 LAN966X_P(61, GPIO, QSPI1, NONE, SGPIO_b, FC0_c, MIIM_Sb, NONE, R); 1029 LAN966X_P(62, GPIO, QSPI1, FC_SHRD13, SGPIO_b, FC0_c, TWI_SLC_GATE, SFP_SD, R); 1030 LAN966X_P(63, GPIO, QSPI1, FC_SHRD14, SGPIO_b, FC0_c, TWI_SLC_GATE, SFP_SD, R); 1031 LAN966X_P(64, GPIO, QSPI1, FC4_c, SGPIO_b, FC_SHRD15, TWI_SLC_GATE, SFP_SD, R); 1032 LAN966X_P(65, GPIO, USB_H_a, FC4_c, NONE, IRQ_OUT_c, TWI_SLC_GATE_AD, NONE, R); 1033 LAN966X_P(66, GPIO, USB_H_a, FC4_c, USB_S_a, IRQ_OUT_c, IRQ_IN_c, NONE, R); 1034 LAN966X_P(67, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R); 1035 LAN966X_P(68, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R); 1036 LAN966X_P(69, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R); 1037 LAN966X_P(70, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R); 1038 LAN966X_P(71, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R); 1039 LAN966X_P(72, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R); 1040 LAN966X_P(73, GPIO, EMMC, NONE, NONE, SD, NONE, NONE, R); 1041 LAN966X_P(74, GPIO, EMMC, NONE, FC_SHRD17, SD, TWI_SLC_GATE, NONE, R); 1042 LAN966X_P(75, GPIO, EMMC, NONE, FC_SHRD18, SD, TWI_SLC_GATE, NONE, R); 1043 LAN966X_P(76, GPIO, EMMC, NONE, FC_SHRD19, SD, TWI_SLC_GATE, NONE, R); 1044 LAN966X_P(77, GPIO, EMMC_SD, NONE, FC_SHRD20, NONE, TWI_SLC_GATE, NONE, R); 1045 1046 #define LAN966X_PIN(n) { \ 1047 .number = n, \ 1048 .name = "GPIO_"#n, \ 1049 .drv_data = &lan966x_pin_##n \ 1050 } 1051 1052 static const struct pinctrl_pin_desc lan966x_pins[] = { 1053 LAN966X_PIN(0), 1054 LAN966X_PIN(1), 1055 LAN966X_PIN(2), 1056 LAN966X_PIN(3), 1057 LAN966X_PIN(4), 1058 LAN966X_PIN(5), 1059 LAN966X_PIN(6), 1060 LAN966X_PIN(7), 1061 LAN966X_PIN(8), 1062 LAN966X_PIN(9), 1063 LAN966X_PIN(10), 1064 LAN966X_PIN(11), 1065 LAN966X_PIN(12), 1066 LAN966X_PIN(13), 1067 LAN966X_PIN(14), 1068 LAN966X_PIN(15), 1069 LAN966X_PIN(16), 1070 LAN966X_PIN(17), 1071 LAN966X_PIN(18), 1072 LAN966X_PIN(19), 1073 LAN966X_PIN(20), 1074 LAN966X_PIN(21), 1075 LAN966X_PIN(22), 1076 LAN966X_PIN(23), 1077 LAN966X_PIN(24), 1078 LAN966X_PIN(25), 1079 LAN966X_PIN(26), 1080 LAN966X_PIN(27), 1081 LAN966X_PIN(28), 1082 LAN966X_PIN(29), 1083 LAN966X_PIN(30), 1084 LAN966X_PIN(31), 1085 LAN966X_PIN(32), 1086 LAN966X_PIN(33), 1087 LAN966X_PIN(34), 1088 LAN966X_PIN(35), 1089 LAN966X_PIN(36), 1090 LAN966X_PIN(37), 1091 LAN966X_PIN(38), 1092 LAN966X_PIN(39), 1093 LAN966X_PIN(40), 1094 LAN966X_PIN(41), 1095 LAN966X_PIN(42), 1096 LAN966X_PIN(43), 1097 LAN966X_PIN(44), 1098 LAN966X_PIN(45), 1099 LAN966X_PIN(46), 1100 LAN966X_PIN(47), 1101 LAN966X_PIN(48), 1102 LAN966X_PIN(49), 1103 LAN966X_PIN(50), 1104 LAN966X_PIN(51), 1105 LAN966X_PIN(52), 1106 LAN966X_PIN(53), 1107 LAN966X_PIN(54), 1108 LAN966X_PIN(55), 1109 LAN966X_PIN(56), 1110 LAN966X_PIN(57), 1111 LAN966X_PIN(58), 1112 LAN966X_PIN(59), 1113 LAN966X_PIN(60), 1114 LAN966X_PIN(61), 1115 LAN966X_PIN(62), 1116 LAN966X_PIN(63), 1117 LAN966X_PIN(64), 1118 LAN966X_PIN(65), 1119 LAN966X_PIN(66), 1120 LAN966X_PIN(67), 1121 LAN966X_PIN(68), 1122 LAN966X_PIN(69), 1123 LAN966X_PIN(70), 1124 LAN966X_PIN(71), 1125 LAN966X_PIN(72), 1126 LAN966X_PIN(73), 1127 LAN966X_PIN(74), 1128 LAN966X_PIN(75), 1129 LAN966X_PIN(76), 1130 LAN966X_PIN(77), 1131 }; 1132 1133 static int ocelot_get_functions_count(struct pinctrl_dev *pctldev) 1134 { 1135 return ARRAY_SIZE(ocelot_function_names); 1136 } 1137 1138 static const char *ocelot_get_function_name(struct pinctrl_dev *pctldev, 1139 unsigned int function) 1140 { 1141 return ocelot_function_names[function]; 1142 } 1143 1144 static int ocelot_get_function_groups(struct pinctrl_dev *pctldev, 1145 unsigned int function, 1146 const char *const **groups, 1147 unsigned *const num_groups) 1148 { 1149 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1150 1151 *groups = info->func[function].groups; 1152 *num_groups = info->func[function].ngroups; 1153 1154 return 0; 1155 } 1156 1157 static int ocelot_pin_function_idx(struct ocelot_pinctrl *info, 1158 unsigned int pin, unsigned int function) 1159 { 1160 struct ocelot_pin_caps *p = info->desc->pins[pin].drv_data; 1161 int i; 1162 1163 for (i = 0; i < OCELOT_FUNC_PER_PIN; i++) { 1164 if (function == p->functions[i]) 1165 return i; 1166 1167 if (function == p->a_functions[i]) 1168 return i + OCELOT_FUNC_PER_PIN; 1169 } 1170 1171 return -1; 1172 } 1173 1174 #define REG_ALT(msb, info, p) (OCELOT_GPIO_ALT0 * (info)->stride + 4 * ((msb) + ((info)->stride * ((p) / 32)))) 1175 1176 static int ocelot_pinmux_set_mux(struct pinctrl_dev *pctldev, 1177 unsigned int selector, unsigned int group) 1178 { 1179 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1180 struct ocelot_pin_caps *pin = info->desc->pins[group].drv_data; 1181 unsigned int p = pin->pin % 32; 1182 int f; 1183 1184 f = ocelot_pin_function_idx(info, group, selector); 1185 if (f < 0) 1186 return -EINVAL; 1187 1188 /* 1189 * f is encoded on two bits. 1190 * bit 0 of f goes in BIT(pin) of ALT[0], bit 1 of f goes in BIT(pin) of 1191 * ALT[1] 1192 * This is racy because both registers can't be updated at the same time 1193 * but it doesn't matter much for now. 1194 * Note: ALT0/ALT1 are organized specially for 64 gpio targets 1195 */ 1196 regmap_update_bits(info->map, REG_ALT(0, info, pin->pin), 1197 BIT(p), f << p); 1198 regmap_update_bits(info->map, REG_ALT(1, info, pin->pin), 1199 BIT(p), f << (p - 1)); 1200 1201 return 0; 1202 } 1203 1204 static int lan966x_pinmux_set_mux(struct pinctrl_dev *pctldev, 1205 unsigned int selector, unsigned int group) 1206 { 1207 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1208 struct ocelot_pin_caps *pin = info->desc->pins[group].drv_data; 1209 unsigned int p = pin->pin % 32; 1210 int f; 1211 1212 f = ocelot_pin_function_idx(info, group, selector); 1213 if (f < 0) 1214 return -EINVAL; 1215 1216 /* 1217 * f is encoded on three bits. 1218 * bit 0 of f goes in BIT(pin) of ALT[0], bit 1 of f goes in BIT(pin) of 1219 * ALT[1], bit 2 of f goes in BIT(pin) of ALT[2] 1220 * This is racy because three registers can't be updated at the same time 1221 * but it doesn't matter much for now. 1222 * Note: ALT0/ALT1/ALT2 are organized specially for 78 gpio targets 1223 */ 1224 regmap_update_bits(info->map, REG_ALT(0, info, pin->pin), 1225 BIT(p), f << p); 1226 regmap_update_bits(info->map, REG_ALT(1, info, pin->pin), 1227 BIT(p), (f >> 1) << p); 1228 regmap_update_bits(info->map, REG_ALT(2, info, pin->pin), 1229 BIT(p), (f >> 2) << p); 1230 1231 return 0; 1232 } 1233 1234 #define REG(r, info, p) ((r) * (info)->stride + (4 * ((p) / 32))) 1235 1236 static int ocelot_gpio_set_direction(struct pinctrl_dev *pctldev, 1237 struct pinctrl_gpio_range *range, 1238 unsigned int pin, bool input) 1239 { 1240 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1241 unsigned int p = pin % 32; 1242 1243 regmap_update_bits(info->map, REG(OCELOT_GPIO_OE, info, pin), BIT(p), 1244 input ? 0 : BIT(p)); 1245 1246 return 0; 1247 } 1248 1249 static int ocelot_gpio_request_enable(struct pinctrl_dev *pctldev, 1250 struct pinctrl_gpio_range *range, 1251 unsigned int offset) 1252 { 1253 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1254 unsigned int p = offset % 32; 1255 1256 regmap_update_bits(info->map, REG_ALT(0, info, offset), 1257 BIT(p), 0); 1258 regmap_update_bits(info->map, REG_ALT(1, info, offset), 1259 BIT(p), 0); 1260 1261 return 0; 1262 } 1263 1264 static int lan966x_gpio_request_enable(struct pinctrl_dev *pctldev, 1265 struct pinctrl_gpio_range *range, 1266 unsigned int offset) 1267 { 1268 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1269 unsigned int p = offset % 32; 1270 1271 regmap_update_bits(info->map, REG_ALT(0, info, offset), 1272 BIT(p), 0); 1273 regmap_update_bits(info->map, REG_ALT(1, info, offset), 1274 BIT(p), 0); 1275 regmap_update_bits(info->map, REG_ALT(2, info, offset), 1276 BIT(p), 0); 1277 1278 return 0; 1279 } 1280 1281 static const struct pinmux_ops ocelot_pmx_ops = { 1282 .get_functions_count = ocelot_get_functions_count, 1283 .get_function_name = ocelot_get_function_name, 1284 .get_function_groups = ocelot_get_function_groups, 1285 .set_mux = ocelot_pinmux_set_mux, 1286 .gpio_set_direction = ocelot_gpio_set_direction, 1287 .gpio_request_enable = ocelot_gpio_request_enable, 1288 }; 1289 1290 static const struct pinmux_ops lan966x_pmx_ops = { 1291 .get_functions_count = ocelot_get_functions_count, 1292 .get_function_name = ocelot_get_function_name, 1293 .get_function_groups = ocelot_get_function_groups, 1294 .set_mux = lan966x_pinmux_set_mux, 1295 .gpio_set_direction = ocelot_gpio_set_direction, 1296 .gpio_request_enable = lan966x_gpio_request_enable, 1297 }; 1298 1299 static int ocelot_pctl_get_groups_count(struct pinctrl_dev *pctldev) 1300 { 1301 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1302 1303 return info->desc->npins; 1304 } 1305 1306 static const char *ocelot_pctl_get_group_name(struct pinctrl_dev *pctldev, 1307 unsigned int group) 1308 { 1309 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1310 1311 return info->desc->pins[group].name; 1312 } 1313 1314 static int ocelot_pctl_get_group_pins(struct pinctrl_dev *pctldev, 1315 unsigned int group, 1316 const unsigned int **pins, 1317 unsigned int *num_pins) 1318 { 1319 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1320 1321 *pins = &info->desc->pins[group].number; 1322 *num_pins = 1; 1323 1324 return 0; 1325 } 1326 1327 static int ocelot_hw_get_value(struct ocelot_pinctrl *info, 1328 unsigned int pin, 1329 unsigned int reg, 1330 int *val) 1331 { 1332 int ret = -EOPNOTSUPP; 1333 1334 if (info->pincfg) { 1335 const struct ocelot_pincfg_data *opd = info->pincfg_data; 1336 u32 regcfg; 1337 1338 ret = regmap_read(info->pincfg, 1339 pin * regmap_get_reg_stride(info->pincfg), 1340 ®cfg); 1341 if (ret) 1342 return ret; 1343 1344 ret = 0; 1345 switch (reg) { 1346 case PINCONF_BIAS: 1347 *val = regcfg & (opd->pd_bit | opd->pu_bit); 1348 break; 1349 1350 case PINCONF_SCHMITT: 1351 *val = regcfg & opd->schmitt_bit; 1352 break; 1353 1354 case PINCONF_DRIVE_STRENGTH: 1355 *val = regcfg & opd->drive_bits; 1356 break; 1357 1358 default: 1359 ret = -EOPNOTSUPP; 1360 break; 1361 } 1362 } 1363 return ret; 1364 } 1365 1366 static int ocelot_pincfg_clrsetbits(struct ocelot_pinctrl *info, u32 regaddr, 1367 u32 clrbits, u32 setbits) 1368 { 1369 u32 val; 1370 int ret; 1371 1372 ret = regmap_read(info->pincfg, 1373 regaddr * regmap_get_reg_stride(info->pincfg), 1374 &val); 1375 if (ret) 1376 return ret; 1377 1378 val &= ~clrbits; 1379 val |= setbits; 1380 1381 ret = regmap_write(info->pincfg, 1382 regaddr * regmap_get_reg_stride(info->pincfg), 1383 val); 1384 1385 return ret; 1386 } 1387 1388 static int ocelot_hw_set_value(struct ocelot_pinctrl *info, 1389 unsigned int pin, 1390 unsigned int reg, 1391 int val) 1392 { 1393 int ret = -EOPNOTSUPP; 1394 1395 if (info->pincfg) { 1396 const struct ocelot_pincfg_data *opd = info->pincfg_data; 1397 1398 ret = 0; 1399 switch (reg) { 1400 case PINCONF_BIAS: 1401 ret = ocelot_pincfg_clrsetbits(info, pin, 1402 opd->pd_bit | opd->pu_bit, 1403 val); 1404 break; 1405 1406 case PINCONF_SCHMITT: 1407 ret = ocelot_pincfg_clrsetbits(info, pin, 1408 opd->schmitt_bit, 1409 val); 1410 break; 1411 1412 case PINCONF_DRIVE_STRENGTH: 1413 if (val <= 3) 1414 ret = ocelot_pincfg_clrsetbits(info, pin, 1415 opd->drive_bits, 1416 val); 1417 else 1418 ret = -EINVAL; 1419 break; 1420 1421 default: 1422 ret = -EOPNOTSUPP; 1423 break; 1424 } 1425 } 1426 return ret; 1427 } 1428 1429 static int ocelot_pinconf_get(struct pinctrl_dev *pctldev, 1430 unsigned int pin, unsigned long *config) 1431 { 1432 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1433 u32 param = pinconf_to_config_param(*config); 1434 int val, err; 1435 1436 switch (param) { 1437 case PIN_CONFIG_BIAS_DISABLE: 1438 case PIN_CONFIG_BIAS_PULL_UP: 1439 case PIN_CONFIG_BIAS_PULL_DOWN: 1440 err = ocelot_hw_get_value(info, pin, PINCONF_BIAS, &val); 1441 if (err) 1442 return err; 1443 if (param == PIN_CONFIG_BIAS_DISABLE) 1444 val = (val == 0); 1445 else if (param == PIN_CONFIG_BIAS_PULL_DOWN) 1446 val = !!(val & info->pincfg_data->pd_bit); 1447 else /* PIN_CONFIG_BIAS_PULL_UP */ 1448 val = !!(val & info->pincfg_data->pu_bit); 1449 break; 1450 1451 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 1452 if (!info->pincfg_data->schmitt_bit) 1453 return -EOPNOTSUPP; 1454 1455 err = ocelot_hw_get_value(info, pin, PINCONF_SCHMITT, &val); 1456 if (err) 1457 return err; 1458 1459 val = !!(val & info->pincfg_data->schmitt_bit); 1460 break; 1461 1462 case PIN_CONFIG_DRIVE_STRENGTH: 1463 err = ocelot_hw_get_value(info, pin, PINCONF_DRIVE_STRENGTH, 1464 &val); 1465 if (err) 1466 return err; 1467 break; 1468 1469 case PIN_CONFIG_OUTPUT: 1470 err = regmap_read(info->map, REG(OCELOT_GPIO_OUT, info, pin), 1471 &val); 1472 if (err) 1473 return err; 1474 val = !!(val & BIT(pin % 32)); 1475 break; 1476 1477 case PIN_CONFIG_INPUT_ENABLE: 1478 case PIN_CONFIG_OUTPUT_ENABLE: 1479 err = regmap_read(info->map, REG(OCELOT_GPIO_OE, info, pin), 1480 &val); 1481 if (err) 1482 return err; 1483 val = val & BIT(pin % 32); 1484 if (param == PIN_CONFIG_OUTPUT_ENABLE) 1485 val = !!val; 1486 else 1487 val = !val; 1488 break; 1489 1490 default: 1491 return -EOPNOTSUPP; 1492 } 1493 1494 *config = pinconf_to_config_packed(param, val); 1495 1496 return 0; 1497 } 1498 1499 static int ocelot_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 1500 unsigned long *configs, unsigned int num_configs) 1501 { 1502 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1503 const struct ocelot_pincfg_data *opd = info->pincfg_data; 1504 u32 param, arg, p; 1505 int cfg, err = 0; 1506 1507 for (cfg = 0; cfg < num_configs; cfg++) { 1508 param = pinconf_to_config_param(configs[cfg]); 1509 arg = pinconf_to_config_argument(configs[cfg]); 1510 1511 switch (param) { 1512 case PIN_CONFIG_BIAS_DISABLE: 1513 case PIN_CONFIG_BIAS_PULL_UP: 1514 case PIN_CONFIG_BIAS_PULL_DOWN: 1515 arg = (param == PIN_CONFIG_BIAS_DISABLE) ? 0 : 1516 (param == PIN_CONFIG_BIAS_PULL_UP) ? 1517 opd->pu_bit : opd->pd_bit; 1518 1519 err = ocelot_hw_set_value(info, pin, PINCONF_BIAS, arg); 1520 if (err) 1521 goto err; 1522 1523 break; 1524 1525 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 1526 if (!opd->schmitt_bit) 1527 return -EOPNOTSUPP; 1528 1529 arg = arg ? opd->schmitt_bit : 0; 1530 err = ocelot_hw_set_value(info, pin, PINCONF_SCHMITT, 1531 arg); 1532 if (err) 1533 goto err; 1534 1535 break; 1536 1537 case PIN_CONFIG_DRIVE_STRENGTH: 1538 err = ocelot_hw_set_value(info, pin, 1539 PINCONF_DRIVE_STRENGTH, 1540 arg); 1541 if (err) 1542 goto err; 1543 1544 break; 1545 1546 case PIN_CONFIG_OUTPUT_ENABLE: 1547 case PIN_CONFIG_INPUT_ENABLE: 1548 case PIN_CONFIG_OUTPUT: 1549 p = pin % 32; 1550 if (arg) 1551 regmap_write(info->map, 1552 REG(OCELOT_GPIO_OUT_SET, info, 1553 pin), 1554 BIT(p)); 1555 else 1556 regmap_write(info->map, 1557 REG(OCELOT_GPIO_OUT_CLR, info, 1558 pin), 1559 BIT(p)); 1560 regmap_update_bits(info->map, 1561 REG(OCELOT_GPIO_OE, info, pin), 1562 BIT(p), 1563 param == PIN_CONFIG_INPUT_ENABLE ? 1564 0 : BIT(p)); 1565 break; 1566 1567 default: 1568 err = -EOPNOTSUPP; 1569 } 1570 } 1571 err: 1572 return err; 1573 } 1574 1575 static const struct pinconf_ops ocelot_confops = { 1576 .is_generic = true, 1577 .pin_config_get = ocelot_pinconf_get, 1578 .pin_config_set = ocelot_pinconf_set, 1579 .pin_config_config_dbg_show = pinconf_generic_dump_config, 1580 }; 1581 1582 static const struct pinctrl_ops ocelot_pctl_ops = { 1583 .get_groups_count = ocelot_pctl_get_groups_count, 1584 .get_group_name = ocelot_pctl_get_group_name, 1585 .get_group_pins = ocelot_pctl_get_group_pins, 1586 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, 1587 .dt_free_map = pinconf_generic_dt_free_map, 1588 }; 1589 1590 static struct ocelot_match_data luton_desc = { 1591 .desc = { 1592 .name = "luton-pinctrl", 1593 .pins = luton_pins, 1594 .npins = ARRAY_SIZE(luton_pins), 1595 .pctlops = &ocelot_pctl_ops, 1596 .pmxops = &ocelot_pmx_ops, 1597 .owner = THIS_MODULE, 1598 }, 1599 }; 1600 1601 static struct ocelot_match_data serval_desc = { 1602 .desc = { 1603 .name = "serval-pinctrl", 1604 .pins = serval_pins, 1605 .npins = ARRAY_SIZE(serval_pins), 1606 .pctlops = &ocelot_pctl_ops, 1607 .pmxops = &ocelot_pmx_ops, 1608 .owner = THIS_MODULE, 1609 }, 1610 }; 1611 1612 static struct ocelot_match_data ocelot_desc = { 1613 .desc = { 1614 .name = "ocelot-pinctrl", 1615 .pins = ocelot_pins, 1616 .npins = ARRAY_SIZE(ocelot_pins), 1617 .pctlops = &ocelot_pctl_ops, 1618 .pmxops = &ocelot_pmx_ops, 1619 .owner = THIS_MODULE, 1620 }, 1621 }; 1622 1623 static struct ocelot_match_data jaguar2_desc = { 1624 .desc = { 1625 .name = "jaguar2-pinctrl", 1626 .pins = jaguar2_pins, 1627 .npins = ARRAY_SIZE(jaguar2_pins), 1628 .pctlops = &ocelot_pctl_ops, 1629 .pmxops = &ocelot_pmx_ops, 1630 .owner = THIS_MODULE, 1631 }, 1632 }; 1633 1634 static struct ocelot_match_data servalt_desc = { 1635 .desc = { 1636 .name = "servalt-pinctrl", 1637 .pins = servalt_pins, 1638 .npins = ARRAY_SIZE(servalt_pins), 1639 .pctlops = &ocelot_pctl_ops, 1640 .pmxops = &ocelot_pmx_ops, 1641 .owner = THIS_MODULE, 1642 }, 1643 }; 1644 1645 static struct ocelot_match_data sparx5_desc = { 1646 .desc = { 1647 .name = "sparx5-pinctrl", 1648 .pins = sparx5_pins, 1649 .npins = ARRAY_SIZE(sparx5_pins), 1650 .pctlops = &ocelot_pctl_ops, 1651 .pmxops = &ocelot_pmx_ops, 1652 .confops = &ocelot_confops, 1653 .owner = THIS_MODULE, 1654 }, 1655 .pincfg_data = { 1656 .pd_bit = BIT(4), 1657 .pu_bit = BIT(3), 1658 .drive_bits = GENMASK(1, 0), 1659 .schmitt_bit = BIT(2), 1660 }, 1661 }; 1662 1663 static struct ocelot_match_data lan966x_desc = { 1664 .desc = { 1665 .name = "lan966x-pinctrl", 1666 .pins = lan966x_pins, 1667 .npins = ARRAY_SIZE(lan966x_pins), 1668 .pctlops = &ocelot_pctl_ops, 1669 .pmxops = &lan966x_pmx_ops, 1670 .confops = &ocelot_confops, 1671 .owner = THIS_MODULE, 1672 }, 1673 .pincfg_data = { 1674 .pd_bit = BIT(3), 1675 .pu_bit = BIT(2), 1676 .drive_bits = GENMASK(1, 0), 1677 }, 1678 }; 1679 1680 static int ocelot_create_group_func_map(struct device *dev, 1681 struct ocelot_pinctrl *info) 1682 { 1683 int f, npins, i; 1684 u8 *pins = kcalloc(info->desc->npins, sizeof(u8), GFP_KERNEL); 1685 1686 if (!pins) 1687 return -ENOMEM; 1688 1689 for (f = 0; f < FUNC_MAX; f++) { 1690 for (npins = 0, i = 0; i < info->desc->npins; i++) { 1691 if (ocelot_pin_function_idx(info, i, f) >= 0) 1692 pins[npins++] = i; 1693 } 1694 1695 if (!npins) 1696 continue; 1697 1698 info->func[f].ngroups = npins; 1699 info->func[f].groups = devm_kcalloc(dev, npins, sizeof(char *), 1700 GFP_KERNEL); 1701 if (!info->func[f].groups) { 1702 kfree(pins); 1703 return -ENOMEM; 1704 } 1705 1706 for (i = 0; i < npins; i++) 1707 info->func[f].groups[i] = 1708 info->desc->pins[pins[i]].name; 1709 } 1710 1711 kfree(pins); 1712 1713 return 0; 1714 } 1715 1716 static int ocelot_pinctrl_register(struct platform_device *pdev, 1717 struct ocelot_pinctrl *info) 1718 { 1719 int ret; 1720 1721 ret = ocelot_create_group_func_map(&pdev->dev, info); 1722 if (ret) { 1723 dev_err(&pdev->dev, "Unable to create group func map.\n"); 1724 return ret; 1725 } 1726 1727 info->pctl = devm_pinctrl_register(&pdev->dev, info->desc, info); 1728 if (IS_ERR(info->pctl)) { 1729 dev_err(&pdev->dev, "Failed to register pinctrl\n"); 1730 return PTR_ERR(info->pctl); 1731 } 1732 1733 return 0; 1734 } 1735 1736 static int ocelot_gpio_get(struct gpio_chip *chip, unsigned int offset) 1737 { 1738 struct ocelot_pinctrl *info = gpiochip_get_data(chip); 1739 unsigned int val; 1740 1741 regmap_read(info->map, REG(OCELOT_GPIO_IN, info, offset), &val); 1742 1743 return !!(val & BIT(offset % 32)); 1744 } 1745 1746 static void ocelot_gpio_set(struct gpio_chip *chip, unsigned int offset, 1747 int value) 1748 { 1749 struct ocelot_pinctrl *info = gpiochip_get_data(chip); 1750 1751 if (value) 1752 regmap_write(info->map, REG(OCELOT_GPIO_OUT_SET, info, offset), 1753 BIT(offset % 32)); 1754 else 1755 regmap_write(info->map, REG(OCELOT_GPIO_OUT_CLR, info, offset), 1756 BIT(offset % 32)); 1757 } 1758 1759 static int ocelot_gpio_get_direction(struct gpio_chip *chip, 1760 unsigned int offset) 1761 { 1762 struct ocelot_pinctrl *info = gpiochip_get_data(chip); 1763 unsigned int val; 1764 1765 regmap_read(info->map, REG(OCELOT_GPIO_OE, info, offset), &val); 1766 1767 if (val & BIT(offset % 32)) 1768 return GPIO_LINE_DIRECTION_OUT; 1769 1770 return GPIO_LINE_DIRECTION_IN; 1771 } 1772 1773 static int ocelot_gpio_direction_input(struct gpio_chip *chip, 1774 unsigned int offset) 1775 { 1776 return pinctrl_gpio_direction_input(chip->base + offset); 1777 } 1778 1779 static int ocelot_gpio_direction_output(struct gpio_chip *chip, 1780 unsigned int offset, int value) 1781 { 1782 struct ocelot_pinctrl *info = gpiochip_get_data(chip); 1783 unsigned int pin = BIT(offset % 32); 1784 1785 if (value) 1786 regmap_write(info->map, REG(OCELOT_GPIO_OUT_SET, info, offset), 1787 pin); 1788 else 1789 regmap_write(info->map, REG(OCELOT_GPIO_OUT_CLR, info, offset), 1790 pin); 1791 1792 return pinctrl_gpio_direction_output(chip->base + offset); 1793 } 1794 1795 static const struct gpio_chip ocelot_gpiolib_chip = { 1796 .request = gpiochip_generic_request, 1797 .free = gpiochip_generic_free, 1798 .set = ocelot_gpio_set, 1799 .get = ocelot_gpio_get, 1800 .get_direction = ocelot_gpio_get_direction, 1801 .direction_input = ocelot_gpio_direction_input, 1802 .direction_output = ocelot_gpio_direction_output, 1803 .owner = THIS_MODULE, 1804 }; 1805 1806 static void ocelot_irq_mask(struct irq_data *data) 1807 { 1808 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 1809 struct ocelot_pinctrl *info = gpiochip_get_data(chip); 1810 unsigned int gpio = irqd_to_hwirq(data); 1811 1812 regmap_update_bits(info->map, REG(OCELOT_GPIO_INTR_ENA, info, gpio), 1813 BIT(gpio % 32), 0); 1814 gpiochip_disable_irq(chip, gpio); 1815 } 1816 1817 static void ocelot_irq_unmask(struct irq_data *data) 1818 { 1819 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 1820 struct ocelot_pinctrl *info = gpiochip_get_data(chip); 1821 unsigned int gpio = irqd_to_hwirq(data); 1822 1823 gpiochip_enable_irq(chip, gpio); 1824 regmap_update_bits(info->map, REG(OCELOT_GPIO_INTR_ENA, info, gpio), 1825 BIT(gpio % 32), BIT(gpio % 32)); 1826 } 1827 1828 static void ocelot_irq_ack(struct irq_data *data) 1829 { 1830 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 1831 struct ocelot_pinctrl *info = gpiochip_get_data(chip); 1832 unsigned int gpio = irqd_to_hwirq(data); 1833 1834 regmap_write_bits(info->map, REG(OCELOT_GPIO_INTR, info, gpio), 1835 BIT(gpio % 32), BIT(gpio % 32)); 1836 } 1837 1838 static int ocelot_irq_set_type(struct irq_data *data, unsigned int type); 1839 1840 static struct irq_chip ocelot_eoi_irqchip = { 1841 .name = "gpio", 1842 .irq_mask = ocelot_irq_mask, 1843 .irq_eoi = ocelot_irq_ack, 1844 .irq_unmask = ocelot_irq_unmask, 1845 .flags = IRQCHIP_EOI_THREADED | IRQCHIP_EOI_IF_HANDLED | 1846 IRQCHIP_IMMUTABLE, 1847 .irq_set_type = ocelot_irq_set_type, 1848 GPIOCHIP_IRQ_RESOURCE_HELPERS 1849 }; 1850 1851 static struct irq_chip ocelot_irqchip = { 1852 .name = "gpio", 1853 .irq_mask = ocelot_irq_mask, 1854 .irq_ack = ocelot_irq_ack, 1855 .irq_unmask = ocelot_irq_unmask, 1856 .irq_set_type = ocelot_irq_set_type, 1857 .flags = IRQCHIP_IMMUTABLE, 1858 GPIOCHIP_IRQ_RESOURCE_HELPERS 1859 }; 1860 1861 static int ocelot_irq_set_type(struct irq_data *data, unsigned int type) 1862 { 1863 type &= IRQ_TYPE_SENSE_MASK; 1864 1865 if (!(type & (IRQ_TYPE_EDGE_BOTH | IRQ_TYPE_LEVEL_HIGH))) 1866 return -EINVAL; 1867 1868 if (type & IRQ_TYPE_LEVEL_HIGH) 1869 irq_set_chip_handler_name_locked(data, &ocelot_eoi_irqchip, 1870 handle_fasteoi_irq, NULL); 1871 if (type & IRQ_TYPE_EDGE_BOTH) 1872 irq_set_chip_handler_name_locked(data, &ocelot_irqchip, 1873 handle_edge_irq, NULL); 1874 1875 return 0; 1876 } 1877 1878 static void ocelot_irq_handler(struct irq_desc *desc) 1879 { 1880 struct irq_chip *parent_chip = irq_desc_get_chip(desc); 1881 struct gpio_chip *chip = irq_desc_get_handler_data(desc); 1882 struct ocelot_pinctrl *info = gpiochip_get_data(chip); 1883 unsigned int id_reg = OCELOT_GPIO_INTR_IDENT * info->stride; 1884 unsigned int reg = 0, irq, i; 1885 unsigned long irqs; 1886 1887 for (i = 0; i < info->stride; i++) { 1888 regmap_read(info->map, id_reg + 4 * i, ®); 1889 if (!reg) 1890 continue; 1891 1892 chained_irq_enter(parent_chip, desc); 1893 1894 irqs = reg; 1895 1896 for_each_set_bit(irq, &irqs, 1897 min(32U, info->desc->npins - 32 * i)) 1898 generic_handle_domain_irq(chip->irq.domain, irq + 32 * i); 1899 1900 chained_irq_exit(parent_chip, desc); 1901 } 1902 } 1903 1904 static int ocelot_gpiochip_register(struct platform_device *pdev, 1905 struct ocelot_pinctrl *info) 1906 { 1907 struct gpio_chip *gc; 1908 struct gpio_irq_chip *girq; 1909 int irq; 1910 1911 info->gpio_chip = ocelot_gpiolib_chip; 1912 1913 gc = &info->gpio_chip; 1914 gc->ngpio = info->desc->npins; 1915 gc->parent = &pdev->dev; 1916 gc->base = -1; 1917 gc->label = "ocelot-gpio"; 1918 1919 irq = platform_get_irq_optional(pdev, 0); 1920 if (irq > 0) { 1921 girq = &gc->irq; 1922 gpio_irq_chip_set_chip(girq, &ocelot_irqchip); 1923 girq->parent_handler = ocelot_irq_handler; 1924 girq->num_parents = 1; 1925 girq->parents = devm_kcalloc(&pdev->dev, 1, 1926 sizeof(*girq->parents), 1927 GFP_KERNEL); 1928 if (!girq->parents) 1929 return -ENOMEM; 1930 girq->parents[0] = irq; 1931 girq->default_type = IRQ_TYPE_NONE; 1932 girq->handler = handle_edge_irq; 1933 } 1934 1935 return devm_gpiochip_add_data(&pdev->dev, gc, info); 1936 } 1937 1938 static const struct of_device_id ocelot_pinctrl_of_match[] = { 1939 { .compatible = "mscc,luton-pinctrl", .data = &luton_desc }, 1940 { .compatible = "mscc,serval-pinctrl", .data = &serval_desc }, 1941 { .compatible = "mscc,ocelot-pinctrl", .data = &ocelot_desc }, 1942 { .compatible = "mscc,jaguar2-pinctrl", .data = &jaguar2_desc }, 1943 { .compatible = "mscc,servalt-pinctrl", .data = &servalt_desc }, 1944 { .compatible = "microchip,sparx5-pinctrl", .data = &sparx5_desc }, 1945 { .compatible = "microchip,lan966x-pinctrl", .data = &lan966x_desc }, 1946 {}, 1947 }; 1948 MODULE_DEVICE_TABLE(of, ocelot_pinctrl_of_match); 1949 1950 static struct regmap *ocelot_pinctrl_create_pincfg(struct platform_device *pdev, 1951 const struct ocelot_pinctrl *info) 1952 { 1953 void __iomem *base; 1954 1955 const struct regmap_config regmap_config = { 1956 .reg_bits = 32, 1957 .val_bits = 32, 1958 .reg_stride = 4, 1959 .max_register = info->desc->npins * 4, 1960 .name = "pincfg", 1961 }; 1962 1963 base = devm_platform_ioremap_resource(pdev, 1); 1964 if (IS_ERR(base)) { 1965 dev_dbg(&pdev->dev, "Failed to ioremap config registers (no extended pinconf)\n"); 1966 return NULL; 1967 } 1968 1969 return devm_regmap_init_mmio(&pdev->dev, base, ®map_config); 1970 } 1971 1972 static int ocelot_pinctrl_probe(struct platform_device *pdev) 1973 { 1974 const struct ocelot_match_data *data; 1975 struct device *dev = &pdev->dev; 1976 struct ocelot_pinctrl *info; 1977 struct reset_control *reset; 1978 struct regmap *pincfg; 1979 int ret; 1980 struct regmap_config regmap_config = { 1981 .reg_bits = 32, 1982 .val_bits = 32, 1983 .reg_stride = 4, 1984 }; 1985 1986 info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL); 1987 if (!info) 1988 return -ENOMEM; 1989 1990 data = device_get_match_data(dev); 1991 if (!data) 1992 return -EINVAL; 1993 1994 info->desc = devm_kmemdup(dev, &data->desc, sizeof(*info->desc), 1995 GFP_KERNEL); 1996 if (!info->desc) 1997 return -ENOMEM; 1998 1999 info->pincfg_data = &data->pincfg_data; 2000 2001 reset = devm_reset_control_get_optional_shared(dev, "switch"); 2002 if (IS_ERR(reset)) 2003 return dev_err_probe(dev, PTR_ERR(reset), 2004 "Failed to get reset\n"); 2005 reset_control_reset(reset); 2006 2007 info->stride = 1 + (info->desc->npins - 1) / 32; 2008 2009 regmap_config.max_register = OCELOT_GPIO_SD_MAP * info->stride + 15 * 4; 2010 2011 info->map = ocelot_regmap_from_resource(pdev, 0, ®map_config); 2012 if (IS_ERR(info->map)) 2013 return dev_err_probe(dev, PTR_ERR(info->map), 2014 "Failed to create regmap\n"); 2015 dev_set_drvdata(dev, info->map); 2016 info->dev = dev; 2017 2018 /* Pinconf registers */ 2019 if (info->desc->confops) { 2020 pincfg = ocelot_pinctrl_create_pincfg(pdev, info); 2021 if (IS_ERR(pincfg)) 2022 dev_dbg(dev, "Failed to create pincfg regmap\n"); 2023 else 2024 info->pincfg = pincfg; 2025 } 2026 2027 ret = ocelot_pinctrl_register(pdev, info); 2028 if (ret) 2029 return ret; 2030 2031 ret = ocelot_gpiochip_register(pdev, info); 2032 if (ret) 2033 return ret; 2034 2035 dev_info(dev, "driver registered\n"); 2036 2037 return 0; 2038 } 2039 2040 static struct platform_driver ocelot_pinctrl_driver = { 2041 .driver = { 2042 .name = "pinctrl-ocelot", 2043 .of_match_table = of_match_ptr(ocelot_pinctrl_of_match), 2044 .suppress_bind_attrs = true, 2045 }, 2046 .probe = ocelot_pinctrl_probe, 2047 }; 2048 module_platform_driver(ocelot_pinctrl_driver); 2049 MODULE_LICENSE("Dual MIT/GPL"); 2050