1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* 3 * Microsemi SoCs pinctrl driver 4 * 5 * Author: <alexandre.belloni@free-electrons.com> 6 * License: Dual MIT/GPL 7 * Copyright (c) 2017 Microsemi Corporation 8 */ 9 10 #include <linux/gpio/driver.h> 11 #include <linux/interrupt.h> 12 #include <linux/io.h> 13 #include <linux/of_device.h> 14 #include <linux/of_irq.h> 15 #include <linux/of_platform.h> 16 #include <linux/pinctrl/pinctrl.h> 17 #include <linux/pinctrl/pinmux.h> 18 #include <linux/pinctrl/pinconf.h> 19 #include <linux/pinctrl/pinconf-generic.h> 20 #include <linux/platform_device.h> 21 #include <linux/regmap.h> 22 #include <linux/slab.h> 23 24 #include "core.h" 25 #include "pinconf.h" 26 #include "pinmux.h" 27 28 #define ocelot_clrsetbits(addr, clear, set) \ 29 writel((readl(addr) & ~(clear)) | (set), (addr)) 30 31 /* PINCONFIG bits (sparx5 only) */ 32 enum { 33 PINCONF_BIAS, 34 PINCONF_SCHMITT, 35 PINCONF_DRIVE_STRENGTH, 36 }; 37 38 #define BIAS_PD_BIT BIT(4) 39 #define BIAS_PU_BIT BIT(3) 40 #define BIAS_BITS (BIAS_PD_BIT|BIAS_PU_BIT) 41 #define SCHMITT_BIT BIT(2) 42 #define DRIVE_BITS GENMASK(1, 0) 43 44 /* GPIO standard registers */ 45 #define OCELOT_GPIO_OUT_SET 0x0 46 #define OCELOT_GPIO_OUT_CLR 0x4 47 #define OCELOT_GPIO_OUT 0x8 48 #define OCELOT_GPIO_IN 0xc 49 #define OCELOT_GPIO_OE 0x10 50 #define OCELOT_GPIO_INTR 0x14 51 #define OCELOT_GPIO_INTR_ENA 0x18 52 #define OCELOT_GPIO_INTR_IDENT 0x1c 53 #define OCELOT_GPIO_ALT0 0x20 54 #define OCELOT_GPIO_ALT1 0x24 55 #define OCELOT_GPIO_SD_MAP 0x28 56 57 #define OCELOT_FUNC_PER_PIN 4 58 59 enum { 60 FUNC_CAN0_a, 61 FUNC_CAN0_b, 62 FUNC_CAN1, 63 FUNC_NONE, 64 FUNC_FC0_a, 65 FUNC_FC0_b, 66 FUNC_FC0_c, 67 FUNC_FC1_a, 68 FUNC_FC1_b, 69 FUNC_FC1_c, 70 FUNC_FC2_a, 71 FUNC_FC2_b, 72 FUNC_FC3_a, 73 FUNC_FC3_b, 74 FUNC_FC3_c, 75 FUNC_FC4_a, 76 FUNC_FC4_b, 77 FUNC_FC4_c, 78 FUNC_FC_SHRD0, 79 FUNC_FC_SHRD1, 80 FUNC_FC_SHRD2, 81 FUNC_FC_SHRD3, 82 FUNC_FC_SHRD4, 83 FUNC_FC_SHRD5, 84 FUNC_FC_SHRD6, 85 FUNC_FC_SHRD7, 86 FUNC_FC_SHRD8, 87 FUNC_FC_SHRD9, 88 FUNC_FC_SHRD10, 89 FUNC_FC_SHRD11, 90 FUNC_FC_SHRD12, 91 FUNC_FC_SHRD13, 92 FUNC_FC_SHRD14, 93 FUNC_FC_SHRD15, 94 FUNC_FC_SHRD16, 95 FUNC_FC_SHRD17, 96 FUNC_FC_SHRD18, 97 FUNC_FC_SHRD19, 98 FUNC_FC_SHRD20, 99 FUNC_GPIO, 100 FUNC_IB_TRG_a, 101 FUNC_IB_TRG_b, 102 FUNC_IB_TRG_c, 103 FUNC_IRQ0, 104 FUNC_IRQ_IN_a, 105 FUNC_IRQ_IN_b, 106 FUNC_IRQ_IN_c, 107 FUNC_IRQ0_IN, 108 FUNC_IRQ_OUT_a, 109 FUNC_IRQ_OUT_b, 110 FUNC_IRQ_OUT_c, 111 FUNC_IRQ0_OUT, 112 FUNC_IRQ1, 113 FUNC_IRQ1_IN, 114 FUNC_IRQ1_OUT, 115 FUNC_EXT_IRQ, 116 FUNC_MIIM, 117 FUNC_MIIM_a, 118 FUNC_MIIM_b, 119 FUNC_MIIM_c, 120 FUNC_MIIM_Sa, 121 FUNC_MIIM_Sb, 122 FUNC_OB_TRG, 123 FUNC_OB_TRG_a, 124 FUNC_OB_TRG_b, 125 FUNC_PHY_LED, 126 FUNC_PCI_WAKE, 127 FUNC_MD, 128 FUNC_PTP0, 129 FUNC_PTP1, 130 FUNC_PTP2, 131 FUNC_PTP3, 132 FUNC_PTPSYNC_1, 133 FUNC_PTPSYNC_2, 134 FUNC_PTPSYNC_3, 135 FUNC_PTPSYNC_4, 136 FUNC_PTPSYNC_5, 137 FUNC_PTPSYNC_6, 138 FUNC_PTPSYNC_7, 139 FUNC_PWM, 140 FUNC_QSPI1, 141 FUNC_QSPI2, 142 FUNC_R, 143 FUNC_RECO_a, 144 FUNC_RECO_b, 145 FUNC_RECO_CLK, 146 FUNC_SD, 147 FUNC_SFP, 148 FUNC_SFP_SD, 149 FUNC_SG0, 150 FUNC_SG1, 151 FUNC_SG2, 152 FUNC_SGPIO_a, 153 FUNC_SGPIO_b, 154 FUNC_SI, 155 FUNC_SI2, 156 FUNC_TACHO, 157 FUNC_TACHO_a, 158 FUNC_TACHO_b, 159 FUNC_TWI, 160 FUNC_TWI2, 161 FUNC_TWI3, 162 FUNC_TWI_SCL_M, 163 FUNC_TWI_SLC_GATE, 164 FUNC_TWI_SLC_GATE_AD, 165 FUNC_UART, 166 FUNC_UART2, 167 FUNC_UART3, 168 FUNC_USB_H_a, 169 FUNC_USB_H_b, 170 FUNC_USB_H_c, 171 FUNC_USB_S_a, 172 FUNC_USB_S_b, 173 FUNC_USB_S_c, 174 FUNC_PLL_STAT, 175 FUNC_EMMC, 176 FUNC_EMMC_SD, 177 FUNC_REF_CLK, 178 FUNC_RCVRD_CLK, 179 FUNC_MAX 180 }; 181 182 static const char *const ocelot_function_names[] = { 183 [FUNC_CAN0_a] = "can0_a", 184 [FUNC_CAN0_b] = "can0_b", 185 [FUNC_CAN1] = "can1", 186 [FUNC_NONE] = "none", 187 [FUNC_FC0_a] = "fc0_a", 188 [FUNC_FC0_b] = "fc0_b", 189 [FUNC_FC0_c] = "fc0_c", 190 [FUNC_FC1_a] = "fc1_a", 191 [FUNC_FC1_b] = "fc1_b", 192 [FUNC_FC1_c] = "fc1_c", 193 [FUNC_FC2_a] = "fc2_a", 194 [FUNC_FC2_b] = "fc2_b", 195 [FUNC_FC3_a] = "fc3_a", 196 [FUNC_FC3_b] = "fc3_b", 197 [FUNC_FC3_c] = "fc3_c", 198 [FUNC_FC4_a] = "fc4_a", 199 [FUNC_FC4_b] = "fc4_b", 200 [FUNC_FC4_c] = "fc4_c", 201 [FUNC_FC_SHRD0] = "fc_shrd0", 202 [FUNC_FC_SHRD1] = "fc_shrd1", 203 [FUNC_FC_SHRD2] = "fc_shrd2", 204 [FUNC_FC_SHRD3] = "fc_shrd3", 205 [FUNC_FC_SHRD4] = "fc_shrd4", 206 [FUNC_FC_SHRD5] = "fc_shrd5", 207 [FUNC_FC_SHRD6] = "fc_shrd6", 208 [FUNC_FC_SHRD7] = "fc_shrd7", 209 [FUNC_FC_SHRD8] = "fc_shrd8", 210 [FUNC_FC_SHRD9] = "fc_shrd9", 211 [FUNC_FC_SHRD10] = "fc_shrd10", 212 [FUNC_FC_SHRD11] = "fc_shrd11", 213 [FUNC_FC_SHRD12] = "fc_shrd12", 214 [FUNC_FC_SHRD13] = "fc_shrd13", 215 [FUNC_FC_SHRD14] = "fc_shrd14", 216 [FUNC_FC_SHRD15] = "fc_shrd15", 217 [FUNC_FC_SHRD16] = "fc_shrd16", 218 [FUNC_FC_SHRD17] = "fc_shrd17", 219 [FUNC_FC_SHRD18] = "fc_shrd18", 220 [FUNC_FC_SHRD19] = "fc_shrd19", 221 [FUNC_FC_SHRD20] = "fc_shrd20", 222 [FUNC_GPIO] = "gpio", 223 [FUNC_IB_TRG_a] = "ib_trig_a", 224 [FUNC_IB_TRG_b] = "ib_trig_b", 225 [FUNC_IB_TRG_c] = "ib_trig_c", 226 [FUNC_IRQ0] = "irq0", 227 [FUNC_IRQ_IN_a] = "irq_in_a", 228 [FUNC_IRQ_IN_b] = "irq_in_b", 229 [FUNC_IRQ_IN_c] = "irq_in_c", 230 [FUNC_IRQ0_IN] = "irq0_in", 231 [FUNC_IRQ_OUT_a] = "irq_out_a", 232 [FUNC_IRQ_OUT_b] = "irq_out_b", 233 [FUNC_IRQ_OUT_c] = "irq_out_c", 234 [FUNC_IRQ0_OUT] = "irq0_out", 235 [FUNC_IRQ1] = "irq1", 236 [FUNC_IRQ1_IN] = "irq1_in", 237 [FUNC_IRQ1_OUT] = "irq1_out", 238 [FUNC_EXT_IRQ] = "ext_irq", 239 [FUNC_MIIM] = "miim", 240 [FUNC_MIIM_a] = "miim_a", 241 [FUNC_MIIM_b] = "miim_b", 242 [FUNC_MIIM_c] = "miim_c", 243 [FUNC_MIIM_Sa] = "miim_slave_a", 244 [FUNC_MIIM_Sb] = "miim_slave_b", 245 [FUNC_PHY_LED] = "phy_led", 246 [FUNC_PCI_WAKE] = "pci_wake", 247 [FUNC_MD] = "md", 248 [FUNC_OB_TRG] = "ob_trig", 249 [FUNC_OB_TRG_a] = "ob_trig_a", 250 [FUNC_OB_TRG_b] = "ob_trig_b", 251 [FUNC_PTP0] = "ptp0", 252 [FUNC_PTP1] = "ptp1", 253 [FUNC_PTP2] = "ptp2", 254 [FUNC_PTP3] = "ptp3", 255 [FUNC_PTPSYNC_1] = "ptpsync_1", 256 [FUNC_PTPSYNC_2] = "ptpsync_2", 257 [FUNC_PTPSYNC_3] = "ptpsync_3", 258 [FUNC_PTPSYNC_4] = "ptpsync_4", 259 [FUNC_PTPSYNC_5] = "ptpsync_5", 260 [FUNC_PTPSYNC_6] = "ptpsync_6", 261 [FUNC_PTPSYNC_7] = "ptpsync_7", 262 [FUNC_PWM] = "pwm", 263 [FUNC_QSPI1] = "qspi1", 264 [FUNC_QSPI2] = "qspi2", 265 [FUNC_R] = "reserved", 266 [FUNC_RECO_a] = "reco_a", 267 [FUNC_RECO_b] = "reco_b", 268 [FUNC_RECO_CLK] = "reco_clk", 269 [FUNC_SD] = "sd", 270 [FUNC_SFP] = "sfp", 271 [FUNC_SFP_SD] = "sfp_sd", 272 [FUNC_SG0] = "sg0", 273 [FUNC_SG1] = "sg1", 274 [FUNC_SG2] = "sg2", 275 [FUNC_SGPIO_a] = "sgpio_a", 276 [FUNC_SGPIO_b] = "sgpio_b", 277 [FUNC_SI] = "si", 278 [FUNC_SI2] = "si2", 279 [FUNC_TACHO] = "tacho", 280 [FUNC_TACHO_a] = "tacho_a", 281 [FUNC_TACHO_b] = "tacho_b", 282 [FUNC_TWI] = "twi", 283 [FUNC_TWI2] = "twi2", 284 [FUNC_TWI3] = "twi3", 285 [FUNC_TWI_SCL_M] = "twi_scl_m", 286 [FUNC_TWI_SLC_GATE] = "twi_slc_gate", 287 [FUNC_TWI_SLC_GATE_AD] = "twi_slc_gate_ad", 288 [FUNC_USB_H_a] = "usb_host_a", 289 [FUNC_USB_H_b] = "usb_host_b", 290 [FUNC_USB_H_c] = "usb_host_c", 291 [FUNC_USB_S_a] = "usb_slave_a", 292 [FUNC_USB_S_b] = "usb_slave_b", 293 [FUNC_USB_S_c] = "usb_slave_c", 294 [FUNC_UART] = "uart", 295 [FUNC_UART2] = "uart2", 296 [FUNC_UART3] = "uart3", 297 [FUNC_PLL_STAT] = "pll_stat", 298 [FUNC_EMMC] = "emmc", 299 [FUNC_EMMC_SD] = "emmc_sd", 300 [FUNC_REF_CLK] = "ref_clk", 301 [FUNC_RCVRD_CLK] = "rcvrd_clk", 302 }; 303 304 struct ocelot_pmx_func { 305 const char **groups; 306 unsigned int ngroups; 307 }; 308 309 struct ocelot_pin_caps { 310 unsigned int pin; 311 unsigned char functions[OCELOT_FUNC_PER_PIN]; 312 unsigned char a_functions[OCELOT_FUNC_PER_PIN]; /* Additional functions */ 313 }; 314 315 struct ocelot_pinctrl { 316 struct device *dev; 317 struct pinctrl_dev *pctl; 318 struct gpio_chip gpio_chip; 319 struct regmap *map; 320 struct regmap *pincfg; 321 struct pinctrl_desc *desc; 322 struct ocelot_pmx_func func[FUNC_MAX]; 323 u8 stride; 324 }; 325 326 #define LUTON_P(p, f0, f1) \ 327 static struct ocelot_pin_caps luton_pin_##p = { \ 328 .pin = p, \ 329 .functions = { \ 330 FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_NONE, \ 331 }, \ 332 } 333 334 LUTON_P(0, SG0, NONE); 335 LUTON_P(1, SG0, NONE); 336 LUTON_P(2, SG0, NONE); 337 LUTON_P(3, SG0, NONE); 338 LUTON_P(4, TACHO, NONE); 339 LUTON_P(5, TWI, PHY_LED); 340 LUTON_P(6, TWI, PHY_LED); 341 LUTON_P(7, NONE, PHY_LED); 342 LUTON_P(8, EXT_IRQ, PHY_LED); 343 LUTON_P(9, EXT_IRQ, PHY_LED); 344 LUTON_P(10, SFP, PHY_LED); 345 LUTON_P(11, SFP, PHY_LED); 346 LUTON_P(12, SFP, PHY_LED); 347 LUTON_P(13, SFP, PHY_LED); 348 LUTON_P(14, SI, PHY_LED); 349 LUTON_P(15, SI, PHY_LED); 350 LUTON_P(16, SI, PHY_LED); 351 LUTON_P(17, SFP, PHY_LED); 352 LUTON_P(18, SFP, PHY_LED); 353 LUTON_P(19, SFP, PHY_LED); 354 LUTON_P(20, SFP, PHY_LED); 355 LUTON_P(21, SFP, PHY_LED); 356 LUTON_P(22, SFP, PHY_LED); 357 LUTON_P(23, SFP, PHY_LED); 358 LUTON_P(24, SFP, PHY_LED); 359 LUTON_P(25, SFP, PHY_LED); 360 LUTON_P(26, SFP, PHY_LED); 361 LUTON_P(27, SFP, PHY_LED); 362 LUTON_P(28, SFP, PHY_LED); 363 LUTON_P(29, PWM, NONE); 364 LUTON_P(30, UART, NONE); 365 LUTON_P(31, UART, NONE); 366 367 #define LUTON_PIN(n) { \ 368 .number = n, \ 369 .name = "GPIO_"#n, \ 370 .drv_data = &luton_pin_##n \ 371 } 372 373 static const struct pinctrl_pin_desc luton_pins[] = { 374 LUTON_PIN(0), 375 LUTON_PIN(1), 376 LUTON_PIN(2), 377 LUTON_PIN(3), 378 LUTON_PIN(4), 379 LUTON_PIN(5), 380 LUTON_PIN(6), 381 LUTON_PIN(7), 382 LUTON_PIN(8), 383 LUTON_PIN(9), 384 LUTON_PIN(10), 385 LUTON_PIN(11), 386 LUTON_PIN(12), 387 LUTON_PIN(13), 388 LUTON_PIN(14), 389 LUTON_PIN(15), 390 LUTON_PIN(16), 391 LUTON_PIN(17), 392 LUTON_PIN(18), 393 LUTON_PIN(19), 394 LUTON_PIN(20), 395 LUTON_PIN(21), 396 LUTON_PIN(22), 397 LUTON_PIN(23), 398 LUTON_PIN(24), 399 LUTON_PIN(25), 400 LUTON_PIN(26), 401 LUTON_PIN(27), 402 LUTON_PIN(28), 403 LUTON_PIN(29), 404 LUTON_PIN(30), 405 LUTON_PIN(31), 406 }; 407 408 #define SERVAL_P(p, f0, f1, f2) \ 409 static struct ocelot_pin_caps serval_pin_##p = { \ 410 .pin = p, \ 411 .functions = { \ 412 FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2, \ 413 }, \ 414 } 415 416 SERVAL_P(0, SG0, NONE, NONE); 417 SERVAL_P(1, SG0, NONE, NONE); 418 SERVAL_P(2, SG0, NONE, NONE); 419 SERVAL_P(3, SG0, NONE, NONE); 420 SERVAL_P(4, TACHO, NONE, NONE); 421 SERVAL_P(5, PWM, NONE, NONE); 422 SERVAL_P(6, TWI, NONE, NONE); 423 SERVAL_P(7, TWI, NONE, NONE); 424 SERVAL_P(8, SI, NONE, NONE); 425 SERVAL_P(9, SI, MD, NONE); 426 SERVAL_P(10, SI, MD, NONE); 427 SERVAL_P(11, SFP, MD, TWI_SCL_M); 428 SERVAL_P(12, SFP, MD, TWI_SCL_M); 429 SERVAL_P(13, SFP, UART2, TWI_SCL_M); 430 SERVAL_P(14, SFP, UART2, TWI_SCL_M); 431 SERVAL_P(15, SFP, PTP0, TWI_SCL_M); 432 SERVAL_P(16, SFP, PTP0, TWI_SCL_M); 433 SERVAL_P(17, SFP, PCI_WAKE, TWI_SCL_M); 434 SERVAL_P(18, SFP, NONE, TWI_SCL_M); 435 SERVAL_P(19, SFP, NONE, TWI_SCL_M); 436 SERVAL_P(20, SFP, NONE, TWI_SCL_M); 437 SERVAL_P(21, SFP, NONE, TWI_SCL_M); 438 SERVAL_P(22, NONE, NONE, NONE); 439 SERVAL_P(23, NONE, NONE, NONE); 440 SERVAL_P(24, NONE, NONE, NONE); 441 SERVAL_P(25, NONE, NONE, NONE); 442 SERVAL_P(26, UART, NONE, NONE); 443 SERVAL_P(27, UART, NONE, NONE); 444 SERVAL_P(28, IRQ0, NONE, NONE); 445 SERVAL_P(29, IRQ1, NONE, NONE); 446 SERVAL_P(30, PTP0, NONE, NONE); 447 SERVAL_P(31, PTP0, NONE, NONE); 448 449 #define SERVAL_PIN(n) { \ 450 .number = n, \ 451 .name = "GPIO_"#n, \ 452 .drv_data = &serval_pin_##n \ 453 } 454 455 static const struct pinctrl_pin_desc serval_pins[] = { 456 SERVAL_PIN(0), 457 SERVAL_PIN(1), 458 SERVAL_PIN(2), 459 SERVAL_PIN(3), 460 SERVAL_PIN(4), 461 SERVAL_PIN(5), 462 SERVAL_PIN(6), 463 SERVAL_PIN(7), 464 SERVAL_PIN(8), 465 SERVAL_PIN(9), 466 SERVAL_PIN(10), 467 SERVAL_PIN(11), 468 SERVAL_PIN(12), 469 SERVAL_PIN(13), 470 SERVAL_PIN(14), 471 SERVAL_PIN(15), 472 SERVAL_PIN(16), 473 SERVAL_PIN(17), 474 SERVAL_PIN(18), 475 SERVAL_PIN(19), 476 SERVAL_PIN(20), 477 SERVAL_PIN(21), 478 SERVAL_PIN(22), 479 SERVAL_PIN(23), 480 SERVAL_PIN(24), 481 SERVAL_PIN(25), 482 SERVAL_PIN(26), 483 SERVAL_PIN(27), 484 SERVAL_PIN(28), 485 SERVAL_PIN(29), 486 SERVAL_PIN(30), 487 SERVAL_PIN(31), 488 }; 489 490 #define OCELOT_P(p, f0, f1, f2) \ 491 static struct ocelot_pin_caps ocelot_pin_##p = { \ 492 .pin = p, \ 493 .functions = { \ 494 FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2, \ 495 }, \ 496 } 497 498 OCELOT_P(0, SG0, NONE, NONE); 499 OCELOT_P(1, SG0, NONE, NONE); 500 OCELOT_P(2, SG0, NONE, NONE); 501 OCELOT_P(3, SG0, NONE, NONE); 502 OCELOT_P(4, IRQ0_IN, IRQ0_OUT, TWI_SCL_M); 503 OCELOT_P(5, IRQ1_IN, IRQ1_OUT, PCI_WAKE); 504 OCELOT_P(6, UART, TWI_SCL_M, NONE); 505 OCELOT_P(7, UART, TWI_SCL_M, NONE); 506 OCELOT_P(8, SI, TWI_SCL_M, IRQ0_OUT); 507 OCELOT_P(9, SI, TWI_SCL_M, IRQ1_OUT); 508 OCELOT_P(10, PTP2, TWI_SCL_M, SFP); 509 OCELOT_P(11, PTP3, TWI_SCL_M, SFP); 510 OCELOT_P(12, UART2, TWI_SCL_M, SFP); 511 OCELOT_P(13, UART2, TWI_SCL_M, SFP); 512 OCELOT_P(14, MIIM, TWI_SCL_M, SFP); 513 OCELOT_P(15, MIIM, TWI_SCL_M, SFP); 514 OCELOT_P(16, TWI, NONE, SI); 515 OCELOT_P(17, TWI, TWI_SCL_M, SI); 516 OCELOT_P(18, PTP0, TWI_SCL_M, NONE); 517 OCELOT_P(19, PTP1, TWI_SCL_M, NONE); 518 OCELOT_P(20, RECO_CLK, TACHO, TWI_SCL_M); 519 OCELOT_P(21, RECO_CLK, PWM, TWI_SCL_M); 520 521 #define OCELOT_PIN(n) { \ 522 .number = n, \ 523 .name = "GPIO_"#n, \ 524 .drv_data = &ocelot_pin_##n \ 525 } 526 527 static const struct pinctrl_pin_desc ocelot_pins[] = { 528 OCELOT_PIN(0), 529 OCELOT_PIN(1), 530 OCELOT_PIN(2), 531 OCELOT_PIN(3), 532 OCELOT_PIN(4), 533 OCELOT_PIN(5), 534 OCELOT_PIN(6), 535 OCELOT_PIN(7), 536 OCELOT_PIN(8), 537 OCELOT_PIN(9), 538 OCELOT_PIN(10), 539 OCELOT_PIN(11), 540 OCELOT_PIN(12), 541 OCELOT_PIN(13), 542 OCELOT_PIN(14), 543 OCELOT_PIN(15), 544 OCELOT_PIN(16), 545 OCELOT_PIN(17), 546 OCELOT_PIN(18), 547 OCELOT_PIN(19), 548 OCELOT_PIN(20), 549 OCELOT_PIN(21), 550 }; 551 552 #define JAGUAR2_P(p, f0, f1) \ 553 static struct ocelot_pin_caps jaguar2_pin_##p = { \ 554 .pin = p, \ 555 .functions = { \ 556 FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_NONE \ 557 }, \ 558 } 559 560 JAGUAR2_P(0, SG0, NONE); 561 JAGUAR2_P(1, SG0, NONE); 562 JAGUAR2_P(2, SG0, NONE); 563 JAGUAR2_P(3, SG0, NONE); 564 JAGUAR2_P(4, SG1, NONE); 565 JAGUAR2_P(5, SG1, NONE); 566 JAGUAR2_P(6, IRQ0_IN, IRQ0_OUT); 567 JAGUAR2_P(7, IRQ1_IN, IRQ1_OUT); 568 JAGUAR2_P(8, PTP0, NONE); 569 JAGUAR2_P(9, PTP1, NONE); 570 JAGUAR2_P(10, UART, NONE); 571 JAGUAR2_P(11, UART, NONE); 572 JAGUAR2_P(12, SG1, NONE); 573 JAGUAR2_P(13, SG1, NONE); 574 JAGUAR2_P(14, TWI, TWI_SCL_M); 575 JAGUAR2_P(15, TWI, NONE); 576 JAGUAR2_P(16, SI, TWI_SCL_M); 577 JAGUAR2_P(17, SI, TWI_SCL_M); 578 JAGUAR2_P(18, SI, TWI_SCL_M); 579 JAGUAR2_P(19, PCI_WAKE, NONE); 580 JAGUAR2_P(20, IRQ0_OUT, TWI_SCL_M); 581 JAGUAR2_P(21, IRQ1_OUT, TWI_SCL_M); 582 JAGUAR2_P(22, TACHO, NONE); 583 JAGUAR2_P(23, PWM, NONE); 584 JAGUAR2_P(24, UART2, NONE); 585 JAGUAR2_P(25, UART2, SI); 586 JAGUAR2_P(26, PTP2, SI); 587 JAGUAR2_P(27, PTP3, SI); 588 JAGUAR2_P(28, TWI2, SI); 589 JAGUAR2_P(29, TWI2, SI); 590 JAGUAR2_P(30, SG2, SI); 591 JAGUAR2_P(31, SG2, SI); 592 JAGUAR2_P(32, SG2, SI); 593 JAGUAR2_P(33, SG2, SI); 594 JAGUAR2_P(34, NONE, TWI_SCL_M); 595 JAGUAR2_P(35, NONE, TWI_SCL_M); 596 JAGUAR2_P(36, NONE, TWI_SCL_M); 597 JAGUAR2_P(37, NONE, TWI_SCL_M); 598 JAGUAR2_P(38, NONE, TWI_SCL_M); 599 JAGUAR2_P(39, NONE, TWI_SCL_M); 600 JAGUAR2_P(40, NONE, TWI_SCL_M); 601 JAGUAR2_P(41, NONE, TWI_SCL_M); 602 JAGUAR2_P(42, NONE, TWI_SCL_M); 603 JAGUAR2_P(43, NONE, TWI_SCL_M); 604 JAGUAR2_P(44, NONE, SFP); 605 JAGUAR2_P(45, NONE, SFP); 606 JAGUAR2_P(46, NONE, SFP); 607 JAGUAR2_P(47, NONE, SFP); 608 JAGUAR2_P(48, SFP, NONE); 609 JAGUAR2_P(49, SFP, SI); 610 JAGUAR2_P(50, SFP, SI); 611 JAGUAR2_P(51, SFP, SI); 612 JAGUAR2_P(52, SFP, NONE); 613 JAGUAR2_P(53, SFP, NONE); 614 JAGUAR2_P(54, SFP, NONE); 615 JAGUAR2_P(55, SFP, NONE); 616 JAGUAR2_P(56, MIIM, SFP); 617 JAGUAR2_P(57, MIIM, SFP); 618 JAGUAR2_P(58, MIIM, SFP); 619 JAGUAR2_P(59, MIIM, SFP); 620 JAGUAR2_P(60, NONE, NONE); 621 JAGUAR2_P(61, NONE, NONE); 622 JAGUAR2_P(62, NONE, NONE); 623 JAGUAR2_P(63, NONE, NONE); 624 625 #define JAGUAR2_PIN(n) { \ 626 .number = n, \ 627 .name = "GPIO_"#n, \ 628 .drv_data = &jaguar2_pin_##n \ 629 } 630 631 static const struct pinctrl_pin_desc jaguar2_pins[] = { 632 JAGUAR2_PIN(0), 633 JAGUAR2_PIN(1), 634 JAGUAR2_PIN(2), 635 JAGUAR2_PIN(3), 636 JAGUAR2_PIN(4), 637 JAGUAR2_PIN(5), 638 JAGUAR2_PIN(6), 639 JAGUAR2_PIN(7), 640 JAGUAR2_PIN(8), 641 JAGUAR2_PIN(9), 642 JAGUAR2_PIN(10), 643 JAGUAR2_PIN(11), 644 JAGUAR2_PIN(12), 645 JAGUAR2_PIN(13), 646 JAGUAR2_PIN(14), 647 JAGUAR2_PIN(15), 648 JAGUAR2_PIN(16), 649 JAGUAR2_PIN(17), 650 JAGUAR2_PIN(18), 651 JAGUAR2_PIN(19), 652 JAGUAR2_PIN(20), 653 JAGUAR2_PIN(21), 654 JAGUAR2_PIN(22), 655 JAGUAR2_PIN(23), 656 JAGUAR2_PIN(24), 657 JAGUAR2_PIN(25), 658 JAGUAR2_PIN(26), 659 JAGUAR2_PIN(27), 660 JAGUAR2_PIN(28), 661 JAGUAR2_PIN(29), 662 JAGUAR2_PIN(30), 663 JAGUAR2_PIN(31), 664 JAGUAR2_PIN(32), 665 JAGUAR2_PIN(33), 666 JAGUAR2_PIN(34), 667 JAGUAR2_PIN(35), 668 JAGUAR2_PIN(36), 669 JAGUAR2_PIN(37), 670 JAGUAR2_PIN(38), 671 JAGUAR2_PIN(39), 672 JAGUAR2_PIN(40), 673 JAGUAR2_PIN(41), 674 JAGUAR2_PIN(42), 675 JAGUAR2_PIN(43), 676 JAGUAR2_PIN(44), 677 JAGUAR2_PIN(45), 678 JAGUAR2_PIN(46), 679 JAGUAR2_PIN(47), 680 JAGUAR2_PIN(48), 681 JAGUAR2_PIN(49), 682 JAGUAR2_PIN(50), 683 JAGUAR2_PIN(51), 684 JAGUAR2_PIN(52), 685 JAGUAR2_PIN(53), 686 JAGUAR2_PIN(54), 687 JAGUAR2_PIN(55), 688 JAGUAR2_PIN(56), 689 JAGUAR2_PIN(57), 690 JAGUAR2_PIN(58), 691 JAGUAR2_PIN(59), 692 JAGUAR2_PIN(60), 693 JAGUAR2_PIN(61), 694 JAGUAR2_PIN(62), 695 JAGUAR2_PIN(63), 696 }; 697 698 #define SERVALT_P(p, f0, f1, f2) \ 699 static struct ocelot_pin_caps servalt_pin_##p = { \ 700 .pin = p, \ 701 .functions = { \ 702 FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2 \ 703 }, \ 704 } 705 706 SERVALT_P(0, SG0, NONE, NONE); 707 SERVALT_P(1, SG0, NONE, NONE); 708 SERVALT_P(2, SG0, NONE, NONE); 709 SERVALT_P(3, SG0, NONE, NONE); 710 SERVALT_P(4, IRQ0_IN, IRQ0_OUT, TWI_SCL_M); 711 SERVALT_P(5, IRQ1_IN, IRQ1_OUT, TWI_SCL_M); 712 SERVALT_P(6, UART, NONE, NONE); 713 SERVALT_P(7, UART, NONE, NONE); 714 SERVALT_P(8, SI, SFP, TWI_SCL_M); 715 SERVALT_P(9, PCI_WAKE, SFP, SI); 716 SERVALT_P(10, PTP0, SFP, TWI_SCL_M); 717 SERVALT_P(11, PTP1, SFP, TWI_SCL_M); 718 SERVALT_P(12, REF_CLK, SFP, TWI_SCL_M); 719 SERVALT_P(13, REF_CLK, SFP, TWI_SCL_M); 720 SERVALT_P(14, REF_CLK, IRQ0_OUT, SI); 721 SERVALT_P(15, REF_CLK, IRQ1_OUT, SI); 722 SERVALT_P(16, TACHO, SFP, SI); 723 SERVALT_P(17, PWM, NONE, TWI_SCL_M); 724 SERVALT_P(18, PTP2, SFP, SI); 725 SERVALT_P(19, PTP3, SFP, SI); 726 SERVALT_P(20, UART2, SFP, SI); 727 SERVALT_P(21, UART2, NONE, NONE); 728 SERVALT_P(22, MIIM, SFP, TWI2); 729 SERVALT_P(23, MIIM, SFP, TWI2); 730 SERVALT_P(24, TWI, NONE, NONE); 731 SERVALT_P(25, TWI, SFP, TWI_SCL_M); 732 SERVALT_P(26, TWI_SCL_M, SFP, SI); 733 SERVALT_P(27, TWI_SCL_M, SFP, SI); 734 SERVALT_P(28, TWI_SCL_M, SFP, SI); 735 SERVALT_P(29, TWI_SCL_M, NONE, NONE); 736 SERVALT_P(30, TWI_SCL_M, NONE, NONE); 737 SERVALT_P(31, TWI_SCL_M, NONE, NONE); 738 SERVALT_P(32, TWI_SCL_M, NONE, NONE); 739 SERVALT_P(33, RCVRD_CLK, NONE, NONE); 740 SERVALT_P(34, RCVRD_CLK, NONE, NONE); 741 SERVALT_P(35, RCVRD_CLK, NONE, NONE); 742 SERVALT_P(36, RCVRD_CLK, NONE, NONE); 743 744 #define SERVALT_PIN(n) { \ 745 .number = n, \ 746 .name = "GPIO_"#n, \ 747 .drv_data = &servalt_pin_##n \ 748 } 749 750 static const struct pinctrl_pin_desc servalt_pins[] = { 751 SERVALT_PIN(0), 752 SERVALT_PIN(1), 753 SERVALT_PIN(2), 754 SERVALT_PIN(3), 755 SERVALT_PIN(4), 756 SERVALT_PIN(5), 757 SERVALT_PIN(6), 758 SERVALT_PIN(7), 759 SERVALT_PIN(8), 760 SERVALT_PIN(9), 761 SERVALT_PIN(10), 762 SERVALT_PIN(11), 763 SERVALT_PIN(12), 764 SERVALT_PIN(13), 765 SERVALT_PIN(14), 766 SERVALT_PIN(15), 767 SERVALT_PIN(16), 768 SERVALT_PIN(17), 769 SERVALT_PIN(18), 770 SERVALT_PIN(19), 771 SERVALT_PIN(20), 772 SERVALT_PIN(21), 773 SERVALT_PIN(22), 774 SERVALT_PIN(23), 775 SERVALT_PIN(24), 776 SERVALT_PIN(25), 777 SERVALT_PIN(26), 778 SERVALT_PIN(27), 779 SERVALT_PIN(28), 780 SERVALT_PIN(29), 781 SERVALT_PIN(30), 782 SERVALT_PIN(31), 783 SERVALT_PIN(32), 784 SERVALT_PIN(33), 785 SERVALT_PIN(34), 786 SERVALT_PIN(35), 787 SERVALT_PIN(36), 788 }; 789 790 #define SPARX5_P(p, f0, f1, f2) \ 791 static struct ocelot_pin_caps sparx5_pin_##p = { \ 792 .pin = p, \ 793 .functions = { \ 794 FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2 \ 795 }, \ 796 } 797 798 SPARX5_P(0, SG0, PLL_STAT, NONE); 799 SPARX5_P(1, SG0, NONE, NONE); 800 SPARX5_P(2, SG0, NONE, NONE); 801 SPARX5_P(3, SG0, NONE, NONE); 802 SPARX5_P(4, SG1, NONE, NONE); 803 SPARX5_P(5, SG1, NONE, NONE); 804 SPARX5_P(6, IRQ0_IN, IRQ0_OUT, SFP); 805 SPARX5_P(7, IRQ1_IN, IRQ1_OUT, SFP); 806 SPARX5_P(8, PTP0, NONE, SFP); 807 SPARX5_P(9, PTP1, SFP, TWI_SCL_M); 808 SPARX5_P(10, UART, NONE, NONE); 809 SPARX5_P(11, UART, NONE, NONE); 810 SPARX5_P(12, SG1, NONE, NONE); 811 SPARX5_P(13, SG1, NONE, NONE); 812 SPARX5_P(14, TWI, TWI_SCL_M, NONE); 813 SPARX5_P(15, TWI, NONE, NONE); 814 SPARX5_P(16, SI, TWI_SCL_M, SFP); 815 SPARX5_P(17, SI, TWI_SCL_M, SFP); 816 SPARX5_P(18, SI, TWI_SCL_M, SFP); 817 SPARX5_P(19, PCI_WAKE, TWI_SCL_M, SFP); 818 SPARX5_P(20, IRQ0_OUT, TWI_SCL_M, SFP); 819 SPARX5_P(21, IRQ1_OUT, TACHO, SFP); 820 SPARX5_P(22, TACHO, IRQ0_OUT, TWI_SCL_M); 821 SPARX5_P(23, PWM, UART3, TWI_SCL_M); 822 SPARX5_P(24, PTP2, UART3, TWI_SCL_M); 823 SPARX5_P(25, PTP3, SI, TWI_SCL_M); 824 SPARX5_P(26, UART2, SI, TWI_SCL_M); 825 SPARX5_P(27, UART2, SI, TWI_SCL_M); 826 SPARX5_P(28, TWI2, SI, SFP); 827 SPARX5_P(29, TWI2, SI, SFP); 828 SPARX5_P(30, SG2, SI, PWM); 829 SPARX5_P(31, SG2, SI, TWI_SCL_M); 830 SPARX5_P(32, SG2, SI, TWI_SCL_M); 831 SPARX5_P(33, SG2, SI, SFP); 832 SPARX5_P(34, NONE, TWI_SCL_M, EMMC); 833 SPARX5_P(35, SFP, TWI_SCL_M, EMMC); 834 SPARX5_P(36, SFP, TWI_SCL_M, EMMC); 835 SPARX5_P(37, SFP, NONE, EMMC); 836 SPARX5_P(38, NONE, TWI_SCL_M, EMMC); 837 SPARX5_P(39, SI2, TWI_SCL_M, EMMC); 838 SPARX5_P(40, SI2, TWI_SCL_M, EMMC); 839 SPARX5_P(41, SI2, TWI_SCL_M, EMMC); 840 SPARX5_P(42, SI2, TWI_SCL_M, EMMC); 841 SPARX5_P(43, SI2, TWI_SCL_M, EMMC); 842 SPARX5_P(44, SI, SFP, EMMC); 843 SPARX5_P(45, SI, SFP, EMMC); 844 SPARX5_P(46, NONE, SFP, EMMC); 845 SPARX5_P(47, NONE, SFP, EMMC); 846 SPARX5_P(48, TWI3, SI, SFP); 847 SPARX5_P(49, TWI3, NONE, SFP); 848 SPARX5_P(50, SFP, NONE, TWI_SCL_M); 849 SPARX5_P(51, SFP, SI, TWI_SCL_M); 850 SPARX5_P(52, SFP, MIIM, TWI_SCL_M); 851 SPARX5_P(53, SFP, MIIM, TWI_SCL_M); 852 SPARX5_P(54, SFP, PTP2, TWI_SCL_M); 853 SPARX5_P(55, SFP, PTP3, PCI_WAKE); 854 SPARX5_P(56, MIIM, SFP, TWI_SCL_M); 855 SPARX5_P(57, MIIM, SFP, TWI_SCL_M); 856 SPARX5_P(58, MIIM, SFP, TWI_SCL_M); 857 SPARX5_P(59, MIIM, SFP, NONE); 858 SPARX5_P(60, RECO_CLK, NONE, NONE); 859 SPARX5_P(61, RECO_CLK, NONE, NONE); 860 SPARX5_P(62, RECO_CLK, PLL_STAT, NONE); 861 SPARX5_P(63, RECO_CLK, NONE, NONE); 862 863 #define SPARX5_PIN(n) { \ 864 .number = n, \ 865 .name = "GPIO_"#n, \ 866 .drv_data = &sparx5_pin_##n \ 867 } 868 869 static const struct pinctrl_pin_desc sparx5_pins[] = { 870 SPARX5_PIN(0), 871 SPARX5_PIN(1), 872 SPARX5_PIN(2), 873 SPARX5_PIN(3), 874 SPARX5_PIN(4), 875 SPARX5_PIN(5), 876 SPARX5_PIN(6), 877 SPARX5_PIN(7), 878 SPARX5_PIN(8), 879 SPARX5_PIN(9), 880 SPARX5_PIN(10), 881 SPARX5_PIN(11), 882 SPARX5_PIN(12), 883 SPARX5_PIN(13), 884 SPARX5_PIN(14), 885 SPARX5_PIN(15), 886 SPARX5_PIN(16), 887 SPARX5_PIN(17), 888 SPARX5_PIN(18), 889 SPARX5_PIN(19), 890 SPARX5_PIN(20), 891 SPARX5_PIN(21), 892 SPARX5_PIN(22), 893 SPARX5_PIN(23), 894 SPARX5_PIN(24), 895 SPARX5_PIN(25), 896 SPARX5_PIN(26), 897 SPARX5_PIN(27), 898 SPARX5_PIN(28), 899 SPARX5_PIN(29), 900 SPARX5_PIN(30), 901 SPARX5_PIN(31), 902 SPARX5_PIN(32), 903 SPARX5_PIN(33), 904 SPARX5_PIN(34), 905 SPARX5_PIN(35), 906 SPARX5_PIN(36), 907 SPARX5_PIN(37), 908 SPARX5_PIN(38), 909 SPARX5_PIN(39), 910 SPARX5_PIN(40), 911 SPARX5_PIN(41), 912 SPARX5_PIN(42), 913 SPARX5_PIN(43), 914 SPARX5_PIN(44), 915 SPARX5_PIN(45), 916 SPARX5_PIN(46), 917 SPARX5_PIN(47), 918 SPARX5_PIN(48), 919 SPARX5_PIN(49), 920 SPARX5_PIN(50), 921 SPARX5_PIN(51), 922 SPARX5_PIN(52), 923 SPARX5_PIN(53), 924 SPARX5_PIN(54), 925 SPARX5_PIN(55), 926 SPARX5_PIN(56), 927 SPARX5_PIN(57), 928 SPARX5_PIN(58), 929 SPARX5_PIN(59), 930 SPARX5_PIN(60), 931 SPARX5_PIN(61), 932 SPARX5_PIN(62), 933 SPARX5_PIN(63), 934 }; 935 936 #define LAN966X_P(p, f0, f1, f2, f3, f4, f5, f6, f7) \ 937 static struct ocelot_pin_caps lan966x_pin_##p = { \ 938 .pin = p, \ 939 .functions = { \ 940 FUNC_##f0, FUNC_##f1, FUNC_##f2, \ 941 FUNC_##f3 \ 942 }, \ 943 .a_functions = { \ 944 FUNC_##f4, FUNC_##f5, FUNC_##f6, \ 945 FUNC_##f7 \ 946 }, \ 947 } 948 949 /* Pinmuxing table taken from data sheet */ 950 /* Pin FUNC0 FUNC1 FUNC2 FUNC3 FUNC4 FUNC5 FUNC6 FUNC7 */ 951 LAN966X_P(0, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 952 LAN966X_P(1, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 953 LAN966X_P(2, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 954 LAN966X_P(3, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 955 LAN966X_P(4, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 956 LAN966X_P(5, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 957 LAN966X_P(6, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 958 LAN966X_P(7, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 959 LAN966X_P(8, GPIO, FC0_a, USB_H_b, NONE, USB_S_b, NONE, NONE, R); 960 LAN966X_P(9, GPIO, FC0_a, USB_H_b, NONE, NONE, NONE, NONE, R); 961 LAN966X_P(10, GPIO, FC0_a, NONE, NONE, NONE, NONE, NONE, R); 962 LAN966X_P(11, GPIO, FC1_a, NONE, NONE, NONE, NONE, NONE, R); 963 LAN966X_P(12, GPIO, FC1_a, NONE, NONE, NONE, NONE, NONE, R); 964 LAN966X_P(13, GPIO, FC1_a, NONE, NONE, NONE, NONE, NONE, R); 965 LAN966X_P(14, GPIO, FC2_a, NONE, NONE, NONE, NONE, NONE, R); 966 LAN966X_P(15, GPIO, FC2_a, NONE, NONE, NONE, NONE, NONE, R); 967 LAN966X_P(16, GPIO, FC2_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, IRQ_OUT_c, R); 968 LAN966X_P(17, GPIO, FC3_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, IRQ_OUT_c, R); 969 LAN966X_P(18, GPIO, FC3_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, IRQ_OUT_c, R); 970 LAN966X_P(19, GPIO, FC3_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, IRQ_OUT_c, R); 971 LAN966X_P(20, GPIO, FC4_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, NONE, R); 972 LAN966X_P(21, GPIO, FC4_a, NONE, NONE, OB_TRG_a, NONE, NONE, R); 973 LAN966X_P(22, GPIO, FC4_a, NONE, NONE, OB_TRG_a, NONE, NONE, R); 974 LAN966X_P(23, GPIO, NONE, NONE, NONE, OB_TRG_a, NONE, NONE, R); 975 LAN966X_P(24, GPIO, FC0_b, IB_TRG_a, USB_H_c, OB_TRG_a, IRQ_IN_c, TACHO_a, R); 976 LAN966X_P(25, GPIO, FC0_b, IB_TRG_a, USB_H_c, OB_TRG_a, IRQ_OUT_c, SFP_SD, R); 977 LAN966X_P(26, GPIO, FC0_b, IB_TRG_a, USB_S_c, OB_TRG_a, CAN0_a, SFP_SD, R); 978 LAN966X_P(27, GPIO, NONE, NONE, NONE, OB_TRG_a, CAN0_a, NONE, R); 979 LAN966X_P(28, GPIO, MIIM_a, NONE, NONE, OB_TRG_a, IRQ_OUT_c, SFP_SD, R); 980 LAN966X_P(29, GPIO, MIIM_a, NONE, NONE, OB_TRG_a, NONE, NONE, R); 981 LAN966X_P(30, GPIO, FC3_c, CAN1, NONE, OB_TRG, RECO_b, NONE, R); 982 LAN966X_P(31, GPIO, FC3_c, CAN1, NONE, OB_TRG, RECO_b, NONE, R); 983 LAN966X_P(32, GPIO, FC3_c, NONE, SGPIO_a, NONE, MIIM_Sa, NONE, R); 984 LAN966X_P(33, GPIO, FC1_b, NONE, SGPIO_a, NONE, MIIM_Sa, MIIM_b, R); 985 LAN966X_P(34, GPIO, FC1_b, NONE, SGPIO_a, NONE, MIIM_Sa, MIIM_b, R); 986 LAN966X_P(35, GPIO, FC1_b, NONE, SGPIO_a, CAN0_b, NONE, NONE, R); 987 LAN966X_P(36, GPIO, NONE, PTPSYNC_1, NONE, CAN0_b, NONE, NONE, R); 988 LAN966X_P(37, GPIO, FC_SHRD0, PTPSYNC_2, TWI_SLC_GATE_AD, NONE, NONE, NONE, R); 989 LAN966X_P(38, GPIO, NONE, PTPSYNC_3, NONE, NONE, NONE, NONE, R); 990 LAN966X_P(39, GPIO, NONE, PTPSYNC_4, NONE, NONE, NONE, NONE, R); 991 LAN966X_P(40, GPIO, FC_SHRD1, PTPSYNC_5, NONE, NONE, NONE, NONE, R); 992 LAN966X_P(41, GPIO, FC_SHRD2, PTPSYNC_6, TWI_SLC_GATE_AD, NONE, NONE, NONE, R); 993 LAN966X_P(42, GPIO, FC_SHRD3, PTPSYNC_7, TWI_SLC_GATE_AD, NONE, NONE, NONE, R); 994 LAN966X_P(43, GPIO, FC2_b, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, RECO_a, IRQ_IN_a, R); 995 LAN966X_P(44, GPIO, FC2_b, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, RECO_a, IRQ_IN_a, R); 996 LAN966X_P(45, GPIO, FC2_b, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, NONE, IRQ_IN_a, R); 997 LAN966X_P(46, GPIO, FC1_c, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, FC_SHRD4, IRQ_IN_a, R); 998 LAN966X_P(47, GPIO, FC1_c, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, FC_SHRD5, IRQ_IN_a, R); 999 LAN966X_P(48, GPIO, FC1_c, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, FC_SHRD6, IRQ_IN_a, R); 1000 LAN966X_P(49, GPIO, FC_SHRD7, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, TWI_SLC_GATE, IRQ_IN_a, R); 1001 LAN966X_P(50, GPIO, FC_SHRD16, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, TWI_SLC_GATE, NONE, R); 1002 LAN966X_P(51, GPIO, FC3_b, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, NONE, IRQ_IN_b, R); 1003 LAN966X_P(52, GPIO, FC3_b, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, TACHO_b, IRQ_IN_b, R); 1004 LAN966X_P(53, GPIO, FC3_b, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, NONE, IRQ_IN_b, R); 1005 LAN966X_P(54, GPIO, FC_SHRD8, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, TWI_SLC_GATE, IRQ_IN_b, R); 1006 LAN966X_P(55, GPIO, FC_SHRD9, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, TWI_SLC_GATE, IRQ_IN_b, R); 1007 LAN966X_P(56, GPIO, FC4_b, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, FC_SHRD10, IRQ_IN_b, R); 1008 LAN966X_P(57, GPIO, FC4_b, TWI_SLC_GATE, IB_TRG_c, IRQ_OUT_b, FC_SHRD11, IRQ_IN_b, R); 1009 LAN966X_P(58, GPIO, FC4_b, TWI_SLC_GATE, IB_TRG_c, IRQ_OUT_b, FC_SHRD12, IRQ_IN_b, R); 1010 LAN966X_P(59, GPIO, QSPI1, MIIM_c, NONE, NONE, MIIM_Sb, NONE, R); 1011 LAN966X_P(60, GPIO, QSPI1, MIIM_c, NONE, NONE, MIIM_Sb, NONE, R); 1012 LAN966X_P(61, GPIO, QSPI1, NONE, SGPIO_b, FC0_c, MIIM_Sb, NONE, R); 1013 LAN966X_P(62, GPIO, QSPI1, FC_SHRD13, SGPIO_b, FC0_c, TWI_SLC_GATE, SFP_SD, R); 1014 LAN966X_P(63, GPIO, QSPI1, FC_SHRD14, SGPIO_b, FC0_c, TWI_SLC_GATE, SFP_SD, R); 1015 LAN966X_P(64, GPIO, QSPI1, FC4_c, SGPIO_b, FC_SHRD15, TWI_SLC_GATE, SFP_SD, R); 1016 LAN966X_P(65, GPIO, USB_H_a, FC4_c, NONE, IRQ_OUT_c, TWI_SLC_GATE_AD, NONE, R); 1017 LAN966X_P(66, GPIO, USB_H_a, FC4_c, USB_S_a, IRQ_OUT_c, IRQ_IN_c, NONE, R); 1018 LAN966X_P(67, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R); 1019 LAN966X_P(68, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R); 1020 LAN966X_P(69, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R); 1021 LAN966X_P(70, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R); 1022 LAN966X_P(71, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R); 1023 LAN966X_P(72, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R); 1024 LAN966X_P(73, GPIO, EMMC, NONE, NONE, SD, NONE, NONE, R); 1025 LAN966X_P(74, GPIO, EMMC, NONE, FC_SHRD17, SD, TWI_SLC_GATE, NONE, R); 1026 LAN966X_P(75, GPIO, EMMC, NONE, FC_SHRD18, SD, TWI_SLC_GATE, NONE, R); 1027 LAN966X_P(76, GPIO, EMMC, NONE, FC_SHRD19, SD, TWI_SLC_GATE, NONE, R); 1028 LAN966X_P(77, GPIO, EMMC_SD, NONE, FC_SHRD20, NONE, TWI_SLC_GATE, NONE, R); 1029 1030 #define LAN966X_PIN(n) { \ 1031 .number = n, \ 1032 .name = "GPIO_"#n, \ 1033 .drv_data = &lan966x_pin_##n \ 1034 } 1035 1036 static const struct pinctrl_pin_desc lan966x_pins[] = { 1037 LAN966X_PIN(0), 1038 LAN966X_PIN(1), 1039 LAN966X_PIN(2), 1040 LAN966X_PIN(3), 1041 LAN966X_PIN(4), 1042 LAN966X_PIN(5), 1043 LAN966X_PIN(6), 1044 LAN966X_PIN(7), 1045 LAN966X_PIN(8), 1046 LAN966X_PIN(9), 1047 LAN966X_PIN(10), 1048 LAN966X_PIN(11), 1049 LAN966X_PIN(12), 1050 LAN966X_PIN(13), 1051 LAN966X_PIN(14), 1052 LAN966X_PIN(15), 1053 LAN966X_PIN(16), 1054 LAN966X_PIN(17), 1055 LAN966X_PIN(18), 1056 LAN966X_PIN(19), 1057 LAN966X_PIN(20), 1058 LAN966X_PIN(21), 1059 LAN966X_PIN(22), 1060 LAN966X_PIN(23), 1061 LAN966X_PIN(24), 1062 LAN966X_PIN(25), 1063 LAN966X_PIN(26), 1064 LAN966X_PIN(27), 1065 LAN966X_PIN(28), 1066 LAN966X_PIN(29), 1067 LAN966X_PIN(30), 1068 LAN966X_PIN(31), 1069 LAN966X_PIN(32), 1070 LAN966X_PIN(33), 1071 LAN966X_PIN(34), 1072 LAN966X_PIN(35), 1073 LAN966X_PIN(36), 1074 LAN966X_PIN(37), 1075 LAN966X_PIN(38), 1076 LAN966X_PIN(39), 1077 LAN966X_PIN(40), 1078 LAN966X_PIN(41), 1079 LAN966X_PIN(42), 1080 LAN966X_PIN(43), 1081 LAN966X_PIN(44), 1082 LAN966X_PIN(45), 1083 LAN966X_PIN(46), 1084 LAN966X_PIN(47), 1085 LAN966X_PIN(48), 1086 LAN966X_PIN(49), 1087 LAN966X_PIN(50), 1088 LAN966X_PIN(51), 1089 LAN966X_PIN(52), 1090 LAN966X_PIN(53), 1091 LAN966X_PIN(54), 1092 LAN966X_PIN(55), 1093 LAN966X_PIN(56), 1094 LAN966X_PIN(57), 1095 LAN966X_PIN(58), 1096 LAN966X_PIN(59), 1097 LAN966X_PIN(60), 1098 LAN966X_PIN(61), 1099 LAN966X_PIN(62), 1100 LAN966X_PIN(63), 1101 LAN966X_PIN(64), 1102 LAN966X_PIN(65), 1103 LAN966X_PIN(66), 1104 LAN966X_PIN(67), 1105 LAN966X_PIN(68), 1106 LAN966X_PIN(69), 1107 LAN966X_PIN(70), 1108 LAN966X_PIN(71), 1109 LAN966X_PIN(72), 1110 LAN966X_PIN(73), 1111 LAN966X_PIN(74), 1112 LAN966X_PIN(75), 1113 LAN966X_PIN(76), 1114 LAN966X_PIN(77), 1115 }; 1116 1117 static int ocelot_get_functions_count(struct pinctrl_dev *pctldev) 1118 { 1119 return ARRAY_SIZE(ocelot_function_names); 1120 } 1121 1122 static const char *ocelot_get_function_name(struct pinctrl_dev *pctldev, 1123 unsigned int function) 1124 { 1125 return ocelot_function_names[function]; 1126 } 1127 1128 static int ocelot_get_function_groups(struct pinctrl_dev *pctldev, 1129 unsigned int function, 1130 const char *const **groups, 1131 unsigned *const num_groups) 1132 { 1133 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1134 1135 *groups = info->func[function].groups; 1136 *num_groups = info->func[function].ngroups; 1137 1138 return 0; 1139 } 1140 1141 static int ocelot_pin_function_idx(struct ocelot_pinctrl *info, 1142 unsigned int pin, unsigned int function) 1143 { 1144 struct ocelot_pin_caps *p = info->desc->pins[pin].drv_data; 1145 int i; 1146 1147 for (i = 0; i < OCELOT_FUNC_PER_PIN; i++) { 1148 if (function == p->functions[i]) 1149 return i; 1150 1151 if (function == p->a_functions[i]) 1152 return i + OCELOT_FUNC_PER_PIN; 1153 } 1154 1155 return -1; 1156 } 1157 1158 #define REG_ALT(msb, info, p) (OCELOT_GPIO_ALT0 * (info)->stride + 4 * ((msb) + ((info)->stride * ((p) / 32)))) 1159 1160 static int ocelot_pinmux_set_mux(struct pinctrl_dev *pctldev, 1161 unsigned int selector, unsigned int group) 1162 { 1163 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1164 struct ocelot_pin_caps *pin = info->desc->pins[group].drv_data; 1165 unsigned int p = pin->pin % 32; 1166 int f; 1167 1168 f = ocelot_pin_function_idx(info, group, selector); 1169 if (f < 0) 1170 return -EINVAL; 1171 1172 /* 1173 * f is encoded on two bits. 1174 * bit 0 of f goes in BIT(pin) of ALT[0], bit 1 of f goes in BIT(pin) of 1175 * ALT[1] 1176 * This is racy because both registers can't be updated at the same time 1177 * but it doesn't matter much for now. 1178 * Note: ALT0/ALT1 are organized specially for 64 gpio targets 1179 */ 1180 regmap_update_bits(info->map, REG_ALT(0, info, pin->pin), 1181 BIT(p), f << p); 1182 regmap_update_bits(info->map, REG_ALT(1, info, pin->pin), 1183 BIT(p), f << (p - 1)); 1184 1185 return 0; 1186 } 1187 1188 static int lan966x_pinmux_set_mux(struct pinctrl_dev *pctldev, 1189 unsigned int selector, unsigned int group) 1190 { 1191 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1192 struct ocelot_pin_caps *pin = info->desc->pins[group].drv_data; 1193 unsigned int p = pin->pin % 32; 1194 int f; 1195 1196 f = ocelot_pin_function_idx(info, group, selector); 1197 if (f < 0) 1198 return -EINVAL; 1199 1200 /* 1201 * f is encoded on three bits. 1202 * bit 0 of f goes in BIT(pin) of ALT[0], bit 1 of f goes in BIT(pin) of 1203 * ALT[1], bit 2 of f goes in BIT(pin) of ALT[2] 1204 * This is racy because three registers can't be updated at the same time 1205 * but it doesn't matter much for now. 1206 * Note: ALT0/ALT1/ALT2 are organized specially for 78 gpio targets 1207 */ 1208 regmap_update_bits(info->map, REG_ALT(0, info, pin->pin), 1209 BIT(p), f << p); 1210 regmap_update_bits(info->map, REG_ALT(1, info, pin->pin), 1211 BIT(p), (f >> 1) << p); 1212 regmap_update_bits(info->map, REG_ALT(2, info, pin->pin), 1213 BIT(p), (f >> 2) << p); 1214 1215 return 0; 1216 } 1217 1218 #define REG(r, info, p) ((r) * (info)->stride + (4 * ((p) / 32))) 1219 1220 static int ocelot_gpio_set_direction(struct pinctrl_dev *pctldev, 1221 struct pinctrl_gpio_range *range, 1222 unsigned int pin, bool input) 1223 { 1224 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1225 unsigned int p = pin % 32; 1226 1227 regmap_update_bits(info->map, REG(OCELOT_GPIO_OE, info, pin), BIT(p), 1228 input ? 0 : BIT(p)); 1229 1230 return 0; 1231 } 1232 1233 static int ocelot_gpio_request_enable(struct pinctrl_dev *pctldev, 1234 struct pinctrl_gpio_range *range, 1235 unsigned int offset) 1236 { 1237 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1238 unsigned int p = offset % 32; 1239 1240 regmap_update_bits(info->map, REG_ALT(0, info, offset), 1241 BIT(p), 0); 1242 regmap_update_bits(info->map, REG_ALT(1, info, offset), 1243 BIT(p), 0); 1244 1245 return 0; 1246 } 1247 1248 static int lan966x_gpio_request_enable(struct pinctrl_dev *pctldev, 1249 struct pinctrl_gpio_range *range, 1250 unsigned int offset) 1251 { 1252 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1253 unsigned int p = offset % 32; 1254 1255 regmap_update_bits(info->map, REG_ALT(0, info, offset), 1256 BIT(p), 0); 1257 regmap_update_bits(info->map, REG_ALT(1, info, offset), 1258 BIT(p), 0); 1259 regmap_update_bits(info->map, REG_ALT(2, info, offset), 1260 BIT(p), 0); 1261 1262 return 0; 1263 } 1264 1265 static const struct pinmux_ops ocelot_pmx_ops = { 1266 .get_functions_count = ocelot_get_functions_count, 1267 .get_function_name = ocelot_get_function_name, 1268 .get_function_groups = ocelot_get_function_groups, 1269 .set_mux = ocelot_pinmux_set_mux, 1270 .gpio_set_direction = ocelot_gpio_set_direction, 1271 .gpio_request_enable = ocelot_gpio_request_enable, 1272 }; 1273 1274 static const struct pinmux_ops lan966x_pmx_ops = { 1275 .get_functions_count = ocelot_get_functions_count, 1276 .get_function_name = ocelot_get_function_name, 1277 .get_function_groups = ocelot_get_function_groups, 1278 .set_mux = lan966x_pinmux_set_mux, 1279 .gpio_set_direction = ocelot_gpio_set_direction, 1280 .gpio_request_enable = lan966x_gpio_request_enable, 1281 }; 1282 1283 static int ocelot_pctl_get_groups_count(struct pinctrl_dev *pctldev) 1284 { 1285 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1286 1287 return info->desc->npins; 1288 } 1289 1290 static const char *ocelot_pctl_get_group_name(struct pinctrl_dev *pctldev, 1291 unsigned int group) 1292 { 1293 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1294 1295 return info->desc->pins[group].name; 1296 } 1297 1298 static int ocelot_pctl_get_group_pins(struct pinctrl_dev *pctldev, 1299 unsigned int group, 1300 const unsigned int **pins, 1301 unsigned int *num_pins) 1302 { 1303 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1304 1305 *pins = &info->desc->pins[group].number; 1306 *num_pins = 1; 1307 1308 return 0; 1309 } 1310 1311 static int ocelot_hw_get_value(struct ocelot_pinctrl *info, 1312 unsigned int pin, 1313 unsigned int reg, 1314 int *val) 1315 { 1316 int ret = -EOPNOTSUPP; 1317 1318 if (info->pincfg) { 1319 u32 regcfg; 1320 1321 ret = regmap_read(info->pincfg, pin, ®cfg); 1322 if (ret) 1323 return ret; 1324 1325 ret = 0; 1326 switch (reg) { 1327 case PINCONF_BIAS: 1328 *val = regcfg & BIAS_BITS; 1329 break; 1330 1331 case PINCONF_SCHMITT: 1332 *val = regcfg & SCHMITT_BIT; 1333 break; 1334 1335 case PINCONF_DRIVE_STRENGTH: 1336 *val = regcfg & DRIVE_BITS; 1337 break; 1338 1339 default: 1340 ret = -EOPNOTSUPP; 1341 break; 1342 } 1343 } 1344 return ret; 1345 } 1346 1347 static int ocelot_pincfg_clrsetbits(struct ocelot_pinctrl *info, u32 regaddr, 1348 u32 clrbits, u32 setbits) 1349 { 1350 u32 val; 1351 int ret; 1352 1353 ret = regmap_read(info->pincfg, regaddr, &val); 1354 if (ret) 1355 return ret; 1356 1357 val &= ~clrbits; 1358 val |= setbits; 1359 1360 ret = regmap_write(info->pincfg, regaddr, val); 1361 1362 return ret; 1363 } 1364 1365 static int ocelot_hw_set_value(struct ocelot_pinctrl *info, 1366 unsigned int pin, 1367 unsigned int reg, 1368 int val) 1369 { 1370 int ret = -EOPNOTSUPP; 1371 1372 if (info->pincfg) { 1373 1374 ret = 0; 1375 switch (reg) { 1376 case PINCONF_BIAS: 1377 ret = ocelot_pincfg_clrsetbits(info, pin, BIAS_BITS, 1378 val); 1379 break; 1380 1381 case PINCONF_SCHMITT: 1382 ret = ocelot_pincfg_clrsetbits(info, pin, SCHMITT_BIT, 1383 val); 1384 break; 1385 1386 case PINCONF_DRIVE_STRENGTH: 1387 if (val <= 3) 1388 ret = ocelot_pincfg_clrsetbits(info, pin, 1389 DRIVE_BITS, val); 1390 else 1391 ret = -EINVAL; 1392 break; 1393 1394 default: 1395 ret = -EOPNOTSUPP; 1396 break; 1397 } 1398 } 1399 return ret; 1400 } 1401 1402 static int ocelot_pinconf_get(struct pinctrl_dev *pctldev, 1403 unsigned int pin, unsigned long *config) 1404 { 1405 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1406 u32 param = pinconf_to_config_param(*config); 1407 int val, err; 1408 1409 switch (param) { 1410 case PIN_CONFIG_BIAS_DISABLE: 1411 case PIN_CONFIG_BIAS_PULL_UP: 1412 case PIN_CONFIG_BIAS_PULL_DOWN: 1413 err = ocelot_hw_get_value(info, pin, PINCONF_BIAS, &val); 1414 if (err) 1415 return err; 1416 if (param == PIN_CONFIG_BIAS_DISABLE) 1417 val = (val == 0); 1418 else if (param == PIN_CONFIG_BIAS_PULL_DOWN) 1419 val = (val & BIAS_PD_BIT ? true : false); 1420 else /* PIN_CONFIG_BIAS_PULL_UP */ 1421 val = (val & BIAS_PU_BIT ? true : false); 1422 break; 1423 1424 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 1425 err = ocelot_hw_get_value(info, pin, PINCONF_SCHMITT, &val); 1426 if (err) 1427 return err; 1428 1429 val = (val & SCHMITT_BIT ? true : false); 1430 break; 1431 1432 case PIN_CONFIG_DRIVE_STRENGTH: 1433 err = ocelot_hw_get_value(info, pin, PINCONF_DRIVE_STRENGTH, 1434 &val); 1435 if (err) 1436 return err; 1437 break; 1438 1439 case PIN_CONFIG_OUTPUT: 1440 err = regmap_read(info->map, REG(OCELOT_GPIO_OUT, info, pin), 1441 &val); 1442 if (err) 1443 return err; 1444 val = !!(val & BIT(pin % 32)); 1445 break; 1446 1447 case PIN_CONFIG_INPUT_ENABLE: 1448 case PIN_CONFIG_OUTPUT_ENABLE: 1449 err = regmap_read(info->map, REG(OCELOT_GPIO_OE, info, pin), 1450 &val); 1451 if (err) 1452 return err; 1453 val = val & BIT(pin % 32); 1454 if (param == PIN_CONFIG_OUTPUT_ENABLE) 1455 val = !!val; 1456 else 1457 val = !val; 1458 break; 1459 1460 default: 1461 return -EOPNOTSUPP; 1462 } 1463 1464 *config = pinconf_to_config_packed(param, val); 1465 1466 return 0; 1467 } 1468 1469 static int ocelot_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 1470 unsigned long *configs, unsigned int num_configs) 1471 { 1472 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1473 u32 param, arg, p; 1474 int cfg, err = 0; 1475 1476 for (cfg = 0; cfg < num_configs; cfg++) { 1477 param = pinconf_to_config_param(configs[cfg]); 1478 arg = pinconf_to_config_argument(configs[cfg]); 1479 1480 switch (param) { 1481 case PIN_CONFIG_BIAS_DISABLE: 1482 case PIN_CONFIG_BIAS_PULL_UP: 1483 case PIN_CONFIG_BIAS_PULL_DOWN: 1484 arg = (param == PIN_CONFIG_BIAS_DISABLE) ? 0 : 1485 (param == PIN_CONFIG_BIAS_PULL_UP) ? BIAS_PU_BIT : 1486 BIAS_PD_BIT; 1487 1488 err = ocelot_hw_set_value(info, pin, PINCONF_BIAS, arg); 1489 if (err) 1490 goto err; 1491 1492 break; 1493 1494 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 1495 arg = arg ? SCHMITT_BIT : 0; 1496 err = ocelot_hw_set_value(info, pin, PINCONF_SCHMITT, 1497 arg); 1498 if (err) 1499 goto err; 1500 1501 break; 1502 1503 case PIN_CONFIG_DRIVE_STRENGTH: 1504 err = ocelot_hw_set_value(info, pin, 1505 PINCONF_DRIVE_STRENGTH, 1506 arg); 1507 if (err) 1508 goto err; 1509 1510 break; 1511 1512 case PIN_CONFIG_OUTPUT_ENABLE: 1513 case PIN_CONFIG_INPUT_ENABLE: 1514 case PIN_CONFIG_OUTPUT: 1515 p = pin % 32; 1516 if (arg) 1517 regmap_write(info->map, 1518 REG(OCELOT_GPIO_OUT_SET, info, 1519 pin), 1520 BIT(p)); 1521 else 1522 regmap_write(info->map, 1523 REG(OCELOT_GPIO_OUT_CLR, info, 1524 pin), 1525 BIT(p)); 1526 regmap_update_bits(info->map, 1527 REG(OCELOT_GPIO_OE, info, pin), 1528 BIT(p), 1529 param == PIN_CONFIG_INPUT_ENABLE ? 1530 0 : BIT(p)); 1531 break; 1532 1533 default: 1534 err = -EOPNOTSUPP; 1535 } 1536 } 1537 err: 1538 return err; 1539 } 1540 1541 static const struct pinconf_ops ocelot_confops = { 1542 .is_generic = true, 1543 .pin_config_get = ocelot_pinconf_get, 1544 .pin_config_set = ocelot_pinconf_set, 1545 .pin_config_config_dbg_show = pinconf_generic_dump_config, 1546 }; 1547 1548 static const struct pinctrl_ops ocelot_pctl_ops = { 1549 .get_groups_count = ocelot_pctl_get_groups_count, 1550 .get_group_name = ocelot_pctl_get_group_name, 1551 .get_group_pins = ocelot_pctl_get_group_pins, 1552 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, 1553 .dt_free_map = pinconf_generic_dt_free_map, 1554 }; 1555 1556 static struct pinctrl_desc luton_desc = { 1557 .name = "luton-pinctrl", 1558 .pins = luton_pins, 1559 .npins = ARRAY_SIZE(luton_pins), 1560 .pctlops = &ocelot_pctl_ops, 1561 .pmxops = &ocelot_pmx_ops, 1562 .owner = THIS_MODULE, 1563 }; 1564 1565 static struct pinctrl_desc serval_desc = { 1566 .name = "serval-pinctrl", 1567 .pins = serval_pins, 1568 .npins = ARRAY_SIZE(serval_pins), 1569 .pctlops = &ocelot_pctl_ops, 1570 .pmxops = &ocelot_pmx_ops, 1571 .owner = THIS_MODULE, 1572 }; 1573 1574 static struct pinctrl_desc ocelot_desc = { 1575 .name = "ocelot-pinctrl", 1576 .pins = ocelot_pins, 1577 .npins = ARRAY_SIZE(ocelot_pins), 1578 .pctlops = &ocelot_pctl_ops, 1579 .pmxops = &ocelot_pmx_ops, 1580 .owner = THIS_MODULE, 1581 }; 1582 1583 static struct pinctrl_desc jaguar2_desc = { 1584 .name = "jaguar2-pinctrl", 1585 .pins = jaguar2_pins, 1586 .npins = ARRAY_SIZE(jaguar2_pins), 1587 .pctlops = &ocelot_pctl_ops, 1588 .pmxops = &ocelot_pmx_ops, 1589 .owner = THIS_MODULE, 1590 }; 1591 1592 static struct pinctrl_desc servalt_desc = { 1593 .name = "servalt-pinctrl", 1594 .pins = servalt_pins, 1595 .npins = ARRAY_SIZE(servalt_pins), 1596 .pctlops = &ocelot_pctl_ops, 1597 .pmxops = &ocelot_pmx_ops, 1598 .owner = THIS_MODULE, 1599 }; 1600 1601 static struct pinctrl_desc sparx5_desc = { 1602 .name = "sparx5-pinctrl", 1603 .pins = sparx5_pins, 1604 .npins = ARRAY_SIZE(sparx5_pins), 1605 .pctlops = &ocelot_pctl_ops, 1606 .pmxops = &ocelot_pmx_ops, 1607 .confops = &ocelot_confops, 1608 .owner = THIS_MODULE, 1609 }; 1610 1611 static struct pinctrl_desc lan966x_desc = { 1612 .name = "lan966x-pinctrl", 1613 .pins = lan966x_pins, 1614 .npins = ARRAY_SIZE(lan966x_pins), 1615 .pctlops = &ocelot_pctl_ops, 1616 .pmxops = &lan966x_pmx_ops, 1617 .confops = &ocelot_confops, 1618 .owner = THIS_MODULE, 1619 }; 1620 1621 static int ocelot_create_group_func_map(struct device *dev, 1622 struct ocelot_pinctrl *info) 1623 { 1624 int f, npins, i; 1625 u8 *pins = kcalloc(info->desc->npins, sizeof(u8), GFP_KERNEL); 1626 1627 if (!pins) 1628 return -ENOMEM; 1629 1630 for (f = 0; f < FUNC_MAX; f++) { 1631 for (npins = 0, i = 0; i < info->desc->npins; i++) { 1632 if (ocelot_pin_function_idx(info, i, f) >= 0) 1633 pins[npins++] = i; 1634 } 1635 1636 if (!npins) 1637 continue; 1638 1639 info->func[f].ngroups = npins; 1640 info->func[f].groups = devm_kcalloc(dev, npins, sizeof(char *), 1641 GFP_KERNEL); 1642 if (!info->func[f].groups) { 1643 kfree(pins); 1644 return -ENOMEM; 1645 } 1646 1647 for (i = 0; i < npins; i++) 1648 info->func[f].groups[i] = 1649 info->desc->pins[pins[i]].name; 1650 } 1651 1652 kfree(pins); 1653 1654 return 0; 1655 } 1656 1657 static int ocelot_pinctrl_register(struct platform_device *pdev, 1658 struct ocelot_pinctrl *info) 1659 { 1660 int ret; 1661 1662 ret = ocelot_create_group_func_map(&pdev->dev, info); 1663 if (ret) { 1664 dev_err(&pdev->dev, "Unable to create group func map.\n"); 1665 return ret; 1666 } 1667 1668 info->pctl = devm_pinctrl_register(&pdev->dev, info->desc, info); 1669 if (IS_ERR(info->pctl)) { 1670 dev_err(&pdev->dev, "Failed to register pinctrl\n"); 1671 return PTR_ERR(info->pctl); 1672 } 1673 1674 return 0; 1675 } 1676 1677 static int ocelot_gpio_get(struct gpio_chip *chip, unsigned int offset) 1678 { 1679 struct ocelot_pinctrl *info = gpiochip_get_data(chip); 1680 unsigned int val; 1681 1682 regmap_read(info->map, REG(OCELOT_GPIO_IN, info, offset), &val); 1683 1684 return !!(val & BIT(offset % 32)); 1685 } 1686 1687 static void ocelot_gpio_set(struct gpio_chip *chip, unsigned int offset, 1688 int value) 1689 { 1690 struct ocelot_pinctrl *info = gpiochip_get_data(chip); 1691 1692 if (value) 1693 regmap_write(info->map, REG(OCELOT_GPIO_OUT_SET, info, offset), 1694 BIT(offset % 32)); 1695 else 1696 regmap_write(info->map, REG(OCELOT_GPIO_OUT_CLR, info, offset), 1697 BIT(offset % 32)); 1698 } 1699 1700 static int ocelot_gpio_get_direction(struct gpio_chip *chip, 1701 unsigned int offset) 1702 { 1703 struct ocelot_pinctrl *info = gpiochip_get_data(chip); 1704 unsigned int val; 1705 1706 regmap_read(info->map, REG(OCELOT_GPIO_OE, info, offset), &val); 1707 1708 if (val & BIT(offset % 32)) 1709 return GPIO_LINE_DIRECTION_OUT; 1710 1711 return GPIO_LINE_DIRECTION_IN; 1712 } 1713 1714 static int ocelot_gpio_direction_input(struct gpio_chip *chip, 1715 unsigned int offset) 1716 { 1717 return pinctrl_gpio_direction_input(chip->base + offset); 1718 } 1719 1720 static int ocelot_gpio_direction_output(struct gpio_chip *chip, 1721 unsigned int offset, int value) 1722 { 1723 struct ocelot_pinctrl *info = gpiochip_get_data(chip); 1724 unsigned int pin = BIT(offset % 32); 1725 1726 if (value) 1727 regmap_write(info->map, REG(OCELOT_GPIO_OUT_SET, info, offset), 1728 pin); 1729 else 1730 regmap_write(info->map, REG(OCELOT_GPIO_OUT_CLR, info, offset), 1731 pin); 1732 1733 return pinctrl_gpio_direction_output(chip->base + offset); 1734 } 1735 1736 static const struct gpio_chip ocelot_gpiolib_chip = { 1737 .request = gpiochip_generic_request, 1738 .free = gpiochip_generic_free, 1739 .set = ocelot_gpio_set, 1740 .get = ocelot_gpio_get, 1741 .get_direction = ocelot_gpio_get_direction, 1742 .direction_input = ocelot_gpio_direction_input, 1743 .direction_output = ocelot_gpio_direction_output, 1744 .owner = THIS_MODULE, 1745 }; 1746 1747 static void ocelot_irq_mask(struct irq_data *data) 1748 { 1749 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 1750 struct ocelot_pinctrl *info = gpiochip_get_data(chip); 1751 unsigned int gpio = irqd_to_hwirq(data); 1752 1753 regmap_update_bits(info->map, REG(OCELOT_GPIO_INTR_ENA, info, gpio), 1754 BIT(gpio % 32), 0); 1755 } 1756 1757 static void ocelot_irq_unmask(struct irq_data *data) 1758 { 1759 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 1760 struct ocelot_pinctrl *info = gpiochip_get_data(chip); 1761 unsigned int gpio = irqd_to_hwirq(data); 1762 1763 regmap_update_bits(info->map, REG(OCELOT_GPIO_INTR_ENA, info, gpio), 1764 BIT(gpio % 32), BIT(gpio % 32)); 1765 } 1766 1767 static void ocelot_irq_ack(struct irq_data *data) 1768 { 1769 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 1770 struct ocelot_pinctrl *info = gpiochip_get_data(chip); 1771 unsigned int gpio = irqd_to_hwirq(data); 1772 1773 regmap_write_bits(info->map, REG(OCELOT_GPIO_INTR, info, gpio), 1774 BIT(gpio % 32), BIT(gpio % 32)); 1775 } 1776 1777 static int ocelot_irq_set_type(struct irq_data *data, unsigned int type); 1778 1779 static struct irq_chip ocelot_eoi_irqchip = { 1780 .name = "gpio", 1781 .irq_mask = ocelot_irq_mask, 1782 .irq_eoi = ocelot_irq_ack, 1783 .irq_unmask = ocelot_irq_unmask, 1784 .flags = IRQCHIP_EOI_THREADED | IRQCHIP_EOI_IF_HANDLED, 1785 .irq_set_type = ocelot_irq_set_type, 1786 }; 1787 1788 static struct irq_chip ocelot_irqchip = { 1789 .name = "gpio", 1790 .irq_mask = ocelot_irq_mask, 1791 .irq_ack = ocelot_irq_ack, 1792 .irq_unmask = ocelot_irq_unmask, 1793 .irq_set_type = ocelot_irq_set_type, 1794 }; 1795 1796 static int ocelot_irq_set_type(struct irq_data *data, unsigned int type) 1797 { 1798 type &= IRQ_TYPE_SENSE_MASK; 1799 1800 if (!(type & (IRQ_TYPE_EDGE_BOTH | IRQ_TYPE_LEVEL_HIGH))) 1801 return -EINVAL; 1802 1803 if (type & IRQ_TYPE_LEVEL_HIGH) 1804 irq_set_chip_handler_name_locked(data, &ocelot_eoi_irqchip, 1805 handle_fasteoi_irq, NULL); 1806 if (type & IRQ_TYPE_EDGE_BOTH) 1807 irq_set_chip_handler_name_locked(data, &ocelot_irqchip, 1808 handle_edge_irq, NULL); 1809 1810 return 0; 1811 } 1812 1813 static void ocelot_irq_handler(struct irq_desc *desc) 1814 { 1815 struct irq_chip *parent_chip = irq_desc_get_chip(desc); 1816 struct gpio_chip *chip = irq_desc_get_handler_data(desc); 1817 struct ocelot_pinctrl *info = gpiochip_get_data(chip); 1818 unsigned int id_reg = OCELOT_GPIO_INTR_IDENT * info->stride; 1819 unsigned int reg = 0, irq, i; 1820 unsigned long irqs; 1821 1822 for (i = 0; i < info->stride; i++) { 1823 regmap_read(info->map, id_reg + 4 * i, ®); 1824 if (!reg) 1825 continue; 1826 1827 chained_irq_enter(parent_chip, desc); 1828 1829 irqs = reg; 1830 1831 for_each_set_bit(irq, &irqs, 1832 min(32U, info->desc->npins - 32 * i)) 1833 generic_handle_domain_irq(chip->irq.domain, irq + 32 * i); 1834 1835 chained_irq_exit(parent_chip, desc); 1836 } 1837 } 1838 1839 static int ocelot_gpiochip_register(struct platform_device *pdev, 1840 struct ocelot_pinctrl *info) 1841 { 1842 struct gpio_chip *gc; 1843 struct gpio_irq_chip *girq; 1844 int irq; 1845 1846 info->gpio_chip = ocelot_gpiolib_chip; 1847 1848 gc = &info->gpio_chip; 1849 gc->ngpio = info->desc->npins; 1850 gc->parent = &pdev->dev; 1851 gc->base = -1; 1852 gc->label = "ocelot-gpio"; 1853 1854 irq = platform_get_irq_optional(pdev, 0); 1855 if (irq > 0) { 1856 girq = &gc->irq; 1857 girq->chip = &ocelot_irqchip; 1858 girq->parent_handler = ocelot_irq_handler; 1859 girq->num_parents = 1; 1860 girq->parents = devm_kcalloc(&pdev->dev, 1, 1861 sizeof(*girq->parents), 1862 GFP_KERNEL); 1863 if (!girq->parents) 1864 return -ENOMEM; 1865 girq->parents[0] = irq; 1866 girq->default_type = IRQ_TYPE_NONE; 1867 girq->handler = handle_edge_irq; 1868 } 1869 1870 return devm_gpiochip_add_data(&pdev->dev, gc, info); 1871 } 1872 1873 static const struct of_device_id ocelot_pinctrl_of_match[] = { 1874 { .compatible = "mscc,luton-pinctrl", .data = &luton_desc }, 1875 { .compatible = "mscc,serval-pinctrl", .data = &serval_desc }, 1876 { .compatible = "mscc,ocelot-pinctrl", .data = &ocelot_desc }, 1877 { .compatible = "mscc,jaguar2-pinctrl", .data = &jaguar2_desc }, 1878 { .compatible = "mscc,servalt-pinctrl", .data = &servalt_desc }, 1879 { .compatible = "microchip,sparx5-pinctrl", .data = &sparx5_desc }, 1880 { .compatible = "microchip,lan966x-pinctrl", .data = &lan966x_desc }, 1881 {}, 1882 }; 1883 1884 static struct regmap *ocelot_pinctrl_create_pincfg(struct platform_device *pdev) 1885 { 1886 void __iomem *base; 1887 1888 const struct regmap_config regmap_config = { 1889 .reg_bits = 32, 1890 .val_bits = 32, 1891 .reg_stride = 4, 1892 .max_register = 32, 1893 .name = "pincfg", 1894 }; 1895 1896 base = devm_platform_ioremap_resource(pdev, 1); 1897 if (IS_ERR(base)) { 1898 dev_dbg(&pdev->dev, "Failed to ioremap config registers (no extended pinconf)\n"); 1899 return NULL; 1900 } 1901 1902 return devm_regmap_init_mmio(&pdev->dev, base, ®map_config); 1903 } 1904 1905 static int ocelot_pinctrl_probe(struct platform_device *pdev) 1906 { 1907 struct device *dev = &pdev->dev; 1908 struct ocelot_pinctrl *info; 1909 struct regmap *pincfg; 1910 void __iomem *base; 1911 int ret; 1912 struct regmap_config regmap_config = { 1913 .reg_bits = 32, 1914 .val_bits = 32, 1915 .reg_stride = 4, 1916 }; 1917 1918 info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL); 1919 if (!info) 1920 return -ENOMEM; 1921 1922 info->desc = (struct pinctrl_desc *)device_get_match_data(dev); 1923 1924 base = devm_ioremap_resource(dev, 1925 platform_get_resource(pdev, IORESOURCE_MEM, 0)); 1926 if (IS_ERR(base)) 1927 return PTR_ERR(base); 1928 1929 info->stride = 1 + (info->desc->npins - 1) / 32; 1930 1931 regmap_config.max_register = OCELOT_GPIO_SD_MAP * info->stride + 15 * 4; 1932 1933 info->map = devm_regmap_init_mmio(dev, base, ®map_config); 1934 if (IS_ERR(info->map)) { 1935 dev_err(dev, "Failed to create regmap\n"); 1936 return PTR_ERR(info->map); 1937 } 1938 dev_set_drvdata(dev, info->map); 1939 info->dev = dev; 1940 1941 /* Pinconf registers */ 1942 if (info->desc->confops) { 1943 pincfg = ocelot_pinctrl_create_pincfg(pdev); 1944 if (IS_ERR(pincfg)) 1945 dev_dbg(dev, "Failed to create pincfg regmap\n"); 1946 else 1947 info->pincfg = pincfg; 1948 } 1949 1950 ret = ocelot_pinctrl_register(pdev, info); 1951 if (ret) 1952 return ret; 1953 1954 ret = ocelot_gpiochip_register(pdev, info); 1955 if (ret) 1956 return ret; 1957 1958 dev_info(dev, "driver registered\n"); 1959 1960 return 0; 1961 } 1962 1963 static struct platform_driver ocelot_pinctrl_driver = { 1964 .driver = { 1965 .name = "pinctrl-ocelot", 1966 .of_match_table = of_match_ptr(ocelot_pinctrl_of_match), 1967 .suppress_bind_attrs = true, 1968 }, 1969 .probe = ocelot_pinctrl_probe, 1970 }; 1971 builtin_platform_driver(ocelot_pinctrl_driver); 1972