1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /*
3  * Microsemi SoCs pinctrl driver
4  *
5  * Author: <alexandre.belloni@free-electrons.com>
6  * License: Dual MIT/GPL
7  * Copyright (c) 2017 Microsemi Corporation
8  */
9 
10 #include <linux/gpio/driver.h>
11 #include <linux/interrupt.h>
12 #include <linux/io.h>
13 #include <linux/of_device.h>
14 #include <linux/of_irq.h>
15 #include <linux/of_platform.h>
16 #include <linux/pinctrl/pinctrl.h>
17 #include <linux/pinctrl/pinmux.h>
18 #include <linux/pinctrl/pinconf.h>
19 #include <linux/pinctrl/pinconf-generic.h>
20 #include <linux/platform_device.h>
21 #include <linux/regmap.h>
22 #include <linux/slab.h>
23 
24 #include "core.h"
25 #include "pinconf.h"
26 #include "pinmux.h"
27 
28 #define ocelot_clrsetbits(addr, clear, set) \
29 	writel((readl(addr) & ~(clear)) | (set), (addr))
30 
31 /* PINCONFIG bits (sparx5 only) */
32 enum {
33 	PINCONF_BIAS,
34 	PINCONF_SCHMITT,
35 	PINCONF_DRIVE_STRENGTH,
36 };
37 
38 #define BIAS_PD_BIT BIT(4)
39 #define BIAS_PU_BIT BIT(3)
40 #define BIAS_BITS   (BIAS_PD_BIT|BIAS_PU_BIT)
41 #define SCHMITT_BIT BIT(2)
42 #define DRIVE_BITS  GENMASK(1, 0)
43 
44 /* GPIO standard registers */
45 #define OCELOT_GPIO_OUT_SET	0x0
46 #define OCELOT_GPIO_OUT_CLR	0x4
47 #define OCELOT_GPIO_OUT		0x8
48 #define OCELOT_GPIO_IN		0xc
49 #define OCELOT_GPIO_OE		0x10
50 #define OCELOT_GPIO_INTR	0x14
51 #define OCELOT_GPIO_INTR_ENA	0x18
52 #define OCELOT_GPIO_INTR_IDENT	0x1c
53 #define OCELOT_GPIO_ALT0	0x20
54 #define OCELOT_GPIO_ALT1	0x24
55 #define OCELOT_GPIO_SD_MAP	0x28
56 
57 #define OCELOT_FUNC_PER_PIN	4
58 
59 enum {
60 	FUNC_CAN0_a,
61 	FUNC_CAN0_b,
62 	FUNC_CAN1,
63 	FUNC_NONE,
64 	FUNC_FC0_a,
65 	FUNC_FC0_b,
66 	FUNC_FC0_c,
67 	FUNC_FC1_a,
68 	FUNC_FC1_b,
69 	FUNC_FC1_c,
70 	FUNC_FC2_a,
71 	FUNC_FC2_b,
72 	FUNC_FC3_a,
73 	FUNC_FC3_b,
74 	FUNC_FC3_c,
75 	FUNC_FC4_a,
76 	FUNC_FC4_b,
77 	FUNC_FC4_c,
78 	FUNC_FC_SHRD0,
79 	FUNC_FC_SHRD1,
80 	FUNC_FC_SHRD2,
81 	FUNC_FC_SHRD3,
82 	FUNC_FC_SHRD4,
83 	FUNC_FC_SHRD5,
84 	FUNC_FC_SHRD6,
85 	FUNC_FC_SHRD7,
86 	FUNC_FC_SHRD8,
87 	FUNC_FC_SHRD9,
88 	FUNC_FC_SHRD10,
89 	FUNC_FC_SHRD11,
90 	FUNC_FC_SHRD12,
91 	FUNC_FC_SHRD13,
92 	FUNC_FC_SHRD14,
93 	FUNC_FC_SHRD15,
94 	FUNC_FC_SHRD16,
95 	FUNC_FC_SHRD17,
96 	FUNC_FC_SHRD18,
97 	FUNC_FC_SHRD19,
98 	FUNC_FC_SHRD20,
99 	FUNC_GPIO,
100 	FUNC_IB_TRG_a,
101 	FUNC_IB_TRG_b,
102 	FUNC_IB_TRG_c,
103 	FUNC_IRQ0,
104 	FUNC_IRQ_IN_a,
105 	FUNC_IRQ_IN_b,
106 	FUNC_IRQ_IN_c,
107 	FUNC_IRQ0_IN,
108 	FUNC_IRQ_OUT_a,
109 	FUNC_IRQ_OUT_b,
110 	FUNC_IRQ_OUT_c,
111 	FUNC_IRQ0_OUT,
112 	FUNC_IRQ1,
113 	FUNC_IRQ1_IN,
114 	FUNC_IRQ1_OUT,
115 	FUNC_EXT_IRQ,
116 	FUNC_MIIM,
117 	FUNC_MIIM_a,
118 	FUNC_MIIM_b,
119 	FUNC_MIIM_c,
120 	FUNC_MIIM_Sa,
121 	FUNC_MIIM_Sb,
122 	FUNC_OB_TRG,
123 	FUNC_OB_TRG_a,
124 	FUNC_OB_TRG_b,
125 	FUNC_PHY_LED,
126 	FUNC_PCI_WAKE,
127 	FUNC_MD,
128 	FUNC_PTP0,
129 	FUNC_PTP1,
130 	FUNC_PTP2,
131 	FUNC_PTP3,
132 	FUNC_PTPSYNC_0,
133 	FUNC_PTPSYNC_1,
134 	FUNC_PTPSYNC_2,
135 	FUNC_PTPSYNC_3,
136 	FUNC_PTPSYNC_4,
137 	FUNC_PTPSYNC_5,
138 	FUNC_PTPSYNC_6,
139 	FUNC_PTPSYNC_7,
140 	FUNC_PWM,
141 	FUNC_QSPI1,
142 	FUNC_QSPI2,
143 	FUNC_R,
144 	FUNC_RECO_a,
145 	FUNC_RECO_b,
146 	FUNC_RECO_CLK,
147 	FUNC_SD,
148 	FUNC_SFP,
149 	FUNC_SFP_SD,
150 	FUNC_SG0,
151 	FUNC_SG1,
152 	FUNC_SG2,
153 	FUNC_SGPIO_a,
154 	FUNC_SGPIO_b,
155 	FUNC_SI,
156 	FUNC_SI2,
157 	FUNC_TACHO,
158 	FUNC_TACHO_a,
159 	FUNC_TACHO_b,
160 	FUNC_TWI,
161 	FUNC_TWI2,
162 	FUNC_TWI3,
163 	FUNC_TWI_SCL_M,
164 	FUNC_TWI_SLC_GATE,
165 	FUNC_TWI_SLC_GATE_AD,
166 	FUNC_UART,
167 	FUNC_UART2,
168 	FUNC_UART3,
169 	FUNC_USB_H_a,
170 	FUNC_USB_H_b,
171 	FUNC_USB_H_c,
172 	FUNC_USB_S_a,
173 	FUNC_USB_S_b,
174 	FUNC_USB_S_c,
175 	FUNC_PLL_STAT,
176 	FUNC_EMMC,
177 	FUNC_EMMC_SD,
178 	FUNC_REF_CLK,
179 	FUNC_RCVRD_CLK,
180 	FUNC_MAX
181 };
182 
183 static const char *const ocelot_function_names[] = {
184 	[FUNC_CAN0_a]		= "can0_a",
185 	[FUNC_CAN0_b]		= "can0_b",
186 	[FUNC_CAN1]		= "can1",
187 	[FUNC_NONE]		= "none",
188 	[FUNC_FC0_a]		= "fc0_a",
189 	[FUNC_FC0_b]		= "fc0_b",
190 	[FUNC_FC0_c]		= "fc0_c",
191 	[FUNC_FC1_a]		= "fc1_a",
192 	[FUNC_FC1_b]		= "fc1_b",
193 	[FUNC_FC1_c]		= "fc1_c",
194 	[FUNC_FC2_a]		= "fc2_a",
195 	[FUNC_FC2_b]		= "fc2_b",
196 	[FUNC_FC3_a]		= "fc3_a",
197 	[FUNC_FC3_b]		= "fc3_b",
198 	[FUNC_FC3_c]		= "fc3_c",
199 	[FUNC_FC4_a]		= "fc4_a",
200 	[FUNC_FC4_b]		= "fc4_b",
201 	[FUNC_FC4_c]		= "fc4_c",
202 	[FUNC_FC_SHRD0]		= "fc_shrd0",
203 	[FUNC_FC_SHRD1]		= "fc_shrd1",
204 	[FUNC_FC_SHRD2]		= "fc_shrd2",
205 	[FUNC_FC_SHRD3]		= "fc_shrd3",
206 	[FUNC_FC_SHRD4]		= "fc_shrd4",
207 	[FUNC_FC_SHRD5]		= "fc_shrd5",
208 	[FUNC_FC_SHRD6]		= "fc_shrd6",
209 	[FUNC_FC_SHRD7]		= "fc_shrd7",
210 	[FUNC_FC_SHRD8]		= "fc_shrd8",
211 	[FUNC_FC_SHRD9]		= "fc_shrd9",
212 	[FUNC_FC_SHRD10]	= "fc_shrd10",
213 	[FUNC_FC_SHRD11]	= "fc_shrd11",
214 	[FUNC_FC_SHRD12]	= "fc_shrd12",
215 	[FUNC_FC_SHRD13]	= "fc_shrd13",
216 	[FUNC_FC_SHRD14]	= "fc_shrd14",
217 	[FUNC_FC_SHRD15]	= "fc_shrd15",
218 	[FUNC_FC_SHRD16]	= "fc_shrd16",
219 	[FUNC_FC_SHRD17]	= "fc_shrd17",
220 	[FUNC_FC_SHRD18]	= "fc_shrd18",
221 	[FUNC_FC_SHRD19]	= "fc_shrd19",
222 	[FUNC_FC_SHRD20]	= "fc_shrd20",
223 	[FUNC_GPIO]		= "gpio",
224 	[FUNC_IB_TRG_a]		= "ib_trig_a",
225 	[FUNC_IB_TRG_b]		= "ib_trig_b",
226 	[FUNC_IB_TRG_c]		= "ib_trig_c",
227 	[FUNC_IRQ0]		= "irq0",
228 	[FUNC_IRQ_IN_a]		= "irq_in_a",
229 	[FUNC_IRQ_IN_b]		= "irq_in_b",
230 	[FUNC_IRQ_IN_c]		= "irq_in_c",
231 	[FUNC_IRQ0_IN]		= "irq0_in",
232 	[FUNC_IRQ_OUT_a]	= "irq_out_a",
233 	[FUNC_IRQ_OUT_b]	= "irq_out_b",
234 	[FUNC_IRQ_OUT_c]	= "irq_out_c",
235 	[FUNC_IRQ0_OUT]		= "irq0_out",
236 	[FUNC_IRQ1]		= "irq1",
237 	[FUNC_IRQ1_IN]		= "irq1_in",
238 	[FUNC_IRQ1_OUT]		= "irq1_out",
239 	[FUNC_EXT_IRQ]		= "ext_irq",
240 	[FUNC_MIIM]		= "miim",
241 	[FUNC_MIIM_a]		= "miim_a",
242 	[FUNC_MIIM_b]		= "miim_b",
243 	[FUNC_MIIM_c]		= "miim_c",
244 	[FUNC_MIIM_Sa]		= "miim_slave_a",
245 	[FUNC_MIIM_Sb]		= "miim_slave_b",
246 	[FUNC_PHY_LED]		= "phy_led",
247 	[FUNC_PCI_WAKE]		= "pci_wake",
248 	[FUNC_MD]		= "md",
249 	[FUNC_OB_TRG]		= "ob_trig",
250 	[FUNC_OB_TRG_a]		= "ob_trig_a",
251 	[FUNC_OB_TRG_b]		= "ob_trig_b",
252 	[FUNC_PTP0]		= "ptp0",
253 	[FUNC_PTP1]		= "ptp1",
254 	[FUNC_PTP2]		= "ptp2",
255 	[FUNC_PTP3]		= "ptp3",
256 	[FUNC_PTPSYNC_0]	= "ptpsync_0",
257 	[FUNC_PTPSYNC_1]	= "ptpsync_1",
258 	[FUNC_PTPSYNC_2]	= "ptpsync_2",
259 	[FUNC_PTPSYNC_3]	= "ptpsync_3",
260 	[FUNC_PTPSYNC_4]	= "ptpsync_4",
261 	[FUNC_PTPSYNC_5]	= "ptpsync_5",
262 	[FUNC_PTPSYNC_6]	= "ptpsync_6",
263 	[FUNC_PTPSYNC_7]	= "ptpsync_7",
264 	[FUNC_PWM]		= "pwm",
265 	[FUNC_QSPI1]		= "qspi1",
266 	[FUNC_QSPI2]		= "qspi2",
267 	[FUNC_R]		= "reserved",
268 	[FUNC_RECO_a]		= "reco_a",
269 	[FUNC_RECO_b]		= "reco_b",
270 	[FUNC_RECO_CLK]		= "reco_clk",
271 	[FUNC_SD]		= "sd",
272 	[FUNC_SFP]		= "sfp",
273 	[FUNC_SFP_SD]		= "sfp_sd",
274 	[FUNC_SG0]		= "sg0",
275 	[FUNC_SG1]		= "sg1",
276 	[FUNC_SG2]		= "sg2",
277 	[FUNC_SGPIO_a]		= "sgpio_a",
278 	[FUNC_SGPIO_b]		= "sgpio_b",
279 	[FUNC_SI]		= "si",
280 	[FUNC_SI2]		= "si2",
281 	[FUNC_TACHO]		= "tacho",
282 	[FUNC_TACHO_a]		= "tacho_a",
283 	[FUNC_TACHO_b]		= "tacho_b",
284 	[FUNC_TWI]		= "twi",
285 	[FUNC_TWI2]		= "twi2",
286 	[FUNC_TWI3]		= "twi3",
287 	[FUNC_TWI_SCL_M]	= "twi_scl_m",
288 	[FUNC_TWI_SLC_GATE]	= "twi_slc_gate",
289 	[FUNC_TWI_SLC_GATE_AD]	= "twi_slc_gate_ad",
290 	[FUNC_USB_H_a]		= "usb_host_a",
291 	[FUNC_USB_H_b]		= "usb_host_b",
292 	[FUNC_USB_H_c]		= "usb_host_c",
293 	[FUNC_USB_S_a]		= "usb_slave_a",
294 	[FUNC_USB_S_b]		= "usb_slave_b",
295 	[FUNC_USB_S_c]		= "usb_slave_c",
296 	[FUNC_UART]		= "uart",
297 	[FUNC_UART2]		= "uart2",
298 	[FUNC_UART3]		= "uart3",
299 	[FUNC_PLL_STAT]		= "pll_stat",
300 	[FUNC_EMMC]		= "emmc",
301 	[FUNC_EMMC_SD]		= "emmc_sd",
302 	[FUNC_REF_CLK]		= "ref_clk",
303 	[FUNC_RCVRD_CLK]	= "rcvrd_clk",
304 };
305 
306 struct ocelot_pmx_func {
307 	const char **groups;
308 	unsigned int ngroups;
309 };
310 
311 struct ocelot_pin_caps {
312 	unsigned int pin;
313 	unsigned char functions[OCELOT_FUNC_PER_PIN];
314 	unsigned char a_functions[OCELOT_FUNC_PER_PIN];	/* Additional functions */
315 };
316 
317 struct ocelot_pinctrl {
318 	struct device *dev;
319 	struct pinctrl_dev *pctl;
320 	struct gpio_chip gpio_chip;
321 	struct regmap *map;
322 	struct regmap *pincfg;
323 	struct pinctrl_desc *desc;
324 	struct ocelot_pmx_func func[FUNC_MAX];
325 	u8 stride;
326 };
327 
328 #define LUTON_P(p, f0, f1)						\
329 static struct ocelot_pin_caps luton_pin_##p = {				\
330 	.pin = p,							\
331 	.functions = {							\
332 			FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_NONE,	\
333 	},								\
334 }
335 
336 LUTON_P(0,  SG0,       NONE);
337 LUTON_P(1,  SG0,       NONE);
338 LUTON_P(2,  SG0,       NONE);
339 LUTON_P(3,  SG0,       NONE);
340 LUTON_P(4,  TACHO,     NONE);
341 LUTON_P(5,  TWI,       PHY_LED);
342 LUTON_P(6,  TWI,       PHY_LED);
343 LUTON_P(7,  NONE,      PHY_LED);
344 LUTON_P(8,  EXT_IRQ,   PHY_LED);
345 LUTON_P(9,  EXT_IRQ,   PHY_LED);
346 LUTON_P(10, SFP,       PHY_LED);
347 LUTON_P(11, SFP,       PHY_LED);
348 LUTON_P(12, SFP,       PHY_LED);
349 LUTON_P(13, SFP,       PHY_LED);
350 LUTON_P(14, SI,        PHY_LED);
351 LUTON_P(15, SI,        PHY_LED);
352 LUTON_P(16, SI,        PHY_LED);
353 LUTON_P(17, SFP,       PHY_LED);
354 LUTON_P(18, SFP,       PHY_LED);
355 LUTON_P(19, SFP,       PHY_LED);
356 LUTON_P(20, SFP,       PHY_LED);
357 LUTON_P(21, SFP,       PHY_LED);
358 LUTON_P(22, SFP,       PHY_LED);
359 LUTON_P(23, SFP,       PHY_LED);
360 LUTON_P(24, SFP,       PHY_LED);
361 LUTON_P(25, SFP,       PHY_LED);
362 LUTON_P(26, SFP,       PHY_LED);
363 LUTON_P(27, SFP,       PHY_LED);
364 LUTON_P(28, SFP,       PHY_LED);
365 LUTON_P(29, PWM,       NONE);
366 LUTON_P(30, UART,      NONE);
367 LUTON_P(31, UART,      NONE);
368 
369 #define LUTON_PIN(n) {						\
370 	.number = n,						\
371 	.name = "GPIO_"#n,					\
372 	.drv_data = &luton_pin_##n				\
373 }
374 
375 static const struct pinctrl_pin_desc luton_pins[] = {
376 	LUTON_PIN(0),
377 	LUTON_PIN(1),
378 	LUTON_PIN(2),
379 	LUTON_PIN(3),
380 	LUTON_PIN(4),
381 	LUTON_PIN(5),
382 	LUTON_PIN(6),
383 	LUTON_PIN(7),
384 	LUTON_PIN(8),
385 	LUTON_PIN(9),
386 	LUTON_PIN(10),
387 	LUTON_PIN(11),
388 	LUTON_PIN(12),
389 	LUTON_PIN(13),
390 	LUTON_PIN(14),
391 	LUTON_PIN(15),
392 	LUTON_PIN(16),
393 	LUTON_PIN(17),
394 	LUTON_PIN(18),
395 	LUTON_PIN(19),
396 	LUTON_PIN(20),
397 	LUTON_PIN(21),
398 	LUTON_PIN(22),
399 	LUTON_PIN(23),
400 	LUTON_PIN(24),
401 	LUTON_PIN(25),
402 	LUTON_PIN(26),
403 	LUTON_PIN(27),
404 	LUTON_PIN(28),
405 	LUTON_PIN(29),
406 	LUTON_PIN(30),
407 	LUTON_PIN(31),
408 };
409 
410 #define SERVAL_P(p, f0, f1, f2)						\
411 static struct ocelot_pin_caps serval_pin_##p = {			\
412 	.pin = p,							\
413 	.functions = {							\
414 			FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2,	\
415 	},								\
416 }
417 
418 SERVAL_P(0,  SG0,       NONE,      NONE);
419 SERVAL_P(1,  SG0,       NONE,      NONE);
420 SERVAL_P(2,  SG0,       NONE,      NONE);
421 SERVAL_P(3,  SG0,       NONE,      NONE);
422 SERVAL_P(4,  TACHO,     NONE,      NONE);
423 SERVAL_P(5,  PWM,       NONE,      NONE);
424 SERVAL_P(6,  TWI,       NONE,      NONE);
425 SERVAL_P(7,  TWI,       NONE,      NONE);
426 SERVAL_P(8,  SI,        NONE,      NONE);
427 SERVAL_P(9,  SI,        MD,        NONE);
428 SERVAL_P(10, SI,        MD,        NONE);
429 SERVAL_P(11, SFP,       MD,        TWI_SCL_M);
430 SERVAL_P(12, SFP,       MD,        TWI_SCL_M);
431 SERVAL_P(13, SFP,       UART2,     TWI_SCL_M);
432 SERVAL_P(14, SFP,       UART2,     TWI_SCL_M);
433 SERVAL_P(15, SFP,       PTP0,      TWI_SCL_M);
434 SERVAL_P(16, SFP,       PTP0,      TWI_SCL_M);
435 SERVAL_P(17, SFP,       PCI_WAKE,  TWI_SCL_M);
436 SERVAL_P(18, SFP,       NONE,      TWI_SCL_M);
437 SERVAL_P(19, SFP,       NONE,      TWI_SCL_M);
438 SERVAL_P(20, SFP,       NONE,      TWI_SCL_M);
439 SERVAL_P(21, SFP,       NONE,      TWI_SCL_M);
440 SERVAL_P(22, NONE,      NONE,      NONE);
441 SERVAL_P(23, NONE,      NONE,      NONE);
442 SERVAL_P(24, NONE,      NONE,      NONE);
443 SERVAL_P(25, NONE,      NONE,      NONE);
444 SERVAL_P(26, UART,      NONE,      NONE);
445 SERVAL_P(27, UART,      NONE,      NONE);
446 SERVAL_P(28, IRQ0,      NONE,      NONE);
447 SERVAL_P(29, IRQ1,      NONE,      NONE);
448 SERVAL_P(30, PTP0,      NONE,      NONE);
449 SERVAL_P(31, PTP0,      NONE,      NONE);
450 
451 #define SERVAL_PIN(n) {						\
452 	.number = n,						\
453 	.name = "GPIO_"#n,					\
454 	.drv_data = &serval_pin_##n				\
455 }
456 
457 static const struct pinctrl_pin_desc serval_pins[] = {
458 	SERVAL_PIN(0),
459 	SERVAL_PIN(1),
460 	SERVAL_PIN(2),
461 	SERVAL_PIN(3),
462 	SERVAL_PIN(4),
463 	SERVAL_PIN(5),
464 	SERVAL_PIN(6),
465 	SERVAL_PIN(7),
466 	SERVAL_PIN(8),
467 	SERVAL_PIN(9),
468 	SERVAL_PIN(10),
469 	SERVAL_PIN(11),
470 	SERVAL_PIN(12),
471 	SERVAL_PIN(13),
472 	SERVAL_PIN(14),
473 	SERVAL_PIN(15),
474 	SERVAL_PIN(16),
475 	SERVAL_PIN(17),
476 	SERVAL_PIN(18),
477 	SERVAL_PIN(19),
478 	SERVAL_PIN(20),
479 	SERVAL_PIN(21),
480 	SERVAL_PIN(22),
481 	SERVAL_PIN(23),
482 	SERVAL_PIN(24),
483 	SERVAL_PIN(25),
484 	SERVAL_PIN(26),
485 	SERVAL_PIN(27),
486 	SERVAL_PIN(28),
487 	SERVAL_PIN(29),
488 	SERVAL_PIN(30),
489 	SERVAL_PIN(31),
490 };
491 
492 #define OCELOT_P(p, f0, f1, f2)						\
493 static struct ocelot_pin_caps ocelot_pin_##p = {			\
494 	.pin = p,							\
495 	.functions = {							\
496 			FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2,	\
497 	},								\
498 }
499 
500 OCELOT_P(0,  SG0,       NONE,      NONE);
501 OCELOT_P(1,  SG0,       NONE,      NONE);
502 OCELOT_P(2,  SG0,       NONE,      NONE);
503 OCELOT_P(3,  SG0,       NONE,      NONE);
504 OCELOT_P(4,  IRQ0_IN,   IRQ0_OUT,  TWI_SCL_M);
505 OCELOT_P(5,  IRQ1_IN,   IRQ1_OUT,  PCI_WAKE);
506 OCELOT_P(6,  UART,      TWI_SCL_M, NONE);
507 OCELOT_P(7,  UART,      TWI_SCL_M, NONE);
508 OCELOT_P(8,  SI,        TWI_SCL_M, IRQ0_OUT);
509 OCELOT_P(9,  SI,        TWI_SCL_M, IRQ1_OUT);
510 OCELOT_P(10, PTP2,      TWI_SCL_M, SFP);
511 OCELOT_P(11, PTP3,      TWI_SCL_M, SFP);
512 OCELOT_P(12, UART2,     TWI_SCL_M, SFP);
513 OCELOT_P(13, UART2,     TWI_SCL_M, SFP);
514 OCELOT_P(14, MIIM,      TWI_SCL_M, SFP);
515 OCELOT_P(15, MIIM,      TWI_SCL_M, SFP);
516 OCELOT_P(16, TWI,       NONE,      SI);
517 OCELOT_P(17, TWI,       TWI_SCL_M, SI);
518 OCELOT_P(18, PTP0,      TWI_SCL_M, NONE);
519 OCELOT_P(19, PTP1,      TWI_SCL_M, NONE);
520 OCELOT_P(20, RECO_CLK,  TACHO,     TWI_SCL_M);
521 OCELOT_P(21, RECO_CLK,  PWM,       TWI_SCL_M);
522 
523 #define OCELOT_PIN(n) {						\
524 	.number = n,						\
525 	.name = "GPIO_"#n,					\
526 	.drv_data = &ocelot_pin_##n				\
527 }
528 
529 static const struct pinctrl_pin_desc ocelot_pins[] = {
530 	OCELOT_PIN(0),
531 	OCELOT_PIN(1),
532 	OCELOT_PIN(2),
533 	OCELOT_PIN(3),
534 	OCELOT_PIN(4),
535 	OCELOT_PIN(5),
536 	OCELOT_PIN(6),
537 	OCELOT_PIN(7),
538 	OCELOT_PIN(8),
539 	OCELOT_PIN(9),
540 	OCELOT_PIN(10),
541 	OCELOT_PIN(11),
542 	OCELOT_PIN(12),
543 	OCELOT_PIN(13),
544 	OCELOT_PIN(14),
545 	OCELOT_PIN(15),
546 	OCELOT_PIN(16),
547 	OCELOT_PIN(17),
548 	OCELOT_PIN(18),
549 	OCELOT_PIN(19),
550 	OCELOT_PIN(20),
551 	OCELOT_PIN(21),
552 };
553 
554 #define JAGUAR2_P(p, f0, f1)						\
555 static struct ocelot_pin_caps jaguar2_pin_##p = {			\
556 	.pin = p,							\
557 	.functions = {							\
558 			FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_NONE	\
559 	},								\
560 }
561 
562 JAGUAR2_P(0,  SG0,       NONE);
563 JAGUAR2_P(1,  SG0,       NONE);
564 JAGUAR2_P(2,  SG0,       NONE);
565 JAGUAR2_P(3,  SG0,       NONE);
566 JAGUAR2_P(4,  SG1,       NONE);
567 JAGUAR2_P(5,  SG1,       NONE);
568 JAGUAR2_P(6,  IRQ0_IN,   IRQ0_OUT);
569 JAGUAR2_P(7,  IRQ1_IN,   IRQ1_OUT);
570 JAGUAR2_P(8,  PTP0,      NONE);
571 JAGUAR2_P(9,  PTP1,      NONE);
572 JAGUAR2_P(10, UART,      NONE);
573 JAGUAR2_P(11, UART,      NONE);
574 JAGUAR2_P(12, SG1,       NONE);
575 JAGUAR2_P(13, SG1,       NONE);
576 JAGUAR2_P(14, TWI,       TWI_SCL_M);
577 JAGUAR2_P(15, TWI,       NONE);
578 JAGUAR2_P(16, SI,        TWI_SCL_M);
579 JAGUAR2_P(17, SI,        TWI_SCL_M);
580 JAGUAR2_P(18, SI,        TWI_SCL_M);
581 JAGUAR2_P(19, PCI_WAKE,  NONE);
582 JAGUAR2_P(20, IRQ0_OUT,  TWI_SCL_M);
583 JAGUAR2_P(21, IRQ1_OUT,  TWI_SCL_M);
584 JAGUAR2_P(22, TACHO,     NONE);
585 JAGUAR2_P(23, PWM,       NONE);
586 JAGUAR2_P(24, UART2,     NONE);
587 JAGUAR2_P(25, UART2,     SI);
588 JAGUAR2_P(26, PTP2,      SI);
589 JAGUAR2_P(27, PTP3,      SI);
590 JAGUAR2_P(28, TWI2,      SI);
591 JAGUAR2_P(29, TWI2,      SI);
592 JAGUAR2_P(30, SG2,       SI);
593 JAGUAR2_P(31, SG2,       SI);
594 JAGUAR2_P(32, SG2,       SI);
595 JAGUAR2_P(33, SG2,       SI);
596 JAGUAR2_P(34, NONE,      TWI_SCL_M);
597 JAGUAR2_P(35, NONE,      TWI_SCL_M);
598 JAGUAR2_P(36, NONE,      TWI_SCL_M);
599 JAGUAR2_P(37, NONE,      TWI_SCL_M);
600 JAGUAR2_P(38, NONE,      TWI_SCL_M);
601 JAGUAR2_P(39, NONE,      TWI_SCL_M);
602 JAGUAR2_P(40, NONE,      TWI_SCL_M);
603 JAGUAR2_P(41, NONE,      TWI_SCL_M);
604 JAGUAR2_P(42, NONE,      TWI_SCL_M);
605 JAGUAR2_P(43, NONE,      TWI_SCL_M);
606 JAGUAR2_P(44, NONE,      SFP);
607 JAGUAR2_P(45, NONE,      SFP);
608 JAGUAR2_P(46, NONE,      SFP);
609 JAGUAR2_P(47, NONE,      SFP);
610 JAGUAR2_P(48, SFP,       NONE);
611 JAGUAR2_P(49, SFP,       SI);
612 JAGUAR2_P(50, SFP,       SI);
613 JAGUAR2_P(51, SFP,       SI);
614 JAGUAR2_P(52, SFP,       NONE);
615 JAGUAR2_P(53, SFP,       NONE);
616 JAGUAR2_P(54, SFP,       NONE);
617 JAGUAR2_P(55, SFP,       NONE);
618 JAGUAR2_P(56, MIIM,      SFP);
619 JAGUAR2_P(57, MIIM,      SFP);
620 JAGUAR2_P(58, MIIM,      SFP);
621 JAGUAR2_P(59, MIIM,      SFP);
622 JAGUAR2_P(60, NONE,      NONE);
623 JAGUAR2_P(61, NONE,      NONE);
624 JAGUAR2_P(62, NONE,      NONE);
625 JAGUAR2_P(63, NONE,      NONE);
626 
627 #define JAGUAR2_PIN(n) {					\
628 	.number = n,						\
629 	.name = "GPIO_"#n,					\
630 	.drv_data = &jaguar2_pin_##n				\
631 }
632 
633 static const struct pinctrl_pin_desc jaguar2_pins[] = {
634 	JAGUAR2_PIN(0),
635 	JAGUAR2_PIN(1),
636 	JAGUAR2_PIN(2),
637 	JAGUAR2_PIN(3),
638 	JAGUAR2_PIN(4),
639 	JAGUAR2_PIN(5),
640 	JAGUAR2_PIN(6),
641 	JAGUAR2_PIN(7),
642 	JAGUAR2_PIN(8),
643 	JAGUAR2_PIN(9),
644 	JAGUAR2_PIN(10),
645 	JAGUAR2_PIN(11),
646 	JAGUAR2_PIN(12),
647 	JAGUAR2_PIN(13),
648 	JAGUAR2_PIN(14),
649 	JAGUAR2_PIN(15),
650 	JAGUAR2_PIN(16),
651 	JAGUAR2_PIN(17),
652 	JAGUAR2_PIN(18),
653 	JAGUAR2_PIN(19),
654 	JAGUAR2_PIN(20),
655 	JAGUAR2_PIN(21),
656 	JAGUAR2_PIN(22),
657 	JAGUAR2_PIN(23),
658 	JAGUAR2_PIN(24),
659 	JAGUAR2_PIN(25),
660 	JAGUAR2_PIN(26),
661 	JAGUAR2_PIN(27),
662 	JAGUAR2_PIN(28),
663 	JAGUAR2_PIN(29),
664 	JAGUAR2_PIN(30),
665 	JAGUAR2_PIN(31),
666 	JAGUAR2_PIN(32),
667 	JAGUAR2_PIN(33),
668 	JAGUAR2_PIN(34),
669 	JAGUAR2_PIN(35),
670 	JAGUAR2_PIN(36),
671 	JAGUAR2_PIN(37),
672 	JAGUAR2_PIN(38),
673 	JAGUAR2_PIN(39),
674 	JAGUAR2_PIN(40),
675 	JAGUAR2_PIN(41),
676 	JAGUAR2_PIN(42),
677 	JAGUAR2_PIN(43),
678 	JAGUAR2_PIN(44),
679 	JAGUAR2_PIN(45),
680 	JAGUAR2_PIN(46),
681 	JAGUAR2_PIN(47),
682 	JAGUAR2_PIN(48),
683 	JAGUAR2_PIN(49),
684 	JAGUAR2_PIN(50),
685 	JAGUAR2_PIN(51),
686 	JAGUAR2_PIN(52),
687 	JAGUAR2_PIN(53),
688 	JAGUAR2_PIN(54),
689 	JAGUAR2_PIN(55),
690 	JAGUAR2_PIN(56),
691 	JAGUAR2_PIN(57),
692 	JAGUAR2_PIN(58),
693 	JAGUAR2_PIN(59),
694 	JAGUAR2_PIN(60),
695 	JAGUAR2_PIN(61),
696 	JAGUAR2_PIN(62),
697 	JAGUAR2_PIN(63),
698 };
699 
700 #define SERVALT_P(p, f0, f1, f2)					\
701 static struct ocelot_pin_caps servalt_pin_##p = {			\
702 	.pin = p,							\
703 	.functions = {							\
704 		FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2		\
705 	},								\
706 }
707 
708 SERVALT_P(0,  SG0,        NONE,      NONE);
709 SERVALT_P(1,  SG0,        NONE,      NONE);
710 SERVALT_P(2,  SG0,        NONE,      NONE);
711 SERVALT_P(3,  SG0,        NONE,      NONE);
712 SERVALT_P(4,  IRQ0_IN,    IRQ0_OUT,  TWI_SCL_M);
713 SERVALT_P(5,  IRQ1_IN,    IRQ1_OUT,  TWI_SCL_M);
714 SERVALT_P(6,  UART,       NONE,      NONE);
715 SERVALT_P(7,  UART,       NONE,      NONE);
716 SERVALT_P(8,  SI,         SFP,       TWI_SCL_M);
717 SERVALT_P(9,  PCI_WAKE,   SFP,       SI);
718 SERVALT_P(10, PTP0,       SFP,       TWI_SCL_M);
719 SERVALT_P(11, PTP1,       SFP,       TWI_SCL_M);
720 SERVALT_P(12, REF_CLK,    SFP,       TWI_SCL_M);
721 SERVALT_P(13, REF_CLK,    SFP,       TWI_SCL_M);
722 SERVALT_P(14, REF_CLK,    IRQ0_OUT,  SI);
723 SERVALT_P(15, REF_CLK,    IRQ1_OUT,  SI);
724 SERVALT_P(16, TACHO,      SFP,       SI);
725 SERVALT_P(17, PWM,        NONE,      TWI_SCL_M);
726 SERVALT_P(18, PTP2,       SFP,       SI);
727 SERVALT_P(19, PTP3,       SFP,       SI);
728 SERVALT_P(20, UART2,      SFP,       SI);
729 SERVALT_P(21, UART2,      NONE,      NONE);
730 SERVALT_P(22, MIIM,       SFP,       TWI2);
731 SERVALT_P(23, MIIM,       SFP,       TWI2);
732 SERVALT_P(24, TWI,        NONE,      NONE);
733 SERVALT_P(25, TWI,        SFP,       TWI_SCL_M);
734 SERVALT_P(26, TWI_SCL_M,  SFP,       SI);
735 SERVALT_P(27, TWI_SCL_M,  SFP,       SI);
736 SERVALT_P(28, TWI_SCL_M,  SFP,       SI);
737 SERVALT_P(29, TWI_SCL_M,  NONE,      NONE);
738 SERVALT_P(30, TWI_SCL_M,  NONE,      NONE);
739 SERVALT_P(31, TWI_SCL_M,  NONE,      NONE);
740 SERVALT_P(32, TWI_SCL_M,  NONE,      NONE);
741 SERVALT_P(33, RCVRD_CLK,  NONE,      NONE);
742 SERVALT_P(34, RCVRD_CLK,  NONE,      NONE);
743 SERVALT_P(35, RCVRD_CLK,  NONE,      NONE);
744 SERVALT_P(36, RCVRD_CLK,  NONE,      NONE);
745 
746 #define SERVALT_PIN(n) {					\
747 	.number = n,						\
748 	.name = "GPIO_"#n,					\
749 	.drv_data = &servalt_pin_##n				\
750 }
751 
752 static const struct pinctrl_pin_desc servalt_pins[] = {
753 	SERVALT_PIN(0),
754 	SERVALT_PIN(1),
755 	SERVALT_PIN(2),
756 	SERVALT_PIN(3),
757 	SERVALT_PIN(4),
758 	SERVALT_PIN(5),
759 	SERVALT_PIN(6),
760 	SERVALT_PIN(7),
761 	SERVALT_PIN(8),
762 	SERVALT_PIN(9),
763 	SERVALT_PIN(10),
764 	SERVALT_PIN(11),
765 	SERVALT_PIN(12),
766 	SERVALT_PIN(13),
767 	SERVALT_PIN(14),
768 	SERVALT_PIN(15),
769 	SERVALT_PIN(16),
770 	SERVALT_PIN(17),
771 	SERVALT_PIN(18),
772 	SERVALT_PIN(19),
773 	SERVALT_PIN(20),
774 	SERVALT_PIN(21),
775 	SERVALT_PIN(22),
776 	SERVALT_PIN(23),
777 	SERVALT_PIN(24),
778 	SERVALT_PIN(25),
779 	SERVALT_PIN(26),
780 	SERVALT_PIN(27),
781 	SERVALT_PIN(28),
782 	SERVALT_PIN(29),
783 	SERVALT_PIN(30),
784 	SERVALT_PIN(31),
785 	SERVALT_PIN(32),
786 	SERVALT_PIN(33),
787 	SERVALT_PIN(34),
788 	SERVALT_PIN(35),
789 	SERVALT_PIN(36),
790 };
791 
792 #define SPARX5_P(p, f0, f1, f2)					\
793 static struct ocelot_pin_caps sparx5_pin_##p = {			\
794 	.pin = p,							\
795 	.functions = {							\
796 		FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2		\
797 	},								\
798 }
799 
800 SPARX5_P(0,  SG0,       PLL_STAT,  NONE);
801 SPARX5_P(1,  SG0,       NONE,      NONE);
802 SPARX5_P(2,  SG0,       NONE,      NONE);
803 SPARX5_P(3,  SG0,       NONE,      NONE);
804 SPARX5_P(4,  SG1,       NONE,      NONE);
805 SPARX5_P(5,  SG1,       NONE,      NONE);
806 SPARX5_P(6,  IRQ0_IN,   IRQ0_OUT,  SFP);
807 SPARX5_P(7,  IRQ1_IN,   IRQ1_OUT,  SFP);
808 SPARX5_P(8,  PTP0,      NONE,      SFP);
809 SPARX5_P(9,  PTP1,      SFP,       TWI_SCL_M);
810 SPARX5_P(10, UART,      NONE,      NONE);
811 SPARX5_P(11, UART,      NONE,      NONE);
812 SPARX5_P(12, SG1,       NONE,      NONE);
813 SPARX5_P(13, SG1,       NONE,      NONE);
814 SPARX5_P(14, TWI,       TWI_SCL_M, NONE);
815 SPARX5_P(15, TWI,       NONE,      NONE);
816 SPARX5_P(16, SI,        TWI_SCL_M, SFP);
817 SPARX5_P(17, SI,        TWI_SCL_M, SFP);
818 SPARX5_P(18, SI,        TWI_SCL_M, SFP);
819 SPARX5_P(19, PCI_WAKE,  TWI_SCL_M, SFP);
820 SPARX5_P(20, IRQ0_OUT,  TWI_SCL_M, SFP);
821 SPARX5_P(21, IRQ1_OUT,  TACHO,     SFP);
822 SPARX5_P(22, TACHO,     IRQ0_OUT,  TWI_SCL_M);
823 SPARX5_P(23, PWM,       UART3,     TWI_SCL_M);
824 SPARX5_P(24, PTP2,      UART3,     TWI_SCL_M);
825 SPARX5_P(25, PTP3,      SI,        TWI_SCL_M);
826 SPARX5_P(26, UART2,     SI,        TWI_SCL_M);
827 SPARX5_P(27, UART2,     SI,        TWI_SCL_M);
828 SPARX5_P(28, TWI2,      SI,        SFP);
829 SPARX5_P(29, TWI2,      SI,        SFP);
830 SPARX5_P(30, SG2,       SI,        PWM);
831 SPARX5_P(31, SG2,       SI,        TWI_SCL_M);
832 SPARX5_P(32, SG2,       SI,        TWI_SCL_M);
833 SPARX5_P(33, SG2,       SI,        SFP);
834 SPARX5_P(34, NONE,      TWI_SCL_M, EMMC);
835 SPARX5_P(35, SFP,       TWI_SCL_M, EMMC);
836 SPARX5_P(36, SFP,       TWI_SCL_M, EMMC);
837 SPARX5_P(37, SFP,       NONE,      EMMC);
838 SPARX5_P(38, NONE,      TWI_SCL_M, EMMC);
839 SPARX5_P(39, SI2,       TWI_SCL_M, EMMC);
840 SPARX5_P(40, SI2,       TWI_SCL_M, EMMC);
841 SPARX5_P(41, SI2,       TWI_SCL_M, EMMC);
842 SPARX5_P(42, SI2,       TWI_SCL_M, EMMC);
843 SPARX5_P(43, SI2,       TWI_SCL_M, EMMC);
844 SPARX5_P(44, SI,        SFP,       EMMC);
845 SPARX5_P(45, SI,        SFP,       EMMC);
846 SPARX5_P(46, NONE,      SFP,       EMMC);
847 SPARX5_P(47, NONE,      SFP,       EMMC);
848 SPARX5_P(48, TWI3,      SI,        SFP);
849 SPARX5_P(49, TWI3,      NONE,      SFP);
850 SPARX5_P(50, SFP,       NONE,      TWI_SCL_M);
851 SPARX5_P(51, SFP,       SI,        TWI_SCL_M);
852 SPARX5_P(52, SFP,       MIIM,      TWI_SCL_M);
853 SPARX5_P(53, SFP,       MIIM,      TWI_SCL_M);
854 SPARX5_P(54, SFP,       PTP2,      TWI_SCL_M);
855 SPARX5_P(55, SFP,       PTP3,      PCI_WAKE);
856 SPARX5_P(56, MIIM,      SFP,       TWI_SCL_M);
857 SPARX5_P(57, MIIM,      SFP,       TWI_SCL_M);
858 SPARX5_P(58, MIIM,      SFP,       TWI_SCL_M);
859 SPARX5_P(59, MIIM,      SFP,       NONE);
860 SPARX5_P(60, RECO_CLK,  NONE,      NONE);
861 SPARX5_P(61, RECO_CLK,  NONE,      NONE);
862 SPARX5_P(62, RECO_CLK,  PLL_STAT,  NONE);
863 SPARX5_P(63, RECO_CLK,  NONE,      NONE);
864 
865 #define SPARX5_PIN(n) {					\
866 	.number = n,						\
867 	.name = "GPIO_"#n,					\
868 	.drv_data = &sparx5_pin_##n				\
869 }
870 
871 static const struct pinctrl_pin_desc sparx5_pins[] = {
872 	SPARX5_PIN(0),
873 	SPARX5_PIN(1),
874 	SPARX5_PIN(2),
875 	SPARX5_PIN(3),
876 	SPARX5_PIN(4),
877 	SPARX5_PIN(5),
878 	SPARX5_PIN(6),
879 	SPARX5_PIN(7),
880 	SPARX5_PIN(8),
881 	SPARX5_PIN(9),
882 	SPARX5_PIN(10),
883 	SPARX5_PIN(11),
884 	SPARX5_PIN(12),
885 	SPARX5_PIN(13),
886 	SPARX5_PIN(14),
887 	SPARX5_PIN(15),
888 	SPARX5_PIN(16),
889 	SPARX5_PIN(17),
890 	SPARX5_PIN(18),
891 	SPARX5_PIN(19),
892 	SPARX5_PIN(20),
893 	SPARX5_PIN(21),
894 	SPARX5_PIN(22),
895 	SPARX5_PIN(23),
896 	SPARX5_PIN(24),
897 	SPARX5_PIN(25),
898 	SPARX5_PIN(26),
899 	SPARX5_PIN(27),
900 	SPARX5_PIN(28),
901 	SPARX5_PIN(29),
902 	SPARX5_PIN(30),
903 	SPARX5_PIN(31),
904 	SPARX5_PIN(32),
905 	SPARX5_PIN(33),
906 	SPARX5_PIN(34),
907 	SPARX5_PIN(35),
908 	SPARX5_PIN(36),
909 	SPARX5_PIN(37),
910 	SPARX5_PIN(38),
911 	SPARX5_PIN(39),
912 	SPARX5_PIN(40),
913 	SPARX5_PIN(41),
914 	SPARX5_PIN(42),
915 	SPARX5_PIN(43),
916 	SPARX5_PIN(44),
917 	SPARX5_PIN(45),
918 	SPARX5_PIN(46),
919 	SPARX5_PIN(47),
920 	SPARX5_PIN(48),
921 	SPARX5_PIN(49),
922 	SPARX5_PIN(50),
923 	SPARX5_PIN(51),
924 	SPARX5_PIN(52),
925 	SPARX5_PIN(53),
926 	SPARX5_PIN(54),
927 	SPARX5_PIN(55),
928 	SPARX5_PIN(56),
929 	SPARX5_PIN(57),
930 	SPARX5_PIN(58),
931 	SPARX5_PIN(59),
932 	SPARX5_PIN(60),
933 	SPARX5_PIN(61),
934 	SPARX5_PIN(62),
935 	SPARX5_PIN(63),
936 };
937 
938 #define LAN966X_P(p, f0, f1, f2, f3, f4, f5, f6, f7)           \
939 static struct ocelot_pin_caps lan966x_pin_##p = {              \
940 	.pin = p,                                              \
941 	.functions = {                                         \
942 		FUNC_##f0, FUNC_##f1, FUNC_##f2,               \
943 		FUNC_##f3                                      \
944 	},                                                     \
945 	.a_functions = {                                       \
946 		FUNC_##f4, FUNC_##f5, FUNC_##f6,               \
947 		FUNC_##f7                                      \
948 	},                                                     \
949 }
950 
951 /* Pinmuxing table taken from data sheet */
952 /*        Pin   FUNC0    FUNC1     FUNC2      FUNC3     FUNC4     FUNC5      FUNC6    FUNC7 */
953 LAN966X_P(0,    GPIO,    NONE,     NONE,      NONE,     NONE,     NONE,      NONE,        R);
954 LAN966X_P(1,    GPIO,    NONE,     NONE,      NONE,     NONE,     NONE,      NONE,        R);
955 LAN966X_P(2,    GPIO,    NONE,     NONE,      NONE,     NONE,     NONE,      NONE,        R);
956 LAN966X_P(3,    GPIO,    NONE,     NONE,      NONE,     NONE,     NONE,      NONE,        R);
957 LAN966X_P(4,    GPIO,    NONE,     NONE,      NONE,     NONE,     NONE,      NONE,        R);
958 LAN966X_P(5,    GPIO,    NONE,     NONE,      NONE,     NONE,     NONE,      NONE,        R);
959 LAN966X_P(6,    GPIO,    NONE,     NONE,      NONE,     NONE,     NONE,      NONE,        R);
960 LAN966X_P(7,    GPIO,    NONE,     NONE,      NONE,     NONE,     NONE,      NONE,        R);
961 LAN966X_P(8,    GPIO,   FC0_a,  USB_H_b,      NONE,  USB_S_b,     NONE,      NONE,        R);
962 LAN966X_P(9,    GPIO,   FC0_a,  USB_H_b,      NONE,     NONE,     NONE,      NONE,        R);
963 LAN966X_P(10,   GPIO,   FC0_a,     NONE,      NONE,     NONE,     NONE,      NONE,        R);
964 LAN966X_P(11,   GPIO,   FC1_a,     NONE,      NONE,     NONE,     NONE,      NONE,        R);
965 LAN966X_P(12,   GPIO,   FC1_a,     NONE,      NONE,     NONE,     NONE,      NONE,        R);
966 LAN966X_P(13,   GPIO,   FC1_a,     NONE,      NONE,     NONE,     NONE,      NONE,        R);
967 LAN966X_P(14,   GPIO,   FC2_a,     NONE,      NONE,     NONE,     NONE,      NONE,        R);
968 LAN966X_P(15,   GPIO,   FC2_a,     NONE,      NONE,     NONE,     NONE,      NONE,        R);
969 LAN966X_P(16,   GPIO,   FC2_a, IB_TRG_a,      NONE, OB_TRG_a, IRQ_IN_c, IRQ_OUT_c,        R);
970 LAN966X_P(17,   GPIO,   FC3_a, IB_TRG_a,      NONE, OB_TRG_a, IRQ_IN_c, IRQ_OUT_c,        R);
971 LAN966X_P(18,   GPIO,   FC3_a, IB_TRG_a,      NONE, OB_TRG_a, IRQ_IN_c, IRQ_OUT_c,        R);
972 LAN966X_P(19,   GPIO,   FC3_a, IB_TRG_a,      NONE, OB_TRG_a, IRQ_IN_c, IRQ_OUT_c,        R);
973 LAN966X_P(20,   GPIO,   FC4_a, IB_TRG_a,      NONE, OB_TRG_a, IRQ_IN_c,      NONE,        R);
974 LAN966X_P(21,   GPIO,   FC4_a,     NONE,      NONE, OB_TRG_a,     NONE,      NONE,        R);
975 LAN966X_P(22,   GPIO,   FC4_a,     NONE,      NONE, OB_TRG_a,     NONE,      NONE,        R);
976 LAN966X_P(23,   GPIO,    NONE,     NONE,      NONE, OB_TRG_a,     NONE,      NONE,        R);
977 LAN966X_P(24,   GPIO,   FC0_b, IB_TRG_a,   USB_H_c, OB_TRG_a, IRQ_IN_c,   TACHO_a,        R);
978 LAN966X_P(25,   GPIO,   FC0_b, IB_TRG_a,   USB_H_c, OB_TRG_a, IRQ_OUT_c,   SFP_SD,        R);
979 LAN966X_P(26,   GPIO,   FC0_b, IB_TRG_a,   USB_S_c, OB_TRG_a,   CAN0_a,    SFP_SD,        R);
980 LAN966X_P(27,   GPIO,    NONE,     NONE,      NONE, OB_TRG_a,   CAN0_a,      NONE,        R);
981 LAN966X_P(28,   GPIO,  MIIM_a,     NONE,      NONE, OB_TRG_a, IRQ_OUT_c,   SFP_SD,        R);
982 LAN966X_P(29,   GPIO,  MIIM_a,     NONE,      NONE, OB_TRG_a,     NONE,      NONE,        R);
983 LAN966X_P(30,   GPIO,   FC3_c,     CAN1,      NONE,   OB_TRG,   RECO_b,      NONE,        R);
984 LAN966X_P(31,   GPIO,   FC3_c,     CAN1,      NONE,   OB_TRG,   RECO_b,      NONE,        R);
985 LAN966X_P(32,   GPIO,   FC3_c,     NONE,   SGPIO_a,     NONE,  MIIM_Sa,      NONE,        R);
986 LAN966X_P(33,   GPIO,   FC1_b,     NONE,   SGPIO_a,     NONE,  MIIM_Sa,    MIIM_b,        R);
987 LAN966X_P(34,   GPIO,   FC1_b,     NONE,   SGPIO_a,     NONE,  MIIM_Sa,    MIIM_b,        R);
988 LAN966X_P(35,   GPIO,   FC1_b,  PTPSYNC_0, SGPIO_a,   CAN0_b,     NONE,      NONE,        R);
989 LAN966X_P(36,   GPIO,    NONE,  PTPSYNC_1,    NONE,   CAN0_b,     NONE,      NONE,        R);
990 LAN966X_P(37,   GPIO, FC_SHRD0, PTPSYNC_2, TWI_SLC_GATE_AD, NONE, NONE,      NONE,        R);
991 LAN966X_P(38,   GPIO,    NONE,  PTPSYNC_3,    NONE,     NONE,     NONE,      NONE,        R);
992 LAN966X_P(39,   GPIO,    NONE,  PTPSYNC_4,    NONE,     NONE,     NONE,      NONE,        R);
993 LAN966X_P(40,   GPIO, FC_SHRD1, PTPSYNC_5,    NONE,     NONE,     NONE,      NONE,        R);
994 LAN966X_P(41,   GPIO, FC_SHRD2, PTPSYNC_6, TWI_SLC_GATE_AD, NONE, NONE,      NONE,        R);
995 LAN966X_P(42,   GPIO, FC_SHRD3, PTPSYNC_7, TWI_SLC_GATE_AD, NONE, NONE,      NONE,        R);
996 LAN966X_P(43,   GPIO,   FC2_b,   OB_TRG_b, IB_TRG_b, IRQ_OUT_a,  RECO_a,  IRQ_IN_a,       R);
997 LAN966X_P(44,   GPIO,   FC2_b,   OB_TRG_b, IB_TRG_b, IRQ_OUT_a,  RECO_a,  IRQ_IN_a,       R);
998 LAN966X_P(45,   GPIO,   FC2_b,   OB_TRG_b, IB_TRG_b, IRQ_OUT_a,    NONE,  IRQ_IN_a,       R);
999 LAN966X_P(46,   GPIO,   FC1_c,   OB_TRG_b, IB_TRG_b, IRQ_OUT_a, FC_SHRD4, IRQ_IN_a,       R);
1000 LAN966X_P(47,   GPIO,   FC1_c,   OB_TRG_b, IB_TRG_b, IRQ_OUT_a, FC_SHRD5, IRQ_IN_a,       R);
1001 LAN966X_P(48,   GPIO,   FC1_c,   OB_TRG_b, IB_TRG_b, IRQ_OUT_a, FC_SHRD6, IRQ_IN_a,       R);
1002 LAN966X_P(49,   GPIO, FC_SHRD7,  OB_TRG_b, IB_TRG_b, IRQ_OUT_a, TWI_SLC_GATE, IRQ_IN_a,   R);
1003 LAN966X_P(50,   GPIO, FC_SHRD16, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, TWI_SLC_GATE, NONE,       R);
1004 LAN966X_P(51,   GPIO,   FC3_b,   OB_TRG_b, IB_TRG_c, IRQ_OUT_b,    NONE,  IRQ_IN_b,       R);
1005 LAN966X_P(52,   GPIO,   FC3_b,   OB_TRG_b, IB_TRG_c, IRQ_OUT_b, TACHO_b,  IRQ_IN_b,       R);
1006 LAN966X_P(53,   GPIO,   FC3_b,   OB_TRG_b, IB_TRG_c, IRQ_OUT_b,    NONE,  IRQ_IN_b,       R);
1007 LAN966X_P(54,   GPIO, FC_SHRD8,  OB_TRG_b, IB_TRG_c, IRQ_OUT_b, TWI_SLC_GATE, IRQ_IN_b,   R);
1008 LAN966X_P(55,   GPIO, FC_SHRD9,  OB_TRG_b, IB_TRG_c, IRQ_OUT_b, TWI_SLC_GATE, IRQ_IN_b,   R);
1009 LAN966X_P(56,   GPIO,   FC4_b,   OB_TRG_b, IB_TRG_c, IRQ_OUT_b, FC_SHRD10,    IRQ_IN_b,   R);
1010 LAN966X_P(57,   GPIO,   FC4_b, TWI_SLC_GATE, IB_TRG_c, IRQ_OUT_b, FC_SHRD11, IRQ_IN_b,    R);
1011 LAN966X_P(58,   GPIO,   FC4_b, TWI_SLC_GATE, IB_TRG_c, IRQ_OUT_b, FC_SHRD12, IRQ_IN_b,    R);
1012 LAN966X_P(59,   GPIO,   QSPI1,   MIIM_c,      NONE,     NONE,  MIIM_Sb,      NONE,        R);
1013 LAN966X_P(60,   GPIO,   QSPI1,   MIIM_c,      NONE,     NONE,  MIIM_Sb,      NONE,        R);
1014 LAN966X_P(61,   GPIO,   QSPI1,     NONE,   SGPIO_b,    FC0_c,  MIIM_Sb,      NONE,        R);
1015 LAN966X_P(62,   GPIO,   QSPI1, FC_SHRD13,  SGPIO_b,    FC0_c, TWI_SLC_GATE,  SFP_SD,      R);
1016 LAN966X_P(63,   GPIO,   QSPI1, FC_SHRD14,  SGPIO_b,    FC0_c, TWI_SLC_GATE,  SFP_SD,      R);
1017 LAN966X_P(64,   GPIO,   QSPI1,    FC4_c,   SGPIO_b, FC_SHRD15, TWI_SLC_GATE, SFP_SD,      R);
1018 LAN966X_P(65,   GPIO, USB_H_a,    FC4_c,      NONE, IRQ_OUT_c, TWI_SLC_GATE_AD, NONE,     R);
1019 LAN966X_P(66,   GPIO, USB_H_a,    FC4_c,   USB_S_a, IRQ_OUT_c, IRQ_IN_c,     NONE,        R);
1020 LAN966X_P(67,   GPIO, EMMC_SD,     NONE,     QSPI2,     NONE,     NONE,      NONE,        R);
1021 LAN966X_P(68,   GPIO, EMMC_SD,     NONE,     QSPI2,     NONE,     NONE,      NONE,        R);
1022 LAN966X_P(69,   GPIO, EMMC_SD,     NONE,     QSPI2,     NONE,     NONE,      NONE,        R);
1023 LAN966X_P(70,   GPIO, EMMC_SD,     NONE,     QSPI2,     NONE,     NONE,      NONE,        R);
1024 LAN966X_P(71,   GPIO, EMMC_SD,     NONE,     QSPI2,     NONE,     NONE,      NONE,        R);
1025 LAN966X_P(72,   GPIO, EMMC_SD,     NONE,     QSPI2,     NONE,     NONE,      NONE,        R);
1026 LAN966X_P(73,   GPIO,    EMMC,     NONE,      NONE,       SD,     NONE,      NONE,        R);
1027 LAN966X_P(74,   GPIO,    EMMC,     NONE, FC_SHRD17,       SD, TWI_SLC_GATE,  NONE,        R);
1028 LAN966X_P(75,   GPIO,    EMMC,     NONE, FC_SHRD18,       SD, TWI_SLC_GATE,  NONE,        R);
1029 LAN966X_P(76,   GPIO,    EMMC,     NONE, FC_SHRD19,       SD, TWI_SLC_GATE,  NONE,        R);
1030 LAN966X_P(77,   GPIO, EMMC_SD,     NONE, FC_SHRD20,     NONE, TWI_SLC_GATE,  NONE,        R);
1031 
1032 #define LAN966X_PIN(n) {                                       \
1033 	.number = n,                                           \
1034 	.name = "GPIO_"#n,                                     \
1035 	.drv_data = &lan966x_pin_##n                           \
1036 }
1037 
1038 static const struct pinctrl_pin_desc lan966x_pins[] = {
1039 	LAN966X_PIN(0),
1040 	LAN966X_PIN(1),
1041 	LAN966X_PIN(2),
1042 	LAN966X_PIN(3),
1043 	LAN966X_PIN(4),
1044 	LAN966X_PIN(5),
1045 	LAN966X_PIN(6),
1046 	LAN966X_PIN(7),
1047 	LAN966X_PIN(8),
1048 	LAN966X_PIN(9),
1049 	LAN966X_PIN(10),
1050 	LAN966X_PIN(11),
1051 	LAN966X_PIN(12),
1052 	LAN966X_PIN(13),
1053 	LAN966X_PIN(14),
1054 	LAN966X_PIN(15),
1055 	LAN966X_PIN(16),
1056 	LAN966X_PIN(17),
1057 	LAN966X_PIN(18),
1058 	LAN966X_PIN(19),
1059 	LAN966X_PIN(20),
1060 	LAN966X_PIN(21),
1061 	LAN966X_PIN(22),
1062 	LAN966X_PIN(23),
1063 	LAN966X_PIN(24),
1064 	LAN966X_PIN(25),
1065 	LAN966X_PIN(26),
1066 	LAN966X_PIN(27),
1067 	LAN966X_PIN(28),
1068 	LAN966X_PIN(29),
1069 	LAN966X_PIN(30),
1070 	LAN966X_PIN(31),
1071 	LAN966X_PIN(32),
1072 	LAN966X_PIN(33),
1073 	LAN966X_PIN(34),
1074 	LAN966X_PIN(35),
1075 	LAN966X_PIN(36),
1076 	LAN966X_PIN(37),
1077 	LAN966X_PIN(38),
1078 	LAN966X_PIN(39),
1079 	LAN966X_PIN(40),
1080 	LAN966X_PIN(41),
1081 	LAN966X_PIN(42),
1082 	LAN966X_PIN(43),
1083 	LAN966X_PIN(44),
1084 	LAN966X_PIN(45),
1085 	LAN966X_PIN(46),
1086 	LAN966X_PIN(47),
1087 	LAN966X_PIN(48),
1088 	LAN966X_PIN(49),
1089 	LAN966X_PIN(50),
1090 	LAN966X_PIN(51),
1091 	LAN966X_PIN(52),
1092 	LAN966X_PIN(53),
1093 	LAN966X_PIN(54),
1094 	LAN966X_PIN(55),
1095 	LAN966X_PIN(56),
1096 	LAN966X_PIN(57),
1097 	LAN966X_PIN(58),
1098 	LAN966X_PIN(59),
1099 	LAN966X_PIN(60),
1100 	LAN966X_PIN(61),
1101 	LAN966X_PIN(62),
1102 	LAN966X_PIN(63),
1103 	LAN966X_PIN(64),
1104 	LAN966X_PIN(65),
1105 	LAN966X_PIN(66),
1106 	LAN966X_PIN(67),
1107 	LAN966X_PIN(68),
1108 	LAN966X_PIN(69),
1109 	LAN966X_PIN(70),
1110 	LAN966X_PIN(71),
1111 	LAN966X_PIN(72),
1112 	LAN966X_PIN(73),
1113 	LAN966X_PIN(74),
1114 	LAN966X_PIN(75),
1115 	LAN966X_PIN(76),
1116 	LAN966X_PIN(77),
1117 };
1118 
1119 static int ocelot_get_functions_count(struct pinctrl_dev *pctldev)
1120 {
1121 	return ARRAY_SIZE(ocelot_function_names);
1122 }
1123 
1124 static const char *ocelot_get_function_name(struct pinctrl_dev *pctldev,
1125 					    unsigned int function)
1126 {
1127 	return ocelot_function_names[function];
1128 }
1129 
1130 static int ocelot_get_function_groups(struct pinctrl_dev *pctldev,
1131 				      unsigned int function,
1132 				      const char *const **groups,
1133 				      unsigned *const num_groups)
1134 {
1135 	struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1136 
1137 	*groups  = info->func[function].groups;
1138 	*num_groups = info->func[function].ngroups;
1139 
1140 	return 0;
1141 }
1142 
1143 static int ocelot_pin_function_idx(struct ocelot_pinctrl *info,
1144 				   unsigned int pin, unsigned int function)
1145 {
1146 	struct ocelot_pin_caps *p = info->desc->pins[pin].drv_data;
1147 	int i;
1148 
1149 	for (i = 0; i < OCELOT_FUNC_PER_PIN; i++) {
1150 		if (function == p->functions[i])
1151 			return i;
1152 
1153 		if (function == p->a_functions[i])
1154 			return i + OCELOT_FUNC_PER_PIN;
1155 	}
1156 
1157 	return -1;
1158 }
1159 
1160 #define REG_ALT(msb, info, p) (OCELOT_GPIO_ALT0 * (info)->stride + 4 * ((msb) + ((info)->stride * ((p) / 32))))
1161 
1162 static int ocelot_pinmux_set_mux(struct pinctrl_dev *pctldev,
1163 				 unsigned int selector, unsigned int group)
1164 {
1165 	struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1166 	struct ocelot_pin_caps *pin = info->desc->pins[group].drv_data;
1167 	unsigned int p = pin->pin % 32;
1168 	int f;
1169 
1170 	f = ocelot_pin_function_idx(info, group, selector);
1171 	if (f < 0)
1172 		return -EINVAL;
1173 
1174 	/*
1175 	 * f is encoded on two bits.
1176 	 * bit 0 of f goes in BIT(pin) of ALT[0], bit 1 of f goes in BIT(pin) of
1177 	 * ALT[1]
1178 	 * This is racy because both registers can't be updated at the same time
1179 	 * but it doesn't matter much for now.
1180 	 * Note: ALT0/ALT1 are organized specially for 64 gpio targets
1181 	 */
1182 	regmap_update_bits(info->map, REG_ALT(0, info, pin->pin),
1183 			   BIT(p), f << p);
1184 	regmap_update_bits(info->map, REG_ALT(1, info, pin->pin),
1185 			   BIT(p), f << (p - 1));
1186 
1187 	return 0;
1188 }
1189 
1190 static int lan966x_pinmux_set_mux(struct pinctrl_dev *pctldev,
1191 				  unsigned int selector, unsigned int group)
1192 {
1193 	struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1194 	struct ocelot_pin_caps *pin = info->desc->pins[group].drv_data;
1195 	unsigned int p = pin->pin % 32;
1196 	int f;
1197 
1198 	f = ocelot_pin_function_idx(info, group, selector);
1199 	if (f < 0)
1200 		return -EINVAL;
1201 
1202 	/*
1203 	 * f is encoded on three bits.
1204 	 * bit 0 of f goes in BIT(pin) of ALT[0], bit 1 of f goes in BIT(pin) of
1205 	 * ALT[1], bit 2 of f goes in BIT(pin) of ALT[2]
1206 	 * This is racy because three registers can't be updated at the same time
1207 	 * but it doesn't matter much for now.
1208 	 * Note: ALT0/ALT1/ALT2 are organized specially for 78 gpio targets
1209 	 */
1210 	regmap_update_bits(info->map, REG_ALT(0, info, pin->pin),
1211 			   BIT(p), f << p);
1212 	regmap_update_bits(info->map, REG_ALT(1, info, pin->pin),
1213 			   BIT(p), (f >> 1) << p);
1214 	regmap_update_bits(info->map, REG_ALT(2, info, pin->pin),
1215 			   BIT(p), (f >> 2) << p);
1216 
1217 	return 0;
1218 }
1219 
1220 #define REG(r, info, p) ((r) * (info)->stride + (4 * ((p) / 32)))
1221 
1222 static int ocelot_gpio_set_direction(struct pinctrl_dev *pctldev,
1223 				     struct pinctrl_gpio_range *range,
1224 				     unsigned int pin, bool input)
1225 {
1226 	struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1227 	unsigned int p = pin % 32;
1228 
1229 	regmap_update_bits(info->map, REG(OCELOT_GPIO_OE, info, pin), BIT(p),
1230 			   input ? 0 : BIT(p));
1231 
1232 	return 0;
1233 }
1234 
1235 static int ocelot_gpio_request_enable(struct pinctrl_dev *pctldev,
1236 				      struct pinctrl_gpio_range *range,
1237 				      unsigned int offset)
1238 {
1239 	struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1240 	unsigned int p = offset % 32;
1241 
1242 	regmap_update_bits(info->map, REG_ALT(0, info, offset),
1243 			   BIT(p), 0);
1244 	regmap_update_bits(info->map, REG_ALT(1, info, offset),
1245 			   BIT(p), 0);
1246 
1247 	return 0;
1248 }
1249 
1250 static int lan966x_gpio_request_enable(struct pinctrl_dev *pctldev,
1251 				       struct pinctrl_gpio_range *range,
1252 				       unsigned int offset)
1253 {
1254 	struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1255 	unsigned int p = offset % 32;
1256 
1257 	regmap_update_bits(info->map, REG_ALT(0, info, offset),
1258 			   BIT(p), 0);
1259 	regmap_update_bits(info->map, REG_ALT(1, info, offset),
1260 			   BIT(p), 0);
1261 	regmap_update_bits(info->map, REG_ALT(2, info, offset),
1262 			   BIT(p), 0);
1263 
1264 	return 0;
1265 }
1266 
1267 static const struct pinmux_ops ocelot_pmx_ops = {
1268 	.get_functions_count = ocelot_get_functions_count,
1269 	.get_function_name = ocelot_get_function_name,
1270 	.get_function_groups = ocelot_get_function_groups,
1271 	.set_mux = ocelot_pinmux_set_mux,
1272 	.gpio_set_direction = ocelot_gpio_set_direction,
1273 	.gpio_request_enable = ocelot_gpio_request_enable,
1274 };
1275 
1276 static const struct pinmux_ops lan966x_pmx_ops = {
1277 	.get_functions_count = ocelot_get_functions_count,
1278 	.get_function_name = ocelot_get_function_name,
1279 	.get_function_groups = ocelot_get_function_groups,
1280 	.set_mux = lan966x_pinmux_set_mux,
1281 	.gpio_set_direction = ocelot_gpio_set_direction,
1282 	.gpio_request_enable = lan966x_gpio_request_enable,
1283 };
1284 
1285 static int ocelot_pctl_get_groups_count(struct pinctrl_dev *pctldev)
1286 {
1287 	struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1288 
1289 	return info->desc->npins;
1290 }
1291 
1292 static const char *ocelot_pctl_get_group_name(struct pinctrl_dev *pctldev,
1293 					      unsigned int group)
1294 {
1295 	struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1296 
1297 	return info->desc->pins[group].name;
1298 }
1299 
1300 static int ocelot_pctl_get_group_pins(struct pinctrl_dev *pctldev,
1301 				      unsigned int group,
1302 				      const unsigned int **pins,
1303 				      unsigned int *num_pins)
1304 {
1305 	struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1306 
1307 	*pins = &info->desc->pins[group].number;
1308 	*num_pins = 1;
1309 
1310 	return 0;
1311 }
1312 
1313 static int ocelot_hw_get_value(struct ocelot_pinctrl *info,
1314 			       unsigned int pin,
1315 			       unsigned int reg,
1316 			       int *val)
1317 {
1318 	int ret = -EOPNOTSUPP;
1319 
1320 	if (info->pincfg) {
1321 		u32 regcfg;
1322 
1323 		ret = regmap_read(info->pincfg, pin, &regcfg);
1324 		if (ret)
1325 			return ret;
1326 
1327 		ret = 0;
1328 		switch (reg) {
1329 		case PINCONF_BIAS:
1330 			*val = regcfg & BIAS_BITS;
1331 			break;
1332 
1333 		case PINCONF_SCHMITT:
1334 			*val = regcfg & SCHMITT_BIT;
1335 			break;
1336 
1337 		case PINCONF_DRIVE_STRENGTH:
1338 			*val = regcfg & DRIVE_BITS;
1339 			break;
1340 
1341 		default:
1342 			ret = -EOPNOTSUPP;
1343 			break;
1344 		}
1345 	}
1346 	return ret;
1347 }
1348 
1349 static int ocelot_pincfg_clrsetbits(struct ocelot_pinctrl *info, u32 regaddr,
1350 				    u32 clrbits, u32 setbits)
1351 {
1352 	u32 val;
1353 	int ret;
1354 
1355 	ret = regmap_read(info->pincfg, regaddr, &val);
1356 	if (ret)
1357 		return ret;
1358 
1359 	val &= ~clrbits;
1360 	val |= setbits;
1361 
1362 	ret = regmap_write(info->pincfg, regaddr, val);
1363 
1364 	return ret;
1365 }
1366 
1367 static int ocelot_hw_set_value(struct ocelot_pinctrl *info,
1368 			       unsigned int pin,
1369 			       unsigned int reg,
1370 			       int val)
1371 {
1372 	int ret = -EOPNOTSUPP;
1373 
1374 	if (info->pincfg) {
1375 
1376 		ret = 0;
1377 		switch (reg) {
1378 		case PINCONF_BIAS:
1379 			ret = ocelot_pincfg_clrsetbits(info, pin, BIAS_BITS,
1380 						       val);
1381 			break;
1382 
1383 		case PINCONF_SCHMITT:
1384 			ret = ocelot_pincfg_clrsetbits(info, pin, SCHMITT_BIT,
1385 						       val);
1386 			break;
1387 
1388 		case PINCONF_DRIVE_STRENGTH:
1389 			if (val <= 3)
1390 				ret = ocelot_pincfg_clrsetbits(info, pin,
1391 							       DRIVE_BITS, val);
1392 			else
1393 				ret = -EINVAL;
1394 			break;
1395 
1396 		default:
1397 			ret = -EOPNOTSUPP;
1398 			break;
1399 		}
1400 	}
1401 	return ret;
1402 }
1403 
1404 static int ocelot_pinconf_get(struct pinctrl_dev *pctldev,
1405 			      unsigned int pin, unsigned long *config)
1406 {
1407 	struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1408 	u32 param = pinconf_to_config_param(*config);
1409 	int val, err;
1410 
1411 	switch (param) {
1412 	case PIN_CONFIG_BIAS_DISABLE:
1413 	case PIN_CONFIG_BIAS_PULL_UP:
1414 	case PIN_CONFIG_BIAS_PULL_DOWN:
1415 		err = ocelot_hw_get_value(info, pin, PINCONF_BIAS, &val);
1416 		if (err)
1417 			return err;
1418 		if (param == PIN_CONFIG_BIAS_DISABLE)
1419 			val = (val == 0);
1420 		else if (param == PIN_CONFIG_BIAS_PULL_DOWN)
1421 			val = (val & BIAS_PD_BIT ? true : false);
1422 		else    /* PIN_CONFIG_BIAS_PULL_UP */
1423 			val = (val & BIAS_PU_BIT ? true : false);
1424 		break;
1425 
1426 	case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
1427 		err = ocelot_hw_get_value(info, pin, PINCONF_SCHMITT, &val);
1428 		if (err)
1429 			return err;
1430 
1431 		val = (val & SCHMITT_BIT ? true : false);
1432 		break;
1433 
1434 	case PIN_CONFIG_DRIVE_STRENGTH:
1435 		err = ocelot_hw_get_value(info, pin, PINCONF_DRIVE_STRENGTH,
1436 					  &val);
1437 		if (err)
1438 			return err;
1439 		break;
1440 
1441 	case PIN_CONFIG_OUTPUT:
1442 		err = regmap_read(info->map, REG(OCELOT_GPIO_OUT, info, pin),
1443 				  &val);
1444 		if (err)
1445 			return err;
1446 		val = !!(val & BIT(pin % 32));
1447 		break;
1448 
1449 	case PIN_CONFIG_INPUT_ENABLE:
1450 	case PIN_CONFIG_OUTPUT_ENABLE:
1451 		err = regmap_read(info->map, REG(OCELOT_GPIO_OE, info, pin),
1452 				  &val);
1453 		if (err)
1454 			return err;
1455 		val = val & BIT(pin % 32);
1456 		if (param == PIN_CONFIG_OUTPUT_ENABLE)
1457 			val = !!val;
1458 		else
1459 			val = !val;
1460 		break;
1461 
1462 	default:
1463 		return -EOPNOTSUPP;
1464 	}
1465 
1466 	*config = pinconf_to_config_packed(param, val);
1467 
1468 	return 0;
1469 }
1470 
1471 static int ocelot_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
1472 			      unsigned long *configs, unsigned int num_configs)
1473 {
1474 	struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1475 	u32 param, arg, p;
1476 	int cfg, err = 0;
1477 
1478 	for (cfg = 0; cfg < num_configs; cfg++) {
1479 		param = pinconf_to_config_param(configs[cfg]);
1480 		arg = pinconf_to_config_argument(configs[cfg]);
1481 
1482 		switch (param) {
1483 		case PIN_CONFIG_BIAS_DISABLE:
1484 		case PIN_CONFIG_BIAS_PULL_UP:
1485 		case PIN_CONFIG_BIAS_PULL_DOWN:
1486 			arg = (param == PIN_CONFIG_BIAS_DISABLE) ? 0 :
1487 			(param == PIN_CONFIG_BIAS_PULL_UP) ? BIAS_PU_BIT :
1488 			BIAS_PD_BIT;
1489 
1490 			err = ocelot_hw_set_value(info, pin, PINCONF_BIAS, arg);
1491 			if (err)
1492 				goto err;
1493 
1494 			break;
1495 
1496 		case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
1497 			arg = arg ? SCHMITT_BIT : 0;
1498 			err = ocelot_hw_set_value(info, pin, PINCONF_SCHMITT,
1499 						  arg);
1500 			if (err)
1501 				goto err;
1502 
1503 			break;
1504 
1505 		case PIN_CONFIG_DRIVE_STRENGTH:
1506 			err = ocelot_hw_set_value(info, pin,
1507 						  PINCONF_DRIVE_STRENGTH,
1508 						  arg);
1509 			if (err)
1510 				goto err;
1511 
1512 			break;
1513 
1514 		case PIN_CONFIG_OUTPUT_ENABLE:
1515 		case PIN_CONFIG_INPUT_ENABLE:
1516 		case PIN_CONFIG_OUTPUT:
1517 			p = pin % 32;
1518 			if (arg)
1519 				regmap_write(info->map,
1520 					     REG(OCELOT_GPIO_OUT_SET, info,
1521 						 pin),
1522 					     BIT(p));
1523 			else
1524 				regmap_write(info->map,
1525 					     REG(OCELOT_GPIO_OUT_CLR, info,
1526 						 pin),
1527 					     BIT(p));
1528 			regmap_update_bits(info->map,
1529 					   REG(OCELOT_GPIO_OE, info, pin),
1530 					   BIT(p),
1531 					   param == PIN_CONFIG_INPUT_ENABLE ?
1532 					   0 : BIT(p));
1533 			break;
1534 
1535 		default:
1536 			err = -EOPNOTSUPP;
1537 		}
1538 	}
1539 err:
1540 	return err;
1541 }
1542 
1543 static const struct pinconf_ops ocelot_confops = {
1544 	.is_generic = true,
1545 	.pin_config_get = ocelot_pinconf_get,
1546 	.pin_config_set = ocelot_pinconf_set,
1547 	.pin_config_config_dbg_show = pinconf_generic_dump_config,
1548 };
1549 
1550 static const struct pinctrl_ops ocelot_pctl_ops = {
1551 	.get_groups_count = ocelot_pctl_get_groups_count,
1552 	.get_group_name = ocelot_pctl_get_group_name,
1553 	.get_group_pins = ocelot_pctl_get_group_pins,
1554 	.dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
1555 	.dt_free_map = pinconf_generic_dt_free_map,
1556 };
1557 
1558 static struct pinctrl_desc luton_desc = {
1559 	.name = "luton-pinctrl",
1560 	.pins = luton_pins,
1561 	.npins = ARRAY_SIZE(luton_pins),
1562 	.pctlops = &ocelot_pctl_ops,
1563 	.pmxops = &ocelot_pmx_ops,
1564 	.owner = THIS_MODULE,
1565 };
1566 
1567 static struct pinctrl_desc serval_desc = {
1568 	.name = "serval-pinctrl",
1569 	.pins = serval_pins,
1570 	.npins = ARRAY_SIZE(serval_pins),
1571 	.pctlops = &ocelot_pctl_ops,
1572 	.pmxops = &ocelot_pmx_ops,
1573 	.owner = THIS_MODULE,
1574 };
1575 
1576 static struct pinctrl_desc ocelot_desc = {
1577 	.name = "ocelot-pinctrl",
1578 	.pins = ocelot_pins,
1579 	.npins = ARRAY_SIZE(ocelot_pins),
1580 	.pctlops = &ocelot_pctl_ops,
1581 	.pmxops = &ocelot_pmx_ops,
1582 	.owner = THIS_MODULE,
1583 };
1584 
1585 static struct pinctrl_desc jaguar2_desc = {
1586 	.name = "jaguar2-pinctrl",
1587 	.pins = jaguar2_pins,
1588 	.npins = ARRAY_SIZE(jaguar2_pins),
1589 	.pctlops = &ocelot_pctl_ops,
1590 	.pmxops = &ocelot_pmx_ops,
1591 	.owner = THIS_MODULE,
1592 };
1593 
1594 static struct pinctrl_desc servalt_desc = {
1595 	.name = "servalt-pinctrl",
1596 	.pins = servalt_pins,
1597 	.npins = ARRAY_SIZE(servalt_pins),
1598 	.pctlops = &ocelot_pctl_ops,
1599 	.pmxops = &ocelot_pmx_ops,
1600 	.owner = THIS_MODULE,
1601 };
1602 
1603 static struct pinctrl_desc sparx5_desc = {
1604 	.name = "sparx5-pinctrl",
1605 	.pins = sparx5_pins,
1606 	.npins = ARRAY_SIZE(sparx5_pins),
1607 	.pctlops = &ocelot_pctl_ops,
1608 	.pmxops = &ocelot_pmx_ops,
1609 	.confops = &ocelot_confops,
1610 	.owner = THIS_MODULE,
1611 };
1612 
1613 static struct pinctrl_desc lan966x_desc = {
1614 	.name = "lan966x-pinctrl",
1615 	.pins = lan966x_pins,
1616 	.npins = ARRAY_SIZE(lan966x_pins),
1617 	.pctlops = &ocelot_pctl_ops,
1618 	.pmxops = &lan966x_pmx_ops,
1619 	.confops = &ocelot_confops,
1620 	.owner = THIS_MODULE,
1621 };
1622 
1623 static int ocelot_create_group_func_map(struct device *dev,
1624 					struct ocelot_pinctrl *info)
1625 {
1626 	int f, npins, i;
1627 	u8 *pins = kcalloc(info->desc->npins, sizeof(u8), GFP_KERNEL);
1628 
1629 	if (!pins)
1630 		return -ENOMEM;
1631 
1632 	for (f = 0; f < FUNC_MAX; f++) {
1633 		for (npins = 0, i = 0; i < info->desc->npins; i++) {
1634 			if (ocelot_pin_function_idx(info, i, f) >= 0)
1635 				pins[npins++] = i;
1636 		}
1637 
1638 		if (!npins)
1639 			continue;
1640 
1641 		info->func[f].ngroups = npins;
1642 		info->func[f].groups = devm_kcalloc(dev, npins, sizeof(char *),
1643 						    GFP_KERNEL);
1644 		if (!info->func[f].groups) {
1645 			kfree(pins);
1646 			return -ENOMEM;
1647 		}
1648 
1649 		for (i = 0; i < npins; i++)
1650 			info->func[f].groups[i] =
1651 				info->desc->pins[pins[i]].name;
1652 	}
1653 
1654 	kfree(pins);
1655 
1656 	return 0;
1657 }
1658 
1659 static int ocelot_pinctrl_register(struct platform_device *pdev,
1660 				   struct ocelot_pinctrl *info)
1661 {
1662 	int ret;
1663 
1664 	ret = ocelot_create_group_func_map(&pdev->dev, info);
1665 	if (ret) {
1666 		dev_err(&pdev->dev, "Unable to create group func map.\n");
1667 		return ret;
1668 	}
1669 
1670 	info->pctl = devm_pinctrl_register(&pdev->dev, info->desc, info);
1671 	if (IS_ERR(info->pctl)) {
1672 		dev_err(&pdev->dev, "Failed to register pinctrl\n");
1673 		return PTR_ERR(info->pctl);
1674 	}
1675 
1676 	return 0;
1677 }
1678 
1679 static int ocelot_gpio_get(struct gpio_chip *chip, unsigned int offset)
1680 {
1681 	struct ocelot_pinctrl *info = gpiochip_get_data(chip);
1682 	unsigned int val;
1683 
1684 	regmap_read(info->map, REG(OCELOT_GPIO_IN, info, offset), &val);
1685 
1686 	return !!(val & BIT(offset % 32));
1687 }
1688 
1689 static void ocelot_gpio_set(struct gpio_chip *chip, unsigned int offset,
1690 			    int value)
1691 {
1692 	struct ocelot_pinctrl *info = gpiochip_get_data(chip);
1693 
1694 	if (value)
1695 		regmap_write(info->map, REG(OCELOT_GPIO_OUT_SET, info, offset),
1696 			     BIT(offset % 32));
1697 	else
1698 		regmap_write(info->map, REG(OCELOT_GPIO_OUT_CLR, info, offset),
1699 			     BIT(offset % 32));
1700 }
1701 
1702 static int ocelot_gpio_get_direction(struct gpio_chip *chip,
1703 				     unsigned int offset)
1704 {
1705 	struct ocelot_pinctrl *info = gpiochip_get_data(chip);
1706 	unsigned int val;
1707 
1708 	regmap_read(info->map, REG(OCELOT_GPIO_OE, info, offset), &val);
1709 
1710 	if (val & BIT(offset % 32))
1711 		return GPIO_LINE_DIRECTION_OUT;
1712 
1713 	return GPIO_LINE_DIRECTION_IN;
1714 }
1715 
1716 static int ocelot_gpio_direction_input(struct gpio_chip *chip,
1717 				       unsigned int offset)
1718 {
1719 	return pinctrl_gpio_direction_input(chip->base + offset);
1720 }
1721 
1722 static int ocelot_gpio_direction_output(struct gpio_chip *chip,
1723 					unsigned int offset, int value)
1724 {
1725 	struct ocelot_pinctrl *info = gpiochip_get_data(chip);
1726 	unsigned int pin = BIT(offset % 32);
1727 
1728 	if (value)
1729 		regmap_write(info->map, REG(OCELOT_GPIO_OUT_SET, info, offset),
1730 			     pin);
1731 	else
1732 		regmap_write(info->map, REG(OCELOT_GPIO_OUT_CLR, info, offset),
1733 			     pin);
1734 
1735 	return pinctrl_gpio_direction_output(chip->base + offset);
1736 }
1737 
1738 static const struct gpio_chip ocelot_gpiolib_chip = {
1739 	.request = gpiochip_generic_request,
1740 	.free = gpiochip_generic_free,
1741 	.set = ocelot_gpio_set,
1742 	.get = ocelot_gpio_get,
1743 	.get_direction = ocelot_gpio_get_direction,
1744 	.direction_input = ocelot_gpio_direction_input,
1745 	.direction_output = ocelot_gpio_direction_output,
1746 	.owner = THIS_MODULE,
1747 };
1748 
1749 static void ocelot_irq_mask(struct irq_data *data)
1750 {
1751 	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
1752 	struct ocelot_pinctrl *info = gpiochip_get_data(chip);
1753 	unsigned int gpio = irqd_to_hwirq(data);
1754 
1755 	regmap_update_bits(info->map, REG(OCELOT_GPIO_INTR_ENA, info, gpio),
1756 			   BIT(gpio % 32), 0);
1757 }
1758 
1759 static void ocelot_irq_unmask(struct irq_data *data)
1760 {
1761 	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
1762 	struct ocelot_pinctrl *info = gpiochip_get_data(chip);
1763 	unsigned int gpio = irqd_to_hwirq(data);
1764 
1765 	regmap_update_bits(info->map, REG(OCELOT_GPIO_INTR_ENA, info, gpio),
1766 			   BIT(gpio % 32), BIT(gpio % 32));
1767 }
1768 
1769 static void ocelot_irq_ack(struct irq_data *data)
1770 {
1771 	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
1772 	struct ocelot_pinctrl *info = gpiochip_get_data(chip);
1773 	unsigned int gpio = irqd_to_hwirq(data);
1774 
1775 	regmap_write_bits(info->map, REG(OCELOT_GPIO_INTR, info, gpio),
1776 			  BIT(gpio % 32), BIT(gpio % 32));
1777 }
1778 
1779 static int ocelot_irq_set_type(struct irq_data *data, unsigned int type);
1780 
1781 static struct irq_chip ocelot_eoi_irqchip = {
1782 	.name		= "gpio",
1783 	.irq_mask	= ocelot_irq_mask,
1784 	.irq_eoi	= ocelot_irq_ack,
1785 	.irq_unmask	= ocelot_irq_unmask,
1786 	.flags          = IRQCHIP_EOI_THREADED | IRQCHIP_EOI_IF_HANDLED,
1787 	.irq_set_type	= ocelot_irq_set_type,
1788 };
1789 
1790 static struct irq_chip ocelot_irqchip = {
1791 	.name		= "gpio",
1792 	.irq_mask	= ocelot_irq_mask,
1793 	.irq_ack	= ocelot_irq_ack,
1794 	.irq_unmask	= ocelot_irq_unmask,
1795 	.irq_set_type	= ocelot_irq_set_type,
1796 };
1797 
1798 static int ocelot_irq_set_type(struct irq_data *data, unsigned int type)
1799 {
1800 	type &= IRQ_TYPE_SENSE_MASK;
1801 
1802 	if (!(type & (IRQ_TYPE_EDGE_BOTH | IRQ_TYPE_LEVEL_HIGH)))
1803 		return -EINVAL;
1804 
1805 	if (type & IRQ_TYPE_LEVEL_HIGH)
1806 		irq_set_chip_handler_name_locked(data, &ocelot_eoi_irqchip,
1807 						 handle_fasteoi_irq, NULL);
1808 	if (type & IRQ_TYPE_EDGE_BOTH)
1809 		irq_set_chip_handler_name_locked(data, &ocelot_irqchip,
1810 						 handle_edge_irq, NULL);
1811 
1812 	return 0;
1813 }
1814 
1815 static void ocelot_irq_handler(struct irq_desc *desc)
1816 {
1817 	struct irq_chip *parent_chip = irq_desc_get_chip(desc);
1818 	struct gpio_chip *chip = irq_desc_get_handler_data(desc);
1819 	struct ocelot_pinctrl *info = gpiochip_get_data(chip);
1820 	unsigned int id_reg = OCELOT_GPIO_INTR_IDENT * info->stride;
1821 	unsigned int reg = 0, irq, i;
1822 	unsigned long irqs;
1823 
1824 	for (i = 0; i < info->stride; i++) {
1825 		regmap_read(info->map, id_reg + 4 * i, &reg);
1826 		if (!reg)
1827 			continue;
1828 
1829 		chained_irq_enter(parent_chip, desc);
1830 
1831 		irqs = reg;
1832 
1833 		for_each_set_bit(irq, &irqs,
1834 				 min(32U, info->desc->npins - 32 * i))
1835 			generic_handle_domain_irq(chip->irq.domain, irq + 32 * i);
1836 
1837 		chained_irq_exit(parent_chip, desc);
1838 	}
1839 }
1840 
1841 static int ocelot_gpiochip_register(struct platform_device *pdev,
1842 				    struct ocelot_pinctrl *info)
1843 {
1844 	struct gpio_chip *gc;
1845 	struct gpio_irq_chip *girq;
1846 	int irq;
1847 
1848 	info->gpio_chip = ocelot_gpiolib_chip;
1849 
1850 	gc = &info->gpio_chip;
1851 	gc->ngpio = info->desc->npins;
1852 	gc->parent = &pdev->dev;
1853 	gc->base = -1;
1854 	gc->label = "ocelot-gpio";
1855 
1856 	irq = platform_get_irq_optional(pdev, 0);
1857 	if (irq > 0) {
1858 		girq = &gc->irq;
1859 		girq->chip = &ocelot_irqchip;
1860 		girq->parent_handler = ocelot_irq_handler;
1861 		girq->num_parents = 1;
1862 		girq->parents = devm_kcalloc(&pdev->dev, 1,
1863 					     sizeof(*girq->parents),
1864 					     GFP_KERNEL);
1865 		if (!girq->parents)
1866 			return -ENOMEM;
1867 		girq->parents[0] = irq;
1868 		girq->default_type = IRQ_TYPE_NONE;
1869 		girq->handler = handle_edge_irq;
1870 	}
1871 
1872 	return devm_gpiochip_add_data(&pdev->dev, gc, info);
1873 }
1874 
1875 static const struct of_device_id ocelot_pinctrl_of_match[] = {
1876 	{ .compatible = "mscc,luton-pinctrl", .data = &luton_desc },
1877 	{ .compatible = "mscc,serval-pinctrl", .data = &serval_desc },
1878 	{ .compatible = "mscc,ocelot-pinctrl", .data = &ocelot_desc },
1879 	{ .compatible = "mscc,jaguar2-pinctrl", .data = &jaguar2_desc },
1880 	{ .compatible = "mscc,servalt-pinctrl", .data = &servalt_desc },
1881 	{ .compatible = "microchip,sparx5-pinctrl", .data = &sparx5_desc },
1882 	{ .compatible = "microchip,lan966x-pinctrl", .data = &lan966x_desc },
1883 	{},
1884 };
1885 
1886 static struct regmap *ocelot_pinctrl_create_pincfg(struct platform_device *pdev)
1887 {
1888 	void __iomem *base;
1889 
1890 	const struct regmap_config regmap_config = {
1891 		.reg_bits = 32,
1892 		.val_bits = 32,
1893 		.reg_stride = 4,
1894 		.max_register = 32,
1895 		.name = "pincfg",
1896 	};
1897 
1898 	base = devm_platform_ioremap_resource(pdev, 1);
1899 	if (IS_ERR(base)) {
1900 		dev_dbg(&pdev->dev, "Failed to ioremap config registers (no extended pinconf)\n");
1901 		return NULL;
1902 	}
1903 
1904 	return devm_regmap_init_mmio(&pdev->dev, base, &regmap_config);
1905 }
1906 
1907 static int ocelot_pinctrl_probe(struct platform_device *pdev)
1908 {
1909 	struct device *dev = &pdev->dev;
1910 	struct ocelot_pinctrl *info;
1911 	struct regmap *pincfg;
1912 	void __iomem *base;
1913 	int ret;
1914 	struct regmap_config regmap_config = {
1915 		.reg_bits = 32,
1916 		.val_bits = 32,
1917 		.reg_stride = 4,
1918 	};
1919 
1920 	info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
1921 	if (!info)
1922 		return -ENOMEM;
1923 
1924 	info->desc = (struct pinctrl_desc *)device_get_match_data(dev);
1925 
1926 	base = devm_ioremap_resource(dev,
1927 			platform_get_resource(pdev, IORESOURCE_MEM, 0));
1928 	if (IS_ERR(base))
1929 		return PTR_ERR(base);
1930 
1931 	info->stride = 1 + (info->desc->npins - 1) / 32;
1932 
1933 	regmap_config.max_register = OCELOT_GPIO_SD_MAP * info->stride + 15 * 4;
1934 
1935 	info->map = devm_regmap_init_mmio(dev, base, &regmap_config);
1936 	if (IS_ERR(info->map)) {
1937 		dev_err(dev, "Failed to create regmap\n");
1938 		return PTR_ERR(info->map);
1939 	}
1940 	dev_set_drvdata(dev, info->map);
1941 	info->dev = dev;
1942 
1943 	/* Pinconf registers */
1944 	if (info->desc->confops) {
1945 		pincfg = ocelot_pinctrl_create_pincfg(pdev);
1946 		if (IS_ERR(pincfg))
1947 			dev_dbg(dev, "Failed to create pincfg regmap\n");
1948 		else
1949 			info->pincfg = pincfg;
1950 	}
1951 
1952 	ret = ocelot_pinctrl_register(pdev, info);
1953 	if (ret)
1954 		return ret;
1955 
1956 	ret = ocelot_gpiochip_register(pdev, info);
1957 	if (ret)
1958 		return ret;
1959 
1960 	dev_info(dev, "driver registered\n");
1961 
1962 	return 0;
1963 }
1964 
1965 static struct platform_driver ocelot_pinctrl_driver = {
1966 	.driver = {
1967 		.name = "pinctrl-ocelot",
1968 		.of_match_table = of_match_ptr(ocelot_pinctrl_of_match),
1969 		.suppress_bind_attrs = true,
1970 	},
1971 	.probe = ocelot_pinctrl_probe,
1972 };
1973 builtin_platform_driver(ocelot_pinctrl_driver);
1974