1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* 3 * Microsemi SoCs pinctrl driver 4 * 5 * Author: <alexandre.belloni@free-electrons.com> 6 * License: Dual MIT/GPL 7 * Copyright (c) 2017 Microsemi Corporation 8 */ 9 10 #include <linux/gpio/driver.h> 11 #include <linux/interrupt.h> 12 #include <linux/io.h> 13 #include <linux/of_device.h> 14 #include <linux/of_irq.h> 15 #include <linux/of_platform.h> 16 #include <linux/pinctrl/pinctrl.h> 17 #include <linux/pinctrl/pinmux.h> 18 #include <linux/pinctrl/pinconf.h> 19 #include <linux/pinctrl/pinconf-generic.h> 20 #include <linux/platform_device.h> 21 #include <linux/regmap.h> 22 #include <linux/reset.h> 23 #include <linux/slab.h> 24 25 #include "core.h" 26 #include "pinconf.h" 27 #include "pinmux.h" 28 29 #define ocelot_clrsetbits(addr, clear, set) \ 30 writel((readl(addr) & ~(clear)) | (set), (addr)) 31 32 enum { 33 PINCONF_BIAS, 34 PINCONF_SCHMITT, 35 PINCONF_DRIVE_STRENGTH, 36 }; 37 38 /* GPIO standard registers */ 39 #define OCELOT_GPIO_OUT_SET 0x0 40 #define OCELOT_GPIO_OUT_CLR 0x4 41 #define OCELOT_GPIO_OUT 0x8 42 #define OCELOT_GPIO_IN 0xc 43 #define OCELOT_GPIO_OE 0x10 44 #define OCELOT_GPIO_INTR 0x14 45 #define OCELOT_GPIO_INTR_ENA 0x18 46 #define OCELOT_GPIO_INTR_IDENT 0x1c 47 #define OCELOT_GPIO_ALT0 0x20 48 #define OCELOT_GPIO_ALT1 0x24 49 #define OCELOT_GPIO_SD_MAP 0x28 50 51 #define OCELOT_FUNC_PER_PIN 4 52 53 enum { 54 FUNC_CAN0_a, 55 FUNC_CAN0_b, 56 FUNC_CAN1, 57 FUNC_CLKMON, 58 FUNC_NONE, 59 FUNC_FC0_a, 60 FUNC_FC0_b, 61 FUNC_FC0_c, 62 FUNC_FC1_a, 63 FUNC_FC1_b, 64 FUNC_FC1_c, 65 FUNC_FC2_a, 66 FUNC_FC2_b, 67 FUNC_FC3_a, 68 FUNC_FC3_b, 69 FUNC_FC3_c, 70 FUNC_FC4_a, 71 FUNC_FC4_b, 72 FUNC_FC4_c, 73 FUNC_FC_SHRD0, 74 FUNC_FC_SHRD1, 75 FUNC_FC_SHRD2, 76 FUNC_FC_SHRD3, 77 FUNC_FC_SHRD4, 78 FUNC_FC_SHRD5, 79 FUNC_FC_SHRD6, 80 FUNC_FC_SHRD7, 81 FUNC_FC_SHRD8, 82 FUNC_FC_SHRD9, 83 FUNC_FC_SHRD10, 84 FUNC_FC_SHRD11, 85 FUNC_FC_SHRD12, 86 FUNC_FC_SHRD13, 87 FUNC_FC_SHRD14, 88 FUNC_FC_SHRD15, 89 FUNC_FC_SHRD16, 90 FUNC_FC_SHRD17, 91 FUNC_FC_SHRD18, 92 FUNC_FC_SHRD19, 93 FUNC_FC_SHRD20, 94 FUNC_GPIO, 95 FUNC_IB_TRG_a, 96 FUNC_IB_TRG_b, 97 FUNC_IB_TRG_c, 98 FUNC_IRQ0, 99 FUNC_IRQ_IN_a, 100 FUNC_IRQ_IN_b, 101 FUNC_IRQ_IN_c, 102 FUNC_IRQ0_IN, 103 FUNC_IRQ_OUT_a, 104 FUNC_IRQ_OUT_b, 105 FUNC_IRQ_OUT_c, 106 FUNC_IRQ0_OUT, 107 FUNC_IRQ1, 108 FUNC_IRQ1_IN, 109 FUNC_IRQ1_OUT, 110 FUNC_EXT_IRQ, 111 FUNC_MIIM, 112 FUNC_MIIM_a, 113 FUNC_MIIM_b, 114 FUNC_MIIM_c, 115 FUNC_MIIM_Sa, 116 FUNC_MIIM_Sb, 117 FUNC_OB_TRG, 118 FUNC_OB_TRG_a, 119 FUNC_OB_TRG_b, 120 FUNC_PHY_LED, 121 FUNC_PCI_WAKE, 122 FUNC_MD, 123 FUNC_PTP0, 124 FUNC_PTP1, 125 FUNC_PTP2, 126 FUNC_PTP3, 127 FUNC_PTPSYNC_0, 128 FUNC_PTPSYNC_1, 129 FUNC_PTPSYNC_2, 130 FUNC_PTPSYNC_3, 131 FUNC_PTPSYNC_4, 132 FUNC_PTPSYNC_5, 133 FUNC_PTPSYNC_6, 134 FUNC_PTPSYNC_7, 135 FUNC_PWM, 136 FUNC_PWM_a, 137 FUNC_PWM_b, 138 FUNC_QSPI1, 139 FUNC_QSPI2, 140 FUNC_R, 141 FUNC_RECO_a, 142 FUNC_RECO_b, 143 FUNC_RECO_CLK, 144 FUNC_SD, 145 FUNC_SFP, 146 FUNC_SFP_SD, 147 FUNC_SG0, 148 FUNC_SG1, 149 FUNC_SG2, 150 FUNC_SGPIO_a, 151 FUNC_SGPIO_b, 152 FUNC_SI, 153 FUNC_SI2, 154 FUNC_TACHO, 155 FUNC_TACHO_a, 156 FUNC_TACHO_b, 157 FUNC_TWI, 158 FUNC_TWI2, 159 FUNC_TWI3, 160 FUNC_TWI_SCL_M, 161 FUNC_TWI_SLC_GATE, 162 FUNC_TWI_SLC_GATE_AD, 163 FUNC_UART, 164 FUNC_UART2, 165 FUNC_UART3, 166 FUNC_USB_H_a, 167 FUNC_USB_H_b, 168 FUNC_USB_H_c, 169 FUNC_USB_S_a, 170 FUNC_USB_S_b, 171 FUNC_USB_S_c, 172 FUNC_PLL_STAT, 173 FUNC_EMMC, 174 FUNC_EMMC_SD, 175 FUNC_REF_CLK, 176 FUNC_RCVRD_CLK, 177 FUNC_MAX 178 }; 179 180 static const char *const ocelot_function_names[] = { 181 [FUNC_CAN0_a] = "can0_a", 182 [FUNC_CAN0_b] = "can0_b", 183 [FUNC_CAN1] = "can1", 184 [FUNC_CLKMON] = "clkmon", 185 [FUNC_NONE] = "none", 186 [FUNC_FC0_a] = "fc0_a", 187 [FUNC_FC0_b] = "fc0_b", 188 [FUNC_FC0_c] = "fc0_c", 189 [FUNC_FC1_a] = "fc1_a", 190 [FUNC_FC1_b] = "fc1_b", 191 [FUNC_FC1_c] = "fc1_c", 192 [FUNC_FC2_a] = "fc2_a", 193 [FUNC_FC2_b] = "fc2_b", 194 [FUNC_FC3_a] = "fc3_a", 195 [FUNC_FC3_b] = "fc3_b", 196 [FUNC_FC3_c] = "fc3_c", 197 [FUNC_FC4_a] = "fc4_a", 198 [FUNC_FC4_b] = "fc4_b", 199 [FUNC_FC4_c] = "fc4_c", 200 [FUNC_FC_SHRD0] = "fc_shrd0", 201 [FUNC_FC_SHRD1] = "fc_shrd1", 202 [FUNC_FC_SHRD2] = "fc_shrd2", 203 [FUNC_FC_SHRD3] = "fc_shrd3", 204 [FUNC_FC_SHRD4] = "fc_shrd4", 205 [FUNC_FC_SHRD5] = "fc_shrd5", 206 [FUNC_FC_SHRD6] = "fc_shrd6", 207 [FUNC_FC_SHRD7] = "fc_shrd7", 208 [FUNC_FC_SHRD8] = "fc_shrd8", 209 [FUNC_FC_SHRD9] = "fc_shrd9", 210 [FUNC_FC_SHRD10] = "fc_shrd10", 211 [FUNC_FC_SHRD11] = "fc_shrd11", 212 [FUNC_FC_SHRD12] = "fc_shrd12", 213 [FUNC_FC_SHRD13] = "fc_shrd13", 214 [FUNC_FC_SHRD14] = "fc_shrd14", 215 [FUNC_FC_SHRD15] = "fc_shrd15", 216 [FUNC_FC_SHRD16] = "fc_shrd16", 217 [FUNC_FC_SHRD17] = "fc_shrd17", 218 [FUNC_FC_SHRD18] = "fc_shrd18", 219 [FUNC_FC_SHRD19] = "fc_shrd19", 220 [FUNC_FC_SHRD20] = "fc_shrd20", 221 [FUNC_GPIO] = "gpio", 222 [FUNC_IB_TRG_a] = "ib_trig_a", 223 [FUNC_IB_TRG_b] = "ib_trig_b", 224 [FUNC_IB_TRG_c] = "ib_trig_c", 225 [FUNC_IRQ0] = "irq0", 226 [FUNC_IRQ_IN_a] = "irq_in_a", 227 [FUNC_IRQ_IN_b] = "irq_in_b", 228 [FUNC_IRQ_IN_c] = "irq_in_c", 229 [FUNC_IRQ0_IN] = "irq0_in", 230 [FUNC_IRQ_OUT_a] = "irq_out_a", 231 [FUNC_IRQ_OUT_b] = "irq_out_b", 232 [FUNC_IRQ_OUT_c] = "irq_out_c", 233 [FUNC_IRQ0_OUT] = "irq0_out", 234 [FUNC_IRQ1] = "irq1", 235 [FUNC_IRQ1_IN] = "irq1_in", 236 [FUNC_IRQ1_OUT] = "irq1_out", 237 [FUNC_EXT_IRQ] = "ext_irq", 238 [FUNC_MIIM] = "miim", 239 [FUNC_MIIM_a] = "miim_a", 240 [FUNC_MIIM_b] = "miim_b", 241 [FUNC_MIIM_c] = "miim_c", 242 [FUNC_MIIM_Sa] = "miim_slave_a", 243 [FUNC_MIIM_Sb] = "miim_slave_b", 244 [FUNC_PHY_LED] = "phy_led", 245 [FUNC_PCI_WAKE] = "pci_wake", 246 [FUNC_MD] = "md", 247 [FUNC_OB_TRG] = "ob_trig", 248 [FUNC_OB_TRG_a] = "ob_trig_a", 249 [FUNC_OB_TRG_b] = "ob_trig_b", 250 [FUNC_PTP0] = "ptp0", 251 [FUNC_PTP1] = "ptp1", 252 [FUNC_PTP2] = "ptp2", 253 [FUNC_PTP3] = "ptp3", 254 [FUNC_PTPSYNC_0] = "ptpsync_0", 255 [FUNC_PTPSYNC_1] = "ptpsync_1", 256 [FUNC_PTPSYNC_2] = "ptpsync_2", 257 [FUNC_PTPSYNC_3] = "ptpsync_3", 258 [FUNC_PTPSYNC_4] = "ptpsync_4", 259 [FUNC_PTPSYNC_5] = "ptpsync_5", 260 [FUNC_PTPSYNC_6] = "ptpsync_6", 261 [FUNC_PTPSYNC_7] = "ptpsync_7", 262 [FUNC_PWM] = "pwm", 263 [FUNC_PWM_a] = "pwm_a", 264 [FUNC_PWM_b] = "pwm_b", 265 [FUNC_QSPI1] = "qspi1", 266 [FUNC_QSPI2] = "qspi2", 267 [FUNC_R] = "reserved", 268 [FUNC_RECO_a] = "reco_a", 269 [FUNC_RECO_b] = "reco_b", 270 [FUNC_RECO_CLK] = "reco_clk", 271 [FUNC_SD] = "sd", 272 [FUNC_SFP] = "sfp", 273 [FUNC_SFP_SD] = "sfp_sd", 274 [FUNC_SG0] = "sg0", 275 [FUNC_SG1] = "sg1", 276 [FUNC_SG2] = "sg2", 277 [FUNC_SGPIO_a] = "sgpio_a", 278 [FUNC_SGPIO_b] = "sgpio_b", 279 [FUNC_SI] = "si", 280 [FUNC_SI2] = "si2", 281 [FUNC_TACHO] = "tacho", 282 [FUNC_TACHO_a] = "tacho_a", 283 [FUNC_TACHO_b] = "tacho_b", 284 [FUNC_TWI] = "twi", 285 [FUNC_TWI2] = "twi2", 286 [FUNC_TWI3] = "twi3", 287 [FUNC_TWI_SCL_M] = "twi_scl_m", 288 [FUNC_TWI_SLC_GATE] = "twi_slc_gate", 289 [FUNC_TWI_SLC_GATE_AD] = "twi_slc_gate_ad", 290 [FUNC_USB_H_a] = "usb_host_a", 291 [FUNC_USB_H_b] = "usb_host_b", 292 [FUNC_USB_H_c] = "usb_host_c", 293 [FUNC_USB_S_a] = "usb_slave_a", 294 [FUNC_USB_S_b] = "usb_slave_b", 295 [FUNC_USB_S_c] = "usb_slave_c", 296 [FUNC_UART] = "uart", 297 [FUNC_UART2] = "uart2", 298 [FUNC_UART3] = "uart3", 299 [FUNC_PLL_STAT] = "pll_stat", 300 [FUNC_EMMC] = "emmc", 301 [FUNC_EMMC_SD] = "emmc_sd", 302 [FUNC_REF_CLK] = "ref_clk", 303 [FUNC_RCVRD_CLK] = "rcvrd_clk", 304 }; 305 306 struct ocelot_pmx_func { 307 const char **groups; 308 unsigned int ngroups; 309 }; 310 311 struct ocelot_pin_caps { 312 unsigned int pin; 313 unsigned char functions[OCELOT_FUNC_PER_PIN]; 314 unsigned char a_functions[OCELOT_FUNC_PER_PIN]; /* Additional functions */ 315 }; 316 317 struct ocelot_pincfg_data { 318 u8 pd_bit; 319 u8 pu_bit; 320 u8 drive_bits; 321 u8 schmitt_bit; 322 }; 323 324 struct ocelot_pinctrl { 325 struct device *dev; 326 struct pinctrl_dev *pctl; 327 struct gpio_chip gpio_chip; 328 struct regmap *map; 329 struct regmap *pincfg; 330 struct pinctrl_desc *desc; 331 const struct ocelot_pincfg_data *pincfg_data; 332 struct ocelot_pmx_func func[FUNC_MAX]; 333 u8 stride; 334 struct workqueue_struct *wq; 335 }; 336 337 struct ocelot_match_data { 338 struct pinctrl_desc desc; 339 struct ocelot_pincfg_data pincfg_data; 340 }; 341 342 struct ocelot_irq_work { 343 struct work_struct irq_work; 344 struct irq_desc *irq_desc; 345 }; 346 347 #define LUTON_P(p, f0, f1) \ 348 static struct ocelot_pin_caps luton_pin_##p = { \ 349 .pin = p, \ 350 .functions = { \ 351 FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_NONE, \ 352 }, \ 353 } 354 355 LUTON_P(0, SG0, NONE); 356 LUTON_P(1, SG0, NONE); 357 LUTON_P(2, SG0, NONE); 358 LUTON_P(3, SG0, NONE); 359 LUTON_P(4, TACHO, NONE); 360 LUTON_P(5, TWI, PHY_LED); 361 LUTON_P(6, TWI, PHY_LED); 362 LUTON_P(7, NONE, PHY_LED); 363 LUTON_P(8, EXT_IRQ, PHY_LED); 364 LUTON_P(9, EXT_IRQ, PHY_LED); 365 LUTON_P(10, SFP, PHY_LED); 366 LUTON_P(11, SFP, PHY_LED); 367 LUTON_P(12, SFP, PHY_LED); 368 LUTON_P(13, SFP, PHY_LED); 369 LUTON_P(14, SI, PHY_LED); 370 LUTON_P(15, SI, PHY_LED); 371 LUTON_P(16, SI, PHY_LED); 372 LUTON_P(17, SFP, PHY_LED); 373 LUTON_P(18, SFP, PHY_LED); 374 LUTON_P(19, SFP, PHY_LED); 375 LUTON_P(20, SFP, PHY_LED); 376 LUTON_P(21, SFP, PHY_LED); 377 LUTON_P(22, SFP, PHY_LED); 378 LUTON_P(23, SFP, PHY_LED); 379 LUTON_P(24, SFP, PHY_LED); 380 LUTON_P(25, SFP, PHY_LED); 381 LUTON_P(26, SFP, PHY_LED); 382 LUTON_P(27, SFP, PHY_LED); 383 LUTON_P(28, SFP, PHY_LED); 384 LUTON_P(29, PWM, NONE); 385 LUTON_P(30, UART, NONE); 386 LUTON_P(31, UART, NONE); 387 388 #define LUTON_PIN(n) { \ 389 .number = n, \ 390 .name = "GPIO_"#n, \ 391 .drv_data = &luton_pin_##n \ 392 } 393 394 static const struct pinctrl_pin_desc luton_pins[] = { 395 LUTON_PIN(0), 396 LUTON_PIN(1), 397 LUTON_PIN(2), 398 LUTON_PIN(3), 399 LUTON_PIN(4), 400 LUTON_PIN(5), 401 LUTON_PIN(6), 402 LUTON_PIN(7), 403 LUTON_PIN(8), 404 LUTON_PIN(9), 405 LUTON_PIN(10), 406 LUTON_PIN(11), 407 LUTON_PIN(12), 408 LUTON_PIN(13), 409 LUTON_PIN(14), 410 LUTON_PIN(15), 411 LUTON_PIN(16), 412 LUTON_PIN(17), 413 LUTON_PIN(18), 414 LUTON_PIN(19), 415 LUTON_PIN(20), 416 LUTON_PIN(21), 417 LUTON_PIN(22), 418 LUTON_PIN(23), 419 LUTON_PIN(24), 420 LUTON_PIN(25), 421 LUTON_PIN(26), 422 LUTON_PIN(27), 423 LUTON_PIN(28), 424 LUTON_PIN(29), 425 LUTON_PIN(30), 426 LUTON_PIN(31), 427 }; 428 429 #define SERVAL_P(p, f0, f1, f2) \ 430 static struct ocelot_pin_caps serval_pin_##p = { \ 431 .pin = p, \ 432 .functions = { \ 433 FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2, \ 434 }, \ 435 } 436 437 SERVAL_P(0, SG0, NONE, NONE); 438 SERVAL_P(1, SG0, NONE, NONE); 439 SERVAL_P(2, SG0, NONE, NONE); 440 SERVAL_P(3, SG0, NONE, NONE); 441 SERVAL_P(4, TACHO, NONE, NONE); 442 SERVAL_P(5, PWM, NONE, NONE); 443 SERVAL_P(6, TWI, NONE, NONE); 444 SERVAL_P(7, TWI, NONE, NONE); 445 SERVAL_P(8, SI, NONE, NONE); 446 SERVAL_P(9, SI, MD, NONE); 447 SERVAL_P(10, SI, MD, NONE); 448 SERVAL_P(11, SFP, MD, TWI_SCL_M); 449 SERVAL_P(12, SFP, MD, TWI_SCL_M); 450 SERVAL_P(13, SFP, UART2, TWI_SCL_M); 451 SERVAL_P(14, SFP, UART2, TWI_SCL_M); 452 SERVAL_P(15, SFP, PTP0, TWI_SCL_M); 453 SERVAL_P(16, SFP, PTP0, TWI_SCL_M); 454 SERVAL_P(17, SFP, PCI_WAKE, TWI_SCL_M); 455 SERVAL_P(18, SFP, NONE, TWI_SCL_M); 456 SERVAL_P(19, SFP, NONE, TWI_SCL_M); 457 SERVAL_P(20, SFP, NONE, TWI_SCL_M); 458 SERVAL_P(21, SFP, NONE, TWI_SCL_M); 459 SERVAL_P(22, NONE, NONE, NONE); 460 SERVAL_P(23, NONE, NONE, NONE); 461 SERVAL_P(24, NONE, NONE, NONE); 462 SERVAL_P(25, NONE, NONE, NONE); 463 SERVAL_P(26, UART, NONE, NONE); 464 SERVAL_P(27, UART, NONE, NONE); 465 SERVAL_P(28, IRQ0, NONE, NONE); 466 SERVAL_P(29, IRQ1, NONE, NONE); 467 SERVAL_P(30, PTP0, NONE, NONE); 468 SERVAL_P(31, PTP0, NONE, NONE); 469 470 #define SERVAL_PIN(n) { \ 471 .number = n, \ 472 .name = "GPIO_"#n, \ 473 .drv_data = &serval_pin_##n \ 474 } 475 476 static const struct pinctrl_pin_desc serval_pins[] = { 477 SERVAL_PIN(0), 478 SERVAL_PIN(1), 479 SERVAL_PIN(2), 480 SERVAL_PIN(3), 481 SERVAL_PIN(4), 482 SERVAL_PIN(5), 483 SERVAL_PIN(6), 484 SERVAL_PIN(7), 485 SERVAL_PIN(8), 486 SERVAL_PIN(9), 487 SERVAL_PIN(10), 488 SERVAL_PIN(11), 489 SERVAL_PIN(12), 490 SERVAL_PIN(13), 491 SERVAL_PIN(14), 492 SERVAL_PIN(15), 493 SERVAL_PIN(16), 494 SERVAL_PIN(17), 495 SERVAL_PIN(18), 496 SERVAL_PIN(19), 497 SERVAL_PIN(20), 498 SERVAL_PIN(21), 499 SERVAL_PIN(22), 500 SERVAL_PIN(23), 501 SERVAL_PIN(24), 502 SERVAL_PIN(25), 503 SERVAL_PIN(26), 504 SERVAL_PIN(27), 505 SERVAL_PIN(28), 506 SERVAL_PIN(29), 507 SERVAL_PIN(30), 508 SERVAL_PIN(31), 509 }; 510 511 #define OCELOT_P(p, f0, f1, f2) \ 512 static struct ocelot_pin_caps ocelot_pin_##p = { \ 513 .pin = p, \ 514 .functions = { \ 515 FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2, \ 516 }, \ 517 } 518 519 OCELOT_P(0, SG0, NONE, NONE); 520 OCELOT_P(1, SG0, NONE, NONE); 521 OCELOT_P(2, SG0, NONE, NONE); 522 OCELOT_P(3, SG0, NONE, NONE); 523 OCELOT_P(4, IRQ0_IN, IRQ0_OUT, TWI_SCL_M); 524 OCELOT_P(5, IRQ1_IN, IRQ1_OUT, PCI_WAKE); 525 OCELOT_P(6, UART, TWI_SCL_M, NONE); 526 OCELOT_P(7, UART, TWI_SCL_M, NONE); 527 OCELOT_P(8, SI, TWI_SCL_M, IRQ0_OUT); 528 OCELOT_P(9, SI, TWI_SCL_M, IRQ1_OUT); 529 OCELOT_P(10, PTP2, TWI_SCL_M, SFP); 530 OCELOT_P(11, PTP3, TWI_SCL_M, SFP); 531 OCELOT_P(12, UART2, TWI_SCL_M, SFP); 532 OCELOT_P(13, UART2, TWI_SCL_M, SFP); 533 OCELOT_P(14, MIIM, TWI_SCL_M, SFP); 534 OCELOT_P(15, MIIM, TWI_SCL_M, SFP); 535 OCELOT_P(16, TWI, NONE, SI); 536 OCELOT_P(17, TWI, TWI_SCL_M, SI); 537 OCELOT_P(18, PTP0, TWI_SCL_M, NONE); 538 OCELOT_P(19, PTP1, TWI_SCL_M, NONE); 539 OCELOT_P(20, RECO_CLK, TACHO, TWI_SCL_M); 540 OCELOT_P(21, RECO_CLK, PWM, TWI_SCL_M); 541 542 #define OCELOT_PIN(n) { \ 543 .number = n, \ 544 .name = "GPIO_"#n, \ 545 .drv_data = &ocelot_pin_##n \ 546 } 547 548 static const struct pinctrl_pin_desc ocelot_pins[] = { 549 OCELOT_PIN(0), 550 OCELOT_PIN(1), 551 OCELOT_PIN(2), 552 OCELOT_PIN(3), 553 OCELOT_PIN(4), 554 OCELOT_PIN(5), 555 OCELOT_PIN(6), 556 OCELOT_PIN(7), 557 OCELOT_PIN(8), 558 OCELOT_PIN(9), 559 OCELOT_PIN(10), 560 OCELOT_PIN(11), 561 OCELOT_PIN(12), 562 OCELOT_PIN(13), 563 OCELOT_PIN(14), 564 OCELOT_PIN(15), 565 OCELOT_PIN(16), 566 OCELOT_PIN(17), 567 OCELOT_PIN(18), 568 OCELOT_PIN(19), 569 OCELOT_PIN(20), 570 OCELOT_PIN(21), 571 }; 572 573 #define JAGUAR2_P(p, f0, f1) \ 574 static struct ocelot_pin_caps jaguar2_pin_##p = { \ 575 .pin = p, \ 576 .functions = { \ 577 FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_NONE \ 578 }, \ 579 } 580 581 JAGUAR2_P(0, SG0, NONE); 582 JAGUAR2_P(1, SG0, NONE); 583 JAGUAR2_P(2, SG0, NONE); 584 JAGUAR2_P(3, SG0, NONE); 585 JAGUAR2_P(4, SG1, NONE); 586 JAGUAR2_P(5, SG1, NONE); 587 JAGUAR2_P(6, IRQ0_IN, IRQ0_OUT); 588 JAGUAR2_P(7, IRQ1_IN, IRQ1_OUT); 589 JAGUAR2_P(8, PTP0, NONE); 590 JAGUAR2_P(9, PTP1, NONE); 591 JAGUAR2_P(10, UART, NONE); 592 JAGUAR2_P(11, UART, NONE); 593 JAGUAR2_P(12, SG1, NONE); 594 JAGUAR2_P(13, SG1, NONE); 595 JAGUAR2_P(14, TWI, TWI_SCL_M); 596 JAGUAR2_P(15, TWI, NONE); 597 JAGUAR2_P(16, SI, TWI_SCL_M); 598 JAGUAR2_P(17, SI, TWI_SCL_M); 599 JAGUAR2_P(18, SI, TWI_SCL_M); 600 JAGUAR2_P(19, PCI_WAKE, NONE); 601 JAGUAR2_P(20, IRQ0_OUT, TWI_SCL_M); 602 JAGUAR2_P(21, IRQ1_OUT, TWI_SCL_M); 603 JAGUAR2_P(22, TACHO, NONE); 604 JAGUAR2_P(23, PWM, NONE); 605 JAGUAR2_P(24, UART2, NONE); 606 JAGUAR2_P(25, UART2, SI); 607 JAGUAR2_P(26, PTP2, SI); 608 JAGUAR2_P(27, PTP3, SI); 609 JAGUAR2_P(28, TWI2, SI); 610 JAGUAR2_P(29, TWI2, SI); 611 JAGUAR2_P(30, SG2, SI); 612 JAGUAR2_P(31, SG2, SI); 613 JAGUAR2_P(32, SG2, SI); 614 JAGUAR2_P(33, SG2, SI); 615 JAGUAR2_P(34, NONE, TWI_SCL_M); 616 JAGUAR2_P(35, NONE, TWI_SCL_M); 617 JAGUAR2_P(36, NONE, TWI_SCL_M); 618 JAGUAR2_P(37, NONE, TWI_SCL_M); 619 JAGUAR2_P(38, NONE, TWI_SCL_M); 620 JAGUAR2_P(39, NONE, TWI_SCL_M); 621 JAGUAR2_P(40, NONE, TWI_SCL_M); 622 JAGUAR2_P(41, NONE, TWI_SCL_M); 623 JAGUAR2_P(42, NONE, TWI_SCL_M); 624 JAGUAR2_P(43, NONE, TWI_SCL_M); 625 JAGUAR2_P(44, NONE, SFP); 626 JAGUAR2_P(45, NONE, SFP); 627 JAGUAR2_P(46, NONE, SFP); 628 JAGUAR2_P(47, NONE, SFP); 629 JAGUAR2_P(48, SFP, NONE); 630 JAGUAR2_P(49, SFP, SI); 631 JAGUAR2_P(50, SFP, SI); 632 JAGUAR2_P(51, SFP, SI); 633 JAGUAR2_P(52, SFP, NONE); 634 JAGUAR2_P(53, SFP, NONE); 635 JAGUAR2_P(54, SFP, NONE); 636 JAGUAR2_P(55, SFP, NONE); 637 JAGUAR2_P(56, MIIM, SFP); 638 JAGUAR2_P(57, MIIM, SFP); 639 JAGUAR2_P(58, MIIM, SFP); 640 JAGUAR2_P(59, MIIM, SFP); 641 JAGUAR2_P(60, NONE, NONE); 642 JAGUAR2_P(61, NONE, NONE); 643 JAGUAR2_P(62, NONE, NONE); 644 JAGUAR2_P(63, NONE, NONE); 645 646 #define JAGUAR2_PIN(n) { \ 647 .number = n, \ 648 .name = "GPIO_"#n, \ 649 .drv_data = &jaguar2_pin_##n \ 650 } 651 652 static const struct pinctrl_pin_desc jaguar2_pins[] = { 653 JAGUAR2_PIN(0), 654 JAGUAR2_PIN(1), 655 JAGUAR2_PIN(2), 656 JAGUAR2_PIN(3), 657 JAGUAR2_PIN(4), 658 JAGUAR2_PIN(5), 659 JAGUAR2_PIN(6), 660 JAGUAR2_PIN(7), 661 JAGUAR2_PIN(8), 662 JAGUAR2_PIN(9), 663 JAGUAR2_PIN(10), 664 JAGUAR2_PIN(11), 665 JAGUAR2_PIN(12), 666 JAGUAR2_PIN(13), 667 JAGUAR2_PIN(14), 668 JAGUAR2_PIN(15), 669 JAGUAR2_PIN(16), 670 JAGUAR2_PIN(17), 671 JAGUAR2_PIN(18), 672 JAGUAR2_PIN(19), 673 JAGUAR2_PIN(20), 674 JAGUAR2_PIN(21), 675 JAGUAR2_PIN(22), 676 JAGUAR2_PIN(23), 677 JAGUAR2_PIN(24), 678 JAGUAR2_PIN(25), 679 JAGUAR2_PIN(26), 680 JAGUAR2_PIN(27), 681 JAGUAR2_PIN(28), 682 JAGUAR2_PIN(29), 683 JAGUAR2_PIN(30), 684 JAGUAR2_PIN(31), 685 JAGUAR2_PIN(32), 686 JAGUAR2_PIN(33), 687 JAGUAR2_PIN(34), 688 JAGUAR2_PIN(35), 689 JAGUAR2_PIN(36), 690 JAGUAR2_PIN(37), 691 JAGUAR2_PIN(38), 692 JAGUAR2_PIN(39), 693 JAGUAR2_PIN(40), 694 JAGUAR2_PIN(41), 695 JAGUAR2_PIN(42), 696 JAGUAR2_PIN(43), 697 JAGUAR2_PIN(44), 698 JAGUAR2_PIN(45), 699 JAGUAR2_PIN(46), 700 JAGUAR2_PIN(47), 701 JAGUAR2_PIN(48), 702 JAGUAR2_PIN(49), 703 JAGUAR2_PIN(50), 704 JAGUAR2_PIN(51), 705 JAGUAR2_PIN(52), 706 JAGUAR2_PIN(53), 707 JAGUAR2_PIN(54), 708 JAGUAR2_PIN(55), 709 JAGUAR2_PIN(56), 710 JAGUAR2_PIN(57), 711 JAGUAR2_PIN(58), 712 JAGUAR2_PIN(59), 713 JAGUAR2_PIN(60), 714 JAGUAR2_PIN(61), 715 JAGUAR2_PIN(62), 716 JAGUAR2_PIN(63), 717 }; 718 719 #define SERVALT_P(p, f0, f1, f2) \ 720 static struct ocelot_pin_caps servalt_pin_##p = { \ 721 .pin = p, \ 722 .functions = { \ 723 FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2 \ 724 }, \ 725 } 726 727 SERVALT_P(0, SG0, NONE, NONE); 728 SERVALT_P(1, SG0, NONE, NONE); 729 SERVALT_P(2, SG0, NONE, NONE); 730 SERVALT_P(3, SG0, NONE, NONE); 731 SERVALT_P(4, IRQ0_IN, IRQ0_OUT, TWI_SCL_M); 732 SERVALT_P(5, IRQ1_IN, IRQ1_OUT, TWI_SCL_M); 733 SERVALT_P(6, UART, NONE, NONE); 734 SERVALT_P(7, UART, NONE, NONE); 735 SERVALT_P(8, SI, SFP, TWI_SCL_M); 736 SERVALT_P(9, PCI_WAKE, SFP, SI); 737 SERVALT_P(10, PTP0, SFP, TWI_SCL_M); 738 SERVALT_P(11, PTP1, SFP, TWI_SCL_M); 739 SERVALT_P(12, REF_CLK, SFP, TWI_SCL_M); 740 SERVALT_P(13, REF_CLK, SFP, TWI_SCL_M); 741 SERVALT_P(14, REF_CLK, IRQ0_OUT, SI); 742 SERVALT_P(15, REF_CLK, IRQ1_OUT, SI); 743 SERVALT_P(16, TACHO, SFP, SI); 744 SERVALT_P(17, PWM, NONE, TWI_SCL_M); 745 SERVALT_P(18, PTP2, SFP, SI); 746 SERVALT_P(19, PTP3, SFP, SI); 747 SERVALT_P(20, UART2, SFP, SI); 748 SERVALT_P(21, UART2, NONE, NONE); 749 SERVALT_P(22, MIIM, SFP, TWI2); 750 SERVALT_P(23, MIIM, SFP, TWI2); 751 SERVALT_P(24, TWI, NONE, NONE); 752 SERVALT_P(25, TWI, SFP, TWI_SCL_M); 753 SERVALT_P(26, TWI_SCL_M, SFP, SI); 754 SERVALT_P(27, TWI_SCL_M, SFP, SI); 755 SERVALT_P(28, TWI_SCL_M, SFP, SI); 756 SERVALT_P(29, TWI_SCL_M, NONE, NONE); 757 SERVALT_P(30, TWI_SCL_M, NONE, NONE); 758 SERVALT_P(31, TWI_SCL_M, NONE, NONE); 759 SERVALT_P(32, TWI_SCL_M, NONE, NONE); 760 SERVALT_P(33, RCVRD_CLK, NONE, NONE); 761 SERVALT_P(34, RCVRD_CLK, NONE, NONE); 762 SERVALT_P(35, RCVRD_CLK, NONE, NONE); 763 SERVALT_P(36, RCVRD_CLK, NONE, NONE); 764 765 #define SERVALT_PIN(n) { \ 766 .number = n, \ 767 .name = "GPIO_"#n, \ 768 .drv_data = &servalt_pin_##n \ 769 } 770 771 static const struct pinctrl_pin_desc servalt_pins[] = { 772 SERVALT_PIN(0), 773 SERVALT_PIN(1), 774 SERVALT_PIN(2), 775 SERVALT_PIN(3), 776 SERVALT_PIN(4), 777 SERVALT_PIN(5), 778 SERVALT_PIN(6), 779 SERVALT_PIN(7), 780 SERVALT_PIN(8), 781 SERVALT_PIN(9), 782 SERVALT_PIN(10), 783 SERVALT_PIN(11), 784 SERVALT_PIN(12), 785 SERVALT_PIN(13), 786 SERVALT_PIN(14), 787 SERVALT_PIN(15), 788 SERVALT_PIN(16), 789 SERVALT_PIN(17), 790 SERVALT_PIN(18), 791 SERVALT_PIN(19), 792 SERVALT_PIN(20), 793 SERVALT_PIN(21), 794 SERVALT_PIN(22), 795 SERVALT_PIN(23), 796 SERVALT_PIN(24), 797 SERVALT_PIN(25), 798 SERVALT_PIN(26), 799 SERVALT_PIN(27), 800 SERVALT_PIN(28), 801 SERVALT_PIN(29), 802 SERVALT_PIN(30), 803 SERVALT_PIN(31), 804 SERVALT_PIN(32), 805 SERVALT_PIN(33), 806 SERVALT_PIN(34), 807 SERVALT_PIN(35), 808 SERVALT_PIN(36), 809 }; 810 811 #define SPARX5_P(p, f0, f1, f2) \ 812 static struct ocelot_pin_caps sparx5_pin_##p = { \ 813 .pin = p, \ 814 .functions = { \ 815 FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2 \ 816 }, \ 817 } 818 819 SPARX5_P(0, SG0, PLL_STAT, NONE); 820 SPARX5_P(1, SG0, NONE, NONE); 821 SPARX5_P(2, SG0, NONE, NONE); 822 SPARX5_P(3, SG0, NONE, NONE); 823 SPARX5_P(4, SG1, NONE, NONE); 824 SPARX5_P(5, SG1, NONE, NONE); 825 SPARX5_P(6, IRQ0_IN, IRQ0_OUT, SFP); 826 SPARX5_P(7, IRQ1_IN, IRQ1_OUT, SFP); 827 SPARX5_P(8, PTP0, NONE, SFP); 828 SPARX5_P(9, PTP1, SFP, TWI_SCL_M); 829 SPARX5_P(10, UART, NONE, NONE); 830 SPARX5_P(11, UART, NONE, NONE); 831 SPARX5_P(12, SG1, NONE, NONE); 832 SPARX5_P(13, SG1, NONE, NONE); 833 SPARX5_P(14, TWI, TWI_SCL_M, NONE); 834 SPARX5_P(15, TWI, NONE, NONE); 835 SPARX5_P(16, SI, TWI_SCL_M, SFP); 836 SPARX5_P(17, SI, TWI_SCL_M, SFP); 837 SPARX5_P(18, SI, TWI_SCL_M, SFP); 838 SPARX5_P(19, PCI_WAKE, TWI_SCL_M, SFP); 839 SPARX5_P(20, IRQ0_OUT, TWI_SCL_M, SFP); 840 SPARX5_P(21, IRQ1_OUT, TACHO, SFP); 841 SPARX5_P(22, TACHO, IRQ0_OUT, TWI_SCL_M); 842 SPARX5_P(23, PWM, UART3, TWI_SCL_M); 843 SPARX5_P(24, PTP2, UART3, TWI_SCL_M); 844 SPARX5_P(25, PTP3, SI, TWI_SCL_M); 845 SPARX5_P(26, UART2, SI, TWI_SCL_M); 846 SPARX5_P(27, UART2, SI, TWI_SCL_M); 847 SPARX5_P(28, TWI2, SI, SFP); 848 SPARX5_P(29, TWI2, SI, SFP); 849 SPARX5_P(30, SG2, SI, PWM); 850 SPARX5_P(31, SG2, SI, TWI_SCL_M); 851 SPARX5_P(32, SG2, SI, TWI_SCL_M); 852 SPARX5_P(33, SG2, SI, SFP); 853 SPARX5_P(34, NONE, TWI_SCL_M, EMMC); 854 SPARX5_P(35, SFP, TWI_SCL_M, EMMC); 855 SPARX5_P(36, SFP, TWI_SCL_M, EMMC); 856 SPARX5_P(37, SFP, NONE, EMMC); 857 SPARX5_P(38, NONE, TWI_SCL_M, EMMC); 858 SPARX5_P(39, SI2, TWI_SCL_M, EMMC); 859 SPARX5_P(40, SI2, TWI_SCL_M, EMMC); 860 SPARX5_P(41, SI2, TWI_SCL_M, EMMC); 861 SPARX5_P(42, SI2, TWI_SCL_M, EMMC); 862 SPARX5_P(43, SI2, TWI_SCL_M, EMMC); 863 SPARX5_P(44, SI, SFP, EMMC); 864 SPARX5_P(45, SI, SFP, EMMC); 865 SPARX5_P(46, NONE, SFP, EMMC); 866 SPARX5_P(47, NONE, SFP, EMMC); 867 SPARX5_P(48, TWI3, SI, SFP); 868 SPARX5_P(49, TWI3, NONE, SFP); 869 SPARX5_P(50, SFP, NONE, TWI_SCL_M); 870 SPARX5_P(51, SFP, SI, TWI_SCL_M); 871 SPARX5_P(52, SFP, MIIM, TWI_SCL_M); 872 SPARX5_P(53, SFP, MIIM, TWI_SCL_M); 873 SPARX5_P(54, SFP, PTP2, TWI_SCL_M); 874 SPARX5_P(55, SFP, PTP3, PCI_WAKE); 875 SPARX5_P(56, MIIM, SFP, TWI_SCL_M); 876 SPARX5_P(57, MIIM, SFP, TWI_SCL_M); 877 SPARX5_P(58, MIIM, SFP, TWI_SCL_M); 878 SPARX5_P(59, MIIM, SFP, NONE); 879 SPARX5_P(60, RECO_CLK, NONE, NONE); 880 SPARX5_P(61, RECO_CLK, NONE, NONE); 881 SPARX5_P(62, RECO_CLK, PLL_STAT, NONE); 882 SPARX5_P(63, RECO_CLK, NONE, NONE); 883 884 #define SPARX5_PIN(n) { \ 885 .number = n, \ 886 .name = "GPIO_"#n, \ 887 .drv_data = &sparx5_pin_##n \ 888 } 889 890 static const struct pinctrl_pin_desc sparx5_pins[] = { 891 SPARX5_PIN(0), 892 SPARX5_PIN(1), 893 SPARX5_PIN(2), 894 SPARX5_PIN(3), 895 SPARX5_PIN(4), 896 SPARX5_PIN(5), 897 SPARX5_PIN(6), 898 SPARX5_PIN(7), 899 SPARX5_PIN(8), 900 SPARX5_PIN(9), 901 SPARX5_PIN(10), 902 SPARX5_PIN(11), 903 SPARX5_PIN(12), 904 SPARX5_PIN(13), 905 SPARX5_PIN(14), 906 SPARX5_PIN(15), 907 SPARX5_PIN(16), 908 SPARX5_PIN(17), 909 SPARX5_PIN(18), 910 SPARX5_PIN(19), 911 SPARX5_PIN(20), 912 SPARX5_PIN(21), 913 SPARX5_PIN(22), 914 SPARX5_PIN(23), 915 SPARX5_PIN(24), 916 SPARX5_PIN(25), 917 SPARX5_PIN(26), 918 SPARX5_PIN(27), 919 SPARX5_PIN(28), 920 SPARX5_PIN(29), 921 SPARX5_PIN(30), 922 SPARX5_PIN(31), 923 SPARX5_PIN(32), 924 SPARX5_PIN(33), 925 SPARX5_PIN(34), 926 SPARX5_PIN(35), 927 SPARX5_PIN(36), 928 SPARX5_PIN(37), 929 SPARX5_PIN(38), 930 SPARX5_PIN(39), 931 SPARX5_PIN(40), 932 SPARX5_PIN(41), 933 SPARX5_PIN(42), 934 SPARX5_PIN(43), 935 SPARX5_PIN(44), 936 SPARX5_PIN(45), 937 SPARX5_PIN(46), 938 SPARX5_PIN(47), 939 SPARX5_PIN(48), 940 SPARX5_PIN(49), 941 SPARX5_PIN(50), 942 SPARX5_PIN(51), 943 SPARX5_PIN(52), 944 SPARX5_PIN(53), 945 SPARX5_PIN(54), 946 SPARX5_PIN(55), 947 SPARX5_PIN(56), 948 SPARX5_PIN(57), 949 SPARX5_PIN(58), 950 SPARX5_PIN(59), 951 SPARX5_PIN(60), 952 SPARX5_PIN(61), 953 SPARX5_PIN(62), 954 SPARX5_PIN(63), 955 }; 956 957 #define LAN966X_P(p, f0, f1, f2, f3, f4, f5, f6, f7) \ 958 static struct ocelot_pin_caps lan966x_pin_##p = { \ 959 .pin = p, \ 960 .functions = { \ 961 FUNC_##f0, FUNC_##f1, FUNC_##f2, \ 962 FUNC_##f3 \ 963 }, \ 964 .a_functions = { \ 965 FUNC_##f4, FUNC_##f5, FUNC_##f6, \ 966 FUNC_##f7 \ 967 }, \ 968 } 969 970 /* Pinmuxing table taken from data sheet */ 971 /* Pin FUNC0 FUNC1 FUNC2 FUNC3 FUNC4 FUNC5 FUNC6 FUNC7 */ 972 LAN966X_P(0, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 973 LAN966X_P(1, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 974 LAN966X_P(2, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 975 LAN966X_P(3, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 976 LAN966X_P(4, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 977 LAN966X_P(5, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 978 LAN966X_P(6, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 979 LAN966X_P(7, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 980 LAN966X_P(8, GPIO, FC0_a, USB_H_b, NONE, USB_S_b, NONE, NONE, R); 981 LAN966X_P(9, GPIO, FC0_a, USB_H_b, NONE, NONE, NONE, NONE, R); 982 LAN966X_P(10, GPIO, FC0_a, NONE, NONE, NONE, NONE, NONE, R); 983 LAN966X_P(11, GPIO, FC1_a, NONE, NONE, NONE, NONE, NONE, R); 984 LAN966X_P(12, GPIO, FC1_a, NONE, NONE, NONE, NONE, NONE, R); 985 LAN966X_P(13, GPIO, FC1_a, NONE, NONE, NONE, NONE, NONE, R); 986 LAN966X_P(14, GPIO, FC2_a, NONE, NONE, NONE, NONE, NONE, R); 987 LAN966X_P(15, GPIO, FC2_a, NONE, NONE, NONE, NONE, NONE, R); 988 LAN966X_P(16, GPIO, FC2_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, IRQ_OUT_c, R); 989 LAN966X_P(17, GPIO, FC3_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, IRQ_OUT_c, R); 990 LAN966X_P(18, GPIO, FC3_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, IRQ_OUT_c, R); 991 LAN966X_P(19, GPIO, FC3_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, IRQ_OUT_c, R); 992 LAN966X_P(20, GPIO, FC4_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, NONE, R); 993 LAN966X_P(21, GPIO, FC4_a, NONE, NONE, OB_TRG_a, NONE, NONE, R); 994 LAN966X_P(22, GPIO, FC4_a, NONE, NONE, OB_TRG_a, NONE, NONE, R); 995 LAN966X_P(23, GPIO, NONE, NONE, NONE, OB_TRG_a, NONE, NONE, R); 996 LAN966X_P(24, GPIO, FC0_b, IB_TRG_a, USB_H_c, OB_TRG_a, IRQ_IN_c, TACHO_a, R); 997 LAN966X_P(25, GPIO, FC0_b, IB_TRG_a, USB_H_c, OB_TRG_a, IRQ_OUT_c, SFP_SD, R); 998 LAN966X_P(26, GPIO, FC0_b, IB_TRG_a, USB_S_c, OB_TRG_a, CAN0_a, SFP_SD, R); 999 LAN966X_P(27, GPIO, NONE, NONE, NONE, OB_TRG_a, CAN0_a, PWM_a, R); 1000 LAN966X_P(28, GPIO, MIIM_a, NONE, NONE, OB_TRG_a, IRQ_OUT_c, SFP_SD, R); 1001 LAN966X_P(29, GPIO, MIIM_a, NONE, NONE, OB_TRG_a, NONE, NONE, R); 1002 LAN966X_P(30, GPIO, FC3_c, CAN1, CLKMON, OB_TRG, RECO_b, NONE, R); 1003 LAN966X_P(31, GPIO, FC3_c, CAN1, CLKMON, OB_TRG, RECO_b, NONE, R); 1004 LAN966X_P(32, GPIO, FC3_c, NONE, SGPIO_a, NONE, MIIM_Sa, NONE, R); 1005 LAN966X_P(33, GPIO, FC1_b, NONE, SGPIO_a, NONE, MIIM_Sa, MIIM_b, R); 1006 LAN966X_P(34, GPIO, FC1_b, NONE, SGPIO_a, NONE, MIIM_Sa, MIIM_b, R); 1007 LAN966X_P(35, GPIO, FC1_b, PTPSYNC_0, SGPIO_a, CAN0_b, NONE, NONE, R); 1008 LAN966X_P(36, GPIO, NONE, PTPSYNC_1, NONE, CAN0_b, NONE, NONE, R); 1009 LAN966X_P(37, GPIO, FC_SHRD0, PTPSYNC_2, TWI_SLC_GATE_AD, NONE, NONE, NONE, R); 1010 LAN966X_P(38, GPIO, NONE, PTPSYNC_3, NONE, NONE, NONE, NONE, R); 1011 LAN966X_P(39, GPIO, NONE, PTPSYNC_4, NONE, NONE, NONE, NONE, R); 1012 LAN966X_P(40, GPIO, FC_SHRD1, PTPSYNC_5, NONE, NONE, NONE, NONE, R); 1013 LAN966X_P(41, GPIO, FC_SHRD2, PTPSYNC_6, TWI_SLC_GATE_AD, NONE, NONE, NONE, R); 1014 LAN966X_P(42, GPIO, FC_SHRD3, PTPSYNC_7, TWI_SLC_GATE_AD, NONE, NONE, NONE, R); 1015 LAN966X_P(43, GPIO, FC2_b, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, RECO_a, IRQ_IN_a, R); 1016 LAN966X_P(44, GPIO, FC2_b, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, RECO_a, IRQ_IN_a, R); 1017 LAN966X_P(45, GPIO, FC2_b, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, NONE, IRQ_IN_a, R); 1018 LAN966X_P(46, GPIO, FC1_c, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, FC_SHRD4, IRQ_IN_a, R); 1019 LAN966X_P(47, GPIO, FC1_c, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, FC_SHRD5, IRQ_IN_a, R); 1020 LAN966X_P(48, GPIO, FC1_c, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, FC_SHRD6, IRQ_IN_a, R); 1021 LAN966X_P(49, GPIO, FC_SHRD7, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, TWI_SLC_GATE, IRQ_IN_a, R); 1022 LAN966X_P(50, GPIO, FC_SHRD16, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, TWI_SLC_GATE, NONE, R); 1023 LAN966X_P(51, GPIO, FC3_b, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, PWM_b, IRQ_IN_b, R); 1024 LAN966X_P(52, GPIO, FC3_b, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, TACHO_b, IRQ_IN_b, R); 1025 LAN966X_P(53, GPIO, FC3_b, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, NONE, IRQ_IN_b, R); 1026 LAN966X_P(54, GPIO, FC_SHRD8, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, TWI_SLC_GATE, IRQ_IN_b, R); 1027 LAN966X_P(55, GPIO, FC_SHRD9, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, TWI_SLC_GATE, IRQ_IN_b, R); 1028 LAN966X_P(56, GPIO, FC4_b, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, FC_SHRD10, IRQ_IN_b, R); 1029 LAN966X_P(57, GPIO, FC4_b, TWI_SLC_GATE, IB_TRG_c, IRQ_OUT_b, FC_SHRD11, IRQ_IN_b, R); 1030 LAN966X_P(58, GPIO, FC4_b, TWI_SLC_GATE, IB_TRG_c, IRQ_OUT_b, FC_SHRD12, IRQ_IN_b, R); 1031 LAN966X_P(59, GPIO, QSPI1, MIIM_c, NONE, NONE, MIIM_Sb, NONE, R); 1032 LAN966X_P(60, GPIO, QSPI1, MIIM_c, NONE, NONE, MIIM_Sb, NONE, R); 1033 LAN966X_P(61, GPIO, QSPI1, NONE, SGPIO_b, FC0_c, MIIM_Sb, NONE, R); 1034 LAN966X_P(62, GPIO, QSPI1, FC_SHRD13, SGPIO_b, FC0_c, TWI_SLC_GATE, SFP_SD, R); 1035 LAN966X_P(63, GPIO, QSPI1, FC_SHRD14, SGPIO_b, FC0_c, TWI_SLC_GATE, SFP_SD, R); 1036 LAN966X_P(64, GPIO, QSPI1, FC4_c, SGPIO_b, FC_SHRD15, TWI_SLC_GATE, SFP_SD, R); 1037 LAN966X_P(65, GPIO, USB_H_a, FC4_c, NONE, IRQ_OUT_c, TWI_SLC_GATE_AD, NONE, R); 1038 LAN966X_P(66, GPIO, USB_H_a, FC4_c, USB_S_a, IRQ_OUT_c, IRQ_IN_c, NONE, R); 1039 LAN966X_P(67, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R); 1040 LAN966X_P(68, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R); 1041 LAN966X_P(69, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R); 1042 LAN966X_P(70, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R); 1043 LAN966X_P(71, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R); 1044 LAN966X_P(72, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R); 1045 LAN966X_P(73, GPIO, EMMC, NONE, NONE, SD, NONE, NONE, R); 1046 LAN966X_P(74, GPIO, EMMC, NONE, FC_SHRD17, SD, TWI_SLC_GATE, NONE, R); 1047 LAN966X_P(75, GPIO, EMMC, NONE, FC_SHRD18, SD, TWI_SLC_GATE, NONE, R); 1048 LAN966X_P(76, GPIO, EMMC, NONE, FC_SHRD19, SD, TWI_SLC_GATE, NONE, R); 1049 LAN966X_P(77, GPIO, EMMC_SD, NONE, FC_SHRD20, NONE, TWI_SLC_GATE, NONE, R); 1050 1051 #define LAN966X_PIN(n) { \ 1052 .number = n, \ 1053 .name = "GPIO_"#n, \ 1054 .drv_data = &lan966x_pin_##n \ 1055 } 1056 1057 static const struct pinctrl_pin_desc lan966x_pins[] = { 1058 LAN966X_PIN(0), 1059 LAN966X_PIN(1), 1060 LAN966X_PIN(2), 1061 LAN966X_PIN(3), 1062 LAN966X_PIN(4), 1063 LAN966X_PIN(5), 1064 LAN966X_PIN(6), 1065 LAN966X_PIN(7), 1066 LAN966X_PIN(8), 1067 LAN966X_PIN(9), 1068 LAN966X_PIN(10), 1069 LAN966X_PIN(11), 1070 LAN966X_PIN(12), 1071 LAN966X_PIN(13), 1072 LAN966X_PIN(14), 1073 LAN966X_PIN(15), 1074 LAN966X_PIN(16), 1075 LAN966X_PIN(17), 1076 LAN966X_PIN(18), 1077 LAN966X_PIN(19), 1078 LAN966X_PIN(20), 1079 LAN966X_PIN(21), 1080 LAN966X_PIN(22), 1081 LAN966X_PIN(23), 1082 LAN966X_PIN(24), 1083 LAN966X_PIN(25), 1084 LAN966X_PIN(26), 1085 LAN966X_PIN(27), 1086 LAN966X_PIN(28), 1087 LAN966X_PIN(29), 1088 LAN966X_PIN(30), 1089 LAN966X_PIN(31), 1090 LAN966X_PIN(32), 1091 LAN966X_PIN(33), 1092 LAN966X_PIN(34), 1093 LAN966X_PIN(35), 1094 LAN966X_PIN(36), 1095 LAN966X_PIN(37), 1096 LAN966X_PIN(38), 1097 LAN966X_PIN(39), 1098 LAN966X_PIN(40), 1099 LAN966X_PIN(41), 1100 LAN966X_PIN(42), 1101 LAN966X_PIN(43), 1102 LAN966X_PIN(44), 1103 LAN966X_PIN(45), 1104 LAN966X_PIN(46), 1105 LAN966X_PIN(47), 1106 LAN966X_PIN(48), 1107 LAN966X_PIN(49), 1108 LAN966X_PIN(50), 1109 LAN966X_PIN(51), 1110 LAN966X_PIN(52), 1111 LAN966X_PIN(53), 1112 LAN966X_PIN(54), 1113 LAN966X_PIN(55), 1114 LAN966X_PIN(56), 1115 LAN966X_PIN(57), 1116 LAN966X_PIN(58), 1117 LAN966X_PIN(59), 1118 LAN966X_PIN(60), 1119 LAN966X_PIN(61), 1120 LAN966X_PIN(62), 1121 LAN966X_PIN(63), 1122 LAN966X_PIN(64), 1123 LAN966X_PIN(65), 1124 LAN966X_PIN(66), 1125 LAN966X_PIN(67), 1126 LAN966X_PIN(68), 1127 LAN966X_PIN(69), 1128 LAN966X_PIN(70), 1129 LAN966X_PIN(71), 1130 LAN966X_PIN(72), 1131 LAN966X_PIN(73), 1132 LAN966X_PIN(74), 1133 LAN966X_PIN(75), 1134 LAN966X_PIN(76), 1135 LAN966X_PIN(77), 1136 }; 1137 1138 static int ocelot_get_functions_count(struct pinctrl_dev *pctldev) 1139 { 1140 return ARRAY_SIZE(ocelot_function_names); 1141 } 1142 1143 static const char *ocelot_get_function_name(struct pinctrl_dev *pctldev, 1144 unsigned int function) 1145 { 1146 return ocelot_function_names[function]; 1147 } 1148 1149 static int ocelot_get_function_groups(struct pinctrl_dev *pctldev, 1150 unsigned int function, 1151 const char *const **groups, 1152 unsigned *const num_groups) 1153 { 1154 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1155 1156 *groups = info->func[function].groups; 1157 *num_groups = info->func[function].ngroups; 1158 1159 return 0; 1160 } 1161 1162 static int ocelot_pin_function_idx(struct ocelot_pinctrl *info, 1163 unsigned int pin, unsigned int function) 1164 { 1165 struct ocelot_pin_caps *p = info->desc->pins[pin].drv_data; 1166 int i; 1167 1168 for (i = 0; i < OCELOT_FUNC_PER_PIN; i++) { 1169 if (function == p->functions[i]) 1170 return i; 1171 1172 if (function == p->a_functions[i]) 1173 return i + OCELOT_FUNC_PER_PIN; 1174 } 1175 1176 return -1; 1177 } 1178 1179 #define REG_ALT(msb, info, p) (OCELOT_GPIO_ALT0 * (info)->stride + 4 * ((msb) + ((info)->stride * ((p) / 32)))) 1180 1181 static int ocelot_pinmux_set_mux(struct pinctrl_dev *pctldev, 1182 unsigned int selector, unsigned int group) 1183 { 1184 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1185 struct ocelot_pin_caps *pin = info->desc->pins[group].drv_data; 1186 unsigned int p = pin->pin % 32; 1187 int f; 1188 1189 f = ocelot_pin_function_idx(info, group, selector); 1190 if (f < 0) 1191 return -EINVAL; 1192 1193 /* 1194 * f is encoded on two bits. 1195 * bit 0 of f goes in BIT(pin) of ALT[0], bit 1 of f goes in BIT(pin) of 1196 * ALT[1] 1197 * This is racy because both registers can't be updated at the same time 1198 * but it doesn't matter much for now. 1199 * Note: ALT0/ALT1 are organized specially for 64 gpio targets 1200 */ 1201 regmap_update_bits(info->map, REG_ALT(0, info, pin->pin), 1202 BIT(p), f << p); 1203 regmap_update_bits(info->map, REG_ALT(1, info, pin->pin), 1204 BIT(p), f << (p - 1)); 1205 1206 return 0; 1207 } 1208 1209 static int lan966x_pinmux_set_mux(struct pinctrl_dev *pctldev, 1210 unsigned int selector, unsigned int group) 1211 { 1212 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1213 struct ocelot_pin_caps *pin = info->desc->pins[group].drv_data; 1214 unsigned int p = pin->pin % 32; 1215 int f; 1216 1217 f = ocelot_pin_function_idx(info, group, selector); 1218 if (f < 0) 1219 return -EINVAL; 1220 1221 /* 1222 * f is encoded on three bits. 1223 * bit 0 of f goes in BIT(pin) of ALT[0], bit 1 of f goes in BIT(pin) of 1224 * ALT[1], bit 2 of f goes in BIT(pin) of ALT[2] 1225 * This is racy because three registers can't be updated at the same time 1226 * but it doesn't matter much for now. 1227 * Note: ALT0/ALT1/ALT2 are organized specially for 78 gpio targets 1228 */ 1229 regmap_update_bits(info->map, REG_ALT(0, info, pin->pin), 1230 BIT(p), f << p); 1231 regmap_update_bits(info->map, REG_ALT(1, info, pin->pin), 1232 BIT(p), (f >> 1) << p); 1233 regmap_update_bits(info->map, REG_ALT(2, info, pin->pin), 1234 BIT(p), (f >> 2) << p); 1235 1236 return 0; 1237 } 1238 1239 #define REG(r, info, p) ((r) * (info)->stride + (4 * ((p) / 32))) 1240 1241 static int ocelot_gpio_set_direction(struct pinctrl_dev *pctldev, 1242 struct pinctrl_gpio_range *range, 1243 unsigned int pin, bool input) 1244 { 1245 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1246 unsigned int p = pin % 32; 1247 1248 regmap_update_bits(info->map, REG(OCELOT_GPIO_OE, info, pin), BIT(p), 1249 input ? 0 : BIT(p)); 1250 1251 return 0; 1252 } 1253 1254 static int ocelot_gpio_request_enable(struct pinctrl_dev *pctldev, 1255 struct pinctrl_gpio_range *range, 1256 unsigned int offset) 1257 { 1258 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1259 unsigned int p = offset % 32; 1260 1261 regmap_update_bits(info->map, REG_ALT(0, info, offset), 1262 BIT(p), 0); 1263 regmap_update_bits(info->map, REG_ALT(1, info, offset), 1264 BIT(p), 0); 1265 1266 return 0; 1267 } 1268 1269 static int lan966x_gpio_request_enable(struct pinctrl_dev *pctldev, 1270 struct pinctrl_gpio_range *range, 1271 unsigned int offset) 1272 { 1273 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1274 unsigned int p = offset % 32; 1275 1276 regmap_update_bits(info->map, REG_ALT(0, info, offset), 1277 BIT(p), 0); 1278 regmap_update_bits(info->map, REG_ALT(1, info, offset), 1279 BIT(p), 0); 1280 regmap_update_bits(info->map, REG_ALT(2, info, offset), 1281 BIT(p), 0); 1282 1283 return 0; 1284 } 1285 1286 static const struct pinmux_ops ocelot_pmx_ops = { 1287 .get_functions_count = ocelot_get_functions_count, 1288 .get_function_name = ocelot_get_function_name, 1289 .get_function_groups = ocelot_get_function_groups, 1290 .set_mux = ocelot_pinmux_set_mux, 1291 .gpio_set_direction = ocelot_gpio_set_direction, 1292 .gpio_request_enable = ocelot_gpio_request_enable, 1293 }; 1294 1295 static const struct pinmux_ops lan966x_pmx_ops = { 1296 .get_functions_count = ocelot_get_functions_count, 1297 .get_function_name = ocelot_get_function_name, 1298 .get_function_groups = ocelot_get_function_groups, 1299 .set_mux = lan966x_pinmux_set_mux, 1300 .gpio_set_direction = ocelot_gpio_set_direction, 1301 .gpio_request_enable = lan966x_gpio_request_enable, 1302 }; 1303 1304 static int ocelot_pctl_get_groups_count(struct pinctrl_dev *pctldev) 1305 { 1306 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1307 1308 return info->desc->npins; 1309 } 1310 1311 static const char *ocelot_pctl_get_group_name(struct pinctrl_dev *pctldev, 1312 unsigned int group) 1313 { 1314 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1315 1316 return info->desc->pins[group].name; 1317 } 1318 1319 static int ocelot_pctl_get_group_pins(struct pinctrl_dev *pctldev, 1320 unsigned int group, 1321 const unsigned int **pins, 1322 unsigned int *num_pins) 1323 { 1324 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1325 1326 *pins = &info->desc->pins[group].number; 1327 *num_pins = 1; 1328 1329 return 0; 1330 } 1331 1332 static int ocelot_hw_get_value(struct ocelot_pinctrl *info, 1333 unsigned int pin, 1334 unsigned int reg, 1335 int *val) 1336 { 1337 int ret = -EOPNOTSUPP; 1338 1339 if (info->pincfg) { 1340 const struct ocelot_pincfg_data *opd = info->pincfg_data; 1341 u32 regcfg; 1342 1343 ret = regmap_read(info->pincfg, 1344 pin * regmap_get_reg_stride(info->pincfg), 1345 ®cfg); 1346 if (ret) 1347 return ret; 1348 1349 ret = 0; 1350 switch (reg) { 1351 case PINCONF_BIAS: 1352 *val = regcfg & (opd->pd_bit | opd->pu_bit); 1353 break; 1354 1355 case PINCONF_SCHMITT: 1356 *val = regcfg & opd->schmitt_bit; 1357 break; 1358 1359 case PINCONF_DRIVE_STRENGTH: 1360 *val = regcfg & opd->drive_bits; 1361 break; 1362 1363 default: 1364 ret = -EOPNOTSUPP; 1365 break; 1366 } 1367 } 1368 return ret; 1369 } 1370 1371 static int ocelot_pincfg_clrsetbits(struct ocelot_pinctrl *info, u32 regaddr, 1372 u32 clrbits, u32 setbits) 1373 { 1374 u32 val; 1375 int ret; 1376 1377 ret = regmap_read(info->pincfg, 1378 regaddr * regmap_get_reg_stride(info->pincfg), 1379 &val); 1380 if (ret) 1381 return ret; 1382 1383 val &= ~clrbits; 1384 val |= setbits; 1385 1386 ret = regmap_write(info->pincfg, 1387 regaddr * regmap_get_reg_stride(info->pincfg), 1388 val); 1389 1390 return ret; 1391 } 1392 1393 static int ocelot_hw_set_value(struct ocelot_pinctrl *info, 1394 unsigned int pin, 1395 unsigned int reg, 1396 int val) 1397 { 1398 int ret = -EOPNOTSUPP; 1399 1400 if (info->pincfg) { 1401 const struct ocelot_pincfg_data *opd = info->pincfg_data; 1402 1403 ret = 0; 1404 switch (reg) { 1405 case PINCONF_BIAS: 1406 ret = ocelot_pincfg_clrsetbits(info, pin, 1407 opd->pd_bit | opd->pu_bit, 1408 val); 1409 break; 1410 1411 case PINCONF_SCHMITT: 1412 ret = ocelot_pincfg_clrsetbits(info, pin, 1413 opd->schmitt_bit, 1414 val); 1415 break; 1416 1417 case PINCONF_DRIVE_STRENGTH: 1418 if (val <= 3) 1419 ret = ocelot_pincfg_clrsetbits(info, pin, 1420 opd->drive_bits, 1421 val); 1422 else 1423 ret = -EINVAL; 1424 break; 1425 1426 default: 1427 ret = -EOPNOTSUPP; 1428 break; 1429 } 1430 } 1431 return ret; 1432 } 1433 1434 static int ocelot_pinconf_get(struct pinctrl_dev *pctldev, 1435 unsigned int pin, unsigned long *config) 1436 { 1437 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1438 u32 param = pinconf_to_config_param(*config); 1439 int val, err; 1440 1441 switch (param) { 1442 case PIN_CONFIG_BIAS_DISABLE: 1443 case PIN_CONFIG_BIAS_PULL_UP: 1444 case PIN_CONFIG_BIAS_PULL_DOWN: 1445 err = ocelot_hw_get_value(info, pin, PINCONF_BIAS, &val); 1446 if (err) 1447 return err; 1448 if (param == PIN_CONFIG_BIAS_DISABLE) 1449 val = (val == 0); 1450 else if (param == PIN_CONFIG_BIAS_PULL_DOWN) 1451 val = !!(val & info->pincfg_data->pd_bit); 1452 else /* PIN_CONFIG_BIAS_PULL_UP */ 1453 val = !!(val & info->pincfg_data->pu_bit); 1454 break; 1455 1456 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 1457 if (!info->pincfg_data->schmitt_bit) 1458 return -EOPNOTSUPP; 1459 1460 err = ocelot_hw_get_value(info, pin, PINCONF_SCHMITT, &val); 1461 if (err) 1462 return err; 1463 1464 val = !!(val & info->pincfg_data->schmitt_bit); 1465 break; 1466 1467 case PIN_CONFIG_DRIVE_STRENGTH: 1468 err = ocelot_hw_get_value(info, pin, PINCONF_DRIVE_STRENGTH, 1469 &val); 1470 if (err) 1471 return err; 1472 break; 1473 1474 case PIN_CONFIG_OUTPUT: 1475 err = regmap_read(info->map, REG(OCELOT_GPIO_OUT, info, pin), 1476 &val); 1477 if (err) 1478 return err; 1479 val = !!(val & BIT(pin % 32)); 1480 break; 1481 1482 case PIN_CONFIG_INPUT_ENABLE: 1483 case PIN_CONFIG_OUTPUT_ENABLE: 1484 err = regmap_read(info->map, REG(OCELOT_GPIO_OE, info, pin), 1485 &val); 1486 if (err) 1487 return err; 1488 val = val & BIT(pin % 32); 1489 if (param == PIN_CONFIG_OUTPUT_ENABLE) 1490 val = !!val; 1491 else 1492 val = !val; 1493 break; 1494 1495 default: 1496 return -EOPNOTSUPP; 1497 } 1498 1499 *config = pinconf_to_config_packed(param, val); 1500 1501 return 0; 1502 } 1503 1504 static int ocelot_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 1505 unsigned long *configs, unsigned int num_configs) 1506 { 1507 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1508 const struct ocelot_pincfg_data *opd = info->pincfg_data; 1509 u32 param, arg, p; 1510 int cfg, err = 0; 1511 1512 for (cfg = 0; cfg < num_configs; cfg++) { 1513 param = pinconf_to_config_param(configs[cfg]); 1514 arg = pinconf_to_config_argument(configs[cfg]); 1515 1516 switch (param) { 1517 case PIN_CONFIG_BIAS_DISABLE: 1518 case PIN_CONFIG_BIAS_PULL_UP: 1519 case PIN_CONFIG_BIAS_PULL_DOWN: 1520 arg = (param == PIN_CONFIG_BIAS_DISABLE) ? 0 : 1521 (param == PIN_CONFIG_BIAS_PULL_UP) ? 1522 opd->pu_bit : opd->pd_bit; 1523 1524 err = ocelot_hw_set_value(info, pin, PINCONF_BIAS, arg); 1525 if (err) 1526 goto err; 1527 1528 break; 1529 1530 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 1531 if (!opd->schmitt_bit) 1532 return -EOPNOTSUPP; 1533 1534 arg = arg ? opd->schmitt_bit : 0; 1535 err = ocelot_hw_set_value(info, pin, PINCONF_SCHMITT, 1536 arg); 1537 if (err) 1538 goto err; 1539 1540 break; 1541 1542 case PIN_CONFIG_DRIVE_STRENGTH: 1543 err = ocelot_hw_set_value(info, pin, 1544 PINCONF_DRIVE_STRENGTH, 1545 arg); 1546 if (err) 1547 goto err; 1548 1549 break; 1550 1551 case PIN_CONFIG_OUTPUT_ENABLE: 1552 case PIN_CONFIG_INPUT_ENABLE: 1553 case PIN_CONFIG_OUTPUT: 1554 p = pin % 32; 1555 if (arg) 1556 regmap_write(info->map, 1557 REG(OCELOT_GPIO_OUT_SET, info, 1558 pin), 1559 BIT(p)); 1560 else 1561 regmap_write(info->map, 1562 REG(OCELOT_GPIO_OUT_CLR, info, 1563 pin), 1564 BIT(p)); 1565 regmap_update_bits(info->map, 1566 REG(OCELOT_GPIO_OE, info, pin), 1567 BIT(p), 1568 param == PIN_CONFIG_INPUT_ENABLE ? 1569 0 : BIT(p)); 1570 break; 1571 1572 default: 1573 err = -EOPNOTSUPP; 1574 } 1575 } 1576 err: 1577 return err; 1578 } 1579 1580 static const struct pinconf_ops ocelot_confops = { 1581 .is_generic = true, 1582 .pin_config_get = ocelot_pinconf_get, 1583 .pin_config_set = ocelot_pinconf_set, 1584 .pin_config_config_dbg_show = pinconf_generic_dump_config, 1585 }; 1586 1587 static const struct pinctrl_ops ocelot_pctl_ops = { 1588 .get_groups_count = ocelot_pctl_get_groups_count, 1589 .get_group_name = ocelot_pctl_get_group_name, 1590 .get_group_pins = ocelot_pctl_get_group_pins, 1591 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, 1592 .dt_free_map = pinconf_generic_dt_free_map, 1593 }; 1594 1595 static struct ocelot_match_data luton_desc = { 1596 .desc = { 1597 .name = "luton-pinctrl", 1598 .pins = luton_pins, 1599 .npins = ARRAY_SIZE(luton_pins), 1600 .pctlops = &ocelot_pctl_ops, 1601 .pmxops = &ocelot_pmx_ops, 1602 .owner = THIS_MODULE, 1603 }, 1604 }; 1605 1606 static struct ocelot_match_data serval_desc = { 1607 .desc = { 1608 .name = "serval-pinctrl", 1609 .pins = serval_pins, 1610 .npins = ARRAY_SIZE(serval_pins), 1611 .pctlops = &ocelot_pctl_ops, 1612 .pmxops = &ocelot_pmx_ops, 1613 .owner = THIS_MODULE, 1614 }, 1615 }; 1616 1617 static struct ocelot_match_data ocelot_desc = { 1618 .desc = { 1619 .name = "ocelot-pinctrl", 1620 .pins = ocelot_pins, 1621 .npins = ARRAY_SIZE(ocelot_pins), 1622 .pctlops = &ocelot_pctl_ops, 1623 .pmxops = &ocelot_pmx_ops, 1624 .owner = THIS_MODULE, 1625 }, 1626 }; 1627 1628 static struct ocelot_match_data jaguar2_desc = { 1629 .desc = { 1630 .name = "jaguar2-pinctrl", 1631 .pins = jaguar2_pins, 1632 .npins = ARRAY_SIZE(jaguar2_pins), 1633 .pctlops = &ocelot_pctl_ops, 1634 .pmxops = &ocelot_pmx_ops, 1635 .owner = THIS_MODULE, 1636 }, 1637 }; 1638 1639 static struct ocelot_match_data servalt_desc = { 1640 .desc = { 1641 .name = "servalt-pinctrl", 1642 .pins = servalt_pins, 1643 .npins = ARRAY_SIZE(servalt_pins), 1644 .pctlops = &ocelot_pctl_ops, 1645 .pmxops = &ocelot_pmx_ops, 1646 .owner = THIS_MODULE, 1647 }, 1648 }; 1649 1650 static struct ocelot_match_data sparx5_desc = { 1651 .desc = { 1652 .name = "sparx5-pinctrl", 1653 .pins = sparx5_pins, 1654 .npins = ARRAY_SIZE(sparx5_pins), 1655 .pctlops = &ocelot_pctl_ops, 1656 .pmxops = &ocelot_pmx_ops, 1657 .confops = &ocelot_confops, 1658 .owner = THIS_MODULE, 1659 }, 1660 .pincfg_data = { 1661 .pd_bit = BIT(4), 1662 .pu_bit = BIT(3), 1663 .drive_bits = GENMASK(1, 0), 1664 .schmitt_bit = BIT(2), 1665 }, 1666 }; 1667 1668 static struct ocelot_match_data lan966x_desc = { 1669 .desc = { 1670 .name = "lan966x-pinctrl", 1671 .pins = lan966x_pins, 1672 .npins = ARRAY_SIZE(lan966x_pins), 1673 .pctlops = &ocelot_pctl_ops, 1674 .pmxops = &lan966x_pmx_ops, 1675 .confops = &ocelot_confops, 1676 .owner = THIS_MODULE, 1677 }, 1678 .pincfg_data = { 1679 .pd_bit = BIT(3), 1680 .pu_bit = BIT(2), 1681 .drive_bits = GENMASK(1, 0), 1682 }, 1683 }; 1684 1685 static int ocelot_create_group_func_map(struct device *dev, 1686 struct ocelot_pinctrl *info) 1687 { 1688 int f, npins, i; 1689 u8 *pins = kcalloc(info->desc->npins, sizeof(u8), GFP_KERNEL); 1690 1691 if (!pins) 1692 return -ENOMEM; 1693 1694 for (f = 0; f < FUNC_MAX; f++) { 1695 for (npins = 0, i = 0; i < info->desc->npins; i++) { 1696 if (ocelot_pin_function_idx(info, i, f) >= 0) 1697 pins[npins++] = i; 1698 } 1699 1700 if (!npins) 1701 continue; 1702 1703 info->func[f].ngroups = npins; 1704 info->func[f].groups = devm_kcalloc(dev, npins, sizeof(char *), 1705 GFP_KERNEL); 1706 if (!info->func[f].groups) { 1707 kfree(pins); 1708 return -ENOMEM; 1709 } 1710 1711 for (i = 0; i < npins; i++) 1712 info->func[f].groups[i] = 1713 info->desc->pins[pins[i]].name; 1714 } 1715 1716 kfree(pins); 1717 1718 return 0; 1719 } 1720 1721 static int ocelot_pinctrl_register(struct platform_device *pdev, 1722 struct ocelot_pinctrl *info) 1723 { 1724 int ret; 1725 1726 ret = ocelot_create_group_func_map(&pdev->dev, info); 1727 if (ret) { 1728 dev_err(&pdev->dev, "Unable to create group func map.\n"); 1729 return ret; 1730 } 1731 1732 info->pctl = devm_pinctrl_register(&pdev->dev, info->desc, info); 1733 if (IS_ERR(info->pctl)) { 1734 dev_err(&pdev->dev, "Failed to register pinctrl\n"); 1735 return PTR_ERR(info->pctl); 1736 } 1737 1738 return 0; 1739 } 1740 1741 static int ocelot_gpio_get(struct gpio_chip *chip, unsigned int offset) 1742 { 1743 struct ocelot_pinctrl *info = gpiochip_get_data(chip); 1744 unsigned int val; 1745 1746 regmap_read(info->map, REG(OCELOT_GPIO_IN, info, offset), &val); 1747 1748 return !!(val & BIT(offset % 32)); 1749 } 1750 1751 static void ocelot_gpio_set(struct gpio_chip *chip, unsigned int offset, 1752 int value) 1753 { 1754 struct ocelot_pinctrl *info = gpiochip_get_data(chip); 1755 1756 if (value) 1757 regmap_write(info->map, REG(OCELOT_GPIO_OUT_SET, info, offset), 1758 BIT(offset % 32)); 1759 else 1760 regmap_write(info->map, REG(OCELOT_GPIO_OUT_CLR, info, offset), 1761 BIT(offset % 32)); 1762 } 1763 1764 static int ocelot_gpio_get_direction(struct gpio_chip *chip, 1765 unsigned int offset) 1766 { 1767 struct ocelot_pinctrl *info = gpiochip_get_data(chip); 1768 unsigned int val; 1769 1770 regmap_read(info->map, REG(OCELOT_GPIO_OE, info, offset), &val); 1771 1772 if (val & BIT(offset % 32)) 1773 return GPIO_LINE_DIRECTION_OUT; 1774 1775 return GPIO_LINE_DIRECTION_IN; 1776 } 1777 1778 static int ocelot_gpio_direction_input(struct gpio_chip *chip, 1779 unsigned int offset) 1780 { 1781 return pinctrl_gpio_direction_input(chip->base + offset); 1782 } 1783 1784 static int ocelot_gpio_direction_output(struct gpio_chip *chip, 1785 unsigned int offset, int value) 1786 { 1787 struct ocelot_pinctrl *info = gpiochip_get_data(chip); 1788 unsigned int pin = BIT(offset % 32); 1789 1790 if (value) 1791 regmap_write(info->map, REG(OCELOT_GPIO_OUT_SET, info, offset), 1792 pin); 1793 else 1794 regmap_write(info->map, REG(OCELOT_GPIO_OUT_CLR, info, offset), 1795 pin); 1796 1797 return pinctrl_gpio_direction_output(chip->base + offset); 1798 } 1799 1800 static const struct gpio_chip ocelot_gpiolib_chip = { 1801 .request = gpiochip_generic_request, 1802 .free = gpiochip_generic_free, 1803 .set = ocelot_gpio_set, 1804 .get = ocelot_gpio_get, 1805 .get_direction = ocelot_gpio_get_direction, 1806 .direction_input = ocelot_gpio_direction_input, 1807 .direction_output = ocelot_gpio_direction_output, 1808 .owner = THIS_MODULE, 1809 }; 1810 1811 static void ocelot_irq_mask(struct irq_data *data) 1812 { 1813 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 1814 struct ocelot_pinctrl *info = gpiochip_get_data(chip); 1815 unsigned int gpio = irqd_to_hwirq(data); 1816 1817 regmap_update_bits(info->map, REG(OCELOT_GPIO_INTR_ENA, info, gpio), 1818 BIT(gpio % 32), 0); 1819 gpiochip_disable_irq(chip, gpio); 1820 } 1821 1822 static void ocelot_irq_work(struct work_struct *work) 1823 { 1824 struct ocelot_irq_work *w = container_of(work, struct ocelot_irq_work, irq_work); 1825 struct irq_chip *parent_chip = irq_desc_get_chip(w->irq_desc); 1826 struct gpio_chip *chip = irq_desc_get_chip_data(w->irq_desc); 1827 struct irq_data *data = irq_desc_get_irq_data(w->irq_desc); 1828 unsigned int gpio = irqd_to_hwirq(data); 1829 1830 local_irq_disable(); 1831 chained_irq_enter(parent_chip, w->irq_desc); 1832 generic_handle_domain_irq(chip->irq.domain, gpio); 1833 chained_irq_exit(parent_chip, w->irq_desc); 1834 local_irq_enable(); 1835 1836 kfree(w); 1837 } 1838 1839 static void ocelot_irq_unmask_level(struct irq_data *data) 1840 { 1841 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 1842 struct ocelot_pinctrl *info = gpiochip_get_data(chip); 1843 struct irq_desc *desc = irq_data_to_desc(data); 1844 unsigned int gpio = irqd_to_hwirq(data); 1845 unsigned int bit = BIT(gpio % 32); 1846 bool ack = false, active = false; 1847 u8 trigger_level; 1848 int val; 1849 1850 trigger_level = irqd_get_trigger_type(data); 1851 1852 /* Check if the interrupt line is still active. */ 1853 regmap_read(info->map, REG(OCELOT_GPIO_IN, info, gpio), &val); 1854 if ((!(val & bit) && trigger_level == IRQ_TYPE_LEVEL_LOW) || 1855 (val & bit && trigger_level == IRQ_TYPE_LEVEL_HIGH)) 1856 active = true; 1857 1858 /* 1859 * Check if the interrupt controller has seen any changes in the 1860 * interrupt line. 1861 */ 1862 regmap_read(info->map, REG(OCELOT_GPIO_INTR, info, gpio), &val); 1863 if (val & bit) 1864 ack = true; 1865 1866 /* Enable the interrupt now */ 1867 gpiochip_enable_irq(chip, gpio); 1868 regmap_update_bits(info->map, REG(OCELOT_GPIO_INTR_ENA, info, gpio), 1869 bit, bit); 1870 1871 /* 1872 * In case the interrupt line is still active and the interrupt 1873 * controller has not seen any changes in the interrupt line, then it 1874 * means that there happen another interrupt while the line was active. 1875 * So we missed that one, so we need to kick the interrupt again 1876 * handler. 1877 */ 1878 if (active && !ack) { 1879 struct ocelot_irq_work *work; 1880 1881 work = kmalloc(sizeof(*work), GFP_ATOMIC); 1882 if (!work) 1883 return; 1884 1885 work->irq_desc = desc; 1886 INIT_WORK(&work->irq_work, ocelot_irq_work); 1887 queue_work(info->wq, &work->irq_work); 1888 } 1889 } 1890 1891 static void ocelot_irq_unmask(struct irq_data *data) 1892 { 1893 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 1894 struct ocelot_pinctrl *info = gpiochip_get_data(chip); 1895 unsigned int gpio = irqd_to_hwirq(data); 1896 1897 gpiochip_enable_irq(chip, gpio); 1898 regmap_update_bits(info->map, REG(OCELOT_GPIO_INTR_ENA, info, gpio), 1899 BIT(gpio % 32), BIT(gpio % 32)); 1900 } 1901 1902 static void ocelot_irq_ack(struct irq_data *data) 1903 { 1904 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 1905 struct ocelot_pinctrl *info = gpiochip_get_data(chip); 1906 unsigned int gpio = irqd_to_hwirq(data); 1907 1908 regmap_write_bits(info->map, REG(OCELOT_GPIO_INTR, info, gpio), 1909 BIT(gpio % 32), BIT(gpio % 32)); 1910 } 1911 1912 static int ocelot_irq_set_type(struct irq_data *data, unsigned int type); 1913 1914 static struct irq_chip ocelot_level_irqchip = { 1915 .name = "gpio", 1916 .irq_mask = ocelot_irq_mask, 1917 .irq_ack = ocelot_irq_ack, 1918 .irq_unmask = ocelot_irq_unmask_level, 1919 .flags = IRQCHIP_IMMUTABLE, 1920 .irq_set_type = ocelot_irq_set_type, 1921 GPIOCHIP_IRQ_RESOURCE_HELPERS 1922 }; 1923 1924 static struct irq_chip ocelot_irqchip = { 1925 .name = "gpio", 1926 .irq_mask = ocelot_irq_mask, 1927 .irq_ack = ocelot_irq_ack, 1928 .irq_unmask = ocelot_irq_unmask, 1929 .irq_set_type = ocelot_irq_set_type, 1930 .flags = IRQCHIP_IMMUTABLE, 1931 GPIOCHIP_IRQ_RESOURCE_HELPERS 1932 }; 1933 1934 static int ocelot_irq_set_type(struct irq_data *data, unsigned int type) 1935 { 1936 if (type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) 1937 irq_set_chip_handler_name_locked(data, &ocelot_level_irqchip, 1938 handle_level_irq, NULL); 1939 if (type & IRQ_TYPE_EDGE_BOTH) 1940 irq_set_chip_handler_name_locked(data, &ocelot_irqchip, 1941 handle_edge_irq, NULL); 1942 1943 return 0; 1944 } 1945 1946 static void ocelot_irq_handler(struct irq_desc *desc) 1947 { 1948 struct irq_chip *parent_chip = irq_desc_get_chip(desc); 1949 struct gpio_chip *chip = irq_desc_get_handler_data(desc); 1950 struct ocelot_pinctrl *info = gpiochip_get_data(chip); 1951 unsigned int id_reg = OCELOT_GPIO_INTR_IDENT * info->stride; 1952 unsigned int reg = 0, irq, i; 1953 unsigned long irqs; 1954 1955 for (i = 0; i < info->stride; i++) { 1956 regmap_read(info->map, id_reg + 4 * i, ®); 1957 if (!reg) 1958 continue; 1959 1960 chained_irq_enter(parent_chip, desc); 1961 1962 irqs = reg; 1963 1964 for_each_set_bit(irq, &irqs, 1965 min(32U, info->desc->npins - 32 * i)) 1966 generic_handle_domain_irq(chip->irq.domain, irq + 32 * i); 1967 1968 chained_irq_exit(parent_chip, desc); 1969 } 1970 } 1971 1972 static int ocelot_gpiochip_register(struct platform_device *pdev, 1973 struct ocelot_pinctrl *info) 1974 { 1975 struct gpio_chip *gc; 1976 struct gpio_irq_chip *girq; 1977 int irq; 1978 1979 info->gpio_chip = ocelot_gpiolib_chip; 1980 1981 gc = &info->gpio_chip; 1982 gc->ngpio = info->desc->npins; 1983 gc->parent = &pdev->dev; 1984 gc->base = -1; 1985 gc->label = "ocelot-gpio"; 1986 1987 irq = platform_get_irq_optional(pdev, 0); 1988 if (irq > 0) { 1989 girq = &gc->irq; 1990 gpio_irq_chip_set_chip(girq, &ocelot_irqchip); 1991 girq->parent_handler = ocelot_irq_handler; 1992 girq->num_parents = 1; 1993 girq->parents = devm_kcalloc(&pdev->dev, 1, 1994 sizeof(*girq->parents), 1995 GFP_KERNEL); 1996 if (!girq->parents) 1997 return -ENOMEM; 1998 girq->parents[0] = irq; 1999 girq->default_type = IRQ_TYPE_NONE; 2000 girq->handler = handle_edge_irq; 2001 } 2002 2003 return devm_gpiochip_add_data(&pdev->dev, gc, info); 2004 } 2005 2006 static const struct of_device_id ocelot_pinctrl_of_match[] = { 2007 { .compatible = "mscc,luton-pinctrl", .data = &luton_desc }, 2008 { .compatible = "mscc,serval-pinctrl", .data = &serval_desc }, 2009 { .compatible = "mscc,ocelot-pinctrl", .data = &ocelot_desc }, 2010 { .compatible = "mscc,jaguar2-pinctrl", .data = &jaguar2_desc }, 2011 { .compatible = "mscc,servalt-pinctrl", .data = &servalt_desc }, 2012 { .compatible = "microchip,sparx5-pinctrl", .data = &sparx5_desc }, 2013 { .compatible = "microchip,lan966x-pinctrl", .data = &lan966x_desc }, 2014 {}, 2015 }; 2016 MODULE_DEVICE_TABLE(of, ocelot_pinctrl_of_match); 2017 2018 static struct regmap *ocelot_pinctrl_create_pincfg(struct platform_device *pdev, 2019 const struct ocelot_pinctrl *info) 2020 { 2021 void __iomem *base; 2022 2023 const struct regmap_config regmap_config = { 2024 .reg_bits = 32, 2025 .val_bits = 32, 2026 .reg_stride = 4, 2027 .max_register = info->desc->npins * 4, 2028 .name = "pincfg", 2029 }; 2030 2031 base = devm_platform_ioremap_resource(pdev, 1); 2032 if (IS_ERR(base)) { 2033 dev_dbg(&pdev->dev, "Failed to ioremap config registers (no extended pinconf)\n"); 2034 return NULL; 2035 } 2036 2037 return devm_regmap_init_mmio(&pdev->dev, base, ®map_config); 2038 } 2039 2040 static int ocelot_pinctrl_probe(struct platform_device *pdev) 2041 { 2042 const struct ocelot_match_data *data; 2043 struct device *dev = &pdev->dev; 2044 struct ocelot_pinctrl *info; 2045 struct reset_control *reset; 2046 struct regmap *pincfg; 2047 void __iomem *base; 2048 int ret; 2049 struct regmap_config regmap_config = { 2050 .reg_bits = 32, 2051 .val_bits = 32, 2052 .reg_stride = 4, 2053 }; 2054 2055 info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL); 2056 if (!info) 2057 return -ENOMEM; 2058 2059 data = device_get_match_data(dev); 2060 if (!data) 2061 return -EINVAL; 2062 2063 info->desc = devm_kmemdup(dev, &data->desc, sizeof(*info->desc), 2064 GFP_KERNEL); 2065 if (!info->desc) 2066 return -ENOMEM; 2067 2068 info->wq = alloc_ordered_workqueue("ocelot_ordered", 0); 2069 if (!info->wq) 2070 return -ENOMEM; 2071 2072 info->pincfg_data = &data->pincfg_data; 2073 2074 reset = devm_reset_control_get_optional_shared(dev, "switch"); 2075 if (IS_ERR(reset)) 2076 return dev_err_probe(dev, PTR_ERR(reset), 2077 "Failed to get reset\n"); 2078 reset_control_reset(reset); 2079 2080 base = devm_ioremap_resource(dev, 2081 platform_get_resource(pdev, IORESOURCE_MEM, 0)); 2082 if (IS_ERR(base)) 2083 return PTR_ERR(base); 2084 2085 info->stride = 1 + (info->desc->npins - 1) / 32; 2086 2087 regmap_config.max_register = OCELOT_GPIO_SD_MAP * info->stride + 15 * 4; 2088 2089 info->map = devm_regmap_init_mmio(dev, base, ®map_config); 2090 if (IS_ERR(info->map)) { 2091 dev_err(dev, "Failed to create regmap\n"); 2092 return PTR_ERR(info->map); 2093 } 2094 dev_set_drvdata(dev, info); 2095 info->dev = dev; 2096 2097 /* Pinconf registers */ 2098 if (info->desc->confops) { 2099 pincfg = ocelot_pinctrl_create_pincfg(pdev, info); 2100 if (IS_ERR(pincfg)) 2101 dev_dbg(dev, "Failed to create pincfg regmap\n"); 2102 else 2103 info->pincfg = pincfg; 2104 } 2105 2106 ret = ocelot_pinctrl_register(pdev, info); 2107 if (ret) 2108 return ret; 2109 2110 ret = ocelot_gpiochip_register(pdev, info); 2111 if (ret) 2112 return ret; 2113 2114 dev_info(dev, "driver registered\n"); 2115 2116 return 0; 2117 } 2118 2119 static int ocelot_pinctrl_remove(struct platform_device *pdev) 2120 { 2121 struct ocelot_pinctrl *info = platform_get_drvdata(pdev); 2122 2123 destroy_workqueue(info->wq); 2124 2125 return 0; 2126 } 2127 2128 static struct platform_driver ocelot_pinctrl_driver = { 2129 .driver = { 2130 .name = "pinctrl-ocelot", 2131 .of_match_table = of_match_ptr(ocelot_pinctrl_of_match), 2132 .suppress_bind_attrs = true, 2133 }, 2134 .probe = ocelot_pinctrl_probe, 2135 .remove = ocelot_pinctrl_remove, 2136 }; 2137 module_platform_driver(ocelot_pinctrl_driver); 2138 MODULE_LICENSE("Dual MIT/GPL"); 2139