1ce8dc094SAlexandre Belloni // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2ce8dc094SAlexandre Belloni /* 3ce8dc094SAlexandre Belloni * Microsemi SoCs pinctrl driver 4ce8dc094SAlexandre Belloni * 5ce8dc094SAlexandre Belloni * Author: <alexandre.belloni@free-electrons.com> 6ce8dc094SAlexandre Belloni * License: Dual MIT/GPL 7ce8dc094SAlexandre Belloni * Copyright (c) 2017 Microsemi Corporation 8ce8dc094SAlexandre Belloni */ 9ce8dc094SAlexandre Belloni 10ce8dc094SAlexandre Belloni #include <linux/gpio/driver.h> 11ce8dc094SAlexandre Belloni #include <linux/interrupt.h> 12ce8dc094SAlexandre Belloni #include <linux/io.h> 13181f604bSColin Foster #include <linux/mfd/ocelot.h> 14ce8dc094SAlexandre Belloni #include <linux/of_device.h> 15be36abb7SQuentin Schulz #include <linux/of_irq.h> 16ce8dc094SAlexandre Belloni #include <linux/of_platform.h> 17ce8dc094SAlexandre Belloni #include <linux/pinctrl/pinctrl.h> 18ce8dc094SAlexandre Belloni #include <linux/pinctrl/pinmux.h> 19ce8dc094SAlexandre Belloni #include <linux/pinctrl/pinconf.h> 20ce8dc094SAlexandre Belloni #include <linux/pinctrl/pinconf-generic.h> 21ce8dc094SAlexandre Belloni #include <linux/platform_device.h> 22ce8dc094SAlexandre Belloni #include <linux/regmap.h> 23453200afSMichael Walle #include <linux/reset.h> 24ce8dc094SAlexandre Belloni #include <linux/slab.h> 25ce8dc094SAlexandre Belloni 26ce8dc094SAlexandre Belloni #include "core.h" 27ce8dc094SAlexandre Belloni #include "pinconf.h" 28ce8dc094SAlexandre Belloni #include "pinmux.h" 29ce8dc094SAlexandre Belloni 30f8a74760SLars Povlsen #define ocelot_clrsetbits(addr, clear, set) \ 31f8a74760SLars Povlsen writel((readl(addr) & ~(clear)) | (set), (addr)) 32f8a74760SLars Povlsen 33f8a74760SLars Povlsen enum { 34f8a74760SLars Povlsen PINCONF_BIAS, 35f8a74760SLars Povlsen PINCONF_SCHMITT, 36f8a74760SLars Povlsen PINCONF_DRIVE_STRENGTH, 37f8a74760SLars Povlsen }; 38f8a74760SLars Povlsen 39f8a74760SLars Povlsen /* GPIO standard registers */ 40ce8dc094SAlexandre Belloni #define OCELOT_GPIO_OUT_SET 0x0 41ce8dc094SAlexandre Belloni #define OCELOT_GPIO_OUT_CLR 0x4 42ce8dc094SAlexandre Belloni #define OCELOT_GPIO_OUT 0x8 43ce8dc094SAlexandre Belloni #define OCELOT_GPIO_IN 0xc 44ce8dc094SAlexandre Belloni #define OCELOT_GPIO_OE 0x10 45ce8dc094SAlexandre Belloni #define OCELOT_GPIO_INTR 0x14 46ce8dc094SAlexandre Belloni #define OCELOT_GPIO_INTR_ENA 0x18 47ce8dc094SAlexandre Belloni #define OCELOT_GPIO_INTR_IDENT 0x1c 48ce8dc094SAlexandre Belloni #define OCELOT_GPIO_ALT0 0x20 49ce8dc094SAlexandre Belloni #define OCELOT_GPIO_ALT1 0x24 50ce8dc094SAlexandre Belloni #define OCELOT_GPIO_SD_MAP 0x28 51ce8dc094SAlexandre Belloni 52ce8dc094SAlexandre Belloni #define OCELOT_FUNC_PER_PIN 4 53ce8dc094SAlexandre Belloni 54ce8dc094SAlexandre Belloni enum { 55531d6ab3SKavyasree Kotagiri FUNC_CAN0_a, 56531d6ab3SKavyasree Kotagiri FUNC_CAN0_b, 57531d6ab3SKavyasree Kotagiri FUNC_CAN1, 58bf3e7f49SMichael Walle FUNC_CLKMON, 59ce8dc094SAlexandre Belloni FUNC_NONE, 60531d6ab3SKavyasree Kotagiri FUNC_FC0_a, 61531d6ab3SKavyasree Kotagiri FUNC_FC0_b, 62531d6ab3SKavyasree Kotagiri FUNC_FC0_c, 63531d6ab3SKavyasree Kotagiri FUNC_FC1_a, 64531d6ab3SKavyasree Kotagiri FUNC_FC1_b, 65531d6ab3SKavyasree Kotagiri FUNC_FC1_c, 66531d6ab3SKavyasree Kotagiri FUNC_FC2_a, 67531d6ab3SKavyasree Kotagiri FUNC_FC2_b, 68531d6ab3SKavyasree Kotagiri FUNC_FC3_a, 69531d6ab3SKavyasree Kotagiri FUNC_FC3_b, 70531d6ab3SKavyasree Kotagiri FUNC_FC3_c, 71531d6ab3SKavyasree Kotagiri FUNC_FC4_a, 72531d6ab3SKavyasree Kotagiri FUNC_FC4_b, 73531d6ab3SKavyasree Kotagiri FUNC_FC4_c, 74531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD0, 75531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD1, 76531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD2, 77531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD3, 78531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD4, 79531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD5, 80531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD6, 81531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD7, 82531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD8, 83531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD9, 84531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD10, 85531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD11, 86531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD12, 87531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD13, 88531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD14, 89531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD15, 90531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD16, 91531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD17, 92531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD18, 93531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD19, 94531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD20, 95ce8dc094SAlexandre Belloni FUNC_GPIO, 96531d6ab3SKavyasree Kotagiri FUNC_IB_TRG_a, 97531d6ab3SKavyasree Kotagiri FUNC_IB_TRG_b, 98531d6ab3SKavyasree Kotagiri FUNC_IB_TRG_c, 99f8a74760SLars Povlsen FUNC_IRQ0, 100531d6ab3SKavyasree Kotagiri FUNC_IRQ_IN_a, 101531d6ab3SKavyasree Kotagiri FUNC_IRQ_IN_b, 102531d6ab3SKavyasree Kotagiri FUNC_IRQ_IN_c, 103ce8dc094SAlexandre Belloni FUNC_IRQ0_IN, 104531d6ab3SKavyasree Kotagiri FUNC_IRQ_OUT_a, 105531d6ab3SKavyasree Kotagiri FUNC_IRQ_OUT_b, 106531d6ab3SKavyasree Kotagiri FUNC_IRQ_OUT_c, 107ce8dc094SAlexandre Belloni FUNC_IRQ0_OUT, 108f8a74760SLars Povlsen FUNC_IRQ1, 109ce8dc094SAlexandre Belloni FUNC_IRQ1_IN, 110ce8dc094SAlexandre Belloni FUNC_IRQ1_OUT, 111f8a74760SLars Povlsen FUNC_EXT_IRQ, 112edc72546SLars Povlsen FUNC_MIIM, 113531d6ab3SKavyasree Kotagiri FUNC_MIIM_a, 114531d6ab3SKavyasree Kotagiri FUNC_MIIM_b, 115531d6ab3SKavyasree Kotagiri FUNC_MIIM_c, 116531d6ab3SKavyasree Kotagiri FUNC_MIIM_Sa, 117531d6ab3SKavyasree Kotagiri FUNC_MIIM_Sb, 118531d6ab3SKavyasree Kotagiri FUNC_OB_TRG, 119531d6ab3SKavyasree Kotagiri FUNC_OB_TRG_a, 120531d6ab3SKavyasree Kotagiri FUNC_OB_TRG_b, 121f8a74760SLars Povlsen FUNC_PHY_LED, 122ce8dc094SAlexandre Belloni FUNC_PCI_WAKE, 123f8a74760SLars Povlsen FUNC_MD, 124ce8dc094SAlexandre Belloni FUNC_PTP0, 125ce8dc094SAlexandre Belloni FUNC_PTP1, 126ce8dc094SAlexandre Belloni FUNC_PTP2, 127ce8dc094SAlexandre Belloni FUNC_PTP3, 128d3683eebSHoratiu Vultur FUNC_PTPSYNC_0, 129531d6ab3SKavyasree Kotagiri FUNC_PTPSYNC_1, 130531d6ab3SKavyasree Kotagiri FUNC_PTPSYNC_2, 131531d6ab3SKavyasree Kotagiri FUNC_PTPSYNC_3, 132531d6ab3SKavyasree Kotagiri FUNC_PTPSYNC_4, 133531d6ab3SKavyasree Kotagiri FUNC_PTPSYNC_5, 134531d6ab3SKavyasree Kotagiri FUNC_PTPSYNC_6, 135531d6ab3SKavyasree Kotagiri FUNC_PTPSYNC_7, 136ce8dc094SAlexandre Belloni FUNC_PWM, 137e97e36cdSMichael Walle FUNC_PWM_a, 138e97e36cdSMichael Walle FUNC_PWM_b, 139531d6ab3SKavyasree Kotagiri FUNC_QSPI1, 140531d6ab3SKavyasree Kotagiri FUNC_QSPI2, 141531d6ab3SKavyasree Kotagiri FUNC_R, 142531d6ab3SKavyasree Kotagiri FUNC_RECO_a, 143531d6ab3SKavyasree Kotagiri FUNC_RECO_b, 144edc72546SLars Povlsen FUNC_RECO_CLK, 145531d6ab3SKavyasree Kotagiri FUNC_SD, 146edc72546SLars Povlsen FUNC_SFP, 147531d6ab3SKavyasree Kotagiri FUNC_SFP_SD, 148ce8dc094SAlexandre Belloni FUNC_SG0, 149da801ab5SAlexandre Belloni FUNC_SG1, 150da801ab5SAlexandre Belloni FUNC_SG2, 151531d6ab3SKavyasree Kotagiri FUNC_SGPIO_a, 152531d6ab3SKavyasree Kotagiri FUNC_SGPIO_b, 153ce8dc094SAlexandre Belloni FUNC_SI, 154f8a74760SLars Povlsen FUNC_SI2, 155ce8dc094SAlexandre Belloni FUNC_TACHO, 156531d6ab3SKavyasree Kotagiri FUNC_TACHO_a, 157531d6ab3SKavyasree Kotagiri FUNC_TACHO_b, 158ce8dc094SAlexandre Belloni FUNC_TWI, 159da801ab5SAlexandre Belloni FUNC_TWI2, 160f8a74760SLars Povlsen FUNC_TWI3, 161ce8dc094SAlexandre Belloni FUNC_TWI_SCL_M, 162531d6ab3SKavyasree Kotagiri FUNC_TWI_SLC_GATE, 163531d6ab3SKavyasree Kotagiri FUNC_TWI_SLC_GATE_AD, 164ce8dc094SAlexandre Belloni FUNC_UART, 165ce8dc094SAlexandre Belloni FUNC_UART2, 166f8a74760SLars Povlsen FUNC_UART3, 167531d6ab3SKavyasree Kotagiri FUNC_USB_H_a, 168531d6ab3SKavyasree Kotagiri FUNC_USB_H_b, 169531d6ab3SKavyasree Kotagiri FUNC_USB_H_c, 170531d6ab3SKavyasree Kotagiri FUNC_USB_S_a, 171531d6ab3SKavyasree Kotagiri FUNC_USB_S_b, 172531d6ab3SKavyasree Kotagiri FUNC_USB_S_c, 173f8a74760SLars Povlsen FUNC_PLL_STAT, 174f8a74760SLars Povlsen FUNC_EMMC, 175531d6ab3SKavyasree Kotagiri FUNC_EMMC_SD, 176f8a74760SLars Povlsen FUNC_REF_CLK, 177f8a74760SLars Povlsen FUNC_RCVRD_CLK, 178ce8dc094SAlexandre Belloni FUNC_MAX 179ce8dc094SAlexandre Belloni }; 180ce8dc094SAlexandre Belloni 181ce8dc094SAlexandre Belloni static const char *const ocelot_function_names[] = { 182531d6ab3SKavyasree Kotagiri [FUNC_CAN0_a] = "can0_a", 183531d6ab3SKavyasree Kotagiri [FUNC_CAN0_b] = "can0_b", 184531d6ab3SKavyasree Kotagiri [FUNC_CAN1] = "can1", 185bf3e7f49SMichael Walle [FUNC_CLKMON] = "clkmon", 186ce8dc094SAlexandre Belloni [FUNC_NONE] = "none", 187531d6ab3SKavyasree Kotagiri [FUNC_FC0_a] = "fc0_a", 188531d6ab3SKavyasree Kotagiri [FUNC_FC0_b] = "fc0_b", 189531d6ab3SKavyasree Kotagiri [FUNC_FC0_c] = "fc0_c", 190531d6ab3SKavyasree Kotagiri [FUNC_FC1_a] = "fc1_a", 191531d6ab3SKavyasree Kotagiri [FUNC_FC1_b] = "fc1_b", 192531d6ab3SKavyasree Kotagiri [FUNC_FC1_c] = "fc1_c", 193531d6ab3SKavyasree Kotagiri [FUNC_FC2_a] = "fc2_a", 194531d6ab3SKavyasree Kotagiri [FUNC_FC2_b] = "fc2_b", 195531d6ab3SKavyasree Kotagiri [FUNC_FC3_a] = "fc3_a", 196531d6ab3SKavyasree Kotagiri [FUNC_FC3_b] = "fc3_b", 197531d6ab3SKavyasree Kotagiri [FUNC_FC3_c] = "fc3_c", 198531d6ab3SKavyasree Kotagiri [FUNC_FC4_a] = "fc4_a", 199531d6ab3SKavyasree Kotagiri [FUNC_FC4_b] = "fc4_b", 200531d6ab3SKavyasree Kotagiri [FUNC_FC4_c] = "fc4_c", 201531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD0] = "fc_shrd0", 202531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD1] = "fc_shrd1", 203531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD2] = "fc_shrd2", 204531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD3] = "fc_shrd3", 205531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD4] = "fc_shrd4", 206531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD5] = "fc_shrd5", 207531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD6] = "fc_shrd6", 208531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD7] = "fc_shrd7", 209531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD8] = "fc_shrd8", 210531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD9] = "fc_shrd9", 211531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD10] = "fc_shrd10", 212531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD11] = "fc_shrd11", 213531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD12] = "fc_shrd12", 214531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD13] = "fc_shrd13", 215531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD14] = "fc_shrd14", 216531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD15] = "fc_shrd15", 217531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD16] = "fc_shrd16", 218531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD17] = "fc_shrd17", 219531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD18] = "fc_shrd18", 220531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD19] = "fc_shrd19", 221531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD20] = "fc_shrd20", 222ce8dc094SAlexandre Belloni [FUNC_GPIO] = "gpio", 223531d6ab3SKavyasree Kotagiri [FUNC_IB_TRG_a] = "ib_trig_a", 224531d6ab3SKavyasree Kotagiri [FUNC_IB_TRG_b] = "ib_trig_b", 225531d6ab3SKavyasree Kotagiri [FUNC_IB_TRG_c] = "ib_trig_c", 226f8a74760SLars Povlsen [FUNC_IRQ0] = "irq0", 227531d6ab3SKavyasree Kotagiri [FUNC_IRQ_IN_a] = "irq_in_a", 228531d6ab3SKavyasree Kotagiri [FUNC_IRQ_IN_b] = "irq_in_b", 229531d6ab3SKavyasree Kotagiri [FUNC_IRQ_IN_c] = "irq_in_c", 230ce8dc094SAlexandre Belloni [FUNC_IRQ0_IN] = "irq0_in", 231531d6ab3SKavyasree Kotagiri [FUNC_IRQ_OUT_a] = "irq_out_a", 232531d6ab3SKavyasree Kotagiri [FUNC_IRQ_OUT_b] = "irq_out_b", 233531d6ab3SKavyasree Kotagiri [FUNC_IRQ_OUT_c] = "irq_out_c", 234ce8dc094SAlexandre Belloni [FUNC_IRQ0_OUT] = "irq0_out", 235f8a74760SLars Povlsen [FUNC_IRQ1] = "irq1", 236ce8dc094SAlexandre Belloni [FUNC_IRQ1_IN] = "irq1_in", 237ce8dc094SAlexandre Belloni [FUNC_IRQ1_OUT] = "irq1_out", 238f8a74760SLars Povlsen [FUNC_EXT_IRQ] = "ext_irq", 239edc72546SLars Povlsen [FUNC_MIIM] = "miim", 240531d6ab3SKavyasree Kotagiri [FUNC_MIIM_a] = "miim_a", 241531d6ab3SKavyasree Kotagiri [FUNC_MIIM_b] = "miim_b", 242531d6ab3SKavyasree Kotagiri [FUNC_MIIM_c] = "miim_c", 243531d6ab3SKavyasree Kotagiri [FUNC_MIIM_Sa] = "miim_slave_a", 244531d6ab3SKavyasree Kotagiri [FUNC_MIIM_Sb] = "miim_slave_b", 245f8a74760SLars Povlsen [FUNC_PHY_LED] = "phy_led", 246ce8dc094SAlexandre Belloni [FUNC_PCI_WAKE] = "pci_wake", 247f8a74760SLars Povlsen [FUNC_MD] = "md", 248531d6ab3SKavyasree Kotagiri [FUNC_OB_TRG] = "ob_trig", 249531d6ab3SKavyasree Kotagiri [FUNC_OB_TRG_a] = "ob_trig_a", 250531d6ab3SKavyasree Kotagiri [FUNC_OB_TRG_b] = "ob_trig_b", 251ce8dc094SAlexandre Belloni [FUNC_PTP0] = "ptp0", 252ce8dc094SAlexandre Belloni [FUNC_PTP1] = "ptp1", 253ce8dc094SAlexandre Belloni [FUNC_PTP2] = "ptp2", 254ce8dc094SAlexandre Belloni [FUNC_PTP3] = "ptp3", 255d3683eebSHoratiu Vultur [FUNC_PTPSYNC_0] = "ptpsync_0", 256531d6ab3SKavyasree Kotagiri [FUNC_PTPSYNC_1] = "ptpsync_1", 257531d6ab3SKavyasree Kotagiri [FUNC_PTPSYNC_2] = "ptpsync_2", 258531d6ab3SKavyasree Kotagiri [FUNC_PTPSYNC_3] = "ptpsync_3", 259531d6ab3SKavyasree Kotagiri [FUNC_PTPSYNC_4] = "ptpsync_4", 260531d6ab3SKavyasree Kotagiri [FUNC_PTPSYNC_5] = "ptpsync_5", 261531d6ab3SKavyasree Kotagiri [FUNC_PTPSYNC_6] = "ptpsync_6", 262531d6ab3SKavyasree Kotagiri [FUNC_PTPSYNC_7] = "ptpsync_7", 263ce8dc094SAlexandre Belloni [FUNC_PWM] = "pwm", 264e97e36cdSMichael Walle [FUNC_PWM_a] = "pwm_a", 265e97e36cdSMichael Walle [FUNC_PWM_b] = "pwm_b", 266531d6ab3SKavyasree Kotagiri [FUNC_QSPI1] = "qspi1", 267531d6ab3SKavyasree Kotagiri [FUNC_QSPI2] = "qspi2", 268531d6ab3SKavyasree Kotagiri [FUNC_R] = "reserved", 269531d6ab3SKavyasree Kotagiri [FUNC_RECO_a] = "reco_a", 270531d6ab3SKavyasree Kotagiri [FUNC_RECO_b] = "reco_b", 271edc72546SLars Povlsen [FUNC_RECO_CLK] = "reco_clk", 272531d6ab3SKavyasree Kotagiri [FUNC_SD] = "sd", 273edc72546SLars Povlsen [FUNC_SFP] = "sfp", 274531d6ab3SKavyasree Kotagiri [FUNC_SFP_SD] = "sfp_sd", 275ce8dc094SAlexandre Belloni [FUNC_SG0] = "sg0", 276da801ab5SAlexandre Belloni [FUNC_SG1] = "sg1", 277da801ab5SAlexandre Belloni [FUNC_SG2] = "sg2", 278531d6ab3SKavyasree Kotagiri [FUNC_SGPIO_a] = "sgpio_a", 279531d6ab3SKavyasree Kotagiri [FUNC_SGPIO_b] = "sgpio_b", 280ce8dc094SAlexandre Belloni [FUNC_SI] = "si", 281f8a74760SLars Povlsen [FUNC_SI2] = "si2", 282ce8dc094SAlexandre Belloni [FUNC_TACHO] = "tacho", 283531d6ab3SKavyasree Kotagiri [FUNC_TACHO_a] = "tacho_a", 284531d6ab3SKavyasree Kotagiri [FUNC_TACHO_b] = "tacho_b", 285ce8dc094SAlexandre Belloni [FUNC_TWI] = "twi", 286da801ab5SAlexandre Belloni [FUNC_TWI2] = "twi2", 287f8a74760SLars Povlsen [FUNC_TWI3] = "twi3", 288ce8dc094SAlexandre Belloni [FUNC_TWI_SCL_M] = "twi_scl_m", 289531d6ab3SKavyasree Kotagiri [FUNC_TWI_SLC_GATE] = "twi_slc_gate", 290531d6ab3SKavyasree Kotagiri [FUNC_TWI_SLC_GATE_AD] = "twi_slc_gate_ad", 291531d6ab3SKavyasree Kotagiri [FUNC_USB_H_a] = "usb_host_a", 292531d6ab3SKavyasree Kotagiri [FUNC_USB_H_b] = "usb_host_b", 293531d6ab3SKavyasree Kotagiri [FUNC_USB_H_c] = "usb_host_c", 294531d6ab3SKavyasree Kotagiri [FUNC_USB_S_a] = "usb_slave_a", 295531d6ab3SKavyasree Kotagiri [FUNC_USB_S_b] = "usb_slave_b", 296531d6ab3SKavyasree Kotagiri [FUNC_USB_S_c] = "usb_slave_c", 297ce8dc094SAlexandre Belloni [FUNC_UART] = "uart", 298ce8dc094SAlexandre Belloni [FUNC_UART2] = "uart2", 299f8a74760SLars Povlsen [FUNC_UART3] = "uart3", 300f8a74760SLars Povlsen [FUNC_PLL_STAT] = "pll_stat", 301f8a74760SLars Povlsen [FUNC_EMMC] = "emmc", 302531d6ab3SKavyasree Kotagiri [FUNC_EMMC_SD] = "emmc_sd", 303f8a74760SLars Povlsen [FUNC_REF_CLK] = "ref_clk", 304f8a74760SLars Povlsen [FUNC_RCVRD_CLK] = "rcvrd_clk", 305ce8dc094SAlexandre Belloni }; 306ce8dc094SAlexandre Belloni 307ce8dc094SAlexandre Belloni struct ocelot_pmx_func { 308ce8dc094SAlexandre Belloni const char **groups; 309ce8dc094SAlexandre Belloni unsigned int ngroups; 310ce8dc094SAlexandre Belloni }; 311ce8dc094SAlexandre Belloni 312ce8dc094SAlexandre Belloni struct ocelot_pin_caps { 313ce8dc094SAlexandre Belloni unsigned int pin; 314ce8dc094SAlexandre Belloni unsigned char functions[OCELOT_FUNC_PER_PIN]; 315531d6ab3SKavyasree Kotagiri unsigned char a_functions[OCELOT_FUNC_PER_PIN]; /* Additional functions */ 316ce8dc094SAlexandre Belloni }; 317ce8dc094SAlexandre Belloni 318dc62db71SHoratiu Vultur struct ocelot_pincfg_data { 319dc62db71SHoratiu Vultur u8 pd_bit; 320dc62db71SHoratiu Vultur u8 pu_bit; 321dc62db71SHoratiu Vultur u8 drive_bits; 322dc62db71SHoratiu Vultur u8 schmitt_bit; 323dc62db71SHoratiu Vultur }; 324dc62db71SHoratiu Vultur 325ce8dc094SAlexandre Belloni struct ocelot_pinctrl { 326ce8dc094SAlexandre Belloni struct device *dev; 327ce8dc094SAlexandre Belloni struct pinctrl_dev *pctl; 328ce8dc094SAlexandre Belloni struct gpio_chip gpio_chip; 329ce8dc094SAlexandre Belloni struct regmap *map; 330076d9e71SColin Foster struct regmap *pincfg; 331da801ab5SAlexandre Belloni struct pinctrl_desc *desc; 332dc62db71SHoratiu Vultur const struct ocelot_pincfg_data *pincfg_data; 333ce8dc094SAlexandre Belloni struct ocelot_pmx_func func[FUNC_MAX]; 334da801ab5SAlexandre Belloni u8 stride; 335c297561bSHoratiu Vultur struct workqueue_struct *wq; 336ce8dc094SAlexandre Belloni }; 337ce8dc094SAlexandre Belloni 338dc62db71SHoratiu Vultur struct ocelot_match_data { 339dc62db71SHoratiu Vultur struct pinctrl_desc desc; 340dc62db71SHoratiu Vultur struct ocelot_pincfg_data pincfg_data; 341dc62db71SHoratiu Vultur }; 342dc62db71SHoratiu Vultur 343c297561bSHoratiu Vultur struct ocelot_irq_work { 344c297561bSHoratiu Vultur struct work_struct irq_work; 345c297561bSHoratiu Vultur struct irq_desc *irq_desc; 346c297561bSHoratiu Vultur }; 347c297561bSHoratiu Vultur 3488f27440dSLars Povlsen #define LUTON_P(p, f0, f1) \ 3498f27440dSLars Povlsen static struct ocelot_pin_caps luton_pin_##p = { \ 3508f27440dSLars Povlsen .pin = p, \ 3518f27440dSLars Povlsen .functions = { \ 3528f27440dSLars Povlsen FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_NONE, \ 3538f27440dSLars Povlsen }, \ 3548f27440dSLars Povlsen } 3558f27440dSLars Povlsen 3568f27440dSLars Povlsen LUTON_P(0, SG0, NONE); 3578f27440dSLars Povlsen LUTON_P(1, SG0, NONE); 3588f27440dSLars Povlsen LUTON_P(2, SG0, NONE); 3598f27440dSLars Povlsen LUTON_P(3, SG0, NONE); 3608f27440dSLars Povlsen LUTON_P(4, TACHO, NONE); 3618f27440dSLars Povlsen LUTON_P(5, TWI, PHY_LED); 3628f27440dSLars Povlsen LUTON_P(6, TWI, PHY_LED); 3638f27440dSLars Povlsen LUTON_P(7, NONE, PHY_LED); 3648f27440dSLars Povlsen LUTON_P(8, EXT_IRQ, PHY_LED); 3658f27440dSLars Povlsen LUTON_P(9, EXT_IRQ, PHY_LED); 3668f27440dSLars Povlsen LUTON_P(10, SFP, PHY_LED); 3678f27440dSLars Povlsen LUTON_P(11, SFP, PHY_LED); 3688f27440dSLars Povlsen LUTON_P(12, SFP, PHY_LED); 3698f27440dSLars Povlsen LUTON_P(13, SFP, PHY_LED); 3708f27440dSLars Povlsen LUTON_P(14, SI, PHY_LED); 3718f27440dSLars Povlsen LUTON_P(15, SI, PHY_LED); 3728f27440dSLars Povlsen LUTON_P(16, SI, PHY_LED); 3738f27440dSLars Povlsen LUTON_P(17, SFP, PHY_LED); 3748f27440dSLars Povlsen LUTON_P(18, SFP, PHY_LED); 3758f27440dSLars Povlsen LUTON_P(19, SFP, PHY_LED); 3768f27440dSLars Povlsen LUTON_P(20, SFP, PHY_LED); 3778f27440dSLars Povlsen LUTON_P(21, SFP, PHY_LED); 3788f27440dSLars Povlsen LUTON_P(22, SFP, PHY_LED); 3798f27440dSLars Povlsen LUTON_P(23, SFP, PHY_LED); 3808f27440dSLars Povlsen LUTON_P(24, SFP, PHY_LED); 3818f27440dSLars Povlsen LUTON_P(25, SFP, PHY_LED); 3828f27440dSLars Povlsen LUTON_P(26, SFP, PHY_LED); 3838f27440dSLars Povlsen LUTON_P(27, SFP, PHY_LED); 3848f27440dSLars Povlsen LUTON_P(28, SFP, PHY_LED); 3858f27440dSLars Povlsen LUTON_P(29, PWM, NONE); 3868f27440dSLars Povlsen LUTON_P(30, UART, NONE); 3878f27440dSLars Povlsen LUTON_P(31, UART, NONE); 3888f27440dSLars Povlsen 3898f27440dSLars Povlsen #define LUTON_PIN(n) { \ 3908f27440dSLars Povlsen .number = n, \ 3918f27440dSLars Povlsen .name = "GPIO_"#n, \ 3928f27440dSLars Povlsen .drv_data = &luton_pin_##n \ 3938f27440dSLars Povlsen } 3948f27440dSLars Povlsen 3958f27440dSLars Povlsen static const struct pinctrl_pin_desc luton_pins[] = { 3968f27440dSLars Povlsen LUTON_PIN(0), 3978f27440dSLars Povlsen LUTON_PIN(1), 3988f27440dSLars Povlsen LUTON_PIN(2), 3998f27440dSLars Povlsen LUTON_PIN(3), 4008f27440dSLars Povlsen LUTON_PIN(4), 4018f27440dSLars Povlsen LUTON_PIN(5), 4028f27440dSLars Povlsen LUTON_PIN(6), 4038f27440dSLars Povlsen LUTON_PIN(7), 4048f27440dSLars Povlsen LUTON_PIN(8), 4058f27440dSLars Povlsen LUTON_PIN(9), 4068f27440dSLars Povlsen LUTON_PIN(10), 4078f27440dSLars Povlsen LUTON_PIN(11), 4088f27440dSLars Povlsen LUTON_PIN(12), 4098f27440dSLars Povlsen LUTON_PIN(13), 4108f27440dSLars Povlsen LUTON_PIN(14), 4118f27440dSLars Povlsen LUTON_PIN(15), 4128f27440dSLars Povlsen LUTON_PIN(16), 4138f27440dSLars Povlsen LUTON_PIN(17), 4148f27440dSLars Povlsen LUTON_PIN(18), 4158f27440dSLars Povlsen LUTON_PIN(19), 4168f27440dSLars Povlsen LUTON_PIN(20), 4178f27440dSLars Povlsen LUTON_PIN(21), 4188f27440dSLars Povlsen LUTON_PIN(22), 4198f27440dSLars Povlsen LUTON_PIN(23), 4208f27440dSLars Povlsen LUTON_PIN(24), 4218f27440dSLars Povlsen LUTON_PIN(25), 4228f27440dSLars Povlsen LUTON_PIN(26), 4238f27440dSLars Povlsen LUTON_PIN(27), 4248f27440dSLars Povlsen LUTON_PIN(28), 4258f27440dSLars Povlsen LUTON_PIN(29), 4268f27440dSLars Povlsen LUTON_PIN(30), 4278f27440dSLars Povlsen LUTON_PIN(31), 4288f27440dSLars Povlsen }; 4298f27440dSLars Povlsen 4306e6347e2SLars Povlsen #define SERVAL_P(p, f0, f1, f2) \ 4316e6347e2SLars Povlsen static struct ocelot_pin_caps serval_pin_##p = { \ 4326e6347e2SLars Povlsen .pin = p, \ 4336e6347e2SLars Povlsen .functions = { \ 4346e6347e2SLars Povlsen FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2, \ 4356e6347e2SLars Povlsen }, \ 4366e6347e2SLars Povlsen } 4376e6347e2SLars Povlsen 4386e6347e2SLars Povlsen SERVAL_P(0, SG0, NONE, NONE); 4396e6347e2SLars Povlsen SERVAL_P(1, SG0, NONE, NONE); 4406e6347e2SLars Povlsen SERVAL_P(2, SG0, NONE, NONE); 4416e6347e2SLars Povlsen SERVAL_P(3, SG0, NONE, NONE); 4426e6347e2SLars Povlsen SERVAL_P(4, TACHO, NONE, NONE); 4436e6347e2SLars Povlsen SERVAL_P(5, PWM, NONE, NONE); 4446e6347e2SLars Povlsen SERVAL_P(6, TWI, NONE, NONE); 4456e6347e2SLars Povlsen SERVAL_P(7, TWI, NONE, NONE); 4466e6347e2SLars Povlsen SERVAL_P(8, SI, NONE, NONE); 4476e6347e2SLars Povlsen SERVAL_P(9, SI, MD, NONE); 4486e6347e2SLars Povlsen SERVAL_P(10, SI, MD, NONE); 4496e6347e2SLars Povlsen SERVAL_P(11, SFP, MD, TWI_SCL_M); 4506e6347e2SLars Povlsen SERVAL_P(12, SFP, MD, TWI_SCL_M); 4516e6347e2SLars Povlsen SERVAL_P(13, SFP, UART2, TWI_SCL_M); 4526e6347e2SLars Povlsen SERVAL_P(14, SFP, UART2, TWI_SCL_M); 4536e6347e2SLars Povlsen SERVAL_P(15, SFP, PTP0, TWI_SCL_M); 4546e6347e2SLars Povlsen SERVAL_P(16, SFP, PTP0, TWI_SCL_M); 4556e6347e2SLars Povlsen SERVAL_P(17, SFP, PCI_WAKE, TWI_SCL_M); 4566e6347e2SLars Povlsen SERVAL_P(18, SFP, NONE, TWI_SCL_M); 4576e6347e2SLars Povlsen SERVAL_P(19, SFP, NONE, TWI_SCL_M); 4586e6347e2SLars Povlsen SERVAL_P(20, SFP, NONE, TWI_SCL_M); 4596e6347e2SLars Povlsen SERVAL_P(21, SFP, NONE, TWI_SCL_M); 4606e6347e2SLars Povlsen SERVAL_P(22, NONE, NONE, NONE); 4616e6347e2SLars Povlsen SERVAL_P(23, NONE, NONE, NONE); 4626e6347e2SLars Povlsen SERVAL_P(24, NONE, NONE, NONE); 4636e6347e2SLars Povlsen SERVAL_P(25, NONE, NONE, NONE); 4646e6347e2SLars Povlsen SERVAL_P(26, UART, NONE, NONE); 4656e6347e2SLars Povlsen SERVAL_P(27, UART, NONE, NONE); 4666e6347e2SLars Povlsen SERVAL_P(28, IRQ0, NONE, NONE); 4676e6347e2SLars Povlsen SERVAL_P(29, IRQ1, NONE, NONE); 4686e6347e2SLars Povlsen SERVAL_P(30, PTP0, NONE, NONE); 4696e6347e2SLars Povlsen SERVAL_P(31, PTP0, NONE, NONE); 4706e6347e2SLars Povlsen 4716e6347e2SLars Povlsen #define SERVAL_PIN(n) { \ 4726e6347e2SLars Povlsen .number = n, \ 4736e6347e2SLars Povlsen .name = "GPIO_"#n, \ 4746e6347e2SLars Povlsen .drv_data = &serval_pin_##n \ 4756e6347e2SLars Povlsen } 4766e6347e2SLars Povlsen 4776e6347e2SLars Povlsen static const struct pinctrl_pin_desc serval_pins[] = { 4786e6347e2SLars Povlsen SERVAL_PIN(0), 4796e6347e2SLars Povlsen SERVAL_PIN(1), 4806e6347e2SLars Povlsen SERVAL_PIN(2), 4816e6347e2SLars Povlsen SERVAL_PIN(3), 4826e6347e2SLars Povlsen SERVAL_PIN(4), 4836e6347e2SLars Povlsen SERVAL_PIN(5), 4846e6347e2SLars Povlsen SERVAL_PIN(6), 4856e6347e2SLars Povlsen SERVAL_PIN(7), 4866e6347e2SLars Povlsen SERVAL_PIN(8), 4876e6347e2SLars Povlsen SERVAL_PIN(9), 4886e6347e2SLars Povlsen SERVAL_PIN(10), 4896e6347e2SLars Povlsen SERVAL_PIN(11), 4906e6347e2SLars Povlsen SERVAL_PIN(12), 4916e6347e2SLars Povlsen SERVAL_PIN(13), 4926e6347e2SLars Povlsen SERVAL_PIN(14), 4936e6347e2SLars Povlsen SERVAL_PIN(15), 4946e6347e2SLars Povlsen SERVAL_PIN(16), 4956e6347e2SLars Povlsen SERVAL_PIN(17), 4966e6347e2SLars Povlsen SERVAL_PIN(18), 4976e6347e2SLars Povlsen SERVAL_PIN(19), 4986e6347e2SLars Povlsen SERVAL_PIN(20), 4996e6347e2SLars Povlsen SERVAL_PIN(21), 5006e6347e2SLars Povlsen SERVAL_PIN(22), 5016e6347e2SLars Povlsen SERVAL_PIN(23), 5026e6347e2SLars Povlsen SERVAL_PIN(24), 5036e6347e2SLars Povlsen SERVAL_PIN(25), 5046e6347e2SLars Povlsen SERVAL_PIN(26), 5056e6347e2SLars Povlsen SERVAL_PIN(27), 5066e6347e2SLars Povlsen SERVAL_PIN(28), 5076e6347e2SLars Povlsen SERVAL_PIN(29), 5086e6347e2SLars Povlsen SERVAL_PIN(30), 5096e6347e2SLars Povlsen SERVAL_PIN(31), 5106e6347e2SLars Povlsen }; 5116e6347e2SLars Povlsen 512ce8dc094SAlexandre Belloni #define OCELOT_P(p, f0, f1, f2) \ 513ce8dc094SAlexandre Belloni static struct ocelot_pin_caps ocelot_pin_##p = { \ 514ce8dc094SAlexandre Belloni .pin = p, \ 515ce8dc094SAlexandre Belloni .functions = { \ 516ce8dc094SAlexandre Belloni FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2, \ 517ce8dc094SAlexandre Belloni }, \ 518ce8dc094SAlexandre Belloni } 519ce8dc094SAlexandre Belloni 520ce8dc094SAlexandre Belloni OCELOT_P(0, SG0, NONE, NONE); 521ce8dc094SAlexandre Belloni OCELOT_P(1, SG0, NONE, NONE); 522ce8dc094SAlexandre Belloni OCELOT_P(2, SG0, NONE, NONE); 523ce8dc094SAlexandre Belloni OCELOT_P(3, SG0, NONE, NONE); 52417f79084SAlexandre Belloni OCELOT_P(4, IRQ0_IN, IRQ0_OUT, TWI_SCL_M); 525ce8dc094SAlexandre Belloni OCELOT_P(5, IRQ1_IN, IRQ1_OUT, PCI_WAKE); 526ce8dc094SAlexandre Belloni OCELOT_P(6, UART, TWI_SCL_M, NONE); 527ce8dc094SAlexandre Belloni OCELOT_P(7, UART, TWI_SCL_M, NONE); 528ce8dc094SAlexandre Belloni OCELOT_P(8, SI, TWI_SCL_M, IRQ0_OUT); 529ce8dc094SAlexandre Belloni OCELOT_P(9, SI, TWI_SCL_M, IRQ1_OUT); 530edc72546SLars Povlsen OCELOT_P(10, PTP2, TWI_SCL_M, SFP); 531edc72546SLars Povlsen OCELOT_P(11, PTP3, TWI_SCL_M, SFP); 532edc72546SLars Povlsen OCELOT_P(12, UART2, TWI_SCL_M, SFP); 533edc72546SLars Povlsen OCELOT_P(13, UART2, TWI_SCL_M, SFP); 534edc72546SLars Povlsen OCELOT_P(14, MIIM, TWI_SCL_M, SFP); 535edc72546SLars Povlsen OCELOT_P(15, MIIM, TWI_SCL_M, SFP); 536ce8dc094SAlexandre Belloni OCELOT_P(16, TWI, NONE, SI); 537ce8dc094SAlexandre Belloni OCELOT_P(17, TWI, TWI_SCL_M, SI); 538ce8dc094SAlexandre Belloni OCELOT_P(18, PTP0, TWI_SCL_M, NONE); 539ce8dc094SAlexandre Belloni OCELOT_P(19, PTP1, TWI_SCL_M, NONE); 540edc72546SLars Povlsen OCELOT_P(20, RECO_CLK, TACHO, TWI_SCL_M); 541edc72546SLars Povlsen OCELOT_P(21, RECO_CLK, PWM, TWI_SCL_M); 542ce8dc094SAlexandre Belloni 543ce8dc094SAlexandre Belloni #define OCELOT_PIN(n) { \ 544ce8dc094SAlexandre Belloni .number = n, \ 545ce8dc094SAlexandre Belloni .name = "GPIO_"#n, \ 546ce8dc094SAlexandre Belloni .drv_data = &ocelot_pin_##n \ 547ce8dc094SAlexandre Belloni } 548ce8dc094SAlexandre Belloni 549ce8dc094SAlexandre Belloni static const struct pinctrl_pin_desc ocelot_pins[] = { 550ce8dc094SAlexandre Belloni OCELOT_PIN(0), 551ce8dc094SAlexandre Belloni OCELOT_PIN(1), 552ce8dc094SAlexandre Belloni OCELOT_PIN(2), 553ce8dc094SAlexandre Belloni OCELOT_PIN(3), 554ce8dc094SAlexandre Belloni OCELOT_PIN(4), 555ce8dc094SAlexandre Belloni OCELOT_PIN(5), 556ce8dc094SAlexandre Belloni OCELOT_PIN(6), 557ce8dc094SAlexandre Belloni OCELOT_PIN(7), 558ce8dc094SAlexandre Belloni OCELOT_PIN(8), 559ce8dc094SAlexandre Belloni OCELOT_PIN(9), 560ce8dc094SAlexandre Belloni OCELOT_PIN(10), 561ce8dc094SAlexandre Belloni OCELOT_PIN(11), 562ce8dc094SAlexandre Belloni OCELOT_PIN(12), 563ce8dc094SAlexandre Belloni OCELOT_PIN(13), 564ce8dc094SAlexandre Belloni OCELOT_PIN(14), 565ce8dc094SAlexandre Belloni OCELOT_PIN(15), 566ce8dc094SAlexandre Belloni OCELOT_PIN(16), 567ce8dc094SAlexandre Belloni OCELOT_PIN(17), 568ce8dc094SAlexandre Belloni OCELOT_PIN(18), 569ce8dc094SAlexandre Belloni OCELOT_PIN(19), 570ce8dc094SAlexandre Belloni OCELOT_PIN(20), 571ce8dc094SAlexandre Belloni OCELOT_PIN(21), 572ce8dc094SAlexandre Belloni }; 573ce8dc094SAlexandre Belloni 574da801ab5SAlexandre Belloni #define JAGUAR2_P(p, f0, f1) \ 575da801ab5SAlexandre Belloni static struct ocelot_pin_caps jaguar2_pin_##p = { \ 576da801ab5SAlexandre Belloni .pin = p, \ 577da801ab5SAlexandre Belloni .functions = { \ 578da801ab5SAlexandre Belloni FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_NONE \ 579da801ab5SAlexandre Belloni }, \ 580da801ab5SAlexandre Belloni } 581da801ab5SAlexandre Belloni 582da801ab5SAlexandre Belloni JAGUAR2_P(0, SG0, NONE); 583da801ab5SAlexandre Belloni JAGUAR2_P(1, SG0, NONE); 584da801ab5SAlexandre Belloni JAGUAR2_P(2, SG0, NONE); 585da801ab5SAlexandre Belloni JAGUAR2_P(3, SG0, NONE); 586da801ab5SAlexandre Belloni JAGUAR2_P(4, SG1, NONE); 587da801ab5SAlexandre Belloni JAGUAR2_P(5, SG1, NONE); 588da801ab5SAlexandre Belloni JAGUAR2_P(6, IRQ0_IN, IRQ0_OUT); 589da801ab5SAlexandre Belloni JAGUAR2_P(7, IRQ1_IN, IRQ1_OUT); 590da801ab5SAlexandre Belloni JAGUAR2_P(8, PTP0, NONE); 591da801ab5SAlexandre Belloni JAGUAR2_P(9, PTP1, NONE); 592da801ab5SAlexandre Belloni JAGUAR2_P(10, UART, NONE); 593da801ab5SAlexandre Belloni JAGUAR2_P(11, UART, NONE); 594da801ab5SAlexandre Belloni JAGUAR2_P(12, SG1, NONE); 595da801ab5SAlexandre Belloni JAGUAR2_P(13, SG1, NONE); 596da801ab5SAlexandre Belloni JAGUAR2_P(14, TWI, TWI_SCL_M); 597da801ab5SAlexandre Belloni JAGUAR2_P(15, TWI, NONE); 598da801ab5SAlexandre Belloni JAGUAR2_P(16, SI, TWI_SCL_M); 599da801ab5SAlexandre Belloni JAGUAR2_P(17, SI, TWI_SCL_M); 600da801ab5SAlexandre Belloni JAGUAR2_P(18, SI, TWI_SCL_M); 601da801ab5SAlexandre Belloni JAGUAR2_P(19, PCI_WAKE, NONE); 602da801ab5SAlexandre Belloni JAGUAR2_P(20, IRQ0_OUT, TWI_SCL_M); 603da801ab5SAlexandre Belloni JAGUAR2_P(21, IRQ1_OUT, TWI_SCL_M); 604da801ab5SAlexandre Belloni JAGUAR2_P(22, TACHO, NONE); 605da801ab5SAlexandre Belloni JAGUAR2_P(23, PWM, NONE); 606da801ab5SAlexandre Belloni JAGUAR2_P(24, UART2, NONE); 607da801ab5SAlexandre Belloni JAGUAR2_P(25, UART2, SI); 608da801ab5SAlexandre Belloni JAGUAR2_P(26, PTP2, SI); 609da801ab5SAlexandre Belloni JAGUAR2_P(27, PTP3, SI); 610da801ab5SAlexandre Belloni JAGUAR2_P(28, TWI2, SI); 611da801ab5SAlexandre Belloni JAGUAR2_P(29, TWI2, SI); 612da801ab5SAlexandre Belloni JAGUAR2_P(30, SG2, SI); 613da801ab5SAlexandre Belloni JAGUAR2_P(31, SG2, SI); 614da801ab5SAlexandre Belloni JAGUAR2_P(32, SG2, SI); 615da801ab5SAlexandre Belloni JAGUAR2_P(33, SG2, SI); 616da801ab5SAlexandre Belloni JAGUAR2_P(34, NONE, TWI_SCL_M); 617da801ab5SAlexandre Belloni JAGUAR2_P(35, NONE, TWI_SCL_M); 618da801ab5SAlexandre Belloni JAGUAR2_P(36, NONE, TWI_SCL_M); 619da801ab5SAlexandre Belloni JAGUAR2_P(37, NONE, TWI_SCL_M); 620da801ab5SAlexandre Belloni JAGUAR2_P(38, NONE, TWI_SCL_M); 621da801ab5SAlexandre Belloni JAGUAR2_P(39, NONE, TWI_SCL_M); 622da801ab5SAlexandre Belloni JAGUAR2_P(40, NONE, TWI_SCL_M); 623da801ab5SAlexandre Belloni JAGUAR2_P(41, NONE, TWI_SCL_M); 624da801ab5SAlexandre Belloni JAGUAR2_P(42, NONE, TWI_SCL_M); 625da801ab5SAlexandre Belloni JAGUAR2_P(43, NONE, TWI_SCL_M); 626edc72546SLars Povlsen JAGUAR2_P(44, NONE, SFP); 627edc72546SLars Povlsen JAGUAR2_P(45, NONE, SFP); 628edc72546SLars Povlsen JAGUAR2_P(46, NONE, SFP); 629edc72546SLars Povlsen JAGUAR2_P(47, NONE, SFP); 630edc72546SLars Povlsen JAGUAR2_P(48, SFP, NONE); 631edc72546SLars Povlsen JAGUAR2_P(49, SFP, SI); 632edc72546SLars Povlsen JAGUAR2_P(50, SFP, SI); 633edc72546SLars Povlsen JAGUAR2_P(51, SFP, SI); 634edc72546SLars Povlsen JAGUAR2_P(52, SFP, NONE); 635edc72546SLars Povlsen JAGUAR2_P(53, SFP, NONE); 636edc72546SLars Povlsen JAGUAR2_P(54, SFP, NONE); 637edc72546SLars Povlsen JAGUAR2_P(55, SFP, NONE); 638edc72546SLars Povlsen JAGUAR2_P(56, MIIM, SFP); 639edc72546SLars Povlsen JAGUAR2_P(57, MIIM, SFP); 640edc72546SLars Povlsen JAGUAR2_P(58, MIIM, SFP); 641edc72546SLars Povlsen JAGUAR2_P(59, MIIM, SFP); 642da801ab5SAlexandre Belloni JAGUAR2_P(60, NONE, NONE); 643da801ab5SAlexandre Belloni JAGUAR2_P(61, NONE, NONE); 644da801ab5SAlexandre Belloni JAGUAR2_P(62, NONE, NONE); 645da801ab5SAlexandre Belloni JAGUAR2_P(63, NONE, NONE); 646da801ab5SAlexandre Belloni 647da801ab5SAlexandre Belloni #define JAGUAR2_PIN(n) { \ 648da801ab5SAlexandre Belloni .number = n, \ 649da801ab5SAlexandre Belloni .name = "GPIO_"#n, \ 650da801ab5SAlexandre Belloni .drv_data = &jaguar2_pin_##n \ 651da801ab5SAlexandre Belloni } 652da801ab5SAlexandre Belloni 653da801ab5SAlexandre Belloni static const struct pinctrl_pin_desc jaguar2_pins[] = { 654da801ab5SAlexandre Belloni JAGUAR2_PIN(0), 655da801ab5SAlexandre Belloni JAGUAR2_PIN(1), 656da801ab5SAlexandre Belloni JAGUAR2_PIN(2), 657da801ab5SAlexandre Belloni JAGUAR2_PIN(3), 658da801ab5SAlexandre Belloni JAGUAR2_PIN(4), 659da801ab5SAlexandre Belloni JAGUAR2_PIN(5), 660da801ab5SAlexandre Belloni JAGUAR2_PIN(6), 661da801ab5SAlexandre Belloni JAGUAR2_PIN(7), 662da801ab5SAlexandre Belloni JAGUAR2_PIN(8), 663da801ab5SAlexandre Belloni JAGUAR2_PIN(9), 664da801ab5SAlexandre Belloni JAGUAR2_PIN(10), 665da801ab5SAlexandre Belloni JAGUAR2_PIN(11), 666da801ab5SAlexandre Belloni JAGUAR2_PIN(12), 667da801ab5SAlexandre Belloni JAGUAR2_PIN(13), 668da801ab5SAlexandre Belloni JAGUAR2_PIN(14), 669da801ab5SAlexandre Belloni JAGUAR2_PIN(15), 670da801ab5SAlexandre Belloni JAGUAR2_PIN(16), 671da801ab5SAlexandre Belloni JAGUAR2_PIN(17), 672da801ab5SAlexandre Belloni JAGUAR2_PIN(18), 673da801ab5SAlexandre Belloni JAGUAR2_PIN(19), 674da801ab5SAlexandre Belloni JAGUAR2_PIN(20), 675da801ab5SAlexandre Belloni JAGUAR2_PIN(21), 676da801ab5SAlexandre Belloni JAGUAR2_PIN(22), 677da801ab5SAlexandre Belloni JAGUAR2_PIN(23), 678da801ab5SAlexandre Belloni JAGUAR2_PIN(24), 679da801ab5SAlexandre Belloni JAGUAR2_PIN(25), 680da801ab5SAlexandre Belloni JAGUAR2_PIN(26), 681da801ab5SAlexandre Belloni JAGUAR2_PIN(27), 682da801ab5SAlexandre Belloni JAGUAR2_PIN(28), 683da801ab5SAlexandre Belloni JAGUAR2_PIN(29), 684da801ab5SAlexandre Belloni JAGUAR2_PIN(30), 685da801ab5SAlexandre Belloni JAGUAR2_PIN(31), 686da801ab5SAlexandre Belloni JAGUAR2_PIN(32), 687da801ab5SAlexandre Belloni JAGUAR2_PIN(33), 688da801ab5SAlexandre Belloni JAGUAR2_PIN(34), 689da801ab5SAlexandre Belloni JAGUAR2_PIN(35), 690da801ab5SAlexandre Belloni JAGUAR2_PIN(36), 691da801ab5SAlexandre Belloni JAGUAR2_PIN(37), 692da801ab5SAlexandre Belloni JAGUAR2_PIN(38), 693da801ab5SAlexandre Belloni JAGUAR2_PIN(39), 694da801ab5SAlexandre Belloni JAGUAR2_PIN(40), 695da801ab5SAlexandre Belloni JAGUAR2_PIN(41), 696da801ab5SAlexandre Belloni JAGUAR2_PIN(42), 697da801ab5SAlexandre Belloni JAGUAR2_PIN(43), 698da801ab5SAlexandre Belloni JAGUAR2_PIN(44), 699da801ab5SAlexandre Belloni JAGUAR2_PIN(45), 700da801ab5SAlexandre Belloni JAGUAR2_PIN(46), 701da801ab5SAlexandre Belloni JAGUAR2_PIN(47), 702da801ab5SAlexandre Belloni JAGUAR2_PIN(48), 703da801ab5SAlexandre Belloni JAGUAR2_PIN(49), 704da801ab5SAlexandre Belloni JAGUAR2_PIN(50), 705da801ab5SAlexandre Belloni JAGUAR2_PIN(51), 706da801ab5SAlexandre Belloni JAGUAR2_PIN(52), 707da801ab5SAlexandre Belloni JAGUAR2_PIN(53), 708da801ab5SAlexandre Belloni JAGUAR2_PIN(54), 709da801ab5SAlexandre Belloni JAGUAR2_PIN(55), 710da801ab5SAlexandre Belloni JAGUAR2_PIN(56), 711da801ab5SAlexandre Belloni JAGUAR2_PIN(57), 712da801ab5SAlexandre Belloni JAGUAR2_PIN(58), 713da801ab5SAlexandre Belloni JAGUAR2_PIN(59), 714da801ab5SAlexandre Belloni JAGUAR2_PIN(60), 715da801ab5SAlexandre Belloni JAGUAR2_PIN(61), 716da801ab5SAlexandre Belloni JAGUAR2_PIN(62), 717da801ab5SAlexandre Belloni JAGUAR2_PIN(63), 718da801ab5SAlexandre Belloni }; 719da801ab5SAlexandre Belloni 7208fc0bfcdSHoratiu Vultur #define SERVALT_P(p, f0, f1, f2) \ 7218fc0bfcdSHoratiu Vultur static struct ocelot_pin_caps servalt_pin_##p = { \ 7228fc0bfcdSHoratiu Vultur .pin = p, \ 7238fc0bfcdSHoratiu Vultur .functions = { \ 7248fc0bfcdSHoratiu Vultur FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2 \ 7258fc0bfcdSHoratiu Vultur }, \ 7268fc0bfcdSHoratiu Vultur } 7278fc0bfcdSHoratiu Vultur 7288fc0bfcdSHoratiu Vultur SERVALT_P(0, SG0, NONE, NONE); 7298fc0bfcdSHoratiu Vultur SERVALT_P(1, SG0, NONE, NONE); 7308fc0bfcdSHoratiu Vultur SERVALT_P(2, SG0, NONE, NONE); 7318fc0bfcdSHoratiu Vultur SERVALT_P(3, SG0, NONE, NONE); 7328fc0bfcdSHoratiu Vultur SERVALT_P(4, IRQ0_IN, IRQ0_OUT, TWI_SCL_M); 7338fc0bfcdSHoratiu Vultur SERVALT_P(5, IRQ1_IN, IRQ1_OUT, TWI_SCL_M); 7348fc0bfcdSHoratiu Vultur SERVALT_P(6, UART, NONE, NONE); 7358fc0bfcdSHoratiu Vultur SERVALT_P(7, UART, NONE, NONE); 7368fc0bfcdSHoratiu Vultur SERVALT_P(8, SI, SFP, TWI_SCL_M); 7378fc0bfcdSHoratiu Vultur SERVALT_P(9, PCI_WAKE, SFP, SI); 7388fc0bfcdSHoratiu Vultur SERVALT_P(10, PTP0, SFP, TWI_SCL_M); 7398fc0bfcdSHoratiu Vultur SERVALT_P(11, PTP1, SFP, TWI_SCL_M); 7408fc0bfcdSHoratiu Vultur SERVALT_P(12, REF_CLK, SFP, TWI_SCL_M); 7418fc0bfcdSHoratiu Vultur SERVALT_P(13, REF_CLK, SFP, TWI_SCL_M); 7428fc0bfcdSHoratiu Vultur SERVALT_P(14, REF_CLK, IRQ0_OUT, SI); 7438fc0bfcdSHoratiu Vultur SERVALT_P(15, REF_CLK, IRQ1_OUT, SI); 7448fc0bfcdSHoratiu Vultur SERVALT_P(16, TACHO, SFP, SI); 7458fc0bfcdSHoratiu Vultur SERVALT_P(17, PWM, NONE, TWI_SCL_M); 7468fc0bfcdSHoratiu Vultur SERVALT_P(18, PTP2, SFP, SI); 7478fc0bfcdSHoratiu Vultur SERVALT_P(19, PTP3, SFP, SI); 7488fc0bfcdSHoratiu Vultur SERVALT_P(20, UART2, SFP, SI); 7498fc0bfcdSHoratiu Vultur SERVALT_P(21, UART2, NONE, NONE); 7508fc0bfcdSHoratiu Vultur SERVALT_P(22, MIIM, SFP, TWI2); 7518fc0bfcdSHoratiu Vultur SERVALT_P(23, MIIM, SFP, TWI2); 7528fc0bfcdSHoratiu Vultur SERVALT_P(24, TWI, NONE, NONE); 7538fc0bfcdSHoratiu Vultur SERVALT_P(25, TWI, SFP, TWI_SCL_M); 7548fc0bfcdSHoratiu Vultur SERVALT_P(26, TWI_SCL_M, SFP, SI); 7558fc0bfcdSHoratiu Vultur SERVALT_P(27, TWI_SCL_M, SFP, SI); 7568fc0bfcdSHoratiu Vultur SERVALT_P(28, TWI_SCL_M, SFP, SI); 7578fc0bfcdSHoratiu Vultur SERVALT_P(29, TWI_SCL_M, NONE, NONE); 7588fc0bfcdSHoratiu Vultur SERVALT_P(30, TWI_SCL_M, NONE, NONE); 7598fc0bfcdSHoratiu Vultur SERVALT_P(31, TWI_SCL_M, NONE, NONE); 7608fc0bfcdSHoratiu Vultur SERVALT_P(32, TWI_SCL_M, NONE, NONE); 7618fc0bfcdSHoratiu Vultur SERVALT_P(33, RCVRD_CLK, NONE, NONE); 7628fc0bfcdSHoratiu Vultur SERVALT_P(34, RCVRD_CLK, NONE, NONE); 7638fc0bfcdSHoratiu Vultur SERVALT_P(35, RCVRD_CLK, NONE, NONE); 7648fc0bfcdSHoratiu Vultur SERVALT_P(36, RCVRD_CLK, NONE, NONE); 7658fc0bfcdSHoratiu Vultur 7668fc0bfcdSHoratiu Vultur #define SERVALT_PIN(n) { \ 7678fc0bfcdSHoratiu Vultur .number = n, \ 7688fc0bfcdSHoratiu Vultur .name = "GPIO_"#n, \ 7698fc0bfcdSHoratiu Vultur .drv_data = &servalt_pin_##n \ 7708fc0bfcdSHoratiu Vultur } 7718fc0bfcdSHoratiu Vultur 7728fc0bfcdSHoratiu Vultur static const struct pinctrl_pin_desc servalt_pins[] = { 7738fc0bfcdSHoratiu Vultur SERVALT_PIN(0), 7748fc0bfcdSHoratiu Vultur SERVALT_PIN(1), 7758fc0bfcdSHoratiu Vultur SERVALT_PIN(2), 7768fc0bfcdSHoratiu Vultur SERVALT_PIN(3), 7778fc0bfcdSHoratiu Vultur SERVALT_PIN(4), 7788fc0bfcdSHoratiu Vultur SERVALT_PIN(5), 7798fc0bfcdSHoratiu Vultur SERVALT_PIN(6), 7808fc0bfcdSHoratiu Vultur SERVALT_PIN(7), 7818fc0bfcdSHoratiu Vultur SERVALT_PIN(8), 7828fc0bfcdSHoratiu Vultur SERVALT_PIN(9), 7838fc0bfcdSHoratiu Vultur SERVALT_PIN(10), 7848fc0bfcdSHoratiu Vultur SERVALT_PIN(11), 7858fc0bfcdSHoratiu Vultur SERVALT_PIN(12), 7868fc0bfcdSHoratiu Vultur SERVALT_PIN(13), 7878fc0bfcdSHoratiu Vultur SERVALT_PIN(14), 7888fc0bfcdSHoratiu Vultur SERVALT_PIN(15), 7898fc0bfcdSHoratiu Vultur SERVALT_PIN(16), 7908fc0bfcdSHoratiu Vultur SERVALT_PIN(17), 7918fc0bfcdSHoratiu Vultur SERVALT_PIN(18), 7928fc0bfcdSHoratiu Vultur SERVALT_PIN(19), 7938fc0bfcdSHoratiu Vultur SERVALT_PIN(20), 7948fc0bfcdSHoratiu Vultur SERVALT_PIN(21), 7958fc0bfcdSHoratiu Vultur SERVALT_PIN(22), 7968fc0bfcdSHoratiu Vultur SERVALT_PIN(23), 7978fc0bfcdSHoratiu Vultur SERVALT_PIN(24), 7988fc0bfcdSHoratiu Vultur SERVALT_PIN(25), 7998fc0bfcdSHoratiu Vultur SERVALT_PIN(26), 8008fc0bfcdSHoratiu Vultur SERVALT_PIN(27), 8018fc0bfcdSHoratiu Vultur SERVALT_PIN(28), 8028fc0bfcdSHoratiu Vultur SERVALT_PIN(29), 8038fc0bfcdSHoratiu Vultur SERVALT_PIN(30), 8048fc0bfcdSHoratiu Vultur SERVALT_PIN(31), 8058fc0bfcdSHoratiu Vultur SERVALT_PIN(32), 8068fc0bfcdSHoratiu Vultur SERVALT_PIN(33), 8078fc0bfcdSHoratiu Vultur SERVALT_PIN(34), 8088fc0bfcdSHoratiu Vultur SERVALT_PIN(35), 8098fc0bfcdSHoratiu Vultur SERVALT_PIN(36), 8108fc0bfcdSHoratiu Vultur }; 8118fc0bfcdSHoratiu Vultur 812f8a74760SLars Povlsen #define SPARX5_P(p, f0, f1, f2) \ 813f8a74760SLars Povlsen static struct ocelot_pin_caps sparx5_pin_##p = { \ 814f8a74760SLars Povlsen .pin = p, \ 815f8a74760SLars Povlsen .functions = { \ 816f8a74760SLars Povlsen FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2 \ 817f8a74760SLars Povlsen }, \ 818f8a74760SLars Povlsen } 819f8a74760SLars Povlsen 820f8a74760SLars Povlsen SPARX5_P(0, SG0, PLL_STAT, NONE); 821f8a74760SLars Povlsen SPARX5_P(1, SG0, NONE, NONE); 822f8a74760SLars Povlsen SPARX5_P(2, SG0, NONE, NONE); 823f8a74760SLars Povlsen SPARX5_P(3, SG0, NONE, NONE); 824f8a74760SLars Povlsen SPARX5_P(4, SG1, NONE, NONE); 825f8a74760SLars Povlsen SPARX5_P(5, SG1, NONE, NONE); 826f8a74760SLars Povlsen SPARX5_P(6, IRQ0_IN, IRQ0_OUT, SFP); 827f8a74760SLars Povlsen SPARX5_P(7, IRQ1_IN, IRQ1_OUT, SFP); 828f8a74760SLars Povlsen SPARX5_P(8, PTP0, NONE, SFP); 829f8a74760SLars Povlsen SPARX5_P(9, PTP1, SFP, TWI_SCL_M); 830f8a74760SLars Povlsen SPARX5_P(10, UART, NONE, NONE); 831f8a74760SLars Povlsen SPARX5_P(11, UART, NONE, NONE); 832f8a74760SLars Povlsen SPARX5_P(12, SG1, NONE, NONE); 833f8a74760SLars Povlsen SPARX5_P(13, SG1, NONE, NONE); 834f8a74760SLars Povlsen SPARX5_P(14, TWI, TWI_SCL_M, NONE); 835f8a74760SLars Povlsen SPARX5_P(15, TWI, NONE, NONE); 836f8a74760SLars Povlsen SPARX5_P(16, SI, TWI_SCL_M, SFP); 837f8a74760SLars Povlsen SPARX5_P(17, SI, TWI_SCL_M, SFP); 838f8a74760SLars Povlsen SPARX5_P(18, SI, TWI_SCL_M, SFP); 839f8a74760SLars Povlsen SPARX5_P(19, PCI_WAKE, TWI_SCL_M, SFP); 840f8a74760SLars Povlsen SPARX5_P(20, IRQ0_OUT, TWI_SCL_M, SFP); 841f8a74760SLars Povlsen SPARX5_P(21, IRQ1_OUT, TACHO, SFP); 842f8a74760SLars Povlsen SPARX5_P(22, TACHO, IRQ0_OUT, TWI_SCL_M); 843f8a74760SLars Povlsen SPARX5_P(23, PWM, UART3, TWI_SCL_M); 844f8a74760SLars Povlsen SPARX5_P(24, PTP2, UART3, TWI_SCL_M); 845f8a74760SLars Povlsen SPARX5_P(25, PTP3, SI, TWI_SCL_M); 846f8a74760SLars Povlsen SPARX5_P(26, UART2, SI, TWI_SCL_M); 847f8a74760SLars Povlsen SPARX5_P(27, UART2, SI, TWI_SCL_M); 848f8a74760SLars Povlsen SPARX5_P(28, TWI2, SI, SFP); 849f8a74760SLars Povlsen SPARX5_P(29, TWI2, SI, SFP); 850f8a74760SLars Povlsen SPARX5_P(30, SG2, SI, PWM); 851f8a74760SLars Povlsen SPARX5_P(31, SG2, SI, TWI_SCL_M); 852f8a74760SLars Povlsen SPARX5_P(32, SG2, SI, TWI_SCL_M); 853f8a74760SLars Povlsen SPARX5_P(33, SG2, SI, SFP); 854f8a74760SLars Povlsen SPARX5_P(34, NONE, TWI_SCL_M, EMMC); 855f8a74760SLars Povlsen SPARX5_P(35, SFP, TWI_SCL_M, EMMC); 856f8a74760SLars Povlsen SPARX5_P(36, SFP, TWI_SCL_M, EMMC); 857f8a74760SLars Povlsen SPARX5_P(37, SFP, NONE, EMMC); 858f8a74760SLars Povlsen SPARX5_P(38, NONE, TWI_SCL_M, EMMC); 859f8a74760SLars Povlsen SPARX5_P(39, SI2, TWI_SCL_M, EMMC); 860f8a74760SLars Povlsen SPARX5_P(40, SI2, TWI_SCL_M, EMMC); 861f8a74760SLars Povlsen SPARX5_P(41, SI2, TWI_SCL_M, EMMC); 862f8a74760SLars Povlsen SPARX5_P(42, SI2, TWI_SCL_M, EMMC); 863f8a74760SLars Povlsen SPARX5_P(43, SI2, TWI_SCL_M, EMMC); 864f8a74760SLars Povlsen SPARX5_P(44, SI, SFP, EMMC); 865f8a74760SLars Povlsen SPARX5_P(45, SI, SFP, EMMC); 866f8a74760SLars Povlsen SPARX5_P(46, NONE, SFP, EMMC); 867f8a74760SLars Povlsen SPARX5_P(47, NONE, SFP, EMMC); 868f8a74760SLars Povlsen SPARX5_P(48, TWI3, SI, SFP); 869f8a74760SLars Povlsen SPARX5_P(49, TWI3, NONE, SFP); 870f8a74760SLars Povlsen SPARX5_P(50, SFP, NONE, TWI_SCL_M); 871f8a74760SLars Povlsen SPARX5_P(51, SFP, SI, TWI_SCL_M); 872f8a74760SLars Povlsen SPARX5_P(52, SFP, MIIM, TWI_SCL_M); 873f8a74760SLars Povlsen SPARX5_P(53, SFP, MIIM, TWI_SCL_M); 874f8a74760SLars Povlsen SPARX5_P(54, SFP, PTP2, TWI_SCL_M); 875f8a74760SLars Povlsen SPARX5_P(55, SFP, PTP3, PCI_WAKE); 876f8a74760SLars Povlsen SPARX5_P(56, MIIM, SFP, TWI_SCL_M); 877f8a74760SLars Povlsen SPARX5_P(57, MIIM, SFP, TWI_SCL_M); 878f8a74760SLars Povlsen SPARX5_P(58, MIIM, SFP, TWI_SCL_M); 879f8a74760SLars Povlsen SPARX5_P(59, MIIM, SFP, NONE); 880f8a74760SLars Povlsen SPARX5_P(60, RECO_CLK, NONE, NONE); 881f8a74760SLars Povlsen SPARX5_P(61, RECO_CLK, NONE, NONE); 882f8a74760SLars Povlsen SPARX5_P(62, RECO_CLK, PLL_STAT, NONE); 883f8a74760SLars Povlsen SPARX5_P(63, RECO_CLK, NONE, NONE); 884f8a74760SLars Povlsen 885f8a74760SLars Povlsen #define SPARX5_PIN(n) { \ 886f8a74760SLars Povlsen .number = n, \ 887f8a74760SLars Povlsen .name = "GPIO_"#n, \ 888f8a74760SLars Povlsen .drv_data = &sparx5_pin_##n \ 889f8a74760SLars Povlsen } 890f8a74760SLars Povlsen 891f8a74760SLars Povlsen static const struct pinctrl_pin_desc sparx5_pins[] = { 892f8a74760SLars Povlsen SPARX5_PIN(0), 893f8a74760SLars Povlsen SPARX5_PIN(1), 894f8a74760SLars Povlsen SPARX5_PIN(2), 895f8a74760SLars Povlsen SPARX5_PIN(3), 896f8a74760SLars Povlsen SPARX5_PIN(4), 897f8a74760SLars Povlsen SPARX5_PIN(5), 898f8a74760SLars Povlsen SPARX5_PIN(6), 899f8a74760SLars Povlsen SPARX5_PIN(7), 900f8a74760SLars Povlsen SPARX5_PIN(8), 901f8a74760SLars Povlsen SPARX5_PIN(9), 902f8a74760SLars Povlsen SPARX5_PIN(10), 903f8a74760SLars Povlsen SPARX5_PIN(11), 904f8a74760SLars Povlsen SPARX5_PIN(12), 905f8a74760SLars Povlsen SPARX5_PIN(13), 906f8a74760SLars Povlsen SPARX5_PIN(14), 907f8a74760SLars Povlsen SPARX5_PIN(15), 908f8a74760SLars Povlsen SPARX5_PIN(16), 909f8a74760SLars Povlsen SPARX5_PIN(17), 910f8a74760SLars Povlsen SPARX5_PIN(18), 911f8a74760SLars Povlsen SPARX5_PIN(19), 912f8a74760SLars Povlsen SPARX5_PIN(20), 913f8a74760SLars Povlsen SPARX5_PIN(21), 914f8a74760SLars Povlsen SPARX5_PIN(22), 915f8a74760SLars Povlsen SPARX5_PIN(23), 916f8a74760SLars Povlsen SPARX5_PIN(24), 917f8a74760SLars Povlsen SPARX5_PIN(25), 918f8a74760SLars Povlsen SPARX5_PIN(26), 919f8a74760SLars Povlsen SPARX5_PIN(27), 920f8a74760SLars Povlsen SPARX5_PIN(28), 921f8a74760SLars Povlsen SPARX5_PIN(29), 922f8a74760SLars Povlsen SPARX5_PIN(30), 923f8a74760SLars Povlsen SPARX5_PIN(31), 924f8a74760SLars Povlsen SPARX5_PIN(32), 925f8a74760SLars Povlsen SPARX5_PIN(33), 926f8a74760SLars Povlsen SPARX5_PIN(34), 927f8a74760SLars Povlsen SPARX5_PIN(35), 928f8a74760SLars Povlsen SPARX5_PIN(36), 929f8a74760SLars Povlsen SPARX5_PIN(37), 930f8a74760SLars Povlsen SPARX5_PIN(38), 931f8a74760SLars Povlsen SPARX5_PIN(39), 932f8a74760SLars Povlsen SPARX5_PIN(40), 933f8a74760SLars Povlsen SPARX5_PIN(41), 934f8a74760SLars Povlsen SPARX5_PIN(42), 935f8a74760SLars Povlsen SPARX5_PIN(43), 936f8a74760SLars Povlsen SPARX5_PIN(44), 937f8a74760SLars Povlsen SPARX5_PIN(45), 938f8a74760SLars Povlsen SPARX5_PIN(46), 939f8a74760SLars Povlsen SPARX5_PIN(47), 940f8a74760SLars Povlsen SPARX5_PIN(48), 941f8a74760SLars Povlsen SPARX5_PIN(49), 942f8a74760SLars Povlsen SPARX5_PIN(50), 943f8a74760SLars Povlsen SPARX5_PIN(51), 944f8a74760SLars Povlsen SPARX5_PIN(52), 945f8a74760SLars Povlsen SPARX5_PIN(53), 946f8a74760SLars Povlsen SPARX5_PIN(54), 947f8a74760SLars Povlsen SPARX5_PIN(55), 948f8a74760SLars Povlsen SPARX5_PIN(56), 949f8a74760SLars Povlsen SPARX5_PIN(57), 950f8a74760SLars Povlsen SPARX5_PIN(58), 951f8a74760SLars Povlsen SPARX5_PIN(59), 952f8a74760SLars Povlsen SPARX5_PIN(60), 953f8a74760SLars Povlsen SPARX5_PIN(61), 954f8a74760SLars Povlsen SPARX5_PIN(62), 955f8a74760SLars Povlsen SPARX5_PIN(63), 956f8a74760SLars Povlsen }; 957f8a74760SLars Povlsen 958531d6ab3SKavyasree Kotagiri #define LAN966X_P(p, f0, f1, f2, f3, f4, f5, f6, f7) \ 959531d6ab3SKavyasree Kotagiri static struct ocelot_pin_caps lan966x_pin_##p = { \ 960531d6ab3SKavyasree Kotagiri .pin = p, \ 961531d6ab3SKavyasree Kotagiri .functions = { \ 962531d6ab3SKavyasree Kotagiri FUNC_##f0, FUNC_##f1, FUNC_##f2, \ 963531d6ab3SKavyasree Kotagiri FUNC_##f3 \ 964531d6ab3SKavyasree Kotagiri }, \ 965531d6ab3SKavyasree Kotagiri .a_functions = { \ 966531d6ab3SKavyasree Kotagiri FUNC_##f4, FUNC_##f5, FUNC_##f6, \ 967531d6ab3SKavyasree Kotagiri FUNC_##f7 \ 968531d6ab3SKavyasree Kotagiri }, \ 969531d6ab3SKavyasree Kotagiri } 970531d6ab3SKavyasree Kotagiri 971531d6ab3SKavyasree Kotagiri /* Pinmuxing table taken from data sheet */ 972531d6ab3SKavyasree Kotagiri /* Pin FUNC0 FUNC1 FUNC2 FUNC3 FUNC4 FUNC5 FUNC6 FUNC7 */ 973531d6ab3SKavyasree Kotagiri LAN966X_P(0, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 974531d6ab3SKavyasree Kotagiri LAN966X_P(1, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 975531d6ab3SKavyasree Kotagiri LAN966X_P(2, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 976531d6ab3SKavyasree Kotagiri LAN966X_P(3, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 977531d6ab3SKavyasree Kotagiri LAN966X_P(4, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 978531d6ab3SKavyasree Kotagiri LAN966X_P(5, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 979531d6ab3SKavyasree Kotagiri LAN966X_P(6, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 980531d6ab3SKavyasree Kotagiri LAN966X_P(7, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 981531d6ab3SKavyasree Kotagiri LAN966X_P(8, GPIO, FC0_a, USB_H_b, NONE, USB_S_b, NONE, NONE, R); 982531d6ab3SKavyasree Kotagiri LAN966X_P(9, GPIO, FC0_a, USB_H_b, NONE, NONE, NONE, NONE, R); 983531d6ab3SKavyasree Kotagiri LAN966X_P(10, GPIO, FC0_a, NONE, NONE, NONE, NONE, NONE, R); 984531d6ab3SKavyasree Kotagiri LAN966X_P(11, GPIO, FC1_a, NONE, NONE, NONE, NONE, NONE, R); 985531d6ab3SKavyasree Kotagiri LAN966X_P(12, GPIO, FC1_a, NONE, NONE, NONE, NONE, NONE, R); 986531d6ab3SKavyasree Kotagiri LAN966X_P(13, GPIO, FC1_a, NONE, NONE, NONE, NONE, NONE, R); 987531d6ab3SKavyasree Kotagiri LAN966X_P(14, GPIO, FC2_a, NONE, NONE, NONE, NONE, NONE, R); 988531d6ab3SKavyasree Kotagiri LAN966X_P(15, GPIO, FC2_a, NONE, NONE, NONE, NONE, NONE, R); 989531d6ab3SKavyasree Kotagiri LAN966X_P(16, GPIO, FC2_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, IRQ_OUT_c, R); 990531d6ab3SKavyasree Kotagiri LAN966X_P(17, GPIO, FC3_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, IRQ_OUT_c, R); 991531d6ab3SKavyasree Kotagiri LAN966X_P(18, GPIO, FC3_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, IRQ_OUT_c, R); 992531d6ab3SKavyasree Kotagiri LAN966X_P(19, GPIO, FC3_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, IRQ_OUT_c, R); 993531d6ab3SKavyasree Kotagiri LAN966X_P(20, GPIO, FC4_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, NONE, R); 994531d6ab3SKavyasree Kotagiri LAN966X_P(21, GPIO, FC4_a, NONE, NONE, OB_TRG_a, NONE, NONE, R); 995531d6ab3SKavyasree Kotagiri LAN966X_P(22, GPIO, FC4_a, NONE, NONE, OB_TRG_a, NONE, NONE, R); 996531d6ab3SKavyasree Kotagiri LAN966X_P(23, GPIO, NONE, NONE, NONE, OB_TRG_a, NONE, NONE, R); 997531d6ab3SKavyasree Kotagiri LAN966X_P(24, GPIO, FC0_b, IB_TRG_a, USB_H_c, OB_TRG_a, IRQ_IN_c, TACHO_a, R); 998531d6ab3SKavyasree Kotagiri LAN966X_P(25, GPIO, FC0_b, IB_TRG_a, USB_H_c, OB_TRG_a, IRQ_OUT_c, SFP_SD, R); 999531d6ab3SKavyasree Kotagiri LAN966X_P(26, GPIO, FC0_b, IB_TRG_a, USB_S_c, OB_TRG_a, CAN0_a, SFP_SD, R); 1000e97e36cdSMichael Walle LAN966X_P(27, GPIO, NONE, NONE, NONE, OB_TRG_a, CAN0_a, PWM_a, R); 1001531d6ab3SKavyasree Kotagiri LAN966X_P(28, GPIO, MIIM_a, NONE, NONE, OB_TRG_a, IRQ_OUT_c, SFP_SD, R); 1002531d6ab3SKavyasree Kotagiri LAN966X_P(29, GPIO, MIIM_a, NONE, NONE, OB_TRG_a, NONE, NONE, R); 1003bf3e7f49SMichael Walle LAN966X_P(30, GPIO, FC3_c, CAN1, CLKMON, OB_TRG, RECO_b, NONE, R); 1004bf3e7f49SMichael Walle LAN966X_P(31, GPIO, FC3_c, CAN1, CLKMON, OB_TRG, RECO_b, NONE, R); 1005531d6ab3SKavyasree Kotagiri LAN966X_P(32, GPIO, FC3_c, NONE, SGPIO_a, NONE, MIIM_Sa, NONE, R); 1006531d6ab3SKavyasree Kotagiri LAN966X_P(33, GPIO, FC1_b, NONE, SGPIO_a, NONE, MIIM_Sa, MIIM_b, R); 1007531d6ab3SKavyasree Kotagiri LAN966X_P(34, GPIO, FC1_b, NONE, SGPIO_a, NONE, MIIM_Sa, MIIM_b, R); 1008d3683eebSHoratiu Vultur LAN966X_P(35, GPIO, FC1_b, PTPSYNC_0, SGPIO_a, CAN0_b, NONE, NONE, R); 1009531d6ab3SKavyasree Kotagiri LAN966X_P(36, GPIO, NONE, PTPSYNC_1, NONE, CAN0_b, NONE, NONE, R); 1010531d6ab3SKavyasree Kotagiri LAN966X_P(37, GPIO, FC_SHRD0, PTPSYNC_2, TWI_SLC_GATE_AD, NONE, NONE, NONE, R); 1011531d6ab3SKavyasree Kotagiri LAN966X_P(38, GPIO, NONE, PTPSYNC_3, NONE, NONE, NONE, NONE, R); 1012531d6ab3SKavyasree Kotagiri LAN966X_P(39, GPIO, NONE, PTPSYNC_4, NONE, NONE, NONE, NONE, R); 1013531d6ab3SKavyasree Kotagiri LAN966X_P(40, GPIO, FC_SHRD1, PTPSYNC_5, NONE, NONE, NONE, NONE, R); 1014531d6ab3SKavyasree Kotagiri LAN966X_P(41, GPIO, FC_SHRD2, PTPSYNC_6, TWI_SLC_GATE_AD, NONE, NONE, NONE, R); 1015531d6ab3SKavyasree Kotagiri LAN966X_P(42, GPIO, FC_SHRD3, PTPSYNC_7, TWI_SLC_GATE_AD, NONE, NONE, NONE, R); 1016531d6ab3SKavyasree Kotagiri LAN966X_P(43, GPIO, FC2_b, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, RECO_a, IRQ_IN_a, R); 1017531d6ab3SKavyasree Kotagiri LAN966X_P(44, GPIO, FC2_b, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, RECO_a, IRQ_IN_a, R); 1018531d6ab3SKavyasree Kotagiri LAN966X_P(45, GPIO, FC2_b, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, NONE, IRQ_IN_a, R); 1019531d6ab3SKavyasree Kotagiri LAN966X_P(46, GPIO, FC1_c, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, FC_SHRD4, IRQ_IN_a, R); 1020531d6ab3SKavyasree Kotagiri LAN966X_P(47, GPIO, FC1_c, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, FC_SHRD5, IRQ_IN_a, R); 1021531d6ab3SKavyasree Kotagiri LAN966X_P(48, GPIO, FC1_c, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, FC_SHRD6, IRQ_IN_a, R); 1022531d6ab3SKavyasree Kotagiri LAN966X_P(49, GPIO, FC_SHRD7, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, TWI_SLC_GATE, IRQ_IN_a, R); 1023531d6ab3SKavyasree Kotagiri LAN966X_P(50, GPIO, FC_SHRD16, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, TWI_SLC_GATE, NONE, R); 1024e97e36cdSMichael Walle LAN966X_P(51, GPIO, FC3_b, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, PWM_b, IRQ_IN_b, R); 1025531d6ab3SKavyasree Kotagiri LAN966X_P(52, GPIO, FC3_b, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, TACHO_b, IRQ_IN_b, R); 1026531d6ab3SKavyasree Kotagiri LAN966X_P(53, GPIO, FC3_b, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, NONE, IRQ_IN_b, R); 1027531d6ab3SKavyasree Kotagiri LAN966X_P(54, GPIO, FC_SHRD8, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, TWI_SLC_GATE, IRQ_IN_b, R); 1028531d6ab3SKavyasree Kotagiri LAN966X_P(55, GPIO, FC_SHRD9, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, TWI_SLC_GATE, IRQ_IN_b, R); 1029531d6ab3SKavyasree Kotagiri LAN966X_P(56, GPIO, FC4_b, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, FC_SHRD10, IRQ_IN_b, R); 1030531d6ab3SKavyasree Kotagiri LAN966X_P(57, GPIO, FC4_b, TWI_SLC_GATE, IB_TRG_c, IRQ_OUT_b, FC_SHRD11, IRQ_IN_b, R); 1031531d6ab3SKavyasree Kotagiri LAN966X_P(58, GPIO, FC4_b, TWI_SLC_GATE, IB_TRG_c, IRQ_OUT_b, FC_SHRD12, IRQ_IN_b, R); 1032531d6ab3SKavyasree Kotagiri LAN966X_P(59, GPIO, QSPI1, MIIM_c, NONE, NONE, MIIM_Sb, NONE, R); 1033531d6ab3SKavyasree Kotagiri LAN966X_P(60, GPIO, QSPI1, MIIM_c, NONE, NONE, MIIM_Sb, NONE, R); 1034531d6ab3SKavyasree Kotagiri LAN966X_P(61, GPIO, QSPI1, NONE, SGPIO_b, FC0_c, MIIM_Sb, NONE, R); 1035531d6ab3SKavyasree Kotagiri LAN966X_P(62, GPIO, QSPI1, FC_SHRD13, SGPIO_b, FC0_c, TWI_SLC_GATE, SFP_SD, R); 1036531d6ab3SKavyasree Kotagiri LAN966X_P(63, GPIO, QSPI1, FC_SHRD14, SGPIO_b, FC0_c, TWI_SLC_GATE, SFP_SD, R); 1037531d6ab3SKavyasree Kotagiri LAN966X_P(64, GPIO, QSPI1, FC4_c, SGPIO_b, FC_SHRD15, TWI_SLC_GATE, SFP_SD, R); 1038531d6ab3SKavyasree Kotagiri LAN966X_P(65, GPIO, USB_H_a, FC4_c, NONE, IRQ_OUT_c, TWI_SLC_GATE_AD, NONE, R); 1039531d6ab3SKavyasree Kotagiri LAN966X_P(66, GPIO, USB_H_a, FC4_c, USB_S_a, IRQ_OUT_c, IRQ_IN_c, NONE, R); 1040531d6ab3SKavyasree Kotagiri LAN966X_P(67, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R); 1041531d6ab3SKavyasree Kotagiri LAN966X_P(68, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R); 1042531d6ab3SKavyasree Kotagiri LAN966X_P(69, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R); 1043531d6ab3SKavyasree Kotagiri LAN966X_P(70, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R); 1044531d6ab3SKavyasree Kotagiri LAN966X_P(71, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R); 1045531d6ab3SKavyasree Kotagiri LAN966X_P(72, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R); 1046531d6ab3SKavyasree Kotagiri LAN966X_P(73, GPIO, EMMC, NONE, NONE, SD, NONE, NONE, R); 1047531d6ab3SKavyasree Kotagiri LAN966X_P(74, GPIO, EMMC, NONE, FC_SHRD17, SD, TWI_SLC_GATE, NONE, R); 1048531d6ab3SKavyasree Kotagiri LAN966X_P(75, GPIO, EMMC, NONE, FC_SHRD18, SD, TWI_SLC_GATE, NONE, R); 1049531d6ab3SKavyasree Kotagiri LAN966X_P(76, GPIO, EMMC, NONE, FC_SHRD19, SD, TWI_SLC_GATE, NONE, R); 1050531d6ab3SKavyasree Kotagiri LAN966X_P(77, GPIO, EMMC_SD, NONE, FC_SHRD20, NONE, TWI_SLC_GATE, NONE, R); 1051531d6ab3SKavyasree Kotagiri 1052531d6ab3SKavyasree Kotagiri #define LAN966X_PIN(n) { \ 1053531d6ab3SKavyasree Kotagiri .number = n, \ 1054531d6ab3SKavyasree Kotagiri .name = "GPIO_"#n, \ 1055531d6ab3SKavyasree Kotagiri .drv_data = &lan966x_pin_##n \ 1056531d6ab3SKavyasree Kotagiri } 1057531d6ab3SKavyasree Kotagiri 1058531d6ab3SKavyasree Kotagiri static const struct pinctrl_pin_desc lan966x_pins[] = { 1059531d6ab3SKavyasree Kotagiri LAN966X_PIN(0), 1060531d6ab3SKavyasree Kotagiri LAN966X_PIN(1), 1061531d6ab3SKavyasree Kotagiri LAN966X_PIN(2), 1062531d6ab3SKavyasree Kotagiri LAN966X_PIN(3), 1063531d6ab3SKavyasree Kotagiri LAN966X_PIN(4), 1064531d6ab3SKavyasree Kotagiri LAN966X_PIN(5), 1065531d6ab3SKavyasree Kotagiri LAN966X_PIN(6), 1066531d6ab3SKavyasree Kotagiri LAN966X_PIN(7), 1067531d6ab3SKavyasree Kotagiri LAN966X_PIN(8), 1068531d6ab3SKavyasree Kotagiri LAN966X_PIN(9), 1069531d6ab3SKavyasree Kotagiri LAN966X_PIN(10), 1070531d6ab3SKavyasree Kotagiri LAN966X_PIN(11), 1071531d6ab3SKavyasree Kotagiri LAN966X_PIN(12), 1072531d6ab3SKavyasree Kotagiri LAN966X_PIN(13), 1073531d6ab3SKavyasree Kotagiri LAN966X_PIN(14), 1074531d6ab3SKavyasree Kotagiri LAN966X_PIN(15), 1075531d6ab3SKavyasree Kotagiri LAN966X_PIN(16), 1076531d6ab3SKavyasree Kotagiri LAN966X_PIN(17), 1077531d6ab3SKavyasree Kotagiri LAN966X_PIN(18), 1078531d6ab3SKavyasree Kotagiri LAN966X_PIN(19), 1079531d6ab3SKavyasree Kotagiri LAN966X_PIN(20), 1080531d6ab3SKavyasree Kotagiri LAN966X_PIN(21), 1081531d6ab3SKavyasree Kotagiri LAN966X_PIN(22), 1082531d6ab3SKavyasree Kotagiri LAN966X_PIN(23), 1083531d6ab3SKavyasree Kotagiri LAN966X_PIN(24), 1084531d6ab3SKavyasree Kotagiri LAN966X_PIN(25), 1085531d6ab3SKavyasree Kotagiri LAN966X_PIN(26), 1086531d6ab3SKavyasree Kotagiri LAN966X_PIN(27), 1087531d6ab3SKavyasree Kotagiri LAN966X_PIN(28), 1088531d6ab3SKavyasree Kotagiri LAN966X_PIN(29), 1089531d6ab3SKavyasree Kotagiri LAN966X_PIN(30), 1090531d6ab3SKavyasree Kotagiri LAN966X_PIN(31), 1091531d6ab3SKavyasree Kotagiri LAN966X_PIN(32), 1092531d6ab3SKavyasree Kotagiri LAN966X_PIN(33), 1093531d6ab3SKavyasree Kotagiri LAN966X_PIN(34), 1094531d6ab3SKavyasree Kotagiri LAN966X_PIN(35), 1095531d6ab3SKavyasree Kotagiri LAN966X_PIN(36), 1096531d6ab3SKavyasree Kotagiri LAN966X_PIN(37), 1097531d6ab3SKavyasree Kotagiri LAN966X_PIN(38), 1098531d6ab3SKavyasree Kotagiri LAN966X_PIN(39), 1099531d6ab3SKavyasree Kotagiri LAN966X_PIN(40), 1100531d6ab3SKavyasree Kotagiri LAN966X_PIN(41), 1101531d6ab3SKavyasree Kotagiri LAN966X_PIN(42), 1102531d6ab3SKavyasree Kotagiri LAN966X_PIN(43), 1103531d6ab3SKavyasree Kotagiri LAN966X_PIN(44), 1104531d6ab3SKavyasree Kotagiri LAN966X_PIN(45), 1105531d6ab3SKavyasree Kotagiri LAN966X_PIN(46), 1106531d6ab3SKavyasree Kotagiri LAN966X_PIN(47), 1107531d6ab3SKavyasree Kotagiri LAN966X_PIN(48), 1108531d6ab3SKavyasree Kotagiri LAN966X_PIN(49), 1109531d6ab3SKavyasree Kotagiri LAN966X_PIN(50), 1110531d6ab3SKavyasree Kotagiri LAN966X_PIN(51), 1111531d6ab3SKavyasree Kotagiri LAN966X_PIN(52), 1112531d6ab3SKavyasree Kotagiri LAN966X_PIN(53), 1113531d6ab3SKavyasree Kotagiri LAN966X_PIN(54), 1114531d6ab3SKavyasree Kotagiri LAN966X_PIN(55), 1115531d6ab3SKavyasree Kotagiri LAN966X_PIN(56), 1116531d6ab3SKavyasree Kotagiri LAN966X_PIN(57), 1117531d6ab3SKavyasree Kotagiri LAN966X_PIN(58), 1118531d6ab3SKavyasree Kotagiri LAN966X_PIN(59), 1119531d6ab3SKavyasree Kotagiri LAN966X_PIN(60), 1120531d6ab3SKavyasree Kotagiri LAN966X_PIN(61), 1121531d6ab3SKavyasree Kotagiri LAN966X_PIN(62), 1122531d6ab3SKavyasree Kotagiri LAN966X_PIN(63), 1123531d6ab3SKavyasree Kotagiri LAN966X_PIN(64), 1124531d6ab3SKavyasree Kotagiri LAN966X_PIN(65), 1125531d6ab3SKavyasree Kotagiri LAN966X_PIN(66), 1126531d6ab3SKavyasree Kotagiri LAN966X_PIN(67), 1127531d6ab3SKavyasree Kotagiri LAN966X_PIN(68), 1128531d6ab3SKavyasree Kotagiri LAN966X_PIN(69), 1129531d6ab3SKavyasree Kotagiri LAN966X_PIN(70), 1130531d6ab3SKavyasree Kotagiri LAN966X_PIN(71), 1131531d6ab3SKavyasree Kotagiri LAN966X_PIN(72), 1132531d6ab3SKavyasree Kotagiri LAN966X_PIN(73), 1133531d6ab3SKavyasree Kotagiri LAN966X_PIN(74), 1134531d6ab3SKavyasree Kotagiri LAN966X_PIN(75), 1135531d6ab3SKavyasree Kotagiri LAN966X_PIN(76), 1136531d6ab3SKavyasree Kotagiri LAN966X_PIN(77), 1137531d6ab3SKavyasree Kotagiri }; 1138531d6ab3SKavyasree Kotagiri 1139ce8dc094SAlexandre Belloni static int ocelot_get_functions_count(struct pinctrl_dev *pctldev) 1140ce8dc094SAlexandre Belloni { 1141ce8dc094SAlexandre Belloni return ARRAY_SIZE(ocelot_function_names); 1142ce8dc094SAlexandre Belloni } 1143ce8dc094SAlexandre Belloni 1144ce8dc094SAlexandre Belloni static const char *ocelot_get_function_name(struct pinctrl_dev *pctldev, 1145ce8dc094SAlexandre Belloni unsigned int function) 1146ce8dc094SAlexandre Belloni { 1147ce8dc094SAlexandre Belloni return ocelot_function_names[function]; 1148ce8dc094SAlexandre Belloni } 1149ce8dc094SAlexandre Belloni 1150ce8dc094SAlexandre Belloni static int ocelot_get_function_groups(struct pinctrl_dev *pctldev, 1151ce8dc094SAlexandre Belloni unsigned int function, 1152ce8dc094SAlexandre Belloni const char *const **groups, 1153ce8dc094SAlexandre Belloni unsigned *const num_groups) 1154ce8dc094SAlexandre Belloni { 1155ce8dc094SAlexandre Belloni struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1156ce8dc094SAlexandre Belloni 1157ce8dc094SAlexandre Belloni *groups = info->func[function].groups; 1158ce8dc094SAlexandre Belloni *num_groups = info->func[function].ngroups; 1159ce8dc094SAlexandre Belloni 1160ce8dc094SAlexandre Belloni return 0; 1161ce8dc094SAlexandre Belloni } 1162ce8dc094SAlexandre Belloni 1163da801ab5SAlexandre Belloni static int ocelot_pin_function_idx(struct ocelot_pinctrl *info, 1164da801ab5SAlexandre Belloni unsigned int pin, unsigned int function) 1165ce8dc094SAlexandre Belloni { 1166da801ab5SAlexandre Belloni struct ocelot_pin_caps *p = info->desc->pins[pin].drv_data; 1167ce8dc094SAlexandre Belloni int i; 1168ce8dc094SAlexandre Belloni 1169ce8dc094SAlexandre Belloni for (i = 0; i < OCELOT_FUNC_PER_PIN; i++) { 1170ce8dc094SAlexandre Belloni if (function == p->functions[i]) 1171ce8dc094SAlexandre Belloni return i; 1172531d6ab3SKavyasree Kotagiri 1173531d6ab3SKavyasree Kotagiri if (function == p->a_functions[i]) 1174531d6ab3SKavyasree Kotagiri return i + OCELOT_FUNC_PER_PIN; 1175ce8dc094SAlexandre Belloni } 1176ce8dc094SAlexandre Belloni 1177ce8dc094SAlexandre Belloni return -1; 1178ce8dc094SAlexandre Belloni } 1179ce8dc094SAlexandre Belloni 11804b36082eSAlexandre Belloni #define REG_ALT(msb, info, p) (OCELOT_GPIO_ALT0 * (info)->stride + 4 * ((msb) + ((info)->stride * ((p) / 32)))) 1181da801ab5SAlexandre Belloni 1182ce8dc094SAlexandre Belloni static int ocelot_pinmux_set_mux(struct pinctrl_dev *pctldev, 1183ce8dc094SAlexandre Belloni unsigned int selector, unsigned int group) 1184ce8dc094SAlexandre Belloni { 1185ce8dc094SAlexandre Belloni struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1186da801ab5SAlexandre Belloni struct ocelot_pin_caps *pin = info->desc->pins[group].drv_data; 1187da801ab5SAlexandre Belloni unsigned int p = pin->pin % 32; 1188ce8dc094SAlexandre Belloni int f; 1189ce8dc094SAlexandre Belloni 1190da801ab5SAlexandre Belloni f = ocelot_pin_function_idx(info, group, selector); 1191ce8dc094SAlexandre Belloni if (f < 0) 1192ce8dc094SAlexandre Belloni return -EINVAL; 1193ce8dc094SAlexandre Belloni 1194ce8dc094SAlexandre Belloni /* 1195ce8dc094SAlexandre Belloni * f is encoded on two bits. 11964b36082eSAlexandre Belloni * bit 0 of f goes in BIT(pin) of ALT[0], bit 1 of f goes in BIT(pin) of 11974b36082eSAlexandre Belloni * ALT[1] 1198ce8dc094SAlexandre Belloni * This is racy because both registers can't be updated at the same time 1199ce8dc094SAlexandre Belloni * but it doesn't matter much for now. 1200f8a74760SLars Povlsen * Note: ALT0/ALT1 are organized specially for 64 gpio targets 1201ce8dc094SAlexandre Belloni */ 12024b36082eSAlexandre Belloni regmap_update_bits(info->map, REG_ALT(0, info, pin->pin), 1203da801ab5SAlexandre Belloni BIT(p), f << p); 12044b36082eSAlexandre Belloni regmap_update_bits(info->map, REG_ALT(1, info, pin->pin), 1205da801ab5SAlexandre Belloni BIT(p), f << (p - 1)); 1206ce8dc094SAlexandre Belloni 1207ce8dc094SAlexandre Belloni return 0; 1208ce8dc094SAlexandre Belloni } 1209ce8dc094SAlexandre Belloni 1210531d6ab3SKavyasree Kotagiri static int lan966x_pinmux_set_mux(struct pinctrl_dev *pctldev, 1211531d6ab3SKavyasree Kotagiri unsigned int selector, unsigned int group) 1212531d6ab3SKavyasree Kotagiri { 1213531d6ab3SKavyasree Kotagiri struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1214531d6ab3SKavyasree Kotagiri struct ocelot_pin_caps *pin = info->desc->pins[group].drv_data; 1215531d6ab3SKavyasree Kotagiri unsigned int p = pin->pin % 32; 1216531d6ab3SKavyasree Kotagiri int f; 1217531d6ab3SKavyasree Kotagiri 1218531d6ab3SKavyasree Kotagiri f = ocelot_pin_function_idx(info, group, selector); 1219531d6ab3SKavyasree Kotagiri if (f < 0) 1220531d6ab3SKavyasree Kotagiri return -EINVAL; 1221531d6ab3SKavyasree Kotagiri 1222531d6ab3SKavyasree Kotagiri /* 1223531d6ab3SKavyasree Kotagiri * f is encoded on three bits. 1224531d6ab3SKavyasree Kotagiri * bit 0 of f goes in BIT(pin) of ALT[0], bit 1 of f goes in BIT(pin) of 1225531d6ab3SKavyasree Kotagiri * ALT[1], bit 2 of f goes in BIT(pin) of ALT[2] 1226531d6ab3SKavyasree Kotagiri * This is racy because three registers can't be updated at the same time 1227531d6ab3SKavyasree Kotagiri * but it doesn't matter much for now. 1228531d6ab3SKavyasree Kotagiri * Note: ALT0/ALT1/ALT2 are organized specially for 78 gpio targets 1229531d6ab3SKavyasree Kotagiri */ 1230531d6ab3SKavyasree Kotagiri regmap_update_bits(info->map, REG_ALT(0, info, pin->pin), 1231531d6ab3SKavyasree Kotagiri BIT(p), f << p); 1232531d6ab3SKavyasree Kotagiri regmap_update_bits(info->map, REG_ALT(1, info, pin->pin), 1233531d6ab3SKavyasree Kotagiri BIT(p), (f >> 1) << p); 1234531d6ab3SKavyasree Kotagiri regmap_update_bits(info->map, REG_ALT(2, info, pin->pin), 1235531d6ab3SKavyasree Kotagiri BIT(p), (f >> 2) << p); 1236531d6ab3SKavyasree Kotagiri 1237531d6ab3SKavyasree Kotagiri return 0; 1238531d6ab3SKavyasree Kotagiri } 1239531d6ab3SKavyasree Kotagiri 12404b36082eSAlexandre Belloni #define REG(r, info, p) ((r) * (info)->stride + (4 * ((p) / 32))) 12414b36082eSAlexandre Belloni 1242ce8dc094SAlexandre Belloni static int ocelot_gpio_set_direction(struct pinctrl_dev *pctldev, 1243ce8dc094SAlexandre Belloni struct pinctrl_gpio_range *range, 1244ce8dc094SAlexandre Belloni unsigned int pin, bool input) 1245ce8dc094SAlexandre Belloni { 1246ce8dc094SAlexandre Belloni struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1247da801ab5SAlexandre Belloni unsigned int p = pin % 32; 1248ce8dc094SAlexandre Belloni 1249f2818ba3SAlexandre Belloni regmap_update_bits(info->map, REG(OCELOT_GPIO_OE, info, pin), BIT(p), 1250da801ab5SAlexandre Belloni input ? 0 : BIT(p)); 1251ce8dc094SAlexandre Belloni 1252ce8dc094SAlexandre Belloni return 0; 1253ce8dc094SAlexandre Belloni } 1254ce8dc094SAlexandre Belloni 1255ce8dc094SAlexandre Belloni static int ocelot_gpio_request_enable(struct pinctrl_dev *pctldev, 1256ce8dc094SAlexandre Belloni struct pinctrl_gpio_range *range, 1257ce8dc094SAlexandre Belloni unsigned int offset) 1258ce8dc094SAlexandre Belloni { 1259ce8dc094SAlexandre Belloni struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1260da801ab5SAlexandre Belloni unsigned int p = offset % 32; 1261ce8dc094SAlexandre Belloni 12624b36082eSAlexandre Belloni regmap_update_bits(info->map, REG_ALT(0, info, offset), 1263da801ab5SAlexandre Belloni BIT(p), 0); 12644b36082eSAlexandre Belloni regmap_update_bits(info->map, REG_ALT(1, info, offset), 1265da801ab5SAlexandre Belloni BIT(p), 0); 1266ce8dc094SAlexandre Belloni 1267ce8dc094SAlexandre Belloni return 0; 1268ce8dc094SAlexandre Belloni } 1269ce8dc094SAlexandre Belloni 1270531d6ab3SKavyasree Kotagiri static int lan966x_gpio_request_enable(struct pinctrl_dev *pctldev, 1271531d6ab3SKavyasree Kotagiri struct pinctrl_gpio_range *range, 1272531d6ab3SKavyasree Kotagiri unsigned int offset) 1273531d6ab3SKavyasree Kotagiri { 1274531d6ab3SKavyasree Kotagiri struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1275531d6ab3SKavyasree Kotagiri unsigned int p = offset % 32; 1276531d6ab3SKavyasree Kotagiri 1277531d6ab3SKavyasree Kotagiri regmap_update_bits(info->map, REG_ALT(0, info, offset), 1278531d6ab3SKavyasree Kotagiri BIT(p), 0); 1279531d6ab3SKavyasree Kotagiri regmap_update_bits(info->map, REG_ALT(1, info, offset), 1280531d6ab3SKavyasree Kotagiri BIT(p), 0); 1281531d6ab3SKavyasree Kotagiri regmap_update_bits(info->map, REG_ALT(2, info, offset), 1282531d6ab3SKavyasree Kotagiri BIT(p), 0); 1283531d6ab3SKavyasree Kotagiri 1284531d6ab3SKavyasree Kotagiri return 0; 1285531d6ab3SKavyasree Kotagiri } 1286531d6ab3SKavyasree Kotagiri 1287ce8dc094SAlexandre Belloni static const struct pinmux_ops ocelot_pmx_ops = { 1288ce8dc094SAlexandre Belloni .get_functions_count = ocelot_get_functions_count, 1289ce8dc094SAlexandre Belloni .get_function_name = ocelot_get_function_name, 1290ce8dc094SAlexandre Belloni .get_function_groups = ocelot_get_function_groups, 1291ce8dc094SAlexandre Belloni .set_mux = ocelot_pinmux_set_mux, 1292ce8dc094SAlexandre Belloni .gpio_set_direction = ocelot_gpio_set_direction, 1293ce8dc094SAlexandre Belloni .gpio_request_enable = ocelot_gpio_request_enable, 1294ce8dc094SAlexandre Belloni }; 1295ce8dc094SAlexandre Belloni 1296531d6ab3SKavyasree Kotagiri static const struct pinmux_ops lan966x_pmx_ops = { 1297531d6ab3SKavyasree Kotagiri .get_functions_count = ocelot_get_functions_count, 1298531d6ab3SKavyasree Kotagiri .get_function_name = ocelot_get_function_name, 1299531d6ab3SKavyasree Kotagiri .get_function_groups = ocelot_get_function_groups, 1300531d6ab3SKavyasree Kotagiri .set_mux = lan966x_pinmux_set_mux, 1301531d6ab3SKavyasree Kotagiri .gpio_set_direction = ocelot_gpio_set_direction, 1302531d6ab3SKavyasree Kotagiri .gpio_request_enable = lan966x_gpio_request_enable, 1303531d6ab3SKavyasree Kotagiri }; 1304531d6ab3SKavyasree Kotagiri 1305ce8dc094SAlexandre Belloni static int ocelot_pctl_get_groups_count(struct pinctrl_dev *pctldev) 1306ce8dc094SAlexandre Belloni { 1307da801ab5SAlexandre Belloni struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1308da801ab5SAlexandre Belloni 1309da801ab5SAlexandre Belloni return info->desc->npins; 1310ce8dc094SAlexandre Belloni } 1311ce8dc094SAlexandre Belloni 1312ce8dc094SAlexandre Belloni static const char *ocelot_pctl_get_group_name(struct pinctrl_dev *pctldev, 1313ce8dc094SAlexandre Belloni unsigned int group) 1314ce8dc094SAlexandre Belloni { 1315da801ab5SAlexandre Belloni struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1316da801ab5SAlexandre Belloni 1317da801ab5SAlexandre Belloni return info->desc->pins[group].name; 1318ce8dc094SAlexandre Belloni } 1319ce8dc094SAlexandre Belloni 1320ce8dc094SAlexandre Belloni static int ocelot_pctl_get_group_pins(struct pinctrl_dev *pctldev, 1321ce8dc094SAlexandre Belloni unsigned int group, 1322ce8dc094SAlexandre Belloni const unsigned int **pins, 1323ce8dc094SAlexandre Belloni unsigned int *num_pins) 1324ce8dc094SAlexandre Belloni { 1325da801ab5SAlexandre Belloni struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1326da801ab5SAlexandre Belloni 1327da801ab5SAlexandre Belloni *pins = &info->desc->pins[group].number; 1328ce8dc094SAlexandre Belloni *num_pins = 1; 1329ce8dc094SAlexandre Belloni 1330ce8dc094SAlexandre Belloni return 0; 1331ce8dc094SAlexandre Belloni } 1332ce8dc094SAlexandre Belloni 1333f8a74760SLars Povlsen static int ocelot_hw_get_value(struct ocelot_pinctrl *info, 1334f8a74760SLars Povlsen unsigned int pin, 1335f8a74760SLars Povlsen unsigned int reg, 1336f8a74760SLars Povlsen int *val) 1337f8a74760SLars Povlsen { 1338f8a74760SLars Povlsen int ret = -EOPNOTSUPP; 1339f8a74760SLars Povlsen 1340f8a74760SLars Povlsen if (info->pincfg) { 1341dc62db71SHoratiu Vultur const struct ocelot_pincfg_data *opd = info->pincfg_data; 1342076d9e71SColin Foster u32 regcfg; 1343076d9e71SColin Foster 1344ba9c4745SHoratiu Vultur ret = regmap_read(info->pincfg, 1345ba9c4745SHoratiu Vultur pin * regmap_get_reg_stride(info->pincfg), 1346ba9c4745SHoratiu Vultur ®cfg); 1347076d9e71SColin Foster if (ret) 1348076d9e71SColin Foster return ret; 1349f8a74760SLars Povlsen 1350f8a74760SLars Povlsen ret = 0; 1351f8a74760SLars Povlsen switch (reg) { 1352f8a74760SLars Povlsen case PINCONF_BIAS: 1353dc62db71SHoratiu Vultur *val = regcfg & (opd->pd_bit | opd->pu_bit); 1354f8a74760SLars Povlsen break; 1355f8a74760SLars Povlsen 1356f8a74760SLars Povlsen case PINCONF_SCHMITT: 1357dc62db71SHoratiu Vultur *val = regcfg & opd->schmitt_bit; 1358f8a74760SLars Povlsen break; 1359f8a74760SLars Povlsen 1360f8a74760SLars Povlsen case PINCONF_DRIVE_STRENGTH: 1361dc62db71SHoratiu Vultur *val = regcfg & opd->drive_bits; 1362f8a74760SLars Povlsen break; 1363f8a74760SLars Povlsen 1364f8a74760SLars Povlsen default: 1365f8a74760SLars Povlsen ret = -EOPNOTSUPP; 1366f8a74760SLars Povlsen break; 1367f8a74760SLars Povlsen } 1368f8a74760SLars Povlsen } 1369f8a74760SLars Povlsen return ret; 1370f8a74760SLars Povlsen } 1371f8a74760SLars Povlsen 1372076d9e71SColin Foster static int ocelot_pincfg_clrsetbits(struct ocelot_pinctrl *info, u32 regaddr, 1373076d9e71SColin Foster u32 clrbits, u32 setbits) 1374076d9e71SColin Foster { 1375076d9e71SColin Foster u32 val; 1376076d9e71SColin Foster int ret; 1377076d9e71SColin Foster 1378ba9c4745SHoratiu Vultur ret = regmap_read(info->pincfg, 1379ba9c4745SHoratiu Vultur regaddr * regmap_get_reg_stride(info->pincfg), 1380ba9c4745SHoratiu Vultur &val); 1381076d9e71SColin Foster if (ret) 1382076d9e71SColin Foster return ret; 1383076d9e71SColin Foster 1384076d9e71SColin Foster val &= ~clrbits; 1385076d9e71SColin Foster val |= setbits; 1386076d9e71SColin Foster 1387ba9c4745SHoratiu Vultur ret = regmap_write(info->pincfg, 1388ba9c4745SHoratiu Vultur regaddr * regmap_get_reg_stride(info->pincfg), 1389ba9c4745SHoratiu Vultur val); 1390076d9e71SColin Foster 1391076d9e71SColin Foster return ret; 1392076d9e71SColin Foster } 1393076d9e71SColin Foster 1394f8a74760SLars Povlsen static int ocelot_hw_set_value(struct ocelot_pinctrl *info, 1395f8a74760SLars Povlsen unsigned int pin, 1396f8a74760SLars Povlsen unsigned int reg, 1397f8a74760SLars Povlsen int val) 1398f8a74760SLars Povlsen { 1399f8a74760SLars Povlsen int ret = -EOPNOTSUPP; 1400f8a74760SLars Povlsen 1401f8a74760SLars Povlsen if (info->pincfg) { 1402dc62db71SHoratiu Vultur const struct ocelot_pincfg_data *opd = info->pincfg_data; 1403f8a74760SLars Povlsen 1404f8a74760SLars Povlsen ret = 0; 1405f8a74760SLars Povlsen switch (reg) { 1406f8a74760SLars Povlsen case PINCONF_BIAS: 1407dc62db71SHoratiu Vultur ret = ocelot_pincfg_clrsetbits(info, pin, 1408dc62db71SHoratiu Vultur opd->pd_bit | opd->pu_bit, 1409076d9e71SColin Foster val); 1410f8a74760SLars Povlsen break; 1411f8a74760SLars Povlsen 1412f8a74760SLars Povlsen case PINCONF_SCHMITT: 1413dc62db71SHoratiu Vultur ret = ocelot_pincfg_clrsetbits(info, pin, 1414dc62db71SHoratiu Vultur opd->schmitt_bit, 1415076d9e71SColin Foster val); 1416f8a74760SLars Povlsen break; 1417f8a74760SLars Povlsen 1418f8a74760SLars Povlsen case PINCONF_DRIVE_STRENGTH: 1419f8a74760SLars Povlsen if (val <= 3) 1420076d9e71SColin Foster ret = ocelot_pincfg_clrsetbits(info, pin, 1421dc62db71SHoratiu Vultur opd->drive_bits, 1422dc62db71SHoratiu Vultur val); 1423f8a74760SLars Povlsen else 1424f8a74760SLars Povlsen ret = -EINVAL; 1425f8a74760SLars Povlsen break; 1426f8a74760SLars Povlsen 1427f8a74760SLars Povlsen default: 1428f8a74760SLars Povlsen ret = -EOPNOTSUPP; 1429f8a74760SLars Povlsen break; 1430f8a74760SLars Povlsen } 1431f8a74760SLars Povlsen } 1432f8a74760SLars Povlsen return ret; 1433f8a74760SLars Povlsen } 1434f8a74760SLars Povlsen 1435f8a74760SLars Povlsen static int ocelot_pinconf_get(struct pinctrl_dev *pctldev, 1436f8a74760SLars Povlsen unsigned int pin, unsigned long *config) 1437f8a74760SLars Povlsen { 1438f8a74760SLars Povlsen struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1439f8a74760SLars Povlsen u32 param = pinconf_to_config_param(*config); 1440f8a74760SLars Povlsen int val, err; 1441f8a74760SLars Povlsen 1442f8a74760SLars Povlsen switch (param) { 1443f8a74760SLars Povlsen case PIN_CONFIG_BIAS_DISABLE: 1444f8a74760SLars Povlsen case PIN_CONFIG_BIAS_PULL_UP: 1445f8a74760SLars Povlsen case PIN_CONFIG_BIAS_PULL_DOWN: 1446f8a74760SLars Povlsen err = ocelot_hw_get_value(info, pin, PINCONF_BIAS, &val); 1447f8a74760SLars Povlsen if (err) 1448f8a74760SLars Povlsen return err; 1449f8a74760SLars Povlsen if (param == PIN_CONFIG_BIAS_DISABLE) 145054515257SKaixu Xia val = (val == 0); 1451f8a74760SLars Povlsen else if (param == PIN_CONFIG_BIAS_PULL_DOWN) 1452dc62db71SHoratiu Vultur val = !!(val & info->pincfg_data->pd_bit); 1453f8a74760SLars Povlsen else /* PIN_CONFIG_BIAS_PULL_UP */ 1454dc62db71SHoratiu Vultur val = !!(val & info->pincfg_data->pu_bit); 1455f8a74760SLars Povlsen break; 1456f8a74760SLars Povlsen 1457f8a74760SLars Povlsen case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 1458dc62db71SHoratiu Vultur if (!info->pincfg_data->schmitt_bit) 1459dc62db71SHoratiu Vultur return -EOPNOTSUPP; 1460dc62db71SHoratiu Vultur 1461f8a74760SLars Povlsen err = ocelot_hw_get_value(info, pin, PINCONF_SCHMITT, &val); 1462f8a74760SLars Povlsen if (err) 1463f8a74760SLars Povlsen return err; 1464f8a74760SLars Povlsen 1465dc62db71SHoratiu Vultur val = !!(val & info->pincfg_data->schmitt_bit); 1466f8a74760SLars Povlsen break; 1467f8a74760SLars Povlsen 1468f8a74760SLars Povlsen case PIN_CONFIG_DRIVE_STRENGTH: 1469f8a74760SLars Povlsen err = ocelot_hw_get_value(info, pin, PINCONF_DRIVE_STRENGTH, 1470f8a74760SLars Povlsen &val); 1471f8a74760SLars Povlsen if (err) 1472f8a74760SLars Povlsen return err; 1473f8a74760SLars Povlsen break; 1474f8a74760SLars Povlsen 1475f8a74760SLars Povlsen case PIN_CONFIG_OUTPUT: 1476f8a74760SLars Povlsen err = regmap_read(info->map, REG(OCELOT_GPIO_OUT, info, pin), 1477f8a74760SLars Povlsen &val); 1478f8a74760SLars Povlsen if (err) 1479f8a74760SLars Povlsen return err; 1480f8a74760SLars Povlsen val = !!(val & BIT(pin % 32)); 1481f8a74760SLars Povlsen break; 1482f8a74760SLars Povlsen 1483f8a74760SLars Povlsen case PIN_CONFIG_INPUT_ENABLE: 1484f8a74760SLars Povlsen case PIN_CONFIG_OUTPUT_ENABLE: 1485f8a74760SLars Povlsen err = regmap_read(info->map, REG(OCELOT_GPIO_OE, info, pin), 1486f8a74760SLars Povlsen &val); 1487f8a74760SLars Povlsen if (err) 1488f8a74760SLars Povlsen return err; 1489f8a74760SLars Povlsen val = val & BIT(pin % 32); 1490f8a74760SLars Povlsen if (param == PIN_CONFIG_OUTPUT_ENABLE) 1491f8a74760SLars Povlsen val = !!val; 1492f8a74760SLars Povlsen else 1493f8a74760SLars Povlsen val = !val; 1494f8a74760SLars Povlsen break; 1495f8a74760SLars Povlsen 1496f8a74760SLars Povlsen default: 1497f8a74760SLars Povlsen return -EOPNOTSUPP; 1498f8a74760SLars Povlsen } 1499f8a74760SLars Povlsen 1500f8a74760SLars Povlsen *config = pinconf_to_config_packed(param, val); 1501f8a74760SLars Povlsen 1502f8a74760SLars Povlsen return 0; 1503f8a74760SLars Povlsen } 1504f8a74760SLars Povlsen 1505f8a74760SLars Povlsen static int ocelot_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 1506f8a74760SLars Povlsen unsigned long *configs, unsigned int num_configs) 1507f8a74760SLars Povlsen { 1508f8a74760SLars Povlsen struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1509dc62db71SHoratiu Vultur const struct ocelot_pincfg_data *opd = info->pincfg_data; 1510f8a74760SLars Povlsen u32 param, arg, p; 1511f8a74760SLars Povlsen int cfg, err = 0; 1512f8a74760SLars Povlsen 1513f8a74760SLars Povlsen for (cfg = 0; cfg < num_configs; cfg++) { 1514f8a74760SLars Povlsen param = pinconf_to_config_param(configs[cfg]); 1515f8a74760SLars Povlsen arg = pinconf_to_config_argument(configs[cfg]); 1516f8a74760SLars Povlsen 1517f8a74760SLars Povlsen switch (param) { 1518f8a74760SLars Povlsen case PIN_CONFIG_BIAS_DISABLE: 1519f8a74760SLars Povlsen case PIN_CONFIG_BIAS_PULL_UP: 1520f8a74760SLars Povlsen case PIN_CONFIG_BIAS_PULL_DOWN: 1521f8a74760SLars Povlsen arg = (param == PIN_CONFIG_BIAS_DISABLE) ? 0 : 1522dc62db71SHoratiu Vultur (param == PIN_CONFIG_BIAS_PULL_UP) ? 1523dc62db71SHoratiu Vultur opd->pu_bit : opd->pd_bit; 1524f8a74760SLars Povlsen 1525f8a74760SLars Povlsen err = ocelot_hw_set_value(info, pin, PINCONF_BIAS, arg); 1526f8a74760SLars Povlsen if (err) 1527f8a74760SLars Povlsen goto err; 1528f8a74760SLars Povlsen 1529f8a74760SLars Povlsen break; 1530f8a74760SLars Povlsen 1531f8a74760SLars Povlsen case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 1532dc62db71SHoratiu Vultur if (!opd->schmitt_bit) 1533dc62db71SHoratiu Vultur return -EOPNOTSUPP; 1534dc62db71SHoratiu Vultur 1535dc62db71SHoratiu Vultur arg = arg ? opd->schmitt_bit : 0; 1536f8a74760SLars Povlsen err = ocelot_hw_set_value(info, pin, PINCONF_SCHMITT, 1537f8a74760SLars Povlsen arg); 1538f8a74760SLars Povlsen if (err) 1539f8a74760SLars Povlsen goto err; 1540f8a74760SLars Povlsen 1541f8a74760SLars Povlsen break; 1542f8a74760SLars Povlsen 1543f8a74760SLars Povlsen case PIN_CONFIG_DRIVE_STRENGTH: 1544f8a74760SLars Povlsen err = ocelot_hw_set_value(info, pin, 1545f8a74760SLars Povlsen PINCONF_DRIVE_STRENGTH, 1546f8a74760SLars Povlsen arg); 1547f8a74760SLars Povlsen if (err) 1548f8a74760SLars Povlsen goto err; 1549f8a74760SLars Povlsen 1550f8a74760SLars Povlsen break; 1551f8a74760SLars Povlsen 1552f8a74760SLars Povlsen case PIN_CONFIG_OUTPUT_ENABLE: 1553f8a74760SLars Povlsen case PIN_CONFIG_INPUT_ENABLE: 1554f8a74760SLars Povlsen case PIN_CONFIG_OUTPUT: 1555f8a74760SLars Povlsen p = pin % 32; 1556f8a74760SLars Povlsen if (arg) 1557f8a74760SLars Povlsen regmap_write(info->map, 1558f8a74760SLars Povlsen REG(OCELOT_GPIO_OUT_SET, info, 1559f8a74760SLars Povlsen pin), 1560f8a74760SLars Povlsen BIT(p)); 1561f8a74760SLars Povlsen else 1562f8a74760SLars Povlsen regmap_write(info->map, 1563f8a74760SLars Povlsen REG(OCELOT_GPIO_OUT_CLR, info, 1564f8a74760SLars Povlsen pin), 1565f8a74760SLars Povlsen BIT(p)); 1566f8a74760SLars Povlsen regmap_update_bits(info->map, 1567f8a74760SLars Povlsen REG(OCELOT_GPIO_OE, info, pin), 1568f8a74760SLars Povlsen BIT(p), 1569f8a74760SLars Povlsen param == PIN_CONFIG_INPUT_ENABLE ? 1570f8a74760SLars Povlsen 0 : BIT(p)); 1571f8a74760SLars Povlsen break; 1572f8a74760SLars Povlsen 1573f8a74760SLars Povlsen default: 1574f8a74760SLars Povlsen err = -EOPNOTSUPP; 1575f8a74760SLars Povlsen } 1576f8a74760SLars Povlsen } 1577f8a74760SLars Povlsen err: 1578f8a74760SLars Povlsen return err; 1579f8a74760SLars Povlsen } 1580f8a74760SLars Povlsen 1581f8a74760SLars Povlsen static const struct pinconf_ops ocelot_confops = { 1582f8a74760SLars Povlsen .is_generic = true, 1583f8a74760SLars Povlsen .pin_config_get = ocelot_pinconf_get, 1584f8a74760SLars Povlsen .pin_config_set = ocelot_pinconf_set, 1585f8a74760SLars Povlsen .pin_config_config_dbg_show = pinconf_generic_dump_config, 1586f8a74760SLars Povlsen }; 1587f8a74760SLars Povlsen 1588ce8dc094SAlexandre Belloni static const struct pinctrl_ops ocelot_pctl_ops = { 1589ce8dc094SAlexandre Belloni .get_groups_count = ocelot_pctl_get_groups_count, 1590ce8dc094SAlexandre Belloni .get_group_name = ocelot_pctl_get_group_name, 1591ce8dc094SAlexandre Belloni .get_group_pins = ocelot_pctl_get_group_pins, 1592ce8dc094SAlexandre Belloni .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, 1593ce8dc094SAlexandre Belloni .dt_free_map = pinconf_generic_dt_free_map, 1594ce8dc094SAlexandre Belloni }; 1595ce8dc094SAlexandre Belloni 1596dc62db71SHoratiu Vultur static struct ocelot_match_data luton_desc = { 1597dc62db71SHoratiu Vultur .desc = { 15988f27440dSLars Povlsen .name = "luton-pinctrl", 15998f27440dSLars Povlsen .pins = luton_pins, 16008f27440dSLars Povlsen .npins = ARRAY_SIZE(luton_pins), 16018f27440dSLars Povlsen .pctlops = &ocelot_pctl_ops, 16028f27440dSLars Povlsen .pmxops = &ocelot_pmx_ops, 16038f27440dSLars Povlsen .owner = THIS_MODULE, 1604dc62db71SHoratiu Vultur }, 16058f27440dSLars Povlsen }; 16068f27440dSLars Povlsen 1607dc62db71SHoratiu Vultur static struct ocelot_match_data serval_desc = { 1608dc62db71SHoratiu Vultur .desc = { 16096e6347e2SLars Povlsen .name = "serval-pinctrl", 16106e6347e2SLars Povlsen .pins = serval_pins, 16116e6347e2SLars Povlsen .npins = ARRAY_SIZE(serval_pins), 16126e6347e2SLars Povlsen .pctlops = &ocelot_pctl_ops, 16136e6347e2SLars Povlsen .pmxops = &ocelot_pmx_ops, 16146e6347e2SLars Povlsen .owner = THIS_MODULE, 1615dc62db71SHoratiu Vultur }, 16166e6347e2SLars Povlsen }; 16176e6347e2SLars Povlsen 1618dc62db71SHoratiu Vultur static struct ocelot_match_data ocelot_desc = { 1619dc62db71SHoratiu Vultur .desc = { 1620ce8dc094SAlexandre Belloni .name = "ocelot-pinctrl", 1621ce8dc094SAlexandre Belloni .pins = ocelot_pins, 1622ce8dc094SAlexandre Belloni .npins = ARRAY_SIZE(ocelot_pins), 1623ce8dc094SAlexandre Belloni .pctlops = &ocelot_pctl_ops, 1624ce8dc094SAlexandre Belloni .pmxops = &ocelot_pmx_ops, 1625ce8dc094SAlexandre Belloni .owner = THIS_MODULE, 1626dc62db71SHoratiu Vultur }, 1627ce8dc094SAlexandre Belloni }; 1628ce8dc094SAlexandre Belloni 1629dc62db71SHoratiu Vultur static struct ocelot_match_data jaguar2_desc = { 1630dc62db71SHoratiu Vultur .desc = { 1631da801ab5SAlexandre Belloni .name = "jaguar2-pinctrl", 1632da801ab5SAlexandre Belloni .pins = jaguar2_pins, 1633da801ab5SAlexandre Belloni .npins = ARRAY_SIZE(jaguar2_pins), 1634da801ab5SAlexandre Belloni .pctlops = &ocelot_pctl_ops, 1635da801ab5SAlexandre Belloni .pmxops = &ocelot_pmx_ops, 1636da801ab5SAlexandre Belloni .owner = THIS_MODULE, 1637dc62db71SHoratiu Vultur }, 1638da801ab5SAlexandre Belloni }; 1639da801ab5SAlexandre Belloni 1640dc62db71SHoratiu Vultur static struct ocelot_match_data servalt_desc = { 1641dc62db71SHoratiu Vultur .desc = { 16428fc0bfcdSHoratiu Vultur .name = "servalt-pinctrl", 16438fc0bfcdSHoratiu Vultur .pins = servalt_pins, 16448fc0bfcdSHoratiu Vultur .npins = ARRAY_SIZE(servalt_pins), 16458fc0bfcdSHoratiu Vultur .pctlops = &ocelot_pctl_ops, 16468fc0bfcdSHoratiu Vultur .pmxops = &ocelot_pmx_ops, 16478fc0bfcdSHoratiu Vultur .owner = THIS_MODULE, 1648dc62db71SHoratiu Vultur }, 16498fc0bfcdSHoratiu Vultur }; 16508fc0bfcdSHoratiu Vultur 1651dc62db71SHoratiu Vultur static struct ocelot_match_data sparx5_desc = { 1652dc62db71SHoratiu Vultur .desc = { 1653f8a74760SLars Povlsen .name = "sparx5-pinctrl", 1654f8a74760SLars Povlsen .pins = sparx5_pins, 1655f8a74760SLars Povlsen .npins = ARRAY_SIZE(sparx5_pins), 1656f8a74760SLars Povlsen .pctlops = &ocelot_pctl_ops, 1657f8a74760SLars Povlsen .pmxops = &ocelot_pmx_ops, 1658f8a74760SLars Povlsen .confops = &ocelot_confops, 1659f8a74760SLars Povlsen .owner = THIS_MODULE, 1660dc62db71SHoratiu Vultur }, 1661dc62db71SHoratiu Vultur .pincfg_data = { 1662dc62db71SHoratiu Vultur .pd_bit = BIT(4), 1663dc62db71SHoratiu Vultur .pu_bit = BIT(3), 1664dc62db71SHoratiu Vultur .drive_bits = GENMASK(1, 0), 1665dc62db71SHoratiu Vultur .schmitt_bit = BIT(2), 1666dc62db71SHoratiu Vultur }, 1667f8a74760SLars Povlsen }; 1668f8a74760SLars Povlsen 1669dc62db71SHoratiu Vultur static struct ocelot_match_data lan966x_desc = { 1670dc62db71SHoratiu Vultur .desc = { 1671531d6ab3SKavyasree Kotagiri .name = "lan966x-pinctrl", 1672531d6ab3SKavyasree Kotagiri .pins = lan966x_pins, 1673531d6ab3SKavyasree Kotagiri .npins = ARRAY_SIZE(lan966x_pins), 1674531d6ab3SKavyasree Kotagiri .pctlops = &ocelot_pctl_ops, 1675531d6ab3SKavyasree Kotagiri .pmxops = &lan966x_pmx_ops, 1676531d6ab3SKavyasree Kotagiri .confops = &ocelot_confops, 1677531d6ab3SKavyasree Kotagiri .owner = THIS_MODULE, 1678dc62db71SHoratiu Vultur }, 1679dc62db71SHoratiu Vultur .pincfg_data = { 1680dc62db71SHoratiu Vultur .pd_bit = BIT(3), 1681dc62db71SHoratiu Vultur .pu_bit = BIT(2), 1682dc62db71SHoratiu Vultur .drive_bits = GENMASK(1, 0), 1683dc62db71SHoratiu Vultur }, 1684531d6ab3SKavyasree Kotagiri }; 1685531d6ab3SKavyasree Kotagiri 1686ce8dc094SAlexandre Belloni static int ocelot_create_group_func_map(struct device *dev, 1687ce8dc094SAlexandre Belloni struct ocelot_pinctrl *info) 1688ce8dc094SAlexandre Belloni { 1689ce8dc094SAlexandre Belloni int f, npins, i; 1690da801ab5SAlexandre Belloni u8 *pins = kcalloc(info->desc->npins, sizeof(u8), GFP_KERNEL); 1691da801ab5SAlexandre Belloni 1692da801ab5SAlexandre Belloni if (!pins) 1693da801ab5SAlexandre Belloni return -ENOMEM; 1694ce8dc094SAlexandre Belloni 1695ce8dc094SAlexandre Belloni for (f = 0; f < FUNC_MAX; f++) { 1696da801ab5SAlexandre Belloni for (npins = 0, i = 0; i < info->desc->npins; i++) { 1697da801ab5SAlexandre Belloni if (ocelot_pin_function_idx(info, i, f) >= 0) 1698ce8dc094SAlexandre Belloni pins[npins++] = i; 1699ce8dc094SAlexandre Belloni } 1700ce8dc094SAlexandre Belloni 1701da801ab5SAlexandre Belloni if (!npins) 1702da801ab5SAlexandre Belloni continue; 1703da801ab5SAlexandre Belloni 1704ce8dc094SAlexandre Belloni info->func[f].ngroups = npins; 1705da801ab5SAlexandre Belloni info->func[f].groups = devm_kcalloc(dev, npins, sizeof(char *), 1706ce8dc094SAlexandre Belloni GFP_KERNEL); 1707da801ab5SAlexandre Belloni if (!info->func[f].groups) { 1708da801ab5SAlexandre Belloni kfree(pins); 1709ce8dc094SAlexandre Belloni return -ENOMEM; 1710da801ab5SAlexandre Belloni } 1711ce8dc094SAlexandre Belloni 1712ce8dc094SAlexandre Belloni for (i = 0; i < npins; i++) 1713f8a74760SLars Povlsen info->func[f].groups[i] = 1714f8a74760SLars Povlsen info->desc->pins[pins[i]].name; 1715ce8dc094SAlexandre Belloni } 1716ce8dc094SAlexandre Belloni 1717da801ab5SAlexandre Belloni kfree(pins); 1718da801ab5SAlexandre Belloni 1719ce8dc094SAlexandre Belloni return 0; 1720ce8dc094SAlexandre Belloni } 1721ce8dc094SAlexandre Belloni 1722ce8dc094SAlexandre Belloni static int ocelot_pinctrl_register(struct platform_device *pdev, 1723ce8dc094SAlexandre Belloni struct ocelot_pinctrl *info) 1724ce8dc094SAlexandre Belloni { 1725ce8dc094SAlexandre Belloni int ret; 1726ce8dc094SAlexandre Belloni 1727ce8dc094SAlexandre Belloni ret = ocelot_create_group_func_map(&pdev->dev, info); 1728ce8dc094SAlexandre Belloni if (ret) { 1729ce8dc094SAlexandre Belloni dev_err(&pdev->dev, "Unable to create group func map.\n"); 1730ce8dc094SAlexandre Belloni return ret; 1731ce8dc094SAlexandre Belloni } 1732ce8dc094SAlexandre Belloni 1733da801ab5SAlexandre Belloni info->pctl = devm_pinctrl_register(&pdev->dev, info->desc, info); 1734ce8dc094SAlexandre Belloni if (IS_ERR(info->pctl)) { 1735ce8dc094SAlexandre Belloni dev_err(&pdev->dev, "Failed to register pinctrl\n"); 1736ce8dc094SAlexandre Belloni return PTR_ERR(info->pctl); 1737ce8dc094SAlexandre Belloni } 1738ce8dc094SAlexandre Belloni 1739ce8dc094SAlexandre Belloni return 0; 1740ce8dc094SAlexandre Belloni } 1741ce8dc094SAlexandre Belloni 1742ce8dc094SAlexandre Belloni static int ocelot_gpio_get(struct gpio_chip *chip, unsigned int offset) 1743ce8dc094SAlexandre Belloni { 1744ce8dc094SAlexandre Belloni struct ocelot_pinctrl *info = gpiochip_get_data(chip); 1745ce8dc094SAlexandre Belloni unsigned int val; 1746ce8dc094SAlexandre Belloni 1747da801ab5SAlexandre Belloni regmap_read(info->map, REG(OCELOT_GPIO_IN, info, offset), &val); 1748ce8dc094SAlexandre Belloni 1749da801ab5SAlexandre Belloni return !!(val & BIT(offset % 32)); 1750ce8dc094SAlexandre Belloni } 1751ce8dc094SAlexandre Belloni 1752ce8dc094SAlexandre Belloni static void ocelot_gpio_set(struct gpio_chip *chip, unsigned int offset, 1753ce8dc094SAlexandre Belloni int value) 1754ce8dc094SAlexandre Belloni { 1755ce8dc094SAlexandre Belloni struct ocelot_pinctrl *info = gpiochip_get_data(chip); 1756ce8dc094SAlexandre Belloni 1757ce8dc094SAlexandre Belloni if (value) 1758da801ab5SAlexandre Belloni regmap_write(info->map, REG(OCELOT_GPIO_OUT_SET, info, offset), 1759da801ab5SAlexandre Belloni BIT(offset % 32)); 1760ce8dc094SAlexandre Belloni else 1761da801ab5SAlexandre Belloni regmap_write(info->map, REG(OCELOT_GPIO_OUT_CLR, info, offset), 1762da801ab5SAlexandre Belloni BIT(offset % 32)); 1763ce8dc094SAlexandre Belloni } 1764ce8dc094SAlexandre Belloni 1765ce8dc094SAlexandre Belloni static int ocelot_gpio_get_direction(struct gpio_chip *chip, 1766ce8dc094SAlexandre Belloni unsigned int offset) 1767ce8dc094SAlexandre Belloni { 1768ce8dc094SAlexandre Belloni struct ocelot_pinctrl *info = gpiochip_get_data(chip); 1769ce8dc094SAlexandre Belloni unsigned int val; 1770ce8dc094SAlexandre Belloni 1771da801ab5SAlexandre Belloni regmap_read(info->map, REG(OCELOT_GPIO_OE, info, offset), &val); 1772ce8dc094SAlexandre Belloni 17733c827873SMatti Vaittinen if (val & BIT(offset % 32)) 17743c827873SMatti Vaittinen return GPIO_LINE_DIRECTION_OUT; 17753c827873SMatti Vaittinen 17763c827873SMatti Vaittinen return GPIO_LINE_DIRECTION_IN; 1777ce8dc094SAlexandre Belloni } 1778ce8dc094SAlexandre Belloni 1779ce8dc094SAlexandre Belloni static int ocelot_gpio_direction_input(struct gpio_chip *chip, 1780ce8dc094SAlexandre Belloni unsigned int offset) 1781ce8dc094SAlexandre Belloni { 1782ce8dc094SAlexandre Belloni return pinctrl_gpio_direction_input(chip->base + offset); 1783ce8dc094SAlexandre Belloni } 1784ce8dc094SAlexandre Belloni 1785ce8dc094SAlexandre Belloni static int ocelot_gpio_direction_output(struct gpio_chip *chip, 1786ce8dc094SAlexandre Belloni unsigned int offset, int value) 1787ce8dc094SAlexandre Belloni { 1788ce8dc094SAlexandre Belloni struct ocelot_pinctrl *info = gpiochip_get_data(chip); 1789da801ab5SAlexandre Belloni unsigned int pin = BIT(offset % 32); 1790ce8dc094SAlexandre Belloni 1791ce8dc094SAlexandre Belloni if (value) 1792da801ab5SAlexandre Belloni regmap_write(info->map, REG(OCELOT_GPIO_OUT_SET, info, offset), 1793da801ab5SAlexandre Belloni pin); 1794ce8dc094SAlexandre Belloni else 1795da801ab5SAlexandre Belloni regmap_write(info->map, REG(OCELOT_GPIO_OUT_CLR, info, offset), 1796da801ab5SAlexandre Belloni pin); 1797ce8dc094SAlexandre Belloni 1798ce8dc094SAlexandre Belloni return pinctrl_gpio_direction_output(chip->base + offset); 1799ce8dc094SAlexandre Belloni } 1800ce8dc094SAlexandre Belloni 1801ce8dc094SAlexandre Belloni static const struct gpio_chip ocelot_gpiolib_chip = { 1802ce8dc094SAlexandre Belloni .request = gpiochip_generic_request, 1803ce8dc094SAlexandre Belloni .free = gpiochip_generic_free, 1804ce8dc094SAlexandre Belloni .set = ocelot_gpio_set, 1805ce8dc094SAlexandre Belloni .get = ocelot_gpio_get, 1806ce8dc094SAlexandre Belloni .get_direction = ocelot_gpio_get_direction, 1807ce8dc094SAlexandre Belloni .direction_input = ocelot_gpio_direction_input, 1808ce8dc094SAlexandre Belloni .direction_output = ocelot_gpio_direction_output, 1809ce8dc094SAlexandre Belloni .owner = THIS_MODULE, 1810ce8dc094SAlexandre Belloni }; 1811ce8dc094SAlexandre Belloni 1812be36abb7SQuentin Schulz static void ocelot_irq_mask(struct irq_data *data) 1813be36abb7SQuentin Schulz { 1814be36abb7SQuentin Schulz struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 1815be36abb7SQuentin Schulz struct ocelot_pinctrl *info = gpiochip_get_data(chip); 1816be36abb7SQuentin Schulz unsigned int gpio = irqd_to_hwirq(data); 1817be36abb7SQuentin Schulz 1818da801ab5SAlexandre Belloni regmap_update_bits(info->map, REG(OCELOT_GPIO_INTR_ENA, info, gpio), 1819da801ab5SAlexandre Belloni BIT(gpio % 32), 0); 182051ff9392SMichael Walle gpiochip_disable_irq(chip, gpio); 1821be36abb7SQuentin Schulz } 1822be36abb7SQuentin Schulz 1823c297561bSHoratiu Vultur static void ocelot_irq_work(struct work_struct *work) 1824c297561bSHoratiu Vultur { 1825c297561bSHoratiu Vultur struct ocelot_irq_work *w = container_of(work, struct ocelot_irq_work, irq_work); 1826c297561bSHoratiu Vultur struct irq_chip *parent_chip = irq_desc_get_chip(w->irq_desc); 1827c297561bSHoratiu Vultur struct gpio_chip *chip = irq_desc_get_chip_data(w->irq_desc); 1828c297561bSHoratiu Vultur struct irq_data *data = irq_desc_get_irq_data(w->irq_desc); 1829c297561bSHoratiu Vultur unsigned int gpio = irqd_to_hwirq(data); 1830c297561bSHoratiu Vultur 1831c297561bSHoratiu Vultur local_irq_disable(); 1832c297561bSHoratiu Vultur chained_irq_enter(parent_chip, w->irq_desc); 1833c297561bSHoratiu Vultur generic_handle_domain_irq(chip->irq.domain, gpio); 1834c297561bSHoratiu Vultur chained_irq_exit(parent_chip, w->irq_desc); 1835c297561bSHoratiu Vultur local_irq_enable(); 1836c297561bSHoratiu Vultur 1837c297561bSHoratiu Vultur kfree(w); 1838c297561bSHoratiu Vultur } 1839c297561bSHoratiu Vultur 1840c297561bSHoratiu Vultur static void ocelot_irq_unmask_level(struct irq_data *data) 1841c297561bSHoratiu Vultur { 1842c297561bSHoratiu Vultur struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 1843c297561bSHoratiu Vultur struct ocelot_pinctrl *info = gpiochip_get_data(chip); 1844c297561bSHoratiu Vultur struct irq_desc *desc = irq_data_to_desc(data); 1845c297561bSHoratiu Vultur unsigned int gpio = irqd_to_hwirq(data); 1846c297561bSHoratiu Vultur unsigned int bit = BIT(gpio % 32); 1847c297561bSHoratiu Vultur bool ack = false, active = false; 1848c297561bSHoratiu Vultur u8 trigger_level; 1849c297561bSHoratiu Vultur int val; 1850c297561bSHoratiu Vultur 1851c297561bSHoratiu Vultur trigger_level = irqd_get_trigger_type(data); 1852c297561bSHoratiu Vultur 1853c297561bSHoratiu Vultur /* Check if the interrupt line is still active. */ 1854c297561bSHoratiu Vultur regmap_read(info->map, REG(OCELOT_GPIO_IN, info, gpio), &val); 1855c297561bSHoratiu Vultur if ((!(val & bit) && trigger_level == IRQ_TYPE_LEVEL_LOW) || 1856c297561bSHoratiu Vultur (val & bit && trigger_level == IRQ_TYPE_LEVEL_HIGH)) 1857c297561bSHoratiu Vultur active = true; 1858c297561bSHoratiu Vultur 1859c297561bSHoratiu Vultur /* 1860c297561bSHoratiu Vultur * Check if the interrupt controller has seen any changes in the 1861c297561bSHoratiu Vultur * interrupt line. 1862c297561bSHoratiu Vultur */ 1863c297561bSHoratiu Vultur regmap_read(info->map, REG(OCELOT_GPIO_INTR, info, gpio), &val); 1864c297561bSHoratiu Vultur if (val & bit) 1865c297561bSHoratiu Vultur ack = true; 1866c297561bSHoratiu Vultur 1867*e9945b26SHoratiu Vultur /* Try to clear any rising edges */ 1868*e9945b26SHoratiu Vultur if (!active && ack) 1869*e9945b26SHoratiu Vultur regmap_write_bits(info->map, REG(OCELOT_GPIO_INTR, info, gpio), 1870*e9945b26SHoratiu Vultur bit, bit); 1871*e9945b26SHoratiu Vultur 1872c297561bSHoratiu Vultur /* Enable the interrupt now */ 1873c297561bSHoratiu Vultur gpiochip_enable_irq(chip, gpio); 1874c297561bSHoratiu Vultur regmap_update_bits(info->map, REG(OCELOT_GPIO_INTR_ENA, info, gpio), 1875c297561bSHoratiu Vultur bit, bit); 1876c297561bSHoratiu Vultur 1877c297561bSHoratiu Vultur /* 1878*e9945b26SHoratiu Vultur * In case the interrupt line is still active then it means that 1879*e9945b26SHoratiu Vultur * there happen another interrupt while the line was active. 1880c297561bSHoratiu Vultur * So we missed that one, so we need to kick the interrupt again 1881c297561bSHoratiu Vultur * handler. 1882c297561bSHoratiu Vultur */ 1883*e9945b26SHoratiu Vultur regmap_read(info->map, REG(OCELOT_GPIO_IN, info, gpio), &val); 1884*e9945b26SHoratiu Vultur if ((!(val & bit) && trigger_level == IRQ_TYPE_LEVEL_LOW) || 1885*e9945b26SHoratiu Vultur (val & bit && trigger_level == IRQ_TYPE_LEVEL_HIGH)) 1886*e9945b26SHoratiu Vultur active = true; 1887*e9945b26SHoratiu Vultur 1888*e9945b26SHoratiu Vultur if (active) { 1889c297561bSHoratiu Vultur struct ocelot_irq_work *work; 1890c297561bSHoratiu Vultur 1891c297561bSHoratiu Vultur work = kmalloc(sizeof(*work), GFP_ATOMIC); 1892c297561bSHoratiu Vultur if (!work) 1893c297561bSHoratiu Vultur return; 1894c297561bSHoratiu Vultur 1895c297561bSHoratiu Vultur work->irq_desc = desc; 1896c297561bSHoratiu Vultur INIT_WORK(&work->irq_work, ocelot_irq_work); 1897c297561bSHoratiu Vultur queue_work(info->wq, &work->irq_work); 1898c297561bSHoratiu Vultur } 1899c297561bSHoratiu Vultur } 1900c297561bSHoratiu Vultur 1901be36abb7SQuentin Schulz static void ocelot_irq_unmask(struct irq_data *data) 1902be36abb7SQuentin Schulz { 1903be36abb7SQuentin Schulz struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 1904be36abb7SQuentin Schulz struct ocelot_pinctrl *info = gpiochip_get_data(chip); 1905be36abb7SQuentin Schulz unsigned int gpio = irqd_to_hwirq(data); 1906be36abb7SQuentin Schulz 190751ff9392SMichael Walle gpiochip_enable_irq(chip, gpio); 1908da801ab5SAlexandre Belloni regmap_update_bits(info->map, REG(OCELOT_GPIO_INTR_ENA, info, gpio), 1909da801ab5SAlexandre Belloni BIT(gpio % 32), BIT(gpio % 32)); 1910be36abb7SQuentin Schulz } 1911be36abb7SQuentin Schulz 1912be36abb7SQuentin Schulz static void ocelot_irq_ack(struct irq_data *data) 1913be36abb7SQuentin Schulz { 1914be36abb7SQuentin Schulz struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 1915be36abb7SQuentin Schulz struct ocelot_pinctrl *info = gpiochip_get_data(chip); 1916be36abb7SQuentin Schulz unsigned int gpio = irqd_to_hwirq(data); 1917be36abb7SQuentin Schulz 1918da801ab5SAlexandre Belloni regmap_write_bits(info->map, REG(OCELOT_GPIO_INTR, info, gpio), 1919da801ab5SAlexandre Belloni BIT(gpio % 32), BIT(gpio % 32)); 1920be36abb7SQuentin Schulz } 1921be36abb7SQuentin Schulz 1922be36abb7SQuentin Schulz static int ocelot_irq_set_type(struct irq_data *data, unsigned int type); 1923be36abb7SQuentin Schulz 1924c297561bSHoratiu Vultur static struct irq_chip ocelot_level_irqchip = { 1925be36abb7SQuentin Schulz .name = "gpio", 1926be36abb7SQuentin Schulz .irq_mask = ocelot_irq_mask, 1927c297561bSHoratiu Vultur .irq_ack = ocelot_irq_ack, 1928c297561bSHoratiu Vultur .irq_unmask = ocelot_irq_unmask_level, 1929c297561bSHoratiu Vultur .flags = IRQCHIP_IMMUTABLE, 1930be36abb7SQuentin Schulz .irq_set_type = ocelot_irq_set_type, 193151ff9392SMichael Walle GPIOCHIP_IRQ_RESOURCE_HELPERS 1932be36abb7SQuentin Schulz }; 1933be36abb7SQuentin Schulz 1934be36abb7SQuentin Schulz static struct irq_chip ocelot_irqchip = { 1935be36abb7SQuentin Schulz .name = "gpio", 1936be36abb7SQuentin Schulz .irq_mask = ocelot_irq_mask, 1937be36abb7SQuentin Schulz .irq_ack = ocelot_irq_ack, 1938be36abb7SQuentin Schulz .irq_unmask = ocelot_irq_unmask, 1939be36abb7SQuentin Schulz .irq_set_type = ocelot_irq_set_type, 194051ff9392SMichael Walle .flags = IRQCHIP_IMMUTABLE, 194151ff9392SMichael Walle GPIOCHIP_IRQ_RESOURCE_HELPERS 1942be36abb7SQuentin Schulz }; 1943be36abb7SQuentin Schulz 1944be36abb7SQuentin Schulz static int ocelot_irq_set_type(struct irq_data *data, unsigned int type) 1945be36abb7SQuentin Schulz { 1946c297561bSHoratiu Vultur if (type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) 1947c297561bSHoratiu Vultur irq_set_chip_handler_name_locked(data, &ocelot_level_irqchip, 1948c297561bSHoratiu Vultur handle_level_irq, NULL); 1949be36abb7SQuentin Schulz if (type & IRQ_TYPE_EDGE_BOTH) 1950be36abb7SQuentin Schulz irq_set_chip_handler_name_locked(data, &ocelot_irqchip, 1951be36abb7SQuentin Schulz handle_edge_irq, NULL); 1952be36abb7SQuentin Schulz 1953be36abb7SQuentin Schulz return 0; 1954be36abb7SQuentin Schulz } 1955be36abb7SQuentin Schulz 1956be36abb7SQuentin Schulz static void ocelot_irq_handler(struct irq_desc *desc) 1957be36abb7SQuentin Schulz { 1958be36abb7SQuentin Schulz struct irq_chip *parent_chip = irq_desc_get_chip(desc); 1959be36abb7SQuentin Schulz struct gpio_chip *chip = irq_desc_get_handler_data(desc); 1960be36abb7SQuentin Schulz struct ocelot_pinctrl *info = gpiochip_get_data(chip); 19610b47afc6SLars Povlsen unsigned int id_reg = OCELOT_GPIO_INTR_IDENT * info->stride; 1962da801ab5SAlexandre Belloni unsigned int reg = 0, irq, i; 1963be36abb7SQuentin Schulz unsigned long irqs; 1964be36abb7SQuentin Schulz 1965da801ab5SAlexandre Belloni for (i = 0; i < info->stride; i++) { 19660b47afc6SLars Povlsen regmap_read(info->map, id_reg + 4 * i, ®); 1967be36abb7SQuentin Schulz if (!reg) 1968da801ab5SAlexandre Belloni continue; 1969be36abb7SQuentin Schulz 1970be36abb7SQuentin Schulz chained_irq_enter(parent_chip, desc); 1971be36abb7SQuentin Schulz 1972be36abb7SQuentin Schulz irqs = reg; 1973be36abb7SQuentin Schulz 1974da801ab5SAlexandre Belloni for_each_set_bit(irq, &irqs, 1975da801ab5SAlexandre Belloni min(32U, info->desc->npins - 32 * i)) 1976a9cb09b7SMarc Zyngier generic_handle_domain_irq(chip->irq.domain, irq + 32 * i); 1977be36abb7SQuentin Schulz 1978be36abb7SQuentin Schulz chained_irq_exit(parent_chip, desc); 1979be36abb7SQuentin Schulz } 1980da801ab5SAlexandre Belloni } 1981be36abb7SQuentin Schulz 1982ce8dc094SAlexandre Belloni static int ocelot_gpiochip_register(struct platform_device *pdev, 1983ce8dc094SAlexandre Belloni struct ocelot_pinctrl *info) 1984ce8dc094SAlexandre Belloni { 1985ce8dc094SAlexandre Belloni struct gpio_chip *gc; 1986d874becaSLinus Walleij struct gpio_irq_chip *girq; 198717f2c8d3SQinglang Miao int irq; 1988ce8dc094SAlexandre Belloni 1989ce8dc094SAlexandre Belloni info->gpio_chip = ocelot_gpiolib_chip; 1990ce8dc094SAlexandre Belloni 1991ce8dc094SAlexandre Belloni gc = &info->gpio_chip; 1992da801ab5SAlexandre Belloni gc->ngpio = info->desc->npins; 1993ce8dc094SAlexandre Belloni gc->parent = &pdev->dev; 1994a159c2b4SColin Foster gc->base = -1; 1995ce8dc094SAlexandre Belloni gc->label = "ocelot-gpio"; 1996ce8dc094SAlexandre Belloni 1997d1f2c82fSHoratiu Vultur irq = platform_get_irq_optional(pdev, 0); 1998d1f2c82fSHoratiu Vultur if (irq > 0) { 1999d874becaSLinus Walleij girq = &gc->irq; 200051ff9392SMichael Walle gpio_irq_chip_set_chip(girq, &ocelot_irqchip); 2001d874becaSLinus Walleij girq->parent_handler = ocelot_irq_handler; 2002d874becaSLinus Walleij girq->num_parents = 1; 2003550713e3SLars Povlsen girq->parents = devm_kcalloc(&pdev->dev, 1, 2004550713e3SLars Povlsen sizeof(*girq->parents), 2005d874becaSLinus Walleij GFP_KERNEL); 2006d874becaSLinus Walleij if (!girq->parents) 2007d874becaSLinus Walleij return -ENOMEM; 2008d874becaSLinus Walleij girq->parents[0] = irq; 2009d874becaSLinus Walleij girq->default_type = IRQ_TYPE_NONE; 2010d874becaSLinus Walleij girq->handler = handle_edge_irq; 2011550713e3SLars Povlsen } 2012d874becaSLinus Walleij 201317f2c8d3SQinglang Miao return devm_gpiochip_add_data(&pdev->dev, gc, info); 2014ce8dc094SAlexandre Belloni } 2015ce8dc094SAlexandre Belloni 2016ce8dc094SAlexandre Belloni static const struct of_device_id ocelot_pinctrl_of_match[] = { 20178f27440dSLars Povlsen { .compatible = "mscc,luton-pinctrl", .data = &luton_desc }, 20186e6347e2SLars Povlsen { .compatible = "mscc,serval-pinctrl", .data = &serval_desc }, 2019da801ab5SAlexandre Belloni { .compatible = "mscc,ocelot-pinctrl", .data = &ocelot_desc }, 2020da801ab5SAlexandre Belloni { .compatible = "mscc,jaguar2-pinctrl", .data = &jaguar2_desc }, 20218fc0bfcdSHoratiu Vultur { .compatible = "mscc,servalt-pinctrl", .data = &servalt_desc }, 2022f8a74760SLars Povlsen { .compatible = "microchip,sparx5-pinctrl", .data = &sparx5_desc }, 2023531d6ab3SKavyasree Kotagiri { .compatible = "microchip,lan966x-pinctrl", .data = &lan966x_desc }, 2024ce8dc094SAlexandre Belloni {}, 2025ce8dc094SAlexandre Belloni }; 20264425205eSClément Léger MODULE_DEVICE_TABLE(of, ocelot_pinctrl_of_match); 2027ce8dc094SAlexandre Belloni 2028ba9c4745SHoratiu Vultur static struct regmap *ocelot_pinctrl_create_pincfg(struct platform_device *pdev, 2029ba9c4745SHoratiu Vultur const struct ocelot_pinctrl *info) 2030076d9e71SColin Foster { 2031076d9e71SColin Foster void __iomem *base; 2032076d9e71SColin Foster 2033076d9e71SColin Foster const struct regmap_config regmap_config = { 2034076d9e71SColin Foster .reg_bits = 32, 2035076d9e71SColin Foster .val_bits = 32, 2036076d9e71SColin Foster .reg_stride = 4, 2037ba9c4745SHoratiu Vultur .max_register = info->desc->npins * 4, 2038359afd90SMichael Walle .name = "pincfg", 2039076d9e71SColin Foster }; 2040076d9e71SColin Foster 204194ef3297SMichael Walle base = devm_platform_ioremap_resource(pdev, 1); 2042076d9e71SColin Foster if (IS_ERR(base)) { 2043076d9e71SColin Foster dev_dbg(&pdev->dev, "Failed to ioremap config registers (no extended pinconf)\n"); 2044076d9e71SColin Foster return NULL; 2045076d9e71SColin Foster } 2046076d9e71SColin Foster 2047076d9e71SColin Foster return devm_regmap_init_mmio(&pdev->dev, base, ®map_config); 2048076d9e71SColin Foster } 2049076d9e71SColin Foster 2050ce3e7f0eSColin Ian King static int ocelot_pinctrl_probe(struct platform_device *pdev) 2051ce8dc094SAlexandre Belloni { 2052dc62db71SHoratiu Vultur const struct ocelot_match_data *data; 2053ce8dc094SAlexandre Belloni struct device *dev = &pdev->dev; 2054ce8dc094SAlexandre Belloni struct ocelot_pinctrl *info; 2055453200afSMichael Walle struct reset_control *reset; 2056076d9e71SColin Foster struct regmap *pincfg; 2057ce8dc094SAlexandre Belloni int ret; 2058da801ab5SAlexandre Belloni struct regmap_config regmap_config = { 2059da801ab5SAlexandre Belloni .reg_bits = 32, 2060da801ab5SAlexandre Belloni .val_bits = 32, 2061da801ab5SAlexandre Belloni .reg_stride = 4, 2062da801ab5SAlexandre Belloni }; 2063ce8dc094SAlexandre Belloni 2064ce8dc094SAlexandre Belloni info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL); 2065ce8dc094SAlexandre Belloni if (!info) 2066ce8dc094SAlexandre Belloni return -ENOMEM; 2067ce8dc094SAlexandre Belloni 2068dc62db71SHoratiu Vultur data = device_get_match_data(dev); 2069dc62db71SHoratiu Vultur if (!data) 2070dc62db71SHoratiu Vultur return -EINVAL; 2071dc62db71SHoratiu Vultur 2072dc62db71SHoratiu Vultur info->desc = devm_kmemdup(dev, &data->desc, sizeof(*info->desc), 2073dc62db71SHoratiu Vultur GFP_KERNEL); 2074dc62db71SHoratiu Vultur if (!info->desc) 2075dc62db71SHoratiu Vultur return -ENOMEM; 2076dc62db71SHoratiu Vultur 2077c297561bSHoratiu Vultur info->wq = alloc_ordered_workqueue("ocelot_ordered", 0); 2078c297561bSHoratiu Vultur if (!info->wq) 2079c297561bSHoratiu Vultur return -ENOMEM; 2080c297561bSHoratiu Vultur 2081dc62db71SHoratiu Vultur info->pincfg_data = &data->pincfg_data; 2082da801ab5SAlexandre Belloni 2083453200afSMichael Walle reset = devm_reset_control_get_optional_shared(dev, "switch"); 2084453200afSMichael Walle if (IS_ERR(reset)) 2085453200afSMichael Walle return dev_err_probe(dev, PTR_ERR(reset), 2086453200afSMichael Walle "Failed to get reset\n"); 2087453200afSMichael Walle reset_control_reset(reset); 2088453200afSMichael Walle 2089da801ab5SAlexandre Belloni info->stride = 1 + (info->desc->npins - 1) / 32; 2090f8a74760SLars Povlsen 2091da801ab5SAlexandre Belloni regmap_config.max_register = OCELOT_GPIO_SD_MAP * info->stride + 15 * 4; 2092da801ab5SAlexandre Belloni 2093181f604bSColin Foster info->map = ocelot_regmap_from_resource(pdev, 0, ®map_config); 2094181f604bSColin Foster if (IS_ERR(info->map)) 2095181f604bSColin Foster return dev_err_probe(dev, PTR_ERR(info->map), 2096181f604bSColin Foster "Failed to create regmap\n"); 2097c297561bSHoratiu Vultur dev_set_drvdata(dev, info); 2098ce8dc094SAlexandre Belloni info->dev = dev; 2099ce8dc094SAlexandre Belloni 2100f8a74760SLars Povlsen /* Pinconf registers */ 2101f8a74760SLars Povlsen if (info->desc->confops) { 2102ba9c4745SHoratiu Vultur pincfg = ocelot_pinctrl_create_pincfg(pdev, info); 2103076d9e71SColin Foster if (IS_ERR(pincfg)) 2104076d9e71SColin Foster dev_dbg(dev, "Failed to create pincfg regmap\n"); 2105f8a74760SLars Povlsen else 2106076d9e71SColin Foster info->pincfg = pincfg; 2107f8a74760SLars Povlsen } 2108f8a74760SLars Povlsen 2109ce8dc094SAlexandre Belloni ret = ocelot_pinctrl_register(pdev, info); 2110ce8dc094SAlexandre Belloni if (ret) 2111ce8dc094SAlexandre Belloni return ret; 2112ce8dc094SAlexandre Belloni 2113ce8dc094SAlexandre Belloni ret = ocelot_gpiochip_register(pdev, info); 2114ce8dc094SAlexandre Belloni if (ret) 2115ce8dc094SAlexandre Belloni return ret; 2116ce8dc094SAlexandre Belloni 2117f8a74760SLars Povlsen dev_info(dev, "driver registered\n"); 2118f8a74760SLars Povlsen 2119ce8dc094SAlexandre Belloni return 0; 2120ce8dc094SAlexandre Belloni } 2121ce8dc094SAlexandre Belloni 2122c297561bSHoratiu Vultur static int ocelot_pinctrl_remove(struct platform_device *pdev) 2123c297561bSHoratiu Vultur { 2124c297561bSHoratiu Vultur struct ocelot_pinctrl *info = platform_get_drvdata(pdev); 2125c297561bSHoratiu Vultur 2126c297561bSHoratiu Vultur destroy_workqueue(info->wq); 2127c297561bSHoratiu Vultur 2128c297561bSHoratiu Vultur return 0; 2129c297561bSHoratiu Vultur } 2130c297561bSHoratiu Vultur 2131ce8dc094SAlexandre Belloni static struct platform_driver ocelot_pinctrl_driver = { 2132ce8dc094SAlexandre Belloni .driver = { 2133ce8dc094SAlexandre Belloni .name = "pinctrl-ocelot", 2134ce8dc094SAlexandre Belloni .of_match_table = of_match_ptr(ocelot_pinctrl_of_match), 2135ce8dc094SAlexandre Belloni .suppress_bind_attrs = true, 2136ce8dc094SAlexandre Belloni }, 2137ce8dc094SAlexandre Belloni .probe = ocelot_pinctrl_probe, 2138c297561bSHoratiu Vultur .remove = ocelot_pinctrl_remove, 2139ce8dc094SAlexandre Belloni }; 21404425205eSClément Léger module_platform_driver(ocelot_pinctrl_driver); 21413f668365SColin Foster 21423f668365SColin Foster MODULE_DESCRIPTION("Ocelot Chip Pinctrl Driver"); 21434425205eSClément Léger MODULE_LICENSE("Dual MIT/GPL"); 2144