1ce8dc094SAlexandre Belloni // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2ce8dc094SAlexandre Belloni /* 3ce8dc094SAlexandre Belloni * Microsemi SoCs pinctrl driver 4ce8dc094SAlexandre Belloni * 5ce8dc094SAlexandre Belloni * Author: <alexandre.belloni@free-electrons.com> 6ce8dc094SAlexandre Belloni * License: Dual MIT/GPL 7ce8dc094SAlexandre Belloni * Copyright (c) 2017 Microsemi Corporation 8ce8dc094SAlexandre Belloni */ 9ce8dc094SAlexandre Belloni 10ce8dc094SAlexandre Belloni #include <linux/gpio/driver.h> 11ce8dc094SAlexandre Belloni #include <linux/interrupt.h> 12ce8dc094SAlexandre Belloni #include <linux/io.h> 13ce8dc094SAlexandre Belloni #include <linux/of_device.h> 14be36abb7SQuentin Schulz #include <linux/of_irq.h> 15ce8dc094SAlexandre Belloni #include <linux/of_platform.h> 16ce8dc094SAlexandre Belloni #include <linux/pinctrl/pinctrl.h> 17ce8dc094SAlexandre Belloni #include <linux/pinctrl/pinmux.h> 18ce8dc094SAlexandre Belloni #include <linux/pinctrl/pinconf.h> 19ce8dc094SAlexandre Belloni #include <linux/pinctrl/pinconf-generic.h> 20ce8dc094SAlexandre Belloni #include <linux/platform_device.h> 21ce8dc094SAlexandre Belloni #include <linux/regmap.h> 22ce8dc094SAlexandre Belloni #include <linux/slab.h> 23ce8dc094SAlexandre Belloni 24ce8dc094SAlexandre Belloni #include "core.h" 25ce8dc094SAlexandre Belloni #include "pinconf.h" 26ce8dc094SAlexandre Belloni #include "pinmux.h" 27ce8dc094SAlexandre Belloni 28f8a74760SLars Povlsen #define ocelot_clrsetbits(addr, clear, set) \ 29f8a74760SLars Povlsen writel((readl(addr) & ~(clear)) | (set), (addr)) 30f8a74760SLars Povlsen 31f8a74760SLars Povlsen /* PINCONFIG bits (sparx5 only) */ 32f8a74760SLars Povlsen enum { 33f8a74760SLars Povlsen PINCONF_BIAS, 34f8a74760SLars Povlsen PINCONF_SCHMITT, 35f8a74760SLars Povlsen PINCONF_DRIVE_STRENGTH, 36f8a74760SLars Povlsen }; 37f8a74760SLars Povlsen 38f8a74760SLars Povlsen #define BIAS_PD_BIT BIT(4) 39f8a74760SLars Povlsen #define BIAS_PU_BIT BIT(3) 40f8a74760SLars Povlsen #define BIAS_BITS (BIAS_PD_BIT|BIAS_PU_BIT) 41f8a74760SLars Povlsen #define SCHMITT_BIT BIT(2) 42f8a74760SLars Povlsen #define DRIVE_BITS GENMASK(1, 0) 43f8a74760SLars Povlsen 44f8a74760SLars Povlsen /* GPIO standard registers */ 45ce8dc094SAlexandre Belloni #define OCELOT_GPIO_OUT_SET 0x0 46ce8dc094SAlexandre Belloni #define OCELOT_GPIO_OUT_CLR 0x4 47ce8dc094SAlexandre Belloni #define OCELOT_GPIO_OUT 0x8 48ce8dc094SAlexandre Belloni #define OCELOT_GPIO_IN 0xc 49ce8dc094SAlexandre Belloni #define OCELOT_GPIO_OE 0x10 50ce8dc094SAlexandre Belloni #define OCELOT_GPIO_INTR 0x14 51ce8dc094SAlexandre Belloni #define OCELOT_GPIO_INTR_ENA 0x18 52ce8dc094SAlexandre Belloni #define OCELOT_GPIO_INTR_IDENT 0x1c 53ce8dc094SAlexandre Belloni #define OCELOT_GPIO_ALT0 0x20 54ce8dc094SAlexandre Belloni #define OCELOT_GPIO_ALT1 0x24 55ce8dc094SAlexandre Belloni #define OCELOT_GPIO_SD_MAP 0x28 56ce8dc094SAlexandre Belloni 57ce8dc094SAlexandre Belloni #define OCELOT_FUNC_PER_PIN 4 58ce8dc094SAlexandre Belloni 59ce8dc094SAlexandre Belloni enum { 60531d6ab3SKavyasree Kotagiri FUNC_CAN0_a, 61531d6ab3SKavyasree Kotagiri FUNC_CAN0_b, 62531d6ab3SKavyasree Kotagiri FUNC_CAN1, 63ce8dc094SAlexandre Belloni FUNC_NONE, 64531d6ab3SKavyasree Kotagiri FUNC_FC0_a, 65531d6ab3SKavyasree Kotagiri FUNC_FC0_b, 66531d6ab3SKavyasree Kotagiri FUNC_FC0_c, 67531d6ab3SKavyasree Kotagiri FUNC_FC1_a, 68531d6ab3SKavyasree Kotagiri FUNC_FC1_b, 69531d6ab3SKavyasree Kotagiri FUNC_FC1_c, 70531d6ab3SKavyasree Kotagiri FUNC_FC2_a, 71531d6ab3SKavyasree Kotagiri FUNC_FC2_b, 72531d6ab3SKavyasree Kotagiri FUNC_FC3_a, 73531d6ab3SKavyasree Kotagiri FUNC_FC3_b, 74531d6ab3SKavyasree Kotagiri FUNC_FC3_c, 75531d6ab3SKavyasree Kotagiri FUNC_FC4_a, 76531d6ab3SKavyasree Kotagiri FUNC_FC4_b, 77531d6ab3SKavyasree Kotagiri FUNC_FC4_c, 78531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD0, 79531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD1, 80531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD2, 81531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD3, 82531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD4, 83531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD5, 84531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD6, 85531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD7, 86531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD8, 87531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD9, 88531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD10, 89531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD11, 90531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD12, 91531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD13, 92531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD14, 93531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD15, 94531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD16, 95531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD17, 96531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD18, 97531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD19, 98531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD20, 99ce8dc094SAlexandre Belloni FUNC_GPIO, 100531d6ab3SKavyasree Kotagiri FUNC_IB_TRG_a, 101531d6ab3SKavyasree Kotagiri FUNC_IB_TRG_b, 102531d6ab3SKavyasree Kotagiri FUNC_IB_TRG_c, 103f8a74760SLars Povlsen FUNC_IRQ0, 104531d6ab3SKavyasree Kotagiri FUNC_IRQ_IN_a, 105531d6ab3SKavyasree Kotagiri FUNC_IRQ_IN_b, 106531d6ab3SKavyasree Kotagiri FUNC_IRQ_IN_c, 107ce8dc094SAlexandre Belloni FUNC_IRQ0_IN, 108531d6ab3SKavyasree Kotagiri FUNC_IRQ_OUT_a, 109531d6ab3SKavyasree Kotagiri FUNC_IRQ_OUT_b, 110531d6ab3SKavyasree Kotagiri FUNC_IRQ_OUT_c, 111ce8dc094SAlexandre Belloni FUNC_IRQ0_OUT, 112f8a74760SLars Povlsen FUNC_IRQ1, 113ce8dc094SAlexandre Belloni FUNC_IRQ1_IN, 114ce8dc094SAlexandre Belloni FUNC_IRQ1_OUT, 115f8a74760SLars Povlsen FUNC_EXT_IRQ, 116edc72546SLars Povlsen FUNC_MIIM, 117531d6ab3SKavyasree Kotagiri FUNC_MIIM_a, 118531d6ab3SKavyasree Kotagiri FUNC_MIIM_b, 119531d6ab3SKavyasree Kotagiri FUNC_MIIM_c, 120531d6ab3SKavyasree Kotagiri FUNC_MIIM_Sa, 121531d6ab3SKavyasree Kotagiri FUNC_MIIM_Sb, 122531d6ab3SKavyasree Kotagiri FUNC_OB_TRG, 123531d6ab3SKavyasree Kotagiri FUNC_OB_TRG_a, 124531d6ab3SKavyasree Kotagiri FUNC_OB_TRG_b, 125f8a74760SLars Povlsen FUNC_PHY_LED, 126ce8dc094SAlexandre Belloni FUNC_PCI_WAKE, 127f8a74760SLars Povlsen FUNC_MD, 128ce8dc094SAlexandre Belloni FUNC_PTP0, 129ce8dc094SAlexandre Belloni FUNC_PTP1, 130ce8dc094SAlexandre Belloni FUNC_PTP2, 131ce8dc094SAlexandre Belloni FUNC_PTP3, 132*d3683eebSHoratiu Vultur FUNC_PTPSYNC_0, 133531d6ab3SKavyasree Kotagiri FUNC_PTPSYNC_1, 134531d6ab3SKavyasree Kotagiri FUNC_PTPSYNC_2, 135531d6ab3SKavyasree Kotagiri FUNC_PTPSYNC_3, 136531d6ab3SKavyasree Kotagiri FUNC_PTPSYNC_4, 137531d6ab3SKavyasree Kotagiri FUNC_PTPSYNC_5, 138531d6ab3SKavyasree Kotagiri FUNC_PTPSYNC_6, 139531d6ab3SKavyasree Kotagiri FUNC_PTPSYNC_7, 140ce8dc094SAlexandre Belloni FUNC_PWM, 141531d6ab3SKavyasree Kotagiri FUNC_QSPI1, 142531d6ab3SKavyasree Kotagiri FUNC_QSPI2, 143531d6ab3SKavyasree Kotagiri FUNC_R, 144531d6ab3SKavyasree Kotagiri FUNC_RECO_a, 145531d6ab3SKavyasree Kotagiri FUNC_RECO_b, 146edc72546SLars Povlsen FUNC_RECO_CLK, 147531d6ab3SKavyasree Kotagiri FUNC_SD, 148edc72546SLars Povlsen FUNC_SFP, 149531d6ab3SKavyasree Kotagiri FUNC_SFP_SD, 150ce8dc094SAlexandre Belloni FUNC_SG0, 151da801ab5SAlexandre Belloni FUNC_SG1, 152da801ab5SAlexandre Belloni FUNC_SG2, 153531d6ab3SKavyasree Kotagiri FUNC_SGPIO_a, 154531d6ab3SKavyasree Kotagiri FUNC_SGPIO_b, 155ce8dc094SAlexandre Belloni FUNC_SI, 156f8a74760SLars Povlsen FUNC_SI2, 157ce8dc094SAlexandre Belloni FUNC_TACHO, 158531d6ab3SKavyasree Kotagiri FUNC_TACHO_a, 159531d6ab3SKavyasree Kotagiri FUNC_TACHO_b, 160ce8dc094SAlexandre Belloni FUNC_TWI, 161da801ab5SAlexandre Belloni FUNC_TWI2, 162f8a74760SLars Povlsen FUNC_TWI3, 163ce8dc094SAlexandre Belloni FUNC_TWI_SCL_M, 164531d6ab3SKavyasree Kotagiri FUNC_TWI_SLC_GATE, 165531d6ab3SKavyasree Kotagiri FUNC_TWI_SLC_GATE_AD, 166ce8dc094SAlexandre Belloni FUNC_UART, 167ce8dc094SAlexandre Belloni FUNC_UART2, 168f8a74760SLars Povlsen FUNC_UART3, 169531d6ab3SKavyasree Kotagiri FUNC_USB_H_a, 170531d6ab3SKavyasree Kotagiri FUNC_USB_H_b, 171531d6ab3SKavyasree Kotagiri FUNC_USB_H_c, 172531d6ab3SKavyasree Kotagiri FUNC_USB_S_a, 173531d6ab3SKavyasree Kotagiri FUNC_USB_S_b, 174531d6ab3SKavyasree Kotagiri FUNC_USB_S_c, 175f8a74760SLars Povlsen FUNC_PLL_STAT, 176f8a74760SLars Povlsen FUNC_EMMC, 177531d6ab3SKavyasree Kotagiri FUNC_EMMC_SD, 178f8a74760SLars Povlsen FUNC_REF_CLK, 179f8a74760SLars Povlsen FUNC_RCVRD_CLK, 180ce8dc094SAlexandre Belloni FUNC_MAX 181ce8dc094SAlexandre Belloni }; 182ce8dc094SAlexandre Belloni 183ce8dc094SAlexandre Belloni static const char *const ocelot_function_names[] = { 184531d6ab3SKavyasree Kotagiri [FUNC_CAN0_a] = "can0_a", 185531d6ab3SKavyasree Kotagiri [FUNC_CAN0_b] = "can0_b", 186531d6ab3SKavyasree Kotagiri [FUNC_CAN1] = "can1", 187ce8dc094SAlexandre Belloni [FUNC_NONE] = "none", 188531d6ab3SKavyasree Kotagiri [FUNC_FC0_a] = "fc0_a", 189531d6ab3SKavyasree Kotagiri [FUNC_FC0_b] = "fc0_b", 190531d6ab3SKavyasree Kotagiri [FUNC_FC0_c] = "fc0_c", 191531d6ab3SKavyasree Kotagiri [FUNC_FC1_a] = "fc1_a", 192531d6ab3SKavyasree Kotagiri [FUNC_FC1_b] = "fc1_b", 193531d6ab3SKavyasree Kotagiri [FUNC_FC1_c] = "fc1_c", 194531d6ab3SKavyasree Kotagiri [FUNC_FC2_a] = "fc2_a", 195531d6ab3SKavyasree Kotagiri [FUNC_FC2_b] = "fc2_b", 196531d6ab3SKavyasree Kotagiri [FUNC_FC3_a] = "fc3_a", 197531d6ab3SKavyasree Kotagiri [FUNC_FC3_b] = "fc3_b", 198531d6ab3SKavyasree Kotagiri [FUNC_FC3_c] = "fc3_c", 199531d6ab3SKavyasree Kotagiri [FUNC_FC4_a] = "fc4_a", 200531d6ab3SKavyasree Kotagiri [FUNC_FC4_b] = "fc4_b", 201531d6ab3SKavyasree Kotagiri [FUNC_FC4_c] = "fc4_c", 202531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD0] = "fc_shrd0", 203531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD1] = "fc_shrd1", 204531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD2] = "fc_shrd2", 205531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD3] = "fc_shrd3", 206531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD4] = "fc_shrd4", 207531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD5] = "fc_shrd5", 208531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD6] = "fc_shrd6", 209531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD7] = "fc_shrd7", 210531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD8] = "fc_shrd8", 211531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD9] = "fc_shrd9", 212531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD10] = "fc_shrd10", 213531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD11] = "fc_shrd11", 214531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD12] = "fc_shrd12", 215531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD13] = "fc_shrd13", 216531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD14] = "fc_shrd14", 217531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD15] = "fc_shrd15", 218531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD16] = "fc_shrd16", 219531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD17] = "fc_shrd17", 220531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD18] = "fc_shrd18", 221531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD19] = "fc_shrd19", 222531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD20] = "fc_shrd20", 223ce8dc094SAlexandre Belloni [FUNC_GPIO] = "gpio", 224531d6ab3SKavyasree Kotagiri [FUNC_IB_TRG_a] = "ib_trig_a", 225531d6ab3SKavyasree Kotagiri [FUNC_IB_TRG_b] = "ib_trig_b", 226531d6ab3SKavyasree Kotagiri [FUNC_IB_TRG_c] = "ib_trig_c", 227f8a74760SLars Povlsen [FUNC_IRQ0] = "irq0", 228531d6ab3SKavyasree Kotagiri [FUNC_IRQ_IN_a] = "irq_in_a", 229531d6ab3SKavyasree Kotagiri [FUNC_IRQ_IN_b] = "irq_in_b", 230531d6ab3SKavyasree Kotagiri [FUNC_IRQ_IN_c] = "irq_in_c", 231ce8dc094SAlexandre Belloni [FUNC_IRQ0_IN] = "irq0_in", 232531d6ab3SKavyasree Kotagiri [FUNC_IRQ_OUT_a] = "irq_out_a", 233531d6ab3SKavyasree Kotagiri [FUNC_IRQ_OUT_b] = "irq_out_b", 234531d6ab3SKavyasree Kotagiri [FUNC_IRQ_OUT_c] = "irq_out_c", 235ce8dc094SAlexandre Belloni [FUNC_IRQ0_OUT] = "irq0_out", 236f8a74760SLars Povlsen [FUNC_IRQ1] = "irq1", 237ce8dc094SAlexandre Belloni [FUNC_IRQ1_IN] = "irq1_in", 238ce8dc094SAlexandre Belloni [FUNC_IRQ1_OUT] = "irq1_out", 239f8a74760SLars Povlsen [FUNC_EXT_IRQ] = "ext_irq", 240edc72546SLars Povlsen [FUNC_MIIM] = "miim", 241531d6ab3SKavyasree Kotagiri [FUNC_MIIM_a] = "miim_a", 242531d6ab3SKavyasree Kotagiri [FUNC_MIIM_b] = "miim_b", 243531d6ab3SKavyasree Kotagiri [FUNC_MIIM_c] = "miim_c", 244531d6ab3SKavyasree Kotagiri [FUNC_MIIM_Sa] = "miim_slave_a", 245531d6ab3SKavyasree Kotagiri [FUNC_MIIM_Sb] = "miim_slave_b", 246f8a74760SLars Povlsen [FUNC_PHY_LED] = "phy_led", 247ce8dc094SAlexandre Belloni [FUNC_PCI_WAKE] = "pci_wake", 248f8a74760SLars Povlsen [FUNC_MD] = "md", 249531d6ab3SKavyasree Kotagiri [FUNC_OB_TRG] = "ob_trig", 250531d6ab3SKavyasree Kotagiri [FUNC_OB_TRG_a] = "ob_trig_a", 251531d6ab3SKavyasree Kotagiri [FUNC_OB_TRG_b] = "ob_trig_b", 252ce8dc094SAlexandre Belloni [FUNC_PTP0] = "ptp0", 253ce8dc094SAlexandre Belloni [FUNC_PTP1] = "ptp1", 254ce8dc094SAlexandre Belloni [FUNC_PTP2] = "ptp2", 255ce8dc094SAlexandre Belloni [FUNC_PTP3] = "ptp3", 256*d3683eebSHoratiu Vultur [FUNC_PTPSYNC_0] = "ptpsync_0", 257531d6ab3SKavyasree Kotagiri [FUNC_PTPSYNC_1] = "ptpsync_1", 258531d6ab3SKavyasree Kotagiri [FUNC_PTPSYNC_2] = "ptpsync_2", 259531d6ab3SKavyasree Kotagiri [FUNC_PTPSYNC_3] = "ptpsync_3", 260531d6ab3SKavyasree Kotagiri [FUNC_PTPSYNC_4] = "ptpsync_4", 261531d6ab3SKavyasree Kotagiri [FUNC_PTPSYNC_5] = "ptpsync_5", 262531d6ab3SKavyasree Kotagiri [FUNC_PTPSYNC_6] = "ptpsync_6", 263531d6ab3SKavyasree Kotagiri [FUNC_PTPSYNC_7] = "ptpsync_7", 264ce8dc094SAlexandre Belloni [FUNC_PWM] = "pwm", 265531d6ab3SKavyasree Kotagiri [FUNC_QSPI1] = "qspi1", 266531d6ab3SKavyasree Kotagiri [FUNC_QSPI2] = "qspi2", 267531d6ab3SKavyasree Kotagiri [FUNC_R] = "reserved", 268531d6ab3SKavyasree Kotagiri [FUNC_RECO_a] = "reco_a", 269531d6ab3SKavyasree Kotagiri [FUNC_RECO_b] = "reco_b", 270edc72546SLars Povlsen [FUNC_RECO_CLK] = "reco_clk", 271531d6ab3SKavyasree Kotagiri [FUNC_SD] = "sd", 272edc72546SLars Povlsen [FUNC_SFP] = "sfp", 273531d6ab3SKavyasree Kotagiri [FUNC_SFP_SD] = "sfp_sd", 274ce8dc094SAlexandre Belloni [FUNC_SG0] = "sg0", 275da801ab5SAlexandre Belloni [FUNC_SG1] = "sg1", 276da801ab5SAlexandre Belloni [FUNC_SG2] = "sg2", 277531d6ab3SKavyasree Kotagiri [FUNC_SGPIO_a] = "sgpio_a", 278531d6ab3SKavyasree Kotagiri [FUNC_SGPIO_b] = "sgpio_b", 279ce8dc094SAlexandre Belloni [FUNC_SI] = "si", 280f8a74760SLars Povlsen [FUNC_SI2] = "si2", 281ce8dc094SAlexandre Belloni [FUNC_TACHO] = "tacho", 282531d6ab3SKavyasree Kotagiri [FUNC_TACHO_a] = "tacho_a", 283531d6ab3SKavyasree Kotagiri [FUNC_TACHO_b] = "tacho_b", 284ce8dc094SAlexandre Belloni [FUNC_TWI] = "twi", 285da801ab5SAlexandre Belloni [FUNC_TWI2] = "twi2", 286f8a74760SLars Povlsen [FUNC_TWI3] = "twi3", 287ce8dc094SAlexandre Belloni [FUNC_TWI_SCL_M] = "twi_scl_m", 288531d6ab3SKavyasree Kotagiri [FUNC_TWI_SLC_GATE] = "twi_slc_gate", 289531d6ab3SKavyasree Kotagiri [FUNC_TWI_SLC_GATE_AD] = "twi_slc_gate_ad", 290531d6ab3SKavyasree Kotagiri [FUNC_USB_H_a] = "usb_host_a", 291531d6ab3SKavyasree Kotagiri [FUNC_USB_H_b] = "usb_host_b", 292531d6ab3SKavyasree Kotagiri [FUNC_USB_H_c] = "usb_host_c", 293531d6ab3SKavyasree Kotagiri [FUNC_USB_S_a] = "usb_slave_a", 294531d6ab3SKavyasree Kotagiri [FUNC_USB_S_b] = "usb_slave_b", 295531d6ab3SKavyasree Kotagiri [FUNC_USB_S_c] = "usb_slave_c", 296ce8dc094SAlexandre Belloni [FUNC_UART] = "uart", 297ce8dc094SAlexandre Belloni [FUNC_UART2] = "uart2", 298f8a74760SLars Povlsen [FUNC_UART3] = "uart3", 299f8a74760SLars Povlsen [FUNC_PLL_STAT] = "pll_stat", 300f8a74760SLars Povlsen [FUNC_EMMC] = "emmc", 301531d6ab3SKavyasree Kotagiri [FUNC_EMMC_SD] = "emmc_sd", 302f8a74760SLars Povlsen [FUNC_REF_CLK] = "ref_clk", 303f8a74760SLars Povlsen [FUNC_RCVRD_CLK] = "rcvrd_clk", 304ce8dc094SAlexandre Belloni }; 305ce8dc094SAlexandre Belloni 306ce8dc094SAlexandre Belloni struct ocelot_pmx_func { 307ce8dc094SAlexandre Belloni const char **groups; 308ce8dc094SAlexandre Belloni unsigned int ngroups; 309ce8dc094SAlexandre Belloni }; 310ce8dc094SAlexandre Belloni 311ce8dc094SAlexandre Belloni struct ocelot_pin_caps { 312ce8dc094SAlexandre Belloni unsigned int pin; 313ce8dc094SAlexandre Belloni unsigned char functions[OCELOT_FUNC_PER_PIN]; 314531d6ab3SKavyasree Kotagiri unsigned char a_functions[OCELOT_FUNC_PER_PIN]; /* Additional functions */ 315ce8dc094SAlexandre Belloni }; 316ce8dc094SAlexandre Belloni 317ce8dc094SAlexandre Belloni struct ocelot_pinctrl { 318ce8dc094SAlexandre Belloni struct device *dev; 319ce8dc094SAlexandre Belloni struct pinctrl_dev *pctl; 320ce8dc094SAlexandre Belloni struct gpio_chip gpio_chip; 321ce8dc094SAlexandre Belloni struct regmap *map; 322076d9e71SColin Foster struct regmap *pincfg; 323da801ab5SAlexandre Belloni struct pinctrl_desc *desc; 324ce8dc094SAlexandre Belloni struct ocelot_pmx_func func[FUNC_MAX]; 325da801ab5SAlexandre Belloni u8 stride; 326ce8dc094SAlexandre Belloni }; 327ce8dc094SAlexandre Belloni 3288f27440dSLars Povlsen #define LUTON_P(p, f0, f1) \ 3298f27440dSLars Povlsen static struct ocelot_pin_caps luton_pin_##p = { \ 3308f27440dSLars Povlsen .pin = p, \ 3318f27440dSLars Povlsen .functions = { \ 3328f27440dSLars Povlsen FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_NONE, \ 3338f27440dSLars Povlsen }, \ 3348f27440dSLars Povlsen } 3358f27440dSLars Povlsen 3368f27440dSLars Povlsen LUTON_P(0, SG0, NONE); 3378f27440dSLars Povlsen LUTON_P(1, SG0, NONE); 3388f27440dSLars Povlsen LUTON_P(2, SG0, NONE); 3398f27440dSLars Povlsen LUTON_P(3, SG0, NONE); 3408f27440dSLars Povlsen LUTON_P(4, TACHO, NONE); 3418f27440dSLars Povlsen LUTON_P(5, TWI, PHY_LED); 3428f27440dSLars Povlsen LUTON_P(6, TWI, PHY_LED); 3438f27440dSLars Povlsen LUTON_P(7, NONE, PHY_LED); 3448f27440dSLars Povlsen LUTON_P(8, EXT_IRQ, PHY_LED); 3458f27440dSLars Povlsen LUTON_P(9, EXT_IRQ, PHY_LED); 3468f27440dSLars Povlsen LUTON_P(10, SFP, PHY_LED); 3478f27440dSLars Povlsen LUTON_P(11, SFP, PHY_LED); 3488f27440dSLars Povlsen LUTON_P(12, SFP, PHY_LED); 3498f27440dSLars Povlsen LUTON_P(13, SFP, PHY_LED); 3508f27440dSLars Povlsen LUTON_P(14, SI, PHY_LED); 3518f27440dSLars Povlsen LUTON_P(15, SI, PHY_LED); 3528f27440dSLars Povlsen LUTON_P(16, SI, PHY_LED); 3538f27440dSLars Povlsen LUTON_P(17, SFP, PHY_LED); 3548f27440dSLars Povlsen LUTON_P(18, SFP, PHY_LED); 3558f27440dSLars Povlsen LUTON_P(19, SFP, PHY_LED); 3568f27440dSLars Povlsen LUTON_P(20, SFP, PHY_LED); 3578f27440dSLars Povlsen LUTON_P(21, SFP, PHY_LED); 3588f27440dSLars Povlsen LUTON_P(22, SFP, PHY_LED); 3598f27440dSLars Povlsen LUTON_P(23, SFP, PHY_LED); 3608f27440dSLars Povlsen LUTON_P(24, SFP, PHY_LED); 3618f27440dSLars Povlsen LUTON_P(25, SFP, PHY_LED); 3628f27440dSLars Povlsen LUTON_P(26, SFP, PHY_LED); 3638f27440dSLars Povlsen LUTON_P(27, SFP, PHY_LED); 3648f27440dSLars Povlsen LUTON_P(28, SFP, PHY_LED); 3658f27440dSLars Povlsen LUTON_P(29, PWM, NONE); 3668f27440dSLars Povlsen LUTON_P(30, UART, NONE); 3678f27440dSLars Povlsen LUTON_P(31, UART, NONE); 3688f27440dSLars Povlsen 3698f27440dSLars Povlsen #define LUTON_PIN(n) { \ 3708f27440dSLars Povlsen .number = n, \ 3718f27440dSLars Povlsen .name = "GPIO_"#n, \ 3728f27440dSLars Povlsen .drv_data = &luton_pin_##n \ 3738f27440dSLars Povlsen } 3748f27440dSLars Povlsen 3758f27440dSLars Povlsen static const struct pinctrl_pin_desc luton_pins[] = { 3768f27440dSLars Povlsen LUTON_PIN(0), 3778f27440dSLars Povlsen LUTON_PIN(1), 3788f27440dSLars Povlsen LUTON_PIN(2), 3798f27440dSLars Povlsen LUTON_PIN(3), 3808f27440dSLars Povlsen LUTON_PIN(4), 3818f27440dSLars Povlsen LUTON_PIN(5), 3828f27440dSLars Povlsen LUTON_PIN(6), 3838f27440dSLars Povlsen LUTON_PIN(7), 3848f27440dSLars Povlsen LUTON_PIN(8), 3858f27440dSLars Povlsen LUTON_PIN(9), 3868f27440dSLars Povlsen LUTON_PIN(10), 3878f27440dSLars Povlsen LUTON_PIN(11), 3888f27440dSLars Povlsen LUTON_PIN(12), 3898f27440dSLars Povlsen LUTON_PIN(13), 3908f27440dSLars Povlsen LUTON_PIN(14), 3918f27440dSLars Povlsen LUTON_PIN(15), 3928f27440dSLars Povlsen LUTON_PIN(16), 3938f27440dSLars Povlsen LUTON_PIN(17), 3948f27440dSLars Povlsen LUTON_PIN(18), 3958f27440dSLars Povlsen LUTON_PIN(19), 3968f27440dSLars Povlsen LUTON_PIN(20), 3978f27440dSLars Povlsen LUTON_PIN(21), 3988f27440dSLars Povlsen LUTON_PIN(22), 3998f27440dSLars Povlsen LUTON_PIN(23), 4008f27440dSLars Povlsen LUTON_PIN(24), 4018f27440dSLars Povlsen LUTON_PIN(25), 4028f27440dSLars Povlsen LUTON_PIN(26), 4038f27440dSLars Povlsen LUTON_PIN(27), 4048f27440dSLars Povlsen LUTON_PIN(28), 4058f27440dSLars Povlsen LUTON_PIN(29), 4068f27440dSLars Povlsen LUTON_PIN(30), 4078f27440dSLars Povlsen LUTON_PIN(31), 4088f27440dSLars Povlsen }; 4098f27440dSLars Povlsen 4106e6347e2SLars Povlsen #define SERVAL_P(p, f0, f1, f2) \ 4116e6347e2SLars Povlsen static struct ocelot_pin_caps serval_pin_##p = { \ 4126e6347e2SLars Povlsen .pin = p, \ 4136e6347e2SLars Povlsen .functions = { \ 4146e6347e2SLars Povlsen FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2, \ 4156e6347e2SLars Povlsen }, \ 4166e6347e2SLars Povlsen } 4176e6347e2SLars Povlsen 4186e6347e2SLars Povlsen SERVAL_P(0, SG0, NONE, NONE); 4196e6347e2SLars Povlsen SERVAL_P(1, SG0, NONE, NONE); 4206e6347e2SLars Povlsen SERVAL_P(2, SG0, NONE, NONE); 4216e6347e2SLars Povlsen SERVAL_P(3, SG0, NONE, NONE); 4226e6347e2SLars Povlsen SERVAL_P(4, TACHO, NONE, NONE); 4236e6347e2SLars Povlsen SERVAL_P(5, PWM, NONE, NONE); 4246e6347e2SLars Povlsen SERVAL_P(6, TWI, NONE, NONE); 4256e6347e2SLars Povlsen SERVAL_P(7, TWI, NONE, NONE); 4266e6347e2SLars Povlsen SERVAL_P(8, SI, NONE, NONE); 4276e6347e2SLars Povlsen SERVAL_P(9, SI, MD, NONE); 4286e6347e2SLars Povlsen SERVAL_P(10, SI, MD, NONE); 4296e6347e2SLars Povlsen SERVAL_P(11, SFP, MD, TWI_SCL_M); 4306e6347e2SLars Povlsen SERVAL_P(12, SFP, MD, TWI_SCL_M); 4316e6347e2SLars Povlsen SERVAL_P(13, SFP, UART2, TWI_SCL_M); 4326e6347e2SLars Povlsen SERVAL_P(14, SFP, UART2, TWI_SCL_M); 4336e6347e2SLars Povlsen SERVAL_P(15, SFP, PTP0, TWI_SCL_M); 4346e6347e2SLars Povlsen SERVAL_P(16, SFP, PTP0, TWI_SCL_M); 4356e6347e2SLars Povlsen SERVAL_P(17, SFP, PCI_WAKE, TWI_SCL_M); 4366e6347e2SLars Povlsen SERVAL_P(18, SFP, NONE, TWI_SCL_M); 4376e6347e2SLars Povlsen SERVAL_P(19, SFP, NONE, TWI_SCL_M); 4386e6347e2SLars Povlsen SERVAL_P(20, SFP, NONE, TWI_SCL_M); 4396e6347e2SLars Povlsen SERVAL_P(21, SFP, NONE, TWI_SCL_M); 4406e6347e2SLars Povlsen SERVAL_P(22, NONE, NONE, NONE); 4416e6347e2SLars Povlsen SERVAL_P(23, NONE, NONE, NONE); 4426e6347e2SLars Povlsen SERVAL_P(24, NONE, NONE, NONE); 4436e6347e2SLars Povlsen SERVAL_P(25, NONE, NONE, NONE); 4446e6347e2SLars Povlsen SERVAL_P(26, UART, NONE, NONE); 4456e6347e2SLars Povlsen SERVAL_P(27, UART, NONE, NONE); 4466e6347e2SLars Povlsen SERVAL_P(28, IRQ0, NONE, NONE); 4476e6347e2SLars Povlsen SERVAL_P(29, IRQ1, NONE, NONE); 4486e6347e2SLars Povlsen SERVAL_P(30, PTP0, NONE, NONE); 4496e6347e2SLars Povlsen SERVAL_P(31, PTP0, NONE, NONE); 4506e6347e2SLars Povlsen 4516e6347e2SLars Povlsen #define SERVAL_PIN(n) { \ 4526e6347e2SLars Povlsen .number = n, \ 4536e6347e2SLars Povlsen .name = "GPIO_"#n, \ 4546e6347e2SLars Povlsen .drv_data = &serval_pin_##n \ 4556e6347e2SLars Povlsen } 4566e6347e2SLars Povlsen 4576e6347e2SLars Povlsen static const struct pinctrl_pin_desc serval_pins[] = { 4586e6347e2SLars Povlsen SERVAL_PIN(0), 4596e6347e2SLars Povlsen SERVAL_PIN(1), 4606e6347e2SLars Povlsen SERVAL_PIN(2), 4616e6347e2SLars Povlsen SERVAL_PIN(3), 4626e6347e2SLars Povlsen SERVAL_PIN(4), 4636e6347e2SLars Povlsen SERVAL_PIN(5), 4646e6347e2SLars Povlsen SERVAL_PIN(6), 4656e6347e2SLars Povlsen SERVAL_PIN(7), 4666e6347e2SLars Povlsen SERVAL_PIN(8), 4676e6347e2SLars Povlsen SERVAL_PIN(9), 4686e6347e2SLars Povlsen SERVAL_PIN(10), 4696e6347e2SLars Povlsen SERVAL_PIN(11), 4706e6347e2SLars Povlsen SERVAL_PIN(12), 4716e6347e2SLars Povlsen SERVAL_PIN(13), 4726e6347e2SLars Povlsen SERVAL_PIN(14), 4736e6347e2SLars Povlsen SERVAL_PIN(15), 4746e6347e2SLars Povlsen SERVAL_PIN(16), 4756e6347e2SLars Povlsen SERVAL_PIN(17), 4766e6347e2SLars Povlsen SERVAL_PIN(18), 4776e6347e2SLars Povlsen SERVAL_PIN(19), 4786e6347e2SLars Povlsen SERVAL_PIN(20), 4796e6347e2SLars Povlsen SERVAL_PIN(21), 4806e6347e2SLars Povlsen SERVAL_PIN(22), 4816e6347e2SLars Povlsen SERVAL_PIN(23), 4826e6347e2SLars Povlsen SERVAL_PIN(24), 4836e6347e2SLars Povlsen SERVAL_PIN(25), 4846e6347e2SLars Povlsen SERVAL_PIN(26), 4856e6347e2SLars Povlsen SERVAL_PIN(27), 4866e6347e2SLars Povlsen SERVAL_PIN(28), 4876e6347e2SLars Povlsen SERVAL_PIN(29), 4886e6347e2SLars Povlsen SERVAL_PIN(30), 4896e6347e2SLars Povlsen SERVAL_PIN(31), 4906e6347e2SLars Povlsen }; 4916e6347e2SLars Povlsen 492ce8dc094SAlexandre Belloni #define OCELOT_P(p, f0, f1, f2) \ 493ce8dc094SAlexandre Belloni static struct ocelot_pin_caps ocelot_pin_##p = { \ 494ce8dc094SAlexandre Belloni .pin = p, \ 495ce8dc094SAlexandre Belloni .functions = { \ 496ce8dc094SAlexandre Belloni FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2, \ 497ce8dc094SAlexandre Belloni }, \ 498ce8dc094SAlexandre Belloni } 499ce8dc094SAlexandre Belloni 500ce8dc094SAlexandre Belloni OCELOT_P(0, SG0, NONE, NONE); 501ce8dc094SAlexandre Belloni OCELOT_P(1, SG0, NONE, NONE); 502ce8dc094SAlexandre Belloni OCELOT_P(2, SG0, NONE, NONE); 503ce8dc094SAlexandre Belloni OCELOT_P(3, SG0, NONE, NONE); 50417f79084SAlexandre Belloni OCELOT_P(4, IRQ0_IN, IRQ0_OUT, TWI_SCL_M); 505ce8dc094SAlexandre Belloni OCELOT_P(5, IRQ1_IN, IRQ1_OUT, PCI_WAKE); 506ce8dc094SAlexandre Belloni OCELOT_P(6, UART, TWI_SCL_M, NONE); 507ce8dc094SAlexandre Belloni OCELOT_P(7, UART, TWI_SCL_M, NONE); 508ce8dc094SAlexandre Belloni OCELOT_P(8, SI, TWI_SCL_M, IRQ0_OUT); 509ce8dc094SAlexandre Belloni OCELOT_P(9, SI, TWI_SCL_M, IRQ1_OUT); 510edc72546SLars Povlsen OCELOT_P(10, PTP2, TWI_SCL_M, SFP); 511edc72546SLars Povlsen OCELOT_P(11, PTP3, TWI_SCL_M, SFP); 512edc72546SLars Povlsen OCELOT_P(12, UART2, TWI_SCL_M, SFP); 513edc72546SLars Povlsen OCELOT_P(13, UART2, TWI_SCL_M, SFP); 514edc72546SLars Povlsen OCELOT_P(14, MIIM, TWI_SCL_M, SFP); 515edc72546SLars Povlsen OCELOT_P(15, MIIM, TWI_SCL_M, SFP); 516ce8dc094SAlexandre Belloni OCELOT_P(16, TWI, NONE, SI); 517ce8dc094SAlexandre Belloni OCELOT_P(17, TWI, TWI_SCL_M, SI); 518ce8dc094SAlexandre Belloni OCELOT_P(18, PTP0, TWI_SCL_M, NONE); 519ce8dc094SAlexandre Belloni OCELOT_P(19, PTP1, TWI_SCL_M, NONE); 520edc72546SLars Povlsen OCELOT_P(20, RECO_CLK, TACHO, TWI_SCL_M); 521edc72546SLars Povlsen OCELOT_P(21, RECO_CLK, PWM, TWI_SCL_M); 522ce8dc094SAlexandre Belloni 523ce8dc094SAlexandre Belloni #define OCELOT_PIN(n) { \ 524ce8dc094SAlexandre Belloni .number = n, \ 525ce8dc094SAlexandre Belloni .name = "GPIO_"#n, \ 526ce8dc094SAlexandre Belloni .drv_data = &ocelot_pin_##n \ 527ce8dc094SAlexandre Belloni } 528ce8dc094SAlexandre Belloni 529ce8dc094SAlexandre Belloni static const struct pinctrl_pin_desc ocelot_pins[] = { 530ce8dc094SAlexandre Belloni OCELOT_PIN(0), 531ce8dc094SAlexandre Belloni OCELOT_PIN(1), 532ce8dc094SAlexandre Belloni OCELOT_PIN(2), 533ce8dc094SAlexandre Belloni OCELOT_PIN(3), 534ce8dc094SAlexandre Belloni OCELOT_PIN(4), 535ce8dc094SAlexandre Belloni OCELOT_PIN(5), 536ce8dc094SAlexandre Belloni OCELOT_PIN(6), 537ce8dc094SAlexandre Belloni OCELOT_PIN(7), 538ce8dc094SAlexandre Belloni OCELOT_PIN(8), 539ce8dc094SAlexandre Belloni OCELOT_PIN(9), 540ce8dc094SAlexandre Belloni OCELOT_PIN(10), 541ce8dc094SAlexandre Belloni OCELOT_PIN(11), 542ce8dc094SAlexandre Belloni OCELOT_PIN(12), 543ce8dc094SAlexandre Belloni OCELOT_PIN(13), 544ce8dc094SAlexandre Belloni OCELOT_PIN(14), 545ce8dc094SAlexandre Belloni OCELOT_PIN(15), 546ce8dc094SAlexandre Belloni OCELOT_PIN(16), 547ce8dc094SAlexandre Belloni OCELOT_PIN(17), 548ce8dc094SAlexandre Belloni OCELOT_PIN(18), 549ce8dc094SAlexandre Belloni OCELOT_PIN(19), 550ce8dc094SAlexandre Belloni OCELOT_PIN(20), 551ce8dc094SAlexandre Belloni OCELOT_PIN(21), 552ce8dc094SAlexandre Belloni }; 553ce8dc094SAlexandre Belloni 554da801ab5SAlexandre Belloni #define JAGUAR2_P(p, f0, f1) \ 555da801ab5SAlexandre Belloni static struct ocelot_pin_caps jaguar2_pin_##p = { \ 556da801ab5SAlexandre Belloni .pin = p, \ 557da801ab5SAlexandre Belloni .functions = { \ 558da801ab5SAlexandre Belloni FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_NONE \ 559da801ab5SAlexandre Belloni }, \ 560da801ab5SAlexandre Belloni } 561da801ab5SAlexandre Belloni 562da801ab5SAlexandre Belloni JAGUAR2_P(0, SG0, NONE); 563da801ab5SAlexandre Belloni JAGUAR2_P(1, SG0, NONE); 564da801ab5SAlexandre Belloni JAGUAR2_P(2, SG0, NONE); 565da801ab5SAlexandre Belloni JAGUAR2_P(3, SG0, NONE); 566da801ab5SAlexandre Belloni JAGUAR2_P(4, SG1, NONE); 567da801ab5SAlexandre Belloni JAGUAR2_P(5, SG1, NONE); 568da801ab5SAlexandre Belloni JAGUAR2_P(6, IRQ0_IN, IRQ0_OUT); 569da801ab5SAlexandre Belloni JAGUAR2_P(7, IRQ1_IN, IRQ1_OUT); 570da801ab5SAlexandre Belloni JAGUAR2_P(8, PTP0, NONE); 571da801ab5SAlexandre Belloni JAGUAR2_P(9, PTP1, NONE); 572da801ab5SAlexandre Belloni JAGUAR2_P(10, UART, NONE); 573da801ab5SAlexandre Belloni JAGUAR2_P(11, UART, NONE); 574da801ab5SAlexandre Belloni JAGUAR2_P(12, SG1, NONE); 575da801ab5SAlexandre Belloni JAGUAR2_P(13, SG1, NONE); 576da801ab5SAlexandre Belloni JAGUAR2_P(14, TWI, TWI_SCL_M); 577da801ab5SAlexandre Belloni JAGUAR2_P(15, TWI, NONE); 578da801ab5SAlexandre Belloni JAGUAR2_P(16, SI, TWI_SCL_M); 579da801ab5SAlexandre Belloni JAGUAR2_P(17, SI, TWI_SCL_M); 580da801ab5SAlexandre Belloni JAGUAR2_P(18, SI, TWI_SCL_M); 581da801ab5SAlexandre Belloni JAGUAR2_P(19, PCI_WAKE, NONE); 582da801ab5SAlexandre Belloni JAGUAR2_P(20, IRQ0_OUT, TWI_SCL_M); 583da801ab5SAlexandre Belloni JAGUAR2_P(21, IRQ1_OUT, TWI_SCL_M); 584da801ab5SAlexandre Belloni JAGUAR2_P(22, TACHO, NONE); 585da801ab5SAlexandre Belloni JAGUAR2_P(23, PWM, NONE); 586da801ab5SAlexandre Belloni JAGUAR2_P(24, UART2, NONE); 587da801ab5SAlexandre Belloni JAGUAR2_P(25, UART2, SI); 588da801ab5SAlexandre Belloni JAGUAR2_P(26, PTP2, SI); 589da801ab5SAlexandre Belloni JAGUAR2_P(27, PTP3, SI); 590da801ab5SAlexandre Belloni JAGUAR2_P(28, TWI2, SI); 591da801ab5SAlexandre Belloni JAGUAR2_P(29, TWI2, SI); 592da801ab5SAlexandre Belloni JAGUAR2_P(30, SG2, SI); 593da801ab5SAlexandre Belloni JAGUAR2_P(31, SG2, SI); 594da801ab5SAlexandre Belloni JAGUAR2_P(32, SG2, SI); 595da801ab5SAlexandre Belloni JAGUAR2_P(33, SG2, SI); 596da801ab5SAlexandre Belloni JAGUAR2_P(34, NONE, TWI_SCL_M); 597da801ab5SAlexandre Belloni JAGUAR2_P(35, NONE, TWI_SCL_M); 598da801ab5SAlexandre Belloni JAGUAR2_P(36, NONE, TWI_SCL_M); 599da801ab5SAlexandre Belloni JAGUAR2_P(37, NONE, TWI_SCL_M); 600da801ab5SAlexandre Belloni JAGUAR2_P(38, NONE, TWI_SCL_M); 601da801ab5SAlexandre Belloni JAGUAR2_P(39, NONE, TWI_SCL_M); 602da801ab5SAlexandre Belloni JAGUAR2_P(40, NONE, TWI_SCL_M); 603da801ab5SAlexandre Belloni JAGUAR2_P(41, NONE, TWI_SCL_M); 604da801ab5SAlexandre Belloni JAGUAR2_P(42, NONE, TWI_SCL_M); 605da801ab5SAlexandre Belloni JAGUAR2_P(43, NONE, TWI_SCL_M); 606edc72546SLars Povlsen JAGUAR2_P(44, NONE, SFP); 607edc72546SLars Povlsen JAGUAR2_P(45, NONE, SFP); 608edc72546SLars Povlsen JAGUAR2_P(46, NONE, SFP); 609edc72546SLars Povlsen JAGUAR2_P(47, NONE, SFP); 610edc72546SLars Povlsen JAGUAR2_P(48, SFP, NONE); 611edc72546SLars Povlsen JAGUAR2_P(49, SFP, SI); 612edc72546SLars Povlsen JAGUAR2_P(50, SFP, SI); 613edc72546SLars Povlsen JAGUAR2_P(51, SFP, SI); 614edc72546SLars Povlsen JAGUAR2_P(52, SFP, NONE); 615edc72546SLars Povlsen JAGUAR2_P(53, SFP, NONE); 616edc72546SLars Povlsen JAGUAR2_P(54, SFP, NONE); 617edc72546SLars Povlsen JAGUAR2_P(55, SFP, NONE); 618edc72546SLars Povlsen JAGUAR2_P(56, MIIM, SFP); 619edc72546SLars Povlsen JAGUAR2_P(57, MIIM, SFP); 620edc72546SLars Povlsen JAGUAR2_P(58, MIIM, SFP); 621edc72546SLars Povlsen JAGUAR2_P(59, MIIM, SFP); 622da801ab5SAlexandre Belloni JAGUAR2_P(60, NONE, NONE); 623da801ab5SAlexandre Belloni JAGUAR2_P(61, NONE, NONE); 624da801ab5SAlexandre Belloni JAGUAR2_P(62, NONE, NONE); 625da801ab5SAlexandre Belloni JAGUAR2_P(63, NONE, NONE); 626da801ab5SAlexandre Belloni 627da801ab5SAlexandre Belloni #define JAGUAR2_PIN(n) { \ 628da801ab5SAlexandre Belloni .number = n, \ 629da801ab5SAlexandre Belloni .name = "GPIO_"#n, \ 630da801ab5SAlexandre Belloni .drv_data = &jaguar2_pin_##n \ 631da801ab5SAlexandre Belloni } 632da801ab5SAlexandre Belloni 633da801ab5SAlexandre Belloni static const struct pinctrl_pin_desc jaguar2_pins[] = { 634da801ab5SAlexandre Belloni JAGUAR2_PIN(0), 635da801ab5SAlexandre Belloni JAGUAR2_PIN(1), 636da801ab5SAlexandre Belloni JAGUAR2_PIN(2), 637da801ab5SAlexandre Belloni JAGUAR2_PIN(3), 638da801ab5SAlexandre Belloni JAGUAR2_PIN(4), 639da801ab5SAlexandre Belloni JAGUAR2_PIN(5), 640da801ab5SAlexandre Belloni JAGUAR2_PIN(6), 641da801ab5SAlexandre Belloni JAGUAR2_PIN(7), 642da801ab5SAlexandre Belloni JAGUAR2_PIN(8), 643da801ab5SAlexandre Belloni JAGUAR2_PIN(9), 644da801ab5SAlexandre Belloni JAGUAR2_PIN(10), 645da801ab5SAlexandre Belloni JAGUAR2_PIN(11), 646da801ab5SAlexandre Belloni JAGUAR2_PIN(12), 647da801ab5SAlexandre Belloni JAGUAR2_PIN(13), 648da801ab5SAlexandre Belloni JAGUAR2_PIN(14), 649da801ab5SAlexandre Belloni JAGUAR2_PIN(15), 650da801ab5SAlexandre Belloni JAGUAR2_PIN(16), 651da801ab5SAlexandre Belloni JAGUAR2_PIN(17), 652da801ab5SAlexandre Belloni JAGUAR2_PIN(18), 653da801ab5SAlexandre Belloni JAGUAR2_PIN(19), 654da801ab5SAlexandre Belloni JAGUAR2_PIN(20), 655da801ab5SAlexandre Belloni JAGUAR2_PIN(21), 656da801ab5SAlexandre Belloni JAGUAR2_PIN(22), 657da801ab5SAlexandre Belloni JAGUAR2_PIN(23), 658da801ab5SAlexandre Belloni JAGUAR2_PIN(24), 659da801ab5SAlexandre Belloni JAGUAR2_PIN(25), 660da801ab5SAlexandre Belloni JAGUAR2_PIN(26), 661da801ab5SAlexandre Belloni JAGUAR2_PIN(27), 662da801ab5SAlexandre Belloni JAGUAR2_PIN(28), 663da801ab5SAlexandre Belloni JAGUAR2_PIN(29), 664da801ab5SAlexandre Belloni JAGUAR2_PIN(30), 665da801ab5SAlexandre Belloni JAGUAR2_PIN(31), 666da801ab5SAlexandre Belloni JAGUAR2_PIN(32), 667da801ab5SAlexandre Belloni JAGUAR2_PIN(33), 668da801ab5SAlexandre Belloni JAGUAR2_PIN(34), 669da801ab5SAlexandre Belloni JAGUAR2_PIN(35), 670da801ab5SAlexandre Belloni JAGUAR2_PIN(36), 671da801ab5SAlexandre Belloni JAGUAR2_PIN(37), 672da801ab5SAlexandre Belloni JAGUAR2_PIN(38), 673da801ab5SAlexandre Belloni JAGUAR2_PIN(39), 674da801ab5SAlexandre Belloni JAGUAR2_PIN(40), 675da801ab5SAlexandre Belloni JAGUAR2_PIN(41), 676da801ab5SAlexandre Belloni JAGUAR2_PIN(42), 677da801ab5SAlexandre Belloni JAGUAR2_PIN(43), 678da801ab5SAlexandre Belloni JAGUAR2_PIN(44), 679da801ab5SAlexandre Belloni JAGUAR2_PIN(45), 680da801ab5SAlexandre Belloni JAGUAR2_PIN(46), 681da801ab5SAlexandre Belloni JAGUAR2_PIN(47), 682da801ab5SAlexandre Belloni JAGUAR2_PIN(48), 683da801ab5SAlexandre Belloni JAGUAR2_PIN(49), 684da801ab5SAlexandre Belloni JAGUAR2_PIN(50), 685da801ab5SAlexandre Belloni JAGUAR2_PIN(51), 686da801ab5SAlexandre Belloni JAGUAR2_PIN(52), 687da801ab5SAlexandre Belloni JAGUAR2_PIN(53), 688da801ab5SAlexandre Belloni JAGUAR2_PIN(54), 689da801ab5SAlexandre Belloni JAGUAR2_PIN(55), 690da801ab5SAlexandre Belloni JAGUAR2_PIN(56), 691da801ab5SAlexandre Belloni JAGUAR2_PIN(57), 692da801ab5SAlexandre Belloni JAGUAR2_PIN(58), 693da801ab5SAlexandre Belloni JAGUAR2_PIN(59), 694da801ab5SAlexandre Belloni JAGUAR2_PIN(60), 695da801ab5SAlexandre Belloni JAGUAR2_PIN(61), 696da801ab5SAlexandre Belloni JAGUAR2_PIN(62), 697da801ab5SAlexandre Belloni JAGUAR2_PIN(63), 698da801ab5SAlexandre Belloni }; 699da801ab5SAlexandre Belloni 7008fc0bfcdSHoratiu Vultur #define SERVALT_P(p, f0, f1, f2) \ 7018fc0bfcdSHoratiu Vultur static struct ocelot_pin_caps servalt_pin_##p = { \ 7028fc0bfcdSHoratiu Vultur .pin = p, \ 7038fc0bfcdSHoratiu Vultur .functions = { \ 7048fc0bfcdSHoratiu Vultur FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2 \ 7058fc0bfcdSHoratiu Vultur }, \ 7068fc0bfcdSHoratiu Vultur } 7078fc0bfcdSHoratiu Vultur 7088fc0bfcdSHoratiu Vultur SERVALT_P(0, SG0, NONE, NONE); 7098fc0bfcdSHoratiu Vultur SERVALT_P(1, SG0, NONE, NONE); 7108fc0bfcdSHoratiu Vultur SERVALT_P(2, SG0, NONE, NONE); 7118fc0bfcdSHoratiu Vultur SERVALT_P(3, SG0, NONE, NONE); 7128fc0bfcdSHoratiu Vultur SERVALT_P(4, IRQ0_IN, IRQ0_OUT, TWI_SCL_M); 7138fc0bfcdSHoratiu Vultur SERVALT_P(5, IRQ1_IN, IRQ1_OUT, TWI_SCL_M); 7148fc0bfcdSHoratiu Vultur SERVALT_P(6, UART, NONE, NONE); 7158fc0bfcdSHoratiu Vultur SERVALT_P(7, UART, NONE, NONE); 7168fc0bfcdSHoratiu Vultur SERVALT_P(8, SI, SFP, TWI_SCL_M); 7178fc0bfcdSHoratiu Vultur SERVALT_P(9, PCI_WAKE, SFP, SI); 7188fc0bfcdSHoratiu Vultur SERVALT_P(10, PTP0, SFP, TWI_SCL_M); 7198fc0bfcdSHoratiu Vultur SERVALT_P(11, PTP1, SFP, TWI_SCL_M); 7208fc0bfcdSHoratiu Vultur SERVALT_P(12, REF_CLK, SFP, TWI_SCL_M); 7218fc0bfcdSHoratiu Vultur SERVALT_P(13, REF_CLK, SFP, TWI_SCL_M); 7228fc0bfcdSHoratiu Vultur SERVALT_P(14, REF_CLK, IRQ0_OUT, SI); 7238fc0bfcdSHoratiu Vultur SERVALT_P(15, REF_CLK, IRQ1_OUT, SI); 7248fc0bfcdSHoratiu Vultur SERVALT_P(16, TACHO, SFP, SI); 7258fc0bfcdSHoratiu Vultur SERVALT_P(17, PWM, NONE, TWI_SCL_M); 7268fc0bfcdSHoratiu Vultur SERVALT_P(18, PTP2, SFP, SI); 7278fc0bfcdSHoratiu Vultur SERVALT_P(19, PTP3, SFP, SI); 7288fc0bfcdSHoratiu Vultur SERVALT_P(20, UART2, SFP, SI); 7298fc0bfcdSHoratiu Vultur SERVALT_P(21, UART2, NONE, NONE); 7308fc0bfcdSHoratiu Vultur SERVALT_P(22, MIIM, SFP, TWI2); 7318fc0bfcdSHoratiu Vultur SERVALT_P(23, MIIM, SFP, TWI2); 7328fc0bfcdSHoratiu Vultur SERVALT_P(24, TWI, NONE, NONE); 7338fc0bfcdSHoratiu Vultur SERVALT_P(25, TWI, SFP, TWI_SCL_M); 7348fc0bfcdSHoratiu Vultur SERVALT_P(26, TWI_SCL_M, SFP, SI); 7358fc0bfcdSHoratiu Vultur SERVALT_P(27, TWI_SCL_M, SFP, SI); 7368fc0bfcdSHoratiu Vultur SERVALT_P(28, TWI_SCL_M, SFP, SI); 7378fc0bfcdSHoratiu Vultur SERVALT_P(29, TWI_SCL_M, NONE, NONE); 7388fc0bfcdSHoratiu Vultur SERVALT_P(30, TWI_SCL_M, NONE, NONE); 7398fc0bfcdSHoratiu Vultur SERVALT_P(31, TWI_SCL_M, NONE, NONE); 7408fc0bfcdSHoratiu Vultur SERVALT_P(32, TWI_SCL_M, NONE, NONE); 7418fc0bfcdSHoratiu Vultur SERVALT_P(33, RCVRD_CLK, NONE, NONE); 7428fc0bfcdSHoratiu Vultur SERVALT_P(34, RCVRD_CLK, NONE, NONE); 7438fc0bfcdSHoratiu Vultur SERVALT_P(35, RCVRD_CLK, NONE, NONE); 7448fc0bfcdSHoratiu Vultur SERVALT_P(36, RCVRD_CLK, NONE, NONE); 7458fc0bfcdSHoratiu Vultur 7468fc0bfcdSHoratiu Vultur #define SERVALT_PIN(n) { \ 7478fc0bfcdSHoratiu Vultur .number = n, \ 7488fc0bfcdSHoratiu Vultur .name = "GPIO_"#n, \ 7498fc0bfcdSHoratiu Vultur .drv_data = &servalt_pin_##n \ 7508fc0bfcdSHoratiu Vultur } 7518fc0bfcdSHoratiu Vultur 7528fc0bfcdSHoratiu Vultur static const struct pinctrl_pin_desc servalt_pins[] = { 7538fc0bfcdSHoratiu Vultur SERVALT_PIN(0), 7548fc0bfcdSHoratiu Vultur SERVALT_PIN(1), 7558fc0bfcdSHoratiu Vultur SERVALT_PIN(2), 7568fc0bfcdSHoratiu Vultur SERVALT_PIN(3), 7578fc0bfcdSHoratiu Vultur SERVALT_PIN(4), 7588fc0bfcdSHoratiu Vultur SERVALT_PIN(5), 7598fc0bfcdSHoratiu Vultur SERVALT_PIN(6), 7608fc0bfcdSHoratiu Vultur SERVALT_PIN(7), 7618fc0bfcdSHoratiu Vultur SERVALT_PIN(8), 7628fc0bfcdSHoratiu Vultur SERVALT_PIN(9), 7638fc0bfcdSHoratiu Vultur SERVALT_PIN(10), 7648fc0bfcdSHoratiu Vultur SERVALT_PIN(11), 7658fc0bfcdSHoratiu Vultur SERVALT_PIN(12), 7668fc0bfcdSHoratiu Vultur SERVALT_PIN(13), 7678fc0bfcdSHoratiu Vultur SERVALT_PIN(14), 7688fc0bfcdSHoratiu Vultur SERVALT_PIN(15), 7698fc0bfcdSHoratiu Vultur SERVALT_PIN(16), 7708fc0bfcdSHoratiu Vultur SERVALT_PIN(17), 7718fc0bfcdSHoratiu Vultur SERVALT_PIN(18), 7728fc0bfcdSHoratiu Vultur SERVALT_PIN(19), 7738fc0bfcdSHoratiu Vultur SERVALT_PIN(20), 7748fc0bfcdSHoratiu Vultur SERVALT_PIN(21), 7758fc0bfcdSHoratiu Vultur SERVALT_PIN(22), 7768fc0bfcdSHoratiu Vultur SERVALT_PIN(23), 7778fc0bfcdSHoratiu Vultur SERVALT_PIN(24), 7788fc0bfcdSHoratiu Vultur SERVALT_PIN(25), 7798fc0bfcdSHoratiu Vultur SERVALT_PIN(26), 7808fc0bfcdSHoratiu Vultur SERVALT_PIN(27), 7818fc0bfcdSHoratiu Vultur SERVALT_PIN(28), 7828fc0bfcdSHoratiu Vultur SERVALT_PIN(29), 7838fc0bfcdSHoratiu Vultur SERVALT_PIN(30), 7848fc0bfcdSHoratiu Vultur SERVALT_PIN(31), 7858fc0bfcdSHoratiu Vultur SERVALT_PIN(32), 7868fc0bfcdSHoratiu Vultur SERVALT_PIN(33), 7878fc0bfcdSHoratiu Vultur SERVALT_PIN(34), 7888fc0bfcdSHoratiu Vultur SERVALT_PIN(35), 7898fc0bfcdSHoratiu Vultur SERVALT_PIN(36), 7908fc0bfcdSHoratiu Vultur }; 7918fc0bfcdSHoratiu Vultur 792f8a74760SLars Povlsen #define SPARX5_P(p, f0, f1, f2) \ 793f8a74760SLars Povlsen static struct ocelot_pin_caps sparx5_pin_##p = { \ 794f8a74760SLars Povlsen .pin = p, \ 795f8a74760SLars Povlsen .functions = { \ 796f8a74760SLars Povlsen FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2 \ 797f8a74760SLars Povlsen }, \ 798f8a74760SLars Povlsen } 799f8a74760SLars Povlsen 800f8a74760SLars Povlsen SPARX5_P(0, SG0, PLL_STAT, NONE); 801f8a74760SLars Povlsen SPARX5_P(1, SG0, NONE, NONE); 802f8a74760SLars Povlsen SPARX5_P(2, SG0, NONE, NONE); 803f8a74760SLars Povlsen SPARX5_P(3, SG0, NONE, NONE); 804f8a74760SLars Povlsen SPARX5_P(4, SG1, NONE, NONE); 805f8a74760SLars Povlsen SPARX5_P(5, SG1, NONE, NONE); 806f8a74760SLars Povlsen SPARX5_P(6, IRQ0_IN, IRQ0_OUT, SFP); 807f8a74760SLars Povlsen SPARX5_P(7, IRQ1_IN, IRQ1_OUT, SFP); 808f8a74760SLars Povlsen SPARX5_P(8, PTP0, NONE, SFP); 809f8a74760SLars Povlsen SPARX5_P(9, PTP1, SFP, TWI_SCL_M); 810f8a74760SLars Povlsen SPARX5_P(10, UART, NONE, NONE); 811f8a74760SLars Povlsen SPARX5_P(11, UART, NONE, NONE); 812f8a74760SLars Povlsen SPARX5_P(12, SG1, NONE, NONE); 813f8a74760SLars Povlsen SPARX5_P(13, SG1, NONE, NONE); 814f8a74760SLars Povlsen SPARX5_P(14, TWI, TWI_SCL_M, NONE); 815f8a74760SLars Povlsen SPARX5_P(15, TWI, NONE, NONE); 816f8a74760SLars Povlsen SPARX5_P(16, SI, TWI_SCL_M, SFP); 817f8a74760SLars Povlsen SPARX5_P(17, SI, TWI_SCL_M, SFP); 818f8a74760SLars Povlsen SPARX5_P(18, SI, TWI_SCL_M, SFP); 819f8a74760SLars Povlsen SPARX5_P(19, PCI_WAKE, TWI_SCL_M, SFP); 820f8a74760SLars Povlsen SPARX5_P(20, IRQ0_OUT, TWI_SCL_M, SFP); 821f8a74760SLars Povlsen SPARX5_P(21, IRQ1_OUT, TACHO, SFP); 822f8a74760SLars Povlsen SPARX5_P(22, TACHO, IRQ0_OUT, TWI_SCL_M); 823f8a74760SLars Povlsen SPARX5_P(23, PWM, UART3, TWI_SCL_M); 824f8a74760SLars Povlsen SPARX5_P(24, PTP2, UART3, TWI_SCL_M); 825f8a74760SLars Povlsen SPARX5_P(25, PTP3, SI, TWI_SCL_M); 826f8a74760SLars Povlsen SPARX5_P(26, UART2, SI, TWI_SCL_M); 827f8a74760SLars Povlsen SPARX5_P(27, UART2, SI, TWI_SCL_M); 828f8a74760SLars Povlsen SPARX5_P(28, TWI2, SI, SFP); 829f8a74760SLars Povlsen SPARX5_P(29, TWI2, SI, SFP); 830f8a74760SLars Povlsen SPARX5_P(30, SG2, SI, PWM); 831f8a74760SLars Povlsen SPARX5_P(31, SG2, SI, TWI_SCL_M); 832f8a74760SLars Povlsen SPARX5_P(32, SG2, SI, TWI_SCL_M); 833f8a74760SLars Povlsen SPARX5_P(33, SG2, SI, SFP); 834f8a74760SLars Povlsen SPARX5_P(34, NONE, TWI_SCL_M, EMMC); 835f8a74760SLars Povlsen SPARX5_P(35, SFP, TWI_SCL_M, EMMC); 836f8a74760SLars Povlsen SPARX5_P(36, SFP, TWI_SCL_M, EMMC); 837f8a74760SLars Povlsen SPARX5_P(37, SFP, NONE, EMMC); 838f8a74760SLars Povlsen SPARX5_P(38, NONE, TWI_SCL_M, EMMC); 839f8a74760SLars Povlsen SPARX5_P(39, SI2, TWI_SCL_M, EMMC); 840f8a74760SLars Povlsen SPARX5_P(40, SI2, TWI_SCL_M, EMMC); 841f8a74760SLars Povlsen SPARX5_P(41, SI2, TWI_SCL_M, EMMC); 842f8a74760SLars Povlsen SPARX5_P(42, SI2, TWI_SCL_M, EMMC); 843f8a74760SLars Povlsen SPARX5_P(43, SI2, TWI_SCL_M, EMMC); 844f8a74760SLars Povlsen SPARX5_P(44, SI, SFP, EMMC); 845f8a74760SLars Povlsen SPARX5_P(45, SI, SFP, EMMC); 846f8a74760SLars Povlsen SPARX5_P(46, NONE, SFP, EMMC); 847f8a74760SLars Povlsen SPARX5_P(47, NONE, SFP, EMMC); 848f8a74760SLars Povlsen SPARX5_P(48, TWI3, SI, SFP); 849f8a74760SLars Povlsen SPARX5_P(49, TWI3, NONE, SFP); 850f8a74760SLars Povlsen SPARX5_P(50, SFP, NONE, TWI_SCL_M); 851f8a74760SLars Povlsen SPARX5_P(51, SFP, SI, TWI_SCL_M); 852f8a74760SLars Povlsen SPARX5_P(52, SFP, MIIM, TWI_SCL_M); 853f8a74760SLars Povlsen SPARX5_P(53, SFP, MIIM, TWI_SCL_M); 854f8a74760SLars Povlsen SPARX5_P(54, SFP, PTP2, TWI_SCL_M); 855f8a74760SLars Povlsen SPARX5_P(55, SFP, PTP3, PCI_WAKE); 856f8a74760SLars Povlsen SPARX5_P(56, MIIM, SFP, TWI_SCL_M); 857f8a74760SLars Povlsen SPARX5_P(57, MIIM, SFP, TWI_SCL_M); 858f8a74760SLars Povlsen SPARX5_P(58, MIIM, SFP, TWI_SCL_M); 859f8a74760SLars Povlsen SPARX5_P(59, MIIM, SFP, NONE); 860f8a74760SLars Povlsen SPARX5_P(60, RECO_CLK, NONE, NONE); 861f8a74760SLars Povlsen SPARX5_P(61, RECO_CLK, NONE, NONE); 862f8a74760SLars Povlsen SPARX5_P(62, RECO_CLK, PLL_STAT, NONE); 863f8a74760SLars Povlsen SPARX5_P(63, RECO_CLK, NONE, NONE); 864f8a74760SLars Povlsen 865f8a74760SLars Povlsen #define SPARX5_PIN(n) { \ 866f8a74760SLars Povlsen .number = n, \ 867f8a74760SLars Povlsen .name = "GPIO_"#n, \ 868f8a74760SLars Povlsen .drv_data = &sparx5_pin_##n \ 869f8a74760SLars Povlsen } 870f8a74760SLars Povlsen 871f8a74760SLars Povlsen static const struct pinctrl_pin_desc sparx5_pins[] = { 872f8a74760SLars Povlsen SPARX5_PIN(0), 873f8a74760SLars Povlsen SPARX5_PIN(1), 874f8a74760SLars Povlsen SPARX5_PIN(2), 875f8a74760SLars Povlsen SPARX5_PIN(3), 876f8a74760SLars Povlsen SPARX5_PIN(4), 877f8a74760SLars Povlsen SPARX5_PIN(5), 878f8a74760SLars Povlsen SPARX5_PIN(6), 879f8a74760SLars Povlsen SPARX5_PIN(7), 880f8a74760SLars Povlsen SPARX5_PIN(8), 881f8a74760SLars Povlsen SPARX5_PIN(9), 882f8a74760SLars Povlsen SPARX5_PIN(10), 883f8a74760SLars Povlsen SPARX5_PIN(11), 884f8a74760SLars Povlsen SPARX5_PIN(12), 885f8a74760SLars Povlsen SPARX5_PIN(13), 886f8a74760SLars Povlsen SPARX5_PIN(14), 887f8a74760SLars Povlsen SPARX5_PIN(15), 888f8a74760SLars Povlsen SPARX5_PIN(16), 889f8a74760SLars Povlsen SPARX5_PIN(17), 890f8a74760SLars Povlsen SPARX5_PIN(18), 891f8a74760SLars Povlsen SPARX5_PIN(19), 892f8a74760SLars Povlsen SPARX5_PIN(20), 893f8a74760SLars Povlsen SPARX5_PIN(21), 894f8a74760SLars Povlsen SPARX5_PIN(22), 895f8a74760SLars Povlsen SPARX5_PIN(23), 896f8a74760SLars Povlsen SPARX5_PIN(24), 897f8a74760SLars Povlsen SPARX5_PIN(25), 898f8a74760SLars Povlsen SPARX5_PIN(26), 899f8a74760SLars Povlsen SPARX5_PIN(27), 900f8a74760SLars Povlsen SPARX5_PIN(28), 901f8a74760SLars Povlsen SPARX5_PIN(29), 902f8a74760SLars Povlsen SPARX5_PIN(30), 903f8a74760SLars Povlsen SPARX5_PIN(31), 904f8a74760SLars Povlsen SPARX5_PIN(32), 905f8a74760SLars Povlsen SPARX5_PIN(33), 906f8a74760SLars Povlsen SPARX5_PIN(34), 907f8a74760SLars Povlsen SPARX5_PIN(35), 908f8a74760SLars Povlsen SPARX5_PIN(36), 909f8a74760SLars Povlsen SPARX5_PIN(37), 910f8a74760SLars Povlsen SPARX5_PIN(38), 911f8a74760SLars Povlsen SPARX5_PIN(39), 912f8a74760SLars Povlsen SPARX5_PIN(40), 913f8a74760SLars Povlsen SPARX5_PIN(41), 914f8a74760SLars Povlsen SPARX5_PIN(42), 915f8a74760SLars Povlsen SPARX5_PIN(43), 916f8a74760SLars Povlsen SPARX5_PIN(44), 917f8a74760SLars Povlsen SPARX5_PIN(45), 918f8a74760SLars Povlsen SPARX5_PIN(46), 919f8a74760SLars Povlsen SPARX5_PIN(47), 920f8a74760SLars Povlsen SPARX5_PIN(48), 921f8a74760SLars Povlsen SPARX5_PIN(49), 922f8a74760SLars Povlsen SPARX5_PIN(50), 923f8a74760SLars Povlsen SPARX5_PIN(51), 924f8a74760SLars Povlsen SPARX5_PIN(52), 925f8a74760SLars Povlsen SPARX5_PIN(53), 926f8a74760SLars Povlsen SPARX5_PIN(54), 927f8a74760SLars Povlsen SPARX5_PIN(55), 928f8a74760SLars Povlsen SPARX5_PIN(56), 929f8a74760SLars Povlsen SPARX5_PIN(57), 930f8a74760SLars Povlsen SPARX5_PIN(58), 931f8a74760SLars Povlsen SPARX5_PIN(59), 932f8a74760SLars Povlsen SPARX5_PIN(60), 933f8a74760SLars Povlsen SPARX5_PIN(61), 934f8a74760SLars Povlsen SPARX5_PIN(62), 935f8a74760SLars Povlsen SPARX5_PIN(63), 936f8a74760SLars Povlsen }; 937f8a74760SLars Povlsen 938531d6ab3SKavyasree Kotagiri #define LAN966X_P(p, f0, f1, f2, f3, f4, f5, f6, f7) \ 939531d6ab3SKavyasree Kotagiri static struct ocelot_pin_caps lan966x_pin_##p = { \ 940531d6ab3SKavyasree Kotagiri .pin = p, \ 941531d6ab3SKavyasree Kotagiri .functions = { \ 942531d6ab3SKavyasree Kotagiri FUNC_##f0, FUNC_##f1, FUNC_##f2, \ 943531d6ab3SKavyasree Kotagiri FUNC_##f3 \ 944531d6ab3SKavyasree Kotagiri }, \ 945531d6ab3SKavyasree Kotagiri .a_functions = { \ 946531d6ab3SKavyasree Kotagiri FUNC_##f4, FUNC_##f5, FUNC_##f6, \ 947531d6ab3SKavyasree Kotagiri FUNC_##f7 \ 948531d6ab3SKavyasree Kotagiri }, \ 949531d6ab3SKavyasree Kotagiri } 950531d6ab3SKavyasree Kotagiri 951531d6ab3SKavyasree Kotagiri /* Pinmuxing table taken from data sheet */ 952531d6ab3SKavyasree Kotagiri /* Pin FUNC0 FUNC1 FUNC2 FUNC3 FUNC4 FUNC5 FUNC6 FUNC7 */ 953531d6ab3SKavyasree Kotagiri LAN966X_P(0, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 954531d6ab3SKavyasree Kotagiri LAN966X_P(1, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 955531d6ab3SKavyasree Kotagiri LAN966X_P(2, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 956531d6ab3SKavyasree Kotagiri LAN966X_P(3, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 957531d6ab3SKavyasree Kotagiri LAN966X_P(4, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 958531d6ab3SKavyasree Kotagiri LAN966X_P(5, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 959531d6ab3SKavyasree Kotagiri LAN966X_P(6, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 960531d6ab3SKavyasree Kotagiri LAN966X_P(7, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 961531d6ab3SKavyasree Kotagiri LAN966X_P(8, GPIO, FC0_a, USB_H_b, NONE, USB_S_b, NONE, NONE, R); 962531d6ab3SKavyasree Kotagiri LAN966X_P(9, GPIO, FC0_a, USB_H_b, NONE, NONE, NONE, NONE, R); 963531d6ab3SKavyasree Kotagiri LAN966X_P(10, GPIO, FC0_a, NONE, NONE, NONE, NONE, NONE, R); 964531d6ab3SKavyasree Kotagiri LAN966X_P(11, GPIO, FC1_a, NONE, NONE, NONE, NONE, NONE, R); 965531d6ab3SKavyasree Kotagiri LAN966X_P(12, GPIO, FC1_a, NONE, NONE, NONE, NONE, NONE, R); 966531d6ab3SKavyasree Kotagiri LAN966X_P(13, GPIO, FC1_a, NONE, NONE, NONE, NONE, NONE, R); 967531d6ab3SKavyasree Kotagiri LAN966X_P(14, GPIO, FC2_a, NONE, NONE, NONE, NONE, NONE, R); 968531d6ab3SKavyasree Kotagiri LAN966X_P(15, GPIO, FC2_a, NONE, NONE, NONE, NONE, NONE, R); 969531d6ab3SKavyasree Kotagiri LAN966X_P(16, GPIO, FC2_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, IRQ_OUT_c, R); 970531d6ab3SKavyasree Kotagiri LAN966X_P(17, GPIO, FC3_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, IRQ_OUT_c, R); 971531d6ab3SKavyasree Kotagiri LAN966X_P(18, GPIO, FC3_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, IRQ_OUT_c, R); 972531d6ab3SKavyasree Kotagiri LAN966X_P(19, GPIO, FC3_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, IRQ_OUT_c, R); 973531d6ab3SKavyasree Kotagiri LAN966X_P(20, GPIO, FC4_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, NONE, R); 974531d6ab3SKavyasree Kotagiri LAN966X_P(21, GPIO, FC4_a, NONE, NONE, OB_TRG_a, NONE, NONE, R); 975531d6ab3SKavyasree Kotagiri LAN966X_P(22, GPIO, FC4_a, NONE, NONE, OB_TRG_a, NONE, NONE, R); 976531d6ab3SKavyasree Kotagiri LAN966X_P(23, GPIO, NONE, NONE, NONE, OB_TRG_a, NONE, NONE, R); 977531d6ab3SKavyasree Kotagiri LAN966X_P(24, GPIO, FC0_b, IB_TRG_a, USB_H_c, OB_TRG_a, IRQ_IN_c, TACHO_a, R); 978531d6ab3SKavyasree Kotagiri LAN966X_P(25, GPIO, FC0_b, IB_TRG_a, USB_H_c, OB_TRG_a, IRQ_OUT_c, SFP_SD, R); 979531d6ab3SKavyasree Kotagiri LAN966X_P(26, GPIO, FC0_b, IB_TRG_a, USB_S_c, OB_TRG_a, CAN0_a, SFP_SD, R); 980531d6ab3SKavyasree Kotagiri LAN966X_P(27, GPIO, NONE, NONE, NONE, OB_TRG_a, CAN0_a, NONE, R); 981531d6ab3SKavyasree Kotagiri LAN966X_P(28, GPIO, MIIM_a, NONE, NONE, OB_TRG_a, IRQ_OUT_c, SFP_SD, R); 982531d6ab3SKavyasree Kotagiri LAN966X_P(29, GPIO, MIIM_a, NONE, NONE, OB_TRG_a, NONE, NONE, R); 983531d6ab3SKavyasree Kotagiri LAN966X_P(30, GPIO, FC3_c, CAN1, NONE, OB_TRG, RECO_b, NONE, R); 984531d6ab3SKavyasree Kotagiri LAN966X_P(31, GPIO, FC3_c, CAN1, NONE, OB_TRG, RECO_b, NONE, R); 985531d6ab3SKavyasree Kotagiri LAN966X_P(32, GPIO, FC3_c, NONE, SGPIO_a, NONE, MIIM_Sa, NONE, R); 986531d6ab3SKavyasree Kotagiri LAN966X_P(33, GPIO, FC1_b, NONE, SGPIO_a, NONE, MIIM_Sa, MIIM_b, R); 987531d6ab3SKavyasree Kotagiri LAN966X_P(34, GPIO, FC1_b, NONE, SGPIO_a, NONE, MIIM_Sa, MIIM_b, R); 988*d3683eebSHoratiu Vultur LAN966X_P(35, GPIO, FC1_b, PTPSYNC_0, SGPIO_a, CAN0_b, NONE, NONE, R); 989531d6ab3SKavyasree Kotagiri LAN966X_P(36, GPIO, NONE, PTPSYNC_1, NONE, CAN0_b, NONE, NONE, R); 990531d6ab3SKavyasree Kotagiri LAN966X_P(37, GPIO, FC_SHRD0, PTPSYNC_2, TWI_SLC_GATE_AD, NONE, NONE, NONE, R); 991531d6ab3SKavyasree Kotagiri LAN966X_P(38, GPIO, NONE, PTPSYNC_3, NONE, NONE, NONE, NONE, R); 992531d6ab3SKavyasree Kotagiri LAN966X_P(39, GPIO, NONE, PTPSYNC_4, NONE, NONE, NONE, NONE, R); 993531d6ab3SKavyasree Kotagiri LAN966X_P(40, GPIO, FC_SHRD1, PTPSYNC_5, NONE, NONE, NONE, NONE, R); 994531d6ab3SKavyasree Kotagiri LAN966X_P(41, GPIO, FC_SHRD2, PTPSYNC_6, TWI_SLC_GATE_AD, NONE, NONE, NONE, R); 995531d6ab3SKavyasree Kotagiri LAN966X_P(42, GPIO, FC_SHRD3, PTPSYNC_7, TWI_SLC_GATE_AD, NONE, NONE, NONE, R); 996531d6ab3SKavyasree Kotagiri LAN966X_P(43, GPIO, FC2_b, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, RECO_a, IRQ_IN_a, R); 997531d6ab3SKavyasree Kotagiri LAN966X_P(44, GPIO, FC2_b, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, RECO_a, IRQ_IN_a, R); 998531d6ab3SKavyasree Kotagiri LAN966X_P(45, GPIO, FC2_b, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, NONE, IRQ_IN_a, R); 999531d6ab3SKavyasree Kotagiri LAN966X_P(46, GPIO, FC1_c, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, FC_SHRD4, IRQ_IN_a, R); 1000531d6ab3SKavyasree Kotagiri LAN966X_P(47, GPIO, FC1_c, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, FC_SHRD5, IRQ_IN_a, R); 1001531d6ab3SKavyasree Kotagiri LAN966X_P(48, GPIO, FC1_c, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, FC_SHRD6, IRQ_IN_a, R); 1002531d6ab3SKavyasree Kotagiri LAN966X_P(49, GPIO, FC_SHRD7, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, TWI_SLC_GATE, IRQ_IN_a, R); 1003531d6ab3SKavyasree Kotagiri LAN966X_P(50, GPIO, FC_SHRD16, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, TWI_SLC_GATE, NONE, R); 1004531d6ab3SKavyasree Kotagiri LAN966X_P(51, GPIO, FC3_b, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, NONE, IRQ_IN_b, R); 1005531d6ab3SKavyasree Kotagiri LAN966X_P(52, GPIO, FC3_b, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, TACHO_b, IRQ_IN_b, R); 1006531d6ab3SKavyasree Kotagiri LAN966X_P(53, GPIO, FC3_b, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, NONE, IRQ_IN_b, R); 1007531d6ab3SKavyasree Kotagiri LAN966X_P(54, GPIO, FC_SHRD8, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, TWI_SLC_GATE, IRQ_IN_b, R); 1008531d6ab3SKavyasree Kotagiri LAN966X_P(55, GPIO, FC_SHRD9, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, TWI_SLC_GATE, IRQ_IN_b, R); 1009531d6ab3SKavyasree Kotagiri LAN966X_P(56, GPIO, FC4_b, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, FC_SHRD10, IRQ_IN_b, R); 1010531d6ab3SKavyasree Kotagiri LAN966X_P(57, GPIO, FC4_b, TWI_SLC_GATE, IB_TRG_c, IRQ_OUT_b, FC_SHRD11, IRQ_IN_b, R); 1011531d6ab3SKavyasree Kotagiri LAN966X_P(58, GPIO, FC4_b, TWI_SLC_GATE, IB_TRG_c, IRQ_OUT_b, FC_SHRD12, IRQ_IN_b, R); 1012531d6ab3SKavyasree Kotagiri LAN966X_P(59, GPIO, QSPI1, MIIM_c, NONE, NONE, MIIM_Sb, NONE, R); 1013531d6ab3SKavyasree Kotagiri LAN966X_P(60, GPIO, QSPI1, MIIM_c, NONE, NONE, MIIM_Sb, NONE, R); 1014531d6ab3SKavyasree Kotagiri LAN966X_P(61, GPIO, QSPI1, NONE, SGPIO_b, FC0_c, MIIM_Sb, NONE, R); 1015531d6ab3SKavyasree Kotagiri LAN966X_P(62, GPIO, QSPI1, FC_SHRD13, SGPIO_b, FC0_c, TWI_SLC_GATE, SFP_SD, R); 1016531d6ab3SKavyasree Kotagiri LAN966X_P(63, GPIO, QSPI1, FC_SHRD14, SGPIO_b, FC0_c, TWI_SLC_GATE, SFP_SD, R); 1017531d6ab3SKavyasree Kotagiri LAN966X_P(64, GPIO, QSPI1, FC4_c, SGPIO_b, FC_SHRD15, TWI_SLC_GATE, SFP_SD, R); 1018531d6ab3SKavyasree Kotagiri LAN966X_P(65, GPIO, USB_H_a, FC4_c, NONE, IRQ_OUT_c, TWI_SLC_GATE_AD, NONE, R); 1019531d6ab3SKavyasree Kotagiri LAN966X_P(66, GPIO, USB_H_a, FC4_c, USB_S_a, IRQ_OUT_c, IRQ_IN_c, NONE, R); 1020531d6ab3SKavyasree Kotagiri LAN966X_P(67, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R); 1021531d6ab3SKavyasree Kotagiri LAN966X_P(68, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R); 1022531d6ab3SKavyasree Kotagiri LAN966X_P(69, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R); 1023531d6ab3SKavyasree Kotagiri LAN966X_P(70, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R); 1024531d6ab3SKavyasree Kotagiri LAN966X_P(71, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R); 1025531d6ab3SKavyasree Kotagiri LAN966X_P(72, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R); 1026531d6ab3SKavyasree Kotagiri LAN966X_P(73, GPIO, EMMC, NONE, NONE, SD, NONE, NONE, R); 1027531d6ab3SKavyasree Kotagiri LAN966X_P(74, GPIO, EMMC, NONE, FC_SHRD17, SD, TWI_SLC_GATE, NONE, R); 1028531d6ab3SKavyasree Kotagiri LAN966X_P(75, GPIO, EMMC, NONE, FC_SHRD18, SD, TWI_SLC_GATE, NONE, R); 1029531d6ab3SKavyasree Kotagiri LAN966X_P(76, GPIO, EMMC, NONE, FC_SHRD19, SD, TWI_SLC_GATE, NONE, R); 1030531d6ab3SKavyasree Kotagiri LAN966X_P(77, GPIO, EMMC_SD, NONE, FC_SHRD20, NONE, TWI_SLC_GATE, NONE, R); 1031531d6ab3SKavyasree Kotagiri 1032531d6ab3SKavyasree Kotagiri #define LAN966X_PIN(n) { \ 1033531d6ab3SKavyasree Kotagiri .number = n, \ 1034531d6ab3SKavyasree Kotagiri .name = "GPIO_"#n, \ 1035531d6ab3SKavyasree Kotagiri .drv_data = &lan966x_pin_##n \ 1036531d6ab3SKavyasree Kotagiri } 1037531d6ab3SKavyasree Kotagiri 1038531d6ab3SKavyasree Kotagiri static const struct pinctrl_pin_desc lan966x_pins[] = { 1039531d6ab3SKavyasree Kotagiri LAN966X_PIN(0), 1040531d6ab3SKavyasree Kotagiri LAN966X_PIN(1), 1041531d6ab3SKavyasree Kotagiri LAN966X_PIN(2), 1042531d6ab3SKavyasree Kotagiri LAN966X_PIN(3), 1043531d6ab3SKavyasree Kotagiri LAN966X_PIN(4), 1044531d6ab3SKavyasree Kotagiri LAN966X_PIN(5), 1045531d6ab3SKavyasree Kotagiri LAN966X_PIN(6), 1046531d6ab3SKavyasree Kotagiri LAN966X_PIN(7), 1047531d6ab3SKavyasree Kotagiri LAN966X_PIN(8), 1048531d6ab3SKavyasree Kotagiri LAN966X_PIN(9), 1049531d6ab3SKavyasree Kotagiri LAN966X_PIN(10), 1050531d6ab3SKavyasree Kotagiri LAN966X_PIN(11), 1051531d6ab3SKavyasree Kotagiri LAN966X_PIN(12), 1052531d6ab3SKavyasree Kotagiri LAN966X_PIN(13), 1053531d6ab3SKavyasree Kotagiri LAN966X_PIN(14), 1054531d6ab3SKavyasree Kotagiri LAN966X_PIN(15), 1055531d6ab3SKavyasree Kotagiri LAN966X_PIN(16), 1056531d6ab3SKavyasree Kotagiri LAN966X_PIN(17), 1057531d6ab3SKavyasree Kotagiri LAN966X_PIN(18), 1058531d6ab3SKavyasree Kotagiri LAN966X_PIN(19), 1059531d6ab3SKavyasree Kotagiri LAN966X_PIN(20), 1060531d6ab3SKavyasree Kotagiri LAN966X_PIN(21), 1061531d6ab3SKavyasree Kotagiri LAN966X_PIN(22), 1062531d6ab3SKavyasree Kotagiri LAN966X_PIN(23), 1063531d6ab3SKavyasree Kotagiri LAN966X_PIN(24), 1064531d6ab3SKavyasree Kotagiri LAN966X_PIN(25), 1065531d6ab3SKavyasree Kotagiri LAN966X_PIN(26), 1066531d6ab3SKavyasree Kotagiri LAN966X_PIN(27), 1067531d6ab3SKavyasree Kotagiri LAN966X_PIN(28), 1068531d6ab3SKavyasree Kotagiri LAN966X_PIN(29), 1069531d6ab3SKavyasree Kotagiri LAN966X_PIN(30), 1070531d6ab3SKavyasree Kotagiri LAN966X_PIN(31), 1071531d6ab3SKavyasree Kotagiri LAN966X_PIN(32), 1072531d6ab3SKavyasree Kotagiri LAN966X_PIN(33), 1073531d6ab3SKavyasree Kotagiri LAN966X_PIN(34), 1074531d6ab3SKavyasree Kotagiri LAN966X_PIN(35), 1075531d6ab3SKavyasree Kotagiri LAN966X_PIN(36), 1076531d6ab3SKavyasree Kotagiri LAN966X_PIN(37), 1077531d6ab3SKavyasree Kotagiri LAN966X_PIN(38), 1078531d6ab3SKavyasree Kotagiri LAN966X_PIN(39), 1079531d6ab3SKavyasree Kotagiri LAN966X_PIN(40), 1080531d6ab3SKavyasree Kotagiri LAN966X_PIN(41), 1081531d6ab3SKavyasree Kotagiri LAN966X_PIN(42), 1082531d6ab3SKavyasree Kotagiri LAN966X_PIN(43), 1083531d6ab3SKavyasree Kotagiri LAN966X_PIN(44), 1084531d6ab3SKavyasree Kotagiri LAN966X_PIN(45), 1085531d6ab3SKavyasree Kotagiri LAN966X_PIN(46), 1086531d6ab3SKavyasree Kotagiri LAN966X_PIN(47), 1087531d6ab3SKavyasree Kotagiri LAN966X_PIN(48), 1088531d6ab3SKavyasree Kotagiri LAN966X_PIN(49), 1089531d6ab3SKavyasree Kotagiri LAN966X_PIN(50), 1090531d6ab3SKavyasree Kotagiri LAN966X_PIN(51), 1091531d6ab3SKavyasree Kotagiri LAN966X_PIN(52), 1092531d6ab3SKavyasree Kotagiri LAN966X_PIN(53), 1093531d6ab3SKavyasree Kotagiri LAN966X_PIN(54), 1094531d6ab3SKavyasree Kotagiri LAN966X_PIN(55), 1095531d6ab3SKavyasree Kotagiri LAN966X_PIN(56), 1096531d6ab3SKavyasree Kotagiri LAN966X_PIN(57), 1097531d6ab3SKavyasree Kotagiri LAN966X_PIN(58), 1098531d6ab3SKavyasree Kotagiri LAN966X_PIN(59), 1099531d6ab3SKavyasree Kotagiri LAN966X_PIN(60), 1100531d6ab3SKavyasree Kotagiri LAN966X_PIN(61), 1101531d6ab3SKavyasree Kotagiri LAN966X_PIN(62), 1102531d6ab3SKavyasree Kotagiri LAN966X_PIN(63), 1103531d6ab3SKavyasree Kotagiri LAN966X_PIN(64), 1104531d6ab3SKavyasree Kotagiri LAN966X_PIN(65), 1105531d6ab3SKavyasree Kotagiri LAN966X_PIN(66), 1106531d6ab3SKavyasree Kotagiri LAN966X_PIN(67), 1107531d6ab3SKavyasree Kotagiri LAN966X_PIN(68), 1108531d6ab3SKavyasree Kotagiri LAN966X_PIN(69), 1109531d6ab3SKavyasree Kotagiri LAN966X_PIN(70), 1110531d6ab3SKavyasree Kotagiri LAN966X_PIN(71), 1111531d6ab3SKavyasree Kotagiri LAN966X_PIN(72), 1112531d6ab3SKavyasree Kotagiri LAN966X_PIN(73), 1113531d6ab3SKavyasree Kotagiri LAN966X_PIN(74), 1114531d6ab3SKavyasree Kotagiri LAN966X_PIN(75), 1115531d6ab3SKavyasree Kotagiri LAN966X_PIN(76), 1116531d6ab3SKavyasree Kotagiri LAN966X_PIN(77), 1117531d6ab3SKavyasree Kotagiri }; 1118531d6ab3SKavyasree Kotagiri 1119ce8dc094SAlexandre Belloni static int ocelot_get_functions_count(struct pinctrl_dev *pctldev) 1120ce8dc094SAlexandre Belloni { 1121ce8dc094SAlexandre Belloni return ARRAY_SIZE(ocelot_function_names); 1122ce8dc094SAlexandre Belloni } 1123ce8dc094SAlexandre Belloni 1124ce8dc094SAlexandre Belloni static const char *ocelot_get_function_name(struct pinctrl_dev *pctldev, 1125ce8dc094SAlexandre Belloni unsigned int function) 1126ce8dc094SAlexandre Belloni { 1127ce8dc094SAlexandre Belloni return ocelot_function_names[function]; 1128ce8dc094SAlexandre Belloni } 1129ce8dc094SAlexandre Belloni 1130ce8dc094SAlexandre Belloni static int ocelot_get_function_groups(struct pinctrl_dev *pctldev, 1131ce8dc094SAlexandre Belloni unsigned int function, 1132ce8dc094SAlexandre Belloni const char *const **groups, 1133ce8dc094SAlexandre Belloni unsigned *const num_groups) 1134ce8dc094SAlexandre Belloni { 1135ce8dc094SAlexandre Belloni struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1136ce8dc094SAlexandre Belloni 1137ce8dc094SAlexandre Belloni *groups = info->func[function].groups; 1138ce8dc094SAlexandre Belloni *num_groups = info->func[function].ngroups; 1139ce8dc094SAlexandre Belloni 1140ce8dc094SAlexandre Belloni return 0; 1141ce8dc094SAlexandre Belloni } 1142ce8dc094SAlexandre Belloni 1143da801ab5SAlexandre Belloni static int ocelot_pin_function_idx(struct ocelot_pinctrl *info, 1144da801ab5SAlexandre Belloni unsigned int pin, unsigned int function) 1145ce8dc094SAlexandre Belloni { 1146da801ab5SAlexandre Belloni struct ocelot_pin_caps *p = info->desc->pins[pin].drv_data; 1147ce8dc094SAlexandre Belloni int i; 1148ce8dc094SAlexandre Belloni 1149ce8dc094SAlexandre Belloni for (i = 0; i < OCELOT_FUNC_PER_PIN; i++) { 1150ce8dc094SAlexandre Belloni if (function == p->functions[i]) 1151ce8dc094SAlexandre Belloni return i; 1152531d6ab3SKavyasree Kotagiri 1153531d6ab3SKavyasree Kotagiri if (function == p->a_functions[i]) 1154531d6ab3SKavyasree Kotagiri return i + OCELOT_FUNC_PER_PIN; 1155ce8dc094SAlexandre Belloni } 1156ce8dc094SAlexandre Belloni 1157ce8dc094SAlexandre Belloni return -1; 1158ce8dc094SAlexandre Belloni } 1159ce8dc094SAlexandre Belloni 11604b36082eSAlexandre Belloni #define REG_ALT(msb, info, p) (OCELOT_GPIO_ALT0 * (info)->stride + 4 * ((msb) + ((info)->stride * ((p) / 32)))) 1161da801ab5SAlexandre Belloni 1162ce8dc094SAlexandre Belloni static int ocelot_pinmux_set_mux(struct pinctrl_dev *pctldev, 1163ce8dc094SAlexandre Belloni unsigned int selector, unsigned int group) 1164ce8dc094SAlexandre Belloni { 1165ce8dc094SAlexandre Belloni struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1166da801ab5SAlexandre Belloni struct ocelot_pin_caps *pin = info->desc->pins[group].drv_data; 1167da801ab5SAlexandre Belloni unsigned int p = pin->pin % 32; 1168ce8dc094SAlexandre Belloni int f; 1169ce8dc094SAlexandre Belloni 1170da801ab5SAlexandre Belloni f = ocelot_pin_function_idx(info, group, selector); 1171ce8dc094SAlexandre Belloni if (f < 0) 1172ce8dc094SAlexandre Belloni return -EINVAL; 1173ce8dc094SAlexandre Belloni 1174ce8dc094SAlexandre Belloni /* 1175ce8dc094SAlexandre Belloni * f is encoded on two bits. 11764b36082eSAlexandre Belloni * bit 0 of f goes in BIT(pin) of ALT[0], bit 1 of f goes in BIT(pin) of 11774b36082eSAlexandre Belloni * ALT[1] 1178ce8dc094SAlexandre Belloni * This is racy because both registers can't be updated at the same time 1179ce8dc094SAlexandre Belloni * but it doesn't matter much for now. 1180f8a74760SLars Povlsen * Note: ALT0/ALT1 are organized specially for 64 gpio targets 1181ce8dc094SAlexandre Belloni */ 11824b36082eSAlexandre Belloni regmap_update_bits(info->map, REG_ALT(0, info, pin->pin), 1183da801ab5SAlexandre Belloni BIT(p), f << p); 11844b36082eSAlexandre Belloni regmap_update_bits(info->map, REG_ALT(1, info, pin->pin), 1185da801ab5SAlexandre Belloni BIT(p), f << (p - 1)); 1186ce8dc094SAlexandre Belloni 1187ce8dc094SAlexandre Belloni return 0; 1188ce8dc094SAlexandre Belloni } 1189ce8dc094SAlexandre Belloni 1190531d6ab3SKavyasree Kotagiri static int lan966x_pinmux_set_mux(struct pinctrl_dev *pctldev, 1191531d6ab3SKavyasree Kotagiri unsigned int selector, unsigned int group) 1192531d6ab3SKavyasree Kotagiri { 1193531d6ab3SKavyasree Kotagiri struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1194531d6ab3SKavyasree Kotagiri struct ocelot_pin_caps *pin = info->desc->pins[group].drv_data; 1195531d6ab3SKavyasree Kotagiri unsigned int p = pin->pin % 32; 1196531d6ab3SKavyasree Kotagiri int f; 1197531d6ab3SKavyasree Kotagiri 1198531d6ab3SKavyasree Kotagiri f = ocelot_pin_function_idx(info, group, selector); 1199531d6ab3SKavyasree Kotagiri if (f < 0) 1200531d6ab3SKavyasree Kotagiri return -EINVAL; 1201531d6ab3SKavyasree Kotagiri 1202531d6ab3SKavyasree Kotagiri /* 1203531d6ab3SKavyasree Kotagiri * f is encoded on three bits. 1204531d6ab3SKavyasree Kotagiri * bit 0 of f goes in BIT(pin) of ALT[0], bit 1 of f goes in BIT(pin) of 1205531d6ab3SKavyasree Kotagiri * ALT[1], bit 2 of f goes in BIT(pin) of ALT[2] 1206531d6ab3SKavyasree Kotagiri * This is racy because three registers can't be updated at the same time 1207531d6ab3SKavyasree Kotagiri * but it doesn't matter much for now. 1208531d6ab3SKavyasree Kotagiri * Note: ALT0/ALT1/ALT2 are organized specially for 78 gpio targets 1209531d6ab3SKavyasree Kotagiri */ 1210531d6ab3SKavyasree Kotagiri regmap_update_bits(info->map, REG_ALT(0, info, pin->pin), 1211531d6ab3SKavyasree Kotagiri BIT(p), f << p); 1212531d6ab3SKavyasree Kotagiri regmap_update_bits(info->map, REG_ALT(1, info, pin->pin), 1213531d6ab3SKavyasree Kotagiri BIT(p), (f >> 1) << p); 1214531d6ab3SKavyasree Kotagiri regmap_update_bits(info->map, REG_ALT(2, info, pin->pin), 1215531d6ab3SKavyasree Kotagiri BIT(p), (f >> 2) << p); 1216531d6ab3SKavyasree Kotagiri 1217531d6ab3SKavyasree Kotagiri return 0; 1218531d6ab3SKavyasree Kotagiri } 1219531d6ab3SKavyasree Kotagiri 12204b36082eSAlexandre Belloni #define REG(r, info, p) ((r) * (info)->stride + (4 * ((p) / 32))) 12214b36082eSAlexandre Belloni 1222ce8dc094SAlexandre Belloni static int ocelot_gpio_set_direction(struct pinctrl_dev *pctldev, 1223ce8dc094SAlexandre Belloni struct pinctrl_gpio_range *range, 1224ce8dc094SAlexandre Belloni unsigned int pin, bool input) 1225ce8dc094SAlexandre Belloni { 1226ce8dc094SAlexandre Belloni struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1227da801ab5SAlexandre Belloni unsigned int p = pin % 32; 1228ce8dc094SAlexandre Belloni 1229f2818ba3SAlexandre Belloni regmap_update_bits(info->map, REG(OCELOT_GPIO_OE, info, pin), BIT(p), 1230da801ab5SAlexandre Belloni input ? 0 : BIT(p)); 1231ce8dc094SAlexandre Belloni 1232ce8dc094SAlexandre Belloni return 0; 1233ce8dc094SAlexandre Belloni } 1234ce8dc094SAlexandre Belloni 1235ce8dc094SAlexandre Belloni static int ocelot_gpio_request_enable(struct pinctrl_dev *pctldev, 1236ce8dc094SAlexandre Belloni struct pinctrl_gpio_range *range, 1237ce8dc094SAlexandre Belloni unsigned int offset) 1238ce8dc094SAlexandre Belloni { 1239ce8dc094SAlexandre Belloni struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1240da801ab5SAlexandre Belloni unsigned int p = offset % 32; 1241ce8dc094SAlexandre Belloni 12424b36082eSAlexandre Belloni regmap_update_bits(info->map, REG_ALT(0, info, offset), 1243da801ab5SAlexandre Belloni BIT(p), 0); 12444b36082eSAlexandre Belloni regmap_update_bits(info->map, REG_ALT(1, info, offset), 1245da801ab5SAlexandre Belloni BIT(p), 0); 1246ce8dc094SAlexandre Belloni 1247ce8dc094SAlexandre Belloni return 0; 1248ce8dc094SAlexandre Belloni } 1249ce8dc094SAlexandre Belloni 1250531d6ab3SKavyasree Kotagiri static int lan966x_gpio_request_enable(struct pinctrl_dev *pctldev, 1251531d6ab3SKavyasree Kotagiri struct pinctrl_gpio_range *range, 1252531d6ab3SKavyasree Kotagiri unsigned int offset) 1253531d6ab3SKavyasree Kotagiri { 1254531d6ab3SKavyasree Kotagiri struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1255531d6ab3SKavyasree Kotagiri unsigned int p = offset % 32; 1256531d6ab3SKavyasree Kotagiri 1257531d6ab3SKavyasree Kotagiri regmap_update_bits(info->map, REG_ALT(0, info, offset), 1258531d6ab3SKavyasree Kotagiri BIT(p), 0); 1259531d6ab3SKavyasree Kotagiri regmap_update_bits(info->map, REG_ALT(1, info, offset), 1260531d6ab3SKavyasree Kotagiri BIT(p), 0); 1261531d6ab3SKavyasree Kotagiri regmap_update_bits(info->map, REG_ALT(2, info, offset), 1262531d6ab3SKavyasree Kotagiri BIT(p), 0); 1263531d6ab3SKavyasree Kotagiri 1264531d6ab3SKavyasree Kotagiri return 0; 1265531d6ab3SKavyasree Kotagiri } 1266531d6ab3SKavyasree Kotagiri 1267ce8dc094SAlexandre Belloni static const struct pinmux_ops ocelot_pmx_ops = { 1268ce8dc094SAlexandre Belloni .get_functions_count = ocelot_get_functions_count, 1269ce8dc094SAlexandre Belloni .get_function_name = ocelot_get_function_name, 1270ce8dc094SAlexandre Belloni .get_function_groups = ocelot_get_function_groups, 1271ce8dc094SAlexandre Belloni .set_mux = ocelot_pinmux_set_mux, 1272ce8dc094SAlexandre Belloni .gpio_set_direction = ocelot_gpio_set_direction, 1273ce8dc094SAlexandre Belloni .gpio_request_enable = ocelot_gpio_request_enable, 1274ce8dc094SAlexandre Belloni }; 1275ce8dc094SAlexandre Belloni 1276531d6ab3SKavyasree Kotagiri static const struct pinmux_ops lan966x_pmx_ops = { 1277531d6ab3SKavyasree Kotagiri .get_functions_count = ocelot_get_functions_count, 1278531d6ab3SKavyasree Kotagiri .get_function_name = ocelot_get_function_name, 1279531d6ab3SKavyasree Kotagiri .get_function_groups = ocelot_get_function_groups, 1280531d6ab3SKavyasree Kotagiri .set_mux = lan966x_pinmux_set_mux, 1281531d6ab3SKavyasree Kotagiri .gpio_set_direction = ocelot_gpio_set_direction, 1282531d6ab3SKavyasree Kotagiri .gpio_request_enable = lan966x_gpio_request_enable, 1283531d6ab3SKavyasree Kotagiri }; 1284531d6ab3SKavyasree Kotagiri 1285ce8dc094SAlexandre Belloni static int ocelot_pctl_get_groups_count(struct pinctrl_dev *pctldev) 1286ce8dc094SAlexandre Belloni { 1287da801ab5SAlexandre Belloni struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1288da801ab5SAlexandre Belloni 1289da801ab5SAlexandre Belloni return info->desc->npins; 1290ce8dc094SAlexandre Belloni } 1291ce8dc094SAlexandre Belloni 1292ce8dc094SAlexandre Belloni static const char *ocelot_pctl_get_group_name(struct pinctrl_dev *pctldev, 1293ce8dc094SAlexandre Belloni unsigned int group) 1294ce8dc094SAlexandre Belloni { 1295da801ab5SAlexandre Belloni struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1296da801ab5SAlexandre Belloni 1297da801ab5SAlexandre Belloni return info->desc->pins[group].name; 1298ce8dc094SAlexandre Belloni } 1299ce8dc094SAlexandre Belloni 1300ce8dc094SAlexandre Belloni static int ocelot_pctl_get_group_pins(struct pinctrl_dev *pctldev, 1301ce8dc094SAlexandre Belloni unsigned int group, 1302ce8dc094SAlexandre Belloni const unsigned int **pins, 1303ce8dc094SAlexandre Belloni unsigned int *num_pins) 1304ce8dc094SAlexandre Belloni { 1305da801ab5SAlexandre Belloni struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1306da801ab5SAlexandre Belloni 1307da801ab5SAlexandre Belloni *pins = &info->desc->pins[group].number; 1308ce8dc094SAlexandre Belloni *num_pins = 1; 1309ce8dc094SAlexandre Belloni 1310ce8dc094SAlexandre Belloni return 0; 1311ce8dc094SAlexandre Belloni } 1312ce8dc094SAlexandre Belloni 1313f8a74760SLars Povlsen static int ocelot_hw_get_value(struct ocelot_pinctrl *info, 1314f8a74760SLars Povlsen unsigned int pin, 1315f8a74760SLars Povlsen unsigned int reg, 1316f8a74760SLars Povlsen int *val) 1317f8a74760SLars Povlsen { 1318f8a74760SLars Povlsen int ret = -EOPNOTSUPP; 1319f8a74760SLars Povlsen 1320f8a74760SLars Povlsen if (info->pincfg) { 1321076d9e71SColin Foster u32 regcfg; 1322076d9e71SColin Foster 1323076d9e71SColin Foster ret = regmap_read(info->pincfg, pin, ®cfg); 1324076d9e71SColin Foster if (ret) 1325076d9e71SColin Foster return ret; 1326f8a74760SLars Povlsen 1327f8a74760SLars Povlsen ret = 0; 1328f8a74760SLars Povlsen switch (reg) { 1329f8a74760SLars Povlsen case PINCONF_BIAS: 1330f8a74760SLars Povlsen *val = regcfg & BIAS_BITS; 1331f8a74760SLars Povlsen break; 1332f8a74760SLars Povlsen 1333f8a74760SLars Povlsen case PINCONF_SCHMITT: 1334f8a74760SLars Povlsen *val = regcfg & SCHMITT_BIT; 1335f8a74760SLars Povlsen break; 1336f8a74760SLars Povlsen 1337f8a74760SLars Povlsen case PINCONF_DRIVE_STRENGTH: 1338f8a74760SLars Povlsen *val = regcfg & DRIVE_BITS; 1339f8a74760SLars Povlsen break; 1340f8a74760SLars Povlsen 1341f8a74760SLars Povlsen default: 1342f8a74760SLars Povlsen ret = -EOPNOTSUPP; 1343f8a74760SLars Povlsen break; 1344f8a74760SLars Povlsen } 1345f8a74760SLars Povlsen } 1346f8a74760SLars Povlsen return ret; 1347f8a74760SLars Povlsen } 1348f8a74760SLars Povlsen 1349076d9e71SColin Foster static int ocelot_pincfg_clrsetbits(struct ocelot_pinctrl *info, u32 regaddr, 1350076d9e71SColin Foster u32 clrbits, u32 setbits) 1351076d9e71SColin Foster { 1352076d9e71SColin Foster u32 val; 1353076d9e71SColin Foster int ret; 1354076d9e71SColin Foster 1355076d9e71SColin Foster ret = regmap_read(info->pincfg, regaddr, &val); 1356076d9e71SColin Foster if (ret) 1357076d9e71SColin Foster return ret; 1358076d9e71SColin Foster 1359076d9e71SColin Foster val &= ~clrbits; 1360076d9e71SColin Foster val |= setbits; 1361076d9e71SColin Foster 1362076d9e71SColin Foster ret = regmap_write(info->pincfg, regaddr, val); 1363076d9e71SColin Foster 1364076d9e71SColin Foster return ret; 1365076d9e71SColin Foster } 1366076d9e71SColin Foster 1367f8a74760SLars Povlsen static int ocelot_hw_set_value(struct ocelot_pinctrl *info, 1368f8a74760SLars Povlsen unsigned int pin, 1369f8a74760SLars Povlsen unsigned int reg, 1370f8a74760SLars Povlsen int val) 1371f8a74760SLars Povlsen { 1372f8a74760SLars Povlsen int ret = -EOPNOTSUPP; 1373f8a74760SLars Povlsen 1374f8a74760SLars Povlsen if (info->pincfg) { 1375f8a74760SLars Povlsen 1376f8a74760SLars Povlsen ret = 0; 1377f8a74760SLars Povlsen switch (reg) { 1378f8a74760SLars Povlsen case PINCONF_BIAS: 1379076d9e71SColin Foster ret = ocelot_pincfg_clrsetbits(info, pin, BIAS_BITS, 1380076d9e71SColin Foster val); 1381f8a74760SLars Povlsen break; 1382f8a74760SLars Povlsen 1383f8a74760SLars Povlsen case PINCONF_SCHMITT: 1384076d9e71SColin Foster ret = ocelot_pincfg_clrsetbits(info, pin, SCHMITT_BIT, 1385076d9e71SColin Foster val); 1386f8a74760SLars Povlsen break; 1387f8a74760SLars Povlsen 1388f8a74760SLars Povlsen case PINCONF_DRIVE_STRENGTH: 1389f8a74760SLars Povlsen if (val <= 3) 1390076d9e71SColin Foster ret = ocelot_pincfg_clrsetbits(info, pin, 1391076d9e71SColin Foster DRIVE_BITS, val); 1392f8a74760SLars Povlsen else 1393f8a74760SLars Povlsen ret = -EINVAL; 1394f8a74760SLars Povlsen break; 1395f8a74760SLars Povlsen 1396f8a74760SLars Povlsen default: 1397f8a74760SLars Povlsen ret = -EOPNOTSUPP; 1398f8a74760SLars Povlsen break; 1399f8a74760SLars Povlsen } 1400f8a74760SLars Povlsen } 1401f8a74760SLars Povlsen return ret; 1402f8a74760SLars Povlsen } 1403f8a74760SLars Povlsen 1404f8a74760SLars Povlsen static int ocelot_pinconf_get(struct pinctrl_dev *pctldev, 1405f8a74760SLars Povlsen unsigned int pin, unsigned long *config) 1406f8a74760SLars Povlsen { 1407f8a74760SLars Povlsen struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1408f8a74760SLars Povlsen u32 param = pinconf_to_config_param(*config); 1409f8a74760SLars Povlsen int val, err; 1410f8a74760SLars Povlsen 1411f8a74760SLars Povlsen switch (param) { 1412f8a74760SLars Povlsen case PIN_CONFIG_BIAS_DISABLE: 1413f8a74760SLars Povlsen case PIN_CONFIG_BIAS_PULL_UP: 1414f8a74760SLars Povlsen case PIN_CONFIG_BIAS_PULL_DOWN: 1415f8a74760SLars Povlsen err = ocelot_hw_get_value(info, pin, PINCONF_BIAS, &val); 1416f8a74760SLars Povlsen if (err) 1417f8a74760SLars Povlsen return err; 1418f8a74760SLars Povlsen if (param == PIN_CONFIG_BIAS_DISABLE) 141954515257SKaixu Xia val = (val == 0); 1420f8a74760SLars Povlsen else if (param == PIN_CONFIG_BIAS_PULL_DOWN) 1421f8a74760SLars Povlsen val = (val & BIAS_PD_BIT ? true : false); 1422f8a74760SLars Povlsen else /* PIN_CONFIG_BIAS_PULL_UP */ 1423f8a74760SLars Povlsen val = (val & BIAS_PU_BIT ? true : false); 1424f8a74760SLars Povlsen break; 1425f8a74760SLars Povlsen 1426f8a74760SLars Povlsen case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 1427f8a74760SLars Povlsen err = ocelot_hw_get_value(info, pin, PINCONF_SCHMITT, &val); 1428f8a74760SLars Povlsen if (err) 1429f8a74760SLars Povlsen return err; 1430f8a74760SLars Povlsen 1431f8a74760SLars Povlsen val = (val & SCHMITT_BIT ? true : false); 1432f8a74760SLars Povlsen break; 1433f8a74760SLars Povlsen 1434f8a74760SLars Povlsen case PIN_CONFIG_DRIVE_STRENGTH: 1435f8a74760SLars Povlsen err = ocelot_hw_get_value(info, pin, PINCONF_DRIVE_STRENGTH, 1436f8a74760SLars Povlsen &val); 1437f8a74760SLars Povlsen if (err) 1438f8a74760SLars Povlsen return err; 1439f8a74760SLars Povlsen break; 1440f8a74760SLars Povlsen 1441f8a74760SLars Povlsen case PIN_CONFIG_OUTPUT: 1442f8a74760SLars Povlsen err = regmap_read(info->map, REG(OCELOT_GPIO_OUT, info, pin), 1443f8a74760SLars Povlsen &val); 1444f8a74760SLars Povlsen if (err) 1445f8a74760SLars Povlsen return err; 1446f8a74760SLars Povlsen val = !!(val & BIT(pin % 32)); 1447f8a74760SLars Povlsen break; 1448f8a74760SLars Povlsen 1449f8a74760SLars Povlsen case PIN_CONFIG_INPUT_ENABLE: 1450f8a74760SLars Povlsen case PIN_CONFIG_OUTPUT_ENABLE: 1451f8a74760SLars Povlsen err = regmap_read(info->map, REG(OCELOT_GPIO_OE, info, pin), 1452f8a74760SLars Povlsen &val); 1453f8a74760SLars Povlsen if (err) 1454f8a74760SLars Povlsen return err; 1455f8a74760SLars Povlsen val = val & BIT(pin % 32); 1456f8a74760SLars Povlsen if (param == PIN_CONFIG_OUTPUT_ENABLE) 1457f8a74760SLars Povlsen val = !!val; 1458f8a74760SLars Povlsen else 1459f8a74760SLars Povlsen val = !val; 1460f8a74760SLars Povlsen break; 1461f8a74760SLars Povlsen 1462f8a74760SLars Povlsen default: 1463f8a74760SLars Povlsen return -EOPNOTSUPP; 1464f8a74760SLars Povlsen } 1465f8a74760SLars Povlsen 1466f8a74760SLars Povlsen *config = pinconf_to_config_packed(param, val); 1467f8a74760SLars Povlsen 1468f8a74760SLars Povlsen return 0; 1469f8a74760SLars Povlsen } 1470f8a74760SLars Povlsen 1471f8a74760SLars Povlsen static int ocelot_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 1472f8a74760SLars Povlsen unsigned long *configs, unsigned int num_configs) 1473f8a74760SLars Povlsen { 1474f8a74760SLars Povlsen struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1475f8a74760SLars Povlsen u32 param, arg, p; 1476f8a74760SLars Povlsen int cfg, err = 0; 1477f8a74760SLars Povlsen 1478f8a74760SLars Povlsen for (cfg = 0; cfg < num_configs; cfg++) { 1479f8a74760SLars Povlsen param = pinconf_to_config_param(configs[cfg]); 1480f8a74760SLars Povlsen arg = pinconf_to_config_argument(configs[cfg]); 1481f8a74760SLars Povlsen 1482f8a74760SLars Povlsen switch (param) { 1483f8a74760SLars Povlsen case PIN_CONFIG_BIAS_DISABLE: 1484f8a74760SLars Povlsen case PIN_CONFIG_BIAS_PULL_UP: 1485f8a74760SLars Povlsen case PIN_CONFIG_BIAS_PULL_DOWN: 1486f8a74760SLars Povlsen arg = (param == PIN_CONFIG_BIAS_DISABLE) ? 0 : 1487f8a74760SLars Povlsen (param == PIN_CONFIG_BIAS_PULL_UP) ? BIAS_PU_BIT : 1488f8a74760SLars Povlsen BIAS_PD_BIT; 1489f8a74760SLars Povlsen 1490f8a74760SLars Povlsen err = ocelot_hw_set_value(info, pin, PINCONF_BIAS, arg); 1491f8a74760SLars Povlsen if (err) 1492f8a74760SLars Povlsen goto err; 1493f8a74760SLars Povlsen 1494f8a74760SLars Povlsen break; 1495f8a74760SLars Povlsen 1496f8a74760SLars Povlsen case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 1497f8a74760SLars Povlsen arg = arg ? SCHMITT_BIT : 0; 1498f8a74760SLars Povlsen err = ocelot_hw_set_value(info, pin, PINCONF_SCHMITT, 1499f8a74760SLars Povlsen arg); 1500f8a74760SLars Povlsen if (err) 1501f8a74760SLars Povlsen goto err; 1502f8a74760SLars Povlsen 1503f8a74760SLars Povlsen break; 1504f8a74760SLars Povlsen 1505f8a74760SLars Povlsen case PIN_CONFIG_DRIVE_STRENGTH: 1506f8a74760SLars Povlsen err = ocelot_hw_set_value(info, pin, 1507f8a74760SLars Povlsen PINCONF_DRIVE_STRENGTH, 1508f8a74760SLars Povlsen arg); 1509f8a74760SLars Povlsen if (err) 1510f8a74760SLars Povlsen goto err; 1511f8a74760SLars Povlsen 1512f8a74760SLars Povlsen break; 1513f8a74760SLars Povlsen 1514f8a74760SLars Povlsen case PIN_CONFIG_OUTPUT_ENABLE: 1515f8a74760SLars Povlsen case PIN_CONFIG_INPUT_ENABLE: 1516f8a74760SLars Povlsen case PIN_CONFIG_OUTPUT: 1517f8a74760SLars Povlsen p = pin % 32; 1518f8a74760SLars Povlsen if (arg) 1519f8a74760SLars Povlsen regmap_write(info->map, 1520f8a74760SLars Povlsen REG(OCELOT_GPIO_OUT_SET, info, 1521f8a74760SLars Povlsen pin), 1522f8a74760SLars Povlsen BIT(p)); 1523f8a74760SLars Povlsen else 1524f8a74760SLars Povlsen regmap_write(info->map, 1525f8a74760SLars Povlsen REG(OCELOT_GPIO_OUT_CLR, info, 1526f8a74760SLars Povlsen pin), 1527f8a74760SLars Povlsen BIT(p)); 1528f8a74760SLars Povlsen regmap_update_bits(info->map, 1529f8a74760SLars Povlsen REG(OCELOT_GPIO_OE, info, pin), 1530f8a74760SLars Povlsen BIT(p), 1531f8a74760SLars Povlsen param == PIN_CONFIG_INPUT_ENABLE ? 1532f8a74760SLars Povlsen 0 : BIT(p)); 1533f8a74760SLars Povlsen break; 1534f8a74760SLars Povlsen 1535f8a74760SLars Povlsen default: 1536f8a74760SLars Povlsen err = -EOPNOTSUPP; 1537f8a74760SLars Povlsen } 1538f8a74760SLars Povlsen } 1539f8a74760SLars Povlsen err: 1540f8a74760SLars Povlsen return err; 1541f8a74760SLars Povlsen } 1542f8a74760SLars Povlsen 1543f8a74760SLars Povlsen static const struct pinconf_ops ocelot_confops = { 1544f8a74760SLars Povlsen .is_generic = true, 1545f8a74760SLars Povlsen .pin_config_get = ocelot_pinconf_get, 1546f8a74760SLars Povlsen .pin_config_set = ocelot_pinconf_set, 1547f8a74760SLars Povlsen .pin_config_config_dbg_show = pinconf_generic_dump_config, 1548f8a74760SLars Povlsen }; 1549f8a74760SLars Povlsen 1550ce8dc094SAlexandre Belloni static const struct pinctrl_ops ocelot_pctl_ops = { 1551ce8dc094SAlexandre Belloni .get_groups_count = ocelot_pctl_get_groups_count, 1552ce8dc094SAlexandre Belloni .get_group_name = ocelot_pctl_get_group_name, 1553ce8dc094SAlexandre Belloni .get_group_pins = ocelot_pctl_get_group_pins, 1554ce8dc094SAlexandre Belloni .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, 1555ce8dc094SAlexandre Belloni .dt_free_map = pinconf_generic_dt_free_map, 1556ce8dc094SAlexandre Belloni }; 1557ce8dc094SAlexandre Belloni 15588f27440dSLars Povlsen static struct pinctrl_desc luton_desc = { 15598f27440dSLars Povlsen .name = "luton-pinctrl", 15608f27440dSLars Povlsen .pins = luton_pins, 15618f27440dSLars Povlsen .npins = ARRAY_SIZE(luton_pins), 15628f27440dSLars Povlsen .pctlops = &ocelot_pctl_ops, 15638f27440dSLars Povlsen .pmxops = &ocelot_pmx_ops, 15648f27440dSLars Povlsen .owner = THIS_MODULE, 15658f27440dSLars Povlsen }; 15668f27440dSLars Povlsen 15676e6347e2SLars Povlsen static struct pinctrl_desc serval_desc = { 15686e6347e2SLars Povlsen .name = "serval-pinctrl", 15696e6347e2SLars Povlsen .pins = serval_pins, 15706e6347e2SLars Povlsen .npins = ARRAY_SIZE(serval_pins), 15716e6347e2SLars Povlsen .pctlops = &ocelot_pctl_ops, 15726e6347e2SLars Povlsen .pmxops = &ocelot_pmx_ops, 15736e6347e2SLars Povlsen .owner = THIS_MODULE, 15746e6347e2SLars Povlsen }; 15756e6347e2SLars Povlsen 1576ce8dc094SAlexandre Belloni static struct pinctrl_desc ocelot_desc = { 1577ce8dc094SAlexandre Belloni .name = "ocelot-pinctrl", 1578ce8dc094SAlexandre Belloni .pins = ocelot_pins, 1579ce8dc094SAlexandre Belloni .npins = ARRAY_SIZE(ocelot_pins), 1580ce8dc094SAlexandre Belloni .pctlops = &ocelot_pctl_ops, 1581ce8dc094SAlexandre Belloni .pmxops = &ocelot_pmx_ops, 1582ce8dc094SAlexandre Belloni .owner = THIS_MODULE, 1583ce8dc094SAlexandre Belloni }; 1584ce8dc094SAlexandre Belloni 1585da801ab5SAlexandre Belloni static struct pinctrl_desc jaguar2_desc = { 1586da801ab5SAlexandre Belloni .name = "jaguar2-pinctrl", 1587da801ab5SAlexandre Belloni .pins = jaguar2_pins, 1588da801ab5SAlexandre Belloni .npins = ARRAY_SIZE(jaguar2_pins), 1589da801ab5SAlexandre Belloni .pctlops = &ocelot_pctl_ops, 1590da801ab5SAlexandre Belloni .pmxops = &ocelot_pmx_ops, 1591da801ab5SAlexandre Belloni .owner = THIS_MODULE, 1592da801ab5SAlexandre Belloni }; 1593da801ab5SAlexandre Belloni 15948fc0bfcdSHoratiu Vultur static struct pinctrl_desc servalt_desc = { 15958fc0bfcdSHoratiu Vultur .name = "servalt-pinctrl", 15968fc0bfcdSHoratiu Vultur .pins = servalt_pins, 15978fc0bfcdSHoratiu Vultur .npins = ARRAY_SIZE(servalt_pins), 15988fc0bfcdSHoratiu Vultur .pctlops = &ocelot_pctl_ops, 15998fc0bfcdSHoratiu Vultur .pmxops = &ocelot_pmx_ops, 16008fc0bfcdSHoratiu Vultur .owner = THIS_MODULE, 16018fc0bfcdSHoratiu Vultur }; 16028fc0bfcdSHoratiu Vultur 1603f8a74760SLars Povlsen static struct pinctrl_desc sparx5_desc = { 1604f8a74760SLars Povlsen .name = "sparx5-pinctrl", 1605f8a74760SLars Povlsen .pins = sparx5_pins, 1606f8a74760SLars Povlsen .npins = ARRAY_SIZE(sparx5_pins), 1607f8a74760SLars Povlsen .pctlops = &ocelot_pctl_ops, 1608f8a74760SLars Povlsen .pmxops = &ocelot_pmx_ops, 1609f8a74760SLars Povlsen .confops = &ocelot_confops, 1610f8a74760SLars Povlsen .owner = THIS_MODULE, 1611f8a74760SLars Povlsen }; 1612f8a74760SLars Povlsen 1613531d6ab3SKavyasree Kotagiri static struct pinctrl_desc lan966x_desc = { 1614531d6ab3SKavyasree Kotagiri .name = "lan966x-pinctrl", 1615531d6ab3SKavyasree Kotagiri .pins = lan966x_pins, 1616531d6ab3SKavyasree Kotagiri .npins = ARRAY_SIZE(lan966x_pins), 1617531d6ab3SKavyasree Kotagiri .pctlops = &ocelot_pctl_ops, 1618531d6ab3SKavyasree Kotagiri .pmxops = &lan966x_pmx_ops, 1619531d6ab3SKavyasree Kotagiri .confops = &ocelot_confops, 1620531d6ab3SKavyasree Kotagiri .owner = THIS_MODULE, 1621531d6ab3SKavyasree Kotagiri }; 1622531d6ab3SKavyasree Kotagiri 1623ce8dc094SAlexandre Belloni static int ocelot_create_group_func_map(struct device *dev, 1624ce8dc094SAlexandre Belloni struct ocelot_pinctrl *info) 1625ce8dc094SAlexandre Belloni { 1626ce8dc094SAlexandre Belloni int f, npins, i; 1627da801ab5SAlexandre Belloni u8 *pins = kcalloc(info->desc->npins, sizeof(u8), GFP_KERNEL); 1628da801ab5SAlexandre Belloni 1629da801ab5SAlexandre Belloni if (!pins) 1630da801ab5SAlexandre Belloni return -ENOMEM; 1631ce8dc094SAlexandre Belloni 1632ce8dc094SAlexandre Belloni for (f = 0; f < FUNC_MAX; f++) { 1633da801ab5SAlexandre Belloni for (npins = 0, i = 0; i < info->desc->npins; i++) { 1634da801ab5SAlexandre Belloni if (ocelot_pin_function_idx(info, i, f) >= 0) 1635ce8dc094SAlexandre Belloni pins[npins++] = i; 1636ce8dc094SAlexandre Belloni } 1637ce8dc094SAlexandre Belloni 1638da801ab5SAlexandre Belloni if (!npins) 1639da801ab5SAlexandre Belloni continue; 1640da801ab5SAlexandre Belloni 1641ce8dc094SAlexandre Belloni info->func[f].ngroups = npins; 1642da801ab5SAlexandre Belloni info->func[f].groups = devm_kcalloc(dev, npins, sizeof(char *), 1643ce8dc094SAlexandre Belloni GFP_KERNEL); 1644da801ab5SAlexandre Belloni if (!info->func[f].groups) { 1645da801ab5SAlexandre Belloni kfree(pins); 1646ce8dc094SAlexandre Belloni return -ENOMEM; 1647da801ab5SAlexandre Belloni } 1648ce8dc094SAlexandre Belloni 1649ce8dc094SAlexandre Belloni for (i = 0; i < npins; i++) 1650f8a74760SLars Povlsen info->func[f].groups[i] = 1651f8a74760SLars Povlsen info->desc->pins[pins[i]].name; 1652ce8dc094SAlexandre Belloni } 1653ce8dc094SAlexandre Belloni 1654da801ab5SAlexandre Belloni kfree(pins); 1655da801ab5SAlexandre Belloni 1656ce8dc094SAlexandre Belloni return 0; 1657ce8dc094SAlexandre Belloni } 1658ce8dc094SAlexandre Belloni 1659ce8dc094SAlexandre Belloni static int ocelot_pinctrl_register(struct platform_device *pdev, 1660ce8dc094SAlexandre Belloni struct ocelot_pinctrl *info) 1661ce8dc094SAlexandre Belloni { 1662ce8dc094SAlexandre Belloni int ret; 1663ce8dc094SAlexandre Belloni 1664ce8dc094SAlexandre Belloni ret = ocelot_create_group_func_map(&pdev->dev, info); 1665ce8dc094SAlexandre Belloni if (ret) { 1666ce8dc094SAlexandre Belloni dev_err(&pdev->dev, "Unable to create group func map.\n"); 1667ce8dc094SAlexandre Belloni return ret; 1668ce8dc094SAlexandre Belloni } 1669ce8dc094SAlexandre Belloni 1670da801ab5SAlexandre Belloni info->pctl = devm_pinctrl_register(&pdev->dev, info->desc, info); 1671ce8dc094SAlexandre Belloni if (IS_ERR(info->pctl)) { 1672ce8dc094SAlexandre Belloni dev_err(&pdev->dev, "Failed to register pinctrl\n"); 1673ce8dc094SAlexandre Belloni return PTR_ERR(info->pctl); 1674ce8dc094SAlexandre Belloni } 1675ce8dc094SAlexandre Belloni 1676ce8dc094SAlexandre Belloni return 0; 1677ce8dc094SAlexandre Belloni } 1678ce8dc094SAlexandre Belloni 1679ce8dc094SAlexandre Belloni static int ocelot_gpio_get(struct gpio_chip *chip, unsigned int offset) 1680ce8dc094SAlexandre Belloni { 1681ce8dc094SAlexandre Belloni struct ocelot_pinctrl *info = gpiochip_get_data(chip); 1682ce8dc094SAlexandre Belloni unsigned int val; 1683ce8dc094SAlexandre Belloni 1684da801ab5SAlexandre Belloni regmap_read(info->map, REG(OCELOT_GPIO_IN, info, offset), &val); 1685ce8dc094SAlexandre Belloni 1686da801ab5SAlexandre Belloni return !!(val & BIT(offset % 32)); 1687ce8dc094SAlexandre Belloni } 1688ce8dc094SAlexandre Belloni 1689ce8dc094SAlexandre Belloni static void ocelot_gpio_set(struct gpio_chip *chip, unsigned int offset, 1690ce8dc094SAlexandre Belloni int value) 1691ce8dc094SAlexandre Belloni { 1692ce8dc094SAlexandre Belloni struct ocelot_pinctrl *info = gpiochip_get_data(chip); 1693ce8dc094SAlexandre Belloni 1694ce8dc094SAlexandre Belloni if (value) 1695da801ab5SAlexandre Belloni regmap_write(info->map, REG(OCELOT_GPIO_OUT_SET, info, offset), 1696da801ab5SAlexandre Belloni BIT(offset % 32)); 1697ce8dc094SAlexandre Belloni else 1698da801ab5SAlexandre Belloni regmap_write(info->map, REG(OCELOT_GPIO_OUT_CLR, info, offset), 1699da801ab5SAlexandre Belloni BIT(offset % 32)); 1700ce8dc094SAlexandre Belloni } 1701ce8dc094SAlexandre Belloni 1702ce8dc094SAlexandre Belloni static int ocelot_gpio_get_direction(struct gpio_chip *chip, 1703ce8dc094SAlexandre Belloni unsigned int offset) 1704ce8dc094SAlexandre Belloni { 1705ce8dc094SAlexandre Belloni struct ocelot_pinctrl *info = gpiochip_get_data(chip); 1706ce8dc094SAlexandre Belloni unsigned int val; 1707ce8dc094SAlexandre Belloni 1708da801ab5SAlexandre Belloni regmap_read(info->map, REG(OCELOT_GPIO_OE, info, offset), &val); 1709ce8dc094SAlexandre Belloni 17103c827873SMatti Vaittinen if (val & BIT(offset % 32)) 17113c827873SMatti Vaittinen return GPIO_LINE_DIRECTION_OUT; 17123c827873SMatti Vaittinen 17133c827873SMatti Vaittinen return GPIO_LINE_DIRECTION_IN; 1714ce8dc094SAlexandre Belloni } 1715ce8dc094SAlexandre Belloni 1716ce8dc094SAlexandre Belloni static int ocelot_gpio_direction_input(struct gpio_chip *chip, 1717ce8dc094SAlexandre Belloni unsigned int offset) 1718ce8dc094SAlexandre Belloni { 1719ce8dc094SAlexandre Belloni return pinctrl_gpio_direction_input(chip->base + offset); 1720ce8dc094SAlexandre Belloni } 1721ce8dc094SAlexandre Belloni 1722ce8dc094SAlexandre Belloni static int ocelot_gpio_direction_output(struct gpio_chip *chip, 1723ce8dc094SAlexandre Belloni unsigned int offset, int value) 1724ce8dc094SAlexandre Belloni { 1725ce8dc094SAlexandre Belloni struct ocelot_pinctrl *info = gpiochip_get_data(chip); 1726da801ab5SAlexandre Belloni unsigned int pin = BIT(offset % 32); 1727ce8dc094SAlexandre Belloni 1728ce8dc094SAlexandre Belloni if (value) 1729da801ab5SAlexandre Belloni regmap_write(info->map, REG(OCELOT_GPIO_OUT_SET, info, offset), 1730da801ab5SAlexandre Belloni pin); 1731ce8dc094SAlexandre Belloni else 1732da801ab5SAlexandre Belloni regmap_write(info->map, REG(OCELOT_GPIO_OUT_CLR, info, offset), 1733da801ab5SAlexandre Belloni pin); 1734ce8dc094SAlexandre Belloni 1735ce8dc094SAlexandre Belloni return pinctrl_gpio_direction_output(chip->base + offset); 1736ce8dc094SAlexandre Belloni } 1737ce8dc094SAlexandre Belloni 1738ce8dc094SAlexandre Belloni static const struct gpio_chip ocelot_gpiolib_chip = { 1739ce8dc094SAlexandre Belloni .request = gpiochip_generic_request, 1740ce8dc094SAlexandre Belloni .free = gpiochip_generic_free, 1741ce8dc094SAlexandre Belloni .set = ocelot_gpio_set, 1742ce8dc094SAlexandre Belloni .get = ocelot_gpio_get, 1743ce8dc094SAlexandre Belloni .get_direction = ocelot_gpio_get_direction, 1744ce8dc094SAlexandre Belloni .direction_input = ocelot_gpio_direction_input, 1745ce8dc094SAlexandre Belloni .direction_output = ocelot_gpio_direction_output, 1746ce8dc094SAlexandre Belloni .owner = THIS_MODULE, 1747ce8dc094SAlexandre Belloni }; 1748ce8dc094SAlexandre Belloni 1749be36abb7SQuentin Schulz static void ocelot_irq_mask(struct irq_data *data) 1750be36abb7SQuentin Schulz { 1751be36abb7SQuentin Schulz struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 1752be36abb7SQuentin Schulz struct ocelot_pinctrl *info = gpiochip_get_data(chip); 1753be36abb7SQuentin Schulz unsigned int gpio = irqd_to_hwirq(data); 1754be36abb7SQuentin Schulz 1755da801ab5SAlexandre Belloni regmap_update_bits(info->map, REG(OCELOT_GPIO_INTR_ENA, info, gpio), 1756da801ab5SAlexandre Belloni BIT(gpio % 32), 0); 1757be36abb7SQuentin Schulz } 1758be36abb7SQuentin Schulz 1759be36abb7SQuentin Schulz static void ocelot_irq_unmask(struct irq_data *data) 1760be36abb7SQuentin Schulz { 1761be36abb7SQuentin Schulz struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 1762be36abb7SQuentin Schulz struct ocelot_pinctrl *info = gpiochip_get_data(chip); 1763be36abb7SQuentin Schulz unsigned int gpio = irqd_to_hwirq(data); 1764be36abb7SQuentin Schulz 1765da801ab5SAlexandre Belloni regmap_update_bits(info->map, REG(OCELOT_GPIO_INTR_ENA, info, gpio), 1766da801ab5SAlexandre Belloni BIT(gpio % 32), BIT(gpio % 32)); 1767be36abb7SQuentin Schulz } 1768be36abb7SQuentin Schulz 1769be36abb7SQuentin Schulz static void ocelot_irq_ack(struct irq_data *data) 1770be36abb7SQuentin Schulz { 1771be36abb7SQuentin Schulz struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 1772be36abb7SQuentin Schulz struct ocelot_pinctrl *info = gpiochip_get_data(chip); 1773be36abb7SQuentin Schulz unsigned int gpio = irqd_to_hwirq(data); 1774be36abb7SQuentin Schulz 1775da801ab5SAlexandre Belloni regmap_write_bits(info->map, REG(OCELOT_GPIO_INTR, info, gpio), 1776da801ab5SAlexandre Belloni BIT(gpio % 32), BIT(gpio % 32)); 1777be36abb7SQuentin Schulz } 1778be36abb7SQuentin Schulz 1779be36abb7SQuentin Schulz static int ocelot_irq_set_type(struct irq_data *data, unsigned int type); 1780be36abb7SQuentin Schulz 1781be36abb7SQuentin Schulz static struct irq_chip ocelot_eoi_irqchip = { 1782be36abb7SQuentin Schulz .name = "gpio", 1783be36abb7SQuentin Schulz .irq_mask = ocelot_irq_mask, 1784be36abb7SQuentin Schulz .irq_eoi = ocelot_irq_ack, 1785be36abb7SQuentin Schulz .irq_unmask = ocelot_irq_unmask, 1786be36abb7SQuentin Schulz .flags = IRQCHIP_EOI_THREADED | IRQCHIP_EOI_IF_HANDLED, 1787be36abb7SQuentin Schulz .irq_set_type = ocelot_irq_set_type, 1788be36abb7SQuentin Schulz }; 1789be36abb7SQuentin Schulz 1790be36abb7SQuentin Schulz static struct irq_chip ocelot_irqchip = { 1791be36abb7SQuentin Schulz .name = "gpio", 1792be36abb7SQuentin Schulz .irq_mask = ocelot_irq_mask, 1793be36abb7SQuentin Schulz .irq_ack = ocelot_irq_ack, 1794be36abb7SQuentin Schulz .irq_unmask = ocelot_irq_unmask, 1795be36abb7SQuentin Schulz .irq_set_type = ocelot_irq_set_type, 1796be36abb7SQuentin Schulz }; 1797be36abb7SQuentin Schulz 1798be36abb7SQuentin Schulz static int ocelot_irq_set_type(struct irq_data *data, unsigned int type) 1799be36abb7SQuentin Schulz { 1800be36abb7SQuentin Schulz type &= IRQ_TYPE_SENSE_MASK; 1801be36abb7SQuentin Schulz 1802be36abb7SQuentin Schulz if (!(type & (IRQ_TYPE_EDGE_BOTH | IRQ_TYPE_LEVEL_HIGH))) 1803be36abb7SQuentin Schulz return -EINVAL; 1804be36abb7SQuentin Schulz 1805be36abb7SQuentin Schulz if (type & IRQ_TYPE_LEVEL_HIGH) 1806be36abb7SQuentin Schulz irq_set_chip_handler_name_locked(data, &ocelot_eoi_irqchip, 1807be36abb7SQuentin Schulz handle_fasteoi_irq, NULL); 1808be36abb7SQuentin Schulz if (type & IRQ_TYPE_EDGE_BOTH) 1809be36abb7SQuentin Schulz irq_set_chip_handler_name_locked(data, &ocelot_irqchip, 1810be36abb7SQuentin Schulz handle_edge_irq, NULL); 1811be36abb7SQuentin Schulz 1812be36abb7SQuentin Schulz return 0; 1813be36abb7SQuentin Schulz } 1814be36abb7SQuentin Schulz 1815be36abb7SQuentin Schulz static void ocelot_irq_handler(struct irq_desc *desc) 1816be36abb7SQuentin Schulz { 1817be36abb7SQuentin Schulz struct irq_chip *parent_chip = irq_desc_get_chip(desc); 1818be36abb7SQuentin Schulz struct gpio_chip *chip = irq_desc_get_handler_data(desc); 1819be36abb7SQuentin Schulz struct ocelot_pinctrl *info = gpiochip_get_data(chip); 18200b47afc6SLars Povlsen unsigned int id_reg = OCELOT_GPIO_INTR_IDENT * info->stride; 1821da801ab5SAlexandre Belloni unsigned int reg = 0, irq, i; 1822be36abb7SQuentin Schulz unsigned long irqs; 1823be36abb7SQuentin Schulz 1824da801ab5SAlexandre Belloni for (i = 0; i < info->stride; i++) { 18250b47afc6SLars Povlsen regmap_read(info->map, id_reg + 4 * i, ®); 1826be36abb7SQuentin Schulz if (!reg) 1827da801ab5SAlexandre Belloni continue; 1828be36abb7SQuentin Schulz 1829be36abb7SQuentin Schulz chained_irq_enter(parent_chip, desc); 1830be36abb7SQuentin Schulz 1831be36abb7SQuentin Schulz irqs = reg; 1832be36abb7SQuentin Schulz 1833da801ab5SAlexandre Belloni for_each_set_bit(irq, &irqs, 1834da801ab5SAlexandre Belloni min(32U, info->desc->npins - 32 * i)) 1835a9cb09b7SMarc Zyngier generic_handle_domain_irq(chip->irq.domain, irq + 32 * i); 1836be36abb7SQuentin Schulz 1837be36abb7SQuentin Schulz chained_irq_exit(parent_chip, desc); 1838be36abb7SQuentin Schulz } 1839da801ab5SAlexandre Belloni } 1840be36abb7SQuentin Schulz 1841ce8dc094SAlexandre Belloni static int ocelot_gpiochip_register(struct platform_device *pdev, 1842ce8dc094SAlexandre Belloni struct ocelot_pinctrl *info) 1843ce8dc094SAlexandre Belloni { 1844ce8dc094SAlexandre Belloni struct gpio_chip *gc; 1845d874becaSLinus Walleij struct gpio_irq_chip *girq; 184617f2c8d3SQinglang Miao int irq; 1847ce8dc094SAlexandre Belloni 1848ce8dc094SAlexandre Belloni info->gpio_chip = ocelot_gpiolib_chip; 1849ce8dc094SAlexandre Belloni 1850ce8dc094SAlexandre Belloni gc = &info->gpio_chip; 1851da801ab5SAlexandre Belloni gc->ngpio = info->desc->npins; 1852ce8dc094SAlexandre Belloni gc->parent = &pdev->dev; 1853a159c2b4SColin Foster gc->base = -1; 1854ce8dc094SAlexandre Belloni gc->label = "ocelot-gpio"; 1855ce8dc094SAlexandre Belloni 1856d1f2c82fSHoratiu Vultur irq = platform_get_irq_optional(pdev, 0); 1857d1f2c82fSHoratiu Vultur if (irq > 0) { 1858d874becaSLinus Walleij girq = &gc->irq; 1859d874becaSLinus Walleij girq->chip = &ocelot_irqchip; 1860d874becaSLinus Walleij girq->parent_handler = ocelot_irq_handler; 1861d874becaSLinus Walleij girq->num_parents = 1; 1862550713e3SLars Povlsen girq->parents = devm_kcalloc(&pdev->dev, 1, 1863550713e3SLars Povlsen sizeof(*girq->parents), 1864d874becaSLinus Walleij GFP_KERNEL); 1865d874becaSLinus Walleij if (!girq->parents) 1866d874becaSLinus Walleij return -ENOMEM; 1867d874becaSLinus Walleij girq->parents[0] = irq; 1868d874becaSLinus Walleij girq->default_type = IRQ_TYPE_NONE; 1869d874becaSLinus Walleij girq->handler = handle_edge_irq; 1870550713e3SLars Povlsen } 1871d874becaSLinus Walleij 187217f2c8d3SQinglang Miao return devm_gpiochip_add_data(&pdev->dev, gc, info); 1873ce8dc094SAlexandre Belloni } 1874ce8dc094SAlexandre Belloni 1875ce8dc094SAlexandre Belloni static const struct of_device_id ocelot_pinctrl_of_match[] = { 18768f27440dSLars Povlsen { .compatible = "mscc,luton-pinctrl", .data = &luton_desc }, 18776e6347e2SLars Povlsen { .compatible = "mscc,serval-pinctrl", .data = &serval_desc }, 1878da801ab5SAlexandre Belloni { .compatible = "mscc,ocelot-pinctrl", .data = &ocelot_desc }, 1879da801ab5SAlexandre Belloni { .compatible = "mscc,jaguar2-pinctrl", .data = &jaguar2_desc }, 18808fc0bfcdSHoratiu Vultur { .compatible = "mscc,servalt-pinctrl", .data = &servalt_desc }, 1881f8a74760SLars Povlsen { .compatible = "microchip,sparx5-pinctrl", .data = &sparx5_desc }, 1882531d6ab3SKavyasree Kotagiri { .compatible = "microchip,lan966x-pinctrl", .data = &lan966x_desc }, 1883ce8dc094SAlexandre Belloni {}, 1884ce8dc094SAlexandre Belloni }; 1885ce8dc094SAlexandre Belloni 1886076d9e71SColin Foster static struct regmap *ocelot_pinctrl_create_pincfg(struct platform_device *pdev) 1887076d9e71SColin Foster { 1888076d9e71SColin Foster void __iomem *base; 1889076d9e71SColin Foster 1890076d9e71SColin Foster const struct regmap_config regmap_config = { 1891076d9e71SColin Foster .reg_bits = 32, 1892076d9e71SColin Foster .val_bits = 32, 1893076d9e71SColin Foster .reg_stride = 4, 1894076d9e71SColin Foster .max_register = 32, 1895359afd90SMichael Walle .name = "pincfg", 1896076d9e71SColin Foster }; 1897076d9e71SColin Foster 189894ef3297SMichael Walle base = devm_platform_ioremap_resource(pdev, 1); 1899076d9e71SColin Foster if (IS_ERR(base)) { 1900076d9e71SColin Foster dev_dbg(&pdev->dev, "Failed to ioremap config registers (no extended pinconf)\n"); 1901076d9e71SColin Foster return NULL; 1902076d9e71SColin Foster } 1903076d9e71SColin Foster 1904076d9e71SColin Foster return devm_regmap_init_mmio(&pdev->dev, base, ®map_config); 1905076d9e71SColin Foster } 1906076d9e71SColin Foster 1907ce3e7f0eSColin Ian King static int ocelot_pinctrl_probe(struct platform_device *pdev) 1908ce8dc094SAlexandre Belloni { 1909ce8dc094SAlexandre Belloni struct device *dev = &pdev->dev; 1910ce8dc094SAlexandre Belloni struct ocelot_pinctrl *info; 1911076d9e71SColin Foster struct regmap *pincfg; 1912ce8dc094SAlexandre Belloni void __iomem *base; 1913ce8dc094SAlexandre Belloni int ret; 1914da801ab5SAlexandre Belloni struct regmap_config regmap_config = { 1915da801ab5SAlexandre Belloni .reg_bits = 32, 1916da801ab5SAlexandre Belloni .val_bits = 32, 1917da801ab5SAlexandre Belloni .reg_stride = 4, 1918da801ab5SAlexandre Belloni }; 1919ce8dc094SAlexandre Belloni 1920ce8dc094SAlexandre Belloni info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL); 1921ce8dc094SAlexandre Belloni if (!info) 1922ce8dc094SAlexandre Belloni return -ENOMEM; 1923ce8dc094SAlexandre Belloni 1924da801ab5SAlexandre Belloni info->desc = (struct pinctrl_desc *)device_get_match_data(dev); 1925da801ab5SAlexandre Belloni 1926ce8dc094SAlexandre Belloni base = devm_ioremap_resource(dev, 1927ce8dc094SAlexandre Belloni platform_get_resource(pdev, IORESOURCE_MEM, 0)); 19280f9facdbSZhen Lei if (IS_ERR(base)) 1929ce8dc094SAlexandre Belloni return PTR_ERR(base); 1930ce8dc094SAlexandre Belloni 1931da801ab5SAlexandre Belloni info->stride = 1 + (info->desc->npins - 1) / 32; 1932f8a74760SLars Povlsen 1933da801ab5SAlexandre Belloni regmap_config.max_register = OCELOT_GPIO_SD_MAP * info->stride + 15 * 4; 1934da801ab5SAlexandre Belloni 1935da801ab5SAlexandre Belloni info->map = devm_regmap_init_mmio(dev, base, ®map_config); 1936ce8dc094SAlexandre Belloni if (IS_ERR(info->map)) { 1937ce8dc094SAlexandre Belloni dev_err(dev, "Failed to create regmap\n"); 1938ce8dc094SAlexandre Belloni return PTR_ERR(info->map); 1939ce8dc094SAlexandre Belloni } 1940ce8dc094SAlexandre Belloni dev_set_drvdata(dev, info->map); 1941ce8dc094SAlexandre Belloni info->dev = dev; 1942ce8dc094SAlexandre Belloni 1943f8a74760SLars Povlsen /* Pinconf registers */ 1944f8a74760SLars Povlsen if (info->desc->confops) { 1945076d9e71SColin Foster pincfg = ocelot_pinctrl_create_pincfg(pdev); 1946076d9e71SColin Foster if (IS_ERR(pincfg)) 1947076d9e71SColin Foster dev_dbg(dev, "Failed to create pincfg regmap\n"); 1948f8a74760SLars Povlsen else 1949076d9e71SColin Foster info->pincfg = pincfg; 1950f8a74760SLars Povlsen } 1951f8a74760SLars Povlsen 1952ce8dc094SAlexandre Belloni ret = ocelot_pinctrl_register(pdev, info); 1953ce8dc094SAlexandre Belloni if (ret) 1954ce8dc094SAlexandre Belloni return ret; 1955ce8dc094SAlexandre Belloni 1956ce8dc094SAlexandre Belloni ret = ocelot_gpiochip_register(pdev, info); 1957ce8dc094SAlexandre Belloni if (ret) 1958ce8dc094SAlexandre Belloni return ret; 1959ce8dc094SAlexandre Belloni 1960f8a74760SLars Povlsen dev_info(dev, "driver registered\n"); 1961f8a74760SLars Povlsen 1962ce8dc094SAlexandre Belloni return 0; 1963ce8dc094SAlexandre Belloni } 1964ce8dc094SAlexandre Belloni 1965ce8dc094SAlexandre Belloni static struct platform_driver ocelot_pinctrl_driver = { 1966ce8dc094SAlexandre Belloni .driver = { 1967ce8dc094SAlexandre Belloni .name = "pinctrl-ocelot", 1968ce8dc094SAlexandre Belloni .of_match_table = of_match_ptr(ocelot_pinctrl_of_match), 1969ce8dc094SAlexandre Belloni .suppress_bind_attrs = true, 1970ce8dc094SAlexandre Belloni }, 1971ce8dc094SAlexandre Belloni .probe = ocelot_pinctrl_probe, 1972ce8dc094SAlexandre Belloni }; 1973ce8dc094SAlexandre Belloni builtin_platform_driver(ocelot_pinctrl_driver); 1974