1ce8dc094SAlexandre Belloni // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2ce8dc094SAlexandre Belloni /* 3ce8dc094SAlexandre Belloni * Microsemi SoCs pinctrl driver 4ce8dc094SAlexandre Belloni * 5ce8dc094SAlexandre Belloni * Author: <alexandre.belloni@free-electrons.com> 6ce8dc094SAlexandre Belloni * License: Dual MIT/GPL 7ce8dc094SAlexandre Belloni * Copyright (c) 2017 Microsemi Corporation 8ce8dc094SAlexandre Belloni */ 9ce8dc094SAlexandre Belloni 10ce8dc094SAlexandre Belloni #include <linux/gpio/driver.h> 11ce8dc094SAlexandre Belloni #include <linux/interrupt.h> 12ce8dc094SAlexandre Belloni #include <linux/io.h> 13ce8dc094SAlexandre Belloni #include <linux/of_device.h> 14be36abb7SQuentin Schulz #include <linux/of_irq.h> 15ce8dc094SAlexandre Belloni #include <linux/of_platform.h> 16ce8dc094SAlexandre Belloni #include <linux/pinctrl/pinctrl.h> 17ce8dc094SAlexandre Belloni #include <linux/pinctrl/pinmux.h> 18ce8dc094SAlexandre Belloni #include <linux/pinctrl/pinconf.h> 19ce8dc094SAlexandre Belloni #include <linux/pinctrl/pinconf-generic.h> 20ce8dc094SAlexandre Belloni #include <linux/platform_device.h> 21ce8dc094SAlexandre Belloni #include <linux/regmap.h> 22453200afSMichael Walle #include <linux/reset.h> 23ce8dc094SAlexandre Belloni #include <linux/slab.h> 24ce8dc094SAlexandre Belloni 25ce8dc094SAlexandre Belloni #include "core.h" 26ce8dc094SAlexandre Belloni #include "pinconf.h" 27ce8dc094SAlexandre Belloni #include "pinmux.h" 28ce8dc094SAlexandre Belloni 29f8a74760SLars Povlsen #define ocelot_clrsetbits(addr, clear, set) \ 30f8a74760SLars Povlsen writel((readl(addr) & ~(clear)) | (set), (addr)) 31f8a74760SLars Povlsen 32f8a74760SLars Povlsen enum { 33f8a74760SLars Povlsen PINCONF_BIAS, 34f8a74760SLars Povlsen PINCONF_SCHMITT, 35f8a74760SLars Povlsen PINCONF_DRIVE_STRENGTH, 36f8a74760SLars Povlsen }; 37f8a74760SLars Povlsen 38f8a74760SLars Povlsen /* GPIO standard registers */ 39ce8dc094SAlexandre Belloni #define OCELOT_GPIO_OUT_SET 0x0 40ce8dc094SAlexandre Belloni #define OCELOT_GPIO_OUT_CLR 0x4 41ce8dc094SAlexandre Belloni #define OCELOT_GPIO_OUT 0x8 42ce8dc094SAlexandre Belloni #define OCELOT_GPIO_IN 0xc 43ce8dc094SAlexandre Belloni #define OCELOT_GPIO_OE 0x10 44ce8dc094SAlexandre Belloni #define OCELOT_GPIO_INTR 0x14 45ce8dc094SAlexandre Belloni #define OCELOT_GPIO_INTR_ENA 0x18 46ce8dc094SAlexandre Belloni #define OCELOT_GPIO_INTR_IDENT 0x1c 47ce8dc094SAlexandre Belloni #define OCELOT_GPIO_ALT0 0x20 48ce8dc094SAlexandre Belloni #define OCELOT_GPIO_ALT1 0x24 49ce8dc094SAlexandre Belloni #define OCELOT_GPIO_SD_MAP 0x28 50ce8dc094SAlexandre Belloni 51ce8dc094SAlexandre Belloni #define OCELOT_FUNC_PER_PIN 4 52ce8dc094SAlexandre Belloni 53ce8dc094SAlexandre Belloni enum { 54531d6ab3SKavyasree Kotagiri FUNC_CAN0_a, 55531d6ab3SKavyasree Kotagiri FUNC_CAN0_b, 56531d6ab3SKavyasree Kotagiri FUNC_CAN1, 57bf3e7f49SMichael Walle FUNC_CLKMON, 58ce8dc094SAlexandre Belloni FUNC_NONE, 59531d6ab3SKavyasree Kotagiri FUNC_FC0_a, 60531d6ab3SKavyasree Kotagiri FUNC_FC0_b, 61531d6ab3SKavyasree Kotagiri FUNC_FC0_c, 62531d6ab3SKavyasree Kotagiri FUNC_FC1_a, 63531d6ab3SKavyasree Kotagiri FUNC_FC1_b, 64531d6ab3SKavyasree Kotagiri FUNC_FC1_c, 65531d6ab3SKavyasree Kotagiri FUNC_FC2_a, 66531d6ab3SKavyasree Kotagiri FUNC_FC2_b, 67531d6ab3SKavyasree Kotagiri FUNC_FC3_a, 68531d6ab3SKavyasree Kotagiri FUNC_FC3_b, 69531d6ab3SKavyasree Kotagiri FUNC_FC3_c, 70531d6ab3SKavyasree Kotagiri FUNC_FC4_a, 71531d6ab3SKavyasree Kotagiri FUNC_FC4_b, 72531d6ab3SKavyasree Kotagiri FUNC_FC4_c, 73531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD0, 74531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD1, 75531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD2, 76531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD3, 77531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD4, 78531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD5, 79531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD6, 80531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD7, 81531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD8, 82531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD9, 83531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD10, 84531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD11, 85531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD12, 86531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD13, 87531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD14, 88531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD15, 89531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD16, 90531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD17, 91531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD18, 92531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD19, 93531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD20, 94ce8dc094SAlexandre Belloni FUNC_GPIO, 95531d6ab3SKavyasree Kotagiri FUNC_IB_TRG_a, 96531d6ab3SKavyasree Kotagiri FUNC_IB_TRG_b, 97531d6ab3SKavyasree Kotagiri FUNC_IB_TRG_c, 98f8a74760SLars Povlsen FUNC_IRQ0, 99531d6ab3SKavyasree Kotagiri FUNC_IRQ_IN_a, 100531d6ab3SKavyasree Kotagiri FUNC_IRQ_IN_b, 101531d6ab3SKavyasree Kotagiri FUNC_IRQ_IN_c, 102ce8dc094SAlexandre Belloni FUNC_IRQ0_IN, 103531d6ab3SKavyasree Kotagiri FUNC_IRQ_OUT_a, 104531d6ab3SKavyasree Kotagiri FUNC_IRQ_OUT_b, 105531d6ab3SKavyasree Kotagiri FUNC_IRQ_OUT_c, 106ce8dc094SAlexandre Belloni FUNC_IRQ0_OUT, 107f8a74760SLars Povlsen FUNC_IRQ1, 108ce8dc094SAlexandre Belloni FUNC_IRQ1_IN, 109ce8dc094SAlexandre Belloni FUNC_IRQ1_OUT, 110f8a74760SLars Povlsen FUNC_EXT_IRQ, 111edc72546SLars Povlsen FUNC_MIIM, 112531d6ab3SKavyasree Kotagiri FUNC_MIIM_a, 113531d6ab3SKavyasree Kotagiri FUNC_MIIM_b, 114531d6ab3SKavyasree Kotagiri FUNC_MIIM_c, 115531d6ab3SKavyasree Kotagiri FUNC_MIIM_Sa, 116531d6ab3SKavyasree Kotagiri FUNC_MIIM_Sb, 117531d6ab3SKavyasree Kotagiri FUNC_OB_TRG, 118531d6ab3SKavyasree Kotagiri FUNC_OB_TRG_a, 119531d6ab3SKavyasree Kotagiri FUNC_OB_TRG_b, 120f8a74760SLars Povlsen FUNC_PHY_LED, 121ce8dc094SAlexandre Belloni FUNC_PCI_WAKE, 122f8a74760SLars Povlsen FUNC_MD, 123ce8dc094SAlexandre Belloni FUNC_PTP0, 124ce8dc094SAlexandre Belloni FUNC_PTP1, 125ce8dc094SAlexandre Belloni FUNC_PTP2, 126ce8dc094SAlexandre Belloni FUNC_PTP3, 127d3683eebSHoratiu Vultur FUNC_PTPSYNC_0, 128531d6ab3SKavyasree Kotagiri FUNC_PTPSYNC_1, 129531d6ab3SKavyasree Kotagiri FUNC_PTPSYNC_2, 130531d6ab3SKavyasree Kotagiri FUNC_PTPSYNC_3, 131531d6ab3SKavyasree Kotagiri FUNC_PTPSYNC_4, 132531d6ab3SKavyasree Kotagiri FUNC_PTPSYNC_5, 133531d6ab3SKavyasree Kotagiri FUNC_PTPSYNC_6, 134531d6ab3SKavyasree Kotagiri FUNC_PTPSYNC_7, 135ce8dc094SAlexandre Belloni FUNC_PWM, 136e97e36cdSMichael Walle FUNC_PWM_a, 137e97e36cdSMichael Walle FUNC_PWM_b, 138531d6ab3SKavyasree Kotagiri FUNC_QSPI1, 139531d6ab3SKavyasree Kotagiri FUNC_QSPI2, 140531d6ab3SKavyasree Kotagiri FUNC_R, 141531d6ab3SKavyasree Kotagiri FUNC_RECO_a, 142531d6ab3SKavyasree Kotagiri FUNC_RECO_b, 143edc72546SLars Povlsen FUNC_RECO_CLK, 144531d6ab3SKavyasree Kotagiri FUNC_SD, 145edc72546SLars Povlsen FUNC_SFP, 146531d6ab3SKavyasree Kotagiri FUNC_SFP_SD, 147ce8dc094SAlexandre Belloni FUNC_SG0, 148da801ab5SAlexandre Belloni FUNC_SG1, 149da801ab5SAlexandre Belloni FUNC_SG2, 150531d6ab3SKavyasree Kotagiri FUNC_SGPIO_a, 151531d6ab3SKavyasree Kotagiri FUNC_SGPIO_b, 152ce8dc094SAlexandre Belloni FUNC_SI, 153f8a74760SLars Povlsen FUNC_SI2, 154ce8dc094SAlexandre Belloni FUNC_TACHO, 155531d6ab3SKavyasree Kotagiri FUNC_TACHO_a, 156531d6ab3SKavyasree Kotagiri FUNC_TACHO_b, 157ce8dc094SAlexandre Belloni FUNC_TWI, 158da801ab5SAlexandre Belloni FUNC_TWI2, 159f8a74760SLars Povlsen FUNC_TWI3, 160ce8dc094SAlexandre Belloni FUNC_TWI_SCL_M, 161531d6ab3SKavyasree Kotagiri FUNC_TWI_SLC_GATE, 162531d6ab3SKavyasree Kotagiri FUNC_TWI_SLC_GATE_AD, 163ce8dc094SAlexandre Belloni FUNC_UART, 164ce8dc094SAlexandre Belloni FUNC_UART2, 165f8a74760SLars Povlsen FUNC_UART3, 166531d6ab3SKavyasree Kotagiri FUNC_USB_H_a, 167531d6ab3SKavyasree Kotagiri FUNC_USB_H_b, 168531d6ab3SKavyasree Kotagiri FUNC_USB_H_c, 169531d6ab3SKavyasree Kotagiri FUNC_USB_S_a, 170531d6ab3SKavyasree Kotagiri FUNC_USB_S_b, 171531d6ab3SKavyasree Kotagiri FUNC_USB_S_c, 172f8a74760SLars Povlsen FUNC_PLL_STAT, 173f8a74760SLars Povlsen FUNC_EMMC, 174531d6ab3SKavyasree Kotagiri FUNC_EMMC_SD, 175f8a74760SLars Povlsen FUNC_REF_CLK, 176f8a74760SLars Povlsen FUNC_RCVRD_CLK, 177ce8dc094SAlexandre Belloni FUNC_MAX 178ce8dc094SAlexandre Belloni }; 179ce8dc094SAlexandre Belloni 180ce8dc094SAlexandre Belloni static const char *const ocelot_function_names[] = { 181531d6ab3SKavyasree Kotagiri [FUNC_CAN0_a] = "can0_a", 182531d6ab3SKavyasree Kotagiri [FUNC_CAN0_b] = "can0_b", 183531d6ab3SKavyasree Kotagiri [FUNC_CAN1] = "can1", 184bf3e7f49SMichael Walle [FUNC_CLKMON] = "clkmon", 185ce8dc094SAlexandre Belloni [FUNC_NONE] = "none", 186531d6ab3SKavyasree Kotagiri [FUNC_FC0_a] = "fc0_a", 187531d6ab3SKavyasree Kotagiri [FUNC_FC0_b] = "fc0_b", 188531d6ab3SKavyasree Kotagiri [FUNC_FC0_c] = "fc0_c", 189531d6ab3SKavyasree Kotagiri [FUNC_FC1_a] = "fc1_a", 190531d6ab3SKavyasree Kotagiri [FUNC_FC1_b] = "fc1_b", 191531d6ab3SKavyasree Kotagiri [FUNC_FC1_c] = "fc1_c", 192531d6ab3SKavyasree Kotagiri [FUNC_FC2_a] = "fc2_a", 193531d6ab3SKavyasree Kotagiri [FUNC_FC2_b] = "fc2_b", 194531d6ab3SKavyasree Kotagiri [FUNC_FC3_a] = "fc3_a", 195531d6ab3SKavyasree Kotagiri [FUNC_FC3_b] = "fc3_b", 196531d6ab3SKavyasree Kotagiri [FUNC_FC3_c] = "fc3_c", 197531d6ab3SKavyasree Kotagiri [FUNC_FC4_a] = "fc4_a", 198531d6ab3SKavyasree Kotagiri [FUNC_FC4_b] = "fc4_b", 199531d6ab3SKavyasree Kotagiri [FUNC_FC4_c] = "fc4_c", 200531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD0] = "fc_shrd0", 201531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD1] = "fc_shrd1", 202531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD2] = "fc_shrd2", 203531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD3] = "fc_shrd3", 204531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD4] = "fc_shrd4", 205531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD5] = "fc_shrd5", 206531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD6] = "fc_shrd6", 207531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD7] = "fc_shrd7", 208531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD8] = "fc_shrd8", 209531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD9] = "fc_shrd9", 210531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD10] = "fc_shrd10", 211531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD11] = "fc_shrd11", 212531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD12] = "fc_shrd12", 213531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD13] = "fc_shrd13", 214531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD14] = "fc_shrd14", 215531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD15] = "fc_shrd15", 216531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD16] = "fc_shrd16", 217531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD17] = "fc_shrd17", 218531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD18] = "fc_shrd18", 219531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD19] = "fc_shrd19", 220531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD20] = "fc_shrd20", 221ce8dc094SAlexandre Belloni [FUNC_GPIO] = "gpio", 222531d6ab3SKavyasree Kotagiri [FUNC_IB_TRG_a] = "ib_trig_a", 223531d6ab3SKavyasree Kotagiri [FUNC_IB_TRG_b] = "ib_trig_b", 224531d6ab3SKavyasree Kotagiri [FUNC_IB_TRG_c] = "ib_trig_c", 225f8a74760SLars Povlsen [FUNC_IRQ0] = "irq0", 226531d6ab3SKavyasree Kotagiri [FUNC_IRQ_IN_a] = "irq_in_a", 227531d6ab3SKavyasree Kotagiri [FUNC_IRQ_IN_b] = "irq_in_b", 228531d6ab3SKavyasree Kotagiri [FUNC_IRQ_IN_c] = "irq_in_c", 229ce8dc094SAlexandre Belloni [FUNC_IRQ0_IN] = "irq0_in", 230531d6ab3SKavyasree Kotagiri [FUNC_IRQ_OUT_a] = "irq_out_a", 231531d6ab3SKavyasree Kotagiri [FUNC_IRQ_OUT_b] = "irq_out_b", 232531d6ab3SKavyasree Kotagiri [FUNC_IRQ_OUT_c] = "irq_out_c", 233ce8dc094SAlexandre Belloni [FUNC_IRQ0_OUT] = "irq0_out", 234f8a74760SLars Povlsen [FUNC_IRQ1] = "irq1", 235ce8dc094SAlexandre Belloni [FUNC_IRQ1_IN] = "irq1_in", 236ce8dc094SAlexandre Belloni [FUNC_IRQ1_OUT] = "irq1_out", 237f8a74760SLars Povlsen [FUNC_EXT_IRQ] = "ext_irq", 238edc72546SLars Povlsen [FUNC_MIIM] = "miim", 239531d6ab3SKavyasree Kotagiri [FUNC_MIIM_a] = "miim_a", 240531d6ab3SKavyasree Kotagiri [FUNC_MIIM_b] = "miim_b", 241531d6ab3SKavyasree Kotagiri [FUNC_MIIM_c] = "miim_c", 242531d6ab3SKavyasree Kotagiri [FUNC_MIIM_Sa] = "miim_slave_a", 243531d6ab3SKavyasree Kotagiri [FUNC_MIIM_Sb] = "miim_slave_b", 244f8a74760SLars Povlsen [FUNC_PHY_LED] = "phy_led", 245ce8dc094SAlexandre Belloni [FUNC_PCI_WAKE] = "pci_wake", 246f8a74760SLars Povlsen [FUNC_MD] = "md", 247531d6ab3SKavyasree Kotagiri [FUNC_OB_TRG] = "ob_trig", 248531d6ab3SKavyasree Kotagiri [FUNC_OB_TRG_a] = "ob_trig_a", 249531d6ab3SKavyasree Kotagiri [FUNC_OB_TRG_b] = "ob_trig_b", 250ce8dc094SAlexandre Belloni [FUNC_PTP0] = "ptp0", 251ce8dc094SAlexandre Belloni [FUNC_PTP1] = "ptp1", 252ce8dc094SAlexandre Belloni [FUNC_PTP2] = "ptp2", 253ce8dc094SAlexandre Belloni [FUNC_PTP3] = "ptp3", 254d3683eebSHoratiu Vultur [FUNC_PTPSYNC_0] = "ptpsync_0", 255531d6ab3SKavyasree Kotagiri [FUNC_PTPSYNC_1] = "ptpsync_1", 256531d6ab3SKavyasree Kotagiri [FUNC_PTPSYNC_2] = "ptpsync_2", 257531d6ab3SKavyasree Kotagiri [FUNC_PTPSYNC_3] = "ptpsync_3", 258531d6ab3SKavyasree Kotagiri [FUNC_PTPSYNC_4] = "ptpsync_4", 259531d6ab3SKavyasree Kotagiri [FUNC_PTPSYNC_5] = "ptpsync_5", 260531d6ab3SKavyasree Kotagiri [FUNC_PTPSYNC_6] = "ptpsync_6", 261531d6ab3SKavyasree Kotagiri [FUNC_PTPSYNC_7] = "ptpsync_7", 262ce8dc094SAlexandre Belloni [FUNC_PWM] = "pwm", 263e97e36cdSMichael Walle [FUNC_PWM_a] = "pwm_a", 264e97e36cdSMichael Walle [FUNC_PWM_b] = "pwm_b", 265531d6ab3SKavyasree Kotagiri [FUNC_QSPI1] = "qspi1", 266531d6ab3SKavyasree Kotagiri [FUNC_QSPI2] = "qspi2", 267531d6ab3SKavyasree Kotagiri [FUNC_R] = "reserved", 268531d6ab3SKavyasree Kotagiri [FUNC_RECO_a] = "reco_a", 269531d6ab3SKavyasree Kotagiri [FUNC_RECO_b] = "reco_b", 270edc72546SLars Povlsen [FUNC_RECO_CLK] = "reco_clk", 271531d6ab3SKavyasree Kotagiri [FUNC_SD] = "sd", 272edc72546SLars Povlsen [FUNC_SFP] = "sfp", 273531d6ab3SKavyasree Kotagiri [FUNC_SFP_SD] = "sfp_sd", 274ce8dc094SAlexandre Belloni [FUNC_SG0] = "sg0", 275da801ab5SAlexandre Belloni [FUNC_SG1] = "sg1", 276da801ab5SAlexandre Belloni [FUNC_SG2] = "sg2", 277531d6ab3SKavyasree Kotagiri [FUNC_SGPIO_a] = "sgpio_a", 278531d6ab3SKavyasree Kotagiri [FUNC_SGPIO_b] = "sgpio_b", 279ce8dc094SAlexandre Belloni [FUNC_SI] = "si", 280f8a74760SLars Povlsen [FUNC_SI2] = "si2", 281ce8dc094SAlexandre Belloni [FUNC_TACHO] = "tacho", 282531d6ab3SKavyasree Kotagiri [FUNC_TACHO_a] = "tacho_a", 283531d6ab3SKavyasree Kotagiri [FUNC_TACHO_b] = "tacho_b", 284ce8dc094SAlexandre Belloni [FUNC_TWI] = "twi", 285da801ab5SAlexandre Belloni [FUNC_TWI2] = "twi2", 286f8a74760SLars Povlsen [FUNC_TWI3] = "twi3", 287ce8dc094SAlexandre Belloni [FUNC_TWI_SCL_M] = "twi_scl_m", 288531d6ab3SKavyasree Kotagiri [FUNC_TWI_SLC_GATE] = "twi_slc_gate", 289531d6ab3SKavyasree Kotagiri [FUNC_TWI_SLC_GATE_AD] = "twi_slc_gate_ad", 290531d6ab3SKavyasree Kotagiri [FUNC_USB_H_a] = "usb_host_a", 291531d6ab3SKavyasree Kotagiri [FUNC_USB_H_b] = "usb_host_b", 292531d6ab3SKavyasree Kotagiri [FUNC_USB_H_c] = "usb_host_c", 293531d6ab3SKavyasree Kotagiri [FUNC_USB_S_a] = "usb_slave_a", 294531d6ab3SKavyasree Kotagiri [FUNC_USB_S_b] = "usb_slave_b", 295531d6ab3SKavyasree Kotagiri [FUNC_USB_S_c] = "usb_slave_c", 296ce8dc094SAlexandre Belloni [FUNC_UART] = "uart", 297ce8dc094SAlexandre Belloni [FUNC_UART2] = "uart2", 298f8a74760SLars Povlsen [FUNC_UART3] = "uart3", 299f8a74760SLars Povlsen [FUNC_PLL_STAT] = "pll_stat", 300f8a74760SLars Povlsen [FUNC_EMMC] = "emmc", 301531d6ab3SKavyasree Kotagiri [FUNC_EMMC_SD] = "emmc_sd", 302f8a74760SLars Povlsen [FUNC_REF_CLK] = "ref_clk", 303f8a74760SLars Povlsen [FUNC_RCVRD_CLK] = "rcvrd_clk", 304ce8dc094SAlexandre Belloni }; 305ce8dc094SAlexandre Belloni 306ce8dc094SAlexandre Belloni struct ocelot_pmx_func { 307ce8dc094SAlexandre Belloni const char **groups; 308ce8dc094SAlexandre Belloni unsigned int ngroups; 309ce8dc094SAlexandre Belloni }; 310ce8dc094SAlexandre Belloni 311ce8dc094SAlexandre Belloni struct ocelot_pin_caps { 312ce8dc094SAlexandre Belloni unsigned int pin; 313ce8dc094SAlexandre Belloni unsigned char functions[OCELOT_FUNC_PER_PIN]; 314531d6ab3SKavyasree Kotagiri unsigned char a_functions[OCELOT_FUNC_PER_PIN]; /* Additional functions */ 315ce8dc094SAlexandre Belloni }; 316ce8dc094SAlexandre Belloni 317dc62db71SHoratiu Vultur struct ocelot_pincfg_data { 318dc62db71SHoratiu Vultur u8 pd_bit; 319dc62db71SHoratiu Vultur u8 pu_bit; 320dc62db71SHoratiu Vultur u8 drive_bits; 321dc62db71SHoratiu Vultur u8 schmitt_bit; 322dc62db71SHoratiu Vultur }; 323dc62db71SHoratiu Vultur 324ce8dc094SAlexandre Belloni struct ocelot_pinctrl { 325ce8dc094SAlexandre Belloni struct device *dev; 326ce8dc094SAlexandre Belloni struct pinctrl_dev *pctl; 327ce8dc094SAlexandre Belloni struct gpio_chip gpio_chip; 328ce8dc094SAlexandre Belloni struct regmap *map; 329076d9e71SColin Foster struct regmap *pincfg; 330da801ab5SAlexandre Belloni struct pinctrl_desc *desc; 331dc62db71SHoratiu Vultur const struct ocelot_pincfg_data *pincfg_data; 332ce8dc094SAlexandre Belloni struct ocelot_pmx_func func[FUNC_MAX]; 333da801ab5SAlexandre Belloni u8 stride; 334ce8dc094SAlexandre Belloni }; 335ce8dc094SAlexandre Belloni 336dc62db71SHoratiu Vultur struct ocelot_match_data { 337dc62db71SHoratiu Vultur struct pinctrl_desc desc; 338dc62db71SHoratiu Vultur struct ocelot_pincfg_data pincfg_data; 339dc62db71SHoratiu Vultur }; 340dc62db71SHoratiu Vultur 3418f27440dSLars Povlsen #define LUTON_P(p, f0, f1) \ 3428f27440dSLars Povlsen static struct ocelot_pin_caps luton_pin_##p = { \ 3438f27440dSLars Povlsen .pin = p, \ 3448f27440dSLars Povlsen .functions = { \ 3458f27440dSLars Povlsen FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_NONE, \ 3468f27440dSLars Povlsen }, \ 3478f27440dSLars Povlsen } 3488f27440dSLars Povlsen 3498f27440dSLars Povlsen LUTON_P(0, SG0, NONE); 3508f27440dSLars Povlsen LUTON_P(1, SG0, NONE); 3518f27440dSLars Povlsen LUTON_P(2, SG0, NONE); 3528f27440dSLars Povlsen LUTON_P(3, SG0, NONE); 3538f27440dSLars Povlsen LUTON_P(4, TACHO, NONE); 3548f27440dSLars Povlsen LUTON_P(5, TWI, PHY_LED); 3558f27440dSLars Povlsen LUTON_P(6, TWI, PHY_LED); 3568f27440dSLars Povlsen LUTON_P(7, NONE, PHY_LED); 3578f27440dSLars Povlsen LUTON_P(8, EXT_IRQ, PHY_LED); 3588f27440dSLars Povlsen LUTON_P(9, EXT_IRQ, PHY_LED); 3598f27440dSLars Povlsen LUTON_P(10, SFP, PHY_LED); 3608f27440dSLars Povlsen LUTON_P(11, SFP, PHY_LED); 3618f27440dSLars Povlsen LUTON_P(12, SFP, PHY_LED); 3628f27440dSLars Povlsen LUTON_P(13, SFP, PHY_LED); 3638f27440dSLars Povlsen LUTON_P(14, SI, PHY_LED); 3648f27440dSLars Povlsen LUTON_P(15, SI, PHY_LED); 3658f27440dSLars Povlsen LUTON_P(16, SI, PHY_LED); 3668f27440dSLars Povlsen LUTON_P(17, SFP, PHY_LED); 3678f27440dSLars Povlsen LUTON_P(18, SFP, PHY_LED); 3688f27440dSLars Povlsen LUTON_P(19, SFP, PHY_LED); 3698f27440dSLars Povlsen LUTON_P(20, SFP, PHY_LED); 3708f27440dSLars Povlsen LUTON_P(21, SFP, PHY_LED); 3718f27440dSLars Povlsen LUTON_P(22, SFP, PHY_LED); 3728f27440dSLars Povlsen LUTON_P(23, SFP, PHY_LED); 3738f27440dSLars Povlsen LUTON_P(24, SFP, PHY_LED); 3748f27440dSLars Povlsen LUTON_P(25, SFP, PHY_LED); 3758f27440dSLars Povlsen LUTON_P(26, SFP, PHY_LED); 3768f27440dSLars Povlsen LUTON_P(27, SFP, PHY_LED); 3778f27440dSLars Povlsen LUTON_P(28, SFP, PHY_LED); 3788f27440dSLars Povlsen LUTON_P(29, PWM, NONE); 3798f27440dSLars Povlsen LUTON_P(30, UART, NONE); 3808f27440dSLars Povlsen LUTON_P(31, UART, NONE); 3818f27440dSLars Povlsen 3828f27440dSLars Povlsen #define LUTON_PIN(n) { \ 3838f27440dSLars Povlsen .number = n, \ 3848f27440dSLars Povlsen .name = "GPIO_"#n, \ 3858f27440dSLars Povlsen .drv_data = &luton_pin_##n \ 3868f27440dSLars Povlsen } 3878f27440dSLars Povlsen 3888f27440dSLars Povlsen static const struct pinctrl_pin_desc luton_pins[] = { 3898f27440dSLars Povlsen LUTON_PIN(0), 3908f27440dSLars Povlsen LUTON_PIN(1), 3918f27440dSLars Povlsen LUTON_PIN(2), 3928f27440dSLars Povlsen LUTON_PIN(3), 3938f27440dSLars Povlsen LUTON_PIN(4), 3948f27440dSLars Povlsen LUTON_PIN(5), 3958f27440dSLars Povlsen LUTON_PIN(6), 3968f27440dSLars Povlsen LUTON_PIN(7), 3978f27440dSLars Povlsen LUTON_PIN(8), 3988f27440dSLars Povlsen LUTON_PIN(9), 3998f27440dSLars Povlsen LUTON_PIN(10), 4008f27440dSLars Povlsen LUTON_PIN(11), 4018f27440dSLars Povlsen LUTON_PIN(12), 4028f27440dSLars Povlsen LUTON_PIN(13), 4038f27440dSLars Povlsen LUTON_PIN(14), 4048f27440dSLars Povlsen LUTON_PIN(15), 4058f27440dSLars Povlsen LUTON_PIN(16), 4068f27440dSLars Povlsen LUTON_PIN(17), 4078f27440dSLars Povlsen LUTON_PIN(18), 4088f27440dSLars Povlsen LUTON_PIN(19), 4098f27440dSLars Povlsen LUTON_PIN(20), 4108f27440dSLars Povlsen LUTON_PIN(21), 4118f27440dSLars Povlsen LUTON_PIN(22), 4128f27440dSLars Povlsen LUTON_PIN(23), 4138f27440dSLars Povlsen LUTON_PIN(24), 4148f27440dSLars Povlsen LUTON_PIN(25), 4158f27440dSLars Povlsen LUTON_PIN(26), 4168f27440dSLars Povlsen LUTON_PIN(27), 4178f27440dSLars Povlsen LUTON_PIN(28), 4188f27440dSLars Povlsen LUTON_PIN(29), 4198f27440dSLars Povlsen LUTON_PIN(30), 4208f27440dSLars Povlsen LUTON_PIN(31), 4218f27440dSLars Povlsen }; 4228f27440dSLars Povlsen 4236e6347e2SLars Povlsen #define SERVAL_P(p, f0, f1, f2) \ 4246e6347e2SLars Povlsen static struct ocelot_pin_caps serval_pin_##p = { \ 4256e6347e2SLars Povlsen .pin = p, \ 4266e6347e2SLars Povlsen .functions = { \ 4276e6347e2SLars Povlsen FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2, \ 4286e6347e2SLars Povlsen }, \ 4296e6347e2SLars Povlsen } 4306e6347e2SLars Povlsen 4316e6347e2SLars Povlsen SERVAL_P(0, SG0, NONE, NONE); 4326e6347e2SLars Povlsen SERVAL_P(1, SG0, NONE, NONE); 4336e6347e2SLars Povlsen SERVAL_P(2, SG0, NONE, NONE); 4346e6347e2SLars Povlsen SERVAL_P(3, SG0, NONE, NONE); 4356e6347e2SLars Povlsen SERVAL_P(4, TACHO, NONE, NONE); 4366e6347e2SLars Povlsen SERVAL_P(5, PWM, NONE, NONE); 4376e6347e2SLars Povlsen SERVAL_P(6, TWI, NONE, NONE); 4386e6347e2SLars Povlsen SERVAL_P(7, TWI, NONE, NONE); 4396e6347e2SLars Povlsen SERVAL_P(8, SI, NONE, NONE); 4406e6347e2SLars Povlsen SERVAL_P(9, SI, MD, NONE); 4416e6347e2SLars Povlsen SERVAL_P(10, SI, MD, NONE); 4426e6347e2SLars Povlsen SERVAL_P(11, SFP, MD, TWI_SCL_M); 4436e6347e2SLars Povlsen SERVAL_P(12, SFP, MD, TWI_SCL_M); 4446e6347e2SLars Povlsen SERVAL_P(13, SFP, UART2, TWI_SCL_M); 4456e6347e2SLars Povlsen SERVAL_P(14, SFP, UART2, TWI_SCL_M); 4466e6347e2SLars Povlsen SERVAL_P(15, SFP, PTP0, TWI_SCL_M); 4476e6347e2SLars Povlsen SERVAL_P(16, SFP, PTP0, TWI_SCL_M); 4486e6347e2SLars Povlsen SERVAL_P(17, SFP, PCI_WAKE, TWI_SCL_M); 4496e6347e2SLars Povlsen SERVAL_P(18, SFP, NONE, TWI_SCL_M); 4506e6347e2SLars Povlsen SERVAL_P(19, SFP, NONE, TWI_SCL_M); 4516e6347e2SLars Povlsen SERVAL_P(20, SFP, NONE, TWI_SCL_M); 4526e6347e2SLars Povlsen SERVAL_P(21, SFP, NONE, TWI_SCL_M); 4536e6347e2SLars Povlsen SERVAL_P(22, NONE, NONE, NONE); 4546e6347e2SLars Povlsen SERVAL_P(23, NONE, NONE, NONE); 4556e6347e2SLars Povlsen SERVAL_P(24, NONE, NONE, NONE); 4566e6347e2SLars Povlsen SERVAL_P(25, NONE, NONE, NONE); 4576e6347e2SLars Povlsen SERVAL_P(26, UART, NONE, NONE); 4586e6347e2SLars Povlsen SERVAL_P(27, UART, NONE, NONE); 4596e6347e2SLars Povlsen SERVAL_P(28, IRQ0, NONE, NONE); 4606e6347e2SLars Povlsen SERVAL_P(29, IRQ1, NONE, NONE); 4616e6347e2SLars Povlsen SERVAL_P(30, PTP0, NONE, NONE); 4626e6347e2SLars Povlsen SERVAL_P(31, PTP0, NONE, NONE); 4636e6347e2SLars Povlsen 4646e6347e2SLars Povlsen #define SERVAL_PIN(n) { \ 4656e6347e2SLars Povlsen .number = n, \ 4666e6347e2SLars Povlsen .name = "GPIO_"#n, \ 4676e6347e2SLars Povlsen .drv_data = &serval_pin_##n \ 4686e6347e2SLars Povlsen } 4696e6347e2SLars Povlsen 4706e6347e2SLars Povlsen static const struct pinctrl_pin_desc serval_pins[] = { 4716e6347e2SLars Povlsen SERVAL_PIN(0), 4726e6347e2SLars Povlsen SERVAL_PIN(1), 4736e6347e2SLars Povlsen SERVAL_PIN(2), 4746e6347e2SLars Povlsen SERVAL_PIN(3), 4756e6347e2SLars Povlsen SERVAL_PIN(4), 4766e6347e2SLars Povlsen SERVAL_PIN(5), 4776e6347e2SLars Povlsen SERVAL_PIN(6), 4786e6347e2SLars Povlsen SERVAL_PIN(7), 4796e6347e2SLars Povlsen SERVAL_PIN(8), 4806e6347e2SLars Povlsen SERVAL_PIN(9), 4816e6347e2SLars Povlsen SERVAL_PIN(10), 4826e6347e2SLars Povlsen SERVAL_PIN(11), 4836e6347e2SLars Povlsen SERVAL_PIN(12), 4846e6347e2SLars Povlsen SERVAL_PIN(13), 4856e6347e2SLars Povlsen SERVAL_PIN(14), 4866e6347e2SLars Povlsen SERVAL_PIN(15), 4876e6347e2SLars Povlsen SERVAL_PIN(16), 4886e6347e2SLars Povlsen SERVAL_PIN(17), 4896e6347e2SLars Povlsen SERVAL_PIN(18), 4906e6347e2SLars Povlsen SERVAL_PIN(19), 4916e6347e2SLars Povlsen SERVAL_PIN(20), 4926e6347e2SLars Povlsen SERVAL_PIN(21), 4936e6347e2SLars Povlsen SERVAL_PIN(22), 4946e6347e2SLars Povlsen SERVAL_PIN(23), 4956e6347e2SLars Povlsen SERVAL_PIN(24), 4966e6347e2SLars Povlsen SERVAL_PIN(25), 4976e6347e2SLars Povlsen SERVAL_PIN(26), 4986e6347e2SLars Povlsen SERVAL_PIN(27), 4996e6347e2SLars Povlsen SERVAL_PIN(28), 5006e6347e2SLars Povlsen SERVAL_PIN(29), 5016e6347e2SLars Povlsen SERVAL_PIN(30), 5026e6347e2SLars Povlsen SERVAL_PIN(31), 5036e6347e2SLars Povlsen }; 5046e6347e2SLars Povlsen 505ce8dc094SAlexandre Belloni #define OCELOT_P(p, f0, f1, f2) \ 506ce8dc094SAlexandre Belloni static struct ocelot_pin_caps ocelot_pin_##p = { \ 507ce8dc094SAlexandre Belloni .pin = p, \ 508ce8dc094SAlexandre Belloni .functions = { \ 509ce8dc094SAlexandre Belloni FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2, \ 510ce8dc094SAlexandre Belloni }, \ 511ce8dc094SAlexandre Belloni } 512ce8dc094SAlexandre Belloni 513ce8dc094SAlexandre Belloni OCELOT_P(0, SG0, NONE, NONE); 514ce8dc094SAlexandre Belloni OCELOT_P(1, SG0, NONE, NONE); 515ce8dc094SAlexandre Belloni OCELOT_P(2, SG0, NONE, NONE); 516ce8dc094SAlexandre Belloni OCELOT_P(3, SG0, NONE, NONE); 51717f79084SAlexandre Belloni OCELOT_P(4, IRQ0_IN, IRQ0_OUT, TWI_SCL_M); 518ce8dc094SAlexandre Belloni OCELOT_P(5, IRQ1_IN, IRQ1_OUT, PCI_WAKE); 519ce8dc094SAlexandre Belloni OCELOT_P(6, UART, TWI_SCL_M, NONE); 520ce8dc094SAlexandre Belloni OCELOT_P(7, UART, TWI_SCL_M, NONE); 521ce8dc094SAlexandre Belloni OCELOT_P(8, SI, TWI_SCL_M, IRQ0_OUT); 522ce8dc094SAlexandre Belloni OCELOT_P(9, SI, TWI_SCL_M, IRQ1_OUT); 523edc72546SLars Povlsen OCELOT_P(10, PTP2, TWI_SCL_M, SFP); 524edc72546SLars Povlsen OCELOT_P(11, PTP3, TWI_SCL_M, SFP); 525edc72546SLars Povlsen OCELOT_P(12, UART2, TWI_SCL_M, SFP); 526edc72546SLars Povlsen OCELOT_P(13, UART2, TWI_SCL_M, SFP); 527edc72546SLars Povlsen OCELOT_P(14, MIIM, TWI_SCL_M, SFP); 528edc72546SLars Povlsen OCELOT_P(15, MIIM, TWI_SCL_M, SFP); 529ce8dc094SAlexandre Belloni OCELOT_P(16, TWI, NONE, SI); 530ce8dc094SAlexandre Belloni OCELOT_P(17, TWI, TWI_SCL_M, SI); 531ce8dc094SAlexandre Belloni OCELOT_P(18, PTP0, TWI_SCL_M, NONE); 532ce8dc094SAlexandre Belloni OCELOT_P(19, PTP1, TWI_SCL_M, NONE); 533edc72546SLars Povlsen OCELOT_P(20, RECO_CLK, TACHO, TWI_SCL_M); 534edc72546SLars Povlsen OCELOT_P(21, RECO_CLK, PWM, TWI_SCL_M); 535ce8dc094SAlexandre Belloni 536ce8dc094SAlexandre Belloni #define OCELOT_PIN(n) { \ 537ce8dc094SAlexandre Belloni .number = n, \ 538ce8dc094SAlexandre Belloni .name = "GPIO_"#n, \ 539ce8dc094SAlexandre Belloni .drv_data = &ocelot_pin_##n \ 540ce8dc094SAlexandre Belloni } 541ce8dc094SAlexandre Belloni 542ce8dc094SAlexandre Belloni static const struct pinctrl_pin_desc ocelot_pins[] = { 543ce8dc094SAlexandre Belloni OCELOT_PIN(0), 544ce8dc094SAlexandre Belloni OCELOT_PIN(1), 545ce8dc094SAlexandre Belloni OCELOT_PIN(2), 546ce8dc094SAlexandre Belloni OCELOT_PIN(3), 547ce8dc094SAlexandre Belloni OCELOT_PIN(4), 548ce8dc094SAlexandre Belloni OCELOT_PIN(5), 549ce8dc094SAlexandre Belloni OCELOT_PIN(6), 550ce8dc094SAlexandre Belloni OCELOT_PIN(7), 551ce8dc094SAlexandre Belloni OCELOT_PIN(8), 552ce8dc094SAlexandre Belloni OCELOT_PIN(9), 553ce8dc094SAlexandre Belloni OCELOT_PIN(10), 554ce8dc094SAlexandre Belloni OCELOT_PIN(11), 555ce8dc094SAlexandre Belloni OCELOT_PIN(12), 556ce8dc094SAlexandre Belloni OCELOT_PIN(13), 557ce8dc094SAlexandre Belloni OCELOT_PIN(14), 558ce8dc094SAlexandre Belloni OCELOT_PIN(15), 559ce8dc094SAlexandre Belloni OCELOT_PIN(16), 560ce8dc094SAlexandre Belloni OCELOT_PIN(17), 561ce8dc094SAlexandre Belloni OCELOT_PIN(18), 562ce8dc094SAlexandre Belloni OCELOT_PIN(19), 563ce8dc094SAlexandre Belloni OCELOT_PIN(20), 564ce8dc094SAlexandre Belloni OCELOT_PIN(21), 565ce8dc094SAlexandre Belloni }; 566ce8dc094SAlexandre Belloni 567da801ab5SAlexandre Belloni #define JAGUAR2_P(p, f0, f1) \ 568da801ab5SAlexandre Belloni static struct ocelot_pin_caps jaguar2_pin_##p = { \ 569da801ab5SAlexandre Belloni .pin = p, \ 570da801ab5SAlexandre Belloni .functions = { \ 571da801ab5SAlexandre Belloni FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_NONE \ 572da801ab5SAlexandre Belloni }, \ 573da801ab5SAlexandre Belloni } 574da801ab5SAlexandre Belloni 575da801ab5SAlexandre Belloni JAGUAR2_P(0, SG0, NONE); 576da801ab5SAlexandre Belloni JAGUAR2_P(1, SG0, NONE); 577da801ab5SAlexandre Belloni JAGUAR2_P(2, SG0, NONE); 578da801ab5SAlexandre Belloni JAGUAR2_P(3, SG0, NONE); 579da801ab5SAlexandre Belloni JAGUAR2_P(4, SG1, NONE); 580da801ab5SAlexandre Belloni JAGUAR2_P(5, SG1, NONE); 581da801ab5SAlexandre Belloni JAGUAR2_P(6, IRQ0_IN, IRQ0_OUT); 582da801ab5SAlexandre Belloni JAGUAR2_P(7, IRQ1_IN, IRQ1_OUT); 583da801ab5SAlexandre Belloni JAGUAR2_P(8, PTP0, NONE); 584da801ab5SAlexandre Belloni JAGUAR2_P(9, PTP1, NONE); 585da801ab5SAlexandre Belloni JAGUAR2_P(10, UART, NONE); 586da801ab5SAlexandre Belloni JAGUAR2_P(11, UART, NONE); 587da801ab5SAlexandre Belloni JAGUAR2_P(12, SG1, NONE); 588da801ab5SAlexandre Belloni JAGUAR2_P(13, SG1, NONE); 589da801ab5SAlexandre Belloni JAGUAR2_P(14, TWI, TWI_SCL_M); 590da801ab5SAlexandre Belloni JAGUAR2_P(15, TWI, NONE); 591da801ab5SAlexandre Belloni JAGUAR2_P(16, SI, TWI_SCL_M); 592da801ab5SAlexandre Belloni JAGUAR2_P(17, SI, TWI_SCL_M); 593da801ab5SAlexandre Belloni JAGUAR2_P(18, SI, TWI_SCL_M); 594da801ab5SAlexandre Belloni JAGUAR2_P(19, PCI_WAKE, NONE); 595da801ab5SAlexandre Belloni JAGUAR2_P(20, IRQ0_OUT, TWI_SCL_M); 596da801ab5SAlexandre Belloni JAGUAR2_P(21, IRQ1_OUT, TWI_SCL_M); 597da801ab5SAlexandre Belloni JAGUAR2_P(22, TACHO, NONE); 598da801ab5SAlexandre Belloni JAGUAR2_P(23, PWM, NONE); 599da801ab5SAlexandre Belloni JAGUAR2_P(24, UART2, NONE); 600da801ab5SAlexandre Belloni JAGUAR2_P(25, UART2, SI); 601da801ab5SAlexandre Belloni JAGUAR2_P(26, PTP2, SI); 602da801ab5SAlexandre Belloni JAGUAR2_P(27, PTP3, SI); 603da801ab5SAlexandre Belloni JAGUAR2_P(28, TWI2, SI); 604da801ab5SAlexandre Belloni JAGUAR2_P(29, TWI2, SI); 605da801ab5SAlexandre Belloni JAGUAR2_P(30, SG2, SI); 606da801ab5SAlexandre Belloni JAGUAR2_P(31, SG2, SI); 607da801ab5SAlexandre Belloni JAGUAR2_P(32, SG2, SI); 608da801ab5SAlexandre Belloni JAGUAR2_P(33, SG2, SI); 609da801ab5SAlexandre Belloni JAGUAR2_P(34, NONE, TWI_SCL_M); 610da801ab5SAlexandre Belloni JAGUAR2_P(35, NONE, TWI_SCL_M); 611da801ab5SAlexandre Belloni JAGUAR2_P(36, NONE, TWI_SCL_M); 612da801ab5SAlexandre Belloni JAGUAR2_P(37, NONE, TWI_SCL_M); 613da801ab5SAlexandre Belloni JAGUAR2_P(38, NONE, TWI_SCL_M); 614da801ab5SAlexandre Belloni JAGUAR2_P(39, NONE, TWI_SCL_M); 615da801ab5SAlexandre Belloni JAGUAR2_P(40, NONE, TWI_SCL_M); 616da801ab5SAlexandre Belloni JAGUAR2_P(41, NONE, TWI_SCL_M); 617da801ab5SAlexandre Belloni JAGUAR2_P(42, NONE, TWI_SCL_M); 618da801ab5SAlexandre Belloni JAGUAR2_P(43, NONE, TWI_SCL_M); 619edc72546SLars Povlsen JAGUAR2_P(44, NONE, SFP); 620edc72546SLars Povlsen JAGUAR2_P(45, NONE, SFP); 621edc72546SLars Povlsen JAGUAR2_P(46, NONE, SFP); 622edc72546SLars Povlsen JAGUAR2_P(47, NONE, SFP); 623edc72546SLars Povlsen JAGUAR2_P(48, SFP, NONE); 624edc72546SLars Povlsen JAGUAR2_P(49, SFP, SI); 625edc72546SLars Povlsen JAGUAR2_P(50, SFP, SI); 626edc72546SLars Povlsen JAGUAR2_P(51, SFP, SI); 627edc72546SLars Povlsen JAGUAR2_P(52, SFP, NONE); 628edc72546SLars Povlsen JAGUAR2_P(53, SFP, NONE); 629edc72546SLars Povlsen JAGUAR2_P(54, SFP, NONE); 630edc72546SLars Povlsen JAGUAR2_P(55, SFP, NONE); 631edc72546SLars Povlsen JAGUAR2_P(56, MIIM, SFP); 632edc72546SLars Povlsen JAGUAR2_P(57, MIIM, SFP); 633edc72546SLars Povlsen JAGUAR2_P(58, MIIM, SFP); 634edc72546SLars Povlsen JAGUAR2_P(59, MIIM, SFP); 635da801ab5SAlexandre Belloni JAGUAR2_P(60, NONE, NONE); 636da801ab5SAlexandre Belloni JAGUAR2_P(61, NONE, NONE); 637da801ab5SAlexandre Belloni JAGUAR2_P(62, NONE, NONE); 638da801ab5SAlexandre Belloni JAGUAR2_P(63, NONE, NONE); 639da801ab5SAlexandre Belloni 640da801ab5SAlexandre Belloni #define JAGUAR2_PIN(n) { \ 641da801ab5SAlexandre Belloni .number = n, \ 642da801ab5SAlexandre Belloni .name = "GPIO_"#n, \ 643da801ab5SAlexandre Belloni .drv_data = &jaguar2_pin_##n \ 644da801ab5SAlexandre Belloni } 645da801ab5SAlexandre Belloni 646da801ab5SAlexandre Belloni static const struct pinctrl_pin_desc jaguar2_pins[] = { 647da801ab5SAlexandre Belloni JAGUAR2_PIN(0), 648da801ab5SAlexandre Belloni JAGUAR2_PIN(1), 649da801ab5SAlexandre Belloni JAGUAR2_PIN(2), 650da801ab5SAlexandre Belloni JAGUAR2_PIN(3), 651da801ab5SAlexandre Belloni JAGUAR2_PIN(4), 652da801ab5SAlexandre Belloni JAGUAR2_PIN(5), 653da801ab5SAlexandre Belloni JAGUAR2_PIN(6), 654da801ab5SAlexandre Belloni JAGUAR2_PIN(7), 655da801ab5SAlexandre Belloni JAGUAR2_PIN(8), 656da801ab5SAlexandre Belloni JAGUAR2_PIN(9), 657da801ab5SAlexandre Belloni JAGUAR2_PIN(10), 658da801ab5SAlexandre Belloni JAGUAR2_PIN(11), 659da801ab5SAlexandre Belloni JAGUAR2_PIN(12), 660da801ab5SAlexandre Belloni JAGUAR2_PIN(13), 661da801ab5SAlexandre Belloni JAGUAR2_PIN(14), 662da801ab5SAlexandre Belloni JAGUAR2_PIN(15), 663da801ab5SAlexandre Belloni JAGUAR2_PIN(16), 664da801ab5SAlexandre Belloni JAGUAR2_PIN(17), 665da801ab5SAlexandre Belloni JAGUAR2_PIN(18), 666da801ab5SAlexandre Belloni JAGUAR2_PIN(19), 667da801ab5SAlexandre Belloni JAGUAR2_PIN(20), 668da801ab5SAlexandre Belloni JAGUAR2_PIN(21), 669da801ab5SAlexandre Belloni JAGUAR2_PIN(22), 670da801ab5SAlexandre Belloni JAGUAR2_PIN(23), 671da801ab5SAlexandre Belloni JAGUAR2_PIN(24), 672da801ab5SAlexandre Belloni JAGUAR2_PIN(25), 673da801ab5SAlexandre Belloni JAGUAR2_PIN(26), 674da801ab5SAlexandre Belloni JAGUAR2_PIN(27), 675da801ab5SAlexandre Belloni JAGUAR2_PIN(28), 676da801ab5SAlexandre Belloni JAGUAR2_PIN(29), 677da801ab5SAlexandre Belloni JAGUAR2_PIN(30), 678da801ab5SAlexandre Belloni JAGUAR2_PIN(31), 679da801ab5SAlexandre Belloni JAGUAR2_PIN(32), 680da801ab5SAlexandre Belloni JAGUAR2_PIN(33), 681da801ab5SAlexandre Belloni JAGUAR2_PIN(34), 682da801ab5SAlexandre Belloni JAGUAR2_PIN(35), 683da801ab5SAlexandre Belloni JAGUAR2_PIN(36), 684da801ab5SAlexandre Belloni JAGUAR2_PIN(37), 685da801ab5SAlexandre Belloni JAGUAR2_PIN(38), 686da801ab5SAlexandre Belloni JAGUAR2_PIN(39), 687da801ab5SAlexandre Belloni JAGUAR2_PIN(40), 688da801ab5SAlexandre Belloni JAGUAR2_PIN(41), 689da801ab5SAlexandre Belloni JAGUAR2_PIN(42), 690da801ab5SAlexandre Belloni JAGUAR2_PIN(43), 691da801ab5SAlexandre Belloni JAGUAR2_PIN(44), 692da801ab5SAlexandre Belloni JAGUAR2_PIN(45), 693da801ab5SAlexandre Belloni JAGUAR2_PIN(46), 694da801ab5SAlexandre Belloni JAGUAR2_PIN(47), 695da801ab5SAlexandre Belloni JAGUAR2_PIN(48), 696da801ab5SAlexandre Belloni JAGUAR2_PIN(49), 697da801ab5SAlexandre Belloni JAGUAR2_PIN(50), 698da801ab5SAlexandre Belloni JAGUAR2_PIN(51), 699da801ab5SAlexandre Belloni JAGUAR2_PIN(52), 700da801ab5SAlexandre Belloni JAGUAR2_PIN(53), 701da801ab5SAlexandre Belloni JAGUAR2_PIN(54), 702da801ab5SAlexandre Belloni JAGUAR2_PIN(55), 703da801ab5SAlexandre Belloni JAGUAR2_PIN(56), 704da801ab5SAlexandre Belloni JAGUAR2_PIN(57), 705da801ab5SAlexandre Belloni JAGUAR2_PIN(58), 706da801ab5SAlexandre Belloni JAGUAR2_PIN(59), 707da801ab5SAlexandre Belloni JAGUAR2_PIN(60), 708da801ab5SAlexandre Belloni JAGUAR2_PIN(61), 709da801ab5SAlexandre Belloni JAGUAR2_PIN(62), 710da801ab5SAlexandre Belloni JAGUAR2_PIN(63), 711da801ab5SAlexandre Belloni }; 712da801ab5SAlexandre Belloni 7138fc0bfcdSHoratiu Vultur #define SERVALT_P(p, f0, f1, f2) \ 7148fc0bfcdSHoratiu Vultur static struct ocelot_pin_caps servalt_pin_##p = { \ 7158fc0bfcdSHoratiu Vultur .pin = p, \ 7168fc0bfcdSHoratiu Vultur .functions = { \ 7178fc0bfcdSHoratiu Vultur FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2 \ 7188fc0bfcdSHoratiu Vultur }, \ 7198fc0bfcdSHoratiu Vultur } 7208fc0bfcdSHoratiu Vultur 7218fc0bfcdSHoratiu Vultur SERVALT_P(0, SG0, NONE, NONE); 7228fc0bfcdSHoratiu Vultur SERVALT_P(1, SG0, NONE, NONE); 7238fc0bfcdSHoratiu Vultur SERVALT_P(2, SG0, NONE, NONE); 7248fc0bfcdSHoratiu Vultur SERVALT_P(3, SG0, NONE, NONE); 7258fc0bfcdSHoratiu Vultur SERVALT_P(4, IRQ0_IN, IRQ0_OUT, TWI_SCL_M); 7268fc0bfcdSHoratiu Vultur SERVALT_P(5, IRQ1_IN, IRQ1_OUT, TWI_SCL_M); 7278fc0bfcdSHoratiu Vultur SERVALT_P(6, UART, NONE, NONE); 7288fc0bfcdSHoratiu Vultur SERVALT_P(7, UART, NONE, NONE); 7298fc0bfcdSHoratiu Vultur SERVALT_P(8, SI, SFP, TWI_SCL_M); 7308fc0bfcdSHoratiu Vultur SERVALT_P(9, PCI_WAKE, SFP, SI); 7318fc0bfcdSHoratiu Vultur SERVALT_P(10, PTP0, SFP, TWI_SCL_M); 7328fc0bfcdSHoratiu Vultur SERVALT_P(11, PTP1, SFP, TWI_SCL_M); 7338fc0bfcdSHoratiu Vultur SERVALT_P(12, REF_CLK, SFP, TWI_SCL_M); 7348fc0bfcdSHoratiu Vultur SERVALT_P(13, REF_CLK, SFP, TWI_SCL_M); 7358fc0bfcdSHoratiu Vultur SERVALT_P(14, REF_CLK, IRQ0_OUT, SI); 7368fc0bfcdSHoratiu Vultur SERVALT_P(15, REF_CLK, IRQ1_OUT, SI); 7378fc0bfcdSHoratiu Vultur SERVALT_P(16, TACHO, SFP, SI); 7388fc0bfcdSHoratiu Vultur SERVALT_P(17, PWM, NONE, TWI_SCL_M); 7398fc0bfcdSHoratiu Vultur SERVALT_P(18, PTP2, SFP, SI); 7408fc0bfcdSHoratiu Vultur SERVALT_P(19, PTP3, SFP, SI); 7418fc0bfcdSHoratiu Vultur SERVALT_P(20, UART2, SFP, SI); 7428fc0bfcdSHoratiu Vultur SERVALT_P(21, UART2, NONE, NONE); 7438fc0bfcdSHoratiu Vultur SERVALT_P(22, MIIM, SFP, TWI2); 7448fc0bfcdSHoratiu Vultur SERVALT_P(23, MIIM, SFP, TWI2); 7458fc0bfcdSHoratiu Vultur SERVALT_P(24, TWI, NONE, NONE); 7468fc0bfcdSHoratiu Vultur SERVALT_P(25, TWI, SFP, TWI_SCL_M); 7478fc0bfcdSHoratiu Vultur SERVALT_P(26, TWI_SCL_M, SFP, SI); 7488fc0bfcdSHoratiu Vultur SERVALT_P(27, TWI_SCL_M, SFP, SI); 7498fc0bfcdSHoratiu Vultur SERVALT_P(28, TWI_SCL_M, SFP, SI); 7508fc0bfcdSHoratiu Vultur SERVALT_P(29, TWI_SCL_M, NONE, NONE); 7518fc0bfcdSHoratiu Vultur SERVALT_P(30, TWI_SCL_M, NONE, NONE); 7528fc0bfcdSHoratiu Vultur SERVALT_P(31, TWI_SCL_M, NONE, NONE); 7538fc0bfcdSHoratiu Vultur SERVALT_P(32, TWI_SCL_M, NONE, NONE); 7548fc0bfcdSHoratiu Vultur SERVALT_P(33, RCVRD_CLK, NONE, NONE); 7558fc0bfcdSHoratiu Vultur SERVALT_P(34, RCVRD_CLK, NONE, NONE); 7568fc0bfcdSHoratiu Vultur SERVALT_P(35, RCVRD_CLK, NONE, NONE); 7578fc0bfcdSHoratiu Vultur SERVALT_P(36, RCVRD_CLK, NONE, NONE); 7588fc0bfcdSHoratiu Vultur 7598fc0bfcdSHoratiu Vultur #define SERVALT_PIN(n) { \ 7608fc0bfcdSHoratiu Vultur .number = n, \ 7618fc0bfcdSHoratiu Vultur .name = "GPIO_"#n, \ 7628fc0bfcdSHoratiu Vultur .drv_data = &servalt_pin_##n \ 7638fc0bfcdSHoratiu Vultur } 7648fc0bfcdSHoratiu Vultur 7658fc0bfcdSHoratiu Vultur static const struct pinctrl_pin_desc servalt_pins[] = { 7668fc0bfcdSHoratiu Vultur SERVALT_PIN(0), 7678fc0bfcdSHoratiu Vultur SERVALT_PIN(1), 7688fc0bfcdSHoratiu Vultur SERVALT_PIN(2), 7698fc0bfcdSHoratiu Vultur SERVALT_PIN(3), 7708fc0bfcdSHoratiu Vultur SERVALT_PIN(4), 7718fc0bfcdSHoratiu Vultur SERVALT_PIN(5), 7728fc0bfcdSHoratiu Vultur SERVALT_PIN(6), 7738fc0bfcdSHoratiu Vultur SERVALT_PIN(7), 7748fc0bfcdSHoratiu Vultur SERVALT_PIN(8), 7758fc0bfcdSHoratiu Vultur SERVALT_PIN(9), 7768fc0bfcdSHoratiu Vultur SERVALT_PIN(10), 7778fc0bfcdSHoratiu Vultur SERVALT_PIN(11), 7788fc0bfcdSHoratiu Vultur SERVALT_PIN(12), 7798fc0bfcdSHoratiu Vultur SERVALT_PIN(13), 7808fc0bfcdSHoratiu Vultur SERVALT_PIN(14), 7818fc0bfcdSHoratiu Vultur SERVALT_PIN(15), 7828fc0bfcdSHoratiu Vultur SERVALT_PIN(16), 7838fc0bfcdSHoratiu Vultur SERVALT_PIN(17), 7848fc0bfcdSHoratiu Vultur SERVALT_PIN(18), 7858fc0bfcdSHoratiu Vultur SERVALT_PIN(19), 7868fc0bfcdSHoratiu Vultur SERVALT_PIN(20), 7878fc0bfcdSHoratiu Vultur SERVALT_PIN(21), 7888fc0bfcdSHoratiu Vultur SERVALT_PIN(22), 7898fc0bfcdSHoratiu Vultur SERVALT_PIN(23), 7908fc0bfcdSHoratiu Vultur SERVALT_PIN(24), 7918fc0bfcdSHoratiu Vultur SERVALT_PIN(25), 7928fc0bfcdSHoratiu Vultur SERVALT_PIN(26), 7938fc0bfcdSHoratiu Vultur SERVALT_PIN(27), 7948fc0bfcdSHoratiu Vultur SERVALT_PIN(28), 7958fc0bfcdSHoratiu Vultur SERVALT_PIN(29), 7968fc0bfcdSHoratiu Vultur SERVALT_PIN(30), 7978fc0bfcdSHoratiu Vultur SERVALT_PIN(31), 7988fc0bfcdSHoratiu Vultur SERVALT_PIN(32), 7998fc0bfcdSHoratiu Vultur SERVALT_PIN(33), 8008fc0bfcdSHoratiu Vultur SERVALT_PIN(34), 8018fc0bfcdSHoratiu Vultur SERVALT_PIN(35), 8028fc0bfcdSHoratiu Vultur SERVALT_PIN(36), 8038fc0bfcdSHoratiu Vultur }; 8048fc0bfcdSHoratiu Vultur 805f8a74760SLars Povlsen #define SPARX5_P(p, f0, f1, f2) \ 806f8a74760SLars Povlsen static struct ocelot_pin_caps sparx5_pin_##p = { \ 807f8a74760SLars Povlsen .pin = p, \ 808f8a74760SLars Povlsen .functions = { \ 809f8a74760SLars Povlsen FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2 \ 810f8a74760SLars Povlsen }, \ 811f8a74760SLars Povlsen } 812f8a74760SLars Povlsen 813f8a74760SLars Povlsen SPARX5_P(0, SG0, PLL_STAT, NONE); 814f8a74760SLars Povlsen SPARX5_P(1, SG0, NONE, NONE); 815f8a74760SLars Povlsen SPARX5_P(2, SG0, NONE, NONE); 816f8a74760SLars Povlsen SPARX5_P(3, SG0, NONE, NONE); 817f8a74760SLars Povlsen SPARX5_P(4, SG1, NONE, NONE); 818f8a74760SLars Povlsen SPARX5_P(5, SG1, NONE, NONE); 819f8a74760SLars Povlsen SPARX5_P(6, IRQ0_IN, IRQ0_OUT, SFP); 820f8a74760SLars Povlsen SPARX5_P(7, IRQ1_IN, IRQ1_OUT, SFP); 821f8a74760SLars Povlsen SPARX5_P(8, PTP0, NONE, SFP); 822f8a74760SLars Povlsen SPARX5_P(9, PTP1, SFP, TWI_SCL_M); 823f8a74760SLars Povlsen SPARX5_P(10, UART, NONE, NONE); 824f8a74760SLars Povlsen SPARX5_P(11, UART, NONE, NONE); 825f8a74760SLars Povlsen SPARX5_P(12, SG1, NONE, NONE); 826f8a74760SLars Povlsen SPARX5_P(13, SG1, NONE, NONE); 827f8a74760SLars Povlsen SPARX5_P(14, TWI, TWI_SCL_M, NONE); 828f8a74760SLars Povlsen SPARX5_P(15, TWI, NONE, NONE); 829f8a74760SLars Povlsen SPARX5_P(16, SI, TWI_SCL_M, SFP); 830f8a74760SLars Povlsen SPARX5_P(17, SI, TWI_SCL_M, SFP); 831f8a74760SLars Povlsen SPARX5_P(18, SI, TWI_SCL_M, SFP); 832f8a74760SLars Povlsen SPARX5_P(19, PCI_WAKE, TWI_SCL_M, SFP); 833f8a74760SLars Povlsen SPARX5_P(20, IRQ0_OUT, TWI_SCL_M, SFP); 834f8a74760SLars Povlsen SPARX5_P(21, IRQ1_OUT, TACHO, SFP); 835f8a74760SLars Povlsen SPARX5_P(22, TACHO, IRQ0_OUT, TWI_SCL_M); 836f8a74760SLars Povlsen SPARX5_P(23, PWM, UART3, TWI_SCL_M); 837f8a74760SLars Povlsen SPARX5_P(24, PTP2, UART3, TWI_SCL_M); 838f8a74760SLars Povlsen SPARX5_P(25, PTP3, SI, TWI_SCL_M); 839f8a74760SLars Povlsen SPARX5_P(26, UART2, SI, TWI_SCL_M); 840f8a74760SLars Povlsen SPARX5_P(27, UART2, SI, TWI_SCL_M); 841f8a74760SLars Povlsen SPARX5_P(28, TWI2, SI, SFP); 842f8a74760SLars Povlsen SPARX5_P(29, TWI2, SI, SFP); 843f8a74760SLars Povlsen SPARX5_P(30, SG2, SI, PWM); 844f8a74760SLars Povlsen SPARX5_P(31, SG2, SI, TWI_SCL_M); 845f8a74760SLars Povlsen SPARX5_P(32, SG2, SI, TWI_SCL_M); 846f8a74760SLars Povlsen SPARX5_P(33, SG2, SI, SFP); 847f8a74760SLars Povlsen SPARX5_P(34, NONE, TWI_SCL_M, EMMC); 848f8a74760SLars Povlsen SPARX5_P(35, SFP, TWI_SCL_M, EMMC); 849f8a74760SLars Povlsen SPARX5_P(36, SFP, TWI_SCL_M, EMMC); 850f8a74760SLars Povlsen SPARX5_P(37, SFP, NONE, EMMC); 851f8a74760SLars Povlsen SPARX5_P(38, NONE, TWI_SCL_M, EMMC); 852f8a74760SLars Povlsen SPARX5_P(39, SI2, TWI_SCL_M, EMMC); 853f8a74760SLars Povlsen SPARX5_P(40, SI2, TWI_SCL_M, EMMC); 854f8a74760SLars Povlsen SPARX5_P(41, SI2, TWI_SCL_M, EMMC); 855f8a74760SLars Povlsen SPARX5_P(42, SI2, TWI_SCL_M, EMMC); 856f8a74760SLars Povlsen SPARX5_P(43, SI2, TWI_SCL_M, EMMC); 857f8a74760SLars Povlsen SPARX5_P(44, SI, SFP, EMMC); 858f8a74760SLars Povlsen SPARX5_P(45, SI, SFP, EMMC); 859f8a74760SLars Povlsen SPARX5_P(46, NONE, SFP, EMMC); 860f8a74760SLars Povlsen SPARX5_P(47, NONE, SFP, EMMC); 861f8a74760SLars Povlsen SPARX5_P(48, TWI3, SI, SFP); 862f8a74760SLars Povlsen SPARX5_P(49, TWI3, NONE, SFP); 863f8a74760SLars Povlsen SPARX5_P(50, SFP, NONE, TWI_SCL_M); 864f8a74760SLars Povlsen SPARX5_P(51, SFP, SI, TWI_SCL_M); 865f8a74760SLars Povlsen SPARX5_P(52, SFP, MIIM, TWI_SCL_M); 866f8a74760SLars Povlsen SPARX5_P(53, SFP, MIIM, TWI_SCL_M); 867f8a74760SLars Povlsen SPARX5_P(54, SFP, PTP2, TWI_SCL_M); 868f8a74760SLars Povlsen SPARX5_P(55, SFP, PTP3, PCI_WAKE); 869f8a74760SLars Povlsen SPARX5_P(56, MIIM, SFP, TWI_SCL_M); 870f8a74760SLars Povlsen SPARX5_P(57, MIIM, SFP, TWI_SCL_M); 871f8a74760SLars Povlsen SPARX5_P(58, MIIM, SFP, TWI_SCL_M); 872f8a74760SLars Povlsen SPARX5_P(59, MIIM, SFP, NONE); 873f8a74760SLars Povlsen SPARX5_P(60, RECO_CLK, NONE, NONE); 874f8a74760SLars Povlsen SPARX5_P(61, RECO_CLK, NONE, NONE); 875f8a74760SLars Povlsen SPARX5_P(62, RECO_CLK, PLL_STAT, NONE); 876f8a74760SLars Povlsen SPARX5_P(63, RECO_CLK, NONE, NONE); 877f8a74760SLars Povlsen 878f8a74760SLars Povlsen #define SPARX5_PIN(n) { \ 879f8a74760SLars Povlsen .number = n, \ 880f8a74760SLars Povlsen .name = "GPIO_"#n, \ 881f8a74760SLars Povlsen .drv_data = &sparx5_pin_##n \ 882f8a74760SLars Povlsen } 883f8a74760SLars Povlsen 884f8a74760SLars Povlsen static const struct pinctrl_pin_desc sparx5_pins[] = { 885f8a74760SLars Povlsen SPARX5_PIN(0), 886f8a74760SLars Povlsen SPARX5_PIN(1), 887f8a74760SLars Povlsen SPARX5_PIN(2), 888f8a74760SLars Povlsen SPARX5_PIN(3), 889f8a74760SLars Povlsen SPARX5_PIN(4), 890f8a74760SLars Povlsen SPARX5_PIN(5), 891f8a74760SLars Povlsen SPARX5_PIN(6), 892f8a74760SLars Povlsen SPARX5_PIN(7), 893f8a74760SLars Povlsen SPARX5_PIN(8), 894f8a74760SLars Povlsen SPARX5_PIN(9), 895f8a74760SLars Povlsen SPARX5_PIN(10), 896f8a74760SLars Povlsen SPARX5_PIN(11), 897f8a74760SLars Povlsen SPARX5_PIN(12), 898f8a74760SLars Povlsen SPARX5_PIN(13), 899f8a74760SLars Povlsen SPARX5_PIN(14), 900f8a74760SLars Povlsen SPARX5_PIN(15), 901f8a74760SLars Povlsen SPARX5_PIN(16), 902f8a74760SLars Povlsen SPARX5_PIN(17), 903f8a74760SLars Povlsen SPARX5_PIN(18), 904f8a74760SLars Povlsen SPARX5_PIN(19), 905f8a74760SLars Povlsen SPARX5_PIN(20), 906f8a74760SLars Povlsen SPARX5_PIN(21), 907f8a74760SLars Povlsen SPARX5_PIN(22), 908f8a74760SLars Povlsen SPARX5_PIN(23), 909f8a74760SLars Povlsen SPARX5_PIN(24), 910f8a74760SLars Povlsen SPARX5_PIN(25), 911f8a74760SLars Povlsen SPARX5_PIN(26), 912f8a74760SLars Povlsen SPARX5_PIN(27), 913f8a74760SLars Povlsen SPARX5_PIN(28), 914f8a74760SLars Povlsen SPARX5_PIN(29), 915f8a74760SLars Povlsen SPARX5_PIN(30), 916f8a74760SLars Povlsen SPARX5_PIN(31), 917f8a74760SLars Povlsen SPARX5_PIN(32), 918f8a74760SLars Povlsen SPARX5_PIN(33), 919f8a74760SLars Povlsen SPARX5_PIN(34), 920f8a74760SLars Povlsen SPARX5_PIN(35), 921f8a74760SLars Povlsen SPARX5_PIN(36), 922f8a74760SLars Povlsen SPARX5_PIN(37), 923f8a74760SLars Povlsen SPARX5_PIN(38), 924f8a74760SLars Povlsen SPARX5_PIN(39), 925f8a74760SLars Povlsen SPARX5_PIN(40), 926f8a74760SLars Povlsen SPARX5_PIN(41), 927f8a74760SLars Povlsen SPARX5_PIN(42), 928f8a74760SLars Povlsen SPARX5_PIN(43), 929f8a74760SLars Povlsen SPARX5_PIN(44), 930f8a74760SLars Povlsen SPARX5_PIN(45), 931f8a74760SLars Povlsen SPARX5_PIN(46), 932f8a74760SLars Povlsen SPARX5_PIN(47), 933f8a74760SLars Povlsen SPARX5_PIN(48), 934f8a74760SLars Povlsen SPARX5_PIN(49), 935f8a74760SLars Povlsen SPARX5_PIN(50), 936f8a74760SLars Povlsen SPARX5_PIN(51), 937f8a74760SLars Povlsen SPARX5_PIN(52), 938f8a74760SLars Povlsen SPARX5_PIN(53), 939f8a74760SLars Povlsen SPARX5_PIN(54), 940f8a74760SLars Povlsen SPARX5_PIN(55), 941f8a74760SLars Povlsen SPARX5_PIN(56), 942f8a74760SLars Povlsen SPARX5_PIN(57), 943f8a74760SLars Povlsen SPARX5_PIN(58), 944f8a74760SLars Povlsen SPARX5_PIN(59), 945f8a74760SLars Povlsen SPARX5_PIN(60), 946f8a74760SLars Povlsen SPARX5_PIN(61), 947f8a74760SLars Povlsen SPARX5_PIN(62), 948f8a74760SLars Povlsen SPARX5_PIN(63), 949f8a74760SLars Povlsen }; 950f8a74760SLars Povlsen 951531d6ab3SKavyasree Kotagiri #define LAN966X_P(p, f0, f1, f2, f3, f4, f5, f6, f7) \ 952531d6ab3SKavyasree Kotagiri static struct ocelot_pin_caps lan966x_pin_##p = { \ 953531d6ab3SKavyasree Kotagiri .pin = p, \ 954531d6ab3SKavyasree Kotagiri .functions = { \ 955531d6ab3SKavyasree Kotagiri FUNC_##f0, FUNC_##f1, FUNC_##f2, \ 956531d6ab3SKavyasree Kotagiri FUNC_##f3 \ 957531d6ab3SKavyasree Kotagiri }, \ 958531d6ab3SKavyasree Kotagiri .a_functions = { \ 959531d6ab3SKavyasree Kotagiri FUNC_##f4, FUNC_##f5, FUNC_##f6, \ 960531d6ab3SKavyasree Kotagiri FUNC_##f7 \ 961531d6ab3SKavyasree Kotagiri }, \ 962531d6ab3SKavyasree Kotagiri } 963531d6ab3SKavyasree Kotagiri 964531d6ab3SKavyasree Kotagiri /* Pinmuxing table taken from data sheet */ 965531d6ab3SKavyasree Kotagiri /* Pin FUNC0 FUNC1 FUNC2 FUNC3 FUNC4 FUNC5 FUNC6 FUNC7 */ 966531d6ab3SKavyasree Kotagiri LAN966X_P(0, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 967531d6ab3SKavyasree Kotagiri LAN966X_P(1, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 968531d6ab3SKavyasree Kotagiri LAN966X_P(2, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 969531d6ab3SKavyasree Kotagiri LAN966X_P(3, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 970531d6ab3SKavyasree Kotagiri LAN966X_P(4, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 971531d6ab3SKavyasree Kotagiri LAN966X_P(5, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 972531d6ab3SKavyasree Kotagiri LAN966X_P(6, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 973531d6ab3SKavyasree Kotagiri LAN966X_P(7, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 974531d6ab3SKavyasree Kotagiri LAN966X_P(8, GPIO, FC0_a, USB_H_b, NONE, USB_S_b, NONE, NONE, R); 975531d6ab3SKavyasree Kotagiri LAN966X_P(9, GPIO, FC0_a, USB_H_b, NONE, NONE, NONE, NONE, R); 976531d6ab3SKavyasree Kotagiri LAN966X_P(10, GPIO, FC0_a, NONE, NONE, NONE, NONE, NONE, R); 977531d6ab3SKavyasree Kotagiri LAN966X_P(11, GPIO, FC1_a, NONE, NONE, NONE, NONE, NONE, R); 978531d6ab3SKavyasree Kotagiri LAN966X_P(12, GPIO, FC1_a, NONE, NONE, NONE, NONE, NONE, R); 979531d6ab3SKavyasree Kotagiri LAN966X_P(13, GPIO, FC1_a, NONE, NONE, NONE, NONE, NONE, R); 980531d6ab3SKavyasree Kotagiri LAN966X_P(14, GPIO, FC2_a, NONE, NONE, NONE, NONE, NONE, R); 981531d6ab3SKavyasree Kotagiri LAN966X_P(15, GPIO, FC2_a, NONE, NONE, NONE, NONE, NONE, R); 982531d6ab3SKavyasree Kotagiri LAN966X_P(16, GPIO, FC2_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, IRQ_OUT_c, R); 983531d6ab3SKavyasree Kotagiri LAN966X_P(17, GPIO, FC3_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, IRQ_OUT_c, R); 984531d6ab3SKavyasree Kotagiri LAN966X_P(18, GPIO, FC3_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, IRQ_OUT_c, R); 985531d6ab3SKavyasree Kotagiri LAN966X_P(19, GPIO, FC3_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, IRQ_OUT_c, R); 986531d6ab3SKavyasree Kotagiri LAN966X_P(20, GPIO, FC4_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, NONE, R); 987531d6ab3SKavyasree Kotagiri LAN966X_P(21, GPIO, FC4_a, NONE, NONE, OB_TRG_a, NONE, NONE, R); 988531d6ab3SKavyasree Kotagiri LAN966X_P(22, GPIO, FC4_a, NONE, NONE, OB_TRG_a, NONE, NONE, R); 989531d6ab3SKavyasree Kotagiri LAN966X_P(23, GPIO, NONE, NONE, NONE, OB_TRG_a, NONE, NONE, R); 990531d6ab3SKavyasree Kotagiri LAN966X_P(24, GPIO, FC0_b, IB_TRG_a, USB_H_c, OB_TRG_a, IRQ_IN_c, TACHO_a, R); 991531d6ab3SKavyasree Kotagiri LAN966X_P(25, GPIO, FC0_b, IB_TRG_a, USB_H_c, OB_TRG_a, IRQ_OUT_c, SFP_SD, R); 992531d6ab3SKavyasree Kotagiri LAN966X_P(26, GPIO, FC0_b, IB_TRG_a, USB_S_c, OB_TRG_a, CAN0_a, SFP_SD, R); 993e97e36cdSMichael Walle LAN966X_P(27, GPIO, NONE, NONE, NONE, OB_TRG_a, CAN0_a, PWM_a, R); 994531d6ab3SKavyasree Kotagiri LAN966X_P(28, GPIO, MIIM_a, NONE, NONE, OB_TRG_a, IRQ_OUT_c, SFP_SD, R); 995531d6ab3SKavyasree Kotagiri LAN966X_P(29, GPIO, MIIM_a, NONE, NONE, OB_TRG_a, NONE, NONE, R); 996bf3e7f49SMichael Walle LAN966X_P(30, GPIO, FC3_c, CAN1, CLKMON, OB_TRG, RECO_b, NONE, R); 997bf3e7f49SMichael Walle LAN966X_P(31, GPIO, FC3_c, CAN1, CLKMON, OB_TRG, RECO_b, NONE, R); 998531d6ab3SKavyasree Kotagiri LAN966X_P(32, GPIO, FC3_c, NONE, SGPIO_a, NONE, MIIM_Sa, NONE, R); 999531d6ab3SKavyasree Kotagiri LAN966X_P(33, GPIO, FC1_b, NONE, SGPIO_a, NONE, MIIM_Sa, MIIM_b, R); 1000531d6ab3SKavyasree Kotagiri LAN966X_P(34, GPIO, FC1_b, NONE, SGPIO_a, NONE, MIIM_Sa, MIIM_b, R); 1001d3683eebSHoratiu Vultur LAN966X_P(35, GPIO, FC1_b, PTPSYNC_0, SGPIO_a, CAN0_b, NONE, NONE, R); 1002531d6ab3SKavyasree Kotagiri LAN966X_P(36, GPIO, NONE, PTPSYNC_1, NONE, CAN0_b, NONE, NONE, R); 1003531d6ab3SKavyasree Kotagiri LAN966X_P(37, GPIO, FC_SHRD0, PTPSYNC_2, TWI_SLC_GATE_AD, NONE, NONE, NONE, R); 1004531d6ab3SKavyasree Kotagiri LAN966X_P(38, GPIO, NONE, PTPSYNC_3, NONE, NONE, NONE, NONE, R); 1005531d6ab3SKavyasree Kotagiri LAN966X_P(39, GPIO, NONE, PTPSYNC_4, NONE, NONE, NONE, NONE, R); 1006531d6ab3SKavyasree Kotagiri LAN966X_P(40, GPIO, FC_SHRD1, PTPSYNC_5, NONE, NONE, NONE, NONE, R); 1007531d6ab3SKavyasree Kotagiri LAN966X_P(41, GPIO, FC_SHRD2, PTPSYNC_6, TWI_SLC_GATE_AD, NONE, NONE, NONE, R); 1008531d6ab3SKavyasree Kotagiri LAN966X_P(42, GPIO, FC_SHRD3, PTPSYNC_7, TWI_SLC_GATE_AD, NONE, NONE, NONE, R); 1009531d6ab3SKavyasree Kotagiri LAN966X_P(43, GPIO, FC2_b, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, RECO_a, IRQ_IN_a, R); 1010531d6ab3SKavyasree Kotagiri LAN966X_P(44, GPIO, FC2_b, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, RECO_a, IRQ_IN_a, R); 1011531d6ab3SKavyasree Kotagiri LAN966X_P(45, GPIO, FC2_b, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, NONE, IRQ_IN_a, R); 1012531d6ab3SKavyasree Kotagiri LAN966X_P(46, GPIO, FC1_c, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, FC_SHRD4, IRQ_IN_a, R); 1013531d6ab3SKavyasree Kotagiri LAN966X_P(47, GPIO, FC1_c, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, FC_SHRD5, IRQ_IN_a, R); 1014531d6ab3SKavyasree Kotagiri LAN966X_P(48, GPIO, FC1_c, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, FC_SHRD6, IRQ_IN_a, R); 1015531d6ab3SKavyasree Kotagiri LAN966X_P(49, GPIO, FC_SHRD7, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, TWI_SLC_GATE, IRQ_IN_a, R); 1016531d6ab3SKavyasree Kotagiri LAN966X_P(50, GPIO, FC_SHRD16, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, TWI_SLC_GATE, NONE, R); 1017e97e36cdSMichael Walle LAN966X_P(51, GPIO, FC3_b, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, PWM_b, IRQ_IN_b, R); 1018531d6ab3SKavyasree Kotagiri LAN966X_P(52, GPIO, FC3_b, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, TACHO_b, IRQ_IN_b, R); 1019531d6ab3SKavyasree Kotagiri LAN966X_P(53, GPIO, FC3_b, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, NONE, IRQ_IN_b, R); 1020531d6ab3SKavyasree Kotagiri LAN966X_P(54, GPIO, FC_SHRD8, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, TWI_SLC_GATE, IRQ_IN_b, R); 1021531d6ab3SKavyasree Kotagiri LAN966X_P(55, GPIO, FC_SHRD9, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, TWI_SLC_GATE, IRQ_IN_b, R); 1022531d6ab3SKavyasree Kotagiri LAN966X_P(56, GPIO, FC4_b, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, FC_SHRD10, IRQ_IN_b, R); 1023531d6ab3SKavyasree Kotagiri LAN966X_P(57, GPIO, FC4_b, TWI_SLC_GATE, IB_TRG_c, IRQ_OUT_b, FC_SHRD11, IRQ_IN_b, R); 1024531d6ab3SKavyasree Kotagiri LAN966X_P(58, GPIO, FC4_b, TWI_SLC_GATE, IB_TRG_c, IRQ_OUT_b, FC_SHRD12, IRQ_IN_b, R); 1025531d6ab3SKavyasree Kotagiri LAN966X_P(59, GPIO, QSPI1, MIIM_c, NONE, NONE, MIIM_Sb, NONE, R); 1026531d6ab3SKavyasree Kotagiri LAN966X_P(60, GPIO, QSPI1, MIIM_c, NONE, NONE, MIIM_Sb, NONE, R); 1027531d6ab3SKavyasree Kotagiri LAN966X_P(61, GPIO, QSPI1, NONE, SGPIO_b, FC0_c, MIIM_Sb, NONE, R); 1028531d6ab3SKavyasree Kotagiri LAN966X_P(62, GPIO, QSPI1, FC_SHRD13, SGPIO_b, FC0_c, TWI_SLC_GATE, SFP_SD, R); 1029531d6ab3SKavyasree Kotagiri LAN966X_P(63, GPIO, QSPI1, FC_SHRD14, SGPIO_b, FC0_c, TWI_SLC_GATE, SFP_SD, R); 1030531d6ab3SKavyasree Kotagiri LAN966X_P(64, GPIO, QSPI1, FC4_c, SGPIO_b, FC_SHRD15, TWI_SLC_GATE, SFP_SD, R); 1031531d6ab3SKavyasree Kotagiri LAN966X_P(65, GPIO, USB_H_a, FC4_c, NONE, IRQ_OUT_c, TWI_SLC_GATE_AD, NONE, R); 1032531d6ab3SKavyasree Kotagiri LAN966X_P(66, GPIO, USB_H_a, FC4_c, USB_S_a, IRQ_OUT_c, IRQ_IN_c, NONE, R); 1033531d6ab3SKavyasree Kotagiri LAN966X_P(67, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R); 1034531d6ab3SKavyasree Kotagiri LAN966X_P(68, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R); 1035531d6ab3SKavyasree Kotagiri LAN966X_P(69, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R); 1036531d6ab3SKavyasree Kotagiri LAN966X_P(70, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R); 1037531d6ab3SKavyasree Kotagiri LAN966X_P(71, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R); 1038531d6ab3SKavyasree Kotagiri LAN966X_P(72, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R); 1039531d6ab3SKavyasree Kotagiri LAN966X_P(73, GPIO, EMMC, NONE, NONE, SD, NONE, NONE, R); 1040531d6ab3SKavyasree Kotagiri LAN966X_P(74, GPIO, EMMC, NONE, FC_SHRD17, SD, TWI_SLC_GATE, NONE, R); 1041531d6ab3SKavyasree Kotagiri LAN966X_P(75, GPIO, EMMC, NONE, FC_SHRD18, SD, TWI_SLC_GATE, NONE, R); 1042531d6ab3SKavyasree Kotagiri LAN966X_P(76, GPIO, EMMC, NONE, FC_SHRD19, SD, TWI_SLC_GATE, NONE, R); 1043531d6ab3SKavyasree Kotagiri LAN966X_P(77, GPIO, EMMC_SD, NONE, FC_SHRD20, NONE, TWI_SLC_GATE, NONE, R); 1044531d6ab3SKavyasree Kotagiri 1045531d6ab3SKavyasree Kotagiri #define LAN966X_PIN(n) { \ 1046531d6ab3SKavyasree Kotagiri .number = n, \ 1047531d6ab3SKavyasree Kotagiri .name = "GPIO_"#n, \ 1048531d6ab3SKavyasree Kotagiri .drv_data = &lan966x_pin_##n \ 1049531d6ab3SKavyasree Kotagiri } 1050531d6ab3SKavyasree Kotagiri 1051531d6ab3SKavyasree Kotagiri static const struct pinctrl_pin_desc lan966x_pins[] = { 1052531d6ab3SKavyasree Kotagiri LAN966X_PIN(0), 1053531d6ab3SKavyasree Kotagiri LAN966X_PIN(1), 1054531d6ab3SKavyasree Kotagiri LAN966X_PIN(2), 1055531d6ab3SKavyasree Kotagiri LAN966X_PIN(3), 1056531d6ab3SKavyasree Kotagiri LAN966X_PIN(4), 1057531d6ab3SKavyasree Kotagiri LAN966X_PIN(5), 1058531d6ab3SKavyasree Kotagiri LAN966X_PIN(6), 1059531d6ab3SKavyasree Kotagiri LAN966X_PIN(7), 1060531d6ab3SKavyasree Kotagiri LAN966X_PIN(8), 1061531d6ab3SKavyasree Kotagiri LAN966X_PIN(9), 1062531d6ab3SKavyasree Kotagiri LAN966X_PIN(10), 1063531d6ab3SKavyasree Kotagiri LAN966X_PIN(11), 1064531d6ab3SKavyasree Kotagiri LAN966X_PIN(12), 1065531d6ab3SKavyasree Kotagiri LAN966X_PIN(13), 1066531d6ab3SKavyasree Kotagiri LAN966X_PIN(14), 1067531d6ab3SKavyasree Kotagiri LAN966X_PIN(15), 1068531d6ab3SKavyasree Kotagiri LAN966X_PIN(16), 1069531d6ab3SKavyasree Kotagiri LAN966X_PIN(17), 1070531d6ab3SKavyasree Kotagiri LAN966X_PIN(18), 1071531d6ab3SKavyasree Kotagiri LAN966X_PIN(19), 1072531d6ab3SKavyasree Kotagiri LAN966X_PIN(20), 1073531d6ab3SKavyasree Kotagiri LAN966X_PIN(21), 1074531d6ab3SKavyasree Kotagiri LAN966X_PIN(22), 1075531d6ab3SKavyasree Kotagiri LAN966X_PIN(23), 1076531d6ab3SKavyasree Kotagiri LAN966X_PIN(24), 1077531d6ab3SKavyasree Kotagiri LAN966X_PIN(25), 1078531d6ab3SKavyasree Kotagiri LAN966X_PIN(26), 1079531d6ab3SKavyasree Kotagiri LAN966X_PIN(27), 1080531d6ab3SKavyasree Kotagiri LAN966X_PIN(28), 1081531d6ab3SKavyasree Kotagiri LAN966X_PIN(29), 1082531d6ab3SKavyasree Kotagiri LAN966X_PIN(30), 1083531d6ab3SKavyasree Kotagiri LAN966X_PIN(31), 1084531d6ab3SKavyasree Kotagiri LAN966X_PIN(32), 1085531d6ab3SKavyasree Kotagiri LAN966X_PIN(33), 1086531d6ab3SKavyasree Kotagiri LAN966X_PIN(34), 1087531d6ab3SKavyasree Kotagiri LAN966X_PIN(35), 1088531d6ab3SKavyasree Kotagiri LAN966X_PIN(36), 1089531d6ab3SKavyasree Kotagiri LAN966X_PIN(37), 1090531d6ab3SKavyasree Kotagiri LAN966X_PIN(38), 1091531d6ab3SKavyasree Kotagiri LAN966X_PIN(39), 1092531d6ab3SKavyasree Kotagiri LAN966X_PIN(40), 1093531d6ab3SKavyasree Kotagiri LAN966X_PIN(41), 1094531d6ab3SKavyasree Kotagiri LAN966X_PIN(42), 1095531d6ab3SKavyasree Kotagiri LAN966X_PIN(43), 1096531d6ab3SKavyasree Kotagiri LAN966X_PIN(44), 1097531d6ab3SKavyasree Kotagiri LAN966X_PIN(45), 1098531d6ab3SKavyasree Kotagiri LAN966X_PIN(46), 1099531d6ab3SKavyasree Kotagiri LAN966X_PIN(47), 1100531d6ab3SKavyasree Kotagiri LAN966X_PIN(48), 1101531d6ab3SKavyasree Kotagiri LAN966X_PIN(49), 1102531d6ab3SKavyasree Kotagiri LAN966X_PIN(50), 1103531d6ab3SKavyasree Kotagiri LAN966X_PIN(51), 1104531d6ab3SKavyasree Kotagiri LAN966X_PIN(52), 1105531d6ab3SKavyasree Kotagiri LAN966X_PIN(53), 1106531d6ab3SKavyasree Kotagiri LAN966X_PIN(54), 1107531d6ab3SKavyasree Kotagiri LAN966X_PIN(55), 1108531d6ab3SKavyasree Kotagiri LAN966X_PIN(56), 1109531d6ab3SKavyasree Kotagiri LAN966X_PIN(57), 1110531d6ab3SKavyasree Kotagiri LAN966X_PIN(58), 1111531d6ab3SKavyasree Kotagiri LAN966X_PIN(59), 1112531d6ab3SKavyasree Kotagiri LAN966X_PIN(60), 1113531d6ab3SKavyasree Kotagiri LAN966X_PIN(61), 1114531d6ab3SKavyasree Kotagiri LAN966X_PIN(62), 1115531d6ab3SKavyasree Kotagiri LAN966X_PIN(63), 1116531d6ab3SKavyasree Kotagiri LAN966X_PIN(64), 1117531d6ab3SKavyasree Kotagiri LAN966X_PIN(65), 1118531d6ab3SKavyasree Kotagiri LAN966X_PIN(66), 1119531d6ab3SKavyasree Kotagiri LAN966X_PIN(67), 1120531d6ab3SKavyasree Kotagiri LAN966X_PIN(68), 1121531d6ab3SKavyasree Kotagiri LAN966X_PIN(69), 1122531d6ab3SKavyasree Kotagiri LAN966X_PIN(70), 1123531d6ab3SKavyasree Kotagiri LAN966X_PIN(71), 1124531d6ab3SKavyasree Kotagiri LAN966X_PIN(72), 1125531d6ab3SKavyasree Kotagiri LAN966X_PIN(73), 1126531d6ab3SKavyasree Kotagiri LAN966X_PIN(74), 1127531d6ab3SKavyasree Kotagiri LAN966X_PIN(75), 1128531d6ab3SKavyasree Kotagiri LAN966X_PIN(76), 1129531d6ab3SKavyasree Kotagiri LAN966X_PIN(77), 1130531d6ab3SKavyasree Kotagiri }; 1131531d6ab3SKavyasree Kotagiri 1132ce8dc094SAlexandre Belloni static int ocelot_get_functions_count(struct pinctrl_dev *pctldev) 1133ce8dc094SAlexandre Belloni { 1134ce8dc094SAlexandre Belloni return ARRAY_SIZE(ocelot_function_names); 1135ce8dc094SAlexandre Belloni } 1136ce8dc094SAlexandre Belloni 1137ce8dc094SAlexandre Belloni static const char *ocelot_get_function_name(struct pinctrl_dev *pctldev, 1138ce8dc094SAlexandre Belloni unsigned int function) 1139ce8dc094SAlexandre Belloni { 1140ce8dc094SAlexandre Belloni return ocelot_function_names[function]; 1141ce8dc094SAlexandre Belloni } 1142ce8dc094SAlexandre Belloni 1143ce8dc094SAlexandre Belloni static int ocelot_get_function_groups(struct pinctrl_dev *pctldev, 1144ce8dc094SAlexandre Belloni unsigned int function, 1145ce8dc094SAlexandre Belloni const char *const **groups, 1146ce8dc094SAlexandre Belloni unsigned *const num_groups) 1147ce8dc094SAlexandre Belloni { 1148ce8dc094SAlexandre Belloni struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1149ce8dc094SAlexandre Belloni 1150ce8dc094SAlexandre Belloni *groups = info->func[function].groups; 1151ce8dc094SAlexandre Belloni *num_groups = info->func[function].ngroups; 1152ce8dc094SAlexandre Belloni 1153ce8dc094SAlexandre Belloni return 0; 1154ce8dc094SAlexandre Belloni } 1155ce8dc094SAlexandre Belloni 1156da801ab5SAlexandre Belloni static int ocelot_pin_function_idx(struct ocelot_pinctrl *info, 1157da801ab5SAlexandre Belloni unsigned int pin, unsigned int function) 1158ce8dc094SAlexandre Belloni { 1159da801ab5SAlexandre Belloni struct ocelot_pin_caps *p = info->desc->pins[pin].drv_data; 1160ce8dc094SAlexandre Belloni int i; 1161ce8dc094SAlexandre Belloni 1162ce8dc094SAlexandre Belloni for (i = 0; i < OCELOT_FUNC_PER_PIN; i++) { 1163ce8dc094SAlexandre Belloni if (function == p->functions[i]) 1164ce8dc094SAlexandre Belloni return i; 1165531d6ab3SKavyasree Kotagiri 1166531d6ab3SKavyasree Kotagiri if (function == p->a_functions[i]) 1167531d6ab3SKavyasree Kotagiri return i + OCELOT_FUNC_PER_PIN; 1168ce8dc094SAlexandre Belloni } 1169ce8dc094SAlexandre Belloni 1170ce8dc094SAlexandre Belloni return -1; 1171ce8dc094SAlexandre Belloni } 1172ce8dc094SAlexandre Belloni 11734b36082eSAlexandre Belloni #define REG_ALT(msb, info, p) (OCELOT_GPIO_ALT0 * (info)->stride + 4 * ((msb) + ((info)->stride * ((p) / 32)))) 1174da801ab5SAlexandre Belloni 1175ce8dc094SAlexandre Belloni static int ocelot_pinmux_set_mux(struct pinctrl_dev *pctldev, 1176ce8dc094SAlexandre Belloni unsigned int selector, unsigned int group) 1177ce8dc094SAlexandre Belloni { 1178ce8dc094SAlexandre Belloni struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1179da801ab5SAlexandre Belloni struct ocelot_pin_caps *pin = info->desc->pins[group].drv_data; 1180da801ab5SAlexandre Belloni unsigned int p = pin->pin % 32; 1181ce8dc094SAlexandre Belloni int f; 1182ce8dc094SAlexandre Belloni 1183da801ab5SAlexandre Belloni f = ocelot_pin_function_idx(info, group, selector); 1184ce8dc094SAlexandre Belloni if (f < 0) 1185ce8dc094SAlexandre Belloni return -EINVAL; 1186ce8dc094SAlexandre Belloni 1187ce8dc094SAlexandre Belloni /* 1188ce8dc094SAlexandre Belloni * f is encoded on two bits. 11894b36082eSAlexandre Belloni * bit 0 of f goes in BIT(pin) of ALT[0], bit 1 of f goes in BIT(pin) of 11904b36082eSAlexandre Belloni * ALT[1] 1191ce8dc094SAlexandre Belloni * This is racy because both registers can't be updated at the same time 1192ce8dc094SAlexandre Belloni * but it doesn't matter much for now. 1193f8a74760SLars Povlsen * Note: ALT0/ALT1 are organized specially for 64 gpio targets 1194ce8dc094SAlexandre Belloni */ 11954b36082eSAlexandre Belloni regmap_update_bits(info->map, REG_ALT(0, info, pin->pin), 1196da801ab5SAlexandre Belloni BIT(p), f << p); 11974b36082eSAlexandre Belloni regmap_update_bits(info->map, REG_ALT(1, info, pin->pin), 1198da801ab5SAlexandre Belloni BIT(p), f << (p - 1)); 1199ce8dc094SAlexandre Belloni 1200ce8dc094SAlexandre Belloni return 0; 1201ce8dc094SAlexandre Belloni } 1202ce8dc094SAlexandre Belloni 1203531d6ab3SKavyasree Kotagiri static int lan966x_pinmux_set_mux(struct pinctrl_dev *pctldev, 1204531d6ab3SKavyasree Kotagiri unsigned int selector, unsigned int group) 1205531d6ab3SKavyasree Kotagiri { 1206531d6ab3SKavyasree Kotagiri struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1207531d6ab3SKavyasree Kotagiri struct ocelot_pin_caps *pin = info->desc->pins[group].drv_data; 1208531d6ab3SKavyasree Kotagiri unsigned int p = pin->pin % 32; 1209531d6ab3SKavyasree Kotagiri int f; 1210531d6ab3SKavyasree Kotagiri 1211531d6ab3SKavyasree Kotagiri f = ocelot_pin_function_idx(info, group, selector); 1212531d6ab3SKavyasree Kotagiri if (f < 0) 1213531d6ab3SKavyasree Kotagiri return -EINVAL; 1214531d6ab3SKavyasree Kotagiri 1215531d6ab3SKavyasree Kotagiri /* 1216531d6ab3SKavyasree Kotagiri * f is encoded on three bits. 1217531d6ab3SKavyasree Kotagiri * bit 0 of f goes in BIT(pin) of ALT[0], bit 1 of f goes in BIT(pin) of 1218531d6ab3SKavyasree Kotagiri * ALT[1], bit 2 of f goes in BIT(pin) of ALT[2] 1219531d6ab3SKavyasree Kotagiri * This is racy because three registers can't be updated at the same time 1220531d6ab3SKavyasree Kotagiri * but it doesn't matter much for now. 1221531d6ab3SKavyasree Kotagiri * Note: ALT0/ALT1/ALT2 are organized specially for 78 gpio targets 1222531d6ab3SKavyasree Kotagiri */ 1223531d6ab3SKavyasree Kotagiri regmap_update_bits(info->map, REG_ALT(0, info, pin->pin), 1224531d6ab3SKavyasree Kotagiri BIT(p), f << p); 1225531d6ab3SKavyasree Kotagiri regmap_update_bits(info->map, REG_ALT(1, info, pin->pin), 1226531d6ab3SKavyasree Kotagiri BIT(p), (f >> 1) << p); 1227531d6ab3SKavyasree Kotagiri regmap_update_bits(info->map, REG_ALT(2, info, pin->pin), 1228531d6ab3SKavyasree Kotagiri BIT(p), (f >> 2) << p); 1229531d6ab3SKavyasree Kotagiri 1230531d6ab3SKavyasree Kotagiri return 0; 1231531d6ab3SKavyasree Kotagiri } 1232531d6ab3SKavyasree Kotagiri 12334b36082eSAlexandre Belloni #define REG(r, info, p) ((r) * (info)->stride + (4 * ((p) / 32))) 12344b36082eSAlexandre Belloni 1235ce8dc094SAlexandre Belloni static int ocelot_gpio_set_direction(struct pinctrl_dev *pctldev, 1236ce8dc094SAlexandre Belloni struct pinctrl_gpio_range *range, 1237ce8dc094SAlexandre Belloni unsigned int pin, bool input) 1238ce8dc094SAlexandre Belloni { 1239ce8dc094SAlexandre Belloni struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1240da801ab5SAlexandre Belloni unsigned int p = pin % 32; 1241ce8dc094SAlexandre Belloni 1242f2818ba3SAlexandre Belloni regmap_update_bits(info->map, REG(OCELOT_GPIO_OE, info, pin), BIT(p), 1243da801ab5SAlexandre Belloni input ? 0 : BIT(p)); 1244ce8dc094SAlexandre Belloni 1245ce8dc094SAlexandre Belloni return 0; 1246ce8dc094SAlexandre Belloni } 1247ce8dc094SAlexandre Belloni 1248ce8dc094SAlexandre Belloni static int ocelot_gpio_request_enable(struct pinctrl_dev *pctldev, 1249ce8dc094SAlexandre Belloni struct pinctrl_gpio_range *range, 1250ce8dc094SAlexandre Belloni unsigned int offset) 1251ce8dc094SAlexandre Belloni { 1252ce8dc094SAlexandre Belloni struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1253da801ab5SAlexandre Belloni unsigned int p = offset % 32; 1254ce8dc094SAlexandre Belloni 12554b36082eSAlexandre Belloni regmap_update_bits(info->map, REG_ALT(0, info, offset), 1256da801ab5SAlexandre Belloni BIT(p), 0); 12574b36082eSAlexandre Belloni regmap_update_bits(info->map, REG_ALT(1, info, offset), 1258da801ab5SAlexandre Belloni BIT(p), 0); 1259ce8dc094SAlexandre Belloni 1260ce8dc094SAlexandre Belloni return 0; 1261ce8dc094SAlexandre Belloni } 1262ce8dc094SAlexandre Belloni 1263531d6ab3SKavyasree Kotagiri static int lan966x_gpio_request_enable(struct pinctrl_dev *pctldev, 1264531d6ab3SKavyasree Kotagiri struct pinctrl_gpio_range *range, 1265531d6ab3SKavyasree Kotagiri unsigned int offset) 1266531d6ab3SKavyasree Kotagiri { 1267531d6ab3SKavyasree Kotagiri struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1268531d6ab3SKavyasree Kotagiri unsigned int p = offset % 32; 1269531d6ab3SKavyasree Kotagiri 1270531d6ab3SKavyasree Kotagiri regmap_update_bits(info->map, REG_ALT(0, info, offset), 1271531d6ab3SKavyasree Kotagiri BIT(p), 0); 1272531d6ab3SKavyasree Kotagiri regmap_update_bits(info->map, REG_ALT(1, info, offset), 1273531d6ab3SKavyasree Kotagiri BIT(p), 0); 1274531d6ab3SKavyasree Kotagiri regmap_update_bits(info->map, REG_ALT(2, info, offset), 1275531d6ab3SKavyasree Kotagiri BIT(p), 0); 1276531d6ab3SKavyasree Kotagiri 1277531d6ab3SKavyasree Kotagiri return 0; 1278531d6ab3SKavyasree Kotagiri } 1279531d6ab3SKavyasree Kotagiri 1280ce8dc094SAlexandre Belloni static const struct pinmux_ops ocelot_pmx_ops = { 1281ce8dc094SAlexandre Belloni .get_functions_count = ocelot_get_functions_count, 1282ce8dc094SAlexandre Belloni .get_function_name = ocelot_get_function_name, 1283ce8dc094SAlexandre Belloni .get_function_groups = ocelot_get_function_groups, 1284ce8dc094SAlexandre Belloni .set_mux = ocelot_pinmux_set_mux, 1285ce8dc094SAlexandre Belloni .gpio_set_direction = ocelot_gpio_set_direction, 1286ce8dc094SAlexandre Belloni .gpio_request_enable = ocelot_gpio_request_enable, 1287ce8dc094SAlexandre Belloni }; 1288ce8dc094SAlexandre Belloni 1289531d6ab3SKavyasree Kotagiri static const struct pinmux_ops lan966x_pmx_ops = { 1290531d6ab3SKavyasree Kotagiri .get_functions_count = ocelot_get_functions_count, 1291531d6ab3SKavyasree Kotagiri .get_function_name = ocelot_get_function_name, 1292531d6ab3SKavyasree Kotagiri .get_function_groups = ocelot_get_function_groups, 1293531d6ab3SKavyasree Kotagiri .set_mux = lan966x_pinmux_set_mux, 1294531d6ab3SKavyasree Kotagiri .gpio_set_direction = ocelot_gpio_set_direction, 1295531d6ab3SKavyasree Kotagiri .gpio_request_enable = lan966x_gpio_request_enable, 1296531d6ab3SKavyasree Kotagiri }; 1297531d6ab3SKavyasree Kotagiri 1298ce8dc094SAlexandre Belloni static int ocelot_pctl_get_groups_count(struct pinctrl_dev *pctldev) 1299ce8dc094SAlexandre Belloni { 1300da801ab5SAlexandre Belloni struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1301da801ab5SAlexandre Belloni 1302da801ab5SAlexandre Belloni return info->desc->npins; 1303ce8dc094SAlexandre Belloni } 1304ce8dc094SAlexandre Belloni 1305ce8dc094SAlexandre Belloni static const char *ocelot_pctl_get_group_name(struct pinctrl_dev *pctldev, 1306ce8dc094SAlexandre Belloni unsigned int group) 1307ce8dc094SAlexandre Belloni { 1308da801ab5SAlexandre Belloni struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1309da801ab5SAlexandre Belloni 1310da801ab5SAlexandre Belloni return info->desc->pins[group].name; 1311ce8dc094SAlexandre Belloni } 1312ce8dc094SAlexandre Belloni 1313ce8dc094SAlexandre Belloni static int ocelot_pctl_get_group_pins(struct pinctrl_dev *pctldev, 1314ce8dc094SAlexandre Belloni unsigned int group, 1315ce8dc094SAlexandre Belloni const unsigned int **pins, 1316ce8dc094SAlexandre Belloni unsigned int *num_pins) 1317ce8dc094SAlexandre Belloni { 1318da801ab5SAlexandre Belloni struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1319da801ab5SAlexandre Belloni 1320da801ab5SAlexandre Belloni *pins = &info->desc->pins[group].number; 1321ce8dc094SAlexandre Belloni *num_pins = 1; 1322ce8dc094SAlexandre Belloni 1323ce8dc094SAlexandre Belloni return 0; 1324ce8dc094SAlexandre Belloni } 1325ce8dc094SAlexandre Belloni 1326f8a74760SLars Povlsen static int ocelot_hw_get_value(struct ocelot_pinctrl *info, 1327f8a74760SLars Povlsen unsigned int pin, 1328f8a74760SLars Povlsen unsigned int reg, 1329f8a74760SLars Povlsen int *val) 1330f8a74760SLars Povlsen { 1331f8a74760SLars Povlsen int ret = -EOPNOTSUPP; 1332f8a74760SLars Povlsen 1333f8a74760SLars Povlsen if (info->pincfg) { 1334dc62db71SHoratiu Vultur const struct ocelot_pincfg_data *opd = info->pincfg_data; 1335076d9e71SColin Foster u32 regcfg; 1336076d9e71SColin Foster 1337*ba9c4745SHoratiu Vultur ret = regmap_read(info->pincfg, 1338*ba9c4745SHoratiu Vultur pin * regmap_get_reg_stride(info->pincfg), 1339*ba9c4745SHoratiu Vultur ®cfg); 1340076d9e71SColin Foster if (ret) 1341076d9e71SColin Foster return ret; 1342f8a74760SLars Povlsen 1343f8a74760SLars Povlsen ret = 0; 1344f8a74760SLars Povlsen switch (reg) { 1345f8a74760SLars Povlsen case PINCONF_BIAS: 1346dc62db71SHoratiu Vultur *val = regcfg & (opd->pd_bit | opd->pu_bit); 1347f8a74760SLars Povlsen break; 1348f8a74760SLars Povlsen 1349f8a74760SLars Povlsen case PINCONF_SCHMITT: 1350dc62db71SHoratiu Vultur *val = regcfg & opd->schmitt_bit; 1351f8a74760SLars Povlsen break; 1352f8a74760SLars Povlsen 1353f8a74760SLars Povlsen case PINCONF_DRIVE_STRENGTH: 1354dc62db71SHoratiu Vultur *val = regcfg & opd->drive_bits; 1355f8a74760SLars Povlsen break; 1356f8a74760SLars Povlsen 1357f8a74760SLars Povlsen default: 1358f8a74760SLars Povlsen ret = -EOPNOTSUPP; 1359f8a74760SLars Povlsen break; 1360f8a74760SLars Povlsen } 1361f8a74760SLars Povlsen } 1362f8a74760SLars Povlsen return ret; 1363f8a74760SLars Povlsen } 1364f8a74760SLars Povlsen 1365076d9e71SColin Foster static int ocelot_pincfg_clrsetbits(struct ocelot_pinctrl *info, u32 regaddr, 1366076d9e71SColin Foster u32 clrbits, u32 setbits) 1367076d9e71SColin Foster { 1368076d9e71SColin Foster u32 val; 1369076d9e71SColin Foster int ret; 1370076d9e71SColin Foster 1371*ba9c4745SHoratiu Vultur ret = regmap_read(info->pincfg, 1372*ba9c4745SHoratiu Vultur regaddr * regmap_get_reg_stride(info->pincfg), 1373*ba9c4745SHoratiu Vultur &val); 1374076d9e71SColin Foster if (ret) 1375076d9e71SColin Foster return ret; 1376076d9e71SColin Foster 1377076d9e71SColin Foster val &= ~clrbits; 1378076d9e71SColin Foster val |= setbits; 1379076d9e71SColin Foster 1380*ba9c4745SHoratiu Vultur ret = regmap_write(info->pincfg, 1381*ba9c4745SHoratiu Vultur regaddr * regmap_get_reg_stride(info->pincfg), 1382*ba9c4745SHoratiu Vultur val); 1383076d9e71SColin Foster 1384076d9e71SColin Foster return ret; 1385076d9e71SColin Foster } 1386076d9e71SColin Foster 1387f8a74760SLars Povlsen static int ocelot_hw_set_value(struct ocelot_pinctrl *info, 1388f8a74760SLars Povlsen unsigned int pin, 1389f8a74760SLars Povlsen unsigned int reg, 1390f8a74760SLars Povlsen int val) 1391f8a74760SLars Povlsen { 1392f8a74760SLars Povlsen int ret = -EOPNOTSUPP; 1393f8a74760SLars Povlsen 1394f8a74760SLars Povlsen if (info->pincfg) { 1395dc62db71SHoratiu Vultur const struct ocelot_pincfg_data *opd = info->pincfg_data; 1396f8a74760SLars Povlsen 1397f8a74760SLars Povlsen ret = 0; 1398f8a74760SLars Povlsen switch (reg) { 1399f8a74760SLars Povlsen case PINCONF_BIAS: 1400dc62db71SHoratiu Vultur ret = ocelot_pincfg_clrsetbits(info, pin, 1401dc62db71SHoratiu Vultur opd->pd_bit | opd->pu_bit, 1402076d9e71SColin Foster val); 1403f8a74760SLars Povlsen break; 1404f8a74760SLars Povlsen 1405f8a74760SLars Povlsen case PINCONF_SCHMITT: 1406dc62db71SHoratiu Vultur ret = ocelot_pincfg_clrsetbits(info, pin, 1407dc62db71SHoratiu Vultur opd->schmitt_bit, 1408076d9e71SColin Foster val); 1409f8a74760SLars Povlsen break; 1410f8a74760SLars Povlsen 1411f8a74760SLars Povlsen case PINCONF_DRIVE_STRENGTH: 1412f8a74760SLars Povlsen if (val <= 3) 1413076d9e71SColin Foster ret = ocelot_pincfg_clrsetbits(info, pin, 1414dc62db71SHoratiu Vultur opd->drive_bits, 1415dc62db71SHoratiu Vultur val); 1416f8a74760SLars Povlsen else 1417f8a74760SLars Povlsen ret = -EINVAL; 1418f8a74760SLars Povlsen break; 1419f8a74760SLars Povlsen 1420f8a74760SLars Povlsen default: 1421f8a74760SLars Povlsen ret = -EOPNOTSUPP; 1422f8a74760SLars Povlsen break; 1423f8a74760SLars Povlsen } 1424f8a74760SLars Povlsen } 1425f8a74760SLars Povlsen return ret; 1426f8a74760SLars Povlsen } 1427f8a74760SLars Povlsen 1428f8a74760SLars Povlsen static int ocelot_pinconf_get(struct pinctrl_dev *pctldev, 1429f8a74760SLars Povlsen unsigned int pin, unsigned long *config) 1430f8a74760SLars Povlsen { 1431f8a74760SLars Povlsen struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1432f8a74760SLars Povlsen u32 param = pinconf_to_config_param(*config); 1433f8a74760SLars Povlsen int val, err; 1434f8a74760SLars Povlsen 1435f8a74760SLars Povlsen switch (param) { 1436f8a74760SLars Povlsen case PIN_CONFIG_BIAS_DISABLE: 1437f8a74760SLars Povlsen case PIN_CONFIG_BIAS_PULL_UP: 1438f8a74760SLars Povlsen case PIN_CONFIG_BIAS_PULL_DOWN: 1439f8a74760SLars Povlsen err = ocelot_hw_get_value(info, pin, PINCONF_BIAS, &val); 1440f8a74760SLars Povlsen if (err) 1441f8a74760SLars Povlsen return err; 1442f8a74760SLars Povlsen if (param == PIN_CONFIG_BIAS_DISABLE) 144354515257SKaixu Xia val = (val == 0); 1444f8a74760SLars Povlsen else if (param == PIN_CONFIG_BIAS_PULL_DOWN) 1445dc62db71SHoratiu Vultur val = !!(val & info->pincfg_data->pd_bit); 1446f8a74760SLars Povlsen else /* PIN_CONFIG_BIAS_PULL_UP */ 1447dc62db71SHoratiu Vultur val = !!(val & info->pincfg_data->pu_bit); 1448f8a74760SLars Povlsen break; 1449f8a74760SLars Povlsen 1450f8a74760SLars Povlsen case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 1451dc62db71SHoratiu Vultur if (!info->pincfg_data->schmitt_bit) 1452dc62db71SHoratiu Vultur return -EOPNOTSUPP; 1453dc62db71SHoratiu Vultur 1454f8a74760SLars Povlsen err = ocelot_hw_get_value(info, pin, PINCONF_SCHMITT, &val); 1455f8a74760SLars Povlsen if (err) 1456f8a74760SLars Povlsen return err; 1457f8a74760SLars Povlsen 1458dc62db71SHoratiu Vultur val = !!(val & info->pincfg_data->schmitt_bit); 1459f8a74760SLars Povlsen break; 1460f8a74760SLars Povlsen 1461f8a74760SLars Povlsen case PIN_CONFIG_DRIVE_STRENGTH: 1462f8a74760SLars Povlsen err = ocelot_hw_get_value(info, pin, PINCONF_DRIVE_STRENGTH, 1463f8a74760SLars Povlsen &val); 1464f8a74760SLars Povlsen if (err) 1465f8a74760SLars Povlsen return err; 1466f8a74760SLars Povlsen break; 1467f8a74760SLars Povlsen 1468f8a74760SLars Povlsen case PIN_CONFIG_OUTPUT: 1469f8a74760SLars Povlsen err = regmap_read(info->map, REG(OCELOT_GPIO_OUT, info, pin), 1470f8a74760SLars Povlsen &val); 1471f8a74760SLars Povlsen if (err) 1472f8a74760SLars Povlsen return err; 1473f8a74760SLars Povlsen val = !!(val & BIT(pin % 32)); 1474f8a74760SLars Povlsen break; 1475f8a74760SLars Povlsen 1476f8a74760SLars Povlsen case PIN_CONFIG_INPUT_ENABLE: 1477f8a74760SLars Povlsen case PIN_CONFIG_OUTPUT_ENABLE: 1478f8a74760SLars Povlsen err = regmap_read(info->map, REG(OCELOT_GPIO_OE, info, pin), 1479f8a74760SLars Povlsen &val); 1480f8a74760SLars Povlsen if (err) 1481f8a74760SLars Povlsen return err; 1482f8a74760SLars Povlsen val = val & BIT(pin % 32); 1483f8a74760SLars Povlsen if (param == PIN_CONFIG_OUTPUT_ENABLE) 1484f8a74760SLars Povlsen val = !!val; 1485f8a74760SLars Povlsen else 1486f8a74760SLars Povlsen val = !val; 1487f8a74760SLars Povlsen break; 1488f8a74760SLars Povlsen 1489f8a74760SLars Povlsen default: 1490f8a74760SLars Povlsen return -EOPNOTSUPP; 1491f8a74760SLars Povlsen } 1492f8a74760SLars Povlsen 1493f8a74760SLars Povlsen *config = pinconf_to_config_packed(param, val); 1494f8a74760SLars Povlsen 1495f8a74760SLars Povlsen return 0; 1496f8a74760SLars Povlsen } 1497f8a74760SLars Povlsen 1498f8a74760SLars Povlsen static int ocelot_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 1499f8a74760SLars Povlsen unsigned long *configs, unsigned int num_configs) 1500f8a74760SLars Povlsen { 1501f8a74760SLars Povlsen struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1502dc62db71SHoratiu Vultur const struct ocelot_pincfg_data *opd = info->pincfg_data; 1503f8a74760SLars Povlsen u32 param, arg, p; 1504f8a74760SLars Povlsen int cfg, err = 0; 1505f8a74760SLars Povlsen 1506f8a74760SLars Povlsen for (cfg = 0; cfg < num_configs; cfg++) { 1507f8a74760SLars Povlsen param = pinconf_to_config_param(configs[cfg]); 1508f8a74760SLars Povlsen arg = pinconf_to_config_argument(configs[cfg]); 1509f8a74760SLars Povlsen 1510f8a74760SLars Povlsen switch (param) { 1511f8a74760SLars Povlsen case PIN_CONFIG_BIAS_DISABLE: 1512f8a74760SLars Povlsen case PIN_CONFIG_BIAS_PULL_UP: 1513f8a74760SLars Povlsen case PIN_CONFIG_BIAS_PULL_DOWN: 1514f8a74760SLars Povlsen arg = (param == PIN_CONFIG_BIAS_DISABLE) ? 0 : 1515dc62db71SHoratiu Vultur (param == PIN_CONFIG_BIAS_PULL_UP) ? 1516dc62db71SHoratiu Vultur opd->pu_bit : opd->pd_bit; 1517f8a74760SLars Povlsen 1518f8a74760SLars Povlsen err = ocelot_hw_set_value(info, pin, PINCONF_BIAS, arg); 1519f8a74760SLars Povlsen if (err) 1520f8a74760SLars Povlsen goto err; 1521f8a74760SLars Povlsen 1522f8a74760SLars Povlsen break; 1523f8a74760SLars Povlsen 1524f8a74760SLars Povlsen case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 1525dc62db71SHoratiu Vultur if (!opd->schmitt_bit) 1526dc62db71SHoratiu Vultur return -EOPNOTSUPP; 1527dc62db71SHoratiu Vultur 1528dc62db71SHoratiu Vultur arg = arg ? opd->schmitt_bit : 0; 1529f8a74760SLars Povlsen err = ocelot_hw_set_value(info, pin, PINCONF_SCHMITT, 1530f8a74760SLars Povlsen arg); 1531f8a74760SLars Povlsen if (err) 1532f8a74760SLars Povlsen goto err; 1533f8a74760SLars Povlsen 1534f8a74760SLars Povlsen break; 1535f8a74760SLars Povlsen 1536f8a74760SLars Povlsen case PIN_CONFIG_DRIVE_STRENGTH: 1537f8a74760SLars Povlsen err = ocelot_hw_set_value(info, pin, 1538f8a74760SLars Povlsen PINCONF_DRIVE_STRENGTH, 1539f8a74760SLars Povlsen arg); 1540f8a74760SLars Povlsen if (err) 1541f8a74760SLars Povlsen goto err; 1542f8a74760SLars Povlsen 1543f8a74760SLars Povlsen break; 1544f8a74760SLars Povlsen 1545f8a74760SLars Povlsen case PIN_CONFIG_OUTPUT_ENABLE: 1546f8a74760SLars Povlsen case PIN_CONFIG_INPUT_ENABLE: 1547f8a74760SLars Povlsen case PIN_CONFIG_OUTPUT: 1548f8a74760SLars Povlsen p = pin % 32; 1549f8a74760SLars Povlsen if (arg) 1550f8a74760SLars Povlsen regmap_write(info->map, 1551f8a74760SLars Povlsen REG(OCELOT_GPIO_OUT_SET, info, 1552f8a74760SLars Povlsen pin), 1553f8a74760SLars Povlsen BIT(p)); 1554f8a74760SLars Povlsen else 1555f8a74760SLars Povlsen regmap_write(info->map, 1556f8a74760SLars Povlsen REG(OCELOT_GPIO_OUT_CLR, info, 1557f8a74760SLars Povlsen pin), 1558f8a74760SLars Povlsen BIT(p)); 1559f8a74760SLars Povlsen regmap_update_bits(info->map, 1560f8a74760SLars Povlsen REG(OCELOT_GPIO_OE, info, pin), 1561f8a74760SLars Povlsen BIT(p), 1562f8a74760SLars Povlsen param == PIN_CONFIG_INPUT_ENABLE ? 1563f8a74760SLars Povlsen 0 : BIT(p)); 1564f8a74760SLars Povlsen break; 1565f8a74760SLars Povlsen 1566f8a74760SLars Povlsen default: 1567f8a74760SLars Povlsen err = -EOPNOTSUPP; 1568f8a74760SLars Povlsen } 1569f8a74760SLars Povlsen } 1570f8a74760SLars Povlsen err: 1571f8a74760SLars Povlsen return err; 1572f8a74760SLars Povlsen } 1573f8a74760SLars Povlsen 1574f8a74760SLars Povlsen static const struct pinconf_ops ocelot_confops = { 1575f8a74760SLars Povlsen .is_generic = true, 1576f8a74760SLars Povlsen .pin_config_get = ocelot_pinconf_get, 1577f8a74760SLars Povlsen .pin_config_set = ocelot_pinconf_set, 1578f8a74760SLars Povlsen .pin_config_config_dbg_show = pinconf_generic_dump_config, 1579f8a74760SLars Povlsen }; 1580f8a74760SLars Povlsen 1581ce8dc094SAlexandre Belloni static const struct pinctrl_ops ocelot_pctl_ops = { 1582ce8dc094SAlexandre Belloni .get_groups_count = ocelot_pctl_get_groups_count, 1583ce8dc094SAlexandre Belloni .get_group_name = ocelot_pctl_get_group_name, 1584ce8dc094SAlexandre Belloni .get_group_pins = ocelot_pctl_get_group_pins, 1585ce8dc094SAlexandre Belloni .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, 1586ce8dc094SAlexandre Belloni .dt_free_map = pinconf_generic_dt_free_map, 1587ce8dc094SAlexandre Belloni }; 1588ce8dc094SAlexandre Belloni 1589dc62db71SHoratiu Vultur static struct ocelot_match_data luton_desc = { 1590dc62db71SHoratiu Vultur .desc = { 15918f27440dSLars Povlsen .name = "luton-pinctrl", 15928f27440dSLars Povlsen .pins = luton_pins, 15938f27440dSLars Povlsen .npins = ARRAY_SIZE(luton_pins), 15948f27440dSLars Povlsen .pctlops = &ocelot_pctl_ops, 15958f27440dSLars Povlsen .pmxops = &ocelot_pmx_ops, 15968f27440dSLars Povlsen .owner = THIS_MODULE, 1597dc62db71SHoratiu Vultur }, 15988f27440dSLars Povlsen }; 15998f27440dSLars Povlsen 1600dc62db71SHoratiu Vultur static struct ocelot_match_data serval_desc = { 1601dc62db71SHoratiu Vultur .desc = { 16026e6347e2SLars Povlsen .name = "serval-pinctrl", 16036e6347e2SLars Povlsen .pins = serval_pins, 16046e6347e2SLars Povlsen .npins = ARRAY_SIZE(serval_pins), 16056e6347e2SLars Povlsen .pctlops = &ocelot_pctl_ops, 16066e6347e2SLars Povlsen .pmxops = &ocelot_pmx_ops, 16076e6347e2SLars Povlsen .owner = THIS_MODULE, 1608dc62db71SHoratiu Vultur }, 16096e6347e2SLars Povlsen }; 16106e6347e2SLars Povlsen 1611dc62db71SHoratiu Vultur static struct ocelot_match_data ocelot_desc = { 1612dc62db71SHoratiu Vultur .desc = { 1613ce8dc094SAlexandre Belloni .name = "ocelot-pinctrl", 1614ce8dc094SAlexandre Belloni .pins = ocelot_pins, 1615ce8dc094SAlexandre Belloni .npins = ARRAY_SIZE(ocelot_pins), 1616ce8dc094SAlexandre Belloni .pctlops = &ocelot_pctl_ops, 1617ce8dc094SAlexandre Belloni .pmxops = &ocelot_pmx_ops, 1618ce8dc094SAlexandre Belloni .owner = THIS_MODULE, 1619dc62db71SHoratiu Vultur }, 1620ce8dc094SAlexandre Belloni }; 1621ce8dc094SAlexandre Belloni 1622dc62db71SHoratiu Vultur static struct ocelot_match_data jaguar2_desc = { 1623dc62db71SHoratiu Vultur .desc = { 1624da801ab5SAlexandre Belloni .name = "jaguar2-pinctrl", 1625da801ab5SAlexandre Belloni .pins = jaguar2_pins, 1626da801ab5SAlexandre Belloni .npins = ARRAY_SIZE(jaguar2_pins), 1627da801ab5SAlexandre Belloni .pctlops = &ocelot_pctl_ops, 1628da801ab5SAlexandre Belloni .pmxops = &ocelot_pmx_ops, 1629da801ab5SAlexandre Belloni .owner = THIS_MODULE, 1630dc62db71SHoratiu Vultur }, 1631da801ab5SAlexandre Belloni }; 1632da801ab5SAlexandre Belloni 1633dc62db71SHoratiu Vultur static struct ocelot_match_data servalt_desc = { 1634dc62db71SHoratiu Vultur .desc = { 16358fc0bfcdSHoratiu Vultur .name = "servalt-pinctrl", 16368fc0bfcdSHoratiu Vultur .pins = servalt_pins, 16378fc0bfcdSHoratiu Vultur .npins = ARRAY_SIZE(servalt_pins), 16388fc0bfcdSHoratiu Vultur .pctlops = &ocelot_pctl_ops, 16398fc0bfcdSHoratiu Vultur .pmxops = &ocelot_pmx_ops, 16408fc0bfcdSHoratiu Vultur .owner = THIS_MODULE, 1641dc62db71SHoratiu Vultur }, 16428fc0bfcdSHoratiu Vultur }; 16438fc0bfcdSHoratiu Vultur 1644dc62db71SHoratiu Vultur static struct ocelot_match_data sparx5_desc = { 1645dc62db71SHoratiu Vultur .desc = { 1646f8a74760SLars Povlsen .name = "sparx5-pinctrl", 1647f8a74760SLars Povlsen .pins = sparx5_pins, 1648f8a74760SLars Povlsen .npins = ARRAY_SIZE(sparx5_pins), 1649f8a74760SLars Povlsen .pctlops = &ocelot_pctl_ops, 1650f8a74760SLars Povlsen .pmxops = &ocelot_pmx_ops, 1651f8a74760SLars Povlsen .confops = &ocelot_confops, 1652f8a74760SLars Povlsen .owner = THIS_MODULE, 1653dc62db71SHoratiu Vultur }, 1654dc62db71SHoratiu Vultur .pincfg_data = { 1655dc62db71SHoratiu Vultur .pd_bit = BIT(4), 1656dc62db71SHoratiu Vultur .pu_bit = BIT(3), 1657dc62db71SHoratiu Vultur .drive_bits = GENMASK(1, 0), 1658dc62db71SHoratiu Vultur .schmitt_bit = BIT(2), 1659dc62db71SHoratiu Vultur }, 1660f8a74760SLars Povlsen }; 1661f8a74760SLars Povlsen 1662dc62db71SHoratiu Vultur static struct ocelot_match_data lan966x_desc = { 1663dc62db71SHoratiu Vultur .desc = { 1664531d6ab3SKavyasree Kotagiri .name = "lan966x-pinctrl", 1665531d6ab3SKavyasree Kotagiri .pins = lan966x_pins, 1666531d6ab3SKavyasree Kotagiri .npins = ARRAY_SIZE(lan966x_pins), 1667531d6ab3SKavyasree Kotagiri .pctlops = &ocelot_pctl_ops, 1668531d6ab3SKavyasree Kotagiri .pmxops = &lan966x_pmx_ops, 1669531d6ab3SKavyasree Kotagiri .confops = &ocelot_confops, 1670531d6ab3SKavyasree Kotagiri .owner = THIS_MODULE, 1671dc62db71SHoratiu Vultur }, 1672dc62db71SHoratiu Vultur .pincfg_data = { 1673dc62db71SHoratiu Vultur .pd_bit = BIT(3), 1674dc62db71SHoratiu Vultur .pu_bit = BIT(2), 1675dc62db71SHoratiu Vultur .drive_bits = GENMASK(1, 0), 1676dc62db71SHoratiu Vultur }, 1677531d6ab3SKavyasree Kotagiri }; 1678531d6ab3SKavyasree Kotagiri 1679ce8dc094SAlexandre Belloni static int ocelot_create_group_func_map(struct device *dev, 1680ce8dc094SAlexandre Belloni struct ocelot_pinctrl *info) 1681ce8dc094SAlexandre Belloni { 1682ce8dc094SAlexandre Belloni int f, npins, i; 1683da801ab5SAlexandre Belloni u8 *pins = kcalloc(info->desc->npins, sizeof(u8), GFP_KERNEL); 1684da801ab5SAlexandre Belloni 1685da801ab5SAlexandre Belloni if (!pins) 1686da801ab5SAlexandre Belloni return -ENOMEM; 1687ce8dc094SAlexandre Belloni 1688ce8dc094SAlexandre Belloni for (f = 0; f < FUNC_MAX; f++) { 1689da801ab5SAlexandre Belloni for (npins = 0, i = 0; i < info->desc->npins; i++) { 1690da801ab5SAlexandre Belloni if (ocelot_pin_function_idx(info, i, f) >= 0) 1691ce8dc094SAlexandre Belloni pins[npins++] = i; 1692ce8dc094SAlexandre Belloni } 1693ce8dc094SAlexandre Belloni 1694da801ab5SAlexandre Belloni if (!npins) 1695da801ab5SAlexandre Belloni continue; 1696da801ab5SAlexandre Belloni 1697ce8dc094SAlexandre Belloni info->func[f].ngroups = npins; 1698da801ab5SAlexandre Belloni info->func[f].groups = devm_kcalloc(dev, npins, sizeof(char *), 1699ce8dc094SAlexandre Belloni GFP_KERNEL); 1700da801ab5SAlexandre Belloni if (!info->func[f].groups) { 1701da801ab5SAlexandre Belloni kfree(pins); 1702ce8dc094SAlexandre Belloni return -ENOMEM; 1703da801ab5SAlexandre Belloni } 1704ce8dc094SAlexandre Belloni 1705ce8dc094SAlexandre Belloni for (i = 0; i < npins; i++) 1706f8a74760SLars Povlsen info->func[f].groups[i] = 1707f8a74760SLars Povlsen info->desc->pins[pins[i]].name; 1708ce8dc094SAlexandre Belloni } 1709ce8dc094SAlexandre Belloni 1710da801ab5SAlexandre Belloni kfree(pins); 1711da801ab5SAlexandre Belloni 1712ce8dc094SAlexandre Belloni return 0; 1713ce8dc094SAlexandre Belloni } 1714ce8dc094SAlexandre Belloni 1715ce8dc094SAlexandre Belloni static int ocelot_pinctrl_register(struct platform_device *pdev, 1716ce8dc094SAlexandre Belloni struct ocelot_pinctrl *info) 1717ce8dc094SAlexandre Belloni { 1718ce8dc094SAlexandre Belloni int ret; 1719ce8dc094SAlexandre Belloni 1720ce8dc094SAlexandre Belloni ret = ocelot_create_group_func_map(&pdev->dev, info); 1721ce8dc094SAlexandre Belloni if (ret) { 1722ce8dc094SAlexandre Belloni dev_err(&pdev->dev, "Unable to create group func map.\n"); 1723ce8dc094SAlexandre Belloni return ret; 1724ce8dc094SAlexandre Belloni } 1725ce8dc094SAlexandre Belloni 1726da801ab5SAlexandre Belloni info->pctl = devm_pinctrl_register(&pdev->dev, info->desc, info); 1727ce8dc094SAlexandre Belloni if (IS_ERR(info->pctl)) { 1728ce8dc094SAlexandre Belloni dev_err(&pdev->dev, "Failed to register pinctrl\n"); 1729ce8dc094SAlexandre Belloni return PTR_ERR(info->pctl); 1730ce8dc094SAlexandre Belloni } 1731ce8dc094SAlexandre Belloni 1732ce8dc094SAlexandre Belloni return 0; 1733ce8dc094SAlexandre Belloni } 1734ce8dc094SAlexandre Belloni 1735ce8dc094SAlexandre Belloni static int ocelot_gpio_get(struct gpio_chip *chip, unsigned int offset) 1736ce8dc094SAlexandre Belloni { 1737ce8dc094SAlexandre Belloni struct ocelot_pinctrl *info = gpiochip_get_data(chip); 1738ce8dc094SAlexandre Belloni unsigned int val; 1739ce8dc094SAlexandre Belloni 1740da801ab5SAlexandre Belloni regmap_read(info->map, REG(OCELOT_GPIO_IN, info, offset), &val); 1741ce8dc094SAlexandre Belloni 1742da801ab5SAlexandre Belloni return !!(val & BIT(offset % 32)); 1743ce8dc094SAlexandre Belloni } 1744ce8dc094SAlexandre Belloni 1745ce8dc094SAlexandre Belloni static void ocelot_gpio_set(struct gpio_chip *chip, unsigned int offset, 1746ce8dc094SAlexandre Belloni int value) 1747ce8dc094SAlexandre Belloni { 1748ce8dc094SAlexandre Belloni struct ocelot_pinctrl *info = gpiochip_get_data(chip); 1749ce8dc094SAlexandre Belloni 1750ce8dc094SAlexandre Belloni if (value) 1751da801ab5SAlexandre Belloni regmap_write(info->map, REG(OCELOT_GPIO_OUT_SET, info, offset), 1752da801ab5SAlexandre Belloni BIT(offset % 32)); 1753ce8dc094SAlexandre Belloni else 1754da801ab5SAlexandre Belloni regmap_write(info->map, REG(OCELOT_GPIO_OUT_CLR, info, offset), 1755da801ab5SAlexandre Belloni BIT(offset % 32)); 1756ce8dc094SAlexandre Belloni } 1757ce8dc094SAlexandre Belloni 1758ce8dc094SAlexandre Belloni static int ocelot_gpio_get_direction(struct gpio_chip *chip, 1759ce8dc094SAlexandre Belloni unsigned int offset) 1760ce8dc094SAlexandre Belloni { 1761ce8dc094SAlexandre Belloni struct ocelot_pinctrl *info = gpiochip_get_data(chip); 1762ce8dc094SAlexandre Belloni unsigned int val; 1763ce8dc094SAlexandre Belloni 1764da801ab5SAlexandre Belloni regmap_read(info->map, REG(OCELOT_GPIO_OE, info, offset), &val); 1765ce8dc094SAlexandre Belloni 17663c827873SMatti Vaittinen if (val & BIT(offset % 32)) 17673c827873SMatti Vaittinen return GPIO_LINE_DIRECTION_OUT; 17683c827873SMatti Vaittinen 17693c827873SMatti Vaittinen return GPIO_LINE_DIRECTION_IN; 1770ce8dc094SAlexandre Belloni } 1771ce8dc094SAlexandre Belloni 1772ce8dc094SAlexandre Belloni static int ocelot_gpio_direction_input(struct gpio_chip *chip, 1773ce8dc094SAlexandre Belloni unsigned int offset) 1774ce8dc094SAlexandre Belloni { 1775ce8dc094SAlexandre Belloni return pinctrl_gpio_direction_input(chip->base + offset); 1776ce8dc094SAlexandre Belloni } 1777ce8dc094SAlexandre Belloni 1778ce8dc094SAlexandre Belloni static int ocelot_gpio_direction_output(struct gpio_chip *chip, 1779ce8dc094SAlexandre Belloni unsigned int offset, int value) 1780ce8dc094SAlexandre Belloni { 1781ce8dc094SAlexandre Belloni struct ocelot_pinctrl *info = gpiochip_get_data(chip); 1782da801ab5SAlexandre Belloni unsigned int pin = BIT(offset % 32); 1783ce8dc094SAlexandre Belloni 1784ce8dc094SAlexandre Belloni if (value) 1785da801ab5SAlexandre Belloni regmap_write(info->map, REG(OCELOT_GPIO_OUT_SET, info, offset), 1786da801ab5SAlexandre Belloni pin); 1787ce8dc094SAlexandre Belloni else 1788da801ab5SAlexandre Belloni regmap_write(info->map, REG(OCELOT_GPIO_OUT_CLR, info, offset), 1789da801ab5SAlexandre Belloni pin); 1790ce8dc094SAlexandre Belloni 1791ce8dc094SAlexandre Belloni return pinctrl_gpio_direction_output(chip->base + offset); 1792ce8dc094SAlexandre Belloni } 1793ce8dc094SAlexandre Belloni 1794ce8dc094SAlexandre Belloni static const struct gpio_chip ocelot_gpiolib_chip = { 1795ce8dc094SAlexandre Belloni .request = gpiochip_generic_request, 1796ce8dc094SAlexandre Belloni .free = gpiochip_generic_free, 1797ce8dc094SAlexandre Belloni .set = ocelot_gpio_set, 1798ce8dc094SAlexandre Belloni .get = ocelot_gpio_get, 1799ce8dc094SAlexandre Belloni .get_direction = ocelot_gpio_get_direction, 1800ce8dc094SAlexandre Belloni .direction_input = ocelot_gpio_direction_input, 1801ce8dc094SAlexandre Belloni .direction_output = ocelot_gpio_direction_output, 1802ce8dc094SAlexandre Belloni .owner = THIS_MODULE, 1803ce8dc094SAlexandre Belloni }; 1804ce8dc094SAlexandre Belloni 1805be36abb7SQuentin Schulz static void ocelot_irq_mask(struct irq_data *data) 1806be36abb7SQuentin Schulz { 1807be36abb7SQuentin Schulz struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 1808be36abb7SQuentin Schulz struct ocelot_pinctrl *info = gpiochip_get_data(chip); 1809be36abb7SQuentin Schulz unsigned int gpio = irqd_to_hwirq(data); 1810be36abb7SQuentin Schulz 1811da801ab5SAlexandre Belloni regmap_update_bits(info->map, REG(OCELOT_GPIO_INTR_ENA, info, gpio), 1812da801ab5SAlexandre Belloni BIT(gpio % 32), 0); 1813be36abb7SQuentin Schulz } 1814be36abb7SQuentin Schulz 1815be36abb7SQuentin Schulz static void ocelot_irq_unmask(struct irq_data *data) 1816be36abb7SQuentin Schulz { 1817be36abb7SQuentin Schulz struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 1818be36abb7SQuentin Schulz struct ocelot_pinctrl *info = gpiochip_get_data(chip); 1819be36abb7SQuentin Schulz unsigned int gpio = irqd_to_hwirq(data); 1820be36abb7SQuentin Schulz 1821da801ab5SAlexandre Belloni regmap_update_bits(info->map, REG(OCELOT_GPIO_INTR_ENA, info, gpio), 1822da801ab5SAlexandre Belloni BIT(gpio % 32), BIT(gpio % 32)); 1823be36abb7SQuentin Schulz } 1824be36abb7SQuentin Schulz 1825be36abb7SQuentin Schulz static void ocelot_irq_ack(struct irq_data *data) 1826be36abb7SQuentin Schulz { 1827be36abb7SQuentin Schulz struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 1828be36abb7SQuentin Schulz struct ocelot_pinctrl *info = gpiochip_get_data(chip); 1829be36abb7SQuentin Schulz unsigned int gpio = irqd_to_hwirq(data); 1830be36abb7SQuentin Schulz 1831da801ab5SAlexandre Belloni regmap_write_bits(info->map, REG(OCELOT_GPIO_INTR, info, gpio), 1832da801ab5SAlexandre Belloni BIT(gpio % 32), BIT(gpio % 32)); 1833be36abb7SQuentin Schulz } 1834be36abb7SQuentin Schulz 1835be36abb7SQuentin Schulz static int ocelot_irq_set_type(struct irq_data *data, unsigned int type); 1836be36abb7SQuentin Schulz 1837be36abb7SQuentin Schulz static struct irq_chip ocelot_eoi_irqchip = { 1838be36abb7SQuentin Schulz .name = "gpio", 1839be36abb7SQuentin Schulz .irq_mask = ocelot_irq_mask, 1840be36abb7SQuentin Schulz .irq_eoi = ocelot_irq_ack, 1841be36abb7SQuentin Schulz .irq_unmask = ocelot_irq_unmask, 1842be36abb7SQuentin Schulz .flags = IRQCHIP_EOI_THREADED | IRQCHIP_EOI_IF_HANDLED, 1843be36abb7SQuentin Schulz .irq_set_type = ocelot_irq_set_type, 1844be36abb7SQuentin Schulz }; 1845be36abb7SQuentin Schulz 1846be36abb7SQuentin Schulz static struct irq_chip ocelot_irqchip = { 1847be36abb7SQuentin Schulz .name = "gpio", 1848be36abb7SQuentin Schulz .irq_mask = ocelot_irq_mask, 1849be36abb7SQuentin Schulz .irq_ack = ocelot_irq_ack, 1850be36abb7SQuentin Schulz .irq_unmask = ocelot_irq_unmask, 1851be36abb7SQuentin Schulz .irq_set_type = ocelot_irq_set_type, 1852be36abb7SQuentin Schulz }; 1853be36abb7SQuentin Schulz 1854be36abb7SQuentin Schulz static int ocelot_irq_set_type(struct irq_data *data, unsigned int type) 1855be36abb7SQuentin Schulz { 1856be36abb7SQuentin Schulz type &= IRQ_TYPE_SENSE_MASK; 1857be36abb7SQuentin Schulz 1858be36abb7SQuentin Schulz if (!(type & (IRQ_TYPE_EDGE_BOTH | IRQ_TYPE_LEVEL_HIGH))) 1859be36abb7SQuentin Schulz return -EINVAL; 1860be36abb7SQuentin Schulz 1861be36abb7SQuentin Schulz if (type & IRQ_TYPE_LEVEL_HIGH) 1862be36abb7SQuentin Schulz irq_set_chip_handler_name_locked(data, &ocelot_eoi_irqchip, 1863be36abb7SQuentin Schulz handle_fasteoi_irq, NULL); 1864be36abb7SQuentin Schulz if (type & IRQ_TYPE_EDGE_BOTH) 1865be36abb7SQuentin Schulz irq_set_chip_handler_name_locked(data, &ocelot_irqchip, 1866be36abb7SQuentin Schulz handle_edge_irq, NULL); 1867be36abb7SQuentin Schulz 1868be36abb7SQuentin Schulz return 0; 1869be36abb7SQuentin Schulz } 1870be36abb7SQuentin Schulz 1871be36abb7SQuentin Schulz static void ocelot_irq_handler(struct irq_desc *desc) 1872be36abb7SQuentin Schulz { 1873be36abb7SQuentin Schulz struct irq_chip *parent_chip = irq_desc_get_chip(desc); 1874be36abb7SQuentin Schulz struct gpio_chip *chip = irq_desc_get_handler_data(desc); 1875be36abb7SQuentin Schulz struct ocelot_pinctrl *info = gpiochip_get_data(chip); 18760b47afc6SLars Povlsen unsigned int id_reg = OCELOT_GPIO_INTR_IDENT * info->stride; 1877da801ab5SAlexandre Belloni unsigned int reg = 0, irq, i; 1878be36abb7SQuentin Schulz unsigned long irqs; 1879be36abb7SQuentin Schulz 1880da801ab5SAlexandre Belloni for (i = 0; i < info->stride; i++) { 18810b47afc6SLars Povlsen regmap_read(info->map, id_reg + 4 * i, ®); 1882be36abb7SQuentin Schulz if (!reg) 1883da801ab5SAlexandre Belloni continue; 1884be36abb7SQuentin Schulz 1885be36abb7SQuentin Schulz chained_irq_enter(parent_chip, desc); 1886be36abb7SQuentin Schulz 1887be36abb7SQuentin Schulz irqs = reg; 1888be36abb7SQuentin Schulz 1889da801ab5SAlexandre Belloni for_each_set_bit(irq, &irqs, 1890da801ab5SAlexandre Belloni min(32U, info->desc->npins - 32 * i)) 1891a9cb09b7SMarc Zyngier generic_handle_domain_irq(chip->irq.domain, irq + 32 * i); 1892be36abb7SQuentin Schulz 1893be36abb7SQuentin Schulz chained_irq_exit(parent_chip, desc); 1894be36abb7SQuentin Schulz } 1895da801ab5SAlexandre Belloni } 1896be36abb7SQuentin Schulz 1897ce8dc094SAlexandre Belloni static int ocelot_gpiochip_register(struct platform_device *pdev, 1898ce8dc094SAlexandre Belloni struct ocelot_pinctrl *info) 1899ce8dc094SAlexandre Belloni { 1900ce8dc094SAlexandre Belloni struct gpio_chip *gc; 1901d874becaSLinus Walleij struct gpio_irq_chip *girq; 190217f2c8d3SQinglang Miao int irq; 1903ce8dc094SAlexandre Belloni 1904ce8dc094SAlexandre Belloni info->gpio_chip = ocelot_gpiolib_chip; 1905ce8dc094SAlexandre Belloni 1906ce8dc094SAlexandre Belloni gc = &info->gpio_chip; 1907da801ab5SAlexandre Belloni gc->ngpio = info->desc->npins; 1908ce8dc094SAlexandre Belloni gc->parent = &pdev->dev; 1909a159c2b4SColin Foster gc->base = -1; 1910ce8dc094SAlexandre Belloni gc->label = "ocelot-gpio"; 1911ce8dc094SAlexandre Belloni 1912d1f2c82fSHoratiu Vultur irq = platform_get_irq_optional(pdev, 0); 1913d1f2c82fSHoratiu Vultur if (irq > 0) { 1914d874becaSLinus Walleij girq = &gc->irq; 1915d874becaSLinus Walleij girq->chip = &ocelot_irqchip; 1916d874becaSLinus Walleij girq->parent_handler = ocelot_irq_handler; 1917d874becaSLinus Walleij girq->num_parents = 1; 1918550713e3SLars Povlsen girq->parents = devm_kcalloc(&pdev->dev, 1, 1919550713e3SLars Povlsen sizeof(*girq->parents), 1920d874becaSLinus Walleij GFP_KERNEL); 1921d874becaSLinus Walleij if (!girq->parents) 1922d874becaSLinus Walleij return -ENOMEM; 1923d874becaSLinus Walleij girq->parents[0] = irq; 1924d874becaSLinus Walleij girq->default_type = IRQ_TYPE_NONE; 1925d874becaSLinus Walleij girq->handler = handle_edge_irq; 1926550713e3SLars Povlsen } 1927d874becaSLinus Walleij 192817f2c8d3SQinglang Miao return devm_gpiochip_add_data(&pdev->dev, gc, info); 1929ce8dc094SAlexandre Belloni } 1930ce8dc094SAlexandre Belloni 1931ce8dc094SAlexandre Belloni static const struct of_device_id ocelot_pinctrl_of_match[] = { 19328f27440dSLars Povlsen { .compatible = "mscc,luton-pinctrl", .data = &luton_desc }, 19336e6347e2SLars Povlsen { .compatible = "mscc,serval-pinctrl", .data = &serval_desc }, 1934da801ab5SAlexandre Belloni { .compatible = "mscc,ocelot-pinctrl", .data = &ocelot_desc }, 1935da801ab5SAlexandre Belloni { .compatible = "mscc,jaguar2-pinctrl", .data = &jaguar2_desc }, 19368fc0bfcdSHoratiu Vultur { .compatible = "mscc,servalt-pinctrl", .data = &servalt_desc }, 1937f8a74760SLars Povlsen { .compatible = "microchip,sparx5-pinctrl", .data = &sparx5_desc }, 1938531d6ab3SKavyasree Kotagiri { .compatible = "microchip,lan966x-pinctrl", .data = &lan966x_desc }, 1939ce8dc094SAlexandre Belloni {}, 1940ce8dc094SAlexandre Belloni }; 1941ce8dc094SAlexandre Belloni 1942*ba9c4745SHoratiu Vultur static struct regmap *ocelot_pinctrl_create_pincfg(struct platform_device *pdev, 1943*ba9c4745SHoratiu Vultur const struct ocelot_pinctrl *info) 1944076d9e71SColin Foster { 1945076d9e71SColin Foster void __iomem *base; 1946076d9e71SColin Foster 1947076d9e71SColin Foster const struct regmap_config regmap_config = { 1948076d9e71SColin Foster .reg_bits = 32, 1949076d9e71SColin Foster .val_bits = 32, 1950076d9e71SColin Foster .reg_stride = 4, 1951*ba9c4745SHoratiu Vultur .max_register = info->desc->npins * 4, 1952359afd90SMichael Walle .name = "pincfg", 1953076d9e71SColin Foster }; 1954076d9e71SColin Foster 195594ef3297SMichael Walle base = devm_platform_ioremap_resource(pdev, 1); 1956076d9e71SColin Foster if (IS_ERR(base)) { 1957076d9e71SColin Foster dev_dbg(&pdev->dev, "Failed to ioremap config registers (no extended pinconf)\n"); 1958076d9e71SColin Foster return NULL; 1959076d9e71SColin Foster } 1960076d9e71SColin Foster 1961076d9e71SColin Foster return devm_regmap_init_mmio(&pdev->dev, base, ®map_config); 1962076d9e71SColin Foster } 1963076d9e71SColin Foster 1964ce3e7f0eSColin Ian King static int ocelot_pinctrl_probe(struct platform_device *pdev) 1965ce8dc094SAlexandre Belloni { 1966dc62db71SHoratiu Vultur const struct ocelot_match_data *data; 1967ce8dc094SAlexandre Belloni struct device *dev = &pdev->dev; 1968ce8dc094SAlexandre Belloni struct ocelot_pinctrl *info; 1969453200afSMichael Walle struct reset_control *reset; 1970076d9e71SColin Foster struct regmap *pincfg; 1971ce8dc094SAlexandre Belloni void __iomem *base; 1972ce8dc094SAlexandre Belloni int ret; 1973da801ab5SAlexandre Belloni struct regmap_config regmap_config = { 1974da801ab5SAlexandre Belloni .reg_bits = 32, 1975da801ab5SAlexandre Belloni .val_bits = 32, 1976da801ab5SAlexandre Belloni .reg_stride = 4, 1977da801ab5SAlexandre Belloni }; 1978ce8dc094SAlexandre Belloni 1979ce8dc094SAlexandre Belloni info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL); 1980ce8dc094SAlexandre Belloni if (!info) 1981ce8dc094SAlexandre Belloni return -ENOMEM; 1982ce8dc094SAlexandre Belloni 1983dc62db71SHoratiu Vultur data = device_get_match_data(dev); 1984dc62db71SHoratiu Vultur if (!data) 1985dc62db71SHoratiu Vultur return -EINVAL; 1986dc62db71SHoratiu Vultur 1987dc62db71SHoratiu Vultur info->desc = devm_kmemdup(dev, &data->desc, sizeof(*info->desc), 1988dc62db71SHoratiu Vultur GFP_KERNEL); 1989dc62db71SHoratiu Vultur if (!info->desc) 1990dc62db71SHoratiu Vultur return -ENOMEM; 1991dc62db71SHoratiu Vultur 1992dc62db71SHoratiu Vultur info->pincfg_data = &data->pincfg_data; 1993da801ab5SAlexandre Belloni 1994453200afSMichael Walle reset = devm_reset_control_get_optional_shared(dev, "switch"); 1995453200afSMichael Walle if (IS_ERR(reset)) 1996453200afSMichael Walle return dev_err_probe(dev, PTR_ERR(reset), 1997453200afSMichael Walle "Failed to get reset\n"); 1998453200afSMichael Walle reset_control_reset(reset); 1999453200afSMichael Walle 2000ce8dc094SAlexandre Belloni base = devm_ioremap_resource(dev, 2001ce8dc094SAlexandre Belloni platform_get_resource(pdev, IORESOURCE_MEM, 0)); 20020f9facdbSZhen Lei if (IS_ERR(base)) 2003ce8dc094SAlexandre Belloni return PTR_ERR(base); 2004ce8dc094SAlexandre Belloni 2005da801ab5SAlexandre Belloni info->stride = 1 + (info->desc->npins - 1) / 32; 2006f8a74760SLars Povlsen 2007da801ab5SAlexandre Belloni regmap_config.max_register = OCELOT_GPIO_SD_MAP * info->stride + 15 * 4; 2008da801ab5SAlexandre Belloni 2009da801ab5SAlexandre Belloni info->map = devm_regmap_init_mmio(dev, base, ®map_config); 2010ce8dc094SAlexandre Belloni if (IS_ERR(info->map)) { 2011ce8dc094SAlexandre Belloni dev_err(dev, "Failed to create regmap\n"); 2012ce8dc094SAlexandre Belloni return PTR_ERR(info->map); 2013ce8dc094SAlexandre Belloni } 2014ce8dc094SAlexandre Belloni dev_set_drvdata(dev, info->map); 2015ce8dc094SAlexandre Belloni info->dev = dev; 2016ce8dc094SAlexandre Belloni 2017f8a74760SLars Povlsen /* Pinconf registers */ 2018f8a74760SLars Povlsen if (info->desc->confops) { 2019*ba9c4745SHoratiu Vultur pincfg = ocelot_pinctrl_create_pincfg(pdev, info); 2020076d9e71SColin Foster if (IS_ERR(pincfg)) 2021076d9e71SColin Foster dev_dbg(dev, "Failed to create pincfg regmap\n"); 2022f8a74760SLars Povlsen else 2023076d9e71SColin Foster info->pincfg = pincfg; 2024f8a74760SLars Povlsen } 2025f8a74760SLars Povlsen 2026ce8dc094SAlexandre Belloni ret = ocelot_pinctrl_register(pdev, info); 2027ce8dc094SAlexandre Belloni if (ret) 2028ce8dc094SAlexandre Belloni return ret; 2029ce8dc094SAlexandre Belloni 2030ce8dc094SAlexandre Belloni ret = ocelot_gpiochip_register(pdev, info); 2031ce8dc094SAlexandre Belloni if (ret) 2032ce8dc094SAlexandre Belloni return ret; 2033ce8dc094SAlexandre Belloni 2034f8a74760SLars Povlsen dev_info(dev, "driver registered\n"); 2035f8a74760SLars Povlsen 2036ce8dc094SAlexandre Belloni return 0; 2037ce8dc094SAlexandre Belloni } 2038ce8dc094SAlexandre Belloni 2039ce8dc094SAlexandre Belloni static struct platform_driver ocelot_pinctrl_driver = { 2040ce8dc094SAlexandre Belloni .driver = { 2041ce8dc094SAlexandre Belloni .name = "pinctrl-ocelot", 2042ce8dc094SAlexandre Belloni .of_match_table = of_match_ptr(ocelot_pinctrl_of_match), 2043ce8dc094SAlexandre Belloni .suppress_bind_attrs = true, 2044ce8dc094SAlexandre Belloni }, 2045ce8dc094SAlexandre Belloni .probe = ocelot_pinctrl_probe, 2046ce8dc094SAlexandre Belloni }; 2047ce8dc094SAlexandre Belloni builtin_platform_driver(ocelot_pinctrl_driver); 2048