1ce8dc094SAlexandre Belloni // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2ce8dc094SAlexandre Belloni /* 3ce8dc094SAlexandre Belloni * Microsemi SoCs pinctrl driver 4ce8dc094SAlexandre Belloni * 5ce8dc094SAlexandre Belloni * Author: <alexandre.belloni@free-electrons.com> 6ce8dc094SAlexandre Belloni * License: Dual MIT/GPL 7ce8dc094SAlexandre Belloni * Copyright (c) 2017 Microsemi Corporation 8ce8dc094SAlexandre Belloni */ 9ce8dc094SAlexandre Belloni 10ce8dc094SAlexandre Belloni #include <linux/gpio/driver.h> 11ce8dc094SAlexandre Belloni #include <linux/interrupt.h> 12ce8dc094SAlexandre Belloni #include <linux/io.h> 13ce8dc094SAlexandre Belloni #include <linux/of_device.h> 14be36abb7SQuentin Schulz #include <linux/of_irq.h> 15ce8dc094SAlexandre Belloni #include <linux/of_platform.h> 16ce8dc094SAlexandre Belloni #include <linux/pinctrl/pinctrl.h> 17ce8dc094SAlexandre Belloni #include <linux/pinctrl/pinmux.h> 18ce8dc094SAlexandre Belloni #include <linux/pinctrl/pinconf.h> 19ce8dc094SAlexandre Belloni #include <linux/pinctrl/pinconf-generic.h> 20ce8dc094SAlexandre Belloni #include <linux/platform_device.h> 21ce8dc094SAlexandre Belloni #include <linux/regmap.h> 22ce8dc094SAlexandre Belloni #include <linux/slab.h> 23ce8dc094SAlexandre Belloni 24ce8dc094SAlexandre Belloni #include "core.h" 25ce8dc094SAlexandre Belloni #include "pinconf.h" 26ce8dc094SAlexandre Belloni #include "pinmux.h" 27ce8dc094SAlexandre Belloni 28f8a74760SLars Povlsen #define ocelot_clrsetbits(addr, clear, set) \ 29f8a74760SLars Povlsen writel((readl(addr) & ~(clear)) | (set), (addr)) 30f8a74760SLars Povlsen 31f8a74760SLars Povlsen /* PINCONFIG bits (sparx5 only) */ 32f8a74760SLars Povlsen enum { 33f8a74760SLars Povlsen PINCONF_BIAS, 34f8a74760SLars Povlsen PINCONF_SCHMITT, 35f8a74760SLars Povlsen PINCONF_DRIVE_STRENGTH, 36f8a74760SLars Povlsen }; 37f8a74760SLars Povlsen 38f8a74760SLars Povlsen #define BIAS_PD_BIT BIT(4) 39f8a74760SLars Povlsen #define BIAS_PU_BIT BIT(3) 40f8a74760SLars Povlsen #define BIAS_BITS (BIAS_PD_BIT|BIAS_PU_BIT) 41f8a74760SLars Povlsen #define SCHMITT_BIT BIT(2) 42f8a74760SLars Povlsen #define DRIVE_BITS GENMASK(1, 0) 43f8a74760SLars Povlsen 44f8a74760SLars Povlsen /* GPIO standard registers */ 45ce8dc094SAlexandre Belloni #define OCELOT_GPIO_OUT_SET 0x0 46ce8dc094SAlexandre Belloni #define OCELOT_GPIO_OUT_CLR 0x4 47ce8dc094SAlexandre Belloni #define OCELOT_GPIO_OUT 0x8 48ce8dc094SAlexandre Belloni #define OCELOT_GPIO_IN 0xc 49ce8dc094SAlexandre Belloni #define OCELOT_GPIO_OE 0x10 50ce8dc094SAlexandre Belloni #define OCELOT_GPIO_INTR 0x14 51ce8dc094SAlexandre Belloni #define OCELOT_GPIO_INTR_ENA 0x18 52ce8dc094SAlexandre Belloni #define OCELOT_GPIO_INTR_IDENT 0x1c 53ce8dc094SAlexandre Belloni #define OCELOT_GPIO_ALT0 0x20 54ce8dc094SAlexandre Belloni #define OCELOT_GPIO_ALT1 0x24 55ce8dc094SAlexandre Belloni #define OCELOT_GPIO_SD_MAP 0x28 56ce8dc094SAlexandre Belloni 57ce8dc094SAlexandre Belloni #define OCELOT_FUNC_PER_PIN 4 58ce8dc094SAlexandre Belloni 59ce8dc094SAlexandre Belloni enum { 60*531d6ab3SKavyasree Kotagiri FUNC_CAN0_a, 61*531d6ab3SKavyasree Kotagiri FUNC_CAN0_b, 62*531d6ab3SKavyasree Kotagiri FUNC_CAN1, 63ce8dc094SAlexandre Belloni FUNC_NONE, 64*531d6ab3SKavyasree Kotagiri FUNC_FC0_a, 65*531d6ab3SKavyasree Kotagiri FUNC_FC0_b, 66*531d6ab3SKavyasree Kotagiri FUNC_FC0_c, 67*531d6ab3SKavyasree Kotagiri FUNC_FC1_a, 68*531d6ab3SKavyasree Kotagiri FUNC_FC1_b, 69*531d6ab3SKavyasree Kotagiri FUNC_FC1_c, 70*531d6ab3SKavyasree Kotagiri FUNC_FC2_a, 71*531d6ab3SKavyasree Kotagiri FUNC_FC2_b, 72*531d6ab3SKavyasree Kotagiri FUNC_FC3_a, 73*531d6ab3SKavyasree Kotagiri FUNC_FC3_b, 74*531d6ab3SKavyasree Kotagiri FUNC_FC3_c, 75*531d6ab3SKavyasree Kotagiri FUNC_FC4_a, 76*531d6ab3SKavyasree Kotagiri FUNC_FC4_b, 77*531d6ab3SKavyasree Kotagiri FUNC_FC4_c, 78*531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD0, 79*531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD1, 80*531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD2, 81*531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD3, 82*531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD4, 83*531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD5, 84*531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD6, 85*531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD7, 86*531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD8, 87*531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD9, 88*531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD10, 89*531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD11, 90*531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD12, 91*531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD13, 92*531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD14, 93*531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD15, 94*531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD16, 95*531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD17, 96*531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD18, 97*531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD19, 98*531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD20, 99ce8dc094SAlexandre Belloni FUNC_GPIO, 100*531d6ab3SKavyasree Kotagiri FUNC_IB_TRG_a, 101*531d6ab3SKavyasree Kotagiri FUNC_IB_TRG_b, 102*531d6ab3SKavyasree Kotagiri FUNC_IB_TRG_c, 103f8a74760SLars Povlsen FUNC_IRQ0, 104*531d6ab3SKavyasree Kotagiri FUNC_IRQ_IN_a, 105*531d6ab3SKavyasree Kotagiri FUNC_IRQ_IN_b, 106*531d6ab3SKavyasree Kotagiri FUNC_IRQ_IN_c, 107ce8dc094SAlexandre Belloni FUNC_IRQ0_IN, 108*531d6ab3SKavyasree Kotagiri FUNC_IRQ_OUT_a, 109*531d6ab3SKavyasree Kotagiri FUNC_IRQ_OUT_b, 110*531d6ab3SKavyasree Kotagiri FUNC_IRQ_OUT_c, 111ce8dc094SAlexandre Belloni FUNC_IRQ0_OUT, 112f8a74760SLars Povlsen FUNC_IRQ1, 113ce8dc094SAlexandre Belloni FUNC_IRQ1_IN, 114ce8dc094SAlexandre Belloni FUNC_IRQ1_OUT, 115f8a74760SLars Povlsen FUNC_EXT_IRQ, 116edc72546SLars Povlsen FUNC_MIIM, 117*531d6ab3SKavyasree Kotagiri FUNC_MIIM_a, 118*531d6ab3SKavyasree Kotagiri FUNC_MIIM_b, 119*531d6ab3SKavyasree Kotagiri FUNC_MIIM_c, 120*531d6ab3SKavyasree Kotagiri FUNC_MIIM_Sa, 121*531d6ab3SKavyasree Kotagiri FUNC_MIIM_Sb, 122*531d6ab3SKavyasree Kotagiri FUNC_OB_TRG, 123*531d6ab3SKavyasree Kotagiri FUNC_OB_TRG_a, 124*531d6ab3SKavyasree Kotagiri FUNC_OB_TRG_b, 125f8a74760SLars Povlsen FUNC_PHY_LED, 126ce8dc094SAlexandre Belloni FUNC_PCI_WAKE, 127f8a74760SLars Povlsen FUNC_MD, 128ce8dc094SAlexandre Belloni FUNC_PTP0, 129ce8dc094SAlexandre Belloni FUNC_PTP1, 130ce8dc094SAlexandre Belloni FUNC_PTP2, 131ce8dc094SAlexandre Belloni FUNC_PTP3, 132*531d6ab3SKavyasree Kotagiri FUNC_PTPSYNC_1, 133*531d6ab3SKavyasree Kotagiri FUNC_PTPSYNC_2, 134*531d6ab3SKavyasree Kotagiri FUNC_PTPSYNC_3, 135*531d6ab3SKavyasree Kotagiri FUNC_PTPSYNC_4, 136*531d6ab3SKavyasree Kotagiri FUNC_PTPSYNC_5, 137*531d6ab3SKavyasree Kotagiri FUNC_PTPSYNC_6, 138*531d6ab3SKavyasree Kotagiri FUNC_PTPSYNC_7, 139ce8dc094SAlexandre Belloni FUNC_PWM, 140*531d6ab3SKavyasree Kotagiri FUNC_QSPI1, 141*531d6ab3SKavyasree Kotagiri FUNC_QSPI2, 142*531d6ab3SKavyasree Kotagiri FUNC_R, 143*531d6ab3SKavyasree Kotagiri FUNC_RECO_a, 144*531d6ab3SKavyasree Kotagiri FUNC_RECO_b, 145edc72546SLars Povlsen FUNC_RECO_CLK, 146*531d6ab3SKavyasree Kotagiri FUNC_SD, 147edc72546SLars Povlsen FUNC_SFP, 148*531d6ab3SKavyasree Kotagiri FUNC_SFP_SD, 149ce8dc094SAlexandre Belloni FUNC_SG0, 150da801ab5SAlexandre Belloni FUNC_SG1, 151da801ab5SAlexandre Belloni FUNC_SG2, 152*531d6ab3SKavyasree Kotagiri FUNC_SGPIO_a, 153*531d6ab3SKavyasree Kotagiri FUNC_SGPIO_b, 154ce8dc094SAlexandre Belloni FUNC_SI, 155f8a74760SLars Povlsen FUNC_SI2, 156ce8dc094SAlexandre Belloni FUNC_TACHO, 157*531d6ab3SKavyasree Kotagiri FUNC_TACHO_a, 158*531d6ab3SKavyasree Kotagiri FUNC_TACHO_b, 159ce8dc094SAlexandre Belloni FUNC_TWI, 160da801ab5SAlexandre Belloni FUNC_TWI2, 161f8a74760SLars Povlsen FUNC_TWI3, 162ce8dc094SAlexandre Belloni FUNC_TWI_SCL_M, 163*531d6ab3SKavyasree Kotagiri FUNC_TWI_SLC_GATE, 164*531d6ab3SKavyasree Kotagiri FUNC_TWI_SLC_GATE_AD, 165ce8dc094SAlexandre Belloni FUNC_UART, 166ce8dc094SAlexandre Belloni FUNC_UART2, 167f8a74760SLars Povlsen FUNC_UART3, 168*531d6ab3SKavyasree Kotagiri FUNC_USB_H_a, 169*531d6ab3SKavyasree Kotagiri FUNC_USB_H_b, 170*531d6ab3SKavyasree Kotagiri FUNC_USB_H_c, 171*531d6ab3SKavyasree Kotagiri FUNC_USB_S_a, 172*531d6ab3SKavyasree Kotagiri FUNC_USB_S_b, 173*531d6ab3SKavyasree Kotagiri FUNC_USB_S_c, 174f8a74760SLars Povlsen FUNC_PLL_STAT, 175f8a74760SLars Povlsen FUNC_EMMC, 176*531d6ab3SKavyasree Kotagiri FUNC_EMMC_SD, 177f8a74760SLars Povlsen FUNC_REF_CLK, 178f8a74760SLars Povlsen FUNC_RCVRD_CLK, 179ce8dc094SAlexandre Belloni FUNC_MAX 180ce8dc094SAlexandre Belloni }; 181ce8dc094SAlexandre Belloni 182ce8dc094SAlexandre Belloni static const char *const ocelot_function_names[] = { 183*531d6ab3SKavyasree Kotagiri [FUNC_CAN0_a] = "can0_a", 184*531d6ab3SKavyasree Kotagiri [FUNC_CAN0_b] = "can0_b", 185*531d6ab3SKavyasree Kotagiri [FUNC_CAN1] = "can1", 186ce8dc094SAlexandre Belloni [FUNC_NONE] = "none", 187*531d6ab3SKavyasree Kotagiri [FUNC_FC0_a] = "fc0_a", 188*531d6ab3SKavyasree Kotagiri [FUNC_FC0_b] = "fc0_b", 189*531d6ab3SKavyasree Kotagiri [FUNC_FC0_c] = "fc0_c", 190*531d6ab3SKavyasree Kotagiri [FUNC_FC1_a] = "fc1_a", 191*531d6ab3SKavyasree Kotagiri [FUNC_FC1_b] = "fc1_b", 192*531d6ab3SKavyasree Kotagiri [FUNC_FC1_c] = "fc1_c", 193*531d6ab3SKavyasree Kotagiri [FUNC_FC2_a] = "fc2_a", 194*531d6ab3SKavyasree Kotagiri [FUNC_FC2_b] = "fc2_b", 195*531d6ab3SKavyasree Kotagiri [FUNC_FC3_a] = "fc3_a", 196*531d6ab3SKavyasree Kotagiri [FUNC_FC3_b] = "fc3_b", 197*531d6ab3SKavyasree Kotagiri [FUNC_FC3_c] = "fc3_c", 198*531d6ab3SKavyasree Kotagiri [FUNC_FC4_a] = "fc4_a", 199*531d6ab3SKavyasree Kotagiri [FUNC_FC4_b] = "fc4_b", 200*531d6ab3SKavyasree Kotagiri [FUNC_FC4_c] = "fc4_c", 201*531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD0] = "fc_shrd0", 202*531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD1] = "fc_shrd1", 203*531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD2] = "fc_shrd2", 204*531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD3] = "fc_shrd3", 205*531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD4] = "fc_shrd4", 206*531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD5] = "fc_shrd5", 207*531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD6] = "fc_shrd6", 208*531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD7] = "fc_shrd7", 209*531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD8] = "fc_shrd8", 210*531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD9] = "fc_shrd9", 211*531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD10] = "fc_shrd10", 212*531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD11] = "fc_shrd11", 213*531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD12] = "fc_shrd12", 214*531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD13] = "fc_shrd13", 215*531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD14] = "fc_shrd14", 216*531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD15] = "fc_shrd15", 217*531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD16] = "fc_shrd16", 218*531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD17] = "fc_shrd17", 219*531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD18] = "fc_shrd18", 220*531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD19] = "fc_shrd19", 221*531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD20] = "fc_shrd20", 222ce8dc094SAlexandre Belloni [FUNC_GPIO] = "gpio", 223*531d6ab3SKavyasree Kotagiri [FUNC_IB_TRG_a] = "ib_trig_a", 224*531d6ab3SKavyasree Kotagiri [FUNC_IB_TRG_b] = "ib_trig_b", 225*531d6ab3SKavyasree Kotagiri [FUNC_IB_TRG_c] = "ib_trig_c", 226f8a74760SLars Povlsen [FUNC_IRQ0] = "irq0", 227*531d6ab3SKavyasree Kotagiri [FUNC_IRQ_IN_a] = "irq_in_a", 228*531d6ab3SKavyasree Kotagiri [FUNC_IRQ_IN_b] = "irq_in_b", 229*531d6ab3SKavyasree Kotagiri [FUNC_IRQ_IN_c] = "irq_in_c", 230ce8dc094SAlexandre Belloni [FUNC_IRQ0_IN] = "irq0_in", 231*531d6ab3SKavyasree Kotagiri [FUNC_IRQ_OUT_a] = "irq_out_a", 232*531d6ab3SKavyasree Kotagiri [FUNC_IRQ_OUT_b] = "irq_out_b", 233*531d6ab3SKavyasree Kotagiri [FUNC_IRQ_OUT_c] = "irq_out_c", 234ce8dc094SAlexandre Belloni [FUNC_IRQ0_OUT] = "irq0_out", 235f8a74760SLars Povlsen [FUNC_IRQ1] = "irq1", 236ce8dc094SAlexandre Belloni [FUNC_IRQ1_IN] = "irq1_in", 237ce8dc094SAlexandre Belloni [FUNC_IRQ1_OUT] = "irq1_out", 238f8a74760SLars Povlsen [FUNC_EXT_IRQ] = "ext_irq", 239edc72546SLars Povlsen [FUNC_MIIM] = "miim", 240*531d6ab3SKavyasree Kotagiri [FUNC_MIIM_a] = "miim_a", 241*531d6ab3SKavyasree Kotagiri [FUNC_MIIM_b] = "miim_b", 242*531d6ab3SKavyasree Kotagiri [FUNC_MIIM_c] = "miim_c", 243*531d6ab3SKavyasree Kotagiri [FUNC_MIIM_Sa] = "miim_slave_a", 244*531d6ab3SKavyasree Kotagiri [FUNC_MIIM_Sb] = "miim_slave_b", 245f8a74760SLars Povlsen [FUNC_PHY_LED] = "phy_led", 246ce8dc094SAlexandre Belloni [FUNC_PCI_WAKE] = "pci_wake", 247f8a74760SLars Povlsen [FUNC_MD] = "md", 248*531d6ab3SKavyasree Kotagiri [FUNC_OB_TRG] = "ob_trig", 249*531d6ab3SKavyasree Kotagiri [FUNC_OB_TRG_a] = "ob_trig_a", 250*531d6ab3SKavyasree Kotagiri [FUNC_OB_TRG_b] = "ob_trig_b", 251ce8dc094SAlexandre Belloni [FUNC_PTP0] = "ptp0", 252ce8dc094SAlexandre Belloni [FUNC_PTP1] = "ptp1", 253ce8dc094SAlexandre Belloni [FUNC_PTP2] = "ptp2", 254ce8dc094SAlexandre Belloni [FUNC_PTP3] = "ptp3", 255*531d6ab3SKavyasree Kotagiri [FUNC_PTPSYNC_1] = "ptpsync_1", 256*531d6ab3SKavyasree Kotagiri [FUNC_PTPSYNC_2] = "ptpsync_2", 257*531d6ab3SKavyasree Kotagiri [FUNC_PTPSYNC_3] = "ptpsync_3", 258*531d6ab3SKavyasree Kotagiri [FUNC_PTPSYNC_4] = "ptpsync_4", 259*531d6ab3SKavyasree Kotagiri [FUNC_PTPSYNC_5] = "ptpsync_5", 260*531d6ab3SKavyasree Kotagiri [FUNC_PTPSYNC_6] = "ptpsync_6", 261*531d6ab3SKavyasree Kotagiri [FUNC_PTPSYNC_7] = "ptpsync_7", 262ce8dc094SAlexandre Belloni [FUNC_PWM] = "pwm", 263*531d6ab3SKavyasree Kotagiri [FUNC_QSPI1] = "qspi1", 264*531d6ab3SKavyasree Kotagiri [FUNC_QSPI2] = "qspi2", 265*531d6ab3SKavyasree Kotagiri [FUNC_R] = "reserved", 266*531d6ab3SKavyasree Kotagiri [FUNC_RECO_a] = "reco_a", 267*531d6ab3SKavyasree Kotagiri [FUNC_RECO_b] = "reco_b", 268edc72546SLars Povlsen [FUNC_RECO_CLK] = "reco_clk", 269*531d6ab3SKavyasree Kotagiri [FUNC_SD] = "sd", 270edc72546SLars Povlsen [FUNC_SFP] = "sfp", 271*531d6ab3SKavyasree Kotagiri [FUNC_SFP_SD] = "sfp_sd", 272ce8dc094SAlexandre Belloni [FUNC_SG0] = "sg0", 273da801ab5SAlexandre Belloni [FUNC_SG1] = "sg1", 274da801ab5SAlexandre Belloni [FUNC_SG2] = "sg2", 275*531d6ab3SKavyasree Kotagiri [FUNC_SGPIO_a] = "sgpio_a", 276*531d6ab3SKavyasree Kotagiri [FUNC_SGPIO_b] = "sgpio_b", 277ce8dc094SAlexandre Belloni [FUNC_SI] = "si", 278f8a74760SLars Povlsen [FUNC_SI2] = "si2", 279ce8dc094SAlexandre Belloni [FUNC_TACHO] = "tacho", 280*531d6ab3SKavyasree Kotagiri [FUNC_TACHO_a] = "tacho_a", 281*531d6ab3SKavyasree Kotagiri [FUNC_TACHO_b] = "tacho_b", 282ce8dc094SAlexandre Belloni [FUNC_TWI] = "twi", 283da801ab5SAlexandre Belloni [FUNC_TWI2] = "twi2", 284f8a74760SLars Povlsen [FUNC_TWI3] = "twi3", 285ce8dc094SAlexandre Belloni [FUNC_TWI_SCL_M] = "twi_scl_m", 286*531d6ab3SKavyasree Kotagiri [FUNC_TWI_SLC_GATE] = "twi_slc_gate", 287*531d6ab3SKavyasree Kotagiri [FUNC_TWI_SLC_GATE_AD] = "twi_slc_gate_ad", 288*531d6ab3SKavyasree Kotagiri [FUNC_USB_H_a] = "usb_host_a", 289*531d6ab3SKavyasree Kotagiri [FUNC_USB_H_b] = "usb_host_b", 290*531d6ab3SKavyasree Kotagiri [FUNC_USB_H_c] = "usb_host_c", 291*531d6ab3SKavyasree Kotagiri [FUNC_USB_S_a] = "usb_slave_a", 292*531d6ab3SKavyasree Kotagiri [FUNC_USB_S_b] = "usb_slave_b", 293*531d6ab3SKavyasree Kotagiri [FUNC_USB_S_c] = "usb_slave_c", 294ce8dc094SAlexandre Belloni [FUNC_UART] = "uart", 295ce8dc094SAlexandre Belloni [FUNC_UART2] = "uart2", 296f8a74760SLars Povlsen [FUNC_UART3] = "uart3", 297f8a74760SLars Povlsen [FUNC_PLL_STAT] = "pll_stat", 298f8a74760SLars Povlsen [FUNC_EMMC] = "emmc", 299*531d6ab3SKavyasree Kotagiri [FUNC_EMMC_SD] = "emmc_sd", 300f8a74760SLars Povlsen [FUNC_REF_CLK] = "ref_clk", 301f8a74760SLars Povlsen [FUNC_RCVRD_CLK] = "rcvrd_clk", 302ce8dc094SAlexandre Belloni }; 303ce8dc094SAlexandre Belloni 304ce8dc094SAlexandre Belloni struct ocelot_pmx_func { 305ce8dc094SAlexandre Belloni const char **groups; 306ce8dc094SAlexandre Belloni unsigned int ngroups; 307ce8dc094SAlexandre Belloni }; 308ce8dc094SAlexandre Belloni 309ce8dc094SAlexandre Belloni struct ocelot_pin_caps { 310ce8dc094SAlexandre Belloni unsigned int pin; 311ce8dc094SAlexandre Belloni unsigned char functions[OCELOT_FUNC_PER_PIN]; 312*531d6ab3SKavyasree Kotagiri unsigned char a_functions[OCELOT_FUNC_PER_PIN]; /* Additional functions */ 313ce8dc094SAlexandre Belloni }; 314ce8dc094SAlexandre Belloni 315ce8dc094SAlexandre Belloni struct ocelot_pinctrl { 316ce8dc094SAlexandre Belloni struct device *dev; 317ce8dc094SAlexandre Belloni struct pinctrl_dev *pctl; 318ce8dc094SAlexandre Belloni struct gpio_chip gpio_chip; 319ce8dc094SAlexandre Belloni struct regmap *map; 320f8a74760SLars Povlsen void __iomem *pincfg; 321da801ab5SAlexandre Belloni struct pinctrl_desc *desc; 322ce8dc094SAlexandre Belloni struct ocelot_pmx_func func[FUNC_MAX]; 323da801ab5SAlexandre Belloni u8 stride; 324ce8dc094SAlexandre Belloni }; 325ce8dc094SAlexandre Belloni 3268f27440dSLars Povlsen #define LUTON_P(p, f0, f1) \ 3278f27440dSLars Povlsen static struct ocelot_pin_caps luton_pin_##p = { \ 3288f27440dSLars Povlsen .pin = p, \ 3298f27440dSLars Povlsen .functions = { \ 3308f27440dSLars Povlsen FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_NONE, \ 3318f27440dSLars Povlsen }, \ 3328f27440dSLars Povlsen } 3338f27440dSLars Povlsen 3348f27440dSLars Povlsen LUTON_P(0, SG0, NONE); 3358f27440dSLars Povlsen LUTON_P(1, SG0, NONE); 3368f27440dSLars Povlsen LUTON_P(2, SG0, NONE); 3378f27440dSLars Povlsen LUTON_P(3, SG0, NONE); 3388f27440dSLars Povlsen LUTON_P(4, TACHO, NONE); 3398f27440dSLars Povlsen LUTON_P(5, TWI, PHY_LED); 3408f27440dSLars Povlsen LUTON_P(6, TWI, PHY_LED); 3418f27440dSLars Povlsen LUTON_P(7, NONE, PHY_LED); 3428f27440dSLars Povlsen LUTON_P(8, EXT_IRQ, PHY_LED); 3438f27440dSLars Povlsen LUTON_P(9, EXT_IRQ, PHY_LED); 3448f27440dSLars Povlsen LUTON_P(10, SFP, PHY_LED); 3458f27440dSLars Povlsen LUTON_P(11, SFP, PHY_LED); 3468f27440dSLars Povlsen LUTON_P(12, SFP, PHY_LED); 3478f27440dSLars Povlsen LUTON_P(13, SFP, PHY_LED); 3488f27440dSLars Povlsen LUTON_P(14, SI, PHY_LED); 3498f27440dSLars Povlsen LUTON_P(15, SI, PHY_LED); 3508f27440dSLars Povlsen LUTON_P(16, SI, PHY_LED); 3518f27440dSLars Povlsen LUTON_P(17, SFP, PHY_LED); 3528f27440dSLars Povlsen LUTON_P(18, SFP, PHY_LED); 3538f27440dSLars Povlsen LUTON_P(19, SFP, PHY_LED); 3548f27440dSLars Povlsen LUTON_P(20, SFP, PHY_LED); 3558f27440dSLars Povlsen LUTON_P(21, SFP, PHY_LED); 3568f27440dSLars Povlsen LUTON_P(22, SFP, PHY_LED); 3578f27440dSLars Povlsen LUTON_P(23, SFP, PHY_LED); 3588f27440dSLars Povlsen LUTON_P(24, SFP, PHY_LED); 3598f27440dSLars Povlsen LUTON_P(25, SFP, PHY_LED); 3608f27440dSLars Povlsen LUTON_P(26, SFP, PHY_LED); 3618f27440dSLars Povlsen LUTON_P(27, SFP, PHY_LED); 3628f27440dSLars Povlsen LUTON_P(28, SFP, PHY_LED); 3638f27440dSLars Povlsen LUTON_P(29, PWM, NONE); 3648f27440dSLars Povlsen LUTON_P(30, UART, NONE); 3658f27440dSLars Povlsen LUTON_P(31, UART, NONE); 3668f27440dSLars Povlsen 3678f27440dSLars Povlsen #define LUTON_PIN(n) { \ 3688f27440dSLars Povlsen .number = n, \ 3698f27440dSLars Povlsen .name = "GPIO_"#n, \ 3708f27440dSLars Povlsen .drv_data = &luton_pin_##n \ 3718f27440dSLars Povlsen } 3728f27440dSLars Povlsen 3738f27440dSLars Povlsen static const struct pinctrl_pin_desc luton_pins[] = { 3748f27440dSLars Povlsen LUTON_PIN(0), 3758f27440dSLars Povlsen LUTON_PIN(1), 3768f27440dSLars Povlsen LUTON_PIN(2), 3778f27440dSLars Povlsen LUTON_PIN(3), 3788f27440dSLars Povlsen LUTON_PIN(4), 3798f27440dSLars Povlsen LUTON_PIN(5), 3808f27440dSLars Povlsen LUTON_PIN(6), 3818f27440dSLars Povlsen LUTON_PIN(7), 3828f27440dSLars Povlsen LUTON_PIN(8), 3838f27440dSLars Povlsen LUTON_PIN(9), 3848f27440dSLars Povlsen LUTON_PIN(10), 3858f27440dSLars Povlsen LUTON_PIN(11), 3868f27440dSLars Povlsen LUTON_PIN(12), 3878f27440dSLars Povlsen LUTON_PIN(13), 3888f27440dSLars Povlsen LUTON_PIN(14), 3898f27440dSLars Povlsen LUTON_PIN(15), 3908f27440dSLars Povlsen LUTON_PIN(16), 3918f27440dSLars Povlsen LUTON_PIN(17), 3928f27440dSLars Povlsen LUTON_PIN(18), 3938f27440dSLars Povlsen LUTON_PIN(19), 3948f27440dSLars Povlsen LUTON_PIN(20), 3958f27440dSLars Povlsen LUTON_PIN(21), 3968f27440dSLars Povlsen LUTON_PIN(22), 3978f27440dSLars Povlsen LUTON_PIN(23), 3988f27440dSLars Povlsen LUTON_PIN(24), 3998f27440dSLars Povlsen LUTON_PIN(25), 4008f27440dSLars Povlsen LUTON_PIN(26), 4018f27440dSLars Povlsen LUTON_PIN(27), 4028f27440dSLars Povlsen LUTON_PIN(28), 4038f27440dSLars Povlsen LUTON_PIN(29), 4048f27440dSLars Povlsen LUTON_PIN(30), 4058f27440dSLars Povlsen LUTON_PIN(31), 4068f27440dSLars Povlsen }; 4078f27440dSLars Povlsen 4086e6347e2SLars Povlsen #define SERVAL_P(p, f0, f1, f2) \ 4096e6347e2SLars Povlsen static struct ocelot_pin_caps serval_pin_##p = { \ 4106e6347e2SLars Povlsen .pin = p, \ 4116e6347e2SLars Povlsen .functions = { \ 4126e6347e2SLars Povlsen FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2, \ 4136e6347e2SLars Povlsen }, \ 4146e6347e2SLars Povlsen } 4156e6347e2SLars Povlsen 4166e6347e2SLars Povlsen SERVAL_P(0, SG0, NONE, NONE); 4176e6347e2SLars Povlsen SERVAL_P(1, SG0, NONE, NONE); 4186e6347e2SLars Povlsen SERVAL_P(2, SG0, NONE, NONE); 4196e6347e2SLars Povlsen SERVAL_P(3, SG0, NONE, NONE); 4206e6347e2SLars Povlsen SERVAL_P(4, TACHO, NONE, NONE); 4216e6347e2SLars Povlsen SERVAL_P(5, PWM, NONE, NONE); 4226e6347e2SLars Povlsen SERVAL_P(6, TWI, NONE, NONE); 4236e6347e2SLars Povlsen SERVAL_P(7, TWI, NONE, NONE); 4246e6347e2SLars Povlsen SERVAL_P(8, SI, NONE, NONE); 4256e6347e2SLars Povlsen SERVAL_P(9, SI, MD, NONE); 4266e6347e2SLars Povlsen SERVAL_P(10, SI, MD, NONE); 4276e6347e2SLars Povlsen SERVAL_P(11, SFP, MD, TWI_SCL_M); 4286e6347e2SLars Povlsen SERVAL_P(12, SFP, MD, TWI_SCL_M); 4296e6347e2SLars Povlsen SERVAL_P(13, SFP, UART2, TWI_SCL_M); 4306e6347e2SLars Povlsen SERVAL_P(14, SFP, UART2, TWI_SCL_M); 4316e6347e2SLars Povlsen SERVAL_P(15, SFP, PTP0, TWI_SCL_M); 4326e6347e2SLars Povlsen SERVAL_P(16, SFP, PTP0, TWI_SCL_M); 4336e6347e2SLars Povlsen SERVAL_P(17, SFP, PCI_WAKE, TWI_SCL_M); 4346e6347e2SLars Povlsen SERVAL_P(18, SFP, NONE, TWI_SCL_M); 4356e6347e2SLars Povlsen SERVAL_P(19, SFP, NONE, TWI_SCL_M); 4366e6347e2SLars Povlsen SERVAL_P(20, SFP, NONE, TWI_SCL_M); 4376e6347e2SLars Povlsen SERVAL_P(21, SFP, NONE, TWI_SCL_M); 4386e6347e2SLars Povlsen SERVAL_P(22, NONE, NONE, NONE); 4396e6347e2SLars Povlsen SERVAL_P(23, NONE, NONE, NONE); 4406e6347e2SLars Povlsen SERVAL_P(24, NONE, NONE, NONE); 4416e6347e2SLars Povlsen SERVAL_P(25, NONE, NONE, NONE); 4426e6347e2SLars Povlsen SERVAL_P(26, UART, NONE, NONE); 4436e6347e2SLars Povlsen SERVAL_P(27, UART, NONE, NONE); 4446e6347e2SLars Povlsen SERVAL_P(28, IRQ0, NONE, NONE); 4456e6347e2SLars Povlsen SERVAL_P(29, IRQ1, NONE, NONE); 4466e6347e2SLars Povlsen SERVAL_P(30, PTP0, NONE, NONE); 4476e6347e2SLars Povlsen SERVAL_P(31, PTP0, NONE, NONE); 4486e6347e2SLars Povlsen 4496e6347e2SLars Povlsen #define SERVAL_PIN(n) { \ 4506e6347e2SLars Povlsen .number = n, \ 4516e6347e2SLars Povlsen .name = "GPIO_"#n, \ 4526e6347e2SLars Povlsen .drv_data = &serval_pin_##n \ 4536e6347e2SLars Povlsen } 4546e6347e2SLars Povlsen 4556e6347e2SLars Povlsen static const struct pinctrl_pin_desc serval_pins[] = { 4566e6347e2SLars Povlsen SERVAL_PIN(0), 4576e6347e2SLars Povlsen SERVAL_PIN(1), 4586e6347e2SLars Povlsen SERVAL_PIN(2), 4596e6347e2SLars Povlsen SERVAL_PIN(3), 4606e6347e2SLars Povlsen SERVAL_PIN(4), 4616e6347e2SLars Povlsen SERVAL_PIN(5), 4626e6347e2SLars Povlsen SERVAL_PIN(6), 4636e6347e2SLars Povlsen SERVAL_PIN(7), 4646e6347e2SLars Povlsen SERVAL_PIN(8), 4656e6347e2SLars Povlsen SERVAL_PIN(9), 4666e6347e2SLars Povlsen SERVAL_PIN(10), 4676e6347e2SLars Povlsen SERVAL_PIN(11), 4686e6347e2SLars Povlsen SERVAL_PIN(12), 4696e6347e2SLars Povlsen SERVAL_PIN(13), 4706e6347e2SLars Povlsen SERVAL_PIN(14), 4716e6347e2SLars Povlsen SERVAL_PIN(15), 4726e6347e2SLars Povlsen SERVAL_PIN(16), 4736e6347e2SLars Povlsen SERVAL_PIN(17), 4746e6347e2SLars Povlsen SERVAL_PIN(18), 4756e6347e2SLars Povlsen SERVAL_PIN(19), 4766e6347e2SLars Povlsen SERVAL_PIN(20), 4776e6347e2SLars Povlsen SERVAL_PIN(21), 4786e6347e2SLars Povlsen SERVAL_PIN(22), 4796e6347e2SLars Povlsen SERVAL_PIN(23), 4806e6347e2SLars Povlsen SERVAL_PIN(24), 4816e6347e2SLars Povlsen SERVAL_PIN(25), 4826e6347e2SLars Povlsen SERVAL_PIN(26), 4836e6347e2SLars Povlsen SERVAL_PIN(27), 4846e6347e2SLars Povlsen SERVAL_PIN(28), 4856e6347e2SLars Povlsen SERVAL_PIN(29), 4866e6347e2SLars Povlsen SERVAL_PIN(30), 4876e6347e2SLars Povlsen SERVAL_PIN(31), 4886e6347e2SLars Povlsen }; 4896e6347e2SLars Povlsen 490ce8dc094SAlexandre Belloni #define OCELOT_P(p, f0, f1, f2) \ 491ce8dc094SAlexandre Belloni static struct ocelot_pin_caps ocelot_pin_##p = { \ 492ce8dc094SAlexandre Belloni .pin = p, \ 493ce8dc094SAlexandre Belloni .functions = { \ 494ce8dc094SAlexandre Belloni FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2, \ 495ce8dc094SAlexandre Belloni }, \ 496ce8dc094SAlexandre Belloni } 497ce8dc094SAlexandre Belloni 498ce8dc094SAlexandre Belloni OCELOT_P(0, SG0, NONE, NONE); 499ce8dc094SAlexandre Belloni OCELOT_P(1, SG0, NONE, NONE); 500ce8dc094SAlexandre Belloni OCELOT_P(2, SG0, NONE, NONE); 501ce8dc094SAlexandre Belloni OCELOT_P(3, SG0, NONE, NONE); 50217f79084SAlexandre Belloni OCELOT_P(4, IRQ0_IN, IRQ0_OUT, TWI_SCL_M); 503ce8dc094SAlexandre Belloni OCELOT_P(5, IRQ1_IN, IRQ1_OUT, PCI_WAKE); 504ce8dc094SAlexandre Belloni OCELOT_P(6, UART, TWI_SCL_M, NONE); 505ce8dc094SAlexandre Belloni OCELOT_P(7, UART, TWI_SCL_M, NONE); 506ce8dc094SAlexandre Belloni OCELOT_P(8, SI, TWI_SCL_M, IRQ0_OUT); 507ce8dc094SAlexandre Belloni OCELOT_P(9, SI, TWI_SCL_M, IRQ1_OUT); 508edc72546SLars Povlsen OCELOT_P(10, PTP2, TWI_SCL_M, SFP); 509edc72546SLars Povlsen OCELOT_P(11, PTP3, TWI_SCL_M, SFP); 510edc72546SLars Povlsen OCELOT_P(12, UART2, TWI_SCL_M, SFP); 511edc72546SLars Povlsen OCELOT_P(13, UART2, TWI_SCL_M, SFP); 512edc72546SLars Povlsen OCELOT_P(14, MIIM, TWI_SCL_M, SFP); 513edc72546SLars Povlsen OCELOT_P(15, MIIM, TWI_SCL_M, SFP); 514ce8dc094SAlexandre Belloni OCELOT_P(16, TWI, NONE, SI); 515ce8dc094SAlexandre Belloni OCELOT_P(17, TWI, TWI_SCL_M, SI); 516ce8dc094SAlexandre Belloni OCELOT_P(18, PTP0, TWI_SCL_M, NONE); 517ce8dc094SAlexandre Belloni OCELOT_P(19, PTP1, TWI_SCL_M, NONE); 518edc72546SLars Povlsen OCELOT_P(20, RECO_CLK, TACHO, TWI_SCL_M); 519edc72546SLars Povlsen OCELOT_P(21, RECO_CLK, PWM, TWI_SCL_M); 520ce8dc094SAlexandre Belloni 521ce8dc094SAlexandre Belloni #define OCELOT_PIN(n) { \ 522ce8dc094SAlexandre Belloni .number = n, \ 523ce8dc094SAlexandre Belloni .name = "GPIO_"#n, \ 524ce8dc094SAlexandre Belloni .drv_data = &ocelot_pin_##n \ 525ce8dc094SAlexandre Belloni } 526ce8dc094SAlexandre Belloni 527ce8dc094SAlexandre Belloni static const struct pinctrl_pin_desc ocelot_pins[] = { 528ce8dc094SAlexandre Belloni OCELOT_PIN(0), 529ce8dc094SAlexandre Belloni OCELOT_PIN(1), 530ce8dc094SAlexandre Belloni OCELOT_PIN(2), 531ce8dc094SAlexandre Belloni OCELOT_PIN(3), 532ce8dc094SAlexandre Belloni OCELOT_PIN(4), 533ce8dc094SAlexandre Belloni OCELOT_PIN(5), 534ce8dc094SAlexandre Belloni OCELOT_PIN(6), 535ce8dc094SAlexandre Belloni OCELOT_PIN(7), 536ce8dc094SAlexandre Belloni OCELOT_PIN(8), 537ce8dc094SAlexandre Belloni OCELOT_PIN(9), 538ce8dc094SAlexandre Belloni OCELOT_PIN(10), 539ce8dc094SAlexandre Belloni OCELOT_PIN(11), 540ce8dc094SAlexandre Belloni OCELOT_PIN(12), 541ce8dc094SAlexandre Belloni OCELOT_PIN(13), 542ce8dc094SAlexandre Belloni OCELOT_PIN(14), 543ce8dc094SAlexandre Belloni OCELOT_PIN(15), 544ce8dc094SAlexandre Belloni OCELOT_PIN(16), 545ce8dc094SAlexandre Belloni OCELOT_PIN(17), 546ce8dc094SAlexandre Belloni OCELOT_PIN(18), 547ce8dc094SAlexandre Belloni OCELOT_PIN(19), 548ce8dc094SAlexandre Belloni OCELOT_PIN(20), 549ce8dc094SAlexandre Belloni OCELOT_PIN(21), 550ce8dc094SAlexandre Belloni }; 551ce8dc094SAlexandre Belloni 552da801ab5SAlexandre Belloni #define JAGUAR2_P(p, f0, f1) \ 553da801ab5SAlexandre Belloni static struct ocelot_pin_caps jaguar2_pin_##p = { \ 554da801ab5SAlexandre Belloni .pin = p, \ 555da801ab5SAlexandre Belloni .functions = { \ 556da801ab5SAlexandre Belloni FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_NONE \ 557da801ab5SAlexandre Belloni }, \ 558da801ab5SAlexandre Belloni } 559da801ab5SAlexandre Belloni 560da801ab5SAlexandre Belloni JAGUAR2_P(0, SG0, NONE); 561da801ab5SAlexandre Belloni JAGUAR2_P(1, SG0, NONE); 562da801ab5SAlexandre Belloni JAGUAR2_P(2, SG0, NONE); 563da801ab5SAlexandre Belloni JAGUAR2_P(3, SG0, NONE); 564da801ab5SAlexandre Belloni JAGUAR2_P(4, SG1, NONE); 565da801ab5SAlexandre Belloni JAGUAR2_P(5, SG1, NONE); 566da801ab5SAlexandre Belloni JAGUAR2_P(6, IRQ0_IN, IRQ0_OUT); 567da801ab5SAlexandre Belloni JAGUAR2_P(7, IRQ1_IN, IRQ1_OUT); 568da801ab5SAlexandre Belloni JAGUAR2_P(8, PTP0, NONE); 569da801ab5SAlexandre Belloni JAGUAR2_P(9, PTP1, NONE); 570da801ab5SAlexandre Belloni JAGUAR2_P(10, UART, NONE); 571da801ab5SAlexandre Belloni JAGUAR2_P(11, UART, NONE); 572da801ab5SAlexandre Belloni JAGUAR2_P(12, SG1, NONE); 573da801ab5SAlexandre Belloni JAGUAR2_P(13, SG1, NONE); 574da801ab5SAlexandre Belloni JAGUAR2_P(14, TWI, TWI_SCL_M); 575da801ab5SAlexandre Belloni JAGUAR2_P(15, TWI, NONE); 576da801ab5SAlexandre Belloni JAGUAR2_P(16, SI, TWI_SCL_M); 577da801ab5SAlexandre Belloni JAGUAR2_P(17, SI, TWI_SCL_M); 578da801ab5SAlexandre Belloni JAGUAR2_P(18, SI, TWI_SCL_M); 579da801ab5SAlexandre Belloni JAGUAR2_P(19, PCI_WAKE, NONE); 580da801ab5SAlexandre Belloni JAGUAR2_P(20, IRQ0_OUT, TWI_SCL_M); 581da801ab5SAlexandre Belloni JAGUAR2_P(21, IRQ1_OUT, TWI_SCL_M); 582da801ab5SAlexandre Belloni JAGUAR2_P(22, TACHO, NONE); 583da801ab5SAlexandre Belloni JAGUAR2_P(23, PWM, NONE); 584da801ab5SAlexandre Belloni JAGUAR2_P(24, UART2, NONE); 585da801ab5SAlexandre Belloni JAGUAR2_P(25, UART2, SI); 586da801ab5SAlexandre Belloni JAGUAR2_P(26, PTP2, SI); 587da801ab5SAlexandre Belloni JAGUAR2_P(27, PTP3, SI); 588da801ab5SAlexandre Belloni JAGUAR2_P(28, TWI2, SI); 589da801ab5SAlexandre Belloni JAGUAR2_P(29, TWI2, SI); 590da801ab5SAlexandre Belloni JAGUAR2_P(30, SG2, SI); 591da801ab5SAlexandre Belloni JAGUAR2_P(31, SG2, SI); 592da801ab5SAlexandre Belloni JAGUAR2_P(32, SG2, SI); 593da801ab5SAlexandre Belloni JAGUAR2_P(33, SG2, SI); 594da801ab5SAlexandre Belloni JAGUAR2_P(34, NONE, TWI_SCL_M); 595da801ab5SAlexandre Belloni JAGUAR2_P(35, NONE, TWI_SCL_M); 596da801ab5SAlexandre Belloni JAGUAR2_P(36, NONE, TWI_SCL_M); 597da801ab5SAlexandre Belloni JAGUAR2_P(37, NONE, TWI_SCL_M); 598da801ab5SAlexandre Belloni JAGUAR2_P(38, NONE, TWI_SCL_M); 599da801ab5SAlexandre Belloni JAGUAR2_P(39, NONE, TWI_SCL_M); 600da801ab5SAlexandre Belloni JAGUAR2_P(40, NONE, TWI_SCL_M); 601da801ab5SAlexandre Belloni JAGUAR2_P(41, NONE, TWI_SCL_M); 602da801ab5SAlexandre Belloni JAGUAR2_P(42, NONE, TWI_SCL_M); 603da801ab5SAlexandre Belloni JAGUAR2_P(43, NONE, TWI_SCL_M); 604edc72546SLars Povlsen JAGUAR2_P(44, NONE, SFP); 605edc72546SLars Povlsen JAGUAR2_P(45, NONE, SFP); 606edc72546SLars Povlsen JAGUAR2_P(46, NONE, SFP); 607edc72546SLars Povlsen JAGUAR2_P(47, NONE, SFP); 608edc72546SLars Povlsen JAGUAR2_P(48, SFP, NONE); 609edc72546SLars Povlsen JAGUAR2_P(49, SFP, SI); 610edc72546SLars Povlsen JAGUAR2_P(50, SFP, SI); 611edc72546SLars Povlsen JAGUAR2_P(51, SFP, SI); 612edc72546SLars Povlsen JAGUAR2_P(52, SFP, NONE); 613edc72546SLars Povlsen JAGUAR2_P(53, SFP, NONE); 614edc72546SLars Povlsen JAGUAR2_P(54, SFP, NONE); 615edc72546SLars Povlsen JAGUAR2_P(55, SFP, NONE); 616edc72546SLars Povlsen JAGUAR2_P(56, MIIM, SFP); 617edc72546SLars Povlsen JAGUAR2_P(57, MIIM, SFP); 618edc72546SLars Povlsen JAGUAR2_P(58, MIIM, SFP); 619edc72546SLars Povlsen JAGUAR2_P(59, MIIM, SFP); 620da801ab5SAlexandre Belloni JAGUAR2_P(60, NONE, NONE); 621da801ab5SAlexandre Belloni JAGUAR2_P(61, NONE, NONE); 622da801ab5SAlexandre Belloni JAGUAR2_P(62, NONE, NONE); 623da801ab5SAlexandre Belloni JAGUAR2_P(63, NONE, NONE); 624da801ab5SAlexandre Belloni 625da801ab5SAlexandre Belloni #define JAGUAR2_PIN(n) { \ 626da801ab5SAlexandre Belloni .number = n, \ 627da801ab5SAlexandre Belloni .name = "GPIO_"#n, \ 628da801ab5SAlexandre Belloni .drv_data = &jaguar2_pin_##n \ 629da801ab5SAlexandre Belloni } 630da801ab5SAlexandre Belloni 631da801ab5SAlexandre Belloni static const struct pinctrl_pin_desc jaguar2_pins[] = { 632da801ab5SAlexandre Belloni JAGUAR2_PIN(0), 633da801ab5SAlexandre Belloni JAGUAR2_PIN(1), 634da801ab5SAlexandre Belloni JAGUAR2_PIN(2), 635da801ab5SAlexandre Belloni JAGUAR2_PIN(3), 636da801ab5SAlexandre Belloni JAGUAR2_PIN(4), 637da801ab5SAlexandre Belloni JAGUAR2_PIN(5), 638da801ab5SAlexandre Belloni JAGUAR2_PIN(6), 639da801ab5SAlexandre Belloni JAGUAR2_PIN(7), 640da801ab5SAlexandre Belloni JAGUAR2_PIN(8), 641da801ab5SAlexandre Belloni JAGUAR2_PIN(9), 642da801ab5SAlexandre Belloni JAGUAR2_PIN(10), 643da801ab5SAlexandre Belloni JAGUAR2_PIN(11), 644da801ab5SAlexandre Belloni JAGUAR2_PIN(12), 645da801ab5SAlexandre Belloni JAGUAR2_PIN(13), 646da801ab5SAlexandre Belloni JAGUAR2_PIN(14), 647da801ab5SAlexandre Belloni JAGUAR2_PIN(15), 648da801ab5SAlexandre Belloni JAGUAR2_PIN(16), 649da801ab5SAlexandre Belloni JAGUAR2_PIN(17), 650da801ab5SAlexandre Belloni JAGUAR2_PIN(18), 651da801ab5SAlexandre Belloni JAGUAR2_PIN(19), 652da801ab5SAlexandre Belloni JAGUAR2_PIN(20), 653da801ab5SAlexandre Belloni JAGUAR2_PIN(21), 654da801ab5SAlexandre Belloni JAGUAR2_PIN(22), 655da801ab5SAlexandre Belloni JAGUAR2_PIN(23), 656da801ab5SAlexandre Belloni JAGUAR2_PIN(24), 657da801ab5SAlexandre Belloni JAGUAR2_PIN(25), 658da801ab5SAlexandre Belloni JAGUAR2_PIN(26), 659da801ab5SAlexandre Belloni JAGUAR2_PIN(27), 660da801ab5SAlexandre Belloni JAGUAR2_PIN(28), 661da801ab5SAlexandre Belloni JAGUAR2_PIN(29), 662da801ab5SAlexandre Belloni JAGUAR2_PIN(30), 663da801ab5SAlexandre Belloni JAGUAR2_PIN(31), 664da801ab5SAlexandre Belloni JAGUAR2_PIN(32), 665da801ab5SAlexandre Belloni JAGUAR2_PIN(33), 666da801ab5SAlexandre Belloni JAGUAR2_PIN(34), 667da801ab5SAlexandre Belloni JAGUAR2_PIN(35), 668da801ab5SAlexandre Belloni JAGUAR2_PIN(36), 669da801ab5SAlexandre Belloni JAGUAR2_PIN(37), 670da801ab5SAlexandre Belloni JAGUAR2_PIN(38), 671da801ab5SAlexandre Belloni JAGUAR2_PIN(39), 672da801ab5SAlexandre Belloni JAGUAR2_PIN(40), 673da801ab5SAlexandre Belloni JAGUAR2_PIN(41), 674da801ab5SAlexandre Belloni JAGUAR2_PIN(42), 675da801ab5SAlexandre Belloni JAGUAR2_PIN(43), 676da801ab5SAlexandre Belloni JAGUAR2_PIN(44), 677da801ab5SAlexandre Belloni JAGUAR2_PIN(45), 678da801ab5SAlexandre Belloni JAGUAR2_PIN(46), 679da801ab5SAlexandre Belloni JAGUAR2_PIN(47), 680da801ab5SAlexandre Belloni JAGUAR2_PIN(48), 681da801ab5SAlexandre Belloni JAGUAR2_PIN(49), 682da801ab5SAlexandre Belloni JAGUAR2_PIN(50), 683da801ab5SAlexandre Belloni JAGUAR2_PIN(51), 684da801ab5SAlexandre Belloni JAGUAR2_PIN(52), 685da801ab5SAlexandre Belloni JAGUAR2_PIN(53), 686da801ab5SAlexandre Belloni JAGUAR2_PIN(54), 687da801ab5SAlexandre Belloni JAGUAR2_PIN(55), 688da801ab5SAlexandre Belloni JAGUAR2_PIN(56), 689da801ab5SAlexandre Belloni JAGUAR2_PIN(57), 690da801ab5SAlexandre Belloni JAGUAR2_PIN(58), 691da801ab5SAlexandre Belloni JAGUAR2_PIN(59), 692da801ab5SAlexandre Belloni JAGUAR2_PIN(60), 693da801ab5SAlexandre Belloni JAGUAR2_PIN(61), 694da801ab5SAlexandre Belloni JAGUAR2_PIN(62), 695da801ab5SAlexandre Belloni JAGUAR2_PIN(63), 696da801ab5SAlexandre Belloni }; 697da801ab5SAlexandre Belloni 698f8a74760SLars Povlsen #define SPARX5_P(p, f0, f1, f2) \ 699f8a74760SLars Povlsen static struct ocelot_pin_caps sparx5_pin_##p = { \ 700f8a74760SLars Povlsen .pin = p, \ 701f8a74760SLars Povlsen .functions = { \ 702f8a74760SLars Povlsen FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2 \ 703f8a74760SLars Povlsen }, \ 704f8a74760SLars Povlsen } 705f8a74760SLars Povlsen 706f8a74760SLars Povlsen SPARX5_P(0, SG0, PLL_STAT, NONE); 707f8a74760SLars Povlsen SPARX5_P(1, SG0, NONE, NONE); 708f8a74760SLars Povlsen SPARX5_P(2, SG0, NONE, NONE); 709f8a74760SLars Povlsen SPARX5_P(3, SG0, NONE, NONE); 710f8a74760SLars Povlsen SPARX5_P(4, SG1, NONE, NONE); 711f8a74760SLars Povlsen SPARX5_P(5, SG1, NONE, NONE); 712f8a74760SLars Povlsen SPARX5_P(6, IRQ0_IN, IRQ0_OUT, SFP); 713f8a74760SLars Povlsen SPARX5_P(7, IRQ1_IN, IRQ1_OUT, SFP); 714f8a74760SLars Povlsen SPARX5_P(8, PTP0, NONE, SFP); 715f8a74760SLars Povlsen SPARX5_P(9, PTP1, SFP, TWI_SCL_M); 716f8a74760SLars Povlsen SPARX5_P(10, UART, NONE, NONE); 717f8a74760SLars Povlsen SPARX5_P(11, UART, NONE, NONE); 718f8a74760SLars Povlsen SPARX5_P(12, SG1, NONE, NONE); 719f8a74760SLars Povlsen SPARX5_P(13, SG1, NONE, NONE); 720f8a74760SLars Povlsen SPARX5_P(14, TWI, TWI_SCL_M, NONE); 721f8a74760SLars Povlsen SPARX5_P(15, TWI, NONE, NONE); 722f8a74760SLars Povlsen SPARX5_P(16, SI, TWI_SCL_M, SFP); 723f8a74760SLars Povlsen SPARX5_P(17, SI, TWI_SCL_M, SFP); 724f8a74760SLars Povlsen SPARX5_P(18, SI, TWI_SCL_M, SFP); 725f8a74760SLars Povlsen SPARX5_P(19, PCI_WAKE, TWI_SCL_M, SFP); 726f8a74760SLars Povlsen SPARX5_P(20, IRQ0_OUT, TWI_SCL_M, SFP); 727f8a74760SLars Povlsen SPARX5_P(21, IRQ1_OUT, TACHO, SFP); 728f8a74760SLars Povlsen SPARX5_P(22, TACHO, IRQ0_OUT, TWI_SCL_M); 729f8a74760SLars Povlsen SPARX5_P(23, PWM, UART3, TWI_SCL_M); 730f8a74760SLars Povlsen SPARX5_P(24, PTP2, UART3, TWI_SCL_M); 731f8a74760SLars Povlsen SPARX5_P(25, PTP3, SI, TWI_SCL_M); 732f8a74760SLars Povlsen SPARX5_P(26, UART2, SI, TWI_SCL_M); 733f8a74760SLars Povlsen SPARX5_P(27, UART2, SI, TWI_SCL_M); 734f8a74760SLars Povlsen SPARX5_P(28, TWI2, SI, SFP); 735f8a74760SLars Povlsen SPARX5_P(29, TWI2, SI, SFP); 736f8a74760SLars Povlsen SPARX5_P(30, SG2, SI, PWM); 737f8a74760SLars Povlsen SPARX5_P(31, SG2, SI, TWI_SCL_M); 738f8a74760SLars Povlsen SPARX5_P(32, SG2, SI, TWI_SCL_M); 739f8a74760SLars Povlsen SPARX5_P(33, SG2, SI, SFP); 740f8a74760SLars Povlsen SPARX5_P(34, NONE, TWI_SCL_M, EMMC); 741f8a74760SLars Povlsen SPARX5_P(35, SFP, TWI_SCL_M, EMMC); 742f8a74760SLars Povlsen SPARX5_P(36, SFP, TWI_SCL_M, EMMC); 743f8a74760SLars Povlsen SPARX5_P(37, SFP, NONE, EMMC); 744f8a74760SLars Povlsen SPARX5_P(38, NONE, TWI_SCL_M, EMMC); 745f8a74760SLars Povlsen SPARX5_P(39, SI2, TWI_SCL_M, EMMC); 746f8a74760SLars Povlsen SPARX5_P(40, SI2, TWI_SCL_M, EMMC); 747f8a74760SLars Povlsen SPARX5_P(41, SI2, TWI_SCL_M, EMMC); 748f8a74760SLars Povlsen SPARX5_P(42, SI2, TWI_SCL_M, EMMC); 749f8a74760SLars Povlsen SPARX5_P(43, SI2, TWI_SCL_M, EMMC); 750f8a74760SLars Povlsen SPARX5_P(44, SI, SFP, EMMC); 751f8a74760SLars Povlsen SPARX5_P(45, SI, SFP, EMMC); 752f8a74760SLars Povlsen SPARX5_P(46, NONE, SFP, EMMC); 753f8a74760SLars Povlsen SPARX5_P(47, NONE, SFP, EMMC); 754f8a74760SLars Povlsen SPARX5_P(48, TWI3, SI, SFP); 755f8a74760SLars Povlsen SPARX5_P(49, TWI3, NONE, SFP); 756f8a74760SLars Povlsen SPARX5_P(50, SFP, NONE, TWI_SCL_M); 757f8a74760SLars Povlsen SPARX5_P(51, SFP, SI, TWI_SCL_M); 758f8a74760SLars Povlsen SPARX5_P(52, SFP, MIIM, TWI_SCL_M); 759f8a74760SLars Povlsen SPARX5_P(53, SFP, MIIM, TWI_SCL_M); 760f8a74760SLars Povlsen SPARX5_P(54, SFP, PTP2, TWI_SCL_M); 761f8a74760SLars Povlsen SPARX5_P(55, SFP, PTP3, PCI_WAKE); 762f8a74760SLars Povlsen SPARX5_P(56, MIIM, SFP, TWI_SCL_M); 763f8a74760SLars Povlsen SPARX5_P(57, MIIM, SFP, TWI_SCL_M); 764f8a74760SLars Povlsen SPARX5_P(58, MIIM, SFP, TWI_SCL_M); 765f8a74760SLars Povlsen SPARX5_P(59, MIIM, SFP, NONE); 766f8a74760SLars Povlsen SPARX5_P(60, RECO_CLK, NONE, NONE); 767f8a74760SLars Povlsen SPARX5_P(61, RECO_CLK, NONE, NONE); 768f8a74760SLars Povlsen SPARX5_P(62, RECO_CLK, PLL_STAT, NONE); 769f8a74760SLars Povlsen SPARX5_P(63, RECO_CLK, NONE, NONE); 770f8a74760SLars Povlsen 771f8a74760SLars Povlsen #define SPARX5_PIN(n) { \ 772f8a74760SLars Povlsen .number = n, \ 773f8a74760SLars Povlsen .name = "GPIO_"#n, \ 774f8a74760SLars Povlsen .drv_data = &sparx5_pin_##n \ 775f8a74760SLars Povlsen } 776f8a74760SLars Povlsen 777f8a74760SLars Povlsen static const struct pinctrl_pin_desc sparx5_pins[] = { 778f8a74760SLars Povlsen SPARX5_PIN(0), 779f8a74760SLars Povlsen SPARX5_PIN(1), 780f8a74760SLars Povlsen SPARX5_PIN(2), 781f8a74760SLars Povlsen SPARX5_PIN(3), 782f8a74760SLars Povlsen SPARX5_PIN(4), 783f8a74760SLars Povlsen SPARX5_PIN(5), 784f8a74760SLars Povlsen SPARX5_PIN(6), 785f8a74760SLars Povlsen SPARX5_PIN(7), 786f8a74760SLars Povlsen SPARX5_PIN(8), 787f8a74760SLars Povlsen SPARX5_PIN(9), 788f8a74760SLars Povlsen SPARX5_PIN(10), 789f8a74760SLars Povlsen SPARX5_PIN(11), 790f8a74760SLars Povlsen SPARX5_PIN(12), 791f8a74760SLars Povlsen SPARX5_PIN(13), 792f8a74760SLars Povlsen SPARX5_PIN(14), 793f8a74760SLars Povlsen SPARX5_PIN(15), 794f8a74760SLars Povlsen SPARX5_PIN(16), 795f8a74760SLars Povlsen SPARX5_PIN(17), 796f8a74760SLars Povlsen SPARX5_PIN(18), 797f8a74760SLars Povlsen SPARX5_PIN(19), 798f8a74760SLars Povlsen SPARX5_PIN(20), 799f8a74760SLars Povlsen SPARX5_PIN(21), 800f8a74760SLars Povlsen SPARX5_PIN(22), 801f8a74760SLars Povlsen SPARX5_PIN(23), 802f8a74760SLars Povlsen SPARX5_PIN(24), 803f8a74760SLars Povlsen SPARX5_PIN(25), 804f8a74760SLars Povlsen SPARX5_PIN(26), 805f8a74760SLars Povlsen SPARX5_PIN(27), 806f8a74760SLars Povlsen SPARX5_PIN(28), 807f8a74760SLars Povlsen SPARX5_PIN(29), 808f8a74760SLars Povlsen SPARX5_PIN(30), 809f8a74760SLars Povlsen SPARX5_PIN(31), 810f8a74760SLars Povlsen SPARX5_PIN(32), 811f8a74760SLars Povlsen SPARX5_PIN(33), 812f8a74760SLars Povlsen SPARX5_PIN(34), 813f8a74760SLars Povlsen SPARX5_PIN(35), 814f8a74760SLars Povlsen SPARX5_PIN(36), 815f8a74760SLars Povlsen SPARX5_PIN(37), 816f8a74760SLars Povlsen SPARX5_PIN(38), 817f8a74760SLars Povlsen SPARX5_PIN(39), 818f8a74760SLars Povlsen SPARX5_PIN(40), 819f8a74760SLars Povlsen SPARX5_PIN(41), 820f8a74760SLars Povlsen SPARX5_PIN(42), 821f8a74760SLars Povlsen SPARX5_PIN(43), 822f8a74760SLars Povlsen SPARX5_PIN(44), 823f8a74760SLars Povlsen SPARX5_PIN(45), 824f8a74760SLars Povlsen SPARX5_PIN(46), 825f8a74760SLars Povlsen SPARX5_PIN(47), 826f8a74760SLars Povlsen SPARX5_PIN(48), 827f8a74760SLars Povlsen SPARX5_PIN(49), 828f8a74760SLars Povlsen SPARX5_PIN(50), 829f8a74760SLars Povlsen SPARX5_PIN(51), 830f8a74760SLars Povlsen SPARX5_PIN(52), 831f8a74760SLars Povlsen SPARX5_PIN(53), 832f8a74760SLars Povlsen SPARX5_PIN(54), 833f8a74760SLars Povlsen SPARX5_PIN(55), 834f8a74760SLars Povlsen SPARX5_PIN(56), 835f8a74760SLars Povlsen SPARX5_PIN(57), 836f8a74760SLars Povlsen SPARX5_PIN(58), 837f8a74760SLars Povlsen SPARX5_PIN(59), 838f8a74760SLars Povlsen SPARX5_PIN(60), 839f8a74760SLars Povlsen SPARX5_PIN(61), 840f8a74760SLars Povlsen SPARX5_PIN(62), 841f8a74760SLars Povlsen SPARX5_PIN(63), 842f8a74760SLars Povlsen }; 843f8a74760SLars Povlsen 844*531d6ab3SKavyasree Kotagiri #define LAN966X_P(p, f0, f1, f2, f3, f4, f5, f6, f7) \ 845*531d6ab3SKavyasree Kotagiri static struct ocelot_pin_caps lan966x_pin_##p = { \ 846*531d6ab3SKavyasree Kotagiri .pin = p, \ 847*531d6ab3SKavyasree Kotagiri .functions = { \ 848*531d6ab3SKavyasree Kotagiri FUNC_##f0, FUNC_##f1, FUNC_##f2, \ 849*531d6ab3SKavyasree Kotagiri FUNC_##f3 \ 850*531d6ab3SKavyasree Kotagiri }, \ 851*531d6ab3SKavyasree Kotagiri .a_functions = { \ 852*531d6ab3SKavyasree Kotagiri FUNC_##f4, FUNC_##f5, FUNC_##f6, \ 853*531d6ab3SKavyasree Kotagiri FUNC_##f7 \ 854*531d6ab3SKavyasree Kotagiri }, \ 855*531d6ab3SKavyasree Kotagiri } 856*531d6ab3SKavyasree Kotagiri 857*531d6ab3SKavyasree Kotagiri /* Pinmuxing table taken from data sheet */ 858*531d6ab3SKavyasree Kotagiri /* Pin FUNC0 FUNC1 FUNC2 FUNC3 FUNC4 FUNC5 FUNC6 FUNC7 */ 859*531d6ab3SKavyasree Kotagiri LAN966X_P(0, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 860*531d6ab3SKavyasree Kotagiri LAN966X_P(1, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 861*531d6ab3SKavyasree Kotagiri LAN966X_P(2, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 862*531d6ab3SKavyasree Kotagiri LAN966X_P(3, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 863*531d6ab3SKavyasree Kotagiri LAN966X_P(4, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 864*531d6ab3SKavyasree Kotagiri LAN966X_P(5, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 865*531d6ab3SKavyasree Kotagiri LAN966X_P(6, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 866*531d6ab3SKavyasree Kotagiri LAN966X_P(7, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 867*531d6ab3SKavyasree Kotagiri LAN966X_P(8, GPIO, FC0_a, USB_H_b, NONE, USB_S_b, NONE, NONE, R); 868*531d6ab3SKavyasree Kotagiri LAN966X_P(9, GPIO, FC0_a, USB_H_b, NONE, NONE, NONE, NONE, R); 869*531d6ab3SKavyasree Kotagiri LAN966X_P(10, GPIO, FC0_a, NONE, NONE, NONE, NONE, NONE, R); 870*531d6ab3SKavyasree Kotagiri LAN966X_P(11, GPIO, FC1_a, NONE, NONE, NONE, NONE, NONE, R); 871*531d6ab3SKavyasree Kotagiri LAN966X_P(12, GPIO, FC1_a, NONE, NONE, NONE, NONE, NONE, R); 872*531d6ab3SKavyasree Kotagiri LAN966X_P(13, GPIO, FC1_a, NONE, NONE, NONE, NONE, NONE, R); 873*531d6ab3SKavyasree Kotagiri LAN966X_P(14, GPIO, FC2_a, NONE, NONE, NONE, NONE, NONE, R); 874*531d6ab3SKavyasree Kotagiri LAN966X_P(15, GPIO, FC2_a, NONE, NONE, NONE, NONE, NONE, R); 875*531d6ab3SKavyasree Kotagiri LAN966X_P(16, GPIO, FC2_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, IRQ_OUT_c, R); 876*531d6ab3SKavyasree Kotagiri LAN966X_P(17, GPIO, FC3_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, IRQ_OUT_c, R); 877*531d6ab3SKavyasree Kotagiri LAN966X_P(18, GPIO, FC3_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, IRQ_OUT_c, R); 878*531d6ab3SKavyasree Kotagiri LAN966X_P(19, GPIO, FC3_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, IRQ_OUT_c, R); 879*531d6ab3SKavyasree Kotagiri LAN966X_P(20, GPIO, FC4_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, NONE, R); 880*531d6ab3SKavyasree Kotagiri LAN966X_P(21, GPIO, FC4_a, NONE, NONE, OB_TRG_a, NONE, NONE, R); 881*531d6ab3SKavyasree Kotagiri LAN966X_P(22, GPIO, FC4_a, NONE, NONE, OB_TRG_a, NONE, NONE, R); 882*531d6ab3SKavyasree Kotagiri LAN966X_P(23, GPIO, NONE, NONE, NONE, OB_TRG_a, NONE, NONE, R); 883*531d6ab3SKavyasree Kotagiri LAN966X_P(24, GPIO, FC0_b, IB_TRG_a, USB_H_c, OB_TRG_a, IRQ_IN_c, TACHO_a, R); 884*531d6ab3SKavyasree Kotagiri LAN966X_P(25, GPIO, FC0_b, IB_TRG_a, USB_H_c, OB_TRG_a, IRQ_OUT_c, SFP_SD, R); 885*531d6ab3SKavyasree Kotagiri LAN966X_P(26, GPIO, FC0_b, IB_TRG_a, USB_S_c, OB_TRG_a, CAN0_a, SFP_SD, R); 886*531d6ab3SKavyasree Kotagiri LAN966X_P(27, GPIO, NONE, NONE, NONE, OB_TRG_a, CAN0_a, NONE, R); 887*531d6ab3SKavyasree Kotagiri LAN966X_P(28, GPIO, MIIM_a, NONE, NONE, OB_TRG_a, IRQ_OUT_c, SFP_SD, R); 888*531d6ab3SKavyasree Kotagiri LAN966X_P(29, GPIO, MIIM_a, NONE, NONE, OB_TRG_a, NONE, NONE, R); 889*531d6ab3SKavyasree Kotagiri LAN966X_P(30, GPIO, FC3_c, CAN1, NONE, OB_TRG, RECO_b, NONE, R); 890*531d6ab3SKavyasree Kotagiri LAN966X_P(31, GPIO, FC3_c, CAN1, NONE, OB_TRG, RECO_b, NONE, R); 891*531d6ab3SKavyasree Kotagiri LAN966X_P(32, GPIO, FC3_c, NONE, SGPIO_a, NONE, MIIM_Sa, NONE, R); 892*531d6ab3SKavyasree Kotagiri LAN966X_P(33, GPIO, FC1_b, NONE, SGPIO_a, NONE, MIIM_Sa, MIIM_b, R); 893*531d6ab3SKavyasree Kotagiri LAN966X_P(34, GPIO, FC1_b, NONE, SGPIO_a, NONE, MIIM_Sa, MIIM_b, R); 894*531d6ab3SKavyasree Kotagiri LAN966X_P(35, GPIO, FC1_b, NONE, SGPIO_a, CAN0_b, NONE, NONE, R); 895*531d6ab3SKavyasree Kotagiri LAN966X_P(36, GPIO, NONE, PTPSYNC_1, NONE, CAN0_b, NONE, NONE, R); 896*531d6ab3SKavyasree Kotagiri LAN966X_P(37, GPIO, FC_SHRD0, PTPSYNC_2, TWI_SLC_GATE_AD, NONE, NONE, NONE, R); 897*531d6ab3SKavyasree Kotagiri LAN966X_P(38, GPIO, NONE, PTPSYNC_3, NONE, NONE, NONE, NONE, R); 898*531d6ab3SKavyasree Kotagiri LAN966X_P(39, GPIO, NONE, PTPSYNC_4, NONE, NONE, NONE, NONE, R); 899*531d6ab3SKavyasree Kotagiri LAN966X_P(40, GPIO, FC_SHRD1, PTPSYNC_5, NONE, NONE, NONE, NONE, R); 900*531d6ab3SKavyasree Kotagiri LAN966X_P(41, GPIO, FC_SHRD2, PTPSYNC_6, TWI_SLC_GATE_AD, NONE, NONE, NONE, R); 901*531d6ab3SKavyasree Kotagiri LAN966X_P(42, GPIO, FC_SHRD3, PTPSYNC_7, TWI_SLC_GATE_AD, NONE, NONE, NONE, R); 902*531d6ab3SKavyasree Kotagiri LAN966X_P(43, GPIO, FC2_b, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, RECO_a, IRQ_IN_a, R); 903*531d6ab3SKavyasree Kotagiri LAN966X_P(44, GPIO, FC2_b, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, RECO_a, IRQ_IN_a, R); 904*531d6ab3SKavyasree Kotagiri LAN966X_P(45, GPIO, FC2_b, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, NONE, IRQ_IN_a, R); 905*531d6ab3SKavyasree Kotagiri LAN966X_P(46, GPIO, FC1_c, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, FC_SHRD4, IRQ_IN_a, R); 906*531d6ab3SKavyasree Kotagiri LAN966X_P(47, GPIO, FC1_c, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, FC_SHRD5, IRQ_IN_a, R); 907*531d6ab3SKavyasree Kotagiri LAN966X_P(48, GPIO, FC1_c, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, FC_SHRD6, IRQ_IN_a, R); 908*531d6ab3SKavyasree Kotagiri LAN966X_P(49, GPIO, FC_SHRD7, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, TWI_SLC_GATE, IRQ_IN_a, R); 909*531d6ab3SKavyasree Kotagiri LAN966X_P(50, GPIO, FC_SHRD16, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, TWI_SLC_GATE, NONE, R); 910*531d6ab3SKavyasree Kotagiri LAN966X_P(51, GPIO, FC3_b, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, NONE, IRQ_IN_b, R); 911*531d6ab3SKavyasree Kotagiri LAN966X_P(52, GPIO, FC3_b, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, TACHO_b, IRQ_IN_b, R); 912*531d6ab3SKavyasree Kotagiri LAN966X_P(53, GPIO, FC3_b, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, NONE, IRQ_IN_b, R); 913*531d6ab3SKavyasree Kotagiri LAN966X_P(54, GPIO, FC_SHRD8, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, TWI_SLC_GATE, IRQ_IN_b, R); 914*531d6ab3SKavyasree Kotagiri LAN966X_P(55, GPIO, FC_SHRD9, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, TWI_SLC_GATE, IRQ_IN_b, R); 915*531d6ab3SKavyasree Kotagiri LAN966X_P(56, GPIO, FC4_b, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, FC_SHRD10, IRQ_IN_b, R); 916*531d6ab3SKavyasree Kotagiri LAN966X_P(57, GPIO, FC4_b, TWI_SLC_GATE, IB_TRG_c, IRQ_OUT_b, FC_SHRD11, IRQ_IN_b, R); 917*531d6ab3SKavyasree Kotagiri LAN966X_P(58, GPIO, FC4_b, TWI_SLC_GATE, IB_TRG_c, IRQ_OUT_b, FC_SHRD12, IRQ_IN_b, R); 918*531d6ab3SKavyasree Kotagiri LAN966X_P(59, GPIO, QSPI1, MIIM_c, NONE, NONE, MIIM_Sb, NONE, R); 919*531d6ab3SKavyasree Kotagiri LAN966X_P(60, GPIO, QSPI1, MIIM_c, NONE, NONE, MIIM_Sb, NONE, R); 920*531d6ab3SKavyasree Kotagiri LAN966X_P(61, GPIO, QSPI1, NONE, SGPIO_b, FC0_c, MIIM_Sb, NONE, R); 921*531d6ab3SKavyasree Kotagiri LAN966X_P(62, GPIO, QSPI1, FC_SHRD13, SGPIO_b, FC0_c, TWI_SLC_GATE, SFP_SD, R); 922*531d6ab3SKavyasree Kotagiri LAN966X_P(63, GPIO, QSPI1, FC_SHRD14, SGPIO_b, FC0_c, TWI_SLC_GATE, SFP_SD, R); 923*531d6ab3SKavyasree Kotagiri LAN966X_P(64, GPIO, QSPI1, FC4_c, SGPIO_b, FC_SHRD15, TWI_SLC_GATE, SFP_SD, R); 924*531d6ab3SKavyasree Kotagiri LAN966X_P(65, GPIO, USB_H_a, FC4_c, NONE, IRQ_OUT_c, TWI_SLC_GATE_AD, NONE, R); 925*531d6ab3SKavyasree Kotagiri LAN966X_P(66, GPIO, USB_H_a, FC4_c, USB_S_a, IRQ_OUT_c, IRQ_IN_c, NONE, R); 926*531d6ab3SKavyasree Kotagiri LAN966X_P(67, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R); 927*531d6ab3SKavyasree Kotagiri LAN966X_P(68, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R); 928*531d6ab3SKavyasree Kotagiri LAN966X_P(69, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R); 929*531d6ab3SKavyasree Kotagiri LAN966X_P(70, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R); 930*531d6ab3SKavyasree Kotagiri LAN966X_P(71, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R); 931*531d6ab3SKavyasree Kotagiri LAN966X_P(72, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R); 932*531d6ab3SKavyasree Kotagiri LAN966X_P(73, GPIO, EMMC, NONE, NONE, SD, NONE, NONE, R); 933*531d6ab3SKavyasree Kotagiri LAN966X_P(74, GPIO, EMMC, NONE, FC_SHRD17, SD, TWI_SLC_GATE, NONE, R); 934*531d6ab3SKavyasree Kotagiri LAN966X_P(75, GPIO, EMMC, NONE, FC_SHRD18, SD, TWI_SLC_GATE, NONE, R); 935*531d6ab3SKavyasree Kotagiri LAN966X_P(76, GPIO, EMMC, NONE, FC_SHRD19, SD, TWI_SLC_GATE, NONE, R); 936*531d6ab3SKavyasree Kotagiri LAN966X_P(77, GPIO, EMMC_SD, NONE, FC_SHRD20, NONE, TWI_SLC_GATE, NONE, R); 937*531d6ab3SKavyasree Kotagiri 938*531d6ab3SKavyasree Kotagiri #define LAN966X_PIN(n) { \ 939*531d6ab3SKavyasree Kotagiri .number = n, \ 940*531d6ab3SKavyasree Kotagiri .name = "GPIO_"#n, \ 941*531d6ab3SKavyasree Kotagiri .drv_data = &lan966x_pin_##n \ 942*531d6ab3SKavyasree Kotagiri } 943*531d6ab3SKavyasree Kotagiri 944*531d6ab3SKavyasree Kotagiri static const struct pinctrl_pin_desc lan966x_pins[] = { 945*531d6ab3SKavyasree Kotagiri LAN966X_PIN(0), 946*531d6ab3SKavyasree Kotagiri LAN966X_PIN(1), 947*531d6ab3SKavyasree Kotagiri LAN966X_PIN(2), 948*531d6ab3SKavyasree Kotagiri LAN966X_PIN(3), 949*531d6ab3SKavyasree Kotagiri LAN966X_PIN(4), 950*531d6ab3SKavyasree Kotagiri LAN966X_PIN(5), 951*531d6ab3SKavyasree Kotagiri LAN966X_PIN(6), 952*531d6ab3SKavyasree Kotagiri LAN966X_PIN(7), 953*531d6ab3SKavyasree Kotagiri LAN966X_PIN(8), 954*531d6ab3SKavyasree Kotagiri LAN966X_PIN(9), 955*531d6ab3SKavyasree Kotagiri LAN966X_PIN(10), 956*531d6ab3SKavyasree Kotagiri LAN966X_PIN(11), 957*531d6ab3SKavyasree Kotagiri LAN966X_PIN(12), 958*531d6ab3SKavyasree Kotagiri LAN966X_PIN(13), 959*531d6ab3SKavyasree Kotagiri LAN966X_PIN(14), 960*531d6ab3SKavyasree Kotagiri LAN966X_PIN(15), 961*531d6ab3SKavyasree Kotagiri LAN966X_PIN(16), 962*531d6ab3SKavyasree Kotagiri LAN966X_PIN(17), 963*531d6ab3SKavyasree Kotagiri LAN966X_PIN(18), 964*531d6ab3SKavyasree Kotagiri LAN966X_PIN(19), 965*531d6ab3SKavyasree Kotagiri LAN966X_PIN(20), 966*531d6ab3SKavyasree Kotagiri LAN966X_PIN(21), 967*531d6ab3SKavyasree Kotagiri LAN966X_PIN(22), 968*531d6ab3SKavyasree Kotagiri LAN966X_PIN(23), 969*531d6ab3SKavyasree Kotagiri LAN966X_PIN(24), 970*531d6ab3SKavyasree Kotagiri LAN966X_PIN(25), 971*531d6ab3SKavyasree Kotagiri LAN966X_PIN(26), 972*531d6ab3SKavyasree Kotagiri LAN966X_PIN(27), 973*531d6ab3SKavyasree Kotagiri LAN966X_PIN(28), 974*531d6ab3SKavyasree Kotagiri LAN966X_PIN(29), 975*531d6ab3SKavyasree Kotagiri LAN966X_PIN(30), 976*531d6ab3SKavyasree Kotagiri LAN966X_PIN(31), 977*531d6ab3SKavyasree Kotagiri LAN966X_PIN(32), 978*531d6ab3SKavyasree Kotagiri LAN966X_PIN(33), 979*531d6ab3SKavyasree Kotagiri LAN966X_PIN(34), 980*531d6ab3SKavyasree Kotagiri LAN966X_PIN(35), 981*531d6ab3SKavyasree Kotagiri LAN966X_PIN(36), 982*531d6ab3SKavyasree Kotagiri LAN966X_PIN(37), 983*531d6ab3SKavyasree Kotagiri LAN966X_PIN(38), 984*531d6ab3SKavyasree Kotagiri LAN966X_PIN(39), 985*531d6ab3SKavyasree Kotagiri LAN966X_PIN(40), 986*531d6ab3SKavyasree Kotagiri LAN966X_PIN(41), 987*531d6ab3SKavyasree Kotagiri LAN966X_PIN(42), 988*531d6ab3SKavyasree Kotagiri LAN966X_PIN(43), 989*531d6ab3SKavyasree Kotagiri LAN966X_PIN(44), 990*531d6ab3SKavyasree Kotagiri LAN966X_PIN(45), 991*531d6ab3SKavyasree Kotagiri LAN966X_PIN(46), 992*531d6ab3SKavyasree Kotagiri LAN966X_PIN(47), 993*531d6ab3SKavyasree Kotagiri LAN966X_PIN(48), 994*531d6ab3SKavyasree Kotagiri LAN966X_PIN(49), 995*531d6ab3SKavyasree Kotagiri LAN966X_PIN(50), 996*531d6ab3SKavyasree Kotagiri LAN966X_PIN(51), 997*531d6ab3SKavyasree Kotagiri LAN966X_PIN(52), 998*531d6ab3SKavyasree Kotagiri LAN966X_PIN(53), 999*531d6ab3SKavyasree Kotagiri LAN966X_PIN(54), 1000*531d6ab3SKavyasree Kotagiri LAN966X_PIN(55), 1001*531d6ab3SKavyasree Kotagiri LAN966X_PIN(56), 1002*531d6ab3SKavyasree Kotagiri LAN966X_PIN(57), 1003*531d6ab3SKavyasree Kotagiri LAN966X_PIN(58), 1004*531d6ab3SKavyasree Kotagiri LAN966X_PIN(59), 1005*531d6ab3SKavyasree Kotagiri LAN966X_PIN(60), 1006*531d6ab3SKavyasree Kotagiri LAN966X_PIN(61), 1007*531d6ab3SKavyasree Kotagiri LAN966X_PIN(62), 1008*531d6ab3SKavyasree Kotagiri LAN966X_PIN(63), 1009*531d6ab3SKavyasree Kotagiri LAN966X_PIN(64), 1010*531d6ab3SKavyasree Kotagiri LAN966X_PIN(65), 1011*531d6ab3SKavyasree Kotagiri LAN966X_PIN(66), 1012*531d6ab3SKavyasree Kotagiri LAN966X_PIN(67), 1013*531d6ab3SKavyasree Kotagiri LAN966X_PIN(68), 1014*531d6ab3SKavyasree Kotagiri LAN966X_PIN(69), 1015*531d6ab3SKavyasree Kotagiri LAN966X_PIN(70), 1016*531d6ab3SKavyasree Kotagiri LAN966X_PIN(71), 1017*531d6ab3SKavyasree Kotagiri LAN966X_PIN(72), 1018*531d6ab3SKavyasree Kotagiri LAN966X_PIN(73), 1019*531d6ab3SKavyasree Kotagiri LAN966X_PIN(74), 1020*531d6ab3SKavyasree Kotagiri LAN966X_PIN(75), 1021*531d6ab3SKavyasree Kotagiri LAN966X_PIN(76), 1022*531d6ab3SKavyasree Kotagiri LAN966X_PIN(77), 1023*531d6ab3SKavyasree Kotagiri }; 1024*531d6ab3SKavyasree Kotagiri 1025ce8dc094SAlexandre Belloni static int ocelot_get_functions_count(struct pinctrl_dev *pctldev) 1026ce8dc094SAlexandre Belloni { 1027ce8dc094SAlexandre Belloni return ARRAY_SIZE(ocelot_function_names); 1028ce8dc094SAlexandre Belloni } 1029ce8dc094SAlexandre Belloni 1030ce8dc094SAlexandre Belloni static const char *ocelot_get_function_name(struct pinctrl_dev *pctldev, 1031ce8dc094SAlexandre Belloni unsigned int function) 1032ce8dc094SAlexandre Belloni { 1033ce8dc094SAlexandre Belloni return ocelot_function_names[function]; 1034ce8dc094SAlexandre Belloni } 1035ce8dc094SAlexandre Belloni 1036ce8dc094SAlexandre Belloni static int ocelot_get_function_groups(struct pinctrl_dev *pctldev, 1037ce8dc094SAlexandre Belloni unsigned int function, 1038ce8dc094SAlexandre Belloni const char *const **groups, 1039ce8dc094SAlexandre Belloni unsigned *const num_groups) 1040ce8dc094SAlexandre Belloni { 1041ce8dc094SAlexandre Belloni struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1042ce8dc094SAlexandre Belloni 1043ce8dc094SAlexandre Belloni *groups = info->func[function].groups; 1044ce8dc094SAlexandre Belloni *num_groups = info->func[function].ngroups; 1045ce8dc094SAlexandre Belloni 1046ce8dc094SAlexandre Belloni return 0; 1047ce8dc094SAlexandre Belloni } 1048ce8dc094SAlexandre Belloni 1049da801ab5SAlexandre Belloni static int ocelot_pin_function_idx(struct ocelot_pinctrl *info, 1050da801ab5SAlexandre Belloni unsigned int pin, unsigned int function) 1051ce8dc094SAlexandre Belloni { 1052da801ab5SAlexandre Belloni struct ocelot_pin_caps *p = info->desc->pins[pin].drv_data; 1053ce8dc094SAlexandre Belloni int i; 1054ce8dc094SAlexandre Belloni 1055ce8dc094SAlexandre Belloni for (i = 0; i < OCELOT_FUNC_PER_PIN; i++) { 1056ce8dc094SAlexandre Belloni if (function == p->functions[i]) 1057ce8dc094SAlexandre Belloni return i; 1058*531d6ab3SKavyasree Kotagiri 1059*531d6ab3SKavyasree Kotagiri if (function == p->a_functions[i]) 1060*531d6ab3SKavyasree Kotagiri return i + OCELOT_FUNC_PER_PIN; 1061ce8dc094SAlexandre Belloni } 1062ce8dc094SAlexandre Belloni 1063ce8dc094SAlexandre Belloni return -1; 1064ce8dc094SAlexandre Belloni } 1065ce8dc094SAlexandre Belloni 10664b36082eSAlexandre Belloni #define REG_ALT(msb, info, p) (OCELOT_GPIO_ALT0 * (info)->stride + 4 * ((msb) + ((info)->stride * ((p) / 32)))) 1067da801ab5SAlexandre Belloni 1068ce8dc094SAlexandre Belloni static int ocelot_pinmux_set_mux(struct pinctrl_dev *pctldev, 1069ce8dc094SAlexandre Belloni unsigned int selector, unsigned int group) 1070ce8dc094SAlexandre Belloni { 1071ce8dc094SAlexandre Belloni struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1072da801ab5SAlexandre Belloni struct ocelot_pin_caps *pin = info->desc->pins[group].drv_data; 1073da801ab5SAlexandre Belloni unsigned int p = pin->pin % 32; 1074ce8dc094SAlexandre Belloni int f; 1075ce8dc094SAlexandre Belloni 1076da801ab5SAlexandre Belloni f = ocelot_pin_function_idx(info, group, selector); 1077ce8dc094SAlexandre Belloni if (f < 0) 1078ce8dc094SAlexandre Belloni return -EINVAL; 1079ce8dc094SAlexandre Belloni 1080ce8dc094SAlexandre Belloni /* 1081ce8dc094SAlexandre Belloni * f is encoded on two bits. 10824b36082eSAlexandre Belloni * bit 0 of f goes in BIT(pin) of ALT[0], bit 1 of f goes in BIT(pin) of 10834b36082eSAlexandre Belloni * ALT[1] 1084ce8dc094SAlexandre Belloni * This is racy because both registers can't be updated at the same time 1085ce8dc094SAlexandre Belloni * but it doesn't matter much for now. 1086f8a74760SLars Povlsen * Note: ALT0/ALT1 are organized specially for 64 gpio targets 1087ce8dc094SAlexandre Belloni */ 10884b36082eSAlexandre Belloni regmap_update_bits(info->map, REG_ALT(0, info, pin->pin), 1089da801ab5SAlexandre Belloni BIT(p), f << p); 10904b36082eSAlexandre Belloni regmap_update_bits(info->map, REG_ALT(1, info, pin->pin), 1091da801ab5SAlexandre Belloni BIT(p), f << (p - 1)); 1092ce8dc094SAlexandre Belloni 1093ce8dc094SAlexandre Belloni return 0; 1094ce8dc094SAlexandre Belloni } 1095ce8dc094SAlexandre Belloni 1096*531d6ab3SKavyasree Kotagiri static int lan966x_pinmux_set_mux(struct pinctrl_dev *pctldev, 1097*531d6ab3SKavyasree Kotagiri unsigned int selector, unsigned int group) 1098*531d6ab3SKavyasree Kotagiri { 1099*531d6ab3SKavyasree Kotagiri struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1100*531d6ab3SKavyasree Kotagiri struct ocelot_pin_caps *pin = info->desc->pins[group].drv_data; 1101*531d6ab3SKavyasree Kotagiri unsigned int p = pin->pin % 32; 1102*531d6ab3SKavyasree Kotagiri int f; 1103*531d6ab3SKavyasree Kotagiri 1104*531d6ab3SKavyasree Kotagiri f = ocelot_pin_function_idx(info, group, selector); 1105*531d6ab3SKavyasree Kotagiri if (f < 0) 1106*531d6ab3SKavyasree Kotagiri return -EINVAL; 1107*531d6ab3SKavyasree Kotagiri 1108*531d6ab3SKavyasree Kotagiri /* 1109*531d6ab3SKavyasree Kotagiri * f is encoded on three bits. 1110*531d6ab3SKavyasree Kotagiri * bit 0 of f goes in BIT(pin) of ALT[0], bit 1 of f goes in BIT(pin) of 1111*531d6ab3SKavyasree Kotagiri * ALT[1], bit 2 of f goes in BIT(pin) of ALT[2] 1112*531d6ab3SKavyasree Kotagiri * This is racy because three registers can't be updated at the same time 1113*531d6ab3SKavyasree Kotagiri * but it doesn't matter much for now. 1114*531d6ab3SKavyasree Kotagiri * Note: ALT0/ALT1/ALT2 are organized specially for 78 gpio targets 1115*531d6ab3SKavyasree Kotagiri */ 1116*531d6ab3SKavyasree Kotagiri regmap_update_bits(info->map, REG_ALT(0, info, pin->pin), 1117*531d6ab3SKavyasree Kotagiri BIT(p), f << p); 1118*531d6ab3SKavyasree Kotagiri regmap_update_bits(info->map, REG_ALT(1, info, pin->pin), 1119*531d6ab3SKavyasree Kotagiri BIT(p), (f >> 1) << p); 1120*531d6ab3SKavyasree Kotagiri regmap_update_bits(info->map, REG_ALT(2, info, pin->pin), 1121*531d6ab3SKavyasree Kotagiri BIT(p), (f >> 2) << p); 1122*531d6ab3SKavyasree Kotagiri 1123*531d6ab3SKavyasree Kotagiri return 0; 1124*531d6ab3SKavyasree Kotagiri } 1125*531d6ab3SKavyasree Kotagiri 11264b36082eSAlexandre Belloni #define REG(r, info, p) ((r) * (info)->stride + (4 * ((p) / 32))) 11274b36082eSAlexandre Belloni 1128ce8dc094SAlexandre Belloni static int ocelot_gpio_set_direction(struct pinctrl_dev *pctldev, 1129ce8dc094SAlexandre Belloni struct pinctrl_gpio_range *range, 1130ce8dc094SAlexandre Belloni unsigned int pin, bool input) 1131ce8dc094SAlexandre Belloni { 1132ce8dc094SAlexandre Belloni struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1133da801ab5SAlexandre Belloni unsigned int p = pin % 32; 1134ce8dc094SAlexandre Belloni 1135f2818ba3SAlexandre Belloni regmap_update_bits(info->map, REG(OCELOT_GPIO_OE, info, pin), BIT(p), 1136da801ab5SAlexandre Belloni input ? 0 : BIT(p)); 1137ce8dc094SAlexandre Belloni 1138ce8dc094SAlexandre Belloni return 0; 1139ce8dc094SAlexandre Belloni } 1140ce8dc094SAlexandre Belloni 1141ce8dc094SAlexandre Belloni static int ocelot_gpio_request_enable(struct pinctrl_dev *pctldev, 1142ce8dc094SAlexandre Belloni struct pinctrl_gpio_range *range, 1143ce8dc094SAlexandre Belloni unsigned int offset) 1144ce8dc094SAlexandre Belloni { 1145ce8dc094SAlexandre Belloni struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1146da801ab5SAlexandre Belloni unsigned int p = offset % 32; 1147ce8dc094SAlexandre Belloni 11484b36082eSAlexandre Belloni regmap_update_bits(info->map, REG_ALT(0, info, offset), 1149da801ab5SAlexandre Belloni BIT(p), 0); 11504b36082eSAlexandre Belloni regmap_update_bits(info->map, REG_ALT(1, info, offset), 1151da801ab5SAlexandre Belloni BIT(p), 0); 1152ce8dc094SAlexandre Belloni 1153ce8dc094SAlexandre Belloni return 0; 1154ce8dc094SAlexandre Belloni } 1155ce8dc094SAlexandre Belloni 1156*531d6ab3SKavyasree Kotagiri static int lan966x_gpio_request_enable(struct pinctrl_dev *pctldev, 1157*531d6ab3SKavyasree Kotagiri struct pinctrl_gpio_range *range, 1158*531d6ab3SKavyasree Kotagiri unsigned int offset) 1159*531d6ab3SKavyasree Kotagiri { 1160*531d6ab3SKavyasree Kotagiri struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1161*531d6ab3SKavyasree Kotagiri unsigned int p = offset % 32; 1162*531d6ab3SKavyasree Kotagiri 1163*531d6ab3SKavyasree Kotagiri regmap_update_bits(info->map, REG_ALT(0, info, offset), 1164*531d6ab3SKavyasree Kotagiri BIT(p), 0); 1165*531d6ab3SKavyasree Kotagiri regmap_update_bits(info->map, REG_ALT(1, info, offset), 1166*531d6ab3SKavyasree Kotagiri BIT(p), 0); 1167*531d6ab3SKavyasree Kotagiri regmap_update_bits(info->map, REG_ALT(2, info, offset), 1168*531d6ab3SKavyasree Kotagiri BIT(p), 0); 1169*531d6ab3SKavyasree Kotagiri 1170*531d6ab3SKavyasree Kotagiri return 0; 1171*531d6ab3SKavyasree Kotagiri } 1172*531d6ab3SKavyasree Kotagiri 1173ce8dc094SAlexandre Belloni static const struct pinmux_ops ocelot_pmx_ops = { 1174ce8dc094SAlexandre Belloni .get_functions_count = ocelot_get_functions_count, 1175ce8dc094SAlexandre Belloni .get_function_name = ocelot_get_function_name, 1176ce8dc094SAlexandre Belloni .get_function_groups = ocelot_get_function_groups, 1177ce8dc094SAlexandre Belloni .set_mux = ocelot_pinmux_set_mux, 1178ce8dc094SAlexandre Belloni .gpio_set_direction = ocelot_gpio_set_direction, 1179ce8dc094SAlexandre Belloni .gpio_request_enable = ocelot_gpio_request_enable, 1180ce8dc094SAlexandre Belloni }; 1181ce8dc094SAlexandre Belloni 1182*531d6ab3SKavyasree Kotagiri static const struct pinmux_ops lan966x_pmx_ops = { 1183*531d6ab3SKavyasree Kotagiri .get_functions_count = ocelot_get_functions_count, 1184*531d6ab3SKavyasree Kotagiri .get_function_name = ocelot_get_function_name, 1185*531d6ab3SKavyasree Kotagiri .get_function_groups = ocelot_get_function_groups, 1186*531d6ab3SKavyasree Kotagiri .set_mux = lan966x_pinmux_set_mux, 1187*531d6ab3SKavyasree Kotagiri .gpio_set_direction = ocelot_gpio_set_direction, 1188*531d6ab3SKavyasree Kotagiri .gpio_request_enable = lan966x_gpio_request_enable, 1189*531d6ab3SKavyasree Kotagiri }; 1190*531d6ab3SKavyasree Kotagiri 1191ce8dc094SAlexandre Belloni static int ocelot_pctl_get_groups_count(struct pinctrl_dev *pctldev) 1192ce8dc094SAlexandre Belloni { 1193da801ab5SAlexandre Belloni struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1194da801ab5SAlexandre Belloni 1195da801ab5SAlexandre Belloni return info->desc->npins; 1196ce8dc094SAlexandre Belloni } 1197ce8dc094SAlexandre Belloni 1198ce8dc094SAlexandre Belloni static const char *ocelot_pctl_get_group_name(struct pinctrl_dev *pctldev, 1199ce8dc094SAlexandre Belloni unsigned int group) 1200ce8dc094SAlexandre Belloni { 1201da801ab5SAlexandre Belloni struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1202da801ab5SAlexandre Belloni 1203da801ab5SAlexandre Belloni return info->desc->pins[group].name; 1204ce8dc094SAlexandre Belloni } 1205ce8dc094SAlexandre Belloni 1206ce8dc094SAlexandre Belloni static int ocelot_pctl_get_group_pins(struct pinctrl_dev *pctldev, 1207ce8dc094SAlexandre Belloni unsigned int group, 1208ce8dc094SAlexandre Belloni const unsigned int **pins, 1209ce8dc094SAlexandre Belloni unsigned int *num_pins) 1210ce8dc094SAlexandre Belloni { 1211da801ab5SAlexandre Belloni struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1212da801ab5SAlexandre Belloni 1213da801ab5SAlexandre Belloni *pins = &info->desc->pins[group].number; 1214ce8dc094SAlexandre Belloni *num_pins = 1; 1215ce8dc094SAlexandre Belloni 1216ce8dc094SAlexandre Belloni return 0; 1217ce8dc094SAlexandre Belloni } 1218ce8dc094SAlexandre Belloni 1219f8a74760SLars Povlsen static int ocelot_hw_get_value(struct ocelot_pinctrl *info, 1220f8a74760SLars Povlsen unsigned int pin, 1221f8a74760SLars Povlsen unsigned int reg, 1222f8a74760SLars Povlsen int *val) 1223f8a74760SLars Povlsen { 1224f8a74760SLars Povlsen int ret = -EOPNOTSUPP; 1225f8a74760SLars Povlsen 1226f8a74760SLars Povlsen if (info->pincfg) { 1227f8a74760SLars Povlsen u32 regcfg = readl(info->pincfg + (pin * sizeof(u32))); 1228f8a74760SLars Povlsen 1229f8a74760SLars Povlsen ret = 0; 1230f8a74760SLars Povlsen switch (reg) { 1231f8a74760SLars Povlsen case PINCONF_BIAS: 1232f8a74760SLars Povlsen *val = regcfg & BIAS_BITS; 1233f8a74760SLars Povlsen break; 1234f8a74760SLars Povlsen 1235f8a74760SLars Povlsen case PINCONF_SCHMITT: 1236f8a74760SLars Povlsen *val = regcfg & SCHMITT_BIT; 1237f8a74760SLars Povlsen break; 1238f8a74760SLars Povlsen 1239f8a74760SLars Povlsen case PINCONF_DRIVE_STRENGTH: 1240f8a74760SLars Povlsen *val = regcfg & DRIVE_BITS; 1241f8a74760SLars Povlsen break; 1242f8a74760SLars Povlsen 1243f8a74760SLars Povlsen default: 1244f8a74760SLars Povlsen ret = -EOPNOTSUPP; 1245f8a74760SLars Povlsen break; 1246f8a74760SLars Povlsen } 1247f8a74760SLars Povlsen } 1248f8a74760SLars Povlsen return ret; 1249f8a74760SLars Povlsen } 1250f8a74760SLars Povlsen 1251f8a74760SLars Povlsen static int ocelot_hw_set_value(struct ocelot_pinctrl *info, 1252f8a74760SLars Povlsen unsigned int pin, 1253f8a74760SLars Povlsen unsigned int reg, 1254f8a74760SLars Povlsen int val) 1255f8a74760SLars Povlsen { 1256f8a74760SLars Povlsen int ret = -EOPNOTSUPP; 1257f8a74760SLars Povlsen 1258f8a74760SLars Povlsen if (info->pincfg) { 1259f8a74760SLars Povlsen void __iomem *regaddr = info->pincfg + (pin * sizeof(u32)); 1260f8a74760SLars Povlsen 1261f8a74760SLars Povlsen ret = 0; 1262f8a74760SLars Povlsen switch (reg) { 1263f8a74760SLars Povlsen case PINCONF_BIAS: 1264f8a74760SLars Povlsen ocelot_clrsetbits(regaddr, BIAS_BITS, val); 1265f8a74760SLars Povlsen break; 1266f8a74760SLars Povlsen 1267f8a74760SLars Povlsen case PINCONF_SCHMITT: 1268f8a74760SLars Povlsen ocelot_clrsetbits(regaddr, SCHMITT_BIT, val); 1269f8a74760SLars Povlsen break; 1270f8a74760SLars Povlsen 1271f8a74760SLars Povlsen case PINCONF_DRIVE_STRENGTH: 1272f8a74760SLars Povlsen if (val <= 3) 1273f8a74760SLars Povlsen ocelot_clrsetbits(regaddr, DRIVE_BITS, val); 1274f8a74760SLars Povlsen else 1275f8a74760SLars Povlsen ret = -EINVAL; 1276f8a74760SLars Povlsen break; 1277f8a74760SLars Povlsen 1278f8a74760SLars Povlsen default: 1279f8a74760SLars Povlsen ret = -EOPNOTSUPP; 1280f8a74760SLars Povlsen break; 1281f8a74760SLars Povlsen } 1282f8a74760SLars Povlsen } 1283f8a74760SLars Povlsen return ret; 1284f8a74760SLars Povlsen } 1285f8a74760SLars Povlsen 1286f8a74760SLars Povlsen static int ocelot_pinconf_get(struct pinctrl_dev *pctldev, 1287f8a74760SLars Povlsen unsigned int pin, unsigned long *config) 1288f8a74760SLars Povlsen { 1289f8a74760SLars Povlsen struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1290f8a74760SLars Povlsen u32 param = pinconf_to_config_param(*config); 1291f8a74760SLars Povlsen int val, err; 1292f8a74760SLars Povlsen 1293f8a74760SLars Povlsen switch (param) { 1294f8a74760SLars Povlsen case PIN_CONFIG_BIAS_DISABLE: 1295f8a74760SLars Povlsen case PIN_CONFIG_BIAS_PULL_UP: 1296f8a74760SLars Povlsen case PIN_CONFIG_BIAS_PULL_DOWN: 1297f8a74760SLars Povlsen err = ocelot_hw_get_value(info, pin, PINCONF_BIAS, &val); 1298f8a74760SLars Povlsen if (err) 1299f8a74760SLars Povlsen return err; 1300f8a74760SLars Povlsen if (param == PIN_CONFIG_BIAS_DISABLE) 130154515257SKaixu Xia val = (val == 0); 1302f8a74760SLars Povlsen else if (param == PIN_CONFIG_BIAS_PULL_DOWN) 1303f8a74760SLars Povlsen val = (val & BIAS_PD_BIT ? true : false); 1304f8a74760SLars Povlsen else /* PIN_CONFIG_BIAS_PULL_UP */ 1305f8a74760SLars Povlsen val = (val & BIAS_PU_BIT ? true : false); 1306f8a74760SLars Povlsen break; 1307f8a74760SLars Povlsen 1308f8a74760SLars Povlsen case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 1309f8a74760SLars Povlsen err = ocelot_hw_get_value(info, pin, PINCONF_SCHMITT, &val); 1310f8a74760SLars Povlsen if (err) 1311f8a74760SLars Povlsen return err; 1312f8a74760SLars Povlsen 1313f8a74760SLars Povlsen val = (val & SCHMITT_BIT ? true : false); 1314f8a74760SLars Povlsen break; 1315f8a74760SLars Povlsen 1316f8a74760SLars Povlsen case PIN_CONFIG_DRIVE_STRENGTH: 1317f8a74760SLars Povlsen err = ocelot_hw_get_value(info, pin, PINCONF_DRIVE_STRENGTH, 1318f8a74760SLars Povlsen &val); 1319f8a74760SLars Povlsen if (err) 1320f8a74760SLars Povlsen return err; 1321f8a74760SLars Povlsen break; 1322f8a74760SLars Povlsen 1323f8a74760SLars Povlsen case PIN_CONFIG_OUTPUT: 1324f8a74760SLars Povlsen err = regmap_read(info->map, REG(OCELOT_GPIO_OUT, info, pin), 1325f8a74760SLars Povlsen &val); 1326f8a74760SLars Povlsen if (err) 1327f8a74760SLars Povlsen return err; 1328f8a74760SLars Povlsen val = !!(val & BIT(pin % 32)); 1329f8a74760SLars Povlsen break; 1330f8a74760SLars Povlsen 1331f8a74760SLars Povlsen case PIN_CONFIG_INPUT_ENABLE: 1332f8a74760SLars Povlsen case PIN_CONFIG_OUTPUT_ENABLE: 1333f8a74760SLars Povlsen err = regmap_read(info->map, REG(OCELOT_GPIO_OE, info, pin), 1334f8a74760SLars Povlsen &val); 1335f8a74760SLars Povlsen if (err) 1336f8a74760SLars Povlsen return err; 1337f8a74760SLars Povlsen val = val & BIT(pin % 32); 1338f8a74760SLars Povlsen if (param == PIN_CONFIG_OUTPUT_ENABLE) 1339f8a74760SLars Povlsen val = !!val; 1340f8a74760SLars Povlsen else 1341f8a74760SLars Povlsen val = !val; 1342f8a74760SLars Povlsen break; 1343f8a74760SLars Povlsen 1344f8a74760SLars Povlsen default: 1345f8a74760SLars Povlsen return -EOPNOTSUPP; 1346f8a74760SLars Povlsen } 1347f8a74760SLars Povlsen 1348f8a74760SLars Povlsen *config = pinconf_to_config_packed(param, val); 1349f8a74760SLars Povlsen 1350f8a74760SLars Povlsen return 0; 1351f8a74760SLars Povlsen } 1352f8a74760SLars Povlsen 1353f8a74760SLars Povlsen static int ocelot_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 1354f8a74760SLars Povlsen unsigned long *configs, unsigned int num_configs) 1355f8a74760SLars Povlsen { 1356f8a74760SLars Povlsen struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1357f8a74760SLars Povlsen u32 param, arg, p; 1358f8a74760SLars Povlsen int cfg, err = 0; 1359f8a74760SLars Povlsen 1360f8a74760SLars Povlsen for (cfg = 0; cfg < num_configs; cfg++) { 1361f8a74760SLars Povlsen param = pinconf_to_config_param(configs[cfg]); 1362f8a74760SLars Povlsen arg = pinconf_to_config_argument(configs[cfg]); 1363f8a74760SLars Povlsen 1364f8a74760SLars Povlsen switch (param) { 1365f8a74760SLars Povlsen case PIN_CONFIG_BIAS_DISABLE: 1366f8a74760SLars Povlsen case PIN_CONFIG_BIAS_PULL_UP: 1367f8a74760SLars Povlsen case PIN_CONFIG_BIAS_PULL_DOWN: 1368f8a74760SLars Povlsen arg = (param == PIN_CONFIG_BIAS_DISABLE) ? 0 : 1369f8a74760SLars Povlsen (param == PIN_CONFIG_BIAS_PULL_UP) ? BIAS_PU_BIT : 1370f8a74760SLars Povlsen BIAS_PD_BIT; 1371f8a74760SLars Povlsen 1372f8a74760SLars Povlsen err = ocelot_hw_set_value(info, pin, PINCONF_BIAS, arg); 1373f8a74760SLars Povlsen if (err) 1374f8a74760SLars Povlsen goto err; 1375f8a74760SLars Povlsen 1376f8a74760SLars Povlsen break; 1377f8a74760SLars Povlsen 1378f8a74760SLars Povlsen case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 1379f8a74760SLars Povlsen arg = arg ? SCHMITT_BIT : 0; 1380f8a74760SLars Povlsen err = ocelot_hw_set_value(info, pin, PINCONF_SCHMITT, 1381f8a74760SLars Povlsen arg); 1382f8a74760SLars Povlsen if (err) 1383f8a74760SLars Povlsen goto err; 1384f8a74760SLars Povlsen 1385f8a74760SLars Povlsen break; 1386f8a74760SLars Povlsen 1387f8a74760SLars Povlsen case PIN_CONFIG_DRIVE_STRENGTH: 1388f8a74760SLars Povlsen err = ocelot_hw_set_value(info, pin, 1389f8a74760SLars Povlsen PINCONF_DRIVE_STRENGTH, 1390f8a74760SLars Povlsen arg); 1391f8a74760SLars Povlsen if (err) 1392f8a74760SLars Povlsen goto err; 1393f8a74760SLars Povlsen 1394f8a74760SLars Povlsen break; 1395f8a74760SLars Povlsen 1396f8a74760SLars Povlsen case PIN_CONFIG_OUTPUT_ENABLE: 1397f8a74760SLars Povlsen case PIN_CONFIG_INPUT_ENABLE: 1398f8a74760SLars Povlsen case PIN_CONFIG_OUTPUT: 1399f8a74760SLars Povlsen p = pin % 32; 1400f8a74760SLars Povlsen if (arg) 1401f8a74760SLars Povlsen regmap_write(info->map, 1402f8a74760SLars Povlsen REG(OCELOT_GPIO_OUT_SET, info, 1403f8a74760SLars Povlsen pin), 1404f8a74760SLars Povlsen BIT(p)); 1405f8a74760SLars Povlsen else 1406f8a74760SLars Povlsen regmap_write(info->map, 1407f8a74760SLars Povlsen REG(OCELOT_GPIO_OUT_CLR, info, 1408f8a74760SLars Povlsen pin), 1409f8a74760SLars Povlsen BIT(p)); 1410f8a74760SLars Povlsen regmap_update_bits(info->map, 1411f8a74760SLars Povlsen REG(OCELOT_GPIO_OE, info, pin), 1412f8a74760SLars Povlsen BIT(p), 1413f8a74760SLars Povlsen param == PIN_CONFIG_INPUT_ENABLE ? 1414f8a74760SLars Povlsen 0 : BIT(p)); 1415f8a74760SLars Povlsen break; 1416f8a74760SLars Povlsen 1417f8a74760SLars Povlsen default: 1418f8a74760SLars Povlsen err = -EOPNOTSUPP; 1419f8a74760SLars Povlsen } 1420f8a74760SLars Povlsen } 1421f8a74760SLars Povlsen err: 1422f8a74760SLars Povlsen return err; 1423f8a74760SLars Povlsen } 1424f8a74760SLars Povlsen 1425f8a74760SLars Povlsen static const struct pinconf_ops ocelot_confops = { 1426f8a74760SLars Povlsen .is_generic = true, 1427f8a74760SLars Povlsen .pin_config_get = ocelot_pinconf_get, 1428f8a74760SLars Povlsen .pin_config_set = ocelot_pinconf_set, 1429f8a74760SLars Povlsen .pin_config_config_dbg_show = pinconf_generic_dump_config, 1430f8a74760SLars Povlsen }; 1431f8a74760SLars Povlsen 1432ce8dc094SAlexandre Belloni static const struct pinctrl_ops ocelot_pctl_ops = { 1433ce8dc094SAlexandre Belloni .get_groups_count = ocelot_pctl_get_groups_count, 1434ce8dc094SAlexandre Belloni .get_group_name = ocelot_pctl_get_group_name, 1435ce8dc094SAlexandre Belloni .get_group_pins = ocelot_pctl_get_group_pins, 1436ce8dc094SAlexandre Belloni .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, 1437ce8dc094SAlexandre Belloni .dt_free_map = pinconf_generic_dt_free_map, 1438ce8dc094SAlexandre Belloni }; 1439ce8dc094SAlexandre Belloni 14408f27440dSLars Povlsen static struct pinctrl_desc luton_desc = { 14418f27440dSLars Povlsen .name = "luton-pinctrl", 14428f27440dSLars Povlsen .pins = luton_pins, 14438f27440dSLars Povlsen .npins = ARRAY_SIZE(luton_pins), 14448f27440dSLars Povlsen .pctlops = &ocelot_pctl_ops, 14458f27440dSLars Povlsen .pmxops = &ocelot_pmx_ops, 14468f27440dSLars Povlsen .owner = THIS_MODULE, 14478f27440dSLars Povlsen }; 14488f27440dSLars Povlsen 14496e6347e2SLars Povlsen static struct pinctrl_desc serval_desc = { 14506e6347e2SLars Povlsen .name = "serval-pinctrl", 14516e6347e2SLars Povlsen .pins = serval_pins, 14526e6347e2SLars Povlsen .npins = ARRAY_SIZE(serval_pins), 14536e6347e2SLars Povlsen .pctlops = &ocelot_pctl_ops, 14546e6347e2SLars Povlsen .pmxops = &ocelot_pmx_ops, 14556e6347e2SLars Povlsen .owner = THIS_MODULE, 14566e6347e2SLars Povlsen }; 14576e6347e2SLars Povlsen 1458ce8dc094SAlexandre Belloni static struct pinctrl_desc ocelot_desc = { 1459ce8dc094SAlexandre Belloni .name = "ocelot-pinctrl", 1460ce8dc094SAlexandre Belloni .pins = ocelot_pins, 1461ce8dc094SAlexandre Belloni .npins = ARRAY_SIZE(ocelot_pins), 1462ce8dc094SAlexandre Belloni .pctlops = &ocelot_pctl_ops, 1463ce8dc094SAlexandre Belloni .pmxops = &ocelot_pmx_ops, 1464ce8dc094SAlexandre Belloni .owner = THIS_MODULE, 1465ce8dc094SAlexandre Belloni }; 1466ce8dc094SAlexandre Belloni 1467da801ab5SAlexandre Belloni static struct pinctrl_desc jaguar2_desc = { 1468da801ab5SAlexandre Belloni .name = "jaguar2-pinctrl", 1469da801ab5SAlexandre Belloni .pins = jaguar2_pins, 1470da801ab5SAlexandre Belloni .npins = ARRAY_SIZE(jaguar2_pins), 1471da801ab5SAlexandre Belloni .pctlops = &ocelot_pctl_ops, 1472da801ab5SAlexandre Belloni .pmxops = &ocelot_pmx_ops, 1473da801ab5SAlexandre Belloni .owner = THIS_MODULE, 1474da801ab5SAlexandre Belloni }; 1475da801ab5SAlexandre Belloni 1476f8a74760SLars Povlsen static struct pinctrl_desc sparx5_desc = { 1477f8a74760SLars Povlsen .name = "sparx5-pinctrl", 1478f8a74760SLars Povlsen .pins = sparx5_pins, 1479f8a74760SLars Povlsen .npins = ARRAY_SIZE(sparx5_pins), 1480f8a74760SLars Povlsen .pctlops = &ocelot_pctl_ops, 1481f8a74760SLars Povlsen .pmxops = &ocelot_pmx_ops, 1482f8a74760SLars Povlsen .confops = &ocelot_confops, 1483f8a74760SLars Povlsen .owner = THIS_MODULE, 1484f8a74760SLars Povlsen }; 1485f8a74760SLars Povlsen 1486*531d6ab3SKavyasree Kotagiri static struct pinctrl_desc lan966x_desc = { 1487*531d6ab3SKavyasree Kotagiri .name = "lan966x-pinctrl", 1488*531d6ab3SKavyasree Kotagiri .pins = lan966x_pins, 1489*531d6ab3SKavyasree Kotagiri .npins = ARRAY_SIZE(lan966x_pins), 1490*531d6ab3SKavyasree Kotagiri .pctlops = &ocelot_pctl_ops, 1491*531d6ab3SKavyasree Kotagiri .pmxops = &lan966x_pmx_ops, 1492*531d6ab3SKavyasree Kotagiri .confops = &ocelot_confops, 1493*531d6ab3SKavyasree Kotagiri .owner = THIS_MODULE, 1494*531d6ab3SKavyasree Kotagiri }; 1495*531d6ab3SKavyasree Kotagiri 1496ce8dc094SAlexandre Belloni static int ocelot_create_group_func_map(struct device *dev, 1497ce8dc094SAlexandre Belloni struct ocelot_pinctrl *info) 1498ce8dc094SAlexandre Belloni { 1499ce8dc094SAlexandre Belloni int f, npins, i; 1500da801ab5SAlexandre Belloni u8 *pins = kcalloc(info->desc->npins, sizeof(u8), GFP_KERNEL); 1501da801ab5SAlexandre Belloni 1502da801ab5SAlexandre Belloni if (!pins) 1503da801ab5SAlexandre Belloni return -ENOMEM; 1504ce8dc094SAlexandre Belloni 1505ce8dc094SAlexandre Belloni for (f = 0; f < FUNC_MAX; f++) { 1506da801ab5SAlexandre Belloni for (npins = 0, i = 0; i < info->desc->npins; i++) { 1507da801ab5SAlexandre Belloni if (ocelot_pin_function_idx(info, i, f) >= 0) 1508ce8dc094SAlexandre Belloni pins[npins++] = i; 1509ce8dc094SAlexandre Belloni } 1510ce8dc094SAlexandre Belloni 1511da801ab5SAlexandre Belloni if (!npins) 1512da801ab5SAlexandre Belloni continue; 1513da801ab5SAlexandre Belloni 1514ce8dc094SAlexandre Belloni info->func[f].ngroups = npins; 1515da801ab5SAlexandre Belloni info->func[f].groups = devm_kcalloc(dev, npins, sizeof(char *), 1516ce8dc094SAlexandre Belloni GFP_KERNEL); 1517da801ab5SAlexandre Belloni if (!info->func[f].groups) { 1518da801ab5SAlexandre Belloni kfree(pins); 1519ce8dc094SAlexandre Belloni return -ENOMEM; 1520da801ab5SAlexandre Belloni } 1521ce8dc094SAlexandre Belloni 1522ce8dc094SAlexandre Belloni for (i = 0; i < npins; i++) 1523f8a74760SLars Povlsen info->func[f].groups[i] = 1524f8a74760SLars Povlsen info->desc->pins[pins[i]].name; 1525ce8dc094SAlexandre Belloni } 1526ce8dc094SAlexandre Belloni 1527da801ab5SAlexandre Belloni kfree(pins); 1528da801ab5SAlexandre Belloni 1529ce8dc094SAlexandre Belloni return 0; 1530ce8dc094SAlexandre Belloni } 1531ce8dc094SAlexandre Belloni 1532ce8dc094SAlexandre Belloni static int ocelot_pinctrl_register(struct platform_device *pdev, 1533ce8dc094SAlexandre Belloni struct ocelot_pinctrl *info) 1534ce8dc094SAlexandre Belloni { 1535ce8dc094SAlexandre Belloni int ret; 1536ce8dc094SAlexandre Belloni 1537ce8dc094SAlexandre Belloni ret = ocelot_create_group_func_map(&pdev->dev, info); 1538ce8dc094SAlexandre Belloni if (ret) { 1539ce8dc094SAlexandre Belloni dev_err(&pdev->dev, "Unable to create group func map.\n"); 1540ce8dc094SAlexandre Belloni return ret; 1541ce8dc094SAlexandre Belloni } 1542ce8dc094SAlexandre Belloni 1543da801ab5SAlexandre Belloni info->pctl = devm_pinctrl_register(&pdev->dev, info->desc, info); 1544ce8dc094SAlexandre Belloni if (IS_ERR(info->pctl)) { 1545ce8dc094SAlexandre Belloni dev_err(&pdev->dev, "Failed to register pinctrl\n"); 1546ce8dc094SAlexandre Belloni return PTR_ERR(info->pctl); 1547ce8dc094SAlexandre Belloni } 1548ce8dc094SAlexandre Belloni 1549ce8dc094SAlexandre Belloni return 0; 1550ce8dc094SAlexandre Belloni } 1551ce8dc094SAlexandre Belloni 1552ce8dc094SAlexandre Belloni static int ocelot_gpio_get(struct gpio_chip *chip, unsigned int offset) 1553ce8dc094SAlexandre Belloni { 1554ce8dc094SAlexandre Belloni struct ocelot_pinctrl *info = gpiochip_get_data(chip); 1555ce8dc094SAlexandre Belloni unsigned int val; 1556ce8dc094SAlexandre Belloni 1557da801ab5SAlexandre Belloni regmap_read(info->map, REG(OCELOT_GPIO_IN, info, offset), &val); 1558ce8dc094SAlexandre Belloni 1559da801ab5SAlexandre Belloni return !!(val & BIT(offset % 32)); 1560ce8dc094SAlexandre Belloni } 1561ce8dc094SAlexandre Belloni 1562ce8dc094SAlexandre Belloni static void ocelot_gpio_set(struct gpio_chip *chip, unsigned int offset, 1563ce8dc094SAlexandre Belloni int value) 1564ce8dc094SAlexandre Belloni { 1565ce8dc094SAlexandre Belloni struct ocelot_pinctrl *info = gpiochip_get_data(chip); 1566ce8dc094SAlexandre Belloni 1567ce8dc094SAlexandre Belloni if (value) 1568da801ab5SAlexandre Belloni regmap_write(info->map, REG(OCELOT_GPIO_OUT_SET, info, offset), 1569da801ab5SAlexandre Belloni BIT(offset % 32)); 1570ce8dc094SAlexandre Belloni else 1571da801ab5SAlexandre Belloni regmap_write(info->map, REG(OCELOT_GPIO_OUT_CLR, info, offset), 1572da801ab5SAlexandre Belloni BIT(offset % 32)); 1573ce8dc094SAlexandre Belloni } 1574ce8dc094SAlexandre Belloni 1575ce8dc094SAlexandre Belloni static int ocelot_gpio_get_direction(struct gpio_chip *chip, 1576ce8dc094SAlexandre Belloni unsigned int offset) 1577ce8dc094SAlexandre Belloni { 1578ce8dc094SAlexandre Belloni struct ocelot_pinctrl *info = gpiochip_get_data(chip); 1579ce8dc094SAlexandre Belloni unsigned int val; 1580ce8dc094SAlexandre Belloni 1581da801ab5SAlexandre Belloni regmap_read(info->map, REG(OCELOT_GPIO_OE, info, offset), &val); 1582ce8dc094SAlexandre Belloni 15833c827873SMatti Vaittinen if (val & BIT(offset % 32)) 15843c827873SMatti Vaittinen return GPIO_LINE_DIRECTION_OUT; 15853c827873SMatti Vaittinen 15863c827873SMatti Vaittinen return GPIO_LINE_DIRECTION_IN; 1587ce8dc094SAlexandre Belloni } 1588ce8dc094SAlexandre Belloni 1589ce8dc094SAlexandre Belloni static int ocelot_gpio_direction_input(struct gpio_chip *chip, 1590ce8dc094SAlexandre Belloni unsigned int offset) 1591ce8dc094SAlexandre Belloni { 1592ce8dc094SAlexandre Belloni return pinctrl_gpio_direction_input(chip->base + offset); 1593ce8dc094SAlexandre Belloni } 1594ce8dc094SAlexandre Belloni 1595ce8dc094SAlexandre Belloni static int ocelot_gpio_direction_output(struct gpio_chip *chip, 1596ce8dc094SAlexandre Belloni unsigned int offset, int value) 1597ce8dc094SAlexandre Belloni { 1598ce8dc094SAlexandre Belloni struct ocelot_pinctrl *info = gpiochip_get_data(chip); 1599da801ab5SAlexandre Belloni unsigned int pin = BIT(offset % 32); 1600ce8dc094SAlexandre Belloni 1601ce8dc094SAlexandre Belloni if (value) 1602da801ab5SAlexandre Belloni regmap_write(info->map, REG(OCELOT_GPIO_OUT_SET, info, offset), 1603da801ab5SAlexandre Belloni pin); 1604ce8dc094SAlexandre Belloni else 1605da801ab5SAlexandre Belloni regmap_write(info->map, REG(OCELOT_GPIO_OUT_CLR, info, offset), 1606da801ab5SAlexandre Belloni pin); 1607ce8dc094SAlexandre Belloni 1608ce8dc094SAlexandre Belloni return pinctrl_gpio_direction_output(chip->base + offset); 1609ce8dc094SAlexandre Belloni } 1610ce8dc094SAlexandre Belloni 1611ce8dc094SAlexandre Belloni static const struct gpio_chip ocelot_gpiolib_chip = { 1612ce8dc094SAlexandre Belloni .request = gpiochip_generic_request, 1613ce8dc094SAlexandre Belloni .free = gpiochip_generic_free, 1614ce8dc094SAlexandre Belloni .set = ocelot_gpio_set, 1615ce8dc094SAlexandre Belloni .get = ocelot_gpio_get, 1616ce8dc094SAlexandre Belloni .get_direction = ocelot_gpio_get_direction, 1617ce8dc094SAlexandre Belloni .direction_input = ocelot_gpio_direction_input, 1618ce8dc094SAlexandre Belloni .direction_output = ocelot_gpio_direction_output, 1619ce8dc094SAlexandre Belloni .owner = THIS_MODULE, 1620ce8dc094SAlexandre Belloni }; 1621ce8dc094SAlexandre Belloni 1622be36abb7SQuentin Schulz static void ocelot_irq_mask(struct irq_data *data) 1623be36abb7SQuentin Schulz { 1624be36abb7SQuentin Schulz struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 1625be36abb7SQuentin Schulz struct ocelot_pinctrl *info = gpiochip_get_data(chip); 1626be36abb7SQuentin Schulz unsigned int gpio = irqd_to_hwirq(data); 1627be36abb7SQuentin Schulz 1628da801ab5SAlexandre Belloni regmap_update_bits(info->map, REG(OCELOT_GPIO_INTR_ENA, info, gpio), 1629da801ab5SAlexandre Belloni BIT(gpio % 32), 0); 1630be36abb7SQuentin Schulz } 1631be36abb7SQuentin Schulz 1632be36abb7SQuentin Schulz static void ocelot_irq_unmask(struct irq_data *data) 1633be36abb7SQuentin Schulz { 1634be36abb7SQuentin Schulz struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 1635be36abb7SQuentin Schulz struct ocelot_pinctrl *info = gpiochip_get_data(chip); 1636be36abb7SQuentin Schulz unsigned int gpio = irqd_to_hwirq(data); 1637be36abb7SQuentin Schulz 1638da801ab5SAlexandre Belloni regmap_update_bits(info->map, REG(OCELOT_GPIO_INTR_ENA, info, gpio), 1639da801ab5SAlexandre Belloni BIT(gpio % 32), BIT(gpio % 32)); 1640be36abb7SQuentin Schulz } 1641be36abb7SQuentin Schulz 1642be36abb7SQuentin Schulz static void ocelot_irq_ack(struct irq_data *data) 1643be36abb7SQuentin Schulz { 1644be36abb7SQuentin Schulz struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 1645be36abb7SQuentin Schulz struct ocelot_pinctrl *info = gpiochip_get_data(chip); 1646be36abb7SQuentin Schulz unsigned int gpio = irqd_to_hwirq(data); 1647be36abb7SQuentin Schulz 1648da801ab5SAlexandre Belloni regmap_write_bits(info->map, REG(OCELOT_GPIO_INTR, info, gpio), 1649da801ab5SAlexandre Belloni BIT(gpio % 32), BIT(gpio % 32)); 1650be36abb7SQuentin Schulz } 1651be36abb7SQuentin Schulz 1652be36abb7SQuentin Schulz static int ocelot_irq_set_type(struct irq_data *data, unsigned int type); 1653be36abb7SQuentin Schulz 1654be36abb7SQuentin Schulz static struct irq_chip ocelot_eoi_irqchip = { 1655be36abb7SQuentin Schulz .name = "gpio", 1656be36abb7SQuentin Schulz .irq_mask = ocelot_irq_mask, 1657be36abb7SQuentin Schulz .irq_eoi = ocelot_irq_ack, 1658be36abb7SQuentin Schulz .irq_unmask = ocelot_irq_unmask, 1659be36abb7SQuentin Schulz .flags = IRQCHIP_EOI_THREADED | IRQCHIP_EOI_IF_HANDLED, 1660be36abb7SQuentin Schulz .irq_set_type = ocelot_irq_set_type, 1661be36abb7SQuentin Schulz }; 1662be36abb7SQuentin Schulz 1663be36abb7SQuentin Schulz static struct irq_chip ocelot_irqchip = { 1664be36abb7SQuentin Schulz .name = "gpio", 1665be36abb7SQuentin Schulz .irq_mask = ocelot_irq_mask, 1666be36abb7SQuentin Schulz .irq_ack = ocelot_irq_ack, 1667be36abb7SQuentin Schulz .irq_unmask = ocelot_irq_unmask, 1668be36abb7SQuentin Schulz .irq_set_type = ocelot_irq_set_type, 1669be36abb7SQuentin Schulz }; 1670be36abb7SQuentin Schulz 1671be36abb7SQuentin Schulz static int ocelot_irq_set_type(struct irq_data *data, unsigned int type) 1672be36abb7SQuentin Schulz { 1673be36abb7SQuentin Schulz type &= IRQ_TYPE_SENSE_MASK; 1674be36abb7SQuentin Schulz 1675be36abb7SQuentin Schulz if (!(type & (IRQ_TYPE_EDGE_BOTH | IRQ_TYPE_LEVEL_HIGH))) 1676be36abb7SQuentin Schulz return -EINVAL; 1677be36abb7SQuentin Schulz 1678be36abb7SQuentin Schulz if (type & IRQ_TYPE_LEVEL_HIGH) 1679be36abb7SQuentin Schulz irq_set_chip_handler_name_locked(data, &ocelot_eoi_irqchip, 1680be36abb7SQuentin Schulz handle_fasteoi_irq, NULL); 1681be36abb7SQuentin Schulz if (type & IRQ_TYPE_EDGE_BOTH) 1682be36abb7SQuentin Schulz irq_set_chip_handler_name_locked(data, &ocelot_irqchip, 1683be36abb7SQuentin Schulz handle_edge_irq, NULL); 1684be36abb7SQuentin Schulz 1685be36abb7SQuentin Schulz return 0; 1686be36abb7SQuentin Schulz } 1687be36abb7SQuentin Schulz 1688be36abb7SQuentin Schulz static void ocelot_irq_handler(struct irq_desc *desc) 1689be36abb7SQuentin Schulz { 1690be36abb7SQuentin Schulz struct irq_chip *parent_chip = irq_desc_get_chip(desc); 1691be36abb7SQuentin Schulz struct gpio_chip *chip = irq_desc_get_handler_data(desc); 1692be36abb7SQuentin Schulz struct ocelot_pinctrl *info = gpiochip_get_data(chip); 16930b47afc6SLars Povlsen unsigned int id_reg = OCELOT_GPIO_INTR_IDENT * info->stride; 1694da801ab5SAlexandre Belloni unsigned int reg = 0, irq, i; 1695be36abb7SQuentin Schulz unsigned long irqs; 1696be36abb7SQuentin Schulz 1697da801ab5SAlexandre Belloni for (i = 0; i < info->stride; i++) { 16980b47afc6SLars Povlsen regmap_read(info->map, id_reg + 4 * i, ®); 1699be36abb7SQuentin Schulz if (!reg) 1700da801ab5SAlexandre Belloni continue; 1701be36abb7SQuentin Schulz 1702be36abb7SQuentin Schulz chained_irq_enter(parent_chip, desc); 1703be36abb7SQuentin Schulz 1704be36abb7SQuentin Schulz irqs = reg; 1705be36abb7SQuentin Schulz 1706da801ab5SAlexandre Belloni for_each_set_bit(irq, &irqs, 1707da801ab5SAlexandre Belloni min(32U, info->desc->npins - 32 * i)) 1708a9cb09b7SMarc Zyngier generic_handle_domain_irq(chip->irq.domain, irq + 32 * i); 1709be36abb7SQuentin Schulz 1710be36abb7SQuentin Schulz chained_irq_exit(parent_chip, desc); 1711be36abb7SQuentin Schulz } 1712da801ab5SAlexandre Belloni } 1713be36abb7SQuentin Schulz 1714ce8dc094SAlexandre Belloni static int ocelot_gpiochip_register(struct platform_device *pdev, 1715ce8dc094SAlexandre Belloni struct ocelot_pinctrl *info) 1716ce8dc094SAlexandre Belloni { 1717ce8dc094SAlexandre Belloni struct gpio_chip *gc; 1718d874becaSLinus Walleij struct gpio_irq_chip *girq; 171917f2c8d3SQinglang Miao int irq; 1720ce8dc094SAlexandre Belloni 1721ce8dc094SAlexandre Belloni info->gpio_chip = ocelot_gpiolib_chip; 1722ce8dc094SAlexandre Belloni 1723ce8dc094SAlexandre Belloni gc = &info->gpio_chip; 1724da801ab5SAlexandre Belloni gc->ngpio = info->desc->npins; 1725ce8dc094SAlexandre Belloni gc->parent = &pdev->dev; 1726ce8dc094SAlexandre Belloni gc->base = 0; 1727ce8dc094SAlexandre Belloni gc->of_node = info->dev->of_node; 1728ce8dc094SAlexandre Belloni gc->label = "ocelot-gpio"; 1729ce8dc094SAlexandre Belloni 1730550713e3SLars Povlsen irq = irq_of_parse_and_map(gc->of_node, 0); 1731550713e3SLars Povlsen if (irq) { 1732d874becaSLinus Walleij girq = &gc->irq; 1733d874becaSLinus Walleij girq->chip = &ocelot_irqchip; 1734d874becaSLinus Walleij girq->parent_handler = ocelot_irq_handler; 1735d874becaSLinus Walleij girq->num_parents = 1; 1736550713e3SLars Povlsen girq->parents = devm_kcalloc(&pdev->dev, 1, 1737550713e3SLars Povlsen sizeof(*girq->parents), 1738d874becaSLinus Walleij GFP_KERNEL); 1739d874becaSLinus Walleij if (!girq->parents) 1740d874becaSLinus Walleij return -ENOMEM; 1741d874becaSLinus Walleij girq->parents[0] = irq; 1742d874becaSLinus Walleij girq->default_type = IRQ_TYPE_NONE; 1743d874becaSLinus Walleij girq->handler = handle_edge_irq; 1744550713e3SLars Povlsen } 1745d874becaSLinus Walleij 174617f2c8d3SQinglang Miao return devm_gpiochip_add_data(&pdev->dev, gc, info); 1747ce8dc094SAlexandre Belloni } 1748ce8dc094SAlexandre Belloni 1749ce8dc094SAlexandre Belloni static const struct of_device_id ocelot_pinctrl_of_match[] = { 17508f27440dSLars Povlsen { .compatible = "mscc,luton-pinctrl", .data = &luton_desc }, 17516e6347e2SLars Povlsen { .compatible = "mscc,serval-pinctrl", .data = &serval_desc }, 1752da801ab5SAlexandre Belloni { .compatible = "mscc,ocelot-pinctrl", .data = &ocelot_desc }, 1753da801ab5SAlexandre Belloni { .compatible = "mscc,jaguar2-pinctrl", .data = &jaguar2_desc }, 1754f8a74760SLars Povlsen { .compatible = "microchip,sparx5-pinctrl", .data = &sparx5_desc }, 1755*531d6ab3SKavyasree Kotagiri { .compatible = "microchip,lan966x-pinctrl", .data = &lan966x_desc }, 1756ce8dc094SAlexandre Belloni {}, 1757ce8dc094SAlexandre Belloni }; 1758ce8dc094SAlexandre Belloni 1759ce3e7f0eSColin Ian King static int ocelot_pinctrl_probe(struct platform_device *pdev) 1760ce8dc094SAlexandre Belloni { 1761ce8dc094SAlexandre Belloni struct device *dev = &pdev->dev; 1762ce8dc094SAlexandre Belloni struct ocelot_pinctrl *info; 1763ce8dc094SAlexandre Belloni void __iomem *base; 1764f8a74760SLars Povlsen struct resource *res; 1765ce8dc094SAlexandre Belloni int ret; 1766da801ab5SAlexandre Belloni struct regmap_config regmap_config = { 1767da801ab5SAlexandre Belloni .reg_bits = 32, 1768da801ab5SAlexandre Belloni .val_bits = 32, 1769da801ab5SAlexandre Belloni .reg_stride = 4, 1770da801ab5SAlexandre Belloni }; 1771ce8dc094SAlexandre Belloni 1772ce8dc094SAlexandre Belloni info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL); 1773ce8dc094SAlexandre Belloni if (!info) 1774ce8dc094SAlexandre Belloni return -ENOMEM; 1775ce8dc094SAlexandre Belloni 1776da801ab5SAlexandre Belloni info->desc = (struct pinctrl_desc *)device_get_match_data(dev); 1777da801ab5SAlexandre Belloni 1778ce8dc094SAlexandre Belloni base = devm_ioremap_resource(dev, 1779ce8dc094SAlexandre Belloni platform_get_resource(pdev, IORESOURCE_MEM, 0)); 17800f9facdbSZhen Lei if (IS_ERR(base)) 1781ce8dc094SAlexandre Belloni return PTR_ERR(base); 1782ce8dc094SAlexandre Belloni 1783da801ab5SAlexandre Belloni info->stride = 1 + (info->desc->npins - 1) / 32; 1784f8a74760SLars Povlsen 1785da801ab5SAlexandre Belloni regmap_config.max_register = OCELOT_GPIO_SD_MAP * info->stride + 15 * 4; 1786da801ab5SAlexandre Belloni 1787da801ab5SAlexandre Belloni info->map = devm_regmap_init_mmio(dev, base, ®map_config); 1788ce8dc094SAlexandre Belloni if (IS_ERR(info->map)) { 1789ce8dc094SAlexandre Belloni dev_err(dev, "Failed to create regmap\n"); 1790ce8dc094SAlexandre Belloni return PTR_ERR(info->map); 1791ce8dc094SAlexandre Belloni } 1792ce8dc094SAlexandre Belloni dev_set_drvdata(dev, info->map); 1793ce8dc094SAlexandre Belloni info->dev = dev; 1794ce8dc094SAlexandre Belloni 1795f8a74760SLars Povlsen /* Pinconf registers */ 1796f8a74760SLars Povlsen if (info->desc->confops) { 1797f8a74760SLars Povlsen res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 1798f8a74760SLars Povlsen base = devm_ioremap_resource(dev, res); 1799f8a74760SLars Povlsen if (IS_ERR(base)) 1800f8a74760SLars Povlsen dev_dbg(dev, "Failed to ioremap config registers (no extended pinconf)\n"); 1801f8a74760SLars Povlsen else 1802f8a74760SLars Povlsen info->pincfg = base; 1803f8a74760SLars Povlsen } 1804f8a74760SLars Povlsen 1805ce8dc094SAlexandre Belloni ret = ocelot_pinctrl_register(pdev, info); 1806ce8dc094SAlexandre Belloni if (ret) 1807ce8dc094SAlexandre Belloni return ret; 1808ce8dc094SAlexandre Belloni 1809ce8dc094SAlexandre Belloni ret = ocelot_gpiochip_register(pdev, info); 1810ce8dc094SAlexandre Belloni if (ret) 1811ce8dc094SAlexandre Belloni return ret; 1812ce8dc094SAlexandre Belloni 1813f8a74760SLars Povlsen dev_info(dev, "driver registered\n"); 1814f8a74760SLars Povlsen 1815ce8dc094SAlexandre Belloni return 0; 1816ce8dc094SAlexandre Belloni } 1817ce8dc094SAlexandre Belloni 1818ce8dc094SAlexandre Belloni static struct platform_driver ocelot_pinctrl_driver = { 1819ce8dc094SAlexandre Belloni .driver = { 1820ce8dc094SAlexandre Belloni .name = "pinctrl-ocelot", 1821ce8dc094SAlexandre Belloni .of_match_table = of_match_ptr(ocelot_pinctrl_of_match), 1822ce8dc094SAlexandre Belloni .suppress_bind_attrs = true, 1823ce8dc094SAlexandre Belloni }, 1824ce8dc094SAlexandre Belloni .probe = ocelot_pinctrl_probe, 1825ce8dc094SAlexandre Belloni }; 1826ce8dc094SAlexandre Belloni builtin_platform_driver(ocelot_pinctrl_driver); 1827