1ce8dc094SAlexandre Belloni // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2ce8dc094SAlexandre Belloni /* 3ce8dc094SAlexandre Belloni * Microsemi SoCs pinctrl driver 4ce8dc094SAlexandre Belloni * 5ce8dc094SAlexandre Belloni * Author: <alexandre.belloni@free-electrons.com> 6ce8dc094SAlexandre Belloni * License: Dual MIT/GPL 7ce8dc094SAlexandre Belloni * Copyright (c) 2017 Microsemi Corporation 8ce8dc094SAlexandre Belloni */ 9ce8dc094SAlexandre Belloni 10ce8dc094SAlexandre Belloni #include <linux/gpio/driver.h> 11ce8dc094SAlexandre Belloni #include <linux/interrupt.h> 12ce8dc094SAlexandre Belloni #include <linux/io.h> 13ce8dc094SAlexandre Belloni #include <linux/of_device.h> 14be36abb7SQuentin Schulz #include <linux/of_irq.h> 15ce8dc094SAlexandre Belloni #include <linux/of_platform.h> 16ce8dc094SAlexandre Belloni #include <linux/pinctrl/pinctrl.h> 17ce8dc094SAlexandre Belloni #include <linux/pinctrl/pinmux.h> 18ce8dc094SAlexandre Belloni #include <linux/pinctrl/pinconf.h> 19ce8dc094SAlexandre Belloni #include <linux/pinctrl/pinconf-generic.h> 20ce8dc094SAlexandre Belloni #include <linux/platform_device.h> 21ce8dc094SAlexandre Belloni #include <linux/regmap.h> 22*453200afSMichael Walle #include <linux/reset.h> 23ce8dc094SAlexandre Belloni #include <linux/slab.h> 24ce8dc094SAlexandre Belloni 25ce8dc094SAlexandre Belloni #include "core.h" 26ce8dc094SAlexandre Belloni #include "pinconf.h" 27ce8dc094SAlexandre Belloni #include "pinmux.h" 28ce8dc094SAlexandre Belloni 29f8a74760SLars Povlsen #define ocelot_clrsetbits(addr, clear, set) \ 30f8a74760SLars Povlsen writel((readl(addr) & ~(clear)) | (set), (addr)) 31f8a74760SLars Povlsen 32f8a74760SLars Povlsen /* PINCONFIG bits (sparx5 only) */ 33f8a74760SLars Povlsen enum { 34f8a74760SLars Povlsen PINCONF_BIAS, 35f8a74760SLars Povlsen PINCONF_SCHMITT, 36f8a74760SLars Povlsen PINCONF_DRIVE_STRENGTH, 37f8a74760SLars Povlsen }; 38f8a74760SLars Povlsen 39f8a74760SLars Povlsen #define BIAS_PD_BIT BIT(4) 40f8a74760SLars Povlsen #define BIAS_PU_BIT BIT(3) 41f8a74760SLars Povlsen #define BIAS_BITS (BIAS_PD_BIT|BIAS_PU_BIT) 42f8a74760SLars Povlsen #define SCHMITT_BIT BIT(2) 43f8a74760SLars Povlsen #define DRIVE_BITS GENMASK(1, 0) 44f8a74760SLars Povlsen 45f8a74760SLars Povlsen /* GPIO standard registers */ 46ce8dc094SAlexandre Belloni #define OCELOT_GPIO_OUT_SET 0x0 47ce8dc094SAlexandre Belloni #define OCELOT_GPIO_OUT_CLR 0x4 48ce8dc094SAlexandre Belloni #define OCELOT_GPIO_OUT 0x8 49ce8dc094SAlexandre Belloni #define OCELOT_GPIO_IN 0xc 50ce8dc094SAlexandre Belloni #define OCELOT_GPIO_OE 0x10 51ce8dc094SAlexandre Belloni #define OCELOT_GPIO_INTR 0x14 52ce8dc094SAlexandre Belloni #define OCELOT_GPIO_INTR_ENA 0x18 53ce8dc094SAlexandre Belloni #define OCELOT_GPIO_INTR_IDENT 0x1c 54ce8dc094SAlexandre Belloni #define OCELOT_GPIO_ALT0 0x20 55ce8dc094SAlexandre Belloni #define OCELOT_GPIO_ALT1 0x24 56ce8dc094SAlexandre Belloni #define OCELOT_GPIO_SD_MAP 0x28 57ce8dc094SAlexandre Belloni 58ce8dc094SAlexandre Belloni #define OCELOT_FUNC_PER_PIN 4 59ce8dc094SAlexandre Belloni 60ce8dc094SAlexandre Belloni enum { 61531d6ab3SKavyasree Kotagiri FUNC_CAN0_a, 62531d6ab3SKavyasree Kotagiri FUNC_CAN0_b, 63531d6ab3SKavyasree Kotagiri FUNC_CAN1, 64bf3e7f49SMichael Walle FUNC_CLKMON, 65ce8dc094SAlexandre Belloni FUNC_NONE, 66531d6ab3SKavyasree Kotagiri FUNC_FC0_a, 67531d6ab3SKavyasree Kotagiri FUNC_FC0_b, 68531d6ab3SKavyasree Kotagiri FUNC_FC0_c, 69531d6ab3SKavyasree Kotagiri FUNC_FC1_a, 70531d6ab3SKavyasree Kotagiri FUNC_FC1_b, 71531d6ab3SKavyasree Kotagiri FUNC_FC1_c, 72531d6ab3SKavyasree Kotagiri FUNC_FC2_a, 73531d6ab3SKavyasree Kotagiri FUNC_FC2_b, 74531d6ab3SKavyasree Kotagiri FUNC_FC3_a, 75531d6ab3SKavyasree Kotagiri FUNC_FC3_b, 76531d6ab3SKavyasree Kotagiri FUNC_FC3_c, 77531d6ab3SKavyasree Kotagiri FUNC_FC4_a, 78531d6ab3SKavyasree Kotagiri FUNC_FC4_b, 79531d6ab3SKavyasree Kotagiri FUNC_FC4_c, 80531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD0, 81531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD1, 82531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD2, 83531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD3, 84531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD4, 85531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD5, 86531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD6, 87531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD7, 88531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD8, 89531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD9, 90531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD10, 91531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD11, 92531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD12, 93531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD13, 94531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD14, 95531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD15, 96531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD16, 97531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD17, 98531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD18, 99531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD19, 100531d6ab3SKavyasree Kotagiri FUNC_FC_SHRD20, 101ce8dc094SAlexandre Belloni FUNC_GPIO, 102531d6ab3SKavyasree Kotagiri FUNC_IB_TRG_a, 103531d6ab3SKavyasree Kotagiri FUNC_IB_TRG_b, 104531d6ab3SKavyasree Kotagiri FUNC_IB_TRG_c, 105f8a74760SLars Povlsen FUNC_IRQ0, 106531d6ab3SKavyasree Kotagiri FUNC_IRQ_IN_a, 107531d6ab3SKavyasree Kotagiri FUNC_IRQ_IN_b, 108531d6ab3SKavyasree Kotagiri FUNC_IRQ_IN_c, 109ce8dc094SAlexandre Belloni FUNC_IRQ0_IN, 110531d6ab3SKavyasree Kotagiri FUNC_IRQ_OUT_a, 111531d6ab3SKavyasree Kotagiri FUNC_IRQ_OUT_b, 112531d6ab3SKavyasree Kotagiri FUNC_IRQ_OUT_c, 113ce8dc094SAlexandre Belloni FUNC_IRQ0_OUT, 114f8a74760SLars Povlsen FUNC_IRQ1, 115ce8dc094SAlexandre Belloni FUNC_IRQ1_IN, 116ce8dc094SAlexandre Belloni FUNC_IRQ1_OUT, 117f8a74760SLars Povlsen FUNC_EXT_IRQ, 118edc72546SLars Povlsen FUNC_MIIM, 119531d6ab3SKavyasree Kotagiri FUNC_MIIM_a, 120531d6ab3SKavyasree Kotagiri FUNC_MIIM_b, 121531d6ab3SKavyasree Kotagiri FUNC_MIIM_c, 122531d6ab3SKavyasree Kotagiri FUNC_MIIM_Sa, 123531d6ab3SKavyasree Kotagiri FUNC_MIIM_Sb, 124531d6ab3SKavyasree Kotagiri FUNC_OB_TRG, 125531d6ab3SKavyasree Kotagiri FUNC_OB_TRG_a, 126531d6ab3SKavyasree Kotagiri FUNC_OB_TRG_b, 127f8a74760SLars Povlsen FUNC_PHY_LED, 128ce8dc094SAlexandre Belloni FUNC_PCI_WAKE, 129f8a74760SLars Povlsen FUNC_MD, 130ce8dc094SAlexandre Belloni FUNC_PTP0, 131ce8dc094SAlexandre Belloni FUNC_PTP1, 132ce8dc094SAlexandre Belloni FUNC_PTP2, 133ce8dc094SAlexandre Belloni FUNC_PTP3, 134531d6ab3SKavyasree Kotagiri FUNC_PTPSYNC_1, 135531d6ab3SKavyasree Kotagiri FUNC_PTPSYNC_2, 136531d6ab3SKavyasree Kotagiri FUNC_PTPSYNC_3, 137531d6ab3SKavyasree Kotagiri FUNC_PTPSYNC_4, 138531d6ab3SKavyasree Kotagiri FUNC_PTPSYNC_5, 139531d6ab3SKavyasree Kotagiri FUNC_PTPSYNC_6, 140531d6ab3SKavyasree Kotagiri FUNC_PTPSYNC_7, 141ce8dc094SAlexandre Belloni FUNC_PWM, 142e97e36cdSMichael Walle FUNC_PWM_a, 143e97e36cdSMichael Walle FUNC_PWM_b, 144531d6ab3SKavyasree Kotagiri FUNC_QSPI1, 145531d6ab3SKavyasree Kotagiri FUNC_QSPI2, 146531d6ab3SKavyasree Kotagiri FUNC_R, 147531d6ab3SKavyasree Kotagiri FUNC_RECO_a, 148531d6ab3SKavyasree Kotagiri FUNC_RECO_b, 149edc72546SLars Povlsen FUNC_RECO_CLK, 150531d6ab3SKavyasree Kotagiri FUNC_SD, 151edc72546SLars Povlsen FUNC_SFP, 152531d6ab3SKavyasree Kotagiri FUNC_SFP_SD, 153ce8dc094SAlexandre Belloni FUNC_SG0, 154da801ab5SAlexandre Belloni FUNC_SG1, 155da801ab5SAlexandre Belloni FUNC_SG2, 156531d6ab3SKavyasree Kotagiri FUNC_SGPIO_a, 157531d6ab3SKavyasree Kotagiri FUNC_SGPIO_b, 158ce8dc094SAlexandre Belloni FUNC_SI, 159f8a74760SLars Povlsen FUNC_SI2, 160ce8dc094SAlexandre Belloni FUNC_TACHO, 161531d6ab3SKavyasree Kotagiri FUNC_TACHO_a, 162531d6ab3SKavyasree Kotagiri FUNC_TACHO_b, 163ce8dc094SAlexandre Belloni FUNC_TWI, 164da801ab5SAlexandre Belloni FUNC_TWI2, 165f8a74760SLars Povlsen FUNC_TWI3, 166ce8dc094SAlexandre Belloni FUNC_TWI_SCL_M, 167531d6ab3SKavyasree Kotagiri FUNC_TWI_SLC_GATE, 168531d6ab3SKavyasree Kotagiri FUNC_TWI_SLC_GATE_AD, 169ce8dc094SAlexandre Belloni FUNC_UART, 170ce8dc094SAlexandre Belloni FUNC_UART2, 171f8a74760SLars Povlsen FUNC_UART3, 172531d6ab3SKavyasree Kotagiri FUNC_USB_H_a, 173531d6ab3SKavyasree Kotagiri FUNC_USB_H_b, 174531d6ab3SKavyasree Kotagiri FUNC_USB_H_c, 175531d6ab3SKavyasree Kotagiri FUNC_USB_S_a, 176531d6ab3SKavyasree Kotagiri FUNC_USB_S_b, 177531d6ab3SKavyasree Kotagiri FUNC_USB_S_c, 178f8a74760SLars Povlsen FUNC_PLL_STAT, 179f8a74760SLars Povlsen FUNC_EMMC, 180531d6ab3SKavyasree Kotagiri FUNC_EMMC_SD, 181f8a74760SLars Povlsen FUNC_REF_CLK, 182f8a74760SLars Povlsen FUNC_RCVRD_CLK, 183ce8dc094SAlexandre Belloni FUNC_MAX 184ce8dc094SAlexandre Belloni }; 185ce8dc094SAlexandre Belloni 186ce8dc094SAlexandre Belloni static const char *const ocelot_function_names[] = { 187531d6ab3SKavyasree Kotagiri [FUNC_CAN0_a] = "can0_a", 188531d6ab3SKavyasree Kotagiri [FUNC_CAN0_b] = "can0_b", 189531d6ab3SKavyasree Kotagiri [FUNC_CAN1] = "can1", 190bf3e7f49SMichael Walle [FUNC_CLKMON] = "clkmon", 191ce8dc094SAlexandre Belloni [FUNC_NONE] = "none", 192531d6ab3SKavyasree Kotagiri [FUNC_FC0_a] = "fc0_a", 193531d6ab3SKavyasree Kotagiri [FUNC_FC0_b] = "fc0_b", 194531d6ab3SKavyasree Kotagiri [FUNC_FC0_c] = "fc0_c", 195531d6ab3SKavyasree Kotagiri [FUNC_FC1_a] = "fc1_a", 196531d6ab3SKavyasree Kotagiri [FUNC_FC1_b] = "fc1_b", 197531d6ab3SKavyasree Kotagiri [FUNC_FC1_c] = "fc1_c", 198531d6ab3SKavyasree Kotagiri [FUNC_FC2_a] = "fc2_a", 199531d6ab3SKavyasree Kotagiri [FUNC_FC2_b] = "fc2_b", 200531d6ab3SKavyasree Kotagiri [FUNC_FC3_a] = "fc3_a", 201531d6ab3SKavyasree Kotagiri [FUNC_FC3_b] = "fc3_b", 202531d6ab3SKavyasree Kotagiri [FUNC_FC3_c] = "fc3_c", 203531d6ab3SKavyasree Kotagiri [FUNC_FC4_a] = "fc4_a", 204531d6ab3SKavyasree Kotagiri [FUNC_FC4_b] = "fc4_b", 205531d6ab3SKavyasree Kotagiri [FUNC_FC4_c] = "fc4_c", 206531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD0] = "fc_shrd0", 207531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD1] = "fc_shrd1", 208531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD2] = "fc_shrd2", 209531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD3] = "fc_shrd3", 210531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD4] = "fc_shrd4", 211531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD5] = "fc_shrd5", 212531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD6] = "fc_shrd6", 213531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD7] = "fc_shrd7", 214531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD8] = "fc_shrd8", 215531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD9] = "fc_shrd9", 216531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD10] = "fc_shrd10", 217531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD11] = "fc_shrd11", 218531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD12] = "fc_shrd12", 219531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD13] = "fc_shrd13", 220531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD14] = "fc_shrd14", 221531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD15] = "fc_shrd15", 222531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD16] = "fc_shrd16", 223531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD17] = "fc_shrd17", 224531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD18] = "fc_shrd18", 225531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD19] = "fc_shrd19", 226531d6ab3SKavyasree Kotagiri [FUNC_FC_SHRD20] = "fc_shrd20", 227ce8dc094SAlexandre Belloni [FUNC_GPIO] = "gpio", 228531d6ab3SKavyasree Kotagiri [FUNC_IB_TRG_a] = "ib_trig_a", 229531d6ab3SKavyasree Kotagiri [FUNC_IB_TRG_b] = "ib_trig_b", 230531d6ab3SKavyasree Kotagiri [FUNC_IB_TRG_c] = "ib_trig_c", 231f8a74760SLars Povlsen [FUNC_IRQ0] = "irq0", 232531d6ab3SKavyasree Kotagiri [FUNC_IRQ_IN_a] = "irq_in_a", 233531d6ab3SKavyasree Kotagiri [FUNC_IRQ_IN_b] = "irq_in_b", 234531d6ab3SKavyasree Kotagiri [FUNC_IRQ_IN_c] = "irq_in_c", 235ce8dc094SAlexandre Belloni [FUNC_IRQ0_IN] = "irq0_in", 236531d6ab3SKavyasree Kotagiri [FUNC_IRQ_OUT_a] = "irq_out_a", 237531d6ab3SKavyasree Kotagiri [FUNC_IRQ_OUT_b] = "irq_out_b", 238531d6ab3SKavyasree Kotagiri [FUNC_IRQ_OUT_c] = "irq_out_c", 239ce8dc094SAlexandre Belloni [FUNC_IRQ0_OUT] = "irq0_out", 240f8a74760SLars Povlsen [FUNC_IRQ1] = "irq1", 241ce8dc094SAlexandre Belloni [FUNC_IRQ1_IN] = "irq1_in", 242ce8dc094SAlexandre Belloni [FUNC_IRQ1_OUT] = "irq1_out", 243f8a74760SLars Povlsen [FUNC_EXT_IRQ] = "ext_irq", 244edc72546SLars Povlsen [FUNC_MIIM] = "miim", 245531d6ab3SKavyasree Kotagiri [FUNC_MIIM_a] = "miim_a", 246531d6ab3SKavyasree Kotagiri [FUNC_MIIM_b] = "miim_b", 247531d6ab3SKavyasree Kotagiri [FUNC_MIIM_c] = "miim_c", 248531d6ab3SKavyasree Kotagiri [FUNC_MIIM_Sa] = "miim_slave_a", 249531d6ab3SKavyasree Kotagiri [FUNC_MIIM_Sb] = "miim_slave_b", 250f8a74760SLars Povlsen [FUNC_PHY_LED] = "phy_led", 251ce8dc094SAlexandre Belloni [FUNC_PCI_WAKE] = "pci_wake", 252f8a74760SLars Povlsen [FUNC_MD] = "md", 253531d6ab3SKavyasree Kotagiri [FUNC_OB_TRG] = "ob_trig", 254531d6ab3SKavyasree Kotagiri [FUNC_OB_TRG_a] = "ob_trig_a", 255531d6ab3SKavyasree Kotagiri [FUNC_OB_TRG_b] = "ob_trig_b", 256ce8dc094SAlexandre Belloni [FUNC_PTP0] = "ptp0", 257ce8dc094SAlexandre Belloni [FUNC_PTP1] = "ptp1", 258ce8dc094SAlexandre Belloni [FUNC_PTP2] = "ptp2", 259ce8dc094SAlexandre Belloni [FUNC_PTP3] = "ptp3", 260531d6ab3SKavyasree Kotagiri [FUNC_PTPSYNC_1] = "ptpsync_1", 261531d6ab3SKavyasree Kotagiri [FUNC_PTPSYNC_2] = "ptpsync_2", 262531d6ab3SKavyasree Kotagiri [FUNC_PTPSYNC_3] = "ptpsync_3", 263531d6ab3SKavyasree Kotagiri [FUNC_PTPSYNC_4] = "ptpsync_4", 264531d6ab3SKavyasree Kotagiri [FUNC_PTPSYNC_5] = "ptpsync_5", 265531d6ab3SKavyasree Kotagiri [FUNC_PTPSYNC_6] = "ptpsync_6", 266531d6ab3SKavyasree Kotagiri [FUNC_PTPSYNC_7] = "ptpsync_7", 267ce8dc094SAlexandre Belloni [FUNC_PWM] = "pwm", 268e97e36cdSMichael Walle [FUNC_PWM_a] = "pwm_a", 269e97e36cdSMichael Walle [FUNC_PWM_b] = "pwm_b", 270531d6ab3SKavyasree Kotagiri [FUNC_QSPI1] = "qspi1", 271531d6ab3SKavyasree Kotagiri [FUNC_QSPI2] = "qspi2", 272531d6ab3SKavyasree Kotagiri [FUNC_R] = "reserved", 273531d6ab3SKavyasree Kotagiri [FUNC_RECO_a] = "reco_a", 274531d6ab3SKavyasree Kotagiri [FUNC_RECO_b] = "reco_b", 275edc72546SLars Povlsen [FUNC_RECO_CLK] = "reco_clk", 276531d6ab3SKavyasree Kotagiri [FUNC_SD] = "sd", 277edc72546SLars Povlsen [FUNC_SFP] = "sfp", 278531d6ab3SKavyasree Kotagiri [FUNC_SFP_SD] = "sfp_sd", 279ce8dc094SAlexandre Belloni [FUNC_SG0] = "sg0", 280da801ab5SAlexandre Belloni [FUNC_SG1] = "sg1", 281da801ab5SAlexandre Belloni [FUNC_SG2] = "sg2", 282531d6ab3SKavyasree Kotagiri [FUNC_SGPIO_a] = "sgpio_a", 283531d6ab3SKavyasree Kotagiri [FUNC_SGPIO_b] = "sgpio_b", 284ce8dc094SAlexandre Belloni [FUNC_SI] = "si", 285f8a74760SLars Povlsen [FUNC_SI2] = "si2", 286ce8dc094SAlexandre Belloni [FUNC_TACHO] = "tacho", 287531d6ab3SKavyasree Kotagiri [FUNC_TACHO_a] = "tacho_a", 288531d6ab3SKavyasree Kotagiri [FUNC_TACHO_b] = "tacho_b", 289ce8dc094SAlexandre Belloni [FUNC_TWI] = "twi", 290da801ab5SAlexandre Belloni [FUNC_TWI2] = "twi2", 291f8a74760SLars Povlsen [FUNC_TWI3] = "twi3", 292ce8dc094SAlexandre Belloni [FUNC_TWI_SCL_M] = "twi_scl_m", 293531d6ab3SKavyasree Kotagiri [FUNC_TWI_SLC_GATE] = "twi_slc_gate", 294531d6ab3SKavyasree Kotagiri [FUNC_TWI_SLC_GATE_AD] = "twi_slc_gate_ad", 295531d6ab3SKavyasree Kotagiri [FUNC_USB_H_a] = "usb_host_a", 296531d6ab3SKavyasree Kotagiri [FUNC_USB_H_b] = "usb_host_b", 297531d6ab3SKavyasree Kotagiri [FUNC_USB_H_c] = "usb_host_c", 298531d6ab3SKavyasree Kotagiri [FUNC_USB_S_a] = "usb_slave_a", 299531d6ab3SKavyasree Kotagiri [FUNC_USB_S_b] = "usb_slave_b", 300531d6ab3SKavyasree Kotagiri [FUNC_USB_S_c] = "usb_slave_c", 301ce8dc094SAlexandre Belloni [FUNC_UART] = "uart", 302ce8dc094SAlexandre Belloni [FUNC_UART2] = "uart2", 303f8a74760SLars Povlsen [FUNC_UART3] = "uart3", 304f8a74760SLars Povlsen [FUNC_PLL_STAT] = "pll_stat", 305f8a74760SLars Povlsen [FUNC_EMMC] = "emmc", 306531d6ab3SKavyasree Kotagiri [FUNC_EMMC_SD] = "emmc_sd", 307f8a74760SLars Povlsen [FUNC_REF_CLK] = "ref_clk", 308f8a74760SLars Povlsen [FUNC_RCVRD_CLK] = "rcvrd_clk", 309ce8dc094SAlexandre Belloni }; 310ce8dc094SAlexandre Belloni 311ce8dc094SAlexandre Belloni struct ocelot_pmx_func { 312ce8dc094SAlexandre Belloni const char **groups; 313ce8dc094SAlexandre Belloni unsigned int ngroups; 314ce8dc094SAlexandre Belloni }; 315ce8dc094SAlexandre Belloni 316ce8dc094SAlexandre Belloni struct ocelot_pin_caps { 317ce8dc094SAlexandre Belloni unsigned int pin; 318ce8dc094SAlexandre Belloni unsigned char functions[OCELOT_FUNC_PER_PIN]; 319531d6ab3SKavyasree Kotagiri unsigned char a_functions[OCELOT_FUNC_PER_PIN]; /* Additional functions */ 320ce8dc094SAlexandre Belloni }; 321ce8dc094SAlexandre Belloni 322ce8dc094SAlexandre Belloni struct ocelot_pinctrl { 323ce8dc094SAlexandre Belloni struct device *dev; 324ce8dc094SAlexandre Belloni struct pinctrl_dev *pctl; 325ce8dc094SAlexandre Belloni struct gpio_chip gpio_chip; 326ce8dc094SAlexandre Belloni struct regmap *map; 327076d9e71SColin Foster struct regmap *pincfg; 328da801ab5SAlexandre Belloni struct pinctrl_desc *desc; 329ce8dc094SAlexandre Belloni struct ocelot_pmx_func func[FUNC_MAX]; 330da801ab5SAlexandre Belloni u8 stride; 331ce8dc094SAlexandre Belloni }; 332ce8dc094SAlexandre Belloni 3338f27440dSLars Povlsen #define LUTON_P(p, f0, f1) \ 3348f27440dSLars Povlsen static struct ocelot_pin_caps luton_pin_##p = { \ 3358f27440dSLars Povlsen .pin = p, \ 3368f27440dSLars Povlsen .functions = { \ 3378f27440dSLars Povlsen FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_NONE, \ 3388f27440dSLars Povlsen }, \ 3398f27440dSLars Povlsen } 3408f27440dSLars Povlsen 3418f27440dSLars Povlsen LUTON_P(0, SG0, NONE); 3428f27440dSLars Povlsen LUTON_P(1, SG0, NONE); 3438f27440dSLars Povlsen LUTON_P(2, SG0, NONE); 3448f27440dSLars Povlsen LUTON_P(3, SG0, NONE); 3458f27440dSLars Povlsen LUTON_P(4, TACHO, NONE); 3468f27440dSLars Povlsen LUTON_P(5, TWI, PHY_LED); 3478f27440dSLars Povlsen LUTON_P(6, TWI, PHY_LED); 3488f27440dSLars Povlsen LUTON_P(7, NONE, PHY_LED); 3498f27440dSLars Povlsen LUTON_P(8, EXT_IRQ, PHY_LED); 3508f27440dSLars Povlsen LUTON_P(9, EXT_IRQ, PHY_LED); 3518f27440dSLars Povlsen LUTON_P(10, SFP, PHY_LED); 3528f27440dSLars Povlsen LUTON_P(11, SFP, PHY_LED); 3538f27440dSLars Povlsen LUTON_P(12, SFP, PHY_LED); 3548f27440dSLars Povlsen LUTON_P(13, SFP, PHY_LED); 3558f27440dSLars Povlsen LUTON_P(14, SI, PHY_LED); 3568f27440dSLars Povlsen LUTON_P(15, SI, PHY_LED); 3578f27440dSLars Povlsen LUTON_P(16, SI, PHY_LED); 3588f27440dSLars Povlsen LUTON_P(17, SFP, PHY_LED); 3598f27440dSLars Povlsen LUTON_P(18, SFP, PHY_LED); 3608f27440dSLars Povlsen LUTON_P(19, SFP, PHY_LED); 3618f27440dSLars Povlsen LUTON_P(20, SFP, PHY_LED); 3628f27440dSLars Povlsen LUTON_P(21, SFP, PHY_LED); 3638f27440dSLars Povlsen LUTON_P(22, SFP, PHY_LED); 3648f27440dSLars Povlsen LUTON_P(23, SFP, PHY_LED); 3658f27440dSLars Povlsen LUTON_P(24, SFP, PHY_LED); 3668f27440dSLars Povlsen LUTON_P(25, SFP, PHY_LED); 3678f27440dSLars Povlsen LUTON_P(26, SFP, PHY_LED); 3688f27440dSLars Povlsen LUTON_P(27, SFP, PHY_LED); 3698f27440dSLars Povlsen LUTON_P(28, SFP, PHY_LED); 3708f27440dSLars Povlsen LUTON_P(29, PWM, NONE); 3718f27440dSLars Povlsen LUTON_P(30, UART, NONE); 3728f27440dSLars Povlsen LUTON_P(31, UART, NONE); 3738f27440dSLars Povlsen 3748f27440dSLars Povlsen #define LUTON_PIN(n) { \ 3758f27440dSLars Povlsen .number = n, \ 3768f27440dSLars Povlsen .name = "GPIO_"#n, \ 3778f27440dSLars Povlsen .drv_data = &luton_pin_##n \ 3788f27440dSLars Povlsen } 3798f27440dSLars Povlsen 3808f27440dSLars Povlsen static const struct pinctrl_pin_desc luton_pins[] = { 3818f27440dSLars Povlsen LUTON_PIN(0), 3828f27440dSLars Povlsen LUTON_PIN(1), 3838f27440dSLars Povlsen LUTON_PIN(2), 3848f27440dSLars Povlsen LUTON_PIN(3), 3858f27440dSLars Povlsen LUTON_PIN(4), 3868f27440dSLars Povlsen LUTON_PIN(5), 3878f27440dSLars Povlsen LUTON_PIN(6), 3888f27440dSLars Povlsen LUTON_PIN(7), 3898f27440dSLars Povlsen LUTON_PIN(8), 3908f27440dSLars Povlsen LUTON_PIN(9), 3918f27440dSLars Povlsen LUTON_PIN(10), 3928f27440dSLars Povlsen LUTON_PIN(11), 3938f27440dSLars Povlsen LUTON_PIN(12), 3948f27440dSLars Povlsen LUTON_PIN(13), 3958f27440dSLars Povlsen LUTON_PIN(14), 3968f27440dSLars Povlsen LUTON_PIN(15), 3978f27440dSLars Povlsen LUTON_PIN(16), 3988f27440dSLars Povlsen LUTON_PIN(17), 3998f27440dSLars Povlsen LUTON_PIN(18), 4008f27440dSLars Povlsen LUTON_PIN(19), 4018f27440dSLars Povlsen LUTON_PIN(20), 4028f27440dSLars Povlsen LUTON_PIN(21), 4038f27440dSLars Povlsen LUTON_PIN(22), 4048f27440dSLars Povlsen LUTON_PIN(23), 4058f27440dSLars Povlsen LUTON_PIN(24), 4068f27440dSLars Povlsen LUTON_PIN(25), 4078f27440dSLars Povlsen LUTON_PIN(26), 4088f27440dSLars Povlsen LUTON_PIN(27), 4098f27440dSLars Povlsen LUTON_PIN(28), 4108f27440dSLars Povlsen LUTON_PIN(29), 4118f27440dSLars Povlsen LUTON_PIN(30), 4128f27440dSLars Povlsen LUTON_PIN(31), 4138f27440dSLars Povlsen }; 4148f27440dSLars Povlsen 4156e6347e2SLars Povlsen #define SERVAL_P(p, f0, f1, f2) \ 4166e6347e2SLars Povlsen static struct ocelot_pin_caps serval_pin_##p = { \ 4176e6347e2SLars Povlsen .pin = p, \ 4186e6347e2SLars Povlsen .functions = { \ 4196e6347e2SLars Povlsen FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2, \ 4206e6347e2SLars Povlsen }, \ 4216e6347e2SLars Povlsen } 4226e6347e2SLars Povlsen 4236e6347e2SLars Povlsen SERVAL_P(0, SG0, NONE, NONE); 4246e6347e2SLars Povlsen SERVAL_P(1, SG0, NONE, NONE); 4256e6347e2SLars Povlsen SERVAL_P(2, SG0, NONE, NONE); 4266e6347e2SLars Povlsen SERVAL_P(3, SG0, NONE, NONE); 4276e6347e2SLars Povlsen SERVAL_P(4, TACHO, NONE, NONE); 4286e6347e2SLars Povlsen SERVAL_P(5, PWM, NONE, NONE); 4296e6347e2SLars Povlsen SERVAL_P(6, TWI, NONE, NONE); 4306e6347e2SLars Povlsen SERVAL_P(7, TWI, NONE, NONE); 4316e6347e2SLars Povlsen SERVAL_P(8, SI, NONE, NONE); 4326e6347e2SLars Povlsen SERVAL_P(9, SI, MD, NONE); 4336e6347e2SLars Povlsen SERVAL_P(10, SI, MD, NONE); 4346e6347e2SLars Povlsen SERVAL_P(11, SFP, MD, TWI_SCL_M); 4356e6347e2SLars Povlsen SERVAL_P(12, SFP, MD, TWI_SCL_M); 4366e6347e2SLars Povlsen SERVAL_P(13, SFP, UART2, TWI_SCL_M); 4376e6347e2SLars Povlsen SERVAL_P(14, SFP, UART2, TWI_SCL_M); 4386e6347e2SLars Povlsen SERVAL_P(15, SFP, PTP0, TWI_SCL_M); 4396e6347e2SLars Povlsen SERVAL_P(16, SFP, PTP0, TWI_SCL_M); 4406e6347e2SLars Povlsen SERVAL_P(17, SFP, PCI_WAKE, TWI_SCL_M); 4416e6347e2SLars Povlsen SERVAL_P(18, SFP, NONE, TWI_SCL_M); 4426e6347e2SLars Povlsen SERVAL_P(19, SFP, NONE, TWI_SCL_M); 4436e6347e2SLars Povlsen SERVAL_P(20, SFP, NONE, TWI_SCL_M); 4446e6347e2SLars Povlsen SERVAL_P(21, SFP, NONE, TWI_SCL_M); 4456e6347e2SLars Povlsen SERVAL_P(22, NONE, NONE, NONE); 4466e6347e2SLars Povlsen SERVAL_P(23, NONE, NONE, NONE); 4476e6347e2SLars Povlsen SERVAL_P(24, NONE, NONE, NONE); 4486e6347e2SLars Povlsen SERVAL_P(25, NONE, NONE, NONE); 4496e6347e2SLars Povlsen SERVAL_P(26, UART, NONE, NONE); 4506e6347e2SLars Povlsen SERVAL_P(27, UART, NONE, NONE); 4516e6347e2SLars Povlsen SERVAL_P(28, IRQ0, NONE, NONE); 4526e6347e2SLars Povlsen SERVAL_P(29, IRQ1, NONE, NONE); 4536e6347e2SLars Povlsen SERVAL_P(30, PTP0, NONE, NONE); 4546e6347e2SLars Povlsen SERVAL_P(31, PTP0, NONE, NONE); 4556e6347e2SLars Povlsen 4566e6347e2SLars Povlsen #define SERVAL_PIN(n) { \ 4576e6347e2SLars Povlsen .number = n, \ 4586e6347e2SLars Povlsen .name = "GPIO_"#n, \ 4596e6347e2SLars Povlsen .drv_data = &serval_pin_##n \ 4606e6347e2SLars Povlsen } 4616e6347e2SLars Povlsen 4626e6347e2SLars Povlsen static const struct pinctrl_pin_desc serval_pins[] = { 4636e6347e2SLars Povlsen SERVAL_PIN(0), 4646e6347e2SLars Povlsen SERVAL_PIN(1), 4656e6347e2SLars Povlsen SERVAL_PIN(2), 4666e6347e2SLars Povlsen SERVAL_PIN(3), 4676e6347e2SLars Povlsen SERVAL_PIN(4), 4686e6347e2SLars Povlsen SERVAL_PIN(5), 4696e6347e2SLars Povlsen SERVAL_PIN(6), 4706e6347e2SLars Povlsen SERVAL_PIN(7), 4716e6347e2SLars Povlsen SERVAL_PIN(8), 4726e6347e2SLars Povlsen SERVAL_PIN(9), 4736e6347e2SLars Povlsen SERVAL_PIN(10), 4746e6347e2SLars Povlsen SERVAL_PIN(11), 4756e6347e2SLars Povlsen SERVAL_PIN(12), 4766e6347e2SLars Povlsen SERVAL_PIN(13), 4776e6347e2SLars Povlsen SERVAL_PIN(14), 4786e6347e2SLars Povlsen SERVAL_PIN(15), 4796e6347e2SLars Povlsen SERVAL_PIN(16), 4806e6347e2SLars Povlsen SERVAL_PIN(17), 4816e6347e2SLars Povlsen SERVAL_PIN(18), 4826e6347e2SLars Povlsen SERVAL_PIN(19), 4836e6347e2SLars Povlsen SERVAL_PIN(20), 4846e6347e2SLars Povlsen SERVAL_PIN(21), 4856e6347e2SLars Povlsen SERVAL_PIN(22), 4866e6347e2SLars Povlsen SERVAL_PIN(23), 4876e6347e2SLars Povlsen SERVAL_PIN(24), 4886e6347e2SLars Povlsen SERVAL_PIN(25), 4896e6347e2SLars Povlsen SERVAL_PIN(26), 4906e6347e2SLars Povlsen SERVAL_PIN(27), 4916e6347e2SLars Povlsen SERVAL_PIN(28), 4926e6347e2SLars Povlsen SERVAL_PIN(29), 4936e6347e2SLars Povlsen SERVAL_PIN(30), 4946e6347e2SLars Povlsen SERVAL_PIN(31), 4956e6347e2SLars Povlsen }; 4966e6347e2SLars Povlsen 497ce8dc094SAlexandre Belloni #define OCELOT_P(p, f0, f1, f2) \ 498ce8dc094SAlexandre Belloni static struct ocelot_pin_caps ocelot_pin_##p = { \ 499ce8dc094SAlexandre Belloni .pin = p, \ 500ce8dc094SAlexandre Belloni .functions = { \ 501ce8dc094SAlexandre Belloni FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2, \ 502ce8dc094SAlexandre Belloni }, \ 503ce8dc094SAlexandre Belloni } 504ce8dc094SAlexandre Belloni 505ce8dc094SAlexandre Belloni OCELOT_P(0, SG0, NONE, NONE); 506ce8dc094SAlexandre Belloni OCELOT_P(1, SG0, NONE, NONE); 507ce8dc094SAlexandre Belloni OCELOT_P(2, SG0, NONE, NONE); 508ce8dc094SAlexandre Belloni OCELOT_P(3, SG0, NONE, NONE); 50917f79084SAlexandre Belloni OCELOT_P(4, IRQ0_IN, IRQ0_OUT, TWI_SCL_M); 510ce8dc094SAlexandre Belloni OCELOT_P(5, IRQ1_IN, IRQ1_OUT, PCI_WAKE); 511ce8dc094SAlexandre Belloni OCELOT_P(6, UART, TWI_SCL_M, NONE); 512ce8dc094SAlexandre Belloni OCELOT_P(7, UART, TWI_SCL_M, NONE); 513ce8dc094SAlexandre Belloni OCELOT_P(8, SI, TWI_SCL_M, IRQ0_OUT); 514ce8dc094SAlexandre Belloni OCELOT_P(9, SI, TWI_SCL_M, IRQ1_OUT); 515edc72546SLars Povlsen OCELOT_P(10, PTP2, TWI_SCL_M, SFP); 516edc72546SLars Povlsen OCELOT_P(11, PTP3, TWI_SCL_M, SFP); 517edc72546SLars Povlsen OCELOT_P(12, UART2, TWI_SCL_M, SFP); 518edc72546SLars Povlsen OCELOT_P(13, UART2, TWI_SCL_M, SFP); 519edc72546SLars Povlsen OCELOT_P(14, MIIM, TWI_SCL_M, SFP); 520edc72546SLars Povlsen OCELOT_P(15, MIIM, TWI_SCL_M, SFP); 521ce8dc094SAlexandre Belloni OCELOT_P(16, TWI, NONE, SI); 522ce8dc094SAlexandre Belloni OCELOT_P(17, TWI, TWI_SCL_M, SI); 523ce8dc094SAlexandre Belloni OCELOT_P(18, PTP0, TWI_SCL_M, NONE); 524ce8dc094SAlexandre Belloni OCELOT_P(19, PTP1, TWI_SCL_M, NONE); 525edc72546SLars Povlsen OCELOT_P(20, RECO_CLK, TACHO, TWI_SCL_M); 526edc72546SLars Povlsen OCELOT_P(21, RECO_CLK, PWM, TWI_SCL_M); 527ce8dc094SAlexandre Belloni 528ce8dc094SAlexandre Belloni #define OCELOT_PIN(n) { \ 529ce8dc094SAlexandre Belloni .number = n, \ 530ce8dc094SAlexandre Belloni .name = "GPIO_"#n, \ 531ce8dc094SAlexandre Belloni .drv_data = &ocelot_pin_##n \ 532ce8dc094SAlexandre Belloni } 533ce8dc094SAlexandre Belloni 534ce8dc094SAlexandre Belloni static const struct pinctrl_pin_desc ocelot_pins[] = { 535ce8dc094SAlexandre Belloni OCELOT_PIN(0), 536ce8dc094SAlexandre Belloni OCELOT_PIN(1), 537ce8dc094SAlexandre Belloni OCELOT_PIN(2), 538ce8dc094SAlexandre Belloni OCELOT_PIN(3), 539ce8dc094SAlexandre Belloni OCELOT_PIN(4), 540ce8dc094SAlexandre Belloni OCELOT_PIN(5), 541ce8dc094SAlexandre Belloni OCELOT_PIN(6), 542ce8dc094SAlexandre Belloni OCELOT_PIN(7), 543ce8dc094SAlexandre Belloni OCELOT_PIN(8), 544ce8dc094SAlexandre Belloni OCELOT_PIN(9), 545ce8dc094SAlexandre Belloni OCELOT_PIN(10), 546ce8dc094SAlexandre Belloni OCELOT_PIN(11), 547ce8dc094SAlexandre Belloni OCELOT_PIN(12), 548ce8dc094SAlexandre Belloni OCELOT_PIN(13), 549ce8dc094SAlexandre Belloni OCELOT_PIN(14), 550ce8dc094SAlexandre Belloni OCELOT_PIN(15), 551ce8dc094SAlexandre Belloni OCELOT_PIN(16), 552ce8dc094SAlexandre Belloni OCELOT_PIN(17), 553ce8dc094SAlexandre Belloni OCELOT_PIN(18), 554ce8dc094SAlexandre Belloni OCELOT_PIN(19), 555ce8dc094SAlexandre Belloni OCELOT_PIN(20), 556ce8dc094SAlexandre Belloni OCELOT_PIN(21), 557ce8dc094SAlexandre Belloni }; 558ce8dc094SAlexandre Belloni 559da801ab5SAlexandre Belloni #define JAGUAR2_P(p, f0, f1) \ 560da801ab5SAlexandre Belloni static struct ocelot_pin_caps jaguar2_pin_##p = { \ 561da801ab5SAlexandre Belloni .pin = p, \ 562da801ab5SAlexandre Belloni .functions = { \ 563da801ab5SAlexandre Belloni FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_NONE \ 564da801ab5SAlexandre Belloni }, \ 565da801ab5SAlexandre Belloni } 566da801ab5SAlexandre Belloni 567da801ab5SAlexandre Belloni JAGUAR2_P(0, SG0, NONE); 568da801ab5SAlexandre Belloni JAGUAR2_P(1, SG0, NONE); 569da801ab5SAlexandre Belloni JAGUAR2_P(2, SG0, NONE); 570da801ab5SAlexandre Belloni JAGUAR2_P(3, SG0, NONE); 571da801ab5SAlexandre Belloni JAGUAR2_P(4, SG1, NONE); 572da801ab5SAlexandre Belloni JAGUAR2_P(5, SG1, NONE); 573da801ab5SAlexandre Belloni JAGUAR2_P(6, IRQ0_IN, IRQ0_OUT); 574da801ab5SAlexandre Belloni JAGUAR2_P(7, IRQ1_IN, IRQ1_OUT); 575da801ab5SAlexandre Belloni JAGUAR2_P(8, PTP0, NONE); 576da801ab5SAlexandre Belloni JAGUAR2_P(9, PTP1, NONE); 577da801ab5SAlexandre Belloni JAGUAR2_P(10, UART, NONE); 578da801ab5SAlexandre Belloni JAGUAR2_P(11, UART, NONE); 579da801ab5SAlexandre Belloni JAGUAR2_P(12, SG1, NONE); 580da801ab5SAlexandre Belloni JAGUAR2_P(13, SG1, NONE); 581da801ab5SAlexandre Belloni JAGUAR2_P(14, TWI, TWI_SCL_M); 582da801ab5SAlexandre Belloni JAGUAR2_P(15, TWI, NONE); 583da801ab5SAlexandre Belloni JAGUAR2_P(16, SI, TWI_SCL_M); 584da801ab5SAlexandre Belloni JAGUAR2_P(17, SI, TWI_SCL_M); 585da801ab5SAlexandre Belloni JAGUAR2_P(18, SI, TWI_SCL_M); 586da801ab5SAlexandre Belloni JAGUAR2_P(19, PCI_WAKE, NONE); 587da801ab5SAlexandre Belloni JAGUAR2_P(20, IRQ0_OUT, TWI_SCL_M); 588da801ab5SAlexandre Belloni JAGUAR2_P(21, IRQ1_OUT, TWI_SCL_M); 589da801ab5SAlexandre Belloni JAGUAR2_P(22, TACHO, NONE); 590da801ab5SAlexandre Belloni JAGUAR2_P(23, PWM, NONE); 591da801ab5SAlexandre Belloni JAGUAR2_P(24, UART2, NONE); 592da801ab5SAlexandre Belloni JAGUAR2_P(25, UART2, SI); 593da801ab5SAlexandre Belloni JAGUAR2_P(26, PTP2, SI); 594da801ab5SAlexandre Belloni JAGUAR2_P(27, PTP3, SI); 595da801ab5SAlexandre Belloni JAGUAR2_P(28, TWI2, SI); 596da801ab5SAlexandre Belloni JAGUAR2_P(29, TWI2, SI); 597da801ab5SAlexandre Belloni JAGUAR2_P(30, SG2, SI); 598da801ab5SAlexandre Belloni JAGUAR2_P(31, SG2, SI); 599da801ab5SAlexandre Belloni JAGUAR2_P(32, SG2, SI); 600da801ab5SAlexandre Belloni JAGUAR2_P(33, SG2, SI); 601da801ab5SAlexandre Belloni JAGUAR2_P(34, NONE, TWI_SCL_M); 602da801ab5SAlexandre Belloni JAGUAR2_P(35, NONE, TWI_SCL_M); 603da801ab5SAlexandre Belloni JAGUAR2_P(36, NONE, TWI_SCL_M); 604da801ab5SAlexandre Belloni JAGUAR2_P(37, NONE, TWI_SCL_M); 605da801ab5SAlexandre Belloni JAGUAR2_P(38, NONE, TWI_SCL_M); 606da801ab5SAlexandre Belloni JAGUAR2_P(39, NONE, TWI_SCL_M); 607da801ab5SAlexandre Belloni JAGUAR2_P(40, NONE, TWI_SCL_M); 608da801ab5SAlexandre Belloni JAGUAR2_P(41, NONE, TWI_SCL_M); 609da801ab5SAlexandre Belloni JAGUAR2_P(42, NONE, TWI_SCL_M); 610da801ab5SAlexandre Belloni JAGUAR2_P(43, NONE, TWI_SCL_M); 611edc72546SLars Povlsen JAGUAR2_P(44, NONE, SFP); 612edc72546SLars Povlsen JAGUAR2_P(45, NONE, SFP); 613edc72546SLars Povlsen JAGUAR2_P(46, NONE, SFP); 614edc72546SLars Povlsen JAGUAR2_P(47, NONE, SFP); 615edc72546SLars Povlsen JAGUAR2_P(48, SFP, NONE); 616edc72546SLars Povlsen JAGUAR2_P(49, SFP, SI); 617edc72546SLars Povlsen JAGUAR2_P(50, SFP, SI); 618edc72546SLars Povlsen JAGUAR2_P(51, SFP, SI); 619edc72546SLars Povlsen JAGUAR2_P(52, SFP, NONE); 620edc72546SLars Povlsen JAGUAR2_P(53, SFP, NONE); 621edc72546SLars Povlsen JAGUAR2_P(54, SFP, NONE); 622edc72546SLars Povlsen JAGUAR2_P(55, SFP, NONE); 623edc72546SLars Povlsen JAGUAR2_P(56, MIIM, SFP); 624edc72546SLars Povlsen JAGUAR2_P(57, MIIM, SFP); 625edc72546SLars Povlsen JAGUAR2_P(58, MIIM, SFP); 626edc72546SLars Povlsen JAGUAR2_P(59, MIIM, SFP); 627da801ab5SAlexandre Belloni JAGUAR2_P(60, NONE, NONE); 628da801ab5SAlexandre Belloni JAGUAR2_P(61, NONE, NONE); 629da801ab5SAlexandre Belloni JAGUAR2_P(62, NONE, NONE); 630da801ab5SAlexandre Belloni JAGUAR2_P(63, NONE, NONE); 631da801ab5SAlexandre Belloni 632da801ab5SAlexandre Belloni #define JAGUAR2_PIN(n) { \ 633da801ab5SAlexandre Belloni .number = n, \ 634da801ab5SAlexandre Belloni .name = "GPIO_"#n, \ 635da801ab5SAlexandre Belloni .drv_data = &jaguar2_pin_##n \ 636da801ab5SAlexandre Belloni } 637da801ab5SAlexandre Belloni 638da801ab5SAlexandre Belloni static const struct pinctrl_pin_desc jaguar2_pins[] = { 639da801ab5SAlexandre Belloni JAGUAR2_PIN(0), 640da801ab5SAlexandre Belloni JAGUAR2_PIN(1), 641da801ab5SAlexandre Belloni JAGUAR2_PIN(2), 642da801ab5SAlexandre Belloni JAGUAR2_PIN(3), 643da801ab5SAlexandre Belloni JAGUAR2_PIN(4), 644da801ab5SAlexandre Belloni JAGUAR2_PIN(5), 645da801ab5SAlexandre Belloni JAGUAR2_PIN(6), 646da801ab5SAlexandre Belloni JAGUAR2_PIN(7), 647da801ab5SAlexandre Belloni JAGUAR2_PIN(8), 648da801ab5SAlexandre Belloni JAGUAR2_PIN(9), 649da801ab5SAlexandre Belloni JAGUAR2_PIN(10), 650da801ab5SAlexandre Belloni JAGUAR2_PIN(11), 651da801ab5SAlexandre Belloni JAGUAR2_PIN(12), 652da801ab5SAlexandre Belloni JAGUAR2_PIN(13), 653da801ab5SAlexandre Belloni JAGUAR2_PIN(14), 654da801ab5SAlexandre Belloni JAGUAR2_PIN(15), 655da801ab5SAlexandre Belloni JAGUAR2_PIN(16), 656da801ab5SAlexandre Belloni JAGUAR2_PIN(17), 657da801ab5SAlexandre Belloni JAGUAR2_PIN(18), 658da801ab5SAlexandre Belloni JAGUAR2_PIN(19), 659da801ab5SAlexandre Belloni JAGUAR2_PIN(20), 660da801ab5SAlexandre Belloni JAGUAR2_PIN(21), 661da801ab5SAlexandre Belloni JAGUAR2_PIN(22), 662da801ab5SAlexandre Belloni JAGUAR2_PIN(23), 663da801ab5SAlexandre Belloni JAGUAR2_PIN(24), 664da801ab5SAlexandre Belloni JAGUAR2_PIN(25), 665da801ab5SAlexandre Belloni JAGUAR2_PIN(26), 666da801ab5SAlexandre Belloni JAGUAR2_PIN(27), 667da801ab5SAlexandre Belloni JAGUAR2_PIN(28), 668da801ab5SAlexandre Belloni JAGUAR2_PIN(29), 669da801ab5SAlexandre Belloni JAGUAR2_PIN(30), 670da801ab5SAlexandre Belloni JAGUAR2_PIN(31), 671da801ab5SAlexandre Belloni JAGUAR2_PIN(32), 672da801ab5SAlexandre Belloni JAGUAR2_PIN(33), 673da801ab5SAlexandre Belloni JAGUAR2_PIN(34), 674da801ab5SAlexandre Belloni JAGUAR2_PIN(35), 675da801ab5SAlexandre Belloni JAGUAR2_PIN(36), 676da801ab5SAlexandre Belloni JAGUAR2_PIN(37), 677da801ab5SAlexandre Belloni JAGUAR2_PIN(38), 678da801ab5SAlexandre Belloni JAGUAR2_PIN(39), 679da801ab5SAlexandre Belloni JAGUAR2_PIN(40), 680da801ab5SAlexandre Belloni JAGUAR2_PIN(41), 681da801ab5SAlexandre Belloni JAGUAR2_PIN(42), 682da801ab5SAlexandre Belloni JAGUAR2_PIN(43), 683da801ab5SAlexandre Belloni JAGUAR2_PIN(44), 684da801ab5SAlexandre Belloni JAGUAR2_PIN(45), 685da801ab5SAlexandre Belloni JAGUAR2_PIN(46), 686da801ab5SAlexandre Belloni JAGUAR2_PIN(47), 687da801ab5SAlexandre Belloni JAGUAR2_PIN(48), 688da801ab5SAlexandre Belloni JAGUAR2_PIN(49), 689da801ab5SAlexandre Belloni JAGUAR2_PIN(50), 690da801ab5SAlexandre Belloni JAGUAR2_PIN(51), 691da801ab5SAlexandre Belloni JAGUAR2_PIN(52), 692da801ab5SAlexandre Belloni JAGUAR2_PIN(53), 693da801ab5SAlexandre Belloni JAGUAR2_PIN(54), 694da801ab5SAlexandre Belloni JAGUAR2_PIN(55), 695da801ab5SAlexandre Belloni JAGUAR2_PIN(56), 696da801ab5SAlexandre Belloni JAGUAR2_PIN(57), 697da801ab5SAlexandre Belloni JAGUAR2_PIN(58), 698da801ab5SAlexandre Belloni JAGUAR2_PIN(59), 699da801ab5SAlexandre Belloni JAGUAR2_PIN(60), 700da801ab5SAlexandre Belloni JAGUAR2_PIN(61), 701da801ab5SAlexandre Belloni JAGUAR2_PIN(62), 702da801ab5SAlexandre Belloni JAGUAR2_PIN(63), 703da801ab5SAlexandre Belloni }; 704da801ab5SAlexandre Belloni 7058fc0bfcdSHoratiu Vultur #define SERVALT_P(p, f0, f1, f2) \ 7068fc0bfcdSHoratiu Vultur static struct ocelot_pin_caps servalt_pin_##p = { \ 7078fc0bfcdSHoratiu Vultur .pin = p, \ 7088fc0bfcdSHoratiu Vultur .functions = { \ 7098fc0bfcdSHoratiu Vultur FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2 \ 7108fc0bfcdSHoratiu Vultur }, \ 7118fc0bfcdSHoratiu Vultur } 7128fc0bfcdSHoratiu Vultur 7138fc0bfcdSHoratiu Vultur SERVALT_P(0, SG0, NONE, NONE); 7148fc0bfcdSHoratiu Vultur SERVALT_P(1, SG0, NONE, NONE); 7158fc0bfcdSHoratiu Vultur SERVALT_P(2, SG0, NONE, NONE); 7168fc0bfcdSHoratiu Vultur SERVALT_P(3, SG0, NONE, NONE); 7178fc0bfcdSHoratiu Vultur SERVALT_P(4, IRQ0_IN, IRQ0_OUT, TWI_SCL_M); 7188fc0bfcdSHoratiu Vultur SERVALT_P(5, IRQ1_IN, IRQ1_OUT, TWI_SCL_M); 7198fc0bfcdSHoratiu Vultur SERVALT_P(6, UART, NONE, NONE); 7208fc0bfcdSHoratiu Vultur SERVALT_P(7, UART, NONE, NONE); 7218fc0bfcdSHoratiu Vultur SERVALT_P(8, SI, SFP, TWI_SCL_M); 7228fc0bfcdSHoratiu Vultur SERVALT_P(9, PCI_WAKE, SFP, SI); 7238fc0bfcdSHoratiu Vultur SERVALT_P(10, PTP0, SFP, TWI_SCL_M); 7248fc0bfcdSHoratiu Vultur SERVALT_P(11, PTP1, SFP, TWI_SCL_M); 7258fc0bfcdSHoratiu Vultur SERVALT_P(12, REF_CLK, SFP, TWI_SCL_M); 7268fc0bfcdSHoratiu Vultur SERVALT_P(13, REF_CLK, SFP, TWI_SCL_M); 7278fc0bfcdSHoratiu Vultur SERVALT_P(14, REF_CLK, IRQ0_OUT, SI); 7288fc0bfcdSHoratiu Vultur SERVALT_P(15, REF_CLK, IRQ1_OUT, SI); 7298fc0bfcdSHoratiu Vultur SERVALT_P(16, TACHO, SFP, SI); 7308fc0bfcdSHoratiu Vultur SERVALT_P(17, PWM, NONE, TWI_SCL_M); 7318fc0bfcdSHoratiu Vultur SERVALT_P(18, PTP2, SFP, SI); 7328fc0bfcdSHoratiu Vultur SERVALT_P(19, PTP3, SFP, SI); 7338fc0bfcdSHoratiu Vultur SERVALT_P(20, UART2, SFP, SI); 7348fc0bfcdSHoratiu Vultur SERVALT_P(21, UART2, NONE, NONE); 7358fc0bfcdSHoratiu Vultur SERVALT_P(22, MIIM, SFP, TWI2); 7368fc0bfcdSHoratiu Vultur SERVALT_P(23, MIIM, SFP, TWI2); 7378fc0bfcdSHoratiu Vultur SERVALT_P(24, TWI, NONE, NONE); 7388fc0bfcdSHoratiu Vultur SERVALT_P(25, TWI, SFP, TWI_SCL_M); 7398fc0bfcdSHoratiu Vultur SERVALT_P(26, TWI_SCL_M, SFP, SI); 7408fc0bfcdSHoratiu Vultur SERVALT_P(27, TWI_SCL_M, SFP, SI); 7418fc0bfcdSHoratiu Vultur SERVALT_P(28, TWI_SCL_M, SFP, SI); 7428fc0bfcdSHoratiu Vultur SERVALT_P(29, TWI_SCL_M, NONE, NONE); 7438fc0bfcdSHoratiu Vultur SERVALT_P(30, TWI_SCL_M, NONE, NONE); 7448fc0bfcdSHoratiu Vultur SERVALT_P(31, TWI_SCL_M, NONE, NONE); 7458fc0bfcdSHoratiu Vultur SERVALT_P(32, TWI_SCL_M, NONE, NONE); 7468fc0bfcdSHoratiu Vultur SERVALT_P(33, RCVRD_CLK, NONE, NONE); 7478fc0bfcdSHoratiu Vultur SERVALT_P(34, RCVRD_CLK, NONE, NONE); 7488fc0bfcdSHoratiu Vultur SERVALT_P(35, RCVRD_CLK, NONE, NONE); 7498fc0bfcdSHoratiu Vultur SERVALT_P(36, RCVRD_CLK, NONE, NONE); 7508fc0bfcdSHoratiu Vultur 7518fc0bfcdSHoratiu Vultur #define SERVALT_PIN(n) { \ 7528fc0bfcdSHoratiu Vultur .number = n, \ 7538fc0bfcdSHoratiu Vultur .name = "GPIO_"#n, \ 7548fc0bfcdSHoratiu Vultur .drv_data = &servalt_pin_##n \ 7558fc0bfcdSHoratiu Vultur } 7568fc0bfcdSHoratiu Vultur 7578fc0bfcdSHoratiu Vultur static const struct pinctrl_pin_desc servalt_pins[] = { 7588fc0bfcdSHoratiu Vultur SERVALT_PIN(0), 7598fc0bfcdSHoratiu Vultur SERVALT_PIN(1), 7608fc0bfcdSHoratiu Vultur SERVALT_PIN(2), 7618fc0bfcdSHoratiu Vultur SERVALT_PIN(3), 7628fc0bfcdSHoratiu Vultur SERVALT_PIN(4), 7638fc0bfcdSHoratiu Vultur SERVALT_PIN(5), 7648fc0bfcdSHoratiu Vultur SERVALT_PIN(6), 7658fc0bfcdSHoratiu Vultur SERVALT_PIN(7), 7668fc0bfcdSHoratiu Vultur SERVALT_PIN(8), 7678fc0bfcdSHoratiu Vultur SERVALT_PIN(9), 7688fc0bfcdSHoratiu Vultur SERVALT_PIN(10), 7698fc0bfcdSHoratiu Vultur SERVALT_PIN(11), 7708fc0bfcdSHoratiu Vultur SERVALT_PIN(12), 7718fc0bfcdSHoratiu Vultur SERVALT_PIN(13), 7728fc0bfcdSHoratiu Vultur SERVALT_PIN(14), 7738fc0bfcdSHoratiu Vultur SERVALT_PIN(15), 7748fc0bfcdSHoratiu Vultur SERVALT_PIN(16), 7758fc0bfcdSHoratiu Vultur SERVALT_PIN(17), 7768fc0bfcdSHoratiu Vultur SERVALT_PIN(18), 7778fc0bfcdSHoratiu Vultur SERVALT_PIN(19), 7788fc0bfcdSHoratiu Vultur SERVALT_PIN(20), 7798fc0bfcdSHoratiu Vultur SERVALT_PIN(21), 7808fc0bfcdSHoratiu Vultur SERVALT_PIN(22), 7818fc0bfcdSHoratiu Vultur SERVALT_PIN(23), 7828fc0bfcdSHoratiu Vultur SERVALT_PIN(24), 7838fc0bfcdSHoratiu Vultur SERVALT_PIN(25), 7848fc0bfcdSHoratiu Vultur SERVALT_PIN(26), 7858fc0bfcdSHoratiu Vultur SERVALT_PIN(27), 7868fc0bfcdSHoratiu Vultur SERVALT_PIN(28), 7878fc0bfcdSHoratiu Vultur SERVALT_PIN(29), 7888fc0bfcdSHoratiu Vultur SERVALT_PIN(30), 7898fc0bfcdSHoratiu Vultur SERVALT_PIN(31), 7908fc0bfcdSHoratiu Vultur SERVALT_PIN(32), 7918fc0bfcdSHoratiu Vultur SERVALT_PIN(33), 7928fc0bfcdSHoratiu Vultur SERVALT_PIN(34), 7938fc0bfcdSHoratiu Vultur SERVALT_PIN(35), 7948fc0bfcdSHoratiu Vultur SERVALT_PIN(36), 7958fc0bfcdSHoratiu Vultur }; 7968fc0bfcdSHoratiu Vultur 797f8a74760SLars Povlsen #define SPARX5_P(p, f0, f1, f2) \ 798f8a74760SLars Povlsen static struct ocelot_pin_caps sparx5_pin_##p = { \ 799f8a74760SLars Povlsen .pin = p, \ 800f8a74760SLars Povlsen .functions = { \ 801f8a74760SLars Povlsen FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2 \ 802f8a74760SLars Povlsen }, \ 803f8a74760SLars Povlsen } 804f8a74760SLars Povlsen 805f8a74760SLars Povlsen SPARX5_P(0, SG0, PLL_STAT, NONE); 806f8a74760SLars Povlsen SPARX5_P(1, SG0, NONE, NONE); 807f8a74760SLars Povlsen SPARX5_P(2, SG0, NONE, NONE); 808f8a74760SLars Povlsen SPARX5_P(3, SG0, NONE, NONE); 809f8a74760SLars Povlsen SPARX5_P(4, SG1, NONE, NONE); 810f8a74760SLars Povlsen SPARX5_P(5, SG1, NONE, NONE); 811f8a74760SLars Povlsen SPARX5_P(6, IRQ0_IN, IRQ0_OUT, SFP); 812f8a74760SLars Povlsen SPARX5_P(7, IRQ1_IN, IRQ1_OUT, SFP); 813f8a74760SLars Povlsen SPARX5_P(8, PTP0, NONE, SFP); 814f8a74760SLars Povlsen SPARX5_P(9, PTP1, SFP, TWI_SCL_M); 815f8a74760SLars Povlsen SPARX5_P(10, UART, NONE, NONE); 816f8a74760SLars Povlsen SPARX5_P(11, UART, NONE, NONE); 817f8a74760SLars Povlsen SPARX5_P(12, SG1, NONE, NONE); 818f8a74760SLars Povlsen SPARX5_P(13, SG1, NONE, NONE); 819f8a74760SLars Povlsen SPARX5_P(14, TWI, TWI_SCL_M, NONE); 820f8a74760SLars Povlsen SPARX5_P(15, TWI, NONE, NONE); 821f8a74760SLars Povlsen SPARX5_P(16, SI, TWI_SCL_M, SFP); 822f8a74760SLars Povlsen SPARX5_P(17, SI, TWI_SCL_M, SFP); 823f8a74760SLars Povlsen SPARX5_P(18, SI, TWI_SCL_M, SFP); 824f8a74760SLars Povlsen SPARX5_P(19, PCI_WAKE, TWI_SCL_M, SFP); 825f8a74760SLars Povlsen SPARX5_P(20, IRQ0_OUT, TWI_SCL_M, SFP); 826f8a74760SLars Povlsen SPARX5_P(21, IRQ1_OUT, TACHO, SFP); 827f8a74760SLars Povlsen SPARX5_P(22, TACHO, IRQ0_OUT, TWI_SCL_M); 828f8a74760SLars Povlsen SPARX5_P(23, PWM, UART3, TWI_SCL_M); 829f8a74760SLars Povlsen SPARX5_P(24, PTP2, UART3, TWI_SCL_M); 830f8a74760SLars Povlsen SPARX5_P(25, PTP3, SI, TWI_SCL_M); 831f8a74760SLars Povlsen SPARX5_P(26, UART2, SI, TWI_SCL_M); 832f8a74760SLars Povlsen SPARX5_P(27, UART2, SI, TWI_SCL_M); 833f8a74760SLars Povlsen SPARX5_P(28, TWI2, SI, SFP); 834f8a74760SLars Povlsen SPARX5_P(29, TWI2, SI, SFP); 835f8a74760SLars Povlsen SPARX5_P(30, SG2, SI, PWM); 836f8a74760SLars Povlsen SPARX5_P(31, SG2, SI, TWI_SCL_M); 837f8a74760SLars Povlsen SPARX5_P(32, SG2, SI, TWI_SCL_M); 838f8a74760SLars Povlsen SPARX5_P(33, SG2, SI, SFP); 839f8a74760SLars Povlsen SPARX5_P(34, NONE, TWI_SCL_M, EMMC); 840f8a74760SLars Povlsen SPARX5_P(35, SFP, TWI_SCL_M, EMMC); 841f8a74760SLars Povlsen SPARX5_P(36, SFP, TWI_SCL_M, EMMC); 842f8a74760SLars Povlsen SPARX5_P(37, SFP, NONE, EMMC); 843f8a74760SLars Povlsen SPARX5_P(38, NONE, TWI_SCL_M, EMMC); 844f8a74760SLars Povlsen SPARX5_P(39, SI2, TWI_SCL_M, EMMC); 845f8a74760SLars Povlsen SPARX5_P(40, SI2, TWI_SCL_M, EMMC); 846f8a74760SLars Povlsen SPARX5_P(41, SI2, TWI_SCL_M, EMMC); 847f8a74760SLars Povlsen SPARX5_P(42, SI2, TWI_SCL_M, EMMC); 848f8a74760SLars Povlsen SPARX5_P(43, SI2, TWI_SCL_M, EMMC); 849f8a74760SLars Povlsen SPARX5_P(44, SI, SFP, EMMC); 850f8a74760SLars Povlsen SPARX5_P(45, SI, SFP, EMMC); 851f8a74760SLars Povlsen SPARX5_P(46, NONE, SFP, EMMC); 852f8a74760SLars Povlsen SPARX5_P(47, NONE, SFP, EMMC); 853f8a74760SLars Povlsen SPARX5_P(48, TWI3, SI, SFP); 854f8a74760SLars Povlsen SPARX5_P(49, TWI3, NONE, SFP); 855f8a74760SLars Povlsen SPARX5_P(50, SFP, NONE, TWI_SCL_M); 856f8a74760SLars Povlsen SPARX5_P(51, SFP, SI, TWI_SCL_M); 857f8a74760SLars Povlsen SPARX5_P(52, SFP, MIIM, TWI_SCL_M); 858f8a74760SLars Povlsen SPARX5_P(53, SFP, MIIM, TWI_SCL_M); 859f8a74760SLars Povlsen SPARX5_P(54, SFP, PTP2, TWI_SCL_M); 860f8a74760SLars Povlsen SPARX5_P(55, SFP, PTP3, PCI_WAKE); 861f8a74760SLars Povlsen SPARX5_P(56, MIIM, SFP, TWI_SCL_M); 862f8a74760SLars Povlsen SPARX5_P(57, MIIM, SFP, TWI_SCL_M); 863f8a74760SLars Povlsen SPARX5_P(58, MIIM, SFP, TWI_SCL_M); 864f8a74760SLars Povlsen SPARX5_P(59, MIIM, SFP, NONE); 865f8a74760SLars Povlsen SPARX5_P(60, RECO_CLK, NONE, NONE); 866f8a74760SLars Povlsen SPARX5_P(61, RECO_CLK, NONE, NONE); 867f8a74760SLars Povlsen SPARX5_P(62, RECO_CLK, PLL_STAT, NONE); 868f8a74760SLars Povlsen SPARX5_P(63, RECO_CLK, NONE, NONE); 869f8a74760SLars Povlsen 870f8a74760SLars Povlsen #define SPARX5_PIN(n) { \ 871f8a74760SLars Povlsen .number = n, \ 872f8a74760SLars Povlsen .name = "GPIO_"#n, \ 873f8a74760SLars Povlsen .drv_data = &sparx5_pin_##n \ 874f8a74760SLars Povlsen } 875f8a74760SLars Povlsen 876f8a74760SLars Povlsen static const struct pinctrl_pin_desc sparx5_pins[] = { 877f8a74760SLars Povlsen SPARX5_PIN(0), 878f8a74760SLars Povlsen SPARX5_PIN(1), 879f8a74760SLars Povlsen SPARX5_PIN(2), 880f8a74760SLars Povlsen SPARX5_PIN(3), 881f8a74760SLars Povlsen SPARX5_PIN(4), 882f8a74760SLars Povlsen SPARX5_PIN(5), 883f8a74760SLars Povlsen SPARX5_PIN(6), 884f8a74760SLars Povlsen SPARX5_PIN(7), 885f8a74760SLars Povlsen SPARX5_PIN(8), 886f8a74760SLars Povlsen SPARX5_PIN(9), 887f8a74760SLars Povlsen SPARX5_PIN(10), 888f8a74760SLars Povlsen SPARX5_PIN(11), 889f8a74760SLars Povlsen SPARX5_PIN(12), 890f8a74760SLars Povlsen SPARX5_PIN(13), 891f8a74760SLars Povlsen SPARX5_PIN(14), 892f8a74760SLars Povlsen SPARX5_PIN(15), 893f8a74760SLars Povlsen SPARX5_PIN(16), 894f8a74760SLars Povlsen SPARX5_PIN(17), 895f8a74760SLars Povlsen SPARX5_PIN(18), 896f8a74760SLars Povlsen SPARX5_PIN(19), 897f8a74760SLars Povlsen SPARX5_PIN(20), 898f8a74760SLars Povlsen SPARX5_PIN(21), 899f8a74760SLars Povlsen SPARX5_PIN(22), 900f8a74760SLars Povlsen SPARX5_PIN(23), 901f8a74760SLars Povlsen SPARX5_PIN(24), 902f8a74760SLars Povlsen SPARX5_PIN(25), 903f8a74760SLars Povlsen SPARX5_PIN(26), 904f8a74760SLars Povlsen SPARX5_PIN(27), 905f8a74760SLars Povlsen SPARX5_PIN(28), 906f8a74760SLars Povlsen SPARX5_PIN(29), 907f8a74760SLars Povlsen SPARX5_PIN(30), 908f8a74760SLars Povlsen SPARX5_PIN(31), 909f8a74760SLars Povlsen SPARX5_PIN(32), 910f8a74760SLars Povlsen SPARX5_PIN(33), 911f8a74760SLars Povlsen SPARX5_PIN(34), 912f8a74760SLars Povlsen SPARX5_PIN(35), 913f8a74760SLars Povlsen SPARX5_PIN(36), 914f8a74760SLars Povlsen SPARX5_PIN(37), 915f8a74760SLars Povlsen SPARX5_PIN(38), 916f8a74760SLars Povlsen SPARX5_PIN(39), 917f8a74760SLars Povlsen SPARX5_PIN(40), 918f8a74760SLars Povlsen SPARX5_PIN(41), 919f8a74760SLars Povlsen SPARX5_PIN(42), 920f8a74760SLars Povlsen SPARX5_PIN(43), 921f8a74760SLars Povlsen SPARX5_PIN(44), 922f8a74760SLars Povlsen SPARX5_PIN(45), 923f8a74760SLars Povlsen SPARX5_PIN(46), 924f8a74760SLars Povlsen SPARX5_PIN(47), 925f8a74760SLars Povlsen SPARX5_PIN(48), 926f8a74760SLars Povlsen SPARX5_PIN(49), 927f8a74760SLars Povlsen SPARX5_PIN(50), 928f8a74760SLars Povlsen SPARX5_PIN(51), 929f8a74760SLars Povlsen SPARX5_PIN(52), 930f8a74760SLars Povlsen SPARX5_PIN(53), 931f8a74760SLars Povlsen SPARX5_PIN(54), 932f8a74760SLars Povlsen SPARX5_PIN(55), 933f8a74760SLars Povlsen SPARX5_PIN(56), 934f8a74760SLars Povlsen SPARX5_PIN(57), 935f8a74760SLars Povlsen SPARX5_PIN(58), 936f8a74760SLars Povlsen SPARX5_PIN(59), 937f8a74760SLars Povlsen SPARX5_PIN(60), 938f8a74760SLars Povlsen SPARX5_PIN(61), 939f8a74760SLars Povlsen SPARX5_PIN(62), 940f8a74760SLars Povlsen SPARX5_PIN(63), 941f8a74760SLars Povlsen }; 942f8a74760SLars Povlsen 943531d6ab3SKavyasree Kotagiri #define LAN966X_P(p, f0, f1, f2, f3, f4, f5, f6, f7) \ 944531d6ab3SKavyasree Kotagiri static struct ocelot_pin_caps lan966x_pin_##p = { \ 945531d6ab3SKavyasree Kotagiri .pin = p, \ 946531d6ab3SKavyasree Kotagiri .functions = { \ 947531d6ab3SKavyasree Kotagiri FUNC_##f0, FUNC_##f1, FUNC_##f2, \ 948531d6ab3SKavyasree Kotagiri FUNC_##f3 \ 949531d6ab3SKavyasree Kotagiri }, \ 950531d6ab3SKavyasree Kotagiri .a_functions = { \ 951531d6ab3SKavyasree Kotagiri FUNC_##f4, FUNC_##f5, FUNC_##f6, \ 952531d6ab3SKavyasree Kotagiri FUNC_##f7 \ 953531d6ab3SKavyasree Kotagiri }, \ 954531d6ab3SKavyasree Kotagiri } 955531d6ab3SKavyasree Kotagiri 956531d6ab3SKavyasree Kotagiri /* Pinmuxing table taken from data sheet */ 957531d6ab3SKavyasree Kotagiri /* Pin FUNC0 FUNC1 FUNC2 FUNC3 FUNC4 FUNC5 FUNC6 FUNC7 */ 958531d6ab3SKavyasree Kotagiri LAN966X_P(0, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 959531d6ab3SKavyasree Kotagiri LAN966X_P(1, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 960531d6ab3SKavyasree Kotagiri LAN966X_P(2, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 961531d6ab3SKavyasree Kotagiri LAN966X_P(3, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 962531d6ab3SKavyasree Kotagiri LAN966X_P(4, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 963531d6ab3SKavyasree Kotagiri LAN966X_P(5, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 964531d6ab3SKavyasree Kotagiri LAN966X_P(6, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 965531d6ab3SKavyasree Kotagiri LAN966X_P(7, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 966531d6ab3SKavyasree Kotagiri LAN966X_P(8, GPIO, FC0_a, USB_H_b, NONE, USB_S_b, NONE, NONE, R); 967531d6ab3SKavyasree Kotagiri LAN966X_P(9, GPIO, FC0_a, USB_H_b, NONE, NONE, NONE, NONE, R); 968531d6ab3SKavyasree Kotagiri LAN966X_P(10, GPIO, FC0_a, NONE, NONE, NONE, NONE, NONE, R); 969531d6ab3SKavyasree Kotagiri LAN966X_P(11, GPIO, FC1_a, NONE, NONE, NONE, NONE, NONE, R); 970531d6ab3SKavyasree Kotagiri LAN966X_P(12, GPIO, FC1_a, NONE, NONE, NONE, NONE, NONE, R); 971531d6ab3SKavyasree Kotagiri LAN966X_P(13, GPIO, FC1_a, NONE, NONE, NONE, NONE, NONE, R); 972531d6ab3SKavyasree Kotagiri LAN966X_P(14, GPIO, FC2_a, NONE, NONE, NONE, NONE, NONE, R); 973531d6ab3SKavyasree Kotagiri LAN966X_P(15, GPIO, FC2_a, NONE, NONE, NONE, NONE, NONE, R); 974531d6ab3SKavyasree Kotagiri LAN966X_P(16, GPIO, FC2_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, IRQ_OUT_c, R); 975531d6ab3SKavyasree Kotagiri LAN966X_P(17, GPIO, FC3_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, IRQ_OUT_c, R); 976531d6ab3SKavyasree Kotagiri LAN966X_P(18, GPIO, FC3_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, IRQ_OUT_c, R); 977531d6ab3SKavyasree Kotagiri LAN966X_P(19, GPIO, FC3_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, IRQ_OUT_c, R); 978531d6ab3SKavyasree Kotagiri LAN966X_P(20, GPIO, FC4_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, NONE, R); 979531d6ab3SKavyasree Kotagiri LAN966X_P(21, GPIO, FC4_a, NONE, NONE, OB_TRG_a, NONE, NONE, R); 980531d6ab3SKavyasree Kotagiri LAN966X_P(22, GPIO, FC4_a, NONE, NONE, OB_TRG_a, NONE, NONE, R); 981531d6ab3SKavyasree Kotagiri LAN966X_P(23, GPIO, NONE, NONE, NONE, OB_TRG_a, NONE, NONE, R); 982531d6ab3SKavyasree Kotagiri LAN966X_P(24, GPIO, FC0_b, IB_TRG_a, USB_H_c, OB_TRG_a, IRQ_IN_c, TACHO_a, R); 983531d6ab3SKavyasree Kotagiri LAN966X_P(25, GPIO, FC0_b, IB_TRG_a, USB_H_c, OB_TRG_a, IRQ_OUT_c, SFP_SD, R); 984531d6ab3SKavyasree Kotagiri LAN966X_P(26, GPIO, FC0_b, IB_TRG_a, USB_S_c, OB_TRG_a, CAN0_a, SFP_SD, R); 985e97e36cdSMichael Walle LAN966X_P(27, GPIO, NONE, NONE, NONE, OB_TRG_a, CAN0_a, PWM_a, R); 986531d6ab3SKavyasree Kotagiri LAN966X_P(28, GPIO, MIIM_a, NONE, NONE, OB_TRG_a, IRQ_OUT_c, SFP_SD, R); 987531d6ab3SKavyasree Kotagiri LAN966X_P(29, GPIO, MIIM_a, NONE, NONE, OB_TRG_a, NONE, NONE, R); 988bf3e7f49SMichael Walle LAN966X_P(30, GPIO, FC3_c, CAN1, CLKMON, OB_TRG, RECO_b, NONE, R); 989bf3e7f49SMichael Walle LAN966X_P(31, GPIO, FC3_c, CAN1, CLKMON, OB_TRG, RECO_b, NONE, R); 990531d6ab3SKavyasree Kotagiri LAN966X_P(32, GPIO, FC3_c, NONE, SGPIO_a, NONE, MIIM_Sa, NONE, R); 991531d6ab3SKavyasree Kotagiri LAN966X_P(33, GPIO, FC1_b, NONE, SGPIO_a, NONE, MIIM_Sa, MIIM_b, R); 992531d6ab3SKavyasree Kotagiri LAN966X_P(34, GPIO, FC1_b, NONE, SGPIO_a, NONE, MIIM_Sa, MIIM_b, R); 993531d6ab3SKavyasree Kotagiri LAN966X_P(35, GPIO, FC1_b, NONE, SGPIO_a, CAN0_b, NONE, NONE, R); 994531d6ab3SKavyasree Kotagiri LAN966X_P(36, GPIO, NONE, PTPSYNC_1, NONE, CAN0_b, NONE, NONE, R); 995531d6ab3SKavyasree Kotagiri LAN966X_P(37, GPIO, FC_SHRD0, PTPSYNC_2, TWI_SLC_GATE_AD, NONE, NONE, NONE, R); 996531d6ab3SKavyasree Kotagiri LAN966X_P(38, GPIO, NONE, PTPSYNC_3, NONE, NONE, NONE, NONE, R); 997531d6ab3SKavyasree Kotagiri LAN966X_P(39, GPIO, NONE, PTPSYNC_4, NONE, NONE, NONE, NONE, R); 998531d6ab3SKavyasree Kotagiri LAN966X_P(40, GPIO, FC_SHRD1, PTPSYNC_5, NONE, NONE, NONE, NONE, R); 999531d6ab3SKavyasree Kotagiri LAN966X_P(41, GPIO, FC_SHRD2, PTPSYNC_6, TWI_SLC_GATE_AD, NONE, NONE, NONE, R); 1000531d6ab3SKavyasree Kotagiri LAN966X_P(42, GPIO, FC_SHRD3, PTPSYNC_7, TWI_SLC_GATE_AD, NONE, NONE, NONE, R); 1001531d6ab3SKavyasree Kotagiri LAN966X_P(43, GPIO, FC2_b, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, RECO_a, IRQ_IN_a, R); 1002531d6ab3SKavyasree Kotagiri LAN966X_P(44, GPIO, FC2_b, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, RECO_a, IRQ_IN_a, R); 1003531d6ab3SKavyasree Kotagiri LAN966X_P(45, GPIO, FC2_b, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, NONE, IRQ_IN_a, R); 1004531d6ab3SKavyasree Kotagiri LAN966X_P(46, GPIO, FC1_c, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, FC_SHRD4, IRQ_IN_a, R); 1005531d6ab3SKavyasree Kotagiri LAN966X_P(47, GPIO, FC1_c, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, FC_SHRD5, IRQ_IN_a, R); 1006531d6ab3SKavyasree Kotagiri LAN966X_P(48, GPIO, FC1_c, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, FC_SHRD6, IRQ_IN_a, R); 1007531d6ab3SKavyasree Kotagiri LAN966X_P(49, GPIO, FC_SHRD7, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, TWI_SLC_GATE, IRQ_IN_a, R); 1008531d6ab3SKavyasree Kotagiri LAN966X_P(50, GPIO, FC_SHRD16, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, TWI_SLC_GATE, NONE, R); 1009e97e36cdSMichael Walle LAN966X_P(51, GPIO, FC3_b, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, PWM_b, IRQ_IN_b, R); 1010531d6ab3SKavyasree Kotagiri LAN966X_P(52, GPIO, FC3_b, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, TACHO_b, IRQ_IN_b, R); 1011531d6ab3SKavyasree Kotagiri LAN966X_P(53, GPIO, FC3_b, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, NONE, IRQ_IN_b, R); 1012531d6ab3SKavyasree Kotagiri LAN966X_P(54, GPIO, FC_SHRD8, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, TWI_SLC_GATE, IRQ_IN_b, R); 1013531d6ab3SKavyasree Kotagiri LAN966X_P(55, GPIO, FC_SHRD9, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, TWI_SLC_GATE, IRQ_IN_b, R); 1014531d6ab3SKavyasree Kotagiri LAN966X_P(56, GPIO, FC4_b, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, FC_SHRD10, IRQ_IN_b, R); 1015531d6ab3SKavyasree Kotagiri LAN966X_P(57, GPIO, FC4_b, TWI_SLC_GATE, IB_TRG_c, IRQ_OUT_b, FC_SHRD11, IRQ_IN_b, R); 1016531d6ab3SKavyasree Kotagiri LAN966X_P(58, GPIO, FC4_b, TWI_SLC_GATE, IB_TRG_c, IRQ_OUT_b, FC_SHRD12, IRQ_IN_b, R); 1017531d6ab3SKavyasree Kotagiri LAN966X_P(59, GPIO, QSPI1, MIIM_c, NONE, NONE, MIIM_Sb, NONE, R); 1018531d6ab3SKavyasree Kotagiri LAN966X_P(60, GPIO, QSPI1, MIIM_c, NONE, NONE, MIIM_Sb, NONE, R); 1019531d6ab3SKavyasree Kotagiri LAN966X_P(61, GPIO, QSPI1, NONE, SGPIO_b, FC0_c, MIIM_Sb, NONE, R); 1020531d6ab3SKavyasree Kotagiri LAN966X_P(62, GPIO, QSPI1, FC_SHRD13, SGPIO_b, FC0_c, TWI_SLC_GATE, SFP_SD, R); 1021531d6ab3SKavyasree Kotagiri LAN966X_P(63, GPIO, QSPI1, FC_SHRD14, SGPIO_b, FC0_c, TWI_SLC_GATE, SFP_SD, R); 1022531d6ab3SKavyasree Kotagiri LAN966X_P(64, GPIO, QSPI1, FC4_c, SGPIO_b, FC_SHRD15, TWI_SLC_GATE, SFP_SD, R); 1023531d6ab3SKavyasree Kotagiri LAN966X_P(65, GPIO, USB_H_a, FC4_c, NONE, IRQ_OUT_c, TWI_SLC_GATE_AD, NONE, R); 1024531d6ab3SKavyasree Kotagiri LAN966X_P(66, GPIO, USB_H_a, FC4_c, USB_S_a, IRQ_OUT_c, IRQ_IN_c, NONE, R); 1025531d6ab3SKavyasree Kotagiri LAN966X_P(67, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R); 1026531d6ab3SKavyasree Kotagiri LAN966X_P(68, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R); 1027531d6ab3SKavyasree Kotagiri LAN966X_P(69, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R); 1028531d6ab3SKavyasree Kotagiri LAN966X_P(70, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R); 1029531d6ab3SKavyasree Kotagiri LAN966X_P(71, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R); 1030531d6ab3SKavyasree Kotagiri LAN966X_P(72, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R); 1031531d6ab3SKavyasree Kotagiri LAN966X_P(73, GPIO, EMMC, NONE, NONE, SD, NONE, NONE, R); 1032531d6ab3SKavyasree Kotagiri LAN966X_P(74, GPIO, EMMC, NONE, FC_SHRD17, SD, TWI_SLC_GATE, NONE, R); 1033531d6ab3SKavyasree Kotagiri LAN966X_P(75, GPIO, EMMC, NONE, FC_SHRD18, SD, TWI_SLC_GATE, NONE, R); 1034531d6ab3SKavyasree Kotagiri LAN966X_P(76, GPIO, EMMC, NONE, FC_SHRD19, SD, TWI_SLC_GATE, NONE, R); 1035531d6ab3SKavyasree Kotagiri LAN966X_P(77, GPIO, EMMC_SD, NONE, FC_SHRD20, NONE, TWI_SLC_GATE, NONE, R); 1036531d6ab3SKavyasree Kotagiri 1037531d6ab3SKavyasree Kotagiri #define LAN966X_PIN(n) { \ 1038531d6ab3SKavyasree Kotagiri .number = n, \ 1039531d6ab3SKavyasree Kotagiri .name = "GPIO_"#n, \ 1040531d6ab3SKavyasree Kotagiri .drv_data = &lan966x_pin_##n \ 1041531d6ab3SKavyasree Kotagiri } 1042531d6ab3SKavyasree Kotagiri 1043531d6ab3SKavyasree Kotagiri static const struct pinctrl_pin_desc lan966x_pins[] = { 1044531d6ab3SKavyasree Kotagiri LAN966X_PIN(0), 1045531d6ab3SKavyasree Kotagiri LAN966X_PIN(1), 1046531d6ab3SKavyasree Kotagiri LAN966X_PIN(2), 1047531d6ab3SKavyasree Kotagiri LAN966X_PIN(3), 1048531d6ab3SKavyasree Kotagiri LAN966X_PIN(4), 1049531d6ab3SKavyasree Kotagiri LAN966X_PIN(5), 1050531d6ab3SKavyasree Kotagiri LAN966X_PIN(6), 1051531d6ab3SKavyasree Kotagiri LAN966X_PIN(7), 1052531d6ab3SKavyasree Kotagiri LAN966X_PIN(8), 1053531d6ab3SKavyasree Kotagiri LAN966X_PIN(9), 1054531d6ab3SKavyasree Kotagiri LAN966X_PIN(10), 1055531d6ab3SKavyasree Kotagiri LAN966X_PIN(11), 1056531d6ab3SKavyasree Kotagiri LAN966X_PIN(12), 1057531d6ab3SKavyasree Kotagiri LAN966X_PIN(13), 1058531d6ab3SKavyasree Kotagiri LAN966X_PIN(14), 1059531d6ab3SKavyasree Kotagiri LAN966X_PIN(15), 1060531d6ab3SKavyasree Kotagiri LAN966X_PIN(16), 1061531d6ab3SKavyasree Kotagiri LAN966X_PIN(17), 1062531d6ab3SKavyasree Kotagiri LAN966X_PIN(18), 1063531d6ab3SKavyasree Kotagiri LAN966X_PIN(19), 1064531d6ab3SKavyasree Kotagiri LAN966X_PIN(20), 1065531d6ab3SKavyasree Kotagiri LAN966X_PIN(21), 1066531d6ab3SKavyasree Kotagiri LAN966X_PIN(22), 1067531d6ab3SKavyasree Kotagiri LAN966X_PIN(23), 1068531d6ab3SKavyasree Kotagiri LAN966X_PIN(24), 1069531d6ab3SKavyasree Kotagiri LAN966X_PIN(25), 1070531d6ab3SKavyasree Kotagiri LAN966X_PIN(26), 1071531d6ab3SKavyasree Kotagiri LAN966X_PIN(27), 1072531d6ab3SKavyasree Kotagiri LAN966X_PIN(28), 1073531d6ab3SKavyasree Kotagiri LAN966X_PIN(29), 1074531d6ab3SKavyasree Kotagiri LAN966X_PIN(30), 1075531d6ab3SKavyasree Kotagiri LAN966X_PIN(31), 1076531d6ab3SKavyasree Kotagiri LAN966X_PIN(32), 1077531d6ab3SKavyasree Kotagiri LAN966X_PIN(33), 1078531d6ab3SKavyasree Kotagiri LAN966X_PIN(34), 1079531d6ab3SKavyasree Kotagiri LAN966X_PIN(35), 1080531d6ab3SKavyasree Kotagiri LAN966X_PIN(36), 1081531d6ab3SKavyasree Kotagiri LAN966X_PIN(37), 1082531d6ab3SKavyasree Kotagiri LAN966X_PIN(38), 1083531d6ab3SKavyasree Kotagiri LAN966X_PIN(39), 1084531d6ab3SKavyasree Kotagiri LAN966X_PIN(40), 1085531d6ab3SKavyasree Kotagiri LAN966X_PIN(41), 1086531d6ab3SKavyasree Kotagiri LAN966X_PIN(42), 1087531d6ab3SKavyasree Kotagiri LAN966X_PIN(43), 1088531d6ab3SKavyasree Kotagiri LAN966X_PIN(44), 1089531d6ab3SKavyasree Kotagiri LAN966X_PIN(45), 1090531d6ab3SKavyasree Kotagiri LAN966X_PIN(46), 1091531d6ab3SKavyasree Kotagiri LAN966X_PIN(47), 1092531d6ab3SKavyasree Kotagiri LAN966X_PIN(48), 1093531d6ab3SKavyasree Kotagiri LAN966X_PIN(49), 1094531d6ab3SKavyasree Kotagiri LAN966X_PIN(50), 1095531d6ab3SKavyasree Kotagiri LAN966X_PIN(51), 1096531d6ab3SKavyasree Kotagiri LAN966X_PIN(52), 1097531d6ab3SKavyasree Kotagiri LAN966X_PIN(53), 1098531d6ab3SKavyasree Kotagiri LAN966X_PIN(54), 1099531d6ab3SKavyasree Kotagiri LAN966X_PIN(55), 1100531d6ab3SKavyasree Kotagiri LAN966X_PIN(56), 1101531d6ab3SKavyasree Kotagiri LAN966X_PIN(57), 1102531d6ab3SKavyasree Kotagiri LAN966X_PIN(58), 1103531d6ab3SKavyasree Kotagiri LAN966X_PIN(59), 1104531d6ab3SKavyasree Kotagiri LAN966X_PIN(60), 1105531d6ab3SKavyasree Kotagiri LAN966X_PIN(61), 1106531d6ab3SKavyasree Kotagiri LAN966X_PIN(62), 1107531d6ab3SKavyasree Kotagiri LAN966X_PIN(63), 1108531d6ab3SKavyasree Kotagiri LAN966X_PIN(64), 1109531d6ab3SKavyasree Kotagiri LAN966X_PIN(65), 1110531d6ab3SKavyasree Kotagiri LAN966X_PIN(66), 1111531d6ab3SKavyasree Kotagiri LAN966X_PIN(67), 1112531d6ab3SKavyasree Kotagiri LAN966X_PIN(68), 1113531d6ab3SKavyasree Kotagiri LAN966X_PIN(69), 1114531d6ab3SKavyasree Kotagiri LAN966X_PIN(70), 1115531d6ab3SKavyasree Kotagiri LAN966X_PIN(71), 1116531d6ab3SKavyasree Kotagiri LAN966X_PIN(72), 1117531d6ab3SKavyasree Kotagiri LAN966X_PIN(73), 1118531d6ab3SKavyasree Kotagiri LAN966X_PIN(74), 1119531d6ab3SKavyasree Kotagiri LAN966X_PIN(75), 1120531d6ab3SKavyasree Kotagiri LAN966X_PIN(76), 1121531d6ab3SKavyasree Kotagiri LAN966X_PIN(77), 1122531d6ab3SKavyasree Kotagiri }; 1123531d6ab3SKavyasree Kotagiri 1124ce8dc094SAlexandre Belloni static int ocelot_get_functions_count(struct pinctrl_dev *pctldev) 1125ce8dc094SAlexandre Belloni { 1126ce8dc094SAlexandre Belloni return ARRAY_SIZE(ocelot_function_names); 1127ce8dc094SAlexandre Belloni } 1128ce8dc094SAlexandre Belloni 1129ce8dc094SAlexandre Belloni static const char *ocelot_get_function_name(struct pinctrl_dev *pctldev, 1130ce8dc094SAlexandre Belloni unsigned int function) 1131ce8dc094SAlexandre Belloni { 1132ce8dc094SAlexandre Belloni return ocelot_function_names[function]; 1133ce8dc094SAlexandre Belloni } 1134ce8dc094SAlexandre Belloni 1135ce8dc094SAlexandre Belloni static int ocelot_get_function_groups(struct pinctrl_dev *pctldev, 1136ce8dc094SAlexandre Belloni unsigned int function, 1137ce8dc094SAlexandre Belloni const char *const **groups, 1138ce8dc094SAlexandre Belloni unsigned *const num_groups) 1139ce8dc094SAlexandre Belloni { 1140ce8dc094SAlexandre Belloni struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1141ce8dc094SAlexandre Belloni 1142ce8dc094SAlexandre Belloni *groups = info->func[function].groups; 1143ce8dc094SAlexandre Belloni *num_groups = info->func[function].ngroups; 1144ce8dc094SAlexandre Belloni 1145ce8dc094SAlexandre Belloni return 0; 1146ce8dc094SAlexandre Belloni } 1147ce8dc094SAlexandre Belloni 1148da801ab5SAlexandre Belloni static int ocelot_pin_function_idx(struct ocelot_pinctrl *info, 1149da801ab5SAlexandre Belloni unsigned int pin, unsigned int function) 1150ce8dc094SAlexandre Belloni { 1151da801ab5SAlexandre Belloni struct ocelot_pin_caps *p = info->desc->pins[pin].drv_data; 1152ce8dc094SAlexandre Belloni int i; 1153ce8dc094SAlexandre Belloni 1154ce8dc094SAlexandre Belloni for (i = 0; i < OCELOT_FUNC_PER_PIN; i++) { 1155ce8dc094SAlexandre Belloni if (function == p->functions[i]) 1156ce8dc094SAlexandre Belloni return i; 1157531d6ab3SKavyasree Kotagiri 1158531d6ab3SKavyasree Kotagiri if (function == p->a_functions[i]) 1159531d6ab3SKavyasree Kotagiri return i + OCELOT_FUNC_PER_PIN; 1160ce8dc094SAlexandre Belloni } 1161ce8dc094SAlexandre Belloni 1162ce8dc094SAlexandre Belloni return -1; 1163ce8dc094SAlexandre Belloni } 1164ce8dc094SAlexandre Belloni 11654b36082eSAlexandre Belloni #define REG_ALT(msb, info, p) (OCELOT_GPIO_ALT0 * (info)->stride + 4 * ((msb) + ((info)->stride * ((p) / 32)))) 1166da801ab5SAlexandre Belloni 1167ce8dc094SAlexandre Belloni static int ocelot_pinmux_set_mux(struct pinctrl_dev *pctldev, 1168ce8dc094SAlexandre Belloni unsigned int selector, unsigned int group) 1169ce8dc094SAlexandre Belloni { 1170ce8dc094SAlexandre Belloni struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1171da801ab5SAlexandre Belloni struct ocelot_pin_caps *pin = info->desc->pins[group].drv_data; 1172da801ab5SAlexandre Belloni unsigned int p = pin->pin % 32; 1173ce8dc094SAlexandre Belloni int f; 1174ce8dc094SAlexandre Belloni 1175da801ab5SAlexandre Belloni f = ocelot_pin_function_idx(info, group, selector); 1176ce8dc094SAlexandre Belloni if (f < 0) 1177ce8dc094SAlexandre Belloni return -EINVAL; 1178ce8dc094SAlexandre Belloni 1179ce8dc094SAlexandre Belloni /* 1180ce8dc094SAlexandre Belloni * f is encoded on two bits. 11814b36082eSAlexandre Belloni * bit 0 of f goes in BIT(pin) of ALT[0], bit 1 of f goes in BIT(pin) of 11824b36082eSAlexandre Belloni * ALT[1] 1183ce8dc094SAlexandre Belloni * This is racy because both registers can't be updated at the same time 1184ce8dc094SAlexandre Belloni * but it doesn't matter much for now. 1185f8a74760SLars Povlsen * Note: ALT0/ALT1 are organized specially for 64 gpio targets 1186ce8dc094SAlexandre Belloni */ 11874b36082eSAlexandre Belloni regmap_update_bits(info->map, REG_ALT(0, info, pin->pin), 1188da801ab5SAlexandre Belloni BIT(p), f << p); 11894b36082eSAlexandre Belloni regmap_update_bits(info->map, REG_ALT(1, info, pin->pin), 1190da801ab5SAlexandre Belloni BIT(p), f << (p - 1)); 1191ce8dc094SAlexandre Belloni 1192ce8dc094SAlexandre Belloni return 0; 1193ce8dc094SAlexandre Belloni } 1194ce8dc094SAlexandre Belloni 1195531d6ab3SKavyasree Kotagiri static int lan966x_pinmux_set_mux(struct pinctrl_dev *pctldev, 1196531d6ab3SKavyasree Kotagiri unsigned int selector, unsigned int group) 1197531d6ab3SKavyasree Kotagiri { 1198531d6ab3SKavyasree Kotagiri struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1199531d6ab3SKavyasree Kotagiri struct ocelot_pin_caps *pin = info->desc->pins[group].drv_data; 1200531d6ab3SKavyasree Kotagiri unsigned int p = pin->pin % 32; 1201531d6ab3SKavyasree Kotagiri int f; 1202531d6ab3SKavyasree Kotagiri 1203531d6ab3SKavyasree Kotagiri f = ocelot_pin_function_idx(info, group, selector); 1204531d6ab3SKavyasree Kotagiri if (f < 0) 1205531d6ab3SKavyasree Kotagiri return -EINVAL; 1206531d6ab3SKavyasree Kotagiri 1207531d6ab3SKavyasree Kotagiri /* 1208531d6ab3SKavyasree Kotagiri * f is encoded on three bits. 1209531d6ab3SKavyasree Kotagiri * bit 0 of f goes in BIT(pin) of ALT[0], bit 1 of f goes in BIT(pin) of 1210531d6ab3SKavyasree Kotagiri * ALT[1], bit 2 of f goes in BIT(pin) of ALT[2] 1211531d6ab3SKavyasree Kotagiri * This is racy because three registers can't be updated at the same time 1212531d6ab3SKavyasree Kotagiri * but it doesn't matter much for now. 1213531d6ab3SKavyasree Kotagiri * Note: ALT0/ALT1/ALT2 are organized specially for 78 gpio targets 1214531d6ab3SKavyasree Kotagiri */ 1215531d6ab3SKavyasree Kotagiri regmap_update_bits(info->map, REG_ALT(0, info, pin->pin), 1216531d6ab3SKavyasree Kotagiri BIT(p), f << p); 1217531d6ab3SKavyasree Kotagiri regmap_update_bits(info->map, REG_ALT(1, info, pin->pin), 1218531d6ab3SKavyasree Kotagiri BIT(p), (f >> 1) << p); 1219531d6ab3SKavyasree Kotagiri regmap_update_bits(info->map, REG_ALT(2, info, pin->pin), 1220531d6ab3SKavyasree Kotagiri BIT(p), (f >> 2) << p); 1221531d6ab3SKavyasree Kotagiri 1222531d6ab3SKavyasree Kotagiri return 0; 1223531d6ab3SKavyasree Kotagiri } 1224531d6ab3SKavyasree Kotagiri 12254b36082eSAlexandre Belloni #define REG(r, info, p) ((r) * (info)->stride + (4 * ((p) / 32))) 12264b36082eSAlexandre Belloni 1227ce8dc094SAlexandre Belloni static int ocelot_gpio_set_direction(struct pinctrl_dev *pctldev, 1228ce8dc094SAlexandre Belloni struct pinctrl_gpio_range *range, 1229ce8dc094SAlexandre Belloni unsigned int pin, bool input) 1230ce8dc094SAlexandre Belloni { 1231ce8dc094SAlexandre Belloni struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1232da801ab5SAlexandre Belloni unsigned int p = pin % 32; 1233ce8dc094SAlexandre Belloni 1234f2818ba3SAlexandre Belloni regmap_update_bits(info->map, REG(OCELOT_GPIO_OE, info, pin), BIT(p), 1235da801ab5SAlexandre Belloni input ? 0 : BIT(p)); 1236ce8dc094SAlexandre Belloni 1237ce8dc094SAlexandre Belloni return 0; 1238ce8dc094SAlexandre Belloni } 1239ce8dc094SAlexandre Belloni 1240ce8dc094SAlexandre Belloni static int ocelot_gpio_request_enable(struct pinctrl_dev *pctldev, 1241ce8dc094SAlexandre Belloni struct pinctrl_gpio_range *range, 1242ce8dc094SAlexandre Belloni unsigned int offset) 1243ce8dc094SAlexandre Belloni { 1244ce8dc094SAlexandre Belloni struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1245da801ab5SAlexandre Belloni unsigned int p = offset % 32; 1246ce8dc094SAlexandre Belloni 12474b36082eSAlexandre Belloni regmap_update_bits(info->map, REG_ALT(0, info, offset), 1248da801ab5SAlexandre Belloni BIT(p), 0); 12494b36082eSAlexandre Belloni regmap_update_bits(info->map, REG_ALT(1, info, offset), 1250da801ab5SAlexandre Belloni BIT(p), 0); 1251ce8dc094SAlexandre Belloni 1252ce8dc094SAlexandre Belloni return 0; 1253ce8dc094SAlexandre Belloni } 1254ce8dc094SAlexandre Belloni 1255531d6ab3SKavyasree Kotagiri static int lan966x_gpio_request_enable(struct pinctrl_dev *pctldev, 1256531d6ab3SKavyasree Kotagiri struct pinctrl_gpio_range *range, 1257531d6ab3SKavyasree Kotagiri unsigned int offset) 1258531d6ab3SKavyasree Kotagiri { 1259531d6ab3SKavyasree Kotagiri struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1260531d6ab3SKavyasree Kotagiri unsigned int p = offset % 32; 1261531d6ab3SKavyasree Kotagiri 1262531d6ab3SKavyasree Kotagiri regmap_update_bits(info->map, REG_ALT(0, info, offset), 1263531d6ab3SKavyasree Kotagiri BIT(p), 0); 1264531d6ab3SKavyasree Kotagiri regmap_update_bits(info->map, REG_ALT(1, info, offset), 1265531d6ab3SKavyasree Kotagiri BIT(p), 0); 1266531d6ab3SKavyasree Kotagiri regmap_update_bits(info->map, REG_ALT(2, info, offset), 1267531d6ab3SKavyasree Kotagiri BIT(p), 0); 1268531d6ab3SKavyasree Kotagiri 1269531d6ab3SKavyasree Kotagiri return 0; 1270531d6ab3SKavyasree Kotagiri } 1271531d6ab3SKavyasree Kotagiri 1272ce8dc094SAlexandre Belloni static const struct pinmux_ops ocelot_pmx_ops = { 1273ce8dc094SAlexandre Belloni .get_functions_count = ocelot_get_functions_count, 1274ce8dc094SAlexandre Belloni .get_function_name = ocelot_get_function_name, 1275ce8dc094SAlexandre Belloni .get_function_groups = ocelot_get_function_groups, 1276ce8dc094SAlexandre Belloni .set_mux = ocelot_pinmux_set_mux, 1277ce8dc094SAlexandre Belloni .gpio_set_direction = ocelot_gpio_set_direction, 1278ce8dc094SAlexandre Belloni .gpio_request_enable = ocelot_gpio_request_enable, 1279ce8dc094SAlexandre Belloni }; 1280ce8dc094SAlexandre Belloni 1281531d6ab3SKavyasree Kotagiri static const struct pinmux_ops lan966x_pmx_ops = { 1282531d6ab3SKavyasree Kotagiri .get_functions_count = ocelot_get_functions_count, 1283531d6ab3SKavyasree Kotagiri .get_function_name = ocelot_get_function_name, 1284531d6ab3SKavyasree Kotagiri .get_function_groups = ocelot_get_function_groups, 1285531d6ab3SKavyasree Kotagiri .set_mux = lan966x_pinmux_set_mux, 1286531d6ab3SKavyasree Kotagiri .gpio_set_direction = ocelot_gpio_set_direction, 1287531d6ab3SKavyasree Kotagiri .gpio_request_enable = lan966x_gpio_request_enable, 1288531d6ab3SKavyasree Kotagiri }; 1289531d6ab3SKavyasree Kotagiri 1290ce8dc094SAlexandre Belloni static int ocelot_pctl_get_groups_count(struct pinctrl_dev *pctldev) 1291ce8dc094SAlexandre Belloni { 1292da801ab5SAlexandre Belloni struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1293da801ab5SAlexandre Belloni 1294da801ab5SAlexandre Belloni return info->desc->npins; 1295ce8dc094SAlexandre Belloni } 1296ce8dc094SAlexandre Belloni 1297ce8dc094SAlexandre Belloni static const char *ocelot_pctl_get_group_name(struct pinctrl_dev *pctldev, 1298ce8dc094SAlexandre Belloni unsigned int group) 1299ce8dc094SAlexandre Belloni { 1300da801ab5SAlexandre Belloni struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1301da801ab5SAlexandre Belloni 1302da801ab5SAlexandre Belloni return info->desc->pins[group].name; 1303ce8dc094SAlexandre Belloni } 1304ce8dc094SAlexandre Belloni 1305ce8dc094SAlexandre Belloni static int ocelot_pctl_get_group_pins(struct pinctrl_dev *pctldev, 1306ce8dc094SAlexandre Belloni unsigned int group, 1307ce8dc094SAlexandre Belloni const unsigned int **pins, 1308ce8dc094SAlexandre Belloni unsigned int *num_pins) 1309ce8dc094SAlexandre Belloni { 1310da801ab5SAlexandre Belloni struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1311da801ab5SAlexandre Belloni 1312da801ab5SAlexandre Belloni *pins = &info->desc->pins[group].number; 1313ce8dc094SAlexandre Belloni *num_pins = 1; 1314ce8dc094SAlexandre Belloni 1315ce8dc094SAlexandre Belloni return 0; 1316ce8dc094SAlexandre Belloni } 1317ce8dc094SAlexandre Belloni 1318f8a74760SLars Povlsen static int ocelot_hw_get_value(struct ocelot_pinctrl *info, 1319f8a74760SLars Povlsen unsigned int pin, 1320f8a74760SLars Povlsen unsigned int reg, 1321f8a74760SLars Povlsen int *val) 1322f8a74760SLars Povlsen { 1323f8a74760SLars Povlsen int ret = -EOPNOTSUPP; 1324f8a74760SLars Povlsen 1325f8a74760SLars Povlsen if (info->pincfg) { 1326076d9e71SColin Foster u32 regcfg; 1327076d9e71SColin Foster 1328076d9e71SColin Foster ret = regmap_read(info->pincfg, pin, ®cfg); 1329076d9e71SColin Foster if (ret) 1330076d9e71SColin Foster return ret; 1331f8a74760SLars Povlsen 1332f8a74760SLars Povlsen ret = 0; 1333f8a74760SLars Povlsen switch (reg) { 1334f8a74760SLars Povlsen case PINCONF_BIAS: 1335f8a74760SLars Povlsen *val = regcfg & BIAS_BITS; 1336f8a74760SLars Povlsen break; 1337f8a74760SLars Povlsen 1338f8a74760SLars Povlsen case PINCONF_SCHMITT: 1339f8a74760SLars Povlsen *val = regcfg & SCHMITT_BIT; 1340f8a74760SLars Povlsen break; 1341f8a74760SLars Povlsen 1342f8a74760SLars Povlsen case PINCONF_DRIVE_STRENGTH: 1343f8a74760SLars Povlsen *val = regcfg & DRIVE_BITS; 1344f8a74760SLars Povlsen break; 1345f8a74760SLars Povlsen 1346f8a74760SLars Povlsen default: 1347f8a74760SLars Povlsen ret = -EOPNOTSUPP; 1348f8a74760SLars Povlsen break; 1349f8a74760SLars Povlsen } 1350f8a74760SLars Povlsen } 1351f8a74760SLars Povlsen return ret; 1352f8a74760SLars Povlsen } 1353f8a74760SLars Povlsen 1354076d9e71SColin Foster static int ocelot_pincfg_clrsetbits(struct ocelot_pinctrl *info, u32 regaddr, 1355076d9e71SColin Foster u32 clrbits, u32 setbits) 1356076d9e71SColin Foster { 1357076d9e71SColin Foster u32 val; 1358076d9e71SColin Foster int ret; 1359076d9e71SColin Foster 1360076d9e71SColin Foster ret = regmap_read(info->pincfg, regaddr, &val); 1361076d9e71SColin Foster if (ret) 1362076d9e71SColin Foster return ret; 1363076d9e71SColin Foster 1364076d9e71SColin Foster val &= ~clrbits; 1365076d9e71SColin Foster val |= setbits; 1366076d9e71SColin Foster 1367076d9e71SColin Foster ret = regmap_write(info->pincfg, regaddr, val); 1368076d9e71SColin Foster 1369076d9e71SColin Foster return ret; 1370076d9e71SColin Foster } 1371076d9e71SColin Foster 1372f8a74760SLars Povlsen static int ocelot_hw_set_value(struct ocelot_pinctrl *info, 1373f8a74760SLars Povlsen unsigned int pin, 1374f8a74760SLars Povlsen unsigned int reg, 1375f8a74760SLars Povlsen int val) 1376f8a74760SLars Povlsen { 1377f8a74760SLars Povlsen int ret = -EOPNOTSUPP; 1378f8a74760SLars Povlsen 1379f8a74760SLars Povlsen if (info->pincfg) { 1380f8a74760SLars Povlsen 1381f8a74760SLars Povlsen ret = 0; 1382f8a74760SLars Povlsen switch (reg) { 1383f8a74760SLars Povlsen case PINCONF_BIAS: 1384076d9e71SColin Foster ret = ocelot_pincfg_clrsetbits(info, pin, BIAS_BITS, 1385076d9e71SColin Foster val); 1386f8a74760SLars Povlsen break; 1387f8a74760SLars Povlsen 1388f8a74760SLars Povlsen case PINCONF_SCHMITT: 1389076d9e71SColin Foster ret = ocelot_pincfg_clrsetbits(info, pin, SCHMITT_BIT, 1390076d9e71SColin Foster val); 1391f8a74760SLars Povlsen break; 1392f8a74760SLars Povlsen 1393f8a74760SLars Povlsen case PINCONF_DRIVE_STRENGTH: 1394f8a74760SLars Povlsen if (val <= 3) 1395076d9e71SColin Foster ret = ocelot_pincfg_clrsetbits(info, pin, 1396076d9e71SColin Foster DRIVE_BITS, val); 1397f8a74760SLars Povlsen else 1398f8a74760SLars Povlsen ret = -EINVAL; 1399f8a74760SLars Povlsen break; 1400f8a74760SLars Povlsen 1401f8a74760SLars Povlsen default: 1402f8a74760SLars Povlsen ret = -EOPNOTSUPP; 1403f8a74760SLars Povlsen break; 1404f8a74760SLars Povlsen } 1405f8a74760SLars Povlsen } 1406f8a74760SLars Povlsen return ret; 1407f8a74760SLars Povlsen } 1408f8a74760SLars Povlsen 1409f8a74760SLars Povlsen static int ocelot_pinconf_get(struct pinctrl_dev *pctldev, 1410f8a74760SLars Povlsen unsigned int pin, unsigned long *config) 1411f8a74760SLars Povlsen { 1412f8a74760SLars Povlsen struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1413f8a74760SLars Povlsen u32 param = pinconf_to_config_param(*config); 1414f8a74760SLars Povlsen int val, err; 1415f8a74760SLars Povlsen 1416f8a74760SLars Povlsen switch (param) { 1417f8a74760SLars Povlsen case PIN_CONFIG_BIAS_DISABLE: 1418f8a74760SLars Povlsen case PIN_CONFIG_BIAS_PULL_UP: 1419f8a74760SLars Povlsen case PIN_CONFIG_BIAS_PULL_DOWN: 1420f8a74760SLars Povlsen err = ocelot_hw_get_value(info, pin, PINCONF_BIAS, &val); 1421f8a74760SLars Povlsen if (err) 1422f8a74760SLars Povlsen return err; 1423f8a74760SLars Povlsen if (param == PIN_CONFIG_BIAS_DISABLE) 142454515257SKaixu Xia val = (val == 0); 1425f8a74760SLars Povlsen else if (param == PIN_CONFIG_BIAS_PULL_DOWN) 1426f8a74760SLars Povlsen val = (val & BIAS_PD_BIT ? true : false); 1427f8a74760SLars Povlsen else /* PIN_CONFIG_BIAS_PULL_UP */ 1428f8a74760SLars Povlsen val = (val & BIAS_PU_BIT ? true : false); 1429f8a74760SLars Povlsen break; 1430f8a74760SLars Povlsen 1431f8a74760SLars Povlsen case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 1432f8a74760SLars Povlsen err = ocelot_hw_get_value(info, pin, PINCONF_SCHMITT, &val); 1433f8a74760SLars Povlsen if (err) 1434f8a74760SLars Povlsen return err; 1435f8a74760SLars Povlsen 1436f8a74760SLars Povlsen val = (val & SCHMITT_BIT ? true : false); 1437f8a74760SLars Povlsen break; 1438f8a74760SLars Povlsen 1439f8a74760SLars Povlsen case PIN_CONFIG_DRIVE_STRENGTH: 1440f8a74760SLars Povlsen err = ocelot_hw_get_value(info, pin, PINCONF_DRIVE_STRENGTH, 1441f8a74760SLars Povlsen &val); 1442f8a74760SLars Povlsen if (err) 1443f8a74760SLars Povlsen return err; 1444f8a74760SLars Povlsen break; 1445f8a74760SLars Povlsen 1446f8a74760SLars Povlsen case PIN_CONFIG_OUTPUT: 1447f8a74760SLars Povlsen err = regmap_read(info->map, REG(OCELOT_GPIO_OUT, info, pin), 1448f8a74760SLars Povlsen &val); 1449f8a74760SLars Povlsen if (err) 1450f8a74760SLars Povlsen return err; 1451f8a74760SLars Povlsen val = !!(val & BIT(pin % 32)); 1452f8a74760SLars Povlsen break; 1453f8a74760SLars Povlsen 1454f8a74760SLars Povlsen case PIN_CONFIG_INPUT_ENABLE: 1455f8a74760SLars Povlsen case PIN_CONFIG_OUTPUT_ENABLE: 1456f8a74760SLars Povlsen err = regmap_read(info->map, REG(OCELOT_GPIO_OE, info, pin), 1457f8a74760SLars Povlsen &val); 1458f8a74760SLars Povlsen if (err) 1459f8a74760SLars Povlsen return err; 1460f8a74760SLars Povlsen val = val & BIT(pin % 32); 1461f8a74760SLars Povlsen if (param == PIN_CONFIG_OUTPUT_ENABLE) 1462f8a74760SLars Povlsen val = !!val; 1463f8a74760SLars Povlsen else 1464f8a74760SLars Povlsen val = !val; 1465f8a74760SLars Povlsen break; 1466f8a74760SLars Povlsen 1467f8a74760SLars Povlsen default: 1468f8a74760SLars Povlsen return -EOPNOTSUPP; 1469f8a74760SLars Povlsen } 1470f8a74760SLars Povlsen 1471f8a74760SLars Povlsen *config = pinconf_to_config_packed(param, val); 1472f8a74760SLars Povlsen 1473f8a74760SLars Povlsen return 0; 1474f8a74760SLars Povlsen } 1475f8a74760SLars Povlsen 1476f8a74760SLars Povlsen static int ocelot_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 1477f8a74760SLars Povlsen unsigned long *configs, unsigned int num_configs) 1478f8a74760SLars Povlsen { 1479f8a74760SLars Povlsen struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1480f8a74760SLars Povlsen u32 param, arg, p; 1481f8a74760SLars Povlsen int cfg, err = 0; 1482f8a74760SLars Povlsen 1483f8a74760SLars Povlsen for (cfg = 0; cfg < num_configs; cfg++) { 1484f8a74760SLars Povlsen param = pinconf_to_config_param(configs[cfg]); 1485f8a74760SLars Povlsen arg = pinconf_to_config_argument(configs[cfg]); 1486f8a74760SLars Povlsen 1487f8a74760SLars Povlsen switch (param) { 1488f8a74760SLars Povlsen case PIN_CONFIG_BIAS_DISABLE: 1489f8a74760SLars Povlsen case PIN_CONFIG_BIAS_PULL_UP: 1490f8a74760SLars Povlsen case PIN_CONFIG_BIAS_PULL_DOWN: 1491f8a74760SLars Povlsen arg = (param == PIN_CONFIG_BIAS_DISABLE) ? 0 : 1492f8a74760SLars Povlsen (param == PIN_CONFIG_BIAS_PULL_UP) ? BIAS_PU_BIT : 1493f8a74760SLars Povlsen BIAS_PD_BIT; 1494f8a74760SLars Povlsen 1495f8a74760SLars Povlsen err = ocelot_hw_set_value(info, pin, PINCONF_BIAS, arg); 1496f8a74760SLars Povlsen if (err) 1497f8a74760SLars Povlsen goto err; 1498f8a74760SLars Povlsen 1499f8a74760SLars Povlsen break; 1500f8a74760SLars Povlsen 1501f8a74760SLars Povlsen case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 1502f8a74760SLars Povlsen arg = arg ? SCHMITT_BIT : 0; 1503f8a74760SLars Povlsen err = ocelot_hw_set_value(info, pin, PINCONF_SCHMITT, 1504f8a74760SLars Povlsen arg); 1505f8a74760SLars Povlsen if (err) 1506f8a74760SLars Povlsen goto err; 1507f8a74760SLars Povlsen 1508f8a74760SLars Povlsen break; 1509f8a74760SLars Povlsen 1510f8a74760SLars Povlsen case PIN_CONFIG_DRIVE_STRENGTH: 1511f8a74760SLars Povlsen err = ocelot_hw_set_value(info, pin, 1512f8a74760SLars Povlsen PINCONF_DRIVE_STRENGTH, 1513f8a74760SLars Povlsen arg); 1514f8a74760SLars Povlsen if (err) 1515f8a74760SLars Povlsen goto err; 1516f8a74760SLars Povlsen 1517f8a74760SLars Povlsen break; 1518f8a74760SLars Povlsen 1519f8a74760SLars Povlsen case PIN_CONFIG_OUTPUT_ENABLE: 1520f8a74760SLars Povlsen case PIN_CONFIG_INPUT_ENABLE: 1521f8a74760SLars Povlsen case PIN_CONFIG_OUTPUT: 1522f8a74760SLars Povlsen p = pin % 32; 1523f8a74760SLars Povlsen if (arg) 1524f8a74760SLars Povlsen regmap_write(info->map, 1525f8a74760SLars Povlsen REG(OCELOT_GPIO_OUT_SET, info, 1526f8a74760SLars Povlsen pin), 1527f8a74760SLars Povlsen BIT(p)); 1528f8a74760SLars Povlsen else 1529f8a74760SLars Povlsen regmap_write(info->map, 1530f8a74760SLars Povlsen REG(OCELOT_GPIO_OUT_CLR, info, 1531f8a74760SLars Povlsen pin), 1532f8a74760SLars Povlsen BIT(p)); 1533f8a74760SLars Povlsen regmap_update_bits(info->map, 1534f8a74760SLars Povlsen REG(OCELOT_GPIO_OE, info, pin), 1535f8a74760SLars Povlsen BIT(p), 1536f8a74760SLars Povlsen param == PIN_CONFIG_INPUT_ENABLE ? 1537f8a74760SLars Povlsen 0 : BIT(p)); 1538f8a74760SLars Povlsen break; 1539f8a74760SLars Povlsen 1540f8a74760SLars Povlsen default: 1541f8a74760SLars Povlsen err = -EOPNOTSUPP; 1542f8a74760SLars Povlsen } 1543f8a74760SLars Povlsen } 1544f8a74760SLars Povlsen err: 1545f8a74760SLars Povlsen return err; 1546f8a74760SLars Povlsen } 1547f8a74760SLars Povlsen 1548f8a74760SLars Povlsen static const struct pinconf_ops ocelot_confops = { 1549f8a74760SLars Povlsen .is_generic = true, 1550f8a74760SLars Povlsen .pin_config_get = ocelot_pinconf_get, 1551f8a74760SLars Povlsen .pin_config_set = ocelot_pinconf_set, 1552f8a74760SLars Povlsen .pin_config_config_dbg_show = pinconf_generic_dump_config, 1553f8a74760SLars Povlsen }; 1554f8a74760SLars Povlsen 1555ce8dc094SAlexandre Belloni static const struct pinctrl_ops ocelot_pctl_ops = { 1556ce8dc094SAlexandre Belloni .get_groups_count = ocelot_pctl_get_groups_count, 1557ce8dc094SAlexandre Belloni .get_group_name = ocelot_pctl_get_group_name, 1558ce8dc094SAlexandre Belloni .get_group_pins = ocelot_pctl_get_group_pins, 1559ce8dc094SAlexandre Belloni .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, 1560ce8dc094SAlexandre Belloni .dt_free_map = pinconf_generic_dt_free_map, 1561ce8dc094SAlexandre Belloni }; 1562ce8dc094SAlexandre Belloni 15638f27440dSLars Povlsen static struct pinctrl_desc luton_desc = { 15648f27440dSLars Povlsen .name = "luton-pinctrl", 15658f27440dSLars Povlsen .pins = luton_pins, 15668f27440dSLars Povlsen .npins = ARRAY_SIZE(luton_pins), 15678f27440dSLars Povlsen .pctlops = &ocelot_pctl_ops, 15688f27440dSLars Povlsen .pmxops = &ocelot_pmx_ops, 15698f27440dSLars Povlsen .owner = THIS_MODULE, 15708f27440dSLars Povlsen }; 15718f27440dSLars Povlsen 15726e6347e2SLars Povlsen static struct pinctrl_desc serval_desc = { 15736e6347e2SLars Povlsen .name = "serval-pinctrl", 15746e6347e2SLars Povlsen .pins = serval_pins, 15756e6347e2SLars Povlsen .npins = ARRAY_SIZE(serval_pins), 15766e6347e2SLars Povlsen .pctlops = &ocelot_pctl_ops, 15776e6347e2SLars Povlsen .pmxops = &ocelot_pmx_ops, 15786e6347e2SLars Povlsen .owner = THIS_MODULE, 15796e6347e2SLars Povlsen }; 15806e6347e2SLars Povlsen 1581ce8dc094SAlexandre Belloni static struct pinctrl_desc ocelot_desc = { 1582ce8dc094SAlexandre Belloni .name = "ocelot-pinctrl", 1583ce8dc094SAlexandre Belloni .pins = ocelot_pins, 1584ce8dc094SAlexandre Belloni .npins = ARRAY_SIZE(ocelot_pins), 1585ce8dc094SAlexandre Belloni .pctlops = &ocelot_pctl_ops, 1586ce8dc094SAlexandre Belloni .pmxops = &ocelot_pmx_ops, 1587ce8dc094SAlexandre Belloni .owner = THIS_MODULE, 1588ce8dc094SAlexandre Belloni }; 1589ce8dc094SAlexandre Belloni 1590da801ab5SAlexandre Belloni static struct pinctrl_desc jaguar2_desc = { 1591da801ab5SAlexandre Belloni .name = "jaguar2-pinctrl", 1592da801ab5SAlexandre Belloni .pins = jaguar2_pins, 1593da801ab5SAlexandre Belloni .npins = ARRAY_SIZE(jaguar2_pins), 1594da801ab5SAlexandre Belloni .pctlops = &ocelot_pctl_ops, 1595da801ab5SAlexandre Belloni .pmxops = &ocelot_pmx_ops, 1596da801ab5SAlexandre Belloni .owner = THIS_MODULE, 1597da801ab5SAlexandre Belloni }; 1598da801ab5SAlexandre Belloni 15998fc0bfcdSHoratiu Vultur static struct pinctrl_desc servalt_desc = { 16008fc0bfcdSHoratiu Vultur .name = "servalt-pinctrl", 16018fc0bfcdSHoratiu Vultur .pins = servalt_pins, 16028fc0bfcdSHoratiu Vultur .npins = ARRAY_SIZE(servalt_pins), 16038fc0bfcdSHoratiu Vultur .pctlops = &ocelot_pctl_ops, 16048fc0bfcdSHoratiu Vultur .pmxops = &ocelot_pmx_ops, 16058fc0bfcdSHoratiu Vultur .owner = THIS_MODULE, 16068fc0bfcdSHoratiu Vultur }; 16078fc0bfcdSHoratiu Vultur 1608f8a74760SLars Povlsen static struct pinctrl_desc sparx5_desc = { 1609f8a74760SLars Povlsen .name = "sparx5-pinctrl", 1610f8a74760SLars Povlsen .pins = sparx5_pins, 1611f8a74760SLars Povlsen .npins = ARRAY_SIZE(sparx5_pins), 1612f8a74760SLars Povlsen .pctlops = &ocelot_pctl_ops, 1613f8a74760SLars Povlsen .pmxops = &ocelot_pmx_ops, 1614f8a74760SLars Povlsen .confops = &ocelot_confops, 1615f8a74760SLars Povlsen .owner = THIS_MODULE, 1616f8a74760SLars Povlsen }; 1617f8a74760SLars Povlsen 1618531d6ab3SKavyasree Kotagiri static struct pinctrl_desc lan966x_desc = { 1619531d6ab3SKavyasree Kotagiri .name = "lan966x-pinctrl", 1620531d6ab3SKavyasree Kotagiri .pins = lan966x_pins, 1621531d6ab3SKavyasree Kotagiri .npins = ARRAY_SIZE(lan966x_pins), 1622531d6ab3SKavyasree Kotagiri .pctlops = &ocelot_pctl_ops, 1623531d6ab3SKavyasree Kotagiri .pmxops = &lan966x_pmx_ops, 1624531d6ab3SKavyasree Kotagiri .confops = &ocelot_confops, 1625531d6ab3SKavyasree Kotagiri .owner = THIS_MODULE, 1626531d6ab3SKavyasree Kotagiri }; 1627531d6ab3SKavyasree Kotagiri 1628ce8dc094SAlexandre Belloni static int ocelot_create_group_func_map(struct device *dev, 1629ce8dc094SAlexandre Belloni struct ocelot_pinctrl *info) 1630ce8dc094SAlexandre Belloni { 1631ce8dc094SAlexandre Belloni int f, npins, i; 1632da801ab5SAlexandre Belloni u8 *pins = kcalloc(info->desc->npins, sizeof(u8), GFP_KERNEL); 1633da801ab5SAlexandre Belloni 1634da801ab5SAlexandre Belloni if (!pins) 1635da801ab5SAlexandre Belloni return -ENOMEM; 1636ce8dc094SAlexandre Belloni 1637ce8dc094SAlexandre Belloni for (f = 0; f < FUNC_MAX; f++) { 1638da801ab5SAlexandre Belloni for (npins = 0, i = 0; i < info->desc->npins; i++) { 1639da801ab5SAlexandre Belloni if (ocelot_pin_function_idx(info, i, f) >= 0) 1640ce8dc094SAlexandre Belloni pins[npins++] = i; 1641ce8dc094SAlexandre Belloni } 1642ce8dc094SAlexandre Belloni 1643da801ab5SAlexandre Belloni if (!npins) 1644da801ab5SAlexandre Belloni continue; 1645da801ab5SAlexandre Belloni 1646ce8dc094SAlexandre Belloni info->func[f].ngroups = npins; 1647da801ab5SAlexandre Belloni info->func[f].groups = devm_kcalloc(dev, npins, sizeof(char *), 1648ce8dc094SAlexandre Belloni GFP_KERNEL); 1649da801ab5SAlexandre Belloni if (!info->func[f].groups) { 1650da801ab5SAlexandre Belloni kfree(pins); 1651ce8dc094SAlexandre Belloni return -ENOMEM; 1652da801ab5SAlexandre Belloni } 1653ce8dc094SAlexandre Belloni 1654ce8dc094SAlexandre Belloni for (i = 0; i < npins; i++) 1655f8a74760SLars Povlsen info->func[f].groups[i] = 1656f8a74760SLars Povlsen info->desc->pins[pins[i]].name; 1657ce8dc094SAlexandre Belloni } 1658ce8dc094SAlexandre Belloni 1659da801ab5SAlexandre Belloni kfree(pins); 1660da801ab5SAlexandre Belloni 1661ce8dc094SAlexandre Belloni return 0; 1662ce8dc094SAlexandre Belloni } 1663ce8dc094SAlexandre Belloni 1664ce8dc094SAlexandre Belloni static int ocelot_pinctrl_register(struct platform_device *pdev, 1665ce8dc094SAlexandre Belloni struct ocelot_pinctrl *info) 1666ce8dc094SAlexandre Belloni { 1667ce8dc094SAlexandre Belloni int ret; 1668ce8dc094SAlexandre Belloni 1669ce8dc094SAlexandre Belloni ret = ocelot_create_group_func_map(&pdev->dev, info); 1670ce8dc094SAlexandre Belloni if (ret) { 1671ce8dc094SAlexandre Belloni dev_err(&pdev->dev, "Unable to create group func map.\n"); 1672ce8dc094SAlexandre Belloni return ret; 1673ce8dc094SAlexandre Belloni } 1674ce8dc094SAlexandre Belloni 1675da801ab5SAlexandre Belloni info->pctl = devm_pinctrl_register(&pdev->dev, info->desc, info); 1676ce8dc094SAlexandre Belloni if (IS_ERR(info->pctl)) { 1677ce8dc094SAlexandre Belloni dev_err(&pdev->dev, "Failed to register pinctrl\n"); 1678ce8dc094SAlexandre Belloni return PTR_ERR(info->pctl); 1679ce8dc094SAlexandre Belloni } 1680ce8dc094SAlexandre Belloni 1681ce8dc094SAlexandre Belloni return 0; 1682ce8dc094SAlexandre Belloni } 1683ce8dc094SAlexandre Belloni 1684ce8dc094SAlexandre Belloni static int ocelot_gpio_get(struct gpio_chip *chip, unsigned int offset) 1685ce8dc094SAlexandre Belloni { 1686ce8dc094SAlexandre Belloni struct ocelot_pinctrl *info = gpiochip_get_data(chip); 1687ce8dc094SAlexandre Belloni unsigned int val; 1688ce8dc094SAlexandre Belloni 1689da801ab5SAlexandre Belloni regmap_read(info->map, REG(OCELOT_GPIO_IN, info, offset), &val); 1690ce8dc094SAlexandre Belloni 1691da801ab5SAlexandre Belloni return !!(val & BIT(offset % 32)); 1692ce8dc094SAlexandre Belloni } 1693ce8dc094SAlexandre Belloni 1694ce8dc094SAlexandre Belloni static void ocelot_gpio_set(struct gpio_chip *chip, unsigned int offset, 1695ce8dc094SAlexandre Belloni int value) 1696ce8dc094SAlexandre Belloni { 1697ce8dc094SAlexandre Belloni struct ocelot_pinctrl *info = gpiochip_get_data(chip); 1698ce8dc094SAlexandre Belloni 1699ce8dc094SAlexandre Belloni if (value) 1700da801ab5SAlexandre Belloni regmap_write(info->map, REG(OCELOT_GPIO_OUT_SET, info, offset), 1701da801ab5SAlexandre Belloni BIT(offset % 32)); 1702ce8dc094SAlexandre Belloni else 1703da801ab5SAlexandre Belloni regmap_write(info->map, REG(OCELOT_GPIO_OUT_CLR, info, offset), 1704da801ab5SAlexandre Belloni BIT(offset % 32)); 1705ce8dc094SAlexandre Belloni } 1706ce8dc094SAlexandre Belloni 1707ce8dc094SAlexandre Belloni static int ocelot_gpio_get_direction(struct gpio_chip *chip, 1708ce8dc094SAlexandre Belloni unsigned int offset) 1709ce8dc094SAlexandre Belloni { 1710ce8dc094SAlexandre Belloni struct ocelot_pinctrl *info = gpiochip_get_data(chip); 1711ce8dc094SAlexandre Belloni unsigned int val; 1712ce8dc094SAlexandre Belloni 1713da801ab5SAlexandre Belloni regmap_read(info->map, REG(OCELOT_GPIO_OE, info, offset), &val); 1714ce8dc094SAlexandre Belloni 17153c827873SMatti Vaittinen if (val & BIT(offset % 32)) 17163c827873SMatti Vaittinen return GPIO_LINE_DIRECTION_OUT; 17173c827873SMatti Vaittinen 17183c827873SMatti Vaittinen return GPIO_LINE_DIRECTION_IN; 1719ce8dc094SAlexandre Belloni } 1720ce8dc094SAlexandre Belloni 1721ce8dc094SAlexandre Belloni static int ocelot_gpio_direction_input(struct gpio_chip *chip, 1722ce8dc094SAlexandre Belloni unsigned int offset) 1723ce8dc094SAlexandre Belloni { 1724ce8dc094SAlexandre Belloni return pinctrl_gpio_direction_input(chip->base + offset); 1725ce8dc094SAlexandre Belloni } 1726ce8dc094SAlexandre Belloni 1727ce8dc094SAlexandre Belloni static int ocelot_gpio_direction_output(struct gpio_chip *chip, 1728ce8dc094SAlexandre Belloni unsigned int offset, int value) 1729ce8dc094SAlexandre Belloni { 1730ce8dc094SAlexandre Belloni struct ocelot_pinctrl *info = gpiochip_get_data(chip); 1731da801ab5SAlexandre Belloni unsigned int pin = BIT(offset % 32); 1732ce8dc094SAlexandre Belloni 1733ce8dc094SAlexandre Belloni if (value) 1734da801ab5SAlexandre Belloni regmap_write(info->map, REG(OCELOT_GPIO_OUT_SET, info, offset), 1735da801ab5SAlexandre Belloni pin); 1736ce8dc094SAlexandre Belloni else 1737da801ab5SAlexandre Belloni regmap_write(info->map, REG(OCELOT_GPIO_OUT_CLR, info, offset), 1738da801ab5SAlexandre Belloni pin); 1739ce8dc094SAlexandre Belloni 1740ce8dc094SAlexandre Belloni return pinctrl_gpio_direction_output(chip->base + offset); 1741ce8dc094SAlexandre Belloni } 1742ce8dc094SAlexandre Belloni 1743ce8dc094SAlexandre Belloni static const struct gpio_chip ocelot_gpiolib_chip = { 1744ce8dc094SAlexandre Belloni .request = gpiochip_generic_request, 1745ce8dc094SAlexandre Belloni .free = gpiochip_generic_free, 1746ce8dc094SAlexandre Belloni .set = ocelot_gpio_set, 1747ce8dc094SAlexandre Belloni .get = ocelot_gpio_get, 1748ce8dc094SAlexandre Belloni .get_direction = ocelot_gpio_get_direction, 1749ce8dc094SAlexandre Belloni .direction_input = ocelot_gpio_direction_input, 1750ce8dc094SAlexandre Belloni .direction_output = ocelot_gpio_direction_output, 1751ce8dc094SAlexandre Belloni .owner = THIS_MODULE, 1752ce8dc094SAlexandre Belloni }; 1753ce8dc094SAlexandre Belloni 1754be36abb7SQuentin Schulz static void ocelot_irq_mask(struct irq_data *data) 1755be36abb7SQuentin Schulz { 1756be36abb7SQuentin Schulz struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 1757be36abb7SQuentin Schulz struct ocelot_pinctrl *info = gpiochip_get_data(chip); 1758be36abb7SQuentin Schulz unsigned int gpio = irqd_to_hwirq(data); 1759be36abb7SQuentin Schulz 1760da801ab5SAlexandre Belloni regmap_update_bits(info->map, REG(OCELOT_GPIO_INTR_ENA, info, gpio), 1761da801ab5SAlexandre Belloni BIT(gpio % 32), 0); 1762be36abb7SQuentin Schulz } 1763be36abb7SQuentin Schulz 1764be36abb7SQuentin Schulz static void ocelot_irq_unmask(struct irq_data *data) 1765be36abb7SQuentin Schulz { 1766be36abb7SQuentin Schulz struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 1767be36abb7SQuentin Schulz struct ocelot_pinctrl *info = gpiochip_get_data(chip); 1768be36abb7SQuentin Schulz unsigned int gpio = irqd_to_hwirq(data); 1769be36abb7SQuentin Schulz 1770da801ab5SAlexandre Belloni regmap_update_bits(info->map, REG(OCELOT_GPIO_INTR_ENA, info, gpio), 1771da801ab5SAlexandre Belloni BIT(gpio % 32), BIT(gpio % 32)); 1772be36abb7SQuentin Schulz } 1773be36abb7SQuentin Schulz 1774be36abb7SQuentin Schulz static void ocelot_irq_ack(struct irq_data *data) 1775be36abb7SQuentin Schulz { 1776be36abb7SQuentin Schulz struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 1777be36abb7SQuentin Schulz struct ocelot_pinctrl *info = gpiochip_get_data(chip); 1778be36abb7SQuentin Schulz unsigned int gpio = irqd_to_hwirq(data); 1779be36abb7SQuentin Schulz 1780da801ab5SAlexandre Belloni regmap_write_bits(info->map, REG(OCELOT_GPIO_INTR, info, gpio), 1781da801ab5SAlexandre Belloni BIT(gpio % 32), BIT(gpio % 32)); 1782be36abb7SQuentin Schulz } 1783be36abb7SQuentin Schulz 1784be36abb7SQuentin Schulz static int ocelot_irq_set_type(struct irq_data *data, unsigned int type); 1785be36abb7SQuentin Schulz 1786be36abb7SQuentin Schulz static struct irq_chip ocelot_eoi_irqchip = { 1787be36abb7SQuentin Schulz .name = "gpio", 1788be36abb7SQuentin Schulz .irq_mask = ocelot_irq_mask, 1789be36abb7SQuentin Schulz .irq_eoi = ocelot_irq_ack, 1790be36abb7SQuentin Schulz .irq_unmask = ocelot_irq_unmask, 1791be36abb7SQuentin Schulz .flags = IRQCHIP_EOI_THREADED | IRQCHIP_EOI_IF_HANDLED, 1792be36abb7SQuentin Schulz .irq_set_type = ocelot_irq_set_type, 1793be36abb7SQuentin Schulz }; 1794be36abb7SQuentin Schulz 1795be36abb7SQuentin Schulz static struct irq_chip ocelot_irqchip = { 1796be36abb7SQuentin Schulz .name = "gpio", 1797be36abb7SQuentin Schulz .irq_mask = ocelot_irq_mask, 1798be36abb7SQuentin Schulz .irq_ack = ocelot_irq_ack, 1799be36abb7SQuentin Schulz .irq_unmask = ocelot_irq_unmask, 1800be36abb7SQuentin Schulz .irq_set_type = ocelot_irq_set_type, 1801be36abb7SQuentin Schulz }; 1802be36abb7SQuentin Schulz 1803be36abb7SQuentin Schulz static int ocelot_irq_set_type(struct irq_data *data, unsigned int type) 1804be36abb7SQuentin Schulz { 1805be36abb7SQuentin Schulz type &= IRQ_TYPE_SENSE_MASK; 1806be36abb7SQuentin Schulz 1807be36abb7SQuentin Schulz if (!(type & (IRQ_TYPE_EDGE_BOTH | IRQ_TYPE_LEVEL_HIGH))) 1808be36abb7SQuentin Schulz return -EINVAL; 1809be36abb7SQuentin Schulz 1810be36abb7SQuentin Schulz if (type & IRQ_TYPE_LEVEL_HIGH) 1811be36abb7SQuentin Schulz irq_set_chip_handler_name_locked(data, &ocelot_eoi_irqchip, 1812be36abb7SQuentin Schulz handle_fasteoi_irq, NULL); 1813be36abb7SQuentin Schulz if (type & IRQ_TYPE_EDGE_BOTH) 1814be36abb7SQuentin Schulz irq_set_chip_handler_name_locked(data, &ocelot_irqchip, 1815be36abb7SQuentin Schulz handle_edge_irq, NULL); 1816be36abb7SQuentin Schulz 1817be36abb7SQuentin Schulz return 0; 1818be36abb7SQuentin Schulz } 1819be36abb7SQuentin Schulz 1820be36abb7SQuentin Schulz static void ocelot_irq_handler(struct irq_desc *desc) 1821be36abb7SQuentin Schulz { 1822be36abb7SQuentin Schulz struct irq_chip *parent_chip = irq_desc_get_chip(desc); 1823be36abb7SQuentin Schulz struct gpio_chip *chip = irq_desc_get_handler_data(desc); 1824be36abb7SQuentin Schulz struct ocelot_pinctrl *info = gpiochip_get_data(chip); 18250b47afc6SLars Povlsen unsigned int id_reg = OCELOT_GPIO_INTR_IDENT * info->stride; 1826da801ab5SAlexandre Belloni unsigned int reg = 0, irq, i; 1827be36abb7SQuentin Schulz unsigned long irqs; 1828be36abb7SQuentin Schulz 1829da801ab5SAlexandre Belloni for (i = 0; i < info->stride; i++) { 18300b47afc6SLars Povlsen regmap_read(info->map, id_reg + 4 * i, ®); 1831be36abb7SQuentin Schulz if (!reg) 1832da801ab5SAlexandre Belloni continue; 1833be36abb7SQuentin Schulz 1834be36abb7SQuentin Schulz chained_irq_enter(parent_chip, desc); 1835be36abb7SQuentin Schulz 1836be36abb7SQuentin Schulz irqs = reg; 1837be36abb7SQuentin Schulz 1838da801ab5SAlexandre Belloni for_each_set_bit(irq, &irqs, 1839da801ab5SAlexandre Belloni min(32U, info->desc->npins - 32 * i)) 1840a9cb09b7SMarc Zyngier generic_handle_domain_irq(chip->irq.domain, irq + 32 * i); 1841be36abb7SQuentin Schulz 1842be36abb7SQuentin Schulz chained_irq_exit(parent_chip, desc); 1843be36abb7SQuentin Schulz } 1844da801ab5SAlexandre Belloni } 1845be36abb7SQuentin Schulz 1846ce8dc094SAlexandre Belloni static int ocelot_gpiochip_register(struct platform_device *pdev, 1847ce8dc094SAlexandre Belloni struct ocelot_pinctrl *info) 1848ce8dc094SAlexandre Belloni { 1849ce8dc094SAlexandre Belloni struct gpio_chip *gc; 1850d874becaSLinus Walleij struct gpio_irq_chip *girq; 185117f2c8d3SQinglang Miao int irq; 1852ce8dc094SAlexandre Belloni 1853ce8dc094SAlexandre Belloni info->gpio_chip = ocelot_gpiolib_chip; 1854ce8dc094SAlexandre Belloni 1855ce8dc094SAlexandre Belloni gc = &info->gpio_chip; 1856da801ab5SAlexandre Belloni gc->ngpio = info->desc->npins; 1857ce8dc094SAlexandre Belloni gc->parent = &pdev->dev; 1858a159c2b4SColin Foster gc->base = -1; 1859ce8dc094SAlexandre Belloni gc->label = "ocelot-gpio"; 1860ce8dc094SAlexandre Belloni 1861d1f2c82fSHoratiu Vultur irq = platform_get_irq_optional(pdev, 0); 1862d1f2c82fSHoratiu Vultur if (irq > 0) { 1863d874becaSLinus Walleij girq = &gc->irq; 1864d874becaSLinus Walleij girq->chip = &ocelot_irqchip; 1865d874becaSLinus Walleij girq->parent_handler = ocelot_irq_handler; 1866d874becaSLinus Walleij girq->num_parents = 1; 1867550713e3SLars Povlsen girq->parents = devm_kcalloc(&pdev->dev, 1, 1868550713e3SLars Povlsen sizeof(*girq->parents), 1869d874becaSLinus Walleij GFP_KERNEL); 1870d874becaSLinus Walleij if (!girq->parents) 1871d874becaSLinus Walleij return -ENOMEM; 1872d874becaSLinus Walleij girq->parents[0] = irq; 1873d874becaSLinus Walleij girq->default_type = IRQ_TYPE_NONE; 1874d874becaSLinus Walleij girq->handler = handle_edge_irq; 1875550713e3SLars Povlsen } 1876d874becaSLinus Walleij 187717f2c8d3SQinglang Miao return devm_gpiochip_add_data(&pdev->dev, gc, info); 1878ce8dc094SAlexandre Belloni } 1879ce8dc094SAlexandre Belloni 1880ce8dc094SAlexandre Belloni static const struct of_device_id ocelot_pinctrl_of_match[] = { 18818f27440dSLars Povlsen { .compatible = "mscc,luton-pinctrl", .data = &luton_desc }, 18826e6347e2SLars Povlsen { .compatible = "mscc,serval-pinctrl", .data = &serval_desc }, 1883da801ab5SAlexandre Belloni { .compatible = "mscc,ocelot-pinctrl", .data = &ocelot_desc }, 1884da801ab5SAlexandre Belloni { .compatible = "mscc,jaguar2-pinctrl", .data = &jaguar2_desc }, 18858fc0bfcdSHoratiu Vultur { .compatible = "mscc,servalt-pinctrl", .data = &servalt_desc }, 1886f8a74760SLars Povlsen { .compatible = "microchip,sparx5-pinctrl", .data = &sparx5_desc }, 1887531d6ab3SKavyasree Kotagiri { .compatible = "microchip,lan966x-pinctrl", .data = &lan966x_desc }, 1888ce8dc094SAlexandre Belloni {}, 1889ce8dc094SAlexandre Belloni }; 1890ce8dc094SAlexandre Belloni 1891076d9e71SColin Foster static struct regmap *ocelot_pinctrl_create_pincfg(struct platform_device *pdev) 1892076d9e71SColin Foster { 1893076d9e71SColin Foster void __iomem *base; 1894076d9e71SColin Foster 1895076d9e71SColin Foster const struct regmap_config regmap_config = { 1896076d9e71SColin Foster .reg_bits = 32, 1897076d9e71SColin Foster .val_bits = 32, 1898076d9e71SColin Foster .reg_stride = 4, 1899076d9e71SColin Foster .max_register = 32, 1900359afd90SMichael Walle .name = "pincfg", 1901076d9e71SColin Foster }; 1902076d9e71SColin Foster 190394ef3297SMichael Walle base = devm_platform_ioremap_resource(pdev, 1); 1904076d9e71SColin Foster if (IS_ERR(base)) { 1905076d9e71SColin Foster dev_dbg(&pdev->dev, "Failed to ioremap config registers (no extended pinconf)\n"); 1906076d9e71SColin Foster return NULL; 1907076d9e71SColin Foster } 1908076d9e71SColin Foster 1909076d9e71SColin Foster return devm_regmap_init_mmio(&pdev->dev, base, ®map_config); 1910076d9e71SColin Foster } 1911076d9e71SColin Foster 1912ce3e7f0eSColin Ian King static int ocelot_pinctrl_probe(struct platform_device *pdev) 1913ce8dc094SAlexandre Belloni { 1914ce8dc094SAlexandre Belloni struct device *dev = &pdev->dev; 1915ce8dc094SAlexandre Belloni struct ocelot_pinctrl *info; 1916*453200afSMichael Walle struct reset_control *reset; 1917076d9e71SColin Foster struct regmap *pincfg; 1918ce8dc094SAlexandre Belloni void __iomem *base; 1919ce8dc094SAlexandre Belloni int ret; 1920da801ab5SAlexandre Belloni struct regmap_config regmap_config = { 1921da801ab5SAlexandre Belloni .reg_bits = 32, 1922da801ab5SAlexandre Belloni .val_bits = 32, 1923da801ab5SAlexandre Belloni .reg_stride = 4, 1924da801ab5SAlexandre Belloni }; 1925ce8dc094SAlexandre Belloni 1926ce8dc094SAlexandre Belloni info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL); 1927ce8dc094SAlexandre Belloni if (!info) 1928ce8dc094SAlexandre Belloni return -ENOMEM; 1929ce8dc094SAlexandre Belloni 1930da801ab5SAlexandre Belloni info->desc = (struct pinctrl_desc *)device_get_match_data(dev); 1931da801ab5SAlexandre Belloni 1932*453200afSMichael Walle reset = devm_reset_control_get_optional_shared(dev, "switch"); 1933*453200afSMichael Walle if (IS_ERR(reset)) 1934*453200afSMichael Walle return dev_err_probe(dev, PTR_ERR(reset), 1935*453200afSMichael Walle "Failed to get reset\n"); 1936*453200afSMichael Walle reset_control_reset(reset); 1937*453200afSMichael Walle 1938ce8dc094SAlexandre Belloni base = devm_ioremap_resource(dev, 1939ce8dc094SAlexandre Belloni platform_get_resource(pdev, IORESOURCE_MEM, 0)); 19400f9facdbSZhen Lei if (IS_ERR(base)) 1941ce8dc094SAlexandre Belloni return PTR_ERR(base); 1942ce8dc094SAlexandre Belloni 1943da801ab5SAlexandre Belloni info->stride = 1 + (info->desc->npins - 1) / 32; 1944f8a74760SLars Povlsen 1945da801ab5SAlexandre Belloni regmap_config.max_register = OCELOT_GPIO_SD_MAP * info->stride + 15 * 4; 1946da801ab5SAlexandre Belloni 1947da801ab5SAlexandre Belloni info->map = devm_regmap_init_mmio(dev, base, ®map_config); 1948ce8dc094SAlexandre Belloni if (IS_ERR(info->map)) { 1949ce8dc094SAlexandre Belloni dev_err(dev, "Failed to create regmap\n"); 1950ce8dc094SAlexandre Belloni return PTR_ERR(info->map); 1951ce8dc094SAlexandre Belloni } 1952ce8dc094SAlexandre Belloni dev_set_drvdata(dev, info->map); 1953ce8dc094SAlexandre Belloni info->dev = dev; 1954ce8dc094SAlexandre Belloni 1955f8a74760SLars Povlsen /* Pinconf registers */ 1956f8a74760SLars Povlsen if (info->desc->confops) { 1957076d9e71SColin Foster pincfg = ocelot_pinctrl_create_pincfg(pdev); 1958076d9e71SColin Foster if (IS_ERR(pincfg)) 1959076d9e71SColin Foster dev_dbg(dev, "Failed to create pincfg regmap\n"); 1960f8a74760SLars Povlsen else 1961076d9e71SColin Foster info->pincfg = pincfg; 1962f8a74760SLars Povlsen } 1963f8a74760SLars Povlsen 1964ce8dc094SAlexandre Belloni ret = ocelot_pinctrl_register(pdev, info); 1965ce8dc094SAlexandre Belloni if (ret) 1966ce8dc094SAlexandre Belloni return ret; 1967ce8dc094SAlexandre Belloni 1968ce8dc094SAlexandre Belloni ret = ocelot_gpiochip_register(pdev, info); 1969ce8dc094SAlexandre Belloni if (ret) 1970ce8dc094SAlexandre Belloni return ret; 1971ce8dc094SAlexandre Belloni 1972f8a74760SLars Povlsen dev_info(dev, "driver registered\n"); 1973f8a74760SLars Povlsen 1974ce8dc094SAlexandre Belloni return 0; 1975ce8dc094SAlexandre Belloni } 1976ce8dc094SAlexandre Belloni 1977ce8dc094SAlexandre Belloni static struct platform_driver ocelot_pinctrl_driver = { 1978ce8dc094SAlexandre Belloni .driver = { 1979ce8dc094SAlexandre Belloni .name = "pinctrl-ocelot", 1980ce8dc094SAlexandre Belloni .of_match_table = of_match_ptr(ocelot_pinctrl_of_match), 1981ce8dc094SAlexandre Belloni .suppress_bind_attrs = true, 1982ce8dc094SAlexandre Belloni }, 1983ce8dc094SAlexandre Belloni .probe = ocelot_pinctrl_probe, 1984ce8dc094SAlexandre Belloni }; 1985ce8dc094SAlexandre Belloni builtin_platform_driver(ocelot_pinctrl_driver); 1986