1 /* MCP23S08 SPI/I2C GPIO driver */ 2 3 #include <linux/kernel.h> 4 #include <linux/device.h> 5 #include <linux/mutex.h> 6 #include <linux/module.h> 7 #include <linux/gpio.h> 8 #include <linux/i2c.h> 9 #include <linux/spi/spi.h> 10 #include <linux/spi/mcp23s08.h> 11 #include <linux/slab.h> 12 #include <asm/byteorder.h> 13 #include <linux/interrupt.h> 14 #include <linux/of_device.h> 15 #include <linux/regmap.h> 16 #include <linux/pinctrl/pinctrl.h> 17 #include <linux/pinctrl/pinconf.h> 18 #include <linux/pinctrl/pinconf-generic.h> 19 20 /* 21 * MCP types supported by driver 22 */ 23 #define MCP_TYPE_S08 0 24 #define MCP_TYPE_S17 1 25 #define MCP_TYPE_008 2 26 #define MCP_TYPE_017 3 27 #define MCP_TYPE_S18 4 28 29 #define MCP_MAX_DEV_PER_CS 8 30 31 /* Registers are all 8 bits wide. 32 * 33 * The mcp23s17 has twice as many bits, and can be configured to work 34 * with either 16 bit registers or with two adjacent 8 bit banks. 35 */ 36 #define MCP_IODIR 0x00 /* init/reset: all ones */ 37 #define MCP_IPOL 0x01 38 #define MCP_GPINTEN 0x02 39 #define MCP_DEFVAL 0x03 40 #define MCP_INTCON 0x04 41 #define MCP_IOCON 0x05 42 # define IOCON_MIRROR (1 << 6) 43 # define IOCON_SEQOP (1 << 5) 44 # define IOCON_HAEN (1 << 3) 45 # define IOCON_ODR (1 << 2) 46 # define IOCON_INTPOL (1 << 1) 47 # define IOCON_INTCC (1) 48 #define MCP_GPPU 0x06 49 #define MCP_INTF 0x07 50 #define MCP_INTCAP 0x08 51 #define MCP_GPIO 0x09 52 #define MCP_OLAT 0x0a 53 54 struct mcp23s08; 55 56 struct mcp23s08 { 57 u8 addr; 58 bool irq_active_high; 59 bool reg_shift; 60 61 u16 irq_rise; 62 u16 irq_fall; 63 int irq; 64 bool irq_controller; 65 int cached_gpio; 66 /* lock protects regmap access with bypass/cache flags */ 67 struct mutex lock; 68 69 struct gpio_chip chip; 70 71 struct regmap *regmap; 72 struct device *dev; 73 74 struct pinctrl_dev *pctldev; 75 struct pinctrl_desc pinctrl_desc; 76 }; 77 78 static const struct reg_default mcp23x08_defaults[] = { 79 {.reg = MCP_IODIR, .def = 0xff}, 80 {.reg = MCP_IPOL, .def = 0x00}, 81 {.reg = MCP_GPINTEN, .def = 0x00}, 82 {.reg = MCP_DEFVAL, .def = 0x00}, 83 {.reg = MCP_INTCON, .def = 0x00}, 84 {.reg = MCP_IOCON, .def = 0x00}, 85 {.reg = MCP_GPPU, .def = 0x00}, 86 {.reg = MCP_OLAT, .def = 0x00}, 87 }; 88 89 static const struct regmap_range mcp23x08_volatile_range = { 90 .range_min = MCP_INTF, 91 .range_max = MCP_GPIO, 92 }; 93 94 static const struct regmap_access_table mcp23x08_volatile_table = { 95 .yes_ranges = &mcp23x08_volatile_range, 96 .n_yes_ranges = 1, 97 }; 98 99 static const struct regmap_range mcp23x08_precious_range = { 100 .range_min = MCP_GPIO, 101 .range_max = MCP_GPIO, 102 }; 103 104 static const struct regmap_access_table mcp23x08_precious_table = { 105 .yes_ranges = &mcp23x08_precious_range, 106 .n_yes_ranges = 1, 107 }; 108 109 static const struct regmap_config mcp23x08_regmap = { 110 .reg_bits = 8, 111 .val_bits = 8, 112 113 .reg_stride = 1, 114 .volatile_table = &mcp23x08_volatile_table, 115 .precious_table = &mcp23x08_precious_table, 116 .reg_defaults = mcp23x08_defaults, 117 .num_reg_defaults = ARRAY_SIZE(mcp23x08_defaults), 118 .cache_type = REGCACHE_FLAT, 119 .max_register = MCP_OLAT, 120 }; 121 122 static const struct reg_default mcp23x16_defaults[] = { 123 {.reg = MCP_IODIR << 1, .def = 0xffff}, 124 {.reg = MCP_IPOL << 1, .def = 0x0000}, 125 {.reg = MCP_GPINTEN << 1, .def = 0x0000}, 126 {.reg = MCP_DEFVAL << 1, .def = 0x0000}, 127 {.reg = MCP_INTCON << 1, .def = 0x0000}, 128 {.reg = MCP_IOCON << 1, .def = 0x0000}, 129 {.reg = MCP_GPPU << 1, .def = 0x0000}, 130 {.reg = MCP_OLAT << 1, .def = 0x0000}, 131 }; 132 133 static const struct regmap_range mcp23x16_volatile_range = { 134 .range_min = MCP_INTF << 1, 135 .range_max = MCP_GPIO << 1, 136 }; 137 138 static const struct regmap_access_table mcp23x16_volatile_table = { 139 .yes_ranges = &mcp23x16_volatile_range, 140 .n_yes_ranges = 1, 141 }; 142 143 static const struct regmap_range mcp23x16_precious_range = { 144 .range_min = MCP_GPIO << 1, 145 .range_max = MCP_GPIO << 1, 146 }; 147 148 static const struct regmap_access_table mcp23x16_precious_table = { 149 .yes_ranges = &mcp23x16_precious_range, 150 .n_yes_ranges = 1, 151 }; 152 153 static const struct regmap_config mcp23x17_regmap = { 154 .reg_bits = 8, 155 .val_bits = 16, 156 157 .reg_stride = 2, 158 .max_register = MCP_OLAT << 1, 159 .volatile_table = &mcp23x16_volatile_table, 160 .precious_table = &mcp23x16_precious_table, 161 .reg_defaults = mcp23x16_defaults, 162 .num_reg_defaults = ARRAY_SIZE(mcp23x16_defaults), 163 .cache_type = REGCACHE_FLAT, 164 .val_format_endian = REGMAP_ENDIAN_LITTLE, 165 }; 166 167 static int mcp_read(struct mcp23s08 *mcp, unsigned int reg, unsigned int *val) 168 { 169 return regmap_read(mcp->regmap, reg << mcp->reg_shift, val); 170 } 171 172 static int mcp_write(struct mcp23s08 *mcp, unsigned int reg, unsigned int val) 173 { 174 return regmap_write(mcp->regmap, reg << mcp->reg_shift, val); 175 } 176 177 static int mcp_set_mask(struct mcp23s08 *mcp, unsigned int reg, 178 unsigned int mask, bool enabled) 179 { 180 u16 val = enabled ? 0xffff : 0x0000; 181 return regmap_update_bits(mcp->regmap, reg << mcp->reg_shift, 182 mask, val); 183 } 184 185 static int mcp_set_bit(struct mcp23s08 *mcp, unsigned int reg, 186 unsigned int pin, bool enabled) 187 { 188 u16 mask = BIT(pin); 189 return mcp_set_mask(mcp, reg, mask, enabled); 190 } 191 192 static const struct pinctrl_pin_desc mcp23x08_pins[] = { 193 PINCTRL_PIN(0, "gpio0"), 194 PINCTRL_PIN(1, "gpio1"), 195 PINCTRL_PIN(2, "gpio2"), 196 PINCTRL_PIN(3, "gpio3"), 197 PINCTRL_PIN(4, "gpio4"), 198 PINCTRL_PIN(5, "gpio5"), 199 PINCTRL_PIN(6, "gpio6"), 200 PINCTRL_PIN(7, "gpio7"), 201 }; 202 203 static const struct pinctrl_pin_desc mcp23x17_pins[] = { 204 PINCTRL_PIN(0, "gpio0"), 205 PINCTRL_PIN(1, "gpio1"), 206 PINCTRL_PIN(2, "gpio2"), 207 PINCTRL_PIN(3, "gpio3"), 208 PINCTRL_PIN(4, "gpio4"), 209 PINCTRL_PIN(5, "gpio5"), 210 PINCTRL_PIN(6, "gpio6"), 211 PINCTRL_PIN(7, "gpio7"), 212 PINCTRL_PIN(8, "gpio8"), 213 PINCTRL_PIN(9, "gpio9"), 214 PINCTRL_PIN(10, "gpio10"), 215 PINCTRL_PIN(11, "gpio11"), 216 PINCTRL_PIN(12, "gpio12"), 217 PINCTRL_PIN(13, "gpio13"), 218 PINCTRL_PIN(14, "gpio14"), 219 PINCTRL_PIN(15, "gpio15"), 220 }; 221 222 static int mcp_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) 223 { 224 return 0; 225 } 226 227 static const char *mcp_pinctrl_get_group_name(struct pinctrl_dev *pctldev, 228 unsigned int group) 229 { 230 return NULL; 231 } 232 233 static int mcp_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, 234 unsigned int group, 235 const unsigned int **pins, 236 unsigned int *num_pins) 237 { 238 return -ENOTSUPP; 239 } 240 241 static const struct pinctrl_ops mcp_pinctrl_ops = { 242 .get_groups_count = mcp_pinctrl_get_groups_count, 243 .get_group_name = mcp_pinctrl_get_group_name, 244 .get_group_pins = mcp_pinctrl_get_group_pins, 245 #ifdef CONFIG_OF 246 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, 247 .dt_free_map = pinconf_generic_dt_free_map, 248 #endif 249 }; 250 251 static int mcp_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, 252 unsigned long *config) 253 { 254 struct mcp23s08 *mcp = pinctrl_dev_get_drvdata(pctldev); 255 enum pin_config_param param = pinconf_to_config_param(*config); 256 unsigned int data, status; 257 int ret; 258 259 switch (param) { 260 case PIN_CONFIG_BIAS_PULL_UP: 261 ret = mcp_read(mcp, MCP_GPPU, &data); 262 if (ret < 0) 263 return ret; 264 status = (data & BIT(pin)) ? 1 : 0; 265 break; 266 default: 267 dev_err(mcp->dev, "Invalid config param %04x\n", param); 268 return -ENOTSUPP; 269 } 270 271 *config = 0; 272 273 return status ? 0 : -EINVAL; 274 } 275 276 static int mcp_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 277 unsigned long *configs, unsigned int num_configs) 278 { 279 struct mcp23s08 *mcp = pinctrl_dev_get_drvdata(pctldev); 280 enum pin_config_param param; 281 u32 arg, mask; 282 u16 val; 283 int ret = 0; 284 int i; 285 286 for (i = 0; i < num_configs; i++) { 287 param = pinconf_to_config_param(configs[i]); 288 arg = pinconf_to_config_argument(configs[i]); 289 290 switch (param) { 291 case PIN_CONFIG_BIAS_PULL_UP: 292 val = arg ? 0xFFFF : 0x0000; 293 mask = BIT(pin); 294 ret = mcp_set_bit(mcp, MCP_GPPU, pin, arg); 295 break; 296 default: 297 dev_err(mcp->dev, "Invalid config param %04x\n", param); 298 return -ENOTSUPP; 299 } 300 } 301 302 return ret; 303 } 304 305 static const struct pinconf_ops mcp_pinconf_ops = { 306 .pin_config_get = mcp_pinconf_get, 307 .pin_config_set = mcp_pinconf_set, 308 .is_generic = true, 309 }; 310 311 /*----------------------------------------------------------------------*/ 312 313 #ifdef CONFIG_SPI_MASTER 314 315 static int mcp23sxx_spi_write(void *context, const void *data, size_t count) 316 { 317 struct mcp23s08 *mcp = context; 318 struct spi_device *spi = to_spi_device(mcp->dev); 319 struct spi_message m; 320 struct spi_transfer t[2] = { { .tx_buf = &mcp->addr, .len = 1, }, 321 { .tx_buf = data, .len = count, }, }; 322 323 spi_message_init(&m); 324 spi_message_add_tail(&t[0], &m); 325 spi_message_add_tail(&t[1], &m); 326 327 return spi_sync(spi, &m); 328 } 329 330 static int mcp23sxx_spi_gather_write(void *context, 331 const void *reg, size_t reg_size, 332 const void *val, size_t val_size) 333 { 334 struct mcp23s08 *mcp = context; 335 struct spi_device *spi = to_spi_device(mcp->dev); 336 struct spi_message m; 337 struct spi_transfer t[3] = { { .tx_buf = &mcp->addr, .len = 1, }, 338 { .tx_buf = reg, .len = reg_size, }, 339 { .tx_buf = val, .len = val_size, }, }; 340 341 spi_message_init(&m); 342 spi_message_add_tail(&t[0], &m); 343 spi_message_add_tail(&t[1], &m); 344 spi_message_add_tail(&t[2], &m); 345 346 return spi_sync(spi, &m); 347 } 348 349 static int mcp23sxx_spi_read(void *context, const void *reg, size_t reg_size, 350 void *val, size_t val_size) 351 { 352 struct mcp23s08 *mcp = context; 353 struct spi_device *spi = to_spi_device(mcp->dev); 354 u8 tx[2]; 355 356 if (reg_size != 1) 357 return -EINVAL; 358 359 tx[0] = mcp->addr | 0x01; 360 tx[1] = *((u8 *) reg); 361 362 return spi_write_then_read(spi, tx, sizeof(tx), val, val_size); 363 } 364 365 static const struct regmap_bus mcp23sxx_spi_regmap = { 366 .write = mcp23sxx_spi_write, 367 .gather_write = mcp23sxx_spi_gather_write, 368 .read = mcp23sxx_spi_read, 369 }; 370 371 #endif /* CONFIG_SPI_MASTER */ 372 373 /*----------------------------------------------------------------------*/ 374 375 /* A given spi_device can represent up to eight mcp23sxx chips 376 * sharing the same chipselect but using different addresses 377 * (e.g. chips #0 and #3 might be populated, but not #1 or $2). 378 * Driver data holds all the per-chip data. 379 */ 380 struct mcp23s08_driver_data { 381 unsigned ngpio; 382 struct mcp23s08 *mcp[8]; 383 struct mcp23s08 chip[]; 384 }; 385 386 387 static int mcp23s08_direction_input(struct gpio_chip *chip, unsigned offset) 388 { 389 struct mcp23s08 *mcp = gpiochip_get_data(chip); 390 int status; 391 392 mutex_lock(&mcp->lock); 393 status = mcp_set_bit(mcp, MCP_IODIR, offset, true); 394 mutex_unlock(&mcp->lock); 395 396 return status; 397 } 398 399 static int mcp23s08_get(struct gpio_chip *chip, unsigned offset) 400 { 401 struct mcp23s08 *mcp = gpiochip_get_data(chip); 402 int status, ret; 403 404 mutex_lock(&mcp->lock); 405 406 /* REVISIT reading this clears any IRQ ... */ 407 ret = mcp_read(mcp, MCP_GPIO, &status); 408 if (ret < 0) 409 status = 0; 410 else { 411 mcp->cached_gpio = status; 412 status = !!(status & (1 << offset)); 413 } 414 415 mutex_unlock(&mcp->lock); 416 return status; 417 } 418 419 static int __mcp23s08_set(struct mcp23s08 *mcp, unsigned mask, bool value) 420 { 421 return mcp_set_mask(mcp, MCP_OLAT, mask, value); 422 } 423 424 static void mcp23s08_set(struct gpio_chip *chip, unsigned offset, int value) 425 { 426 struct mcp23s08 *mcp = gpiochip_get_data(chip); 427 unsigned mask = BIT(offset); 428 429 mutex_lock(&mcp->lock); 430 __mcp23s08_set(mcp, mask, !!value); 431 mutex_unlock(&mcp->lock); 432 } 433 434 static int 435 mcp23s08_direction_output(struct gpio_chip *chip, unsigned offset, int value) 436 { 437 struct mcp23s08 *mcp = gpiochip_get_data(chip); 438 unsigned mask = BIT(offset); 439 int status; 440 441 mutex_lock(&mcp->lock); 442 status = __mcp23s08_set(mcp, mask, value); 443 if (status == 0) { 444 status = mcp_set_mask(mcp, MCP_IODIR, mask, false); 445 } 446 mutex_unlock(&mcp->lock); 447 return status; 448 } 449 450 /*----------------------------------------------------------------------*/ 451 static irqreturn_t mcp23s08_irq(int irq, void *data) 452 { 453 struct mcp23s08 *mcp = data; 454 int intcap, intcon, intf, i, gpio, gpio_orig, intcap_mask, defval; 455 unsigned int child_irq; 456 bool intf_set, intcap_changed, gpio_bit_changed, 457 defval_changed, gpio_set; 458 459 mutex_lock(&mcp->lock); 460 if (mcp_read(mcp, MCP_INTF, &intf) < 0) { 461 mutex_unlock(&mcp->lock); 462 return IRQ_HANDLED; 463 } 464 465 if (mcp_read(mcp, MCP_INTCAP, &intcap) < 0) { 466 mutex_unlock(&mcp->lock); 467 return IRQ_HANDLED; 468 } 469 470 if (mcp_read(mcp, MCP_INTCON, &intcon) < 0) { 471 mutex_unlock(&mcp->lock); 472 return IRQ_HANDLED; 473 } 474 475 if (mcp_read(mcp, MCP_DEFVAL, &defval) < 0) { 476 mutex_unlock(&mcp->lock); 477 return IRQ_HANDLED; 478 } 479 480 /* This clears the interrupt(configurable on S18) */ 481 if (mcp_read(mcp, MCP_GPIO, &gpio) < 0) { 482 mutex_unlock(&mcp->lock); 483 return IRQ_HANDLED; 484 } 485 gpio_orig = mcp->cached_gpio; 486 mcp->cached_gpio = gpio; 487 mutex_unlock(&mcp->lock); 488 489 if (intf == 0) { 490 /* There is no interrupt pending */ 491 return IRQ_HANDLED; 492 } 493 494 dev_dbg(mcp->chip.parent, 495 "intcap 0x%04X intf 0x%04X gpio_orig 0x%04X gpio 0x%04X\n", 496 intcap, intf, gpio_orig, gpio); 497 498 for (i = 0; i < mcp->chip.ngpio; i++) { 499 /* We must check all of the inputs on the chip, 500 * otherwise we may not notice a change on >=2 pins. 501 * 502 * On at least the mcp23s17, INTCAP is only updated 503 * one byte at a time(INTCAPA and INTCAPB are 504 * not written to at the same time - only on a per-bank 505 * basis). 506 * 507 * INTF only contains the single bit that caused the 508 * interrupt per-bank. On the mcp23s17, there is 509 * INTFA and INTFB. If two pins are changed on the A 510 * side at the same time, INTF will only have one bit 511 * set. If one pin on the A side and one pin on the B 512 * side are changed at the same time, INTF will have 513 * two bits set. Thus, INTF can't be the only check 514 * to see if the input has changed. 515 */ 516 517 intf_set = intf & BIT(i); 518 if (i < 8 && intf_set) 519 intcap_mask = 0x00FF; 520 else if (i >= 8 && intf_set) 521 intcap_mask = 0xFF00; 522 else 523 intcap_mask = 0x00; 524 525 intcap_changed = (intcap_mask & 526 (intcap & BIT(i))) != 527 (intcap_mask & (BIT(i) & gpio_orig)); 528 gpio_set = BIT(i) & gpio; 529 gpio_bit_changed = (BIT(i) & gpio_orig) != 530 (BIT(i) & gpio); 531 defval_changed = (BIT(i) & intcon) && 532 ((BIT(i) & gpio) != 533 (BIT(i) & defval)); 534 535 if (((gpio_bit_changed || intcap_changed) && 536 (BIT(i) & mcp->irq_rise) && gpio_set) || 537 ((gpio_bit_changed || intcap_changed) && 538 (BIT(i) & mcp->irq_fall) && !gpio_set) || 539 defval_changed) { 540 child_irq = irq_find_mapping(mcp->chip.irqdomain, i); 541 handle_nested_irq(child_irq); 542 } 543 } 544 545 return IRQ_HANDLED; 546 } 547 548 static void mcp23s08_irq_mask(struct irq_data *data) 549 { 550 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 551 struct mcp23s08 *mcp = gpiochip_get_data(gc); 552 unsigned int pos = data->hwirq; 553 554 mcp_set_bit(mcp, MCP_GPINTEN, pos, false); 555 } 556 557 static void mcp23s08_irq_unmask(struct irq_data *data) 558 { 559 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 560 struct mcp23s08 *mcp = gpiochip_get_data(gc); 561 unsigned int pos = data->hwirq; 562 563 mcp_set_bit(mcp, MCP_GPINTEN, pos, true); 564 } 565 566 static int mcp23s08_irq_set_type(struct irq_data *data, unsigned int type) 567 { 568 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 569 struct mcp23s08 *mcp = gpiochip_get_data(gc); 570 unsigned int pos = data->hwirq; 571 int status = 0; 572 573 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) { 574 mcp_set_bit(mcp, MCP_INTCON, pos, false); 575 mcp->irq_rise |= BIT(pos); 576 mcp->irq_fall |= BIT(pos); 577 } else if (type & IRQ_TYPE_EDGE_RISING) { 578 mcp_set_bit(mcp, MCP_INTCON, pos, false); 579 mcp->irq_rise |= BIT(pos); 580 mcp->irq_fall &= ~BIT(pos); 581 } else if (type & IRQ_TYPE_EDGE_FALLING) { 582 mcp_set_bit(mcp, MCP_INTCON, pos, false); 583 mcp->irq_rise &= ~BIT(pos); 584 mcp->irq_fall |= BIT(pos); 585 } else if (type & IRQ_TYPE_LEVEL_HIGH) { 586 mcp_set_bit(mcp, MCP_INTCON, pos, true); 587 mcp_set_bit(mcp, MCP_DEFVAL, pos, false); 588 } else if (type & IRQ_TYPE_LEVEL_LOW) { 589 mcp_set_bit(mcp, MCP_INTCON, pos, true); 590 mcp_set_bit(mcp, MCP_DEFVAL, pos, true); 591 } else 592 return -EINVAL; 593 594 return status; 595 } 596 597 static void mcp23s08_irq_bus_lock(struct irq_data *data) 598 { 599 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 600 struct mcp23s08 *mcp = gpiochip_get_data(gc); 601 602 mutex_lock(&mcp->lock); 603 regcache_cache_only(mcp->regmap, true); 604 } 605 606 static void mcp23s08_irq_bus_unlock(struct irq_data *data) 607 { 608 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 609 struct mcp23s08 *mcp = gpiochip_get_data(gc); 610 611 regcache_cache_only(mcp->regmap, false); 612 regcache_sync(mcp->regmap); 613 614 mutex_unlock(&mcp->lock); 615 } 616 617 static struct irq_chip mcp23s08_irq_chip = { 618 .name = "gpio-mcp23xxx", 619 .irq_mask = mcp23s08_irq_mask, 620 .irq_unmask = mcp23s08_irq_unmask, 621 .irq_set_type = mcp23s08_irq_set_type, 622 .irq_bus_lock = mcp23s08_irq_bus_lock, 623 .irq_bus_sync_unlock = mcp23s08_irq_bus_unlock, 624 }; 625 626 static int mcp23s08_irq_setup(struct mcp23s08 *mcp) 627 { 628 struct gpio_chip *chip = &mcp->chip; 629 int err; 630 unsigned long irqflags = IRQF_ONESHOT | IRQF_SHARED; 631 632 if (mcp->irq_active_high) 633 irqflags |= IRQF_TRIGGER_HIGH; 634 else 635 irqflags |= IRQF_TRIGGER_LOW; 636 637 err = devm_request_threaded_irq(chip->parent, mcp->irq, NULL, 638 mcp23s08_irq, 639 irqflags, dev_name(chip->parent), mcp); 640 if (err != 0) { 641 dev_err(chip->parent, "unable to request IRQ#%d: %d\n", 642 mcp->irq, err); 643 return err; 644 } 645 646 err = gpiochip_irqchip_add_nested(chip, 647 &mcp23s08_irq_chip, 648 0, 649 handle_simple_irq, 650 IRQ_TYPE_NONE); 651 if (err) { 652 dev_err(chip->parent, 653 "could not connect irqchip to gpiochip: %d\n", err); 654 return err; 655 } 656 657 gpiochip_set_nested_irqchip(chip, 658 &mcp23s08_irq_chip, 659 mcp->irq); 660 661 return 0; 662 } 663 664 /*----------------------------------------------------------------------*/ 665 666 #ifdef CONFIG_DEBUG_FS 667 668 #include <linux/seq_file.h> 669 670 /* 671 * This compares the chip's registers with the register 672 * cache and corrects any incorrectly set register. This 673 * can be used to fix state for MCP23xxx, that temporary 674 * lost its power supply. 675 */ 676 #define MCP23S08_CONFIG_REGS 8 677 static int __check_mcp23s08_reg_cache(struct mcp23s08 *mcp) 678 { 679 int cached[MCP23S08_CONFIG_REGS]; 680 int err = 0, i; 681 682 /* read cached config registers */ 683 for (i = 0; i < MCP23S08_CONFIG_REGS; i++) { 684 err = mcp_read(mcp, i, &cached[i]); 685 if (err) 686 goto out; 687 } 688 689 regcache_cache_bypass(mcp->regmap, true); 690 691 for (i = 0; i < MCP23S08_CONFIG_REGS; i++) { 692 int uncached; 693 err = mcp_read(mcp, i, &uncached); 694 if (err) 695 goto out; 696 697 if (uncached != cached[i]) { 698 dev_err(mcp->dev, "restoring reg 0x%02x from 0x%04x to 0x%04x (power-loss?)\n", 699 i, uncached, cached[i]); 700 mcp_write(mcp, i, cached[i]); 701 } 702 } 703 704 out: 705 if (err) 706 dev_err(mcp->dev, "read error: reg=%02x, err=%d", i, err); 707 regcache_cache_bypass(mcp->regmap, false); 708 return err; 709 } 710 711 /* 712 * This shows more info than the generic gpio dump code: 713 * pullups, deglitching, open drain drive. 714 */ 715 static void mcp23s08_dbg_show(struct seq_file *s, struct gpio_chip *chip) 716 { 717 struct mcp23s08 *mcp; 718 char bank; 719 int t; 720 unsigned mask; 721 int iodir, gpio, gppu; 722 723 mcp = gpiochip_get_data(chip); 724 725 /* NOTE: we only handle one bank for now ... */ 726 bank = '0' + ((mcp->addr >> 1) & 0x7); 727 728 mutex_lock(&mcp->lock); 729 730 t = __check_mcp23s08_reg_cache(mcp); 731 if (t) { 732 seq_printf(s, " I/O Error\n"); 733 goto done; 734 } 735 t = mcp_read(mcp, MCP_IODIR, &iodir); 736 if (t) { 737 seq_printf(s, " I/O Error\n"); 738 goto done; 739 } 740 t = mcp_read(mcp, MCP_GPIO, &gpio); 741 if (t) { 742 seq_printf(s, " I/O Error\n"); 743 goto done; 744 } 745 t = mcp_read(mcp, MCP_GPPU, &gppu); 746 if (t) { 747 seq_printf(s, " I/O Error\n"); 748 goto done; 749 } 750 751 for (t = 0, mask = BIT(0); t < chip->ngpio; t++, mask <<= 1) { 752 const char *label; 753 754 label = gpiochip_is_requested(chip, t); 755 if (!label) 756 continue; 757 758 seq_printf(s, " gpio-%-3d P%c.%d (%-12s) %s %s %s", 759 chip->base + t, bank, t, label, 760 (iodir & mask) ? "in " : "out", 761 (gpio & mask) ? "hi" : "lo", 762 (gppu & mask) ? "up" : " "); 763 /* NOTE: ignoring the irq-related registers */ 764 seq_puts(s, "\n"); 765 } 766 done: 767 mutex_unlock(&mcp->lock); 768 } 769 770 #else 771 #define mcp23s08_dbg_show NULL 772 #endif 773 774 /*----------------------------------------------------------------------*/ 775 776 static int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev, 777 void *data, unsigned addr, unsigned type, 778 unsigned int base, int cs) 779 { 780 int status, ret; 781 bool mirror = false; 782 783 mutex_init(&mcp->lock); 784 785 mcp->dev = dev; 786 mcp->addr = addr; 787 mcp->irq_active_high = false; 788 789 mcp->chip.direction_input = mcp23s08_direction_input; 790 mcp->chip.get = mcp23s08_get; 791 mcp->chip.direction_output = mcp23s08_direction_output; 792 mcp->chip.set = mcp23s08_set; 793 mcp->chip.dbg_show = mcp23s08_dbg_show; 794 #ifdef CONFIG_OF_GPIO 795 mcp->chip.of_gpio_n_cells = 2; 796 mcp->chip.of_node = dev->of_node; 797 #endif 798 799 switch (type) { 800 #ifdef CONFIG_SPI_MASTER 801 case MCP_TYPE_S08: 802 mcp->regmap = devm_regmap_init(dev, &mcp23sxx_spi_regmap, mcp, 803 &mcp23x08_regmap); 804 mcp->reg_shift = 0; 805 mcp->chip.ngpio = 8; 806 mcp->chip.label = "mcp23s08"; 807 break; 808 809 case MCP_TYPE_S17: 810 mcp->regmap = devm_regmap_init(dev, &mcp23sxx_spi_regmap, mcp, 811 &mcp23x17_regmap); 812 mcp->reg_shift = 1; 813 mcp->chip.ngpio = 16; 814 mcp->chip.label = "mcp23s17"; 815 break; 816 817 case MCP_TYPE_S18: 818 mcp->regmap = devm_regmap_init(dev, &mcp23sxx_spi_regmap, mcp, 819 &mcp23x17_regmap); 820 mcp->reg_shift = 1; 821 mcp->chip.ngpio = 16; 822 mcp->chip.label = "mcp23s18"; 823 break; 824 #endif /* CONFIG_SPI_MASTER */ 825 826 #if IS_ENABLED(CONFIG_I2C) 827 case MCP_TYPE_008: 828 mcp->regmap = devm_regmap_init_i2c(data, &mcp23x08_regmap); 829 mcp->reg_shift = 0; 830 mcp->chip.ngpio = 8; 831 mcp->chip.label = "mcp23008"; 832 break; 833 834 case MCP_TYPE_017: 835 mcp->regmap = devm_regmap_init_i2c(data, &mcp23x17_regmap); 836 mcp->reg_shift = 1; 837 mcp->chip.ngpio = 16; 838 mcp->chip.label = "mcp23017"; 839 break; 840 #endif /* CONFIG_I2C */ 841 842 default: 843 dev_err(dev, "invalid device type (%d)\n", type); 844 return -EINVAL; 845 } 846 847 if (IS_ERR(mcp->regmap)) 848 return PTR_ERR(mcp->regmap); 849 850 mcp->chip.base = base; 851 mcp->chip.can_sleep = true; 852 mcp->chip.parent = dev; 853 mcp->chip.owner = THIS_MODULE; 854 855 /* verify MCP_IOCON.SEQOP = 0, so sequential reads work, 856 * and MCP_IOCON.HAEN = 1, so we work with all chips. 857 */ 858 859 ret = mcp_read(mcp, MCP_IOCON, &status); 860 if (ret < 0) 861 goto fail; 862 863 mcp->irq_controller = 864 device_property_read_bool(dev, "interrupt-controller"); 865 if (mcp->irq && mcp->irq_controller) { 866 mcp->irq_active_high = 867 device_property_read_bool(dev, 868 "microchip,irq-active-high"); 869 870 mirror = device_property_read_bool(dev, "microchip,irq-mirror"); 871 } 872 873 if ((status & IOCON_SEQOP) || !(status & IOCON_HAEN) || mirror || 874 mcp->irq_active_high) { 875 /* mcp23s17 has IOCON twice, make sure they are in sync */ 876 status &= ~(IOCON_SEQOP | (IOCON_SEQOP << 8)); 877 status |= IOCON_HAEN | (IOCON_HAEN << 8); 878 if (mcp->irq_active_high) 879 status |= IOCON_INTPOL | (IOCON_INTPOL << 8); 880 else 881 status &= ~(IOCON_INTPOL | (IOCON_INTPOL << 8)); 882 883 if (mirror) 884 status |= IOCON_MIRROR | (IOCON_MIRROR << 8); 885 886 if (type == MCP_TYPE_S18) 887 status |= IOCON_INTCC | (IOCON_INTCC << 8); 888 889 ret = mcp_write(mcp, MCP_IOCON, status); 890 if (ret < 0) 891 goto fail; 892 } 893 894 ret = devm_gpiochip_add_data(dev, &mcp->chip, mcp); 895 if (ret < 0) 896 goto fail; 897 898 if (mcp->irq && mcp->irq_controller) { 899 ret = mcp23s08_irq_setup(mcp); 900 if (ret) 901 goto fail; 902 } 903 904 mcp->pinctrl_desc.name = "mcp23xxx-pinctrl"; 905 mcp->pinctrl_desc.pctlops = &mcp_pinctrl_ops; 906 mcp->pinctrl_desc.confops = &mcp_pinconf_ops; 907 mcp->pinctrl_desc.npins = mcp->chip.ngpio; 908 if (mcp->pinctrl_desc.npins == 8) 909 mcp->pinctrl_desc.pins = mcp23x08_pins; 910 else if (mcp->pinctrl_desc.npins == 16) 911 mcp->pinctrl_desc.pins = mcp23x17_pins; 912 mcp->pinctrl_desc.owner = THIS_MODULE; 913 914 mcp->pctldev = devm_pinctrl_register(dev, &mcp->pinctrl_desc, mcp); 915 if (IS_ERR(mcp->pctldev)) { 916 ret = PTR_ERR(mcp->pctldev); 917 goto fail; 918 } 919 920 fail: 921 if (ret < 0) 922 dev_dbg(dev, "can't setup chip %d, --> %d\n", addr, ret); 923 return ret; 924 } 925 926 /*----------------------------------------------------------------------*/ 927 928 #ifdef CONFIG_OF 929 #ifdef CONFIG_SPI_MASTER 930 static const struct of_device_id mcp23s08_spi_of_match[] = { 931 { 932 .compatible = "microchip,mcp23s08", 933 .data = (void *) MCP_TYPE_S08, 934 }, 935 { 936 .compatible = "microchip,mcp23s17", 937 .data = (void *) MCP_TYPE_S17, 938 }, 939 { 940 .compatible = "microchip,mcp23s18", 941 .data = (void *) MCP_TYPE_S18, 942 }, 943 /* NOTE: The use of the mcp prefix is deprecated and will be removed. */ 944 { 945 .compatible = "mcp,mcp23s08", 946 .data = (void *) MCP_TYPE_S08, 947 }, 948 { 949 .compatible = "mcp,mcp23s17", 950 .data = (void *) MCP_TYPE_S17, 951 }, 952 { }, 953 }; 954 MODULE_DEVICE_TABLE(of, mcp23s08_spi_of_match); 955 #endif 956 957 #if IS_ENABLED(CONFIG_I2C) 958 static const struct of_device_id mcp23s08_i2c_of_match[] = { 959 { 960 .compatible = "microchip,mcp23008", 961 .data = (void *) MCP_TYPE_008, 962 }, 963 { 964 .compatible = "microchip,mcp23017", 965 .data = (void *) MCP_TYPE_017, 966 }, 967 /* NOTE: The use of the mcp prefix is deprecated and will be removed. */ 968 { 969 .compatible = "mcp,mcp23008", 970 .data = (void *) MCP_TYPE_008, 971 }, 972 { 973 .compatible = "mcp,mcp23017", 974 .data = (void *) MCP_TYPE_017, 975 }, 976 { }, 977 }; 978 MODULE_DEVICE_TABLE(of, mcp23s08_i2c_of_match); 979 #endif 980 #endif /* CONFIG_OF */ 981 982 983 #if IS_ENABLED(CONFIG_I2C) 984 985 static int mcp230xx_probe(struct i2c_client *client, 986 const struct i2c_device_id *id) 987 { 988 struct mcp23s08_platform_data *pdata, local_pdata; 989 struct mcp23s08 *mcp; 990 int status; 991 992 pdata = dev_get_platdata(&client->dev); 993 if (!pdata) { 994 pdata = &local_pdata; 995 pdata->base = -1; 996 } 997 998 mcp = devm_kzalloc(&client->dev, sizeof(*mcp), GFP_KERNEL); 999 if (!mcp) 1000 return -ENOMEM; 1001 1002 mcp->irq = client->irq; 1003 status = mcp23s08_probe_one(mcp, &client->dev, client, client->addr, 1004 id->driver_data, pdata->base, 0); 1005 if (status) 1006 return status; 1007 1008 i2c_set_clientdata(client, mcp); 1009 1010 return 0; 1011 } 1012 1013 static const struct i2c_device_id mcp230xx_id[] = { 1014 { "mcp23008", MCP_TYPE_008 }, 1015 { "mcp23017", MCP_TYPE_017 }, 1016 { }, 1017 }; 1018 MODULE_DEVICE_TABLE(i2c, mcp230xx_id); 1019 1020 static struct i2c_driver mcp230xx_driver = { 1021 .driver = { 1022 .name = "mcp230xx", 1023 .of_match_table = of_match_ptr(mcp23s08_i2c_of_match), 1024 }, 1025 .probe = mcp230xx_probe, 1026 .id_table = mcp230xx_id, 1027 }; 1028 1029 static int __init mcp23s08_i2c_init(void) 1030 { 1031 return i2c_add_driver(&mcp230xx_driver); 1032 } 1033 1034 static void mcp23s08_i2c_exit(void) 1035 { 1036 i2c_del_driver(&mcp230xx_driver); 1037 } 1038 1039 #else 1040 1041 static int __init mcp23s08_i2c_init(void) { return 0; } 1042 static void mcp23s08_i2c_exit(void) { } 1043 1044 #endif /* CONFIG_I2C */ 1045 1046 /*----------------------------------------------------------------------*/ 1047 1048 #ifdef CONFIG_SPI_MASTER 1049 1050 static int mcp23s08_probe(struct spi_device *spi) 1051 { 1052 struct mcp23s08_platform_data *pdata, local_pdata; 1053 unsigned addr; 1054 int chips = 0; 1055 struct mcp23s08_driver_data *data; 1056 int status, type; 1057 unsigned ngpio = 0; 1058 const struct of_device_id *match; 1059 1060 match = of_match_device(of_match_ptr(mcp23s08_spi_of_match), &spi->dev); 1061 if (match) 1062 type = (int)(uintptr_t)match->data; 1063 else 1064 type = spi_get_device_id(spi)->driver_data; 1065 1066 pdata = dev_get_platdata(&spi->dev); 1067 if (!pdata) { 1068 pdata = &local_pdata; 1069 pdata->base = -1; 1070 1071 status = device_property_read_u32(&spi->dev, 1072 "microchip,spi-present-mask", &pdata->spi_present_mask); 1073 if (status) { 1074 status = device_property_read_u32(&spi->dev, 1075 "mcp,spi-present-mask", 1076 &pdata->spi_present_mask); 1077 1078 if (status) { 1079 dev_err(&spi->dev, "missing spi-present-mask"); 1080 return -ENODEV; 1081 } 1082 } 1083 } 1084 1085 if (!pdata->spi_present_mask || pdata->spi_present_mask > 0xff) { 1086 dev_err(&spi->dev, "invalid spi-present-mask"); 1087 return -ENODEV; 1088 } 1089 1090 for (addr = 0; addr < MCP_MAX_DEV_PER_CS; addr++) { 1091 if (pdata->spi_present_mask & BIT(addr)) 1092 chips++; 1093 } 1094 1095 if (!chips) 1096 return -ENODEV; 1097 1098 data = devm_kzalloc(&spi->dev, 1099 sizeof(*data) + chips * sizeof(struct mcp23s08), 1100 GFP_KERNEL); 1101 if (!data) 1102 return -ENOMEM; 1103 1104 spi_set_drvdata(spi, data); 1105 1106 for (addr = 0; addr < MCP_MAX_DEV_PER_CS; addr++) { 1107 if (!(pdata->spi_present_mask & BIT(addr))) 1108 continue; 1109 chips--; 1110 data->mcp[addr] = &data->chip[chips]; 1111 data->mcp[addr]->irq = spi->irq; 1112 status = mcp23s08_probe_one(data->mcp[addr], &spi->dev, spi, 1113 0x40 | (addr << 1), type, 1114 pdata->base, addr); 1115 if (status < 0) 1116 return status; 1117 1118 if (pdata->base != -1) 1119 pdata->base += data->mcp[addr]->chip.ngpio; 1120 ngpio += data->mcp[addr]->chip.ngpio; 1121 } 1122 data->ngpio = ngpio; 1123 1124 return 0; 1125 } 1126 1127 static const struct spi_device_id mcp23s08_ids[] = { 1128 { "mcp23s08", MCP_TYPE_S08 }, 1129 { "mcp23s17", MCP_TYPE_S17 }, 1130 { "mcp23s18", MCP_TYPE_S18 }, 1131 { }, 1132 }; 1133 MODULE_DEVICE_TABLE(spi, mcp23s08_ids); 1134 1135 static struct spi_driver mcp23s08_driver = { 1136 .probe = mcp23s08_probe, 1137 .id_table = mcp23s08_ids, 1138 .driver = { 1139 .name = "mcp23s08", 1140 .of_match_table = of_match_ptr(mcp23s08_spi_of_match), 1141 }, 1142 }; 1143 1144 static int __init mcp23s08_spi_init(void) 1145 { 1146 return spi_register_driver(&mcp23s08_driver); 1147 } 1148 1149 static void mcp23s08_spi_exit(void) 1150 { 1151 spi_unregister_driver(&mcp23s08_driver); 1152 } 1153 1154 #else 1155 1156 static int __init mcp23s08_spi_init(void) { return 0; } 1157 static void mcp23s08_spi_exit(void) { } 1158 1159 #endif /* CONFIG_SPI_MASTER */ 1160 1161 /*----------------------------------------------------------------------*/ 1162 1163 static int __init mcp23s08_init(void) 1164 { 1165 int ret; 1166 1167 ret = mcp23s08_spi_init(); 1168 if (ret) 1169 goto spi_fail; 1170 1171 ret = mcp23s08_i2c_init(); 1172 if (ret) 1173 goto i2c_fail; 1174 1175 return 0; 1176 1177 i2c_fail: 1178 mcp23s08_spi_exit(); 1179 spi_fail: 1180 return ret; 1181 } 1182 /* register after spi/i2c postcore initcall and before 1183 * subsys initcalls that may rely on these GPIOs 1184 */ 1185 subsys_initcall(mcp23s08_init); 1186 1187 static void __exit mcp23s08_exit(void) 1188 { 1189 mcp23s08_spi_exit(); 1190 mcp23s08_i2c_exit(); 1191 } 1192 module_exit(mcp23s08_exit); 1193 1194 MODULE_LICENSE("GPL"); 1195