1 // SPDX-License-Identifier: GPL-2.0-only 2 /* MCP23S08 SPI/I2C GPIO driver */ 3 4 #include <linux/kernel.h> 5 #include <linux/device.h> 6 #include <linux/mutex.h> 7 #include <linux/module.h> 8 #include <linux/gpio/driver.h> 9 #include <linux/i2c.h> 10 #include <linux/spi/spi.h> 11 #include <linux/spi/mcp23s08.h> 12 #include <linux/slab.h> 13 #include <asm/byteorder.h> 14 #include <linux/interrupt.h> 15 #include <linux/of_device.h> 16 #include <linux/regmap.h> 17 #include <linux/pinctrl/pinctrl.h> 18 #include <linux/pinctrl/pinconf.h> 19 #include <linux/pinctrl/pinconf-generic.h> 20 21 /* 22 * MCP types supported by driver 23 */ 24 #define MCP_TYPE_S08 0 25 #define MCP_TYPE_S17 1 26 #define MCP_TYPE_008 2 27 #define MCP_TYPE_017 3 28 #define MCP_TYPE_S18 4 29 #define MCP_TYPE_018 5 30 31 #define MCP_MAX_DEV_PER_CS 8 32 33 /* Registers are all 8 bits wide. 34 * 35 * The mcp23s17 has twice as many bits, and can be configured to work 36 * with either 16 bit registers or with two adjacent 8 bit banks. 37 */ 38 #define MCP_IODIR 0x00 /* init/reset: all ones */ 39 #define MCP_IPOL 0x01 40 #define MCP_GPINTEN 0x02 41 #define MCP_DEFVAL 0x03 42 #define MCP_INTCON 0x04 43 #define MCP_IOCON 0x05 44 # define IOCON_MIRROR (1 << 6) 45 # define IOCON_SEQOP (1 << 5) 46 # define IOCON_HAEN (1 << 3) 47 # define IOCON_ODR (1 << 2) 48 # define IOCON_INTPOL (1 << 1) 49 # define IOCON_INTCC (1) 50 #define MCP_GPPU 0x06 51 #define MCP_INTF 0x07 52 #define MCP_INTCAP 0x08 53 #define MCP_GPIO 0x09 54 #define MCP_OLAT 0x0a 55 56 struct mcp23s08; 57 58 struct mcp23s08 { 59 u8 addr; 60 bool irq_active_high; 61 bool reg_shift; 62 63 u16 irq_rise; 64 u16 irq_fall; 65 int irq; 66 bool irq_controller; 67 int cached_gpio; 68 /* lock protects regmap access with bypass/cache flags */ 69 struct mutex lock; 70 71 struct gpio_chip chip; 72 struct irq_chip irq_chip; 73 74 struct regmap *regmap; 75 struct device *dev; 76 77 struct pinctrl_dev *pctldev; 78 struct pinctrl_desc pinctrl_desc; 79 }; 80 81 static const struct reg_default mcp23x08_defaults[] = { 82 {.reg = MCP_IODIR, .def = 0xff}, 83 {.reg = MCP_IPOL, .def = 0x00}, 84 {.reg = MCP_GPINTEN, .def = 0x00}, 85 {.reg = MCP_DEFVAL, .def = 0x00}, 86 {.reg = MCP_INTCON, .def = 0x00}, 87 {.reg = MCP_IOCON, .def = 0x00}, 88 {.reg = MCP_GPPU, .def = 0x00}, 89 {.reg = MCP_OLAT, .def = 0x00}, 90 }; 91 92 static const struct regmap_range mcp23x08_volatile_range = { 93 .range_min = MCP_INTF, 94 .range_max = MCP_GPIO, 95 }; 96 97 static const struct regmap_access_table mcp23x08_volatile_table = { 98 .yes_ranges = &mcp23x08_volatile_range, 99 .n_yes_ranges = 1, 100 }; 101 102 static const struct regmap_range mcp23x08_precious_range = { 103 .range_min = MCP_GPIO, 104 .range_max = MCP_GPIO, 105 }; 106 107 static const struct regmap_access_table mcp23x08_precious_table = { 108 .yes_ranges = &mcp23x08_precious_range, 109 .n_yes_ranges = 1, 110 }; 111 112 static const struct regmap_config mcp23x08_regmap = { 113 .reg_bits = 8, 114 .val_bits = 8, 115 116 .reg_stride = 1, 117 .volatile_table = &mcp23x08_volatile_table, 118 .precious_table = &mcp23x08_precious_table, 119 .reg_defaults = mcp23x08_defaults, 120 .num_reg_defaults = ARRAY_SIZE(mcp23x08_defaults), 121 .cache_type = REGCACHE_FLAT, 122 .max_register = MCP_OLAT, 123 }; 124 125 static const struct reg_default mcp23x16_defaults[] = { 126 {.reg = MCP_IODIR << 1, .def = 0xffff}, 127 {.reg = MCP_IPOL << 1, .def = 0x0000}, 128 {.reg = MCP_GPINTEN << 1, .def = 0x0000}, 129 {.reg = MCP_DEFVAL << 1, .def = 0x0000}, 130 {.reg = MCP_INTCON << 1, .def = 0x0000}, 131 {.reg = MCP_IOCON << 1, .def = 0x0000}, 132 {.reg = MCP_GPPU << 1, .def = 0x0000}, 133 {.reg = MCP_OLAT << 1, .def = 0x0000}, 134 }; 135 136 static const struct regmap_range mcp23x16_volatile_range = { 137 .range_min = MCP_INTF << 1, 138 .range_max = MCP_GPIO << 1, 139 }; 140 141 static const struct regmap_access_table mcp23x16_volatile_table = { 142 .yes_ranges = &mcp23x16_volatile_range, 143 .n_yes_ranges = 1, 144 }; 145 146 static const struct regmap_range mcp23x16_precious_range = { 147 .range_min = MCP_GPIO << 1, 148 .range_max = MCP_GPIO << 1, 149 }; 150 151 static const struct regmap_access_table mcp23x16_precious_table = { 152 .yes_ranges = &mcp23x16_precious_range, 153 .n_yes_ranges = 1, 154 }; 155 156 static const struct regmap_config mcp23x17_regmap = { 157 .reg_bits = 8, 158 .val_bits = 16, 159 160 .reg_stride = 2, 161 .max_register = MCP_OLAT << 1, 162 .volatile_table = &mcp23x16_volatile_table, 163 .precious_table = &mcp23x16_precious_table, 164 .reg_defaults = mcp23x16_defaults, 165 .num_reg_defaults = ARRAY_SIZE(mcp23x16_defaults), 166 .cache_type = REGCACHE_FLAT, 167 .val_format_endian = REGMAP_ENDIAN_LITTLE, 168 }; 169 170 static int mcp_read(struct mcp23s08 *mcp, unsigned int reg, unsigned int *val) 171 { 172 return regmap_read(mcp->regmap, reg << mcp->reg_shift, val); 173 } 174 175 static int mcp_write(struct mcp23s08 *mcp, unsigned int reg, unsigned int val) 176 { 177 return regmap_write(mcp->regmap, reg << mcp->reg_shift, val); 178 } 179 180 static int mcp_set_mask(struct mcp23s08 *mcp, unsigned int reg, 181 unsigned int mask, bool enabled) 182 { 183 u16 val = enabled ? 0xffff : 0x0000; 184 return regmap_update_bits(mcp->regmap, reg << mcp->reg_shift, 185 mask, val); 186 } 187 188 static int mcp_set_bit(struct mcp23s08 *mcp, unsigned int reg, 189 unsigned int pin, bool enabled) 190 { 191 u16 mask = BIT(pin); 192 return mcp_set_mask(mcp, reg, mask, enabled); 193 } 194 195 static const struct pinctrl_pin_desc mcp23x08_pins[] = { 196 PINCTRL_PIN(0, "gpio0"), 197 PINCTRL_PIN(1, "gpio1"), 198 PINCTRL_PIN(2, "gpio2"), 199 PINCTRL_PIN(3, "gpio3"), 200 PINCTRL_PIN(4, "gpio4"), 201 PINCTRL_PIN(5, "gpio5"), 202 PINCTRL_PIN(6, "gpio6"), 203 PINCTRL_PIN(7, "gpio7"), 204 }; 205 206 static const struct pinctrl_pin_desc mcp23x17_pins[] = { 207 PINCTRL_PIN(0, "gpio0"), 208 PINCTRL_PIN(1, "gpio1"), 209 PINCTRL_PIN(2, "gpio2"), 210 PINCTRL_PIN(3, "gpio3"), 211 PINCTRL_PIN(4, "gpio4"), 212 PINCTRL_PIN(5, "gpio5"), 213 PINCTRL_PIN(6, "gpio6"), 214 PINCTRL_PIN(7, "gpio7"), 215 PINCTRL_PIN(8, "gpio8"), 216 PINCTRL_PIN(9, "gpio9"), 217 PINCTRL_PIN(10, "gpio10"), 218 PINCTRL_PIN(11, "gpio11"), 219 PINCTRL_PIN(12, "gpio12"), 220 PINCTRL_PIN(13, "gpio13"), 221 PINCTRL_PIN(14, "gpio14"), 222 PINCTRL_PIN(15, "gpio15"), 223 }; 224 225 static int mcp_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) 226 { 227 return 0; 228 } 229 230 static const char *mcp_pinctrl_get_group_name(struct pinctrl_dev *pctldev, 231 unsigned int group) 232 { 233 return NULL; 234 } 235 236 static int mcp_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, 237 unsigned int group, 238 const unsigned int **pins, 239 unsigned int *num_pins) 240 { 241 return -ENOTSUPP; 242 } 243 244 static const struct pinctrl_ops mcp_pinctrl_ops = { 245 .get_groups_count = mcp_pinctrl_get_groups_count, 246 .get_group_name = mcp_pinctrl_get_group_name, 247 .get_group_pins = mcp_pinctrl_get_group_pins, 248 #ifdef CONFIG_OF 249 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, 250 .dt_free_map = pinconf_generic_dt_free_map, 251 #endif 252 }; 253 254 static int mcp_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, 255 unsigned long *config) 256 { 257 struct mcp23s08 *mcp = pinctrl_dev_get_drvdata(pctldev); 258 enum pin_config_param param = pinconf_to_config_param(*config); 259 unsigned int data, status; 260 int ret; 261 262 switch (param) { 263 case PIN_CONFIG_BIAS_PULL_UP: 264 ret = mcp_read(mcp, MCP_GPPU, &data); 265 if (ret < 0) 266 return ret; 267 status = (data & BIT(pin)) ? 1 : 0; 268 break; 269 default: 270 return -ENOTSUPP; 271 } 272 273 *config = 0; 274 275 return status ? 0 : -EINVAL; 276 } 277 278 static int mcp_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 279 unsigned long *configs, unsigned int num_configs) 280 { 281 struct mcp23s08 *mcp = pinctrl_dev_get_drvdata(pctldev); 282 enum pin_config_param param; 283 u32 arg; 284 int ret = 0; 285 int i; 286 287 for (i = 0; i < num_configs; i++) { 288 param = pinconf_to_config_param(configs[i]); 289 arg = pinconf_to_config_argument(configs[i]); 290 291 switch (param) { 292 case PIN_CONFIG_BIAS_PULL_UP: 293 ret = mcp_set_bit(mcp, MCP_GPPU, pin, arg); 294 break; 295 default: 296 dev_dbg(mcp->dev, "Invalid config param %04x\n", param); 297 return -ENOTSUPP; 298 } 299 } 300 301 return ret; 302 } 303 304 static const struct pinconf_ops mcp_pinconf_ops = { 305 .pin_config_get = mcp_pinconf_get, 306 .pin_config_set = mcp_pinconf_set, 307 .is_generic = true, 308 }; 309 310 /*----------------------------------------------------------------------*/ 311 312 #ifdef CONFIG_SPI_MASTER 313 314 static int mcp23sxx_spi_write(void *context, const void *data, size_t count) 315 { 316 struct mcp23s08 *mcp = context; 317 struct spi_device *spi = to_spi_device(mcp->dev); 318 struct spi_message m; 319 struct spi_transfer t[2] = { { .tx_buf = &mcp->addr, .len = 1, }, 320 { .tx_buf = data, .len = count, }, }; 321 322 spi_message_init(&m); 323 spi_message_add_tail(&t[0], &m); 324 spi_message_add_tail(&t[1], &m); 325 326 return spi_sync(spi, &m); 327 } 328 329 static int mcp23sxx_spi_gather_write(void *context, 330 const void *reg, size_t reg_size, 331 const void *val, size_t val_size) 332 { 333 struct mcp23s08 *mcp = context; 334 struct spi_device *spi = to_spi_device(mcp->dev); 335 struct spi_message m; 336 struct spi_transfer t[3] = { { .tx_buf = &mcp->addr, .len = 1, }, 337 { .tx_buf = reg, .len = reg_size, }, 338 { .tx_buf = val, .len = val_size, }, }; 339 340 spi_message_init(&m); 341 spi_message_add_tail(&t[0], &m); 342 spi_message_add_tail(&t[1], &m); 343 spi_message_add_tail(&t[2], &m); 344 345 return spi_sync(spi, &m); 346 } 347 348 static int mcp23sxx_spi_read(void *context, const void *reg, size_t reg_size, 349 void *val, size_t val_size) 350 { 351 struct mcp23s08 *mcp = context; 352 struct spi_device *spi = to_spi_device(mcp->dev); 353 u8 tx[2]; 354 355 if (reg_size != 1) 356 return -EINVAL; 357 358 tx[0] = mcp->addr | 0x01; 359 tx[1] = *((u8 *) reg); 360 361 return spi_write_then_read(spi, tx, sizeof(tx), val, val_size); 362 } 363 364 static const struct regmap_bus mcp23sxx_spi_regmap = { 365 .write = mcp23sxx_spi_write, 366 .gather_write = mcp23sxx_spi_gather_write, 367 .read = mcp23sxx_spi_read, 368 }; 369 370 #endif /* CONFIG_SPI_MASTER */ 371 372 /*----------------------------------------------------------------------*/ 373 374 /* A given spi_device can represent up to eight mcp23sxx chips 375 * sharing the same chipselect but using different addresses 376 * (e.g. chips #0 and #3 might be populated, but not #1 or $2). 377 * Driver data holds all the per-chip data. 378 */ 379 struct mcp23s08_driver_data { 380 unsigned ngpio; 381 struct mcp23s08 *mcp[8]; 382 struct mcp23s08 chip[]; 383 }; 384 385 386 static int mcp23s08_direction_input(struct gpio_chip *chip, unsigned offset) 387 { 388 struct mcp23s08 *mcp = gpiochip_get_data(chip); 389 int status; 390 391 mutex_lock(&mcp->lock); 392 status = mcp_set_bit(mcp, MCP_IODIR, offset, true); 393 mutex_unlock(&mcp->lock); 394 395 return status; 396 } 397 398 static int mcp23s08_get(struct gpio_chip *chip, unsigned offset) 399 { 400 struct mcp23s08 *mcp = gpiochip_get_data(chip); 401 int status, ret; 402 403 mutex_lock(&mcp->lock); 404 405 /* REVISIT reading this clears any IRQ ... */ 406 ret = mcp_read(mcp, MCP_GPIO, &status); 407 if (ret < 0) 408 status = 0; 409 else { 410 mcp->cached_gpio = status; 411 status = !!(status & (1 << offset)); 412 } 413 414 mutex_unlock(&mcp->lock); 415 return status; 416 } 417 418 static int __mcp23s08_set(struct mcp23s08 *mcp, unsigned mask, bool value) 419 { 420 return mcp_set_mask(mcp, MCP_OLAT, mask, value); 421 } 422 423 static void mcp23s08_set(struct gpio_chip *chip, unsigned offset, int value) 424 { 425 struct mcp23s08 *mcp = gpiochip_get_data(chip); 426 unsigned mask = BIT(offset); 427 428 mutex_lock(&mcp->lock); 429 __mcp23s08_set(mcp, mask, !!value); 430 mutex_unlock(&mcp->lock); 431 } 432 433 static int 434 mcp23s08_direction_output(struct gpio_chip *chip, unsigned offset, int value) 435 { 436 struct mcp23s08 *mcp = gpiochip_get_data(chip); 437 unsigned mask = BIT(offset); 438 int status; 439 440 mutex_lock(&mcp->lock); 441 status = __mcp23s08_set(mcp, mask, value); 442 if (status == 0) { 443 status = mcp_set_mask(mcp, MCP_IODIR, mask, false); 444 } 445 mutex_unlock(&mcp->lock); 446 return status; 447 } 448 449 /*----------------------------------------------------------------------*/ 450 static irqreturn_t mcp23s08_irq(int irq, void *data) 451 { 452 struct mcp23s08 *mcp = data; 453 int intcap, intcon, intf, i, gpio, gpio_orig, intcap_mask, defval; 454 unsigned int child_irq; 455 bool intf_set, intcap_changed, gpio_bit_changed, 456 defval_changed, gpio_set; 457 458 mutex_lock(&mcp->lock); 459 if (mcp_read(mcp, MCP_INTF, &intf)) 460 goto unlock; 461 462 if (mcp_read(mcp, MCP_INTCAP, &intcap)) 463 goto unlock; 464 465 if (mcp_read(mcp, MCP_INTCON, &intcon)) 466 goto unlock; 467 468 if (mcp_read(mcp, MCP_DEFVAL, &defval)) 469 goto unlock; 470 471 /* This clears the interrupt(configurable on S18) */ 472 if (mcp_read(mcp, MCP_GPIO, &gpio)) 473 goto unlock; 474 475 gpio_orig = mcp->cached_gpio; 476 mcp->cached_gpio = gpio; 477 mutex_unlock(&mcp->lock); 478 479 if (intf == 0) { 480 /* There is no interrupt pending */ 481 return IRQ_HANDLED; 482 } 483 484 dev_dbg(mcp->chip.parent, 485 "intcap 0x%04X intf 0x%04X gpio_orig 0x%04X gpio 0x%04X\n", 486 intcap, intf, gpio_orig, gpio); 487 488 for (i = 0; i < mcp->chip.ngpio; i++) { 489 /* We must check all of the inputs on the chip, 490 * otherwise we may not notice a change on >=2 pins. 491 * 492 * On at least the mcp23s17, INTCAP is only updated 493 * one byte at a time(INTCAPA and INTCAPB are 494 * not written to at the same time - only on a per-bank 495 * basis). 496 * 497 * INTF only contains the single bit that caused the 498 * interrupt per-bank. On the mcp23s17, there is 499 * INTFA and INTFB. If two pins are changed on the A 500 * side at the same time, INTF will only have one bit 501 * set. If one pin on the A side and one pin on the B 502 * side are changed at the same time, INTF will have 503 * two bits set. Thus, INTF can't be the only check 504 * to see if the input has changed. 505 */ 506 507 intf_set = intf & BIT(i); 508 if (i < 8 && intf_set) 509 intcap_mask = 0x00FF; 510 else if (i >= 8 && intf_set) 511 intcap_mask = 0xFF00; 512 else 513 intcap_mask = 0x00; 514 515 intcap_changed = (intcap_mask & 516 (intcap & BIT(i))) != 517 (intcap_mask & (BIT(i) & gpio_orig)); 518 gpio_set = BIT(i) & gpio; 519 gpio_bit_changed = (BIT(i) & gpio_orig) != 520 (BIT(i) & gpio); 521 defval_changed = (BIT(i) & intcon) && 522 ((BIT(i) & gpio) != 523 (BIT(i) & defval)); 524 525 if (((gpio_bit_changed || intcap_changed) && 526 (BIT(i) & mcp->irq_rise) && gpio_set) || 527 ((gpio_bit_changed || intcap_changed) && 528 (BIT(i) & mcp->irq_fall) && !gpio_set) || 529 defval_changed) { 530 child_irq = irq_find_mapping(mcp->chip.irq.domain, i); 531 handle_nested_irq(child_irq); 532 } 533 } 534 535 return IRQ_HANDLED; 536 537 unlock: 538 mutex_unlock(&mcp->lock); 539 return IRQ_HANDLED; 540 } 541 542 static void mcp23s08_irq_mask(struct irq_data *data) 543 { 544 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 545 struct mcp23s08 *mcp = gpiochip_get_data(gc); 546 unsigned int pos = data->hwirq; 547 548 mcp_set_bit(mcp, MCP_GPINTEN, pos, false); 549 } 550 551 static void mcp23s08_irq_unmask(struct irq_data *data) 552 { 553 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 554 struct mcp23s08 *mcp = gpiochip_get_data(gc); 555 unsigned int pos = data->hwirq; 556 557 mcp_set_bit(mcp, MCP_GPINTEN, pos, true); 558 } 559 560 static int mcp23s08_irq_set_type(struct irq_data *data, unsigned int type) 561 { 562 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 563 struct mcp23s08 *mcp = gpiochip_get_data(gc); 564 unsigned int pos = data->hwirq; 565 int status = 0; 566 567 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) { 568 mcp_set_bit(mcp, MCP_INTCON, pos, false); 569 mcp->irq_rise |= BIT(pos); 570 mcp->irq_fall |= BIT(pos); 571 } else if (type & IRQ_TYPE_EDGE_RISING) { 572 mcp_set_bit(mcp, MCP_INTCON, pos, false); 573 mcp->irq_rise |= BIT(pos); 574 mcp->irq_fall &= ~BIT(pos); 575 } else if (type & IRQ_TYPE_EDGE_FALLING) { 576 mcp_set_bit(mcp, MCP_INTCON, pos, false); 577 mcp->irq_rise &= ~BIT(pos); 578 mcp->irq_fall |= BIT(pos); 579 } else if (type & IRQ_TYPE_LEVEL_HIGH) { 580 mcp_set_bit(mcp, MCP_INTCON, pos, true); 581 mcp_set_bit(mcp, MCP_DEFVAL, pos, false); 582 } else if (type & IRQ_TYPE_LEVEL_LOW) { 583 mcp_set_bit(mcp, MCP_INTCON, pos, true); 584 mcp_set_bit(mcp, MCP_DEFVAL, pos, true); 585 } else 586 return -EINVAL; 587 588 return status; 589 } 590 591 static void mcp23s08_irq_bus_lock(struct irq_data *data) 592 { 593 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 594 struct mcp23s08 *mcp = gpiochip_get_data(gc); 595 596 mutex_lock(&mcp->lock); 597 regcache_cache_only(mcp->regmap, true); 598 } 599 600 static void mcp23s08_irq_bus_unlock(struct irq_data *data) 601 { 602 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 603 struct mcp23s08 *mcp = gpiochip_get_data(gc); 604 605 regcache_cache_only(mcp->regmap, false); 606 regcache_sync(mcp->regmap); 607 608 mutex_unlock(&mcp->lock); 609 } 610 611 static int mcp23s08_irq_setup(struct mcp23s08 *mcp) 612 { 613 struct gpio_chip *chip = &mcp->chip; 614 int err; 615 unsigned long irqflags = IRQF_ONESHOT | IRQF_SHARED; 616 617 if (mcp->irq_active_high) 618 irqflags |= IRQF_TRIGGER_HIGH; 619 else 620 irqflags |= IRQF_TRIGGER_LOW; 621 622 err = devm_request_threaded_irq(chip->parent, mcp->irq, NULL, 623 mcp23s08_irq, 624 irqflags, dev_name(chip->parent), mcp); 625 if (err != 0) { 626 dev_err(chip->parent, "unable to request IRQ#%d: %d\n", 627 mcp->irq, err); 628 return err; 629 } 630 631 return 0; 632 } 633 634 static int mcp23s08_irqchip_setup(struct mcp23s08 *mcp) 635 { 636 struct gpio_chip *chip = &mcp->chip; 637 int err; 638 639 err = gpiochip_irqchip_add_nested(chip, 640 &mcp->irq_chip, 641 0, 642 handle_simple_irq, 643 IRQ_TYPE_NONE); 644 if (err) { 645 dev_err(chip->parent, 646 "could not connect irqchip to gpiochip: %d\n", err); 647 return err; 648 } 649 650 gpiochip_set_nested_irqchip(chip, 651 &mcp->irq_chip, 652 mcp->irq); 653 654 return 0; 655 } 656 657 /*----------------------------------------------------------------------*/ 658 659 static int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev, 660 void *data, unsigned addr, unsigned type, 661 unsigned int base, int cs) 662 { 663 int status, ret; 664 bool mirror = false; 665 bool open_drain = false; 666 struct regmap_config *one_regmap_config = NULL; 667 int raw_chip_address = (addr & ~0x40) >> 1; 668 669 mutex_init(&mcp->lock); 670 671 mcp->dev = dev; 672 mcp->addr = addr; 673 mcp->irq_active_high = false; 674 675 mcp->chip.direction_input = mcp23s08_direction_input; 676 mcp->chip.get = mcp23s08_get; 677 mcp->chip.direction_output = mcp23s08_direction_output; 678 mcp->chip.set = mcp23s08_set; 679 #ifdef CONFIG_OF_GPIO 680 mcp->chip.of_gpio_n_cells = 2; 681 mcp->chip.of_node = dev->of_node; 682 #endif 683 684 switch (type) { 685 #ifdef CONFIG_SPI_MASTER 686 case MCP_TYPE_S08: 687 case MCP_TYPE_S17: 688 switch (type) { 689 case MCP_TYPE_S08: 690 one_regmap_config = 691 devm_kmemdup(dev, &mcp23x08_regmap, 692 sizeof(struct regmap_config), GFP_KERNEL); 693 mcp->reg_shift = 0; 694 mcp->chip.ngpio = 8; 695 mcp->chip.label = devm_kasprintf(dev, GFP_KERNEL, 696 "mcp23s08.%d", raw_chip_address); 697 break; 698 case MCP_TYPE_S17: 699 one_regmap_config = 700 devm_kmemdup(dev, &mcp23x17_regmap, 701 sizeof(struct regmap_config), GFP_KERNEL); 702 mcp->reg_shift = 1; 703 mcp->chip.ngpio = 16; 704 mcp->chip.label = devm_kasprintf(dev, GFP_KERNEL, 705 "mcp23s17.%d", raw_chip_address); 706 break; 707 } 708 if (!one_regmap_config) 709 return -ENOMEM; 710 711 one_regmap_config->name = devm_kasprintf(dev, GFP_KERNEL, "%d", raw_chip_address); 712 mcp->regmap = devm_regmap_init(dev, &mcp23sxx_spi_regmap, mcp, 713 one_regmap_config); 714 break; 715 716 case MCP_TYPE_S18: 717 one_regmap_config = 718 devm_kmemdup(dev, &mcp23x17_regmap, 719 sizeof(struct regmap_config), GFP_KERNEL); 720 if (!one_regmap_config) 721 return -ENOMEM; 722 mcp->regmap = devm_regmap_init(dev, &mcp23sxx_spi_regmap, mcp, 723 one_regmap_config); 724 mcp->reg_shift = 1; 725 mcp->chip.ngpio = 16; 726 mcp->chip.label = "mcp23s18"; 727 break; 728 #endif /* CONFIG_SPI_MASTER */ 729 730 #if IS_ENABLED(CONFIG_I2C) 731 case MCP_TYPE_008: 732 mcp->regmap = devm_regmap_init_i2c(data, &mcp23x08_regmap); 733 mcp->reg_shift = 0; 734 mcp->chip.ngpio = 8; 735 mcp->chip.label = "mcp23008"; 736 break; 737 738 case MCP_TYPE_017: 739 mcp->regmap = devm_regmap_init_i2c(data, &mcp23x17_regmap); 740 mcp->reg_shift = 1; 741 mcp->chip.ngpio = 16; 742 mcp->chip.label = "mcp23017"; 743 break; 744 745 case MCP_TYPE_018: 746 mcp->regmap = devm_regmap_init_i2c(data, &mcp23x17_regmap); 747 mcp->reg_shift = 1; 748 mcp->chip.ngpio = 16; 749 mcp->chip.label = "mcp23018"; 750 break; 751 #endif /* CONFIG_I2C */ 752 753 default: 754 dev_err(dev, "invalid device type (%d)\n", type); 755 return -EINVAL; 756 } 757 758 if (IS_ERR(mcp->regmap)) 759 return PTR_ERR(mcp->regmap); 760 761 mcp->chip.base = base; 762 mcp->chip.can_sleep = true; 763 mcp->chip.parent = dev; 764 mcp->chip.owner = THIS_MODULE; 765 766 /* verify MCP_IOCON.SEQOP = 0, so sequential reads work, 767 * and MCP_IOCON.HAEN = 1, so we work with all chips. 768 */ 769 770 ret = mcp_read(mcp, MCP_IOCON, &status); 771 if (ret < 0) 772 goto fail; 773 774 ret = devm_gpiochip_add_data(dev, &mcp->chip, mcp); 775 if (ret < 0) 776 goto fail; 777 778 mcp->irq_controller = 779 device_property_read_bool(dev, "interrupt-controller"); 780 if (mcp->irq && mcp->irq_controller) { 781 mcp->irq_active_high = 782 device_property_read_bool(dev, 783 "microchip,irq-active-high"); 784 785 mirror = device_property_read_bool(dev, "microchip,irq-mirror"); 786 open_drain = device_property_read_bool(dev, "drive-open-drain"); 787 } 788 789 if ((status & IOCON_SEQOP) || !(status & IOCON_HAEN) || mirror || 790 mcp->irq_active_high || open_drain) { 791 /* mcp23s17 has IOCON twice, make sure they are in sync */ 792 status &= ~(IOCON_SEQOP | (IOCON_SEQOP << 8)); 793 status |= IOCON_HAEN | (IOCON_HAEN << 8); 794 if (mcp->irq_active_high) 795 status |= IOCON_INTPOL | (IOCON_INTPOL << 8); 796 else 797 status &= ~(IOCON_INTPOL | (IOCON_INTPOL << 8)); 798 799 if (mirror) 800 status |= IOCON_MIRROR | (IOCON_MIRROR << 8); 801 802 if (open_drain) 803 status |= IOCON_ODR | (IOCON_ODR << 8); 804 805 if (type == MCP_TYPE_S18 || type == MCP_TYPE_018) 806 status |= IOCON_INTCC | (IOCON_INTCC << 8); 807 808 ret = mcp_write(mcp, MCP_IOCON, status); 809 if (ret < 0) 810 goto fail; 811 } 812 813 if (mcp->irq && mcp->irq_controller) { 814 ret = mcp23s08_irqchip_setup(mcp); 815 if (ret) 816 goto fail; 817 } 818 819 if (one_regmap_config) { 820 mcp->pinctrl_desc.name = devm_kasprintf(dev, GFP_KERNEL, 821 "mcp23xxx-pinctrl.%d", raw_chip_address); 822 if (!mcp->pinctrl_desc.name) 823 return -ENOMEM; 824 } else { 825 mcp->pinctrl_desc.name = "mcp23xxx-pinctrl"; 826 } 827 mcp->pinctrl_desc.pctlops = &mcp_pinctrl_ops; 828 mcp->pinctrl_desc.confops = &mcp_pinconf_ops; 829 mcp->pinctrl_desc.npins = mcp->chip.ngpio; 830 if (mcp->pinctrl_desc.npins == 8) 831 mcp->pinctrl_desc.pins = mcp23x08_pins; 832 else if (mcp->pinctrl_desc.npins == 16) 833 mcp->pinctrl_desc.pins = mcp23x17_pins; 834 mcp->pinctrl_desc.owner = THIS_MODULE; 835 836 mcp->pctldev = devm_pinctrl_register(dev, &mcp->pinctrl_desc, mcp); 837 if (IS_ERR(mcp->pctldev)) { 838 ret = PTR_ERR(mcp->pctldev); 839 goto fail; 840 } 841 842 if (mcp->irq) 843 ret = mcp23s08_irq_setup(mcp); 844 845 fail: 846 if (ret < 0) 847 dev_dbg(dev, "can't setup chip %d, --> %d\n", addr, ret); 848 return ret; 849 } 850 851 /*----------------------------------------------------------------------*/ 852 853 #ifdef CONFIG_OF 854 #ifdef CONFIG_SPI_MASTER 855 static const struct of_device_id mcp23s08_spi_of_match[] = { 856 { 857 .compatible = "microchip,mcp23s08", 858 .data = (void *) MCP_TYPE_S08, 859 }, 860 { 861 .compatible = "microchip,mcp23s17", 862 .data = (void *) MCP_TYPE_S17, 863 }, 864 { 865 .compatible = "microchip,mcp23s18", 866 .data = (void *) MCP_TYPE_S18, 867 }, 868 /* NOTE: The use of the mcp prefix is deprecated and will be removed. */ 869 { 870 .compatible = "mcp,mcp23s08", 871 .data = (void *) MCP_TYPE_S08, 872 }, 873 { 874 .compatible = "mcp,mcp23s17", 875 .data = (void *) MCP_TYPE_S17, 876 }, 877 { }, 878 }; 879 MODULE_DEVICE_TABLE(of, mcp23s08_spi_of_match); 880 #endif 881 882 #if IS_ENABLED(CONFIG_I2C) 883 static const struct of_device_id mcp23s08_i2c_of_match[] = { 884 { 885 .compatible = "microchip,mcp23008", 886 .data = (void *) MCP_TYPE_008, 887 }, 888 { 889 .compatible = "microchip,mcp23017", 890 .data = (void *) MCP_TYPE_017, 891 }, 892 { 893 .compatible = "microchip,mcp23018", 894 .data = (void *) MCP_TYPE_018, 895 }, 896 /* NOTE: The use of the mcp prefix is deprecated and will be removed. */ 897 { 898 .compatible = "mcp,mcp23008", 899 .data = (void *) MCP_TYPE_008, 900 }, 901 { 902 .compatible = "mcp,mcp23017", 903 .data = (void *) MCP_TYPE_017, 904 }, 905 { }, 906 }; 907 MODULE_DEVICE_TABLE(of, mcp23s08_i2c_of_match); 908 #endif 909 #endif /* CONFIG_OF */ 910 911 912 #if IS_ENABLED(CONFIG_I2C) 913 914 static int mcp230xx_probe(struct i2c_client *client, 915 const struct i2c_device_id *id) 916 { 917 struct mcp23s08_platform_data *pdata, local_pdata; 918 struct mcp23s08 *mcp; 919 int status; 920 921 pdata = dev_get_platdata(&client->dev); 922 if (!pdata) { 923 pdata = &local_pdata; 924 pdata->base = -1; 925 } 926 927 mcp = devm_kzalloc(&client->dev, sizeof(*mcp), GFP_KERNEL); 928 if (!mcp) 929 return -ENOMEM; 930 931 mcp->irq = client->irq; 932 mcp->irq_chip.name = dev_name(&client->dev); 933 mcp->irq_chip.irq_mask = mcp23s08_irq_mask; 934 mcp->irq_chip.irq_unmask = mcp23s08_irq_unmask; 935 mcp->irq_chip.irq_set_type = mcp23s08_irq_set_type; 936 mcp->irq_chip.irq_bus_lock = mcp23s08_irq_bus_lock; 937 mcp->irq_chip.irq_bus_sync_unlock = mcp23s08_irq_bus_unlock; 938 939 status = mcp23s08_probe_one(mcp, &client->dev, client, client->addr, 940 id->driver_data, pdata->base, 0); 941 if (status) 942 return status; 943 944 i2c_set_clientdata(client, mcp); 945 946 return 0; 947 } 948 949 static const struct i2c_device_id mcp230xx_id[] = { 950 { "mcp23008", MCP_TYPE_008 }, 951 { "mcp23017", MCP_TYPE_017 }, 952 { "mcp23018", MCP_TYPE_018 }, 953 { }, 954 }; 955 MODULE_DEVICE_TABLE(i2c, mcp230xx_id); 956 957 static struct i2c_driver mcp230xx_driver = { 958 .driver = { 959 .name = "mcp230xx", 960 .of_match_table = of_match_ptr(mcp23s08_i2c_of_match), 961 }, 962 .probe = mcp230xx_probe, 963 .id_table = mcp230xx_id, 964 }; 965 966 static int __init mcp23s08_i2c_init(void) 967 { 968 return i2c_add_driver(&mcp230xx_driver); 969 } 970 971 static void mcp23s08_i2c_exit(void) 972 { 973 i2c_del_driver(&mcp230xx_driver); 974 } 975 976 #else 977 978 static int __init mcp23s08_i2c_init(void) { return 0; } 979 static void mcp23s08_i2c_exit(void) { } 980 981 #endif /* CONFIG_I2C */ 982 983 /*----------------------------------------------------------------------*/ 984 985 #ifdef CONFIG_SPI_MASTER 986 987 static int mcp23s08_probe(struct spi_device *spi) 988 { 989 struct mcp23s08_platform_data *pdata, local_pdata; 990 unsigned addr; 991 int chips = 0; 992 struct mcp23s08_driver_data *data; 993 int status, type; 994 unsigned ngpio = 0; 995 const struct of_device_id *match; 996 997 match = of_match_device(of_match_ptr(mcp23s08_spi_of_match), &spi->dev); 998 if (match) 999 type = (int)(uintptr_t)match->data; 1000 else 1001 type = spi_get_device_id(spi)->driver_data; 1002 1003 pdata = dev_get_platdata(&spi->dev); 1004 if (!pdata) { 1005 pdata = &local_pdata; 1006 pdata->base = -1; 1007 1008 status = device_property_read_u32(&spi->dev, 1009 "microchip,spi-present-mask", &pdata->spi_present_mask); 1010 if (status) { 1011 status = device_property_read_u32(&spi->dev, 1012 "mcp,spi-present-mask", 1013 &pdata->spi_present_mask); 1014 1015 if (status) { 1016 dev_err(&spi->dev, "missing spi-present-mask"); 1017 return -ENODEV; 1018 } 1019 } 1020 } 1021 1022 if (!pdata->spi_present_mask || pdata->spi_present_mask > 0xff) { 1023 dev_err(&spi->dev, "invalid spi-present-mask"); 1024 return -ENODEV; 1025 } 1026 1027 for (addr = 0; addr < MCP_MAX_DEV_PER_CS; addr++) { 1028 if (pdata->spi_present_mask & BIT(addr)) 1029 chips++; 1030 } 1031 1032 if (!chips) 1033 return -ENODEV; 1034 1035 data = devm_kzalloc(&spi->dev, 1036 struct_size(data, chip, chips), GFP_KERNEL); 1037 if (!data) 1038 return -ENOMEM; 1039 1040 spi_set_drvdata(spi, data); 1041 1042 for (addr = 0; addr < MCP_MAX_DEV_PER_CS; addr++) { 1043 if (!(pdata->spi_present_mask & BIT(addr))) 1044 continue; 1045 chips--; 1046 data->mcp[addr] = &data->chip[chips]; 1047 data->mcp[addr]->irq = spi->irq; 1048 data->mcp[addr]->irq_chip.name = dev_name(&spi->dev); 1049 data->mcp[addr]->irq_chip.irq_mask = mcp23s08_irq_mask; 1050 data->mcp[addr]->irq_chip.irq_unmask = mcp23s08_irq_unmask; 1051 data->mcp[addr]->irq_chip.irq_set_type = mcp23s08_irq_set_type; 1052 data->mcp[addr]->irq_chip.irq_bus_lock = mcp23s08_irq_bus_lock; 1053 data->mcp[addr]->irq_chip.irq_bus_sync_unlock = 1054 mcp23s08_irq_bus_unlock; 1055 status = mcp23s08_probe_one(data->mcp[addr], &spi->dev, spi, 1056 0x40 | (addr << 1), type, 1057 pdata->base, addr); 1058 if (status < 0) 1059 return status; 1060 1061 if (pdata->base != -1) 1062 pdata->base += data->mcp[addr]->chip.ngpio; 1063 ngpio += data->mcp[addr]->chip.ngpio; 1064 } 1065 data->ngpio = ngpio; 1066 1067 return 0; 1068 } 1069 1070 static const struct spi_device_id mcp23s08_ids[] = { 1071 { "mcp23s08", MCP_TYPE_S08 }, 1072 { "mcp23s17", MCP_TYPE_S17 }, 1073 { "mcp23s18", MCP_TYPE_S18 }, 1074 { }, 1075 }; 1076 MODULE_DEVICE_TABLE(spi, mcp23s08_ids); 1077 1078 static struct spi_driver mcp23s08_driver = { 1079 .probe = mcp23s08_probe, 1080 .id_table = mcp23s08_ids, 1081 .driver = { 1082 .name = "mcp23s08", 1083 .of_match_table = of_match_ptr(mcp23s08_spi_of_match), 1084 }, 1085 }; 1086 1087 static int __init mcp23s08_spi_init(void) 1088 { 1089 return spi_register_driver(&mcp23s08_driver); 1090 } 1091 1092 static void mcp23s08_spi_exit(void) 1093 { 1094 spi_unregister_driver(&mcp23s08_driver); 1095 } 1096 1097 #else 1098 1099 static int __init mcp23s08_spi_init(void) { return 0; } 1100 static void mcp23s08_spi_exit(void) { } 1101 1102 #endif /* CONFIG_SPI_MASTER */ 1103 1104 /*----------------------------------------------------------------------*/ 1105 1106 static int __init mcp23s08_init(void) 1107 { 1108 int ret; 1109 1110 ret = mcp23s08_spi_init(); 1111 if (ret) 1112 goto spi_fail; 1113 1114 ret = mcp23s08_i2c_init(); 1115 if (ret) 1116 goto i2c_fail; 1117 1118 return 0; 1119 1120 i2c_fail: 1121 mcp23s08_spi_exit(); 1122 spi_fail: 1123 return ret; 1124 } 1125 /* register after spi/i2c postcore initcall and before 1126 * subsys initcalls that may rely on these GPIOs 1127 */ 1128 subsys_initcall(mcp23s08_init); 1129 1130 static void __exit mcp23s08_exit(void) 1131 { 1132 mcp23s08_spi_exit(); 1133 mcp23s08_i2c_exit(); 1134 } 1135 module_exit(mcp23s08_exit); 1136 1137 MODULE_LICENSE("GPL"); 1138