1 // SPDX-License-Identifier: GPL-2.0-only
2 /* MCP23S08 SPI/I2C GPIO driver */
3 
4 #include <linux/bitops.h>
5 #include <linux/kernel.h>
6 #include <linux/device.h>
7 #include <linux/mutex.h>
8 #include <linux/mod_devicetable.h>
9 #include <linux/module.h>
10 #include <linux/export.h>
11 #include <linux/gpio/driver.h>
12 #include <linux/gpio/consumer.h>
13 #include <linux/seq_file.h>
14 #include <linux/slab.h>
15 #include <asm/byteorder.h>
16 #include <linux/interrupt.h>
17 #include <linux/regmap.h>
18 #include <linux/pinctrl/pinctrl.h>
19 #include <linux/pinctrl/pinconf.h>
20 #include <linux/pinctrl/pinconf-generic.h>
21 
22 #include "pinctrl-mcp23s08.h"
23 
24 /* Registers are all 8 bits wide.
25  *
26  * The mcp23s17 has twice as many bits, and can be configured to work
27  * with either 16 bit registers or with two adjacent 8 bit banks.
28  */
29 #define MCP_IODIR	0x00		/* init/reset:  all ones */
30 #define MCP_IPOL	0x01
31 #define MCP_GPINTEN	0x02
32 #define MCP_DEFVAL	0x03
33 #define MCP_INTCON	0x04
34 #define MCP_IOCON	0x05
35 #	define IOCON_MIRROR	(1 << 6)
36 #	define IOCON_SEQOP	(1 << 5)
37 #	define IOCON_HAEN	(1 << 3)
38 #	define IOCON_ODR	(1 << 2)
39 #	define IOCON_INTPOL	(1 << 1)
40 #	define IOCON_INTCC	(1)
41 #define MCP_GPPU	0x06
42 #define MCP_INTF	0x07
43 #define MCP_INTCAP	0x08
44 #define MCP_GPIO	0x09
45 #define MCP_OLAT	0x0a
46 
47 static const struct reg_default mcp23x08_defaults[] = {
48 	{.reg = MCP_IODIR,		.def = 0xff},
49 	{.reg = MCP_IPOL,		.def = 0x00},
50 	{.reg = MCP_GPINTEN,		.def = 0x00},
51 	{.reg = MCP_DEFVAL,		.def = 0x00},
52 	{.reg = MCP_INTCON,		.def = 0x00},
53 	{.reg = MCP_IOCON,		.def = 0x00},
54 	{.reg = MCP_GPPU,		.def = 0x00},
55 	{.reg = MCP_OLAT,		.def = 0x00},
56 };
57 
58 static const struct regmap_range mcp23x08_volatile_range = {
59 	.range_min = MCP_INTF,
60 	.range_max = MCP_GPIO,
61 };
62 
63 static const struct regmap_access_table mcp23x08_volatile_table = {
64 	.yes_ranges = &mcp23x08_volatile_range,
65 	.n_yes_ranges = 1,
66 };
67 
68 static const struct regmap_range mcp23x08_precious_range = {
69 	.range_min = MCP_GPIO,
70 	.range_max = MCP_GPIO,
71 };
72 
73 static const struct regmap_access_table mcp23x08_precious_table = {
74 	.yes_ranges = &mcp23x08_precious_range,
75 	.n_yes_ranges = 1,
76 };
77 
78 const struct regmap_config mcp23x08_regmap = {
79 	.reg_bits = 8,
80 	.val_bits = 8,
81 
82 	.reg_stride = 1,
83 	.volatile_table = &mcp23x08_volatile_table,
84 	.precious_table = &mcp23x08_precious_table,
85 	.reg_defaults = mcp23x08_defaults,
86 	.num_reg_defaults = ARRAY_SIZE(mcp23x08_defaults),
87 	.cache_type = REGCACHE_FLAT,
88 	.max_register = MCP_OLAT,
89 };
90 EXPORT_SYMBOL_GPL(mcp23x08_regmap);
91 
92 static const struct reg_default mcp23x17_defaults[] = {
93 	{.reg = MCP_IODIR << 1,		.def = 0xffff},
94 	{.reg = MCP_IPOL << 1,		.def = 0x0000},
95 	{.reg = MCP_GPINTEN << 1,	.def = 0x0000},
96 	{.reg = MCP_DEFVAL << 1,	.def = 0x0000},
97 	{.reg = MCP_INTCON << 1,	.def = 0x0000},
98 	{.reg = MCP_IOCON << 1,		.def = 0x0000},
99 	{.reg = MCP_GPPU << 1,		.def = 0x0000},
100 	{.reg = MCP_OLAT << 1,		.def = 0x0000},
101 };
102 
103 static const struct regmap_range mcp23x17_volatile_range = {
104 	.range_min = MCP_INTF << 1,
105 	.range_max = MCP_GPIO << 1,
106 };
107 
108 static const struct regmap_access_table mcp23x17_volatile_table = {
109 	.yes_ranges = &mcp23x17_volatile_range,
110 	.n_yes_ranges = 1,
111 };
112 
113 static const struct regmap_range mcp23x17_precious_range = {
114 	.range_min = MCP_INTCAP << 1,
115 	.range_max = MCP_GPIO << 1,
116 };
117 
118 static const struct regmap_access_table mcp23x17_precious_table = {
119 	.yes_ranges = &mcp23x17_precious_range,
120 	.n_yes_ranges = 1,
121 };
122 
123 const struct regmap_config mcp23x17_regmap = {
124 	.reg_bits = 8,
125 	.val_bits = 16,
126 
127 	.reg_stride = 2,
128 	.max_register = MCP_OLAT << 1,
129 	.volatile_table = &mcp23x17_volatile_table,
130 	.precious_table = &mcp23x17_precious_table,
131 	.reg_defaults = mcp23x17_defaults,
132 	.num_reg_defaults = ARRAY_SIZE(mcp23x17_defaults),
133 	.cache_type = REGCACHE_FLAT,
134 	.val_format_endian = REGMAP_ENDIAN_LITTLE,
135 };
136 EXPORT_SYMBOL_GPL(mcp23x17_regmap);
137 
138 static int mcp_read(struct mcp23s08 *mcp, unsigned int reg, unsigned int *val)
139 {
140 	return regmap_read(mcp->regmap, reg << mcp->reg_shift, val);
141 }
142 
143 static int mcp_write(struct mcp23s08 *mcp, unsigned int reg, unsigned int val)
144 {
145 	return regmap_write(mcp->regmap, reg << mcp->reg_shift, val);
146 }
147 
148 static int mcp_update_bits(struct mcp23s08 *mcp, unsigned int reg,
149 			   unsigned int mask, unsigned int val)
150 {
151 	return regmap_update_bits(mcp->regmap, reg << mcp->reg_shift,
152 				  mask, val);
153 }
154 
155 static int mcp_set_bit(struct mcp23s08 *mcp, unsigned int reg,
156 		       unsigned int pin, bool enabled)
157 {
158 	u16 mask = BIT(pin);
159 	return mcp_update_bits(mcp, reg, mask, enabled ? mask : 0);
160 }
161 
162 static const struct pinctrl_pin_desc mcp23x08_pins[] = {
163 	PINCTRL_PIN(0, "gpio0"),
164 	PINCTRL_PIN(1, "gpio1"),
165 	PINCTRL_PIN(2, "gpio2"),
166 	PINCTRL_PIN(3, "gpio3"),
167 	PINCTRL_PIN(4, "gpio4"),
168 	PINCTRL_PIN(5, "gpio5"),
169 	PINCTRL_PIN(6, "gpio6"),
170 	PINCTRL_PIN(7, "gpio7"),
171 };
172 
173 static const struct pinctrl_pin_desc mcp23x17_pins[] = {
174 	PINCTRL_PIN(0, "gpio0"),
175 	PINCTRL_PIN(1, "gpio1"),
176 	PINCTRL_PIN(2, "gpio2"),
177 	PINCTRL_PIN(3, "gpio3"),
178 	PINCTRL_PIN(4, "gpio4"),
179 	PINCTRL_PIN(5, "gpio5"),
180 	PINCTRL_PIN(6, "gpio6"),
181 	PINCTRL_PIN(7, "gpio7"),
182 	PINCTRL_PIN(8, "gpio8"),
183 	PINCTRL_PIN(9, "gpio9"),
184 	PINCTRL_PIN(10, "gpio10"),
185 	PINCTRL_PIN(11, "gpio11"),
186 	PINCTRL_PIN(12, "gpio12"),
187 	PINCTRL_PIN(13, "gpio13"),
188 	PINCTRL_PIN(14, "gpio14"),
189 	PINCTRL_PIN(15, "gpio15"),
190 };
191 
192 static int mcp_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
193 {
194 	return 0;
195 }
196 
197 static const char *mcp_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
198 						unsigned int group)
199 {
200 	return NULL;
201 }
202 
203 static int mcp_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
204 					unsigned int group,
205 					const unsigned int **pins,
206 					unsigned int *num_pins)
207 {
208 	return -ENOTSUPP;
209 }
210 
211 static const struct pinctrl_ops mcp_pinctrl_ops = {
212 	.get_groups_count = mcp_pinctrl_get_groups_count,
213 	.get_group_name = mcp_pinctrl_get_group_name,
214 	.get_group_pins = mcp_pinctrl_get_group_pins,
215 #ifdef CONFIG_OF
216 	.dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
217 	.dt_free_map = pinconf_generic_dt_free_map,
218 #endif
219 };
220 
221 static int mcp_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
222 			      unsigned long *config)
223 {
224 	struct mcp23s08 *mcp = pinctrl_dev_get_drvdata(pctldev);
225 	enum pin_config_param param = pinconf_to_config_param(*config);
226 	unsigned int data, status;
227 	int ret;
228 
229 	switch (param) {
230 	case PIN_CONFIG_BIAS_PULL_UP:
231 		ret = mcp_read(mcp, MCP_GPPU, &data);
232 		if (ret < 0)
233 			return ret;
234 		status = (data & BIT(pin)) ? 1 : 0;
235 		break;
236 	default:
237 		return -ENOTSUPP;
238 	}
239 
240 	*config = 0;
241 
242 	return status ? 0 : -EINVAL;
243 }
244 
245 static int mcp_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
246 			      unsigned long *configs, unsigned int num_configs)
247 {
248 	struct mcp23s08 *mcp = pinctrl_dev_get_drvdata(pctldev);
249 	enum pin_config_param param;
250 	u32 arg;
251 	int ret = 0;
252 	int i;
253 
254 	for (i = 0; i < num_configs; i++) {
255 		param = pinconf_to_config_param(configs[i]);
256 		arg = pinconf_to_config_argument(configs[i]);
257 
258 		switch (param) {
259 		case PIN_CONFIG_BIAS_PULL_UP:
260 			ret = mcp_set_bit(mcp, MCP_GPPU, pin, arg);
261 			break;
262 		default:
263 			dev_dbg(mcp->dev, "Invalid config param %04x\n", param);
264 			return -ENOTSUPP;
265 		}
266 	}
267 
268 	return ret;
269 }
270 
271 static const struct pinconf_ops mcp_pinconf_ops = {
272 	.pin_config_get = mcp_pinconf_get,
273 	.pin_config_set = mcp_pinconf_set,
274 	.is_generic = true,
275 };
276 
277 /*----------------------------------------------------------------------*/
278 
279 static int mcp23s08_direction_input(struct gpio_chip *chip, unsigned offset)
280 {
281 	struct mcp23s08	*mcp = gpiochip_get_data(chip);
282 	int status;
283 
284 	mutex_lock(&mcp->lock);
285 	status = mcp_set_bit(mcp, MCP_IODIR, offset, true);
286 	mutex_unlock(&mcp->lock);
287 
288 	return status;
289 }
290 
291 static int mcp23s08_get(struct gpio_chip *chip, unsigned offset)
292 {
293 	struct mcp23s08	*mcp = gpiochip_get_data(chip);
294 	int status, ret;
295 
296 	mutex_lock(&mcp->lock);
297 
298 	/* REVISIT reading this clears any IRQ ... */
299 	ret = mcp_read(mcp, MCP_GPIO, &status);
300 	if (ret < 0)
301 		status = 0;
302 	else {
303 		mcp->cached_gpio = status;
304 		status = !!(status & (1 << offset));
305 	}
306 
307 	mutex_unlock(&mcp->lock);
308 	return status;
309 }
310 
311 static int mcp23s08_get_multiple(struct gpio_chip *chip,
312 				 unsigned long *mask, unsigned long *bits)
313 {
314 	struct mcp23s08 *mcp = gpiochip_get_data(chip);
315 	unsigned int status;
316 	int ret;
317 
318 	mutex_lock(&mcp->lock);
319 
320 	/* REVISIT reading this clears any IRQ ... */
321 	ret = mcp_read(mcp, MCP_GPIO, &status);
322 	if (ret < 0)
323 		status = 0;
324 	else {
325 		mcp->cached_gpio = status;
326 		*bits = status;
327 	}
328 
329 	mutex_unlock(&mcp->lock);
330 	return ret;
331 }
332 
333 static int __mcp23s08_set(struct mcp23s08 *mcp, unsigned mask, bool value)
334 {
335 	return mcp_update_bits(mcp, MCP_OLAT, mask, value ? mask : 0);
336 }
337 
338 static void mcp23s08_set(struct gpio_chip *chip, unsigned offset, int value)
339 {
340 	struct mcp23s08	*mcp = gpiochip_get_data(chip);
341 	unsigned mask = BIT(offset);
342 
343 	mutex_lock(&mcp->lock);
344 	__mcp23s08_set(mcp, mask, !!value);
345 	mutex_unlock(&mcp->lock);
346 }
347 
348 static void mcp23s08_set_multiple(struct gpio_chip *chip,
349 				  unsigned long *mask, unsigned long *bits)
350 {
351 	struct mcp23s08	*mcp = gpiochip_get_data(chip);
352 
353 	mutex_lock(&mcp->lock);
354 	mcp_update_bits(mcp, MCP_OLAT, *mask, *bits);
355 	mutex_unlock(&mcp->lock);
356 }
357 
358 static int
359 mcp23s08_direction_output(struct gpio_chip *chip, unsigned offset, int value)
360 {
361 	struct mcp23s08	*mcp = gpiochip_get_data(chip);
362 	unsigned mask = BIT(offset);
363 	int status;
364 
365 	mutex_lock(&mcp->lock);
366 	status = __mcp23s08_set(mcp, mask, value);
367 	if (status == 0) {
368 		status = mcp_update_bits(mcp, MCP_IODIR, mask, 0);
369 	}
370 	mutex_unlock(&mcp->lock);
371 	return status;
372 }
373 
374 /*----------------------------------------------------------------------*/
375 static irqreturn_t mcp23s08_irq(int irq, void *data)
376 {
377 	struct mcp23s08 *mcp = data;
378 	int intcap, intcon, intf, i, gpio, gpio_orig, intcap_mask, defval;
379 	unsigned int child_irq;
380 	bool intf_set, intcap_changed, gpio_bit_changed,
381 		defval_changed, gpio_set;
382 
383 	mutex_lock(&mcp->lock);
384 	if (mcp_read(mcp, MCP_INTF, &intf))
385 		goto unlock;
386 
387 	if (intf == 0) {
388 		/* There is no interrupt pending */
389 		goto unlock;
390 	}
391 
392 	if (mcp_read(mcp, MCP_INTCAP, &intcap))
393 		goto unlock;
394 
395 	if (mcp_read(mcp, MCP_INTCON, &intcon))
396 		goto unlock;
397 
398 	if (mcp_read(mcp, MCP_DEFVAL, &defval))
399 		goto unlock;
400 
401 	/* This clears the interrupt(configurable on S18) */
402 	if (mcp_read(mcp, MCP_GPIO, &gpio))
403 		goto unlock;
404 
405 	gpio_orig = mcp->cached_gpio;
406 	mcp->cached_gpio = gpio;
407 	mutex_unlock(&mcp->lock);
408 
409 	dev_dbg(mcp->chip.parent,
410 		"intcap 0x%04X intf 0x%04X gpio_orig 0x%04X gpio 0x%04X\n",
411 		intcap, intf, gpio_orig, gpio);
412 
413 	for (i = 0; i < mcp->chip.ngpio; i++) {
414 		/* We must check all of the inputs on the chip,
415 		 * otherwise we may not notice a change on >=2 pins.
416 		 *
417 		 * On at least the mcp23s17, INTCAP is only updated
418 		 * one byte at a time(INTCAPA and INTCAPB are
419 		 * not written to at the same time - only on a per-bank
420 		 * basis).
421 		 *
422 		 * INTF only contains the single bit that caused the
423 		 * interrupt per-bank.  On the mcp23s17, there is
424 		 * INTFA and INTFB.  If two pins are changed on the A
425 		 * side at the same time, INTF will only have one bit
426 		 * set.  If one pin on the A side and one pin on the B
427 		 * side are changed at the same time, INTF will have
428 		 * two bits set.  Thus, INTF can't be the only check
429 		 * to see if the input has changed.
430 		 */
431 
432 		intf_set = intf & BIT(i);
433 		if (i < 8 && intf_set)
434 			intcap_mask = 0x00FF;
435 		else if (i >= 8 && intf_set)
436 			intcap_mask = 0xFF00;
437 		else
438 			intcap_mask = 0x00;
439 
440 		intcap_changed = (intcap_mask &
441 			(intcap & BIT(i))) !=
442 			(intcap_mask & (BIT(i) & gpio_orig));
443 		gpio_set = BIT(i) & gpio;
444 		gpio_bit_changed = (BIT(i) & gpio_orig) !=
445 			(BIT(i) & gpio);
446 		defval_changed = (BIT(i) & intcon) &&
447 			((BIT(i) & gpio) !=
448 			(BIT(i) & defval));
449 
450 		if (((gpio_bit_changed || intcap_changed) &&
451 			(BIT(i) & mcp->irq_rise) && gpio_set) ||
452 		    ((gpio_bit_changed || intcap_changed) &&
453 			(BIT(i) & mcp->irq_fall) && !gpio_set) ||
454 		    defval_changed) {
455 			child_irq = irq_find_mapping(mcp->chip.irq.domain, i);
456 			handle_nested_irq(child_irq);
457 		}
458 	}
459 
460 	return IRQ_HANDLED;
461 
462 unlock:
463 	mutex_unlock(&mcp->lock);
464 	return IRQ_HANDLED;
465 }
466 
467 static void mcp23s08_irq_mask(struct irq_data *data)
468 {
469 	struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
470 	struct mcp23s08 *mcp = gpiochip_get_data(gc);
471 	unsigned int pos = irqd_to_hwirq(data);
472 
473 	mcp_set_bit(mcp, MCP_GPINTEN, pos, false);
474 	gpiochip_disable_irq(gc, pos);
475 }
476 
477 static void mcp23s08_irq_unmask(struct irq_data *data)
478 {
479 	struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
480 	struct mcp23s08 *mcp = gpiochip_get_data(gc);
481 	unsigned int pos = irqd_to_hwirq(data);
482 
483 	gpiochip_enable_irq(gc, pos);
484 	mcp_set_bit(mcp, MCP_GPINTEN, pos, true);
485 }
486 
487 static int mcp23s08_irq_set_type(struct irq_data *data, unsigned int type)
488 {
489 	struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
490 	struct mcp23s08 *mcp = gpiochip_get_data(gc);
491 	unsigned int pos = irqd_to_hwirq(data);
492 
493 	if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
494 		mcp_set_bit(mcp, MCP_INTCON, pos, false);
495 		mcp->irq_rise |= BIT(pos);
496 		mcp->irq_fall |= BIT(pos);
497 	} else if (type & IRQ_TYPE_EDGE_RISING) {
498 		mcp_set_bit(mcp, MCP_INTCON, pos, false);
499 		mcp->irq_rise |= BIT(pos);
500 		mcp->irq_fall &= ~BIT(pos);
501 	} else if (type & IRQ_TYPE_EDGE_FALLING) {
502 		mcp_set_bit(mcp, MCP_INTCON, pos, false);
503 		mcp->irq_rise &= ~BIT(pos);
504 		mcp->irq_fall |= BIT(pos);
505 	} else if (type & IRQ_TYPE_LEVEL_HIGH) {
506 		mcp_set_bit(mcp, MCP_INTCON, pos, true);
507 		mcp_set_bit(mcp, MCP_DEFVAL, pos, false);
508 	} else if (type & IRQ_TYPE_LEVEL_LOW) {
509 		mcp_set_bit(mcp, MCP_INTCON, pos, true);
510 		mcp_set_bit(mcp, MCP_DEFVAL, pos, true);
511 	} else
512 		return -EINVAL;
513 
514 	return 0;
515 }
516 
517 static void mcp23s08_irq_bus_lock(struct irq_data *data)
518 {
519 	struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
520 	struct mcp23s08 *mcp = gpiochip_get_data(gc);
521 
522 	mutex_lock(&mcp->lock);
523 	regcache_cache_only(mcp->regmap, true);
524 }
525 
526 static void mcp23s08_irq_bus_unlock(struct irq_data *data)
527 {
528 	struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
529 	struct mcp23s08 *mcp = gpiochip_get_data(gc);
530 
531 	regcache_cache_only(mcp->regmap, false);
532 	regcache_sync(mcp->regmap);
533 
534 	mutex_unlock(&mcp->lock);
535 }
536 
537 static int mcp23s08_irq_setup(struct mcp23s08 *mcp)
538 {
539 	struct gpio_chip *chip = &mcp->chip;
540 	int err;
541 	unsigned long irqflags = IRQF_ONESHOT | IRQF_SHARED;
542 
543 	if (mcp->irq_active_high)
544 		irqflags |= IRQF_TRIGGER_HIGH;
545 	else
546 		irqflags |= IRQF_TRIGGER_LOW;
547 
548 	err = devm_request_threaded_irq(chip->parent, mcp->irq, NULL,
549 					mcp23s08_irq,
550 					irqflags, dev_name(chip->parent), mcp);
551 	if (err != 0) {
552 		dev_err(chip->parent, "unable to request IRQ#%d: %d\n",
553 			mcp->irq, err);
554 		return err;
555 	}
556 
557 	return 0;
558 }
559 
560 static void mcp23s08_irq_print_chip(struct irq_data *d, struct seq_file *p)
561 {
562 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
563 	struct mcp23s08 *mcp = gpiochip_get_data(gc);
564 
565 	seq_printf(p, dev_name(mcp->dev));
566 }
567 
568 static const struct irq_chip mcp23s08_irq_chip = {
569 	.irq_mask = mcp23s08_irq_mask,
570 	.irq_unmask = mcp23s08_irq_unmask,
571 	.irq_set_type = mcp23s08_irq_set_type,
572 	.irq_bus_lock = mcp23s08_irq_bus_lock,
573 	.irq_bus_sync_unlock = mcp23s08_irq_bus_unlock,
574 	.irq_print_chip = mcp23s08_irq_print_chip,
575 	.flags = IRQCHIP_IMMUTABLE,
576 	GPIOCHIP_IRQ_RESOURCE_HELPERS,
577 };
578 
579 /*----------------------------------------------------------------------*/
580 
581 int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev,
582 		       unsigned int addr, unsigned int type, unsigned int base)
583 {
584 	int status, ret;
585 	bool mirror = false;
586 	bool open_drain = false;
587 
588 	mutex_init(&mcp->lock);
589 
590 	mcp->dev = dev;
591 	mcp->addr = addr;
592 
593 	mcp->irq_active_high = false;
594 
595 	mcp->chip.direction_input = mcp23s08_direction_input;
596 	mcp->chip.get = mcp23s08_get;
597 	mcp->chip.get_multiple = mcp23s08_get_multiple;
598 	mcp->chip.direction_output = mcp23s08_direction_output;
599 	mcp->chip.set = mcp23s08_set;
600 	mcp->chip.set_multiple = mcp23s08_set_multiple;
601 
602 	mcp->chip.base = base;
603 	mcp->chip.can_sleep = true;
604 	mcp->chip.parent = dev;
605 	mcp->chip.owner = THIS_MODULE;
606 
607 	mcp->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
608 
609 	/* verify MCP_IOCON.SEQOP = 0, so sequential reads work,
610 	 * and MCP_IOCON.HAEN = 1, so we work with all chips.
611 	 */
612 
613 	ret = mcp_read(mcp, MCP_IOCON, &status);
614 	if (ret < 0)
615 		return dev_err_probe(dev, ret, "can't identify chip %d\n", addr);
616 
617 	mcp->irq_controller =
618 		device_property_read_bool(dev, "interrupt-controller");
619 	if (mcp->irq && mcp->irq_controller) {
620 		mcp->irq_active_high =
621 			device_property_read_bool(dev,
622 					      "microchip,irq-active-high");
623 
624 		mirror = device_property_read_bool(dev, "microchip,irq-mirror");
625 		open_drain = device_property_read_bool(dev, "drive-open-drain");
626 	}
627 
628 	if ((status & IOCON_SEQOP) || !(status & IOCON_HAEN) || mirror ||
629 	     mcp->irq_active_high || open_drain) {
630 		/* mcp23s17 has IOCON twice, make sure they are in sync */
631 		status &= ~(IOCON_SEQOP | (IOCON_SEQOP << 8));
632 		status |= IOCON_HAEN | (IOCON_HAEN << 8);
633 		if (mcp->irq_active_high)
634 			status |= IOCON_INTPOL | (IOCON_INTPOL << 8);
635 		else
636 			status &= ~(IOCON_INTPOL | (IOCON_INTPOL << 8));
637 
638 		if (mirror)
639 			status |= IOCON_MIRROR | (IOCON_MIRROR << 8);
640 
641 		if (open_drain)
642 			status |= IOCON_ODR | (IOCON_ODR << 8);
643 
644 		if (type == MCP_TYPE_S18 || type == MCP_TYPE_018)
645 			status |= IOCON_INTCC | (IOCON_INTCC << 8);
646 
647 		ret = mcp_write(mcp, MCP_IOCON, status);
648 		if (ret < 0)
649 			return dev_err_probe(dev, ret, "can't write IOCON %d\n", addr);
650 	}
651 
652 	if (mcp->irq && mcp->irq_controller) {
653 		struct gpio_irq_chip *girq = &mcp->chip.irq;
654 
655 		gpio_irq_chip_set_chip(girq, &mcp23s08_irq_chip);
656 		/* This will let us handle the parent IRQ in the driver */
657 		girq->parent_handler = NULL;
658 		girq->num_parents = 0;
659 		girq->parents = NULL;
660 		girq->default_type = IRQ_TYPE_NONE;
661 		girq->handler = handle_simple_irq;
662 		girq->threaded = true;
663 	}
664 
665 	ret = devm_gpiochip_add_data(dev, &mcp->chip, mcp);
666 	if (ret < 0)
667 		return dev_err_probe(dev, ret, "can't add GPIO chip\n");
668 
669 	mcp->pinctrl_desc.pctlops = &mcp_pinctrl_ops;
670 	mcp->pinctrl_desc.confops = &mcp_pinconf_ops;
671 	mcp->pinctrl_desc.npins = mcp->chip.ngpio;
672 	if (mcp->pinctrl_desc.npins == 8)
673 		mcp->pinctrl_desc.pins = mcp23x08_pins;
674 	else if (mcp->pinctrl_desc.npins == 16)
675 		mcp->pinctrl_desc.pins = mcp23x17_pins;
676 	mcp->pinctrl_desc.owner = THIS_MODULE;
677 
678 	mcp->pctldev = devm_pinctrl_register(dev, &mcp->pinctrl_desc, mcp);
679 	if (IS_ERR(mcp->pctldev))
680 		return dev_err_probe(dev, PTR_ERR(mcp->pctldev), "can't register controller\n");
681 
682 	if (mcp->irq) {
683 		ret = mcp23s08_irq_setup(mcp);
684 		if (ret)
685 			return dev_err_probe(dev, ret, "can't setup IRQ\n");
686 	}
687 
688 	return 0;
689 }
690 EXPORT_SYMBOL_GPL(mcp23s08_probe_one);
691 
692 MODULE_LICENSE("GPL");
693