1 /* MCP23S08 SPI/I2C GPIO driver */ 2 3 #include <linux/kernel.h> 4 #include <linux/device.h> 5 #include <linux/mutex.h> 6 #include <linux/module.h> 7 #include <linux/gpio/driver.h> 8 #include <linux/i2c.h> 9 #include <linux/spi/spi.h> 10 #include <linux/spi/mcp23s08.h> 11 #include <linux/slab.h> 12 #include <asm/byteorder.h> 13 #include <linux/interrupt.h> 14 #include <linux/of_device.h> 15 #include <linux/regmap.h> 16 #include <linux/pinctrl/pinctrl.h> 17 #include <linux/pinctrl/pinconf.h> 18 #include <linux/pinctrl/pinconf-generic.h> 19 20 /* 21 * MCP types supported by driver 22 */ 23 #define MCP_TYPE_S08 0 24 #define MCP_TYPE_S17 1 25 #define MCP_TYPE_008 2 26 #define MCP_TYPE_017 3 27 #define MCP_TYPE_S18 4 28 #define MCP_TYPE_018 5 29 30 #define MCP_MAX_DEV_PER_CS 8 31 32 /* Registers are all 8 bits wide. 33 * 34 * The mcp23s17 has twice as many bits, and can be configured to work 35 * with either 16 bit registers or with two adjacent 8 bit banks. 36 */ 37 #define MCP_IODIR 0x00 /* init/reset: all ones */ 38 #define MCP_IPOL 0x01 39 #define MCP_GPINTEN 0x02 40 #define MCP_DEFVAL 0x03 41 #define MCP_INTCON 0x04 42 #define MCP_IOCON 0x05 43 # define IOCON_MIRROR (1 << 6) 44 # define IOCON_SEQOP (1 << 5) 45 # define IOCON_HAEN (1 << 3) 46 # define IOCON_ODR (1 << 2) 47 # define IOCON_INTPOL (1 << 1) 48 # define IOCON_INTCC (1) 49 #define MCP_GPPU 0x06 50 #define MCP_INTF 0x07 51 #define MCP_INTCAP 0x08 52 #define MCP_GPIO 0x09 53 #define MCP_OLAT 0x0a 54 55 struct mcp23s08; 56 57 struct mcp23s08 { 58 u8 addr; 59 bool irq_active_high; 60 bool reg_shift; 61 62 u16 irq_rise; 63 u16 irq_fall; 64 int irq; 65 bool irq_controller; 66 int cached_gpio; 67 /* lock protects regmap access with bypass/cache flags */ 68 struct mutex lock; 69 70 struct gpio_chip chip; 71 struct irq_chip irq_chip; 72 73 struct regmap *regmap; 74 struct device *dev; 75 76 struct pinctrl_dev *pctldev; 77 struct pinctrl_desc pinctrl_desc; 78 }; 79 80 static const struct reg_default mcp23x08_defaults[] = { 81 {.reg = MCP_IODIR, .def = 0xff}, 82 {.reg = MCP_IPOL, .def = 0x00}, 83 {.reg = MCP_GPINTEN, .def = 0x00}, 84 {.reg = MCP_DEFVAL, .def = 0x00}, 85 {.reg = MCP_INTCON, .def = 0x00}, 86 {.reg = MCP_IOCON, .def = 0x00}, 87 {.reg = MCP_GPPU, .def = 0x00}, 88 {.reg = MCP_OLAT, .def = 0x00}, 89 }; 90 91 static const struct regmap_range mcp23x08_volatile_range = { 92 .range_min = MCP_INTF, 93 .range_max = MCP_GPIO, 94 }; 95 96 static const struct regmap_access_table mcp23x08_volatile_table = { 97 .yes_ranges = &mcp23x08_volatile_range, 98 .n_yes_ranges = 1, 99 }; 100 101 static const struct regmap_range mcp23x08_precious_range = { 102 .range_min = MCP_GPIO, 103 .range_max = MCP_GPIO, 104 }; 105 106 static const struct regmap_access_table mcp23x08_precious_table = { 107 .yes_ranges = &mcp23x08_precious_range, 108 .n_yes_ranges = 1, 109 }; 110 111 static const struct regmap_config mcp23x08_regmap = { 112 .reg_bits = 8, 113 .val_bits = 8, 114 115 .reg_stride = 1, 116 .volatile_table = &mcp23x08_volatile_table, 117 .precious_table = &mcp23x08_precious_table, 118 .reg_defaults = mcp23x08_defaults, 119 .num_reg_defaults = ARRAY_SIZE(mcp23x08_defaults), 120 .cache_type = REGCACHE_FLAT, 121 .max_register = MCP_OLAT, 122 }; 123 124 static const struct reg_default mcp23x16_defaults[] = { 125 {.reg = MCP_IODIR << 1, .def = 0xffff}, 126 {.reg = MCP_IPOL << 1, .def = 0x0000}, 127 {.reg = MCP_GPINTEN << 1, .def = 0x0000}, 128 {.reg = MCP_DEFVAL << 1, .def = 0x0000}, 129 {.reg = MCP_INTCON << 1, .def = 0x0000}, 130 {.reg = MCP_IOCON << 1, .def = 0x0000}, 131 {.reg = MCP_GPPU << 1, .def = 0x0000}, 132 {.reg = MCP_OLAT << 1, .def = 0x0000}, 133 }; 134 135 static const struct regmap_range mcp23x16_volatile_range = { 136 .range_min = MCP_INTF << 1, 137 .range_max = MCP_GPIO << 1, 138 }; 139 140 static const struct regmap_access_table mcp23x16_volatile_table = { 141 .yes_ranges = &mcp23x16_volatile_range, 142 .n_yes_ranges = 1, 143 }; 144 145 static const struct regmap_range mcp23x16_precious_range = { 146 .range_min = MCP_GPIO << 1, 147 .range_max = MCP_GPIO << 1, 148 }; 149 150 static const struct regmap_access_table mcp23x16_precious_table = { 151 .yes_ranges = &mcp23x16_precious_range, 152 .n_yes_ranges = 1, 153 }; 154 155 static const struct regmap_config mcp23x17_regmap = { 156 .reg_bits = 8, 157 .val_bits = 16, 158 159 .reg_stride = 2, 160 .max_register = MCP_OLAT << 1, 161 .volatile_table = &mcp23x16_volatile_table, 162 .precious_table = &mcp23x16_precious_table, 163 .reg_defaults = mcp23x16_defaults, 164 .num_reg_defaults = ARRAY_SIZE(mcp23x16_defaults), 165 .cache_type = REGCACHE_FLAT, 166 .val_format_endian = REGMAP_ENDIAN_LITTLE, 167 }; 168 169 static int mcp_read(struct mcp23s08 *mcp, unsigned int reg, unsigned int *val) 170 { 171 return regmap_read(mcp->regmap, reg << mcp->reg_shift, val); 172 } 173 174 static int mcp_write(struct mcp23s08 *mcp, unsigned int reg, unsigned int val) 175 { 176 return regmap_write(mcp->regmap, reg << mcp->reg_shift, val); 177 } 178 179 static int mcp_set_mask(struct mcp23s08 *mcp, unsigned int reg, 180 unsigned int mask, bool enabled) 181 { 182 u16 val = enabled ? 0xffff : 0x0000; 183 return regmap_update_bits(mcp->regmap, reg << mcp->reg_shift, 184 mask, val); 185 } 186 187 static int mcp_set_bit(struct mcp23s08 *mcp, unsigned int reg, 188 unsigned int pin, bool enabled) 189 { 190 u16 mask = BIT(pin); 191 return mcp_set_mask(mcp, reg, mask, enabled); 192 } 193 194 static const struct pinctrl_pin_desc mcp23x08_pins[] = { 195 PINCTRL_PIN(0, "gpio0"), 196 PINCTRL_PIN(1, "gpio1"), 197 PINCTRL_PIN(2, "gpio2"), 198 PINCTRL_PIN(3, "gpio3"), 199 PINCTRL_PIN(4, "gpio4"), 200 PINCTRL_PIN(5, "gpio5"), 201 PINCTRL_PIN(6, "gpio6"), 202 PINCTRL_PIN(7, "gpio7"), 203 }; 204 205 static const struct pinctrl_pin_desc mcp23x17_pins[] = { 206 PINCTRL_PIN(0, "gpio0"), 207 PINCTRL_PIN(1, "gpio1"), 208 PINCTRL_PIN(2, "gpio2"), 209 PINCTRL_PIN(3, "gpio3"), 210 PINCTRL_PIN(4, "gpio4"), 211 PINCTRL_PIN(5, "gpio5"), 212 PINCTRL_PIN(6, "gpio6"), 213 PINCTRL_PIN(7, "gpio7"), 214 PINCTRL_PIN(8, "gpio8"), 215 PINCTRL_PIN(9, "gpio9"), 216 PINCTRL_PIN(10, "gpio10"), 217 PINCTRL_PIN(11, "gpio11"), 218 PINCTRL_PIN(12, "gpio12"), 219 PINCTRL_PIN(13, "gpio13"), 220 PINCTRL_PIN(14, "gpio14"), 221 PINCTRL_PIN(15, "gpio15"), 222 }; 223 224 static int mcp_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) 225 { 226 return 0; 227 } 228 229 static const char *mcp_pinctrl_get_group_name(struct pinctrl_dev *pctldev, 230 unsigned int group) 231 { 232 return NULL; 233 } 234 235 static int mcp_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, 236 unsigned int group, 237 const unsigned int **pins, 238 unsigned int *num_pins) 239 { 240 return -ENOTSUPP; 241 } 242 243 static const struct pinctrl_ops mcp_pinctrl_ops = { 244 .get_groups_count = mcp_pinctrl_get_groups_count, 245 .get_group_name = mcp_pinctrl_get_group_name, 246 .get_group_pins = mcp_pinctrl_get_group_pins, 247 #ifdef CONFIG_OF 248 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, 249 .dt_free_map = pinconf_generic_dt_free_map, 250 #endif 251 }; 252 253 static int mcp_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, 254 unsigned long *config) 255 { 256 struct mcp23s08 *mcp = pinctrl_dev_get_drvdata(pctldev); 257 enum pin_config_param param = pinconf_to_config_param(*config); 258 unsigned int data, status; 259 int ret; 260 261 switch (param) { 262 case PIN_CONFIG_BIAS_PULL_UP: 263 ret = mcp_read(mcp, MCP_GPPU, &data); 264 if (ret < 0) 265 return ret; 266 status = (data & BIT(pin)) ? 1 : 0; 267 break; 268 default: 269 return -ENOTSUPP; 270 } 271 272 *config = 0; 273 274 return status ? 0 : -EINVAL; 275 } 276 277 static int mcp_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 278 unsigned long *configs, unsigned int num_configs) 279 { 280 struct mcp23s08 *mcp = pinctrl_dev_get_drvdata(pctldev); 281 enum pin_config_param param; 282 u32 arg; 283 int ret = 0; 284 int i; 285 286 for (i = 0; i < num_configs; i++) { 287 param = pinconf_to_config_param(configs[i]); 288 arg = pinconf_to_config_argument(configs[i]); 289 290 switch (param) { 291 case PIN_CONFIG_BIAS_PULL_UP: 292 ret = mcp_set_bit(mcp, MCP_GPPU, pin, arg); 293 break; 294 default: 295 dev_dbg(mcp->dev, "Invalid config param %04x\n", param); 296 return -ENOTSUPP; 297 } 298 } 299 300 return ret; 301 } 302 303 static const struct pinconf_ops mcp_pinconf_ops = { 304 .pin_config_get = mcp_pinconf_get, 305 .pin_config_set = mcp_pinconf_set, 306 .is_generic = true, 307 }; 308 309 /*----------------------------------------------------------------------*/ 310 311 #ifdef CONFIG_SPI_MASTER 312 313 static int mcp23sxx_spi_write(void *context, const void *data, size_t count) 314 { 315 struct mcp23s08 *mcp = context; 316 struct spi_device *spi = to_spi_device(mcp->dev); 317 struct spi_message m; 318 struct spi_transfer t[2] = { { .tx_buf = &mcp->addr, .len = 1, }, 319 { .tx_buf = data, .len = count, }, }; 320 321 spi_message_init(&m); 322 spi_message_add_tail(&t[0], &m); 323 spi_message_add_tail(&t[1], &m); 324 325 return spi_sync(spi, &m); 326 } 327 328 static int mcp23sxx_spi_gather_write(void *context, 329 const void *reg, size_t reg_size, 330 const void *val, size_t val_size) 331 { 332 struct mcp23s08 *mcp = context; 333 struct spi_device *spi = to_spi_device(mcp->dev); 334 struct spi_message m; 335 struct spi_transfer t[3] = { { .tx_buf = &mcp->addr, .len = 1, }, 336 { .tx_buf = reg, .len = reg_size, }, 337 { .tx_buf = val, .len = val_size, }, }; 338 339 spi_message_init(&m); 340 spi_message_add_tail(&t[0], &m); 341 spi_message_add_tail(&t[1], &m); 342 spi_message_add_tail(&t[2], &m); 343 344 return spi_sync(spi, &m); 345 } 346 347 static int mcp23sxx_spi_read(void *context, const void *reg, size_t reg_size, 348 void *val, size_t val_size) 349 { 350 struct mcp23s08 *mcp = context; 351 struct spi_device *spi = to_spi_device(mcp->dev); 352 u8 tx[2]; 353 354 if (reg_size != 1) 355 return -EINVAL; 356 357 tx[0] = mcp->addr | 0x01; 358 tx[1] = *((u8 *) reg); 359 360 return spi_write_then_read(spi, tx, sizeof(tx), val, val_size); 361 } 362 363 static const struct regmap_bus mcp23sxx_spi_regmap = { 364 .write = mcp23sxx_spi_write, 365 .gather_write = mcp23sxx_spi_gather_write, 366 .read = mcp23sxx_spi_read, 367 }; 368 369 #endif /* CONFIG_SPI_MASTER */ 370 371 /*----------------------------------------------------------------------*/ 372 373 /* A given spi_device can represent up to eight mcp23sxx chips 374 * sharing the same chipselect but using different addresses 375 * (e.g. chips #0 and #3 might be populated, but not #1 or $2). 376 * Driver data holds all the per-chip data. 377 */ 378 struct mcp23s08_driver_data { 379 unsigned ngpio; 380 struct mcp23s08 *mcp[8]; 381 struct mcp23s08 chip[]; 382 }; 383 384 385 static int mcp23s08_direction_input(struct gpio_chip *chip, unsigned offset) 386 { 387 struct mcp23s08 *mcp = gpiochip_get_data(chip); 388 int status; 389 390 mutex_lock(&mcp->lock); 391 status = mcp_set_bit(mcp, MCP_IODIR, offset, true); 392 mutex_unlock(&mcp->lock); 393 394 return status; 395 } 396 397 static int mcp23s08_get(struct gpio_chip *chip, unsigned offset) 398 { 399 struct mcp23s08 *mcp = gpiochip_get_data(chip); 400 int status, ret; 401 402 mutex_lock(&mcp->lock); 403 404 /* REVISIT reading this clears any IRQ ... */ 405 ret = mcp_read(mcp, MCP_GPIO, &status); 406 if (ret < 0) 407 status = 0; 408 else { 409 mcp->cached_gpio = status; 410 status = !!(status & (1 << offset)); 411 } 412 413 mutex_unlock(&mcp->lock); 414 return status; 415 } 416 417 static int __mcp23s08_set(struct mcp23s08 *mcp, unsigned mask, bool value) 418 { 419 return mcp_set_mask(mcp, MCP_OLAT, mask, value); 420 } 421 422 static void mcp23s08_set(struct gpio_chip *chip, unsigned offset, int value) 423 { 424 struct mcp23s08 *mcp = gpiochip_get_data(chip); 425 unsigned mask = BIT(offset); 426 427 mutex_lock(&mcp->lock); 428 __mcp23s08_set(mcp, mask, !!value); 429 mutex_unlock(&mcp->lock); 430 } 431 432 static int 433 mcp23s08_direction_output(struct gpio_chip *chip, unsigned offset, int value) 434 { 435 struct mcp23s08 *mcp = gpiochip_get_data(chip); 436 unsigned mask = BIT(offset); 437 int status; 438 439 mutex_lock(&mcp->lock); 440 status = __mcp23s08_set(mcp, mask, value); 441 if (status == 0) { 442 status = mcp_set_mask(mcp, MCP_IODIR, mask, false); 443 } 444 mutex_unlock(&mcp->lock); 445 return status; 446 } 447 448 /*----------------------------------------------------------------------*/ 449 static irqreturn_t mcp23s08_irq(int irq, void *data) 450 { 451 struct mcp23s08 *mcp = data; 452 int intcap, intcon, intf, i, gpio, gpio_orig, intcap_mask, defval; 453 unsigned int child_irq; 454 bool intf_set, intcap_changed, gpio_bit_changed, 455 defval_changed, gpio_set; 456 457 mutex_lock(&mcp->lock); 458 if (mcp_read(mcp, MCP_INTF, &intf)) 459 goto unlock; 460 461 if (mcp_read(mcp, MCP_INTCAP, &intcap)) 462 goto unlock; 463 464 if (mcp_read(mcp, MCP_INTCON, &intcon)) 465 goto unlock; 466 467 if (mcp_read(mcp, MCP_DEFVAL, &defval)) 468 goto unlock; 469 470 /* This clears the interrupt(configurable on S18) */ 471 if (mcp_read(mcp, MCP_GPIO, &gpio)) 472 goto unlock; 473 474 gpio_orig = mcp->cached_gpio; 475 mcp->cached_gpio = gpio; 476 mutex_unlock(&mcp->lock); 477 478 if (intf == 0) { 479 /* There is no interrupt pending */ 480 return IRQ_HANDLED; 481 } 482 483 dev_dbg(mcp->chip.parent, 484 "intcap 0x%04X intf 0x%04X gpio_orig 0x%04X gpio 0x%04X\n", 485 intcap, intf, gpio_orig, gpio); 486 487 for (i = 0; i < mcp->chip.ngpio; i++) { 488 /* We must check all of the inputs on the chip, 489 * otherwise we may not notice a change on >=2 pins. 490 * 491 * On at least the mcp23s17, INTCAP is only updated 492 * one byte at a time(INTCAPA and INTCAPB are 493 * not written to at the same time - only on a per-bank 494 * basis). 495 * 496 * INTF only contains the single bit that caused the 497 * interrupt per-bank. On the mcp23s17, there is 498 * INTFA and INTFB. If two pins are changed on the A 499 * side at the same time, INTF will only have one bit 500 * set. If one pin on the A side and one pin on the B 501 * side are changed at the same time, INTF will have 502 * two bits set. Thus, INTF can't be the only check 503 * to see if the input has changed. 504 */ 505 506 intf_set = intf & BIT(i); 507 if (i < 8 && intf_set) 508 intcap_mask = 0x00FF; 509 else if (i >= 8 && intf_set) 510 intcap_mask = 0xFF00; 511 else 512 intcap_mask = 0x00; 513 514 intcap_changed = (intcap_mask & 515 (intcap & BIT(i))) != 516 (intcap_mask & (BIT(i) & gpio_orig)); 517 gpio_set = BIT(i) & gpio; 518 gpio_bit_changed = (BIT(i) & gpio_orig) != 519 (BIT(i) & gpio); 520 defval_changed = (BIT(i) & intcon) && 521 ((BIT(i) & gpio) != 522 (BIT(i) & defval)); 523 524 if (((gpio_bit_changed || intcap_changed) && 525 (BIT(i) & mcp->irq_rise) && gpio_set) || 526 ((gpio_bit_changed || intcap_changed) && 527 (BIT(i) & mcp->irq_fall) && !gpio_set) || 528 defval_changed) { 529 child_irq = irq_find_mapping(mcp->chip.irq.domain, i); 530 handle_nested_irq(child_irq); 531 } 532 } 533 534 return IRQ_HANDLED; 535 536 unlock: 537 mutex_unlock(&mcp->lock); 538 return IRQ_HANDLED; 539 } 540 541 static void mcp23s08_irq_mask(struct irq_data *data) 542 { 543 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 544 struct mcp23s08 *mcp = gpiochip_get_data(gc); 545 unsigned int pos = data->hwirq; 546 547 mcp_set_bit(mcp, MCP_GPINTEN, pos, false); 548 } 549 550 static void mcp23s08_irq_unmask(struct irq_data *data) 551 { 552 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 553 struct mcp23s08 *mcp = gpiochip_get_data(gc); 554 unsigned int pos = data->hwirq; 555 556 mcp_set_bit(mcp, MCP_GPINTEN, pos, true); 557 } 558 559 static int mcp23s08_irq_set_type(struct irq_data *data, unsigned int type) 560 { 561 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 562 struct mcp23s08 *mcp = gpiochip_get_data(gc); 563 unsigned int pos = data->hwirq; 564 int status = 0; 565 566 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) { 567 mcp_set_bit(mcp, MCP_INTCON, pos, false); 568 mcp->irq_rise |= BIT(pos); 569 mcp->irq_fall |= BIT(pos); 570 } else if (type & IRQ_TYPE_EDGE_RISING) { 571 mcp_set_bit(mcp, MCP_INTCON, pos, false); 572 mcp->irq_rise |= BIT(pos); 573 mcp->irq_fall &= ~BIT(pos); 574 } else if (type & IRQ_TYPE_EDGE_FALLING) { 575 mcp_set_bit(mcp, MCP_INTCON, pos, false); 576 mcp->irq_rise &= ~BIT(pos); 577 mcp->irq_fall |= BIT(pos); 578 } else if (type & IRQ_TYPE_LEVEL_HIGH) { 579 mcp_set_bit(mcp, MCP_INTCON, pos, true); 580 mcp_set_bit(mcp, MCP_DEFVAL, pos, false); 581 } else if (type & IRQ_TYPE_LEVEL_LOW) { 582 mcp_set_bit(mcp, MCP_INTCON, pos, true); 583 mcp_set_bit(mcp, MCP_DEFVAL, pos, true); 584 } else 585 return -EINVAL; 586 587 return status; 588 } 589 590 static void mcp23s08_irq_bus_lock(struct irq_data *data) 591 { 592 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 593 struct mcp23s08 *mcp = gpiochip_get_data(gc); 594 595 mutex_lock(&mcp->lock); 596 regcache_cache_only(mcp->regmap, true); 597 } 598 599 static void mcp23s08_irq_bus_unlock(struct irq_data *data) 600 { 601 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 602 struct mcp23s08 *mcp = gpiochip_get_data(gc); 603 604 regcache_cache_only(mcp->regmap, false); 605 regcache_sync(mcp->regmap); 606 607 mutex_unlock(&mcp->lock); 608 } 609 610 static int mcp23s08_irq_setup(struct mcp23s08 *mcp) 611 { 612 struct gpio_chip *chip = &mcp->chip; 613 int err; 614 unsigned long irqflags = IRQF_ONESHOT | IRQF_SHARED; 615 616 if (mcp->irq_active_high) 617 irqflags |= IRQF_TRIGGER_HIGH; 618 else 619 irqflags |= IRQF_TRIGGER_LOW; 620 621 err = devm_request_threaded_irq(chip->parent, mcp->irq, NULL, 622 mcp23s08_irq, 623 irqflags, dev_name(chip->parent), mcp); 624 if (err != 0) { 625 dev_err(chip->parent, "unable to request IRQ#%d: %d\n", 626 mcp->irq, err); 627 return err; 628 } 629 630 return 0; 631 } 632 633 static int mcp23s08_irqchip_setup(struct mcp23s08 *mcp) 634 { 635 struct gpio_chip *chip = &mcp->chip; 636 int err; 637 638 err = gpiochip_irqchip_add_nested(chip, 639 &mcp->irq_chip, 640 0, 641 handle_simple_irq, 642 IRQ_TYPE_NONE); 643 if (err) { 644 dev_err(chip->parent, 645 "could not connect irqchip to gpiochip: %d\n", err); 646 return err; 647 } 648 649 gpiochip_set_nested_irqchip(chip, 650 &mcp->irq_chip, 651 mcp->irq); 652 653 return 0; 654 } 655 656 /*----------------------------------------------------------------------*/ 657 658 static int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev, 659 void *data, unsigned addr, unsigned type, 660 unsigned int base, int cs) 661 { 662 int status, ret; 663 bool mirror = false; 664 bool open_drain = false; 665 struct regmap_config *one_regmap_config = NULL; 666 int raw_chip_address = (addr & ~0x40) >> 1; 667 668 mutex_init(&mcp->lock); 669 670 mcp->dev = dev; 671 mcp->addr = addr; 672 mcp->irq_active_high = false; 673 674 mcp->chip.direction_input = mcp23s08_direction_input; 675 mcp->chip.get = mcp23s08_get; 676 mcp->chip.direction_output = mcp23s08_direction_output; 677 mcp->chip.set = mcp23s08_set; 678 #ifdef CONFIG_OF_GPIO 679 mcp->chip.of_gpio_n_cells = 2; 680 mcp->chip.of_node = dev->of_node; 681 #endif 682 683 switch (type) { 684 #ifdef CONFIG_SPI_MASTER 685 case MCP_TYPE_S08: 686 case MCP_TYPE_S17: 687 switch (type) { 688 case MCP_TYPE_S08: 689 one_regmap_config = 690 devm_kmemdup(dev, &mcp23x08_regmap, 691 sizeof(struct regmap_config), GFP_KERNEL); 692 mcp->reg_shift = 0; 693 mcp->chip.ngpio = 8; 694 mcp->chip.label = devm_kasprintf(dev, GFP_KERNEL, 695 "mcp23s08.%d", raw_chip_address); 696 break; 697 case MCP_TYPE_S17: 698 one_regmap_config = 699 devm_kmemdup(dev, &mcp23x17_regmap, 700 sizeof(struct regmap_config), GFP_KERNEL); 701 mcp->reg_shift = 1; 702 mcp->chip.ngpio = 16; 703 mcp->chip.label = devm_kasprintf(dev, GFP_KERNEL, 704 "mcp23s17.%d", raw_chip_address); 705 break; 706 } 707 if (!one_regmap_config) 708 return -ENOMEM; 709 710 one_regmap_config->name = devm_kasprintf(dev, GFP_KERNEL, "%d", raw_chip_address); 711 mcp->regmap = devm_regmap_init(dev, &mcp23sxx_spi_regmap, mcp, 712 one_regmap_config); 713 break; 714 715 case MCP_TYPE_S18: 716 one_regmap_config = 717 devm_kmemdup(dev, &mcp23x17_regmap, 718 sizeof(struct regmap_config), GFP_KERNEL); 719 if (!one_regmap_config) 720 return -ENOMEM; 721 mcp->regmap = devm_regmap_init(dev, &mcp23sxx_spi_regmap, mcp, 722 one_regmap_config); 723 mcp->reg_shift = 1; 724 mcp->chip.ngpio = 16; 725 mcp->chip.label = "mcp23s18"; 726 break; 727 #endif /* CONFIG_SPI_MASTER */ 728 729 #if IS_ENABLED(CONFIG_I2C) 730 case MCP_TYPE_008: 731 mcp->regmap = devm_regmap_init_i2c(data, &mcp23x08_regmap); 732 mcp->reg_shift = 0; 733 mcp->chip.ngpio = 8; 734 mcp->chip.label = "mcp23008"; 735 break; 736 737 case MCP_TYPE_017: 738 mcp->regmap = devm_regmap_init_i2c(data, &mcp23x17_regmap); 739 mcp->reg_shift = 1; 740 mcp->chip.ngpio = 16; 741 mcp->chip.label = "mcp23017"; 742 break; 743 744 case MCP_TYPE_018: 745 mcp->regmap = devm_regmap_init_i2c(data, &mcp23x17_regmap); 746 mcp->reg_shift = 1; 747 mcp->chip.ngpio = 16; 748 mcp->chip.label = "mcp23018"; 749 break; 750 #endif /* CONFIG_I2C */ 751 752 default: 753 dev_err(dev, "invalid device type (%d)\n", type); 754 return -EINVAL; 755 } 756 757 if (IS_ERR(mcp->regmap)) 758 return PTR_ERR(mcp->regmap); 759 760 mcp->chip.base = base; 761 mcp->chip.can_sleep = true; 762 mcp->chip.parent = dev; 763 mcp->chip.owner = THIS_MODULE; 764 765 /* verify MCP_IOCON.SEQOP = 0, so sequential reads work, 766 * and MCP_IOCON.HAEN = 1, so we work with all chips. 767 */ 768 769 ret = mcp_read(mcp, MCP_IOCON, &status); 770 if (ret < 0) 771 goto fail; 772 773 mcp->irq_controller = 774 device_property_read_bool(dev, "interrupt-controller"); 775 if (mcp->irq && mcp->irq_controller) { 776 mcp->irq_active_high = 777 device_property_read_bool(dev, 778 "microchip,irq-active-high"); 779 780 mirror = device_property_read_bool(dev, "microchip,irq-mirror"); 781 open_drain = device_property_read_bool(dev, "drive-open-drain"); 782 } 783 784 if ((status & IOCON_SEQOP) || !(status & IOCON_HAEN) || mirror || 785 mcp->irq_active_high || open_drain) { 786 /* mcp23s17 has IOCON twice, make sure they are in sync */ 787 status &= ~(IOCON_SEQOP | (IOCON_SEQOP << 8)); 788 status |= IOCON_HAEN | (IOCON_HAEN << 8); 789 if (mcp->irq_active_high) 790 status |= IOCON_INTPOL | (IOCON_INTPOL << 8); 791 else 792 status &= ~(IOCON_INTPOL | (IOCON_INTPOL << 8)); 793 794 if (mirror) 795 status |= IOCON_MIRROR | (IOCON_MIRROR << 8); 796 797 if (open_drain) 798 status |= IOCON_ODR | (IOCON_ODR << 8); 799 800 if (type == MCP_TYPE_S18 || type == MCP_TYPE_018) 801 status |= IOCON_INTCC | (IOCON_INTCC << 8); 802 803 ret = mcp_write(mcp, MCP_IOCON, status); 804 if (ret < 0) 805 goto fail; 806 } 807 808 if (mcp->irq && mcp->irq_controller) { 809 ret = mcp23s08_irqchip_setup(mcp); 810 if (ret) 811 goto fail; 812 } 813 814 ret = devm_gpiochip_add_data(dev, &mcp->chip, mcp); 815 if (ret < 0) 816 goto fail; 817 818 if (one_regmap_config) { 819 mcp->pinctrl_desc.name = devm_kasprintf(dev, GFP_KERNEL, 820 "mcp23xxx-pinctrl.%d", raw_chip_address); 821 if (!mcp->pinctrl_desc.name) 822 return -ENOMEM; 823 } else { 824 mcp->pinctrl_desc.name = "mcp23xxx-pinctrl"; 825 } 826 mcp->pinctrl_desc.pctlops = &mcp_pinctrl_ops; 827 mcp->pinctrl_desc.confops = &mcp_pinconf_ops; 828 mcp->pinctrl_desc.npins = mcp->chip.ngpio; 829 if (mcp->pinctrl_desc.npins == 8) 830 mcp->pinctrl_desc.pins = mcp23x08_pins; 831 else if (mcp->pinctrl_desc.npins == 16) 832 mcp->pinctrl_desc.pins = mcp23x17_pins; 833 mcp->pinctrl_desc.owner = THIS_MODULE; 834 835 mcp->pctldev = devm_pinctrl_register(dev, &mcp->pinctrl_desc, mcp); 836 if (IS_ERR(mcp->pctldev)) { 837 ret = PTR_ERR(mcp->pctldev); 838 goto fail; 839 } 840 841 if (mcp->irq) 842 ret = mcp23s08_irq_setup(mcp); 843 844 fail: 845 if (ret < 0) 846 dev_dbg(dev, "can't setup chip %d, --> %d\n", addr, ret); 847 return ret; 848 } 849 850 /*----------------------------------------------------------------------*/ 851 852 #ifdef CONFIG_OF 853 #ifdef CONFIG_SPI_MASTER 854 static const struct of_device_id mcp23s08_spi_of_match[] = { 855 { 856 .compatible = "microchip,mcp23s08", 857 .data = (void *) MCP_TYPE_S08, 858 }, 859 { 860 .compatible = "microchip,mcp23s17", 861 .data = (void *) MCP_TYPE_S17, 862 }, 863 { 864 .compatible = "microchip,mcp23s18", 865 .data = (void *) MCP_TYPE_S18, 866 }, 867 /* NOTE: The use of the mcp prefix is deprecated and will be removed. */ 868 { 869 .compatible = "mcp,mcp23s08", 870 .data = (void *) MCP_TYPE_S08, 871 }, 872 { 873 .compatible = "mcp,mcp23s17", 874 .data = (void *) MCP_TYPE_S17, 875 }, 876 { }, 877 }; 878 MODULE_DEVICE_TABLE(of, mcp23s08_spi_of_match); 879 #endif 880 881 #if IS_ENABLED(CONFIG_I2C) 882 static const struct of_device_id mcp23s08_i2c_of_match[] = { 883 { 884 .compatible = "microchip,mcp23008", 885 .data = (void *) MCP_TYPE_008, 886 }, 887 { 888 .compatible = "microchip,mcp23017", 889 .data = (void *) MCP_TYPE_017, 890 }, 891 { 892 .compatible = "microchip,mcp23018", 893 .data = (void *) MCP_TYPE_018, 894 }, 895 /* NOTE: The use of the mcp prefix is deprecated and will be removed. */ 896 { 897 .compatible = "mcp,mcp23008", 898 .data = (void *) MCP_TYPE_008, 899 }, 900 { 901 .compatible = "mcp,mcp23017", 902 .data = (void *) MCP_TYPE_017, 903 }, 904 { }, 905 }; 906 MODULE_DEVICE_TABLE(of, mcp23s08_i2c_of_match); 907 #endif 908 #endif /* CONFIG_OF */ 909 910 911 #if IS_ENABLED(CONFIG_I2C) 912 913 static int mcp230xx_probe(struct i2c_client *client, 914 const struct i2c_device_id *id) 915 { 916 struct mcp23s08_platform_data *pdata, local_pdata; 917 struct mcp23s08 *mcp; 918 int status; 919 920 pdata = dev_get_platdata(&client->dev); 921 if (!pdata) { 922 pdata = &local_pdata; 923 pdata->base = -1; 924 } 925 926 mcp = devm_kzalloc(&client->dev, sizeof(*mcp), GFP_KERNEL); 927 if (!mcp) 928 return -ENOMEM; 929 930 mcp->irq = client->irq; 931 mcp->irq_chip.name = dev_name(&client->dev); 932 mcp->irq_chip.irq_mask = mcp23s08_irq_mask; 933 mcp->irq_chip.irq_unmask = mcp23s08_irq_unmask; 934 mcp->irq_chip.irq_set_type = mcp23s08_irq_set_type; 935 mcp->irq_chip.irq_bus_lock = mcp23s08_irq_bus_lock; 936 mcp->irq_chip.irq_bus_sync_unlock = mcp23s08_irq_bus_unlock; 937 938 status = mcp23s08_probe_one(mcp, &client->dev, client, client->addr, 939 id->driver_data, pdata->base, 0); 940 if (status) 941 return status; 942 943 i2c_set_clientdata(client, mcp); 944 945 return 0; 946 } 947 948 static const struct i2c_device_id mcp230xx_id[] = { 949 { "mcp23008", MCP_TYPE_008 }, 950 { "mcp23017", MCP_TYPE_017 }, 951 { "mcp23018", MCP_TYPE_018 }, 952 { }, 953 }; 954 MODULE_DEVICE_TABLE(i2c, mcp230xx_id); 955 956 static struct i2c_driver mcp230xx_driver = { 957 .driver = { 958 .name = "mcp230xx", 959 .of_match_table = of_match_ptr(mcp23s08_i2c_of_match), 960 }, 961 .probe = mcp230xx_probe, 962 .id_table = mcp230xx_id, 963 }; 964 965 static int __init mcp23s08_i2c_init(void) 966 { 967 return i2c_add_driver(&mcp230xx_driver); 968 } 969 970 static void mcp23s08_i2c_exit(void) 971 { 972 i2c_del_driver(&mcp230xx_driver); 973 } 974 975 #else 976 977 static int __init mcp23s08_i2c_init(void) { return 0; } 978 static void mcp23s08_i2c_exit(void) { } 979 980 #endif /* CONFIG_I2C */ 981 982 /*----------------------------------------------------------------------*/ 983 984 #ifdef CONFIG_SPI_MASTER 985 986 static int mcp23s08_probe(struct spi_device *spi) 987 { 988 struct mcp23s08_platform_data *pdata, local_pdata; 989 unsigned addr; 990 int chips = 0; 991 struct mcp23s08_driver_data *data; 992 int status, type; 993 unsigned ngpio = 0; 994 const struct of_device_id *match; 995 996 match = of_match_device(of_match_ptr(mcp23s08_spi_of_match), &spi->dev); 997 if (match) 998 type = (int)(uintptr_t)match->data; 999 else 1000 type = spi_get_device_id(spi)->driver_data; 1001 1002 pdata = dev_get_platdata(&spi->dev); 1003 if (!pdata) { 1004 pdata = &local_pdata; 1005 pdata->base = -1; 1006 1007 status = device_property_read_u32(&spi->dev, 1008 "microchip,spi-present-mask", &pdata->spi_present_mask); 1009 if (status) { 1010 status = device_property_read_u32(&spi->dev, 1011 "mcp,spi-present-mask", 1012 &pdata->spi_present_mask); 1013 1014 if (status) { 1015 dev_err(&spi->dev, "missing spi-present-mask"); 1016 return -ENODEV; 1017 } 1018 } 1019 } 1020 1021 if (!pdata->spi_present_mask || pdata->spi_present_mask > 0xff) { 1022 dev_err(&spi->dev, "invalid spi-present-mask"); 1023 return -ENODEV; 1024 } 1025 1026 for (addr = 0; addr < MCP_MAX_DEV_PER_CS; addr++) { 1027 if (pdata->spi_present_mask & BIT(addr)) 1028 chips++; 1029 } 1030 1031 if (!chips) 1032 return -ENODEV; 1033 1034 data = devm_kzalloc(&spi->dev, 1035 struct_size(data, chip, chips), GFP_KERNEL); 1036 if (!data) 1037 return -ENOMEM; 1038 1039 spi_set_drvdata(spi, data); 1040 1041 for (addr = 0; addr < MCP_MAX_DEV_PER_CS; addr++) { 1042 if (!(pdata->spi_present_mask & BIT(addr))) 1043 continue; 1044 chips--; 1045 data->mcp[addr] = &data->chip[chips]; 1046 data->mcp[addr]->irq = spi->irq; 1047 data->mcp[addr]->irq_chip.name = dev_name(&spi->dev); 1048 data->mcp[addr]->irq_chip.irq_mask = mcp23s08_irq_mask; 1049 data->mcp[addr]->irq_chip.irq_unmask = mcp23s08_irq_unmask; 1050 data->mcp[addr]->irq_chip.irq_set_type = mcp23s08_irq_set_type; 1051 data->mcp[addr]->irq_chip.irq_bus_lock = mcp23s08_irq_bus_lock; 1052 data->mcp[addr]->irq_chip.irq_bus_sync_unlock = 1053 mcp23s08_irq_bus_unlock; 1054 status = mcp23s08_probe_one(data->mcp[addr], &spi->dev, spi, 1055 0x40 | (addr << 1), type, 1056 pdata->base, addr); 1057 if (status < 0) 1058 return status; 1059 1060 if (pdata->base != -1) 1061 pdata->base += data->mcp[addr]->chip.ngpio; 1062 ngpio += data->mcp[addr]->chip.ngpio; 1063 } 1064 data->ngpio = ngpio; 1065 1066 return 0; 1067 } 1068 1069 static const struct spi_device_id mcp23s08_ids[] = { 1070 { "mcp23s08", MCP_TYPE_S08 }, 1071 { "mcp23s17", MCP_TYPE_S17 }, 1072 { "mcp23s18", MCP_TYPE_S18 }, 1073 { }, 1074 }; 1075 MODULE_DEVICE_TABLE(spi, mcp23s08_ids); 1076 1077 static struct spi_driver mcp23s08_driver = { 1078 .probe = mcp23s08_probe, 1079 .id_table = mcp23s08_ids, 1080 .driver = { 1081 .name = "mcp23s08", 1082 .of_match_table = of_match_ptr(mcp23s08_spi_of_match), 1083 }, 1084 }; 1085 1086 static int __init mcp23s08_spi_init(void) 1087 { 1088 return spi_register_driver(&mcp23s08_driver); 1089 } 1090 1091 static void mcp23s08_spi_exit(void) 1092 { 1093 spi_unregister_driver(&mcp23s08_driver); 1094 } 1095 1096 #else 1097 1098 static int __init mcp23s08_spi_init(void) { return 0; } 1099 static void mcp23s08_spi_exit(void) { } 1100 1101 #endif /* CONFIG_SPI_MASTER */ 1102 1103 /*----------------------------------------------------------------------*/ 1104 1105 static int __init mcp23s08_init(void) 1106 { 1107 int ret; 1108 1109 ret = mcp23s08_spi_init(); 1110 if (ret) 1111 goto spi_fail; 1112 1113 ret = mcp23s08_i2c_init(); 1114 if (ret) 1115 goto i2c_fail; 1116 1117 return 0; 1118 1119 i2c_fail: 1120 mcp23s08_spi_exit(); 1121 spi_fail: 1122 return ret; 1123 } 1124 /* register after spi/i2c postcore initcall and before 1125 * subsys initcalls that may rely on these GPIOs 1126 */ 1127 subsys_initcall(mcp23s08_init); 1128 1129 static void __exit mcp23s08_exit(void) 1130 { 1131 mcp23s08_spi_exit(); 1132 mcp23s08_i2c_exit(); 1133 } 1134 module_exit(mcp23s08_exit); 1135 1136 MODULE_LICENSE("GPL"); 1137