1 /*
2  * Pinctrl driver for NXP LPC18xx/LPC43xx System Control Unit (SCU)
3  *
4  * Copyright (C) 2015 Joachim Eastwood <manabian@gmail.com>
5  *
6  * This file is licensed under the terms of the GNU General Public
7  * License version 2. This program is licensed "as is" without any
8  * warranty of any kind, whether express or implied.
9  */
10 
11 #include <linux/bitops.h>
12 #include <linux/clk.h>
13 #include <linux/io.h>
14 #include <linux/init.h>
15 #include <linux/of.h>
16 #include <linux/of_device.h>
17 #include <linux/pinctrl/pinctrl.h>
18 #include <linux/pinctrl/pinmux.h>
19 #include <linux/pinctrl/pinconf-generic.h>
20 
21 #include "core.h"
22 #include "pinctrl-utils.h"
23 
24 /* LPC18XX SCU analog function registers */
25 #define LPC18XX_SCU_REG_ENAIO0		0xc88
26 #define LPC18XX_SCU_REG_ENAIO1		0xc8c
27 #define LPC18XX_SCU_REG_ENAIO2		0xc90
28 #define LPC18XX_SCU_REG_ENAIO2_DAC	BIT(0)
29 
30 /* LPC18XX SCU pin register definitions */
31 #define LPC18XX_SCU_PIN_MODE_MASK	0x7
32 #define LPC18XX_SCU_PIN_EPD		BIT(3)
33 #define LPC18XX_SCU_PIN_EPUN		BIT(4)
34 #define LPC18XX_SCU_PIN_EHS		BIT(5)
35 #define LPC18XX_SCU_PIN_EZI		BIT(6)
36 #define LPC18XX_SCU_PIN_ZIF		BIT(7)
37 #define LPC18XX_SCU_PIN_EHD_MASK	0x300
38 #define LPC18XX_SCU_PIN_EHD_POS		8
39 
40 #define LPC18XX_SCU_USB1_EPD		BIT(2)
41 #define LPC18XX_SCU_USB1_EPWR		BIT(4)
42 
43 #define LPC18XX_SCU_I2C0_EFP		BIT(0)
44 #define LPC18XX_SCU_I2C0_EHD		BIT(2)
45 #define LPC18XX_SCU_I2C0_EZI		BIT(3)
46 #define LPC18XX_SCU_I2C0_ZIF		BIT(7)
47 #define LPC18XX_SCU_I2C0_SCL_SHIFT	0
48 #define LPC18XX_SCU_I2C0_SDA_SHIFT	8
49 
50 #define LPC18XX_SCU_FUNC_PER_PIN	8
51 
52 /* LPC18XX SCU pin interrupt select registers */
53 #define LPC18XX_SCU_PINTSEL0		0xe00
54 #define LPC18XX_SCU_PINTSEL1		0xe04
55 #define LPC18XX_SCU_PINTSEL_VAL_MASK	0xff
56 #define LPC18XX_SCU_PINTSEL_PORT_SHIFT	5
57 #define LPC18XX_SCU_IRQ_PER_PINTSEL	4
58 #define LPC18XX_GPIO_PINS_PER_PORT	32
59 #define LPC18XX_GPIO_PIN_INT_MAX	8
60 
61 #define LPC18XX_SCU_PINTSEL_VAL(val, n) \
62 	((val) << (((n) % LPC18XX_SCU_IRQ_PER_PINTSEL) * 8))
63 
64 /* LPC18xx pin types */
65 enum {
66 	TYPE_ND,	/* Normal-drive */
67 	TYPE_HD,	/* High-drive */
68 	TYPE_HS,	/* High-speed */
69 	TYPE_I2C0,
70 	TYPE_USB1,
71 };
72 
73 /* LPC18xx pin functions */
74 enum {
75 	FUNC_R,		/* Reserved */
76 	FUNC_ADC,
77 	FUNC_ADCTRIG,
78 	FUNC_CAN0,
79 	FUNC_CAN1,
80 	FUNC_CGU_OUT,
81 	FUNC_CLKIN,
82 	FUNC_CLKOUT,
83 	FUNC_CTIN,
84 	FUNC_CTOUT,
85 	FUNC_DAC,
86 	FUNC_EMC,
87 	FUNC_EMC_ALT,
88 	FUNC_ENET,
89 	FUNC_ENET_ALT,
90 	FUNC_GPIO,
91 	FUNC_I2C0,
92 	FUNC_I2C1,
93 	FUNC_I2S0_RX_MCLK,
94 	FUNC_I2S0_RX_SCK,
95 	FUNC_I2S0_RX_SDA,
96 	FUNC_I2S0_RX_WS,
97 	FUNC_I2S0_TX_MCLK,
98 	FUNC_I2S0_TX_SCK,
99 	FUNC_I2S0_TX_SDA,
100 	FUNC_I2S0_TX_WS,
101 	FUNC_I2S1,
102 	FUNC_LCD,
103 	FUNC_LCD_ALT,
104 	FUNC_MCTRL,
105 	FUNC_NMI,
106 	FUNC_QEI,
107 	FUNC_SDMMC,
108 	FUNC_SGPIO,
109 	FUNC_SPI,
110 	FUNC_SPIFI,
111 	FUNC_SSP0,
112 	FUNC_SSP0_ALT,
113 	FUNC_SSP1,
114 	FUNC_TIMER0,
115 	FUNC_TIMER1,
116 	FUNC_TIMER2,
117 	FUNC_TIMER3,
118 	FUNC_TRACE,
119 	FUNC_UART0,
120 	FUNC_UART1,
121 	FUNC_UART2,
122 	FUNC_UART3,
123 	FUNC_USB0,
124 	FUNC_USB1,
125 	FUNC_MAX
126 };
127 
128 static const char *const lpc18xx_function_names[] = {
129 	[FUNC_R]		= "reserved",
130 	[FUNC_ADC]		= "adc",
131 	[FUNC_ADCTRIG]		= "adctrig",
132 	[FUNC_CAN0]		= "can0",
133 	[FUNC_CAN1]		= "can1",
134 	[FUNC_CGU_OUT]		= "cgu_out",
135 	[FUNC_CLKIN]		= "clkin",
136 	[FUNC_CLKOUT]		= "clkout",
137 	[FUNC_CTIN]		= "ctin",
138 	[FUNC_CTOUT]		= "ctout",
139 	[FUNC_DAC]		= "dac",
140 	[FUNC_EMC]		= "emc",
141 	[FUNC_EMC_ALT]		= "emc_alt",
142 	[FUNC_ENET]		= "enet",
143 	[FUNC_ENET_ALT]		= "enet_alt",
144 	[FUNC_GPIO]		= "gpio",
145 	[FUNC_I2C0]		= "i2c0",
146 	[FUNC_I2C1]		= "i2c1",
147 	[FUNC_I2S0_RX_MCLK]	= "i2s0_rx_mclk",
148 	[FUNC_I2S0_RX_SCK]	= "i2s0_rx_sck",
149 	[FUNC_I2S0_RX_SDA]	= "i2s0_rx_sda",
150 	[FUNC_I2S0_RX_WS]	= "i2s0_rx_ws",
151 	[FUNC_I2S0_TX_MCLK]	= "i2s0_tx_mclk",
152 	[FUNC_I2S0_TX_SCK]	= "i2s0_tx_sck",
153 	[FUNC_I2S0_TX_SDA]	= "i2s0_tx_sda",
154 	[FUNC_I2S0_TX_WS]	= "i2s0_tx_ws",
155 	[FUNC_I2S1]		= "i2s1",
156 	[FUNC_LCD]		= "lcd",
157 	[FUNC_LCD_ALT]		= "lcd_alt",
158 	[FUNC_MCTRL]		= "mctrl",
159 	[FUNC_NMI]		= "nmi",
160 	[FUNC_QEI]		= "qei",
161 	[FUNC_SDMMC]		= "sdmmc",
162 	[FUNC_SGPIO]		= "sgpio",
163 	[FUNC_SPI]		= "spi",
164 	[FUNC_SPIFI]		= "spifi",
165 	[FUNC_SSP0]		= "ssp0",
166 	[FUNC_SSP0_ALT]		= "ssp0_alt",
167 	[FUNC_SSP1]		= "ssp1",
168 	[FUNC_TIMER0]		= "timer0",
169 	[FUNC_TIMER1]		= "timer1",
170 	[FUNC_TIMER2]		= "timer2",
171 	[FUNC_TIMER3]		= "timer3",
172 	[FUNC_TRACE]		= "trace",
173 	[FUNC_UART0]		= "uart0",
174 	[FUNC_UART1]		= "uart1",
175 	[FUNC_UART2]		= "uart2",
176 	[FUNC_UART3]		= "uart3",
177 	[FUNC_USB0]		= "usb0",
178 	[FUNC_USB1]		= "usb1",
179 };
180 
181 struct lpc18xx_pmx_func {
182 	const char **groups;
183 	unsigned ngroups;
184 };
185 
186 struct lpc18xx_scu_data {
187 	struct pinctrl_dev *pctl;
188 	void __iomem *base;
189 	struct clk *clk;
190 	struct lpc18xx_pmx_func func[FUNC_MAX];
191 };
192 
193 struct lpc18xx_pin_caps {
194 	unsigned int offset;
195 	unsigned char functions[LPC18XX_SCU_FUNC_PER_PIN];
196 	unsigned char analog;
197 	unsigned char type;
198 };
199 
200 /* Analog pins are required to have both bias and input disabled */
201 #define LPC18XX_SCU_ANALOG_PIN_CFG	0x10
202 
203 /* Macros to maniupluate analog member in lpc18xx_pin_caps */
204 #define LPC18XX_ANALOG_PIN		BIT(7)
205 #define LPC18XX_ANALOG_ADC(a)		((a >> 5) & 0x3)
206 #define LPC18XX_ANALOG_BIT_MASK		0x1f
207 #define ADC0				(LPC18XX_ANALOG_PIN | (0x00 << 5))
208 #define ADC1				(LPC18XX_ANALOG_PIN | (0x01 << 5))
209 #define DAC				LPC18XX_ANALOG_PIN
210 
211 #define LPC_P(port, pin, f0, f1, f2, f3, f4, f5, f6, f7, a, t)	\
212 static struct lpc18xx_pin_caps lpc18xx_pin_p##port##_##pin = {	\
213 	.offset = 0x##port * 32 * 4 + pin * 4,			\
214 	.functions = {						\
215 			FUNC_##f0, FUNC_##f1, FUNC_##f2,	\
216 			FUNC_##f3, FUNC_##f4, FUNC_##f5,	\
217 			FUNC_##f6, FUNC_##f7,			\
218 	},							\
219 	.analog = a,						\
220 	.type = TYPE_##t,					\
221 }
222 
223 #define LPC_N(pname, off, f0, f1, f2, f3, f4, f5, f6, f7, a, t)	\
224 static struct lpc18xx_pin_caps lpc18xx_pin_##pname = {		\
225 	.offset = off,						\
226 	.functions = {						\
227 			FUNC_##f0, FUNC_##f1, FUNC_##f2,	\
228 			FUNC_##f3, FUNC_##f4, FUNC_##f5,	\
229 			FUNC_##f6, FUNC_##f7,			\
230 	},							\
231 	.analog = a,						\
232 	.type = TYPE_##t,					\
233 }
234 
235 
236 /* Pinmuxing table taken from data sheet */
237 /*    Pin    FUNC0  FUNC1  FUNC2  FUNC3   FUNC4   FUNC5   FUNC6    FUNC7 ANALOG TYPE */
238 LPC_P(0,0,   GPIO,  SSP1,  ENET,  SGPIO,      R,      R, I2S0_TX_WS,I2S1,     0, ND);
239 LPC_P(0,1,   GPIO,  SSP1,ENET_ALT,SGPIO,      R,      R,   ENET,    I2S1,     0, ND);
240 LPC_P(1,0,   GPIO,  CTIN,   EMC,      R,      R,   SSP0,  SGPIO,       R,     0, ND);
241 LPC_P(1,1,   GPIO, CTOUT,   EMC,  SGPIO,      R,   SSP0,      R,       R,     0, ND);
242 LPC_P(1,2,   GPIO, CTOUT,   EMC,  SGPIO,      R,   SSP0,      R,       R,     0, ND);
243 LPC_P(1,3,   GPIO, CTOUT, SGPIO,    EMC,   USB0,   SSP1,      R,   SDMMC,     0, ND);
244 LPC_P(1,4,   GPIO, CTOUT, SGPIO,    EMC,   USB0,   SSP1,      R,   SDMMC,     0, ND);
245 LPC_P(1,5,   GPIO, CTOUT,     R,    EMC,   USB0,   SSP1,  SGPIO,   SDMMC,     0, ND);
246 LPC_P(1,6,   GPIO,  CTIN,     R,    EMC,      R,      R,  SGPIO,   SDMMC,     0, ND);
247 LPC_P(1,7,   GPIO, UART1, CTOUT,    EMC,   USB0,      R,      R,       R,     0, ND);
248 LPC_P(1,8,   GPIO, UART1, CTOUT,    EMC,      R,      R,      R,   SDMMC,     0, ND);
249 LPC_P(1,9,   GPIO, UART1, CTOUT,    EMC,      R,      R,      R,   SDMMC,     0, ND);
250 LPC_P(1,10,  GPIO, UART1, CTOUT,    EMC,      R,      R,      R,   SDMMC,     0, ND);
251 LPC_P(1,11,  GPIO, UART1, CTOUT,    EMC,      R,      R,      R,   SDMMC,     0, ND);
252 LPC_P(1,12,  GPIO, UART1,     R,    EMC, TIMER0,      R,  SGPIO,   SDMMC,     0, ND);
253 LPC_P(1,13,  GPIO, UART1,     R,    EMC, TIMER0,      R,  SGPIO,   SDMMC,     0, ND);
254 LPC_P(1,14,  GPIO, UART1,     R,    EMC, TIMER0,      R,  SGPIO,       R,     0, ND);
255 LPC_P(1,15,  GPIO, UART2, SGPIO,   ENET, TIMER0,      R,      R,       R,     0, ND);
256 LPC_P(1,16,  GPIO, UART2, SGPIO,ENET_ALT,TIMER0,      R,      R,    ENET,     0, ND);
257 LPC_P(1,17,  GPIO, UART2,     R,   ENET, TIMER0,   CAN1,  SGPIO,       R,     0, HD);
258 LPC_P(1,18,  GPIO, UART2,     R,   ENET, TIMER0,   CAN1,  SGPIO,       R,     0, ND);
259 LPC_P(1,19,  ENET,  SSP1,     R,      R, CLKOUT,      R, I2S0_RX_MCLK,I2S1,   0, ND);
260 LPC_P(1,20,  GPIO,  SSP1,     R,   ENET, TIMER0,      R,  SGPIO,       R,     0, ND);
261 LPC_P(2,0,  SGPIO, UART0,   EMC,   USB0,   GPIO,      R, TIMER3,    ENET,     0, ND);
262 LPC_P(2,1,  SGPIO, UART0,   EMC,   USB0,   GPIO,      R, TIMER3,       R,     0, ND);
263 LPC_P(2,2,  SGPIO, UART0,   EMC,   USB0,   GPIO,   CTIN, TIMER3,       R,     0, ND);
264 LPC_P(2,3,  SGPIO,  I2C1, UART3,   CTIN,   GPIO,      R, TIMER3,    USB0,     0, HD);
265 LPC_P(2,4,  SGPIO,  I2C1, UART3,   CTIN,   GPIO,      R, TIMER3,    USB0,     0, HD);
266 LPC_P(2,5,  SGPIO,  CTIN,  USB1, ADCTRIG,  GPIO,      R, TIMER3,    USB0,     0, HD);
267 LPC_P(2,6,  SGPIO, UART0,   EMC,   USB0,   GPIO,   CTIN, TIMER3,       R,     0, ND);
268 LPC_P(2,7,   GPIO, CTOUT, UART3,    EMC,      R,      R, TIMER3,       R,     0, ND);
269 LPC_P(2,8,  SGPIO, CTOUT, UART3,    EMC,   GPIO,      R,      R,       R,     0, ND);
270 LPC_P(2,9,   GPIO, CTOUT, UART3,    EMC,      R,      R,      R,       R,     0, ND);
271 LPC_P(2,10,  GPIO, CTOUT, UART2,    EMC,      R,      R,      R,       R,     0, ND);
272 LPC_P(2,11,  GPIO, CTOUT, UART2,    EMC,      R,      R,      R,       R,     0, ND);
273 LPC_P(2,12,  GPIO, CTOUT,     R,    EMC,      R,      R,      R,   UART2,     0, ND);
274 LPC_P(2,13,  GPIO,  CTIN,     R,    EMC,      R,      R,      R,   UART2,     0, ND);
275 LPC_P(3,0,  I2S0_RX_SCK, I2S0_RX_MCLK, I2S0_TX_SCK, I2S0_TX_MCLK,SSP0,R,R,R,  0, ND);
276 LPC_P(3,1,  I2S0_TX_WS, I2S0_RX_WS,CAN0,USB1,GPIO,    R,    LCD,       R,     0, ND);
277 LPC_P(3,2,  I2S0_TX_SDA, I2S0_RX_SDA,CAN0,USB1,GPIO,  R,    LCD,      R,      0, ND);
278 LPC_P(3,3,      R,   SPI,  SSP0,  SPIFI, CGU_OUT,R, I2S0_TX_MCLK,  I2S1,      0, HS);
279 LPC_P(3,4,   GPIO,     R,     R,  SPIFI,  UART1, I2S0_TX_WS, I2S1,  LCD,      0, ND);
280 LPC_P(3,5,   GPIO,     R,     R,  SPIFI,  UART1, I2S0_TX_SDA,I2S1,  LCD,      0, ND);
281 LPC_P(3,6,   GPIO,   SPI,  SSP0,  SPIFI,      R,  SSP0_ALT,   R,      R,      0, ND);
282 LPC_P(3,7,      R,   SPI,  SSP0,  SPIFI,   GPIO,  SSP0_ALT,   R,      R,      0, ND);
283 LPC_P(3,8,      R,   SPI,  SSP0,  SPIFI,   GPIO,  SSP0_ALT,   R,      R,      0, ND);
284 LPC_P(4,0,   GPIO, MCTRL,   NMI,      R,      R,    LCD,  UART3,      R,      0, ND);
285 LPC_P(4,1,   GPIO, CTOUT,   LCD,      R,      R, LCD_ALT, UART3,   ENET, ADC0|1, ND);
286 LPC_P(4,2,   GPIO, CTOUT,   LCD,      R,      R, LCD_ALT, UART3,  SGPIO,      0, ND);
287 LPC_P(4,3,   GPIO, CTOUT,   LCD,      R,      R, LCD_ALT, UART3,  SGPIO, ADC0|0, ND);
288 LPC_P(4,4,   GPIO, CTOUT,   LCD,      R,      R, LCD_ALT, UART3,  SGPIO,    DAC, ND);
289 LPC_P(4,5,   GPIO, CTOUT,   LCD,      R,      R,      R,      R,  SGPIO,      0, ND);
290 LPC_P(4,6,   GPIO, CTOUT,   LCD,      R,      R,      R,      R,  SGPIO,      0, ND);
291 LPC_P(4,7,    LCD, CLKIN,     R,      R,      R,      R,   I2S1,I2S0_TX_SCK,  0, ND);
292 LPC_P(4,8,      R,  CTIN,   LCD,      R,   GPIO, LCD_ALT,  CAN1,  SGPIO,      0, ND);
293 LPC_P(4,9,      R,  CTIN,   LCD,      R,   GPIO, LCD_ALT,  CAN1,  SGPIO,      0, ND);
294 LPC_P(4,10,     R,  CTIN,   LCD,      R,   GPIO, LCD_ALT,     R,  SGPIO,      0, ND);
295 LPC_P(5,0,   GPIO, MCTRL,   EMC,      R,  UART1, TIMER1,      R,      R,      0, ND);
296 LPC_P(5,1,   GPIO, MCTRL,   EMC,      R,  UART1, TIMER1,      R,      R,      0, ND);
297 LPC_P(5,2,   GPIO, MCTRL,   EMC,      R,  UART1, TIMER1,      R,      R,      0, ND);
298 LPC_P(5,3,   GPIO, MCTRL,   EMC,      R,  UART1, TIMER1,      R,      R,      0, ND);
299 LPC_P(5,4,   GPIO, MCTRL,   EMC,      R,  UART1, TIMER1,      R,      R,      0, ND);
300 LPC_P(5,5,   GPIO, MCTRL,   EMC,      R,  UART1, TIMER1,      R,      R,      0, ND);
301 LPC_P(5,6,   GPIO, MCTRL,   EMC,      R,  UART1, TIMER1,      R,      R,      0, ND);
302 LPC_P(5,7,   GPIO, MCTRL,   EMC,      R,  UART1, TIMER1,      R,      R,      0, ND);
303 LPC_P(6,0,      R, I2S0_RX_MCLK,R,    R, I2S0_RX_SCK, R,      R,      R,      0, ND);
304 LPC_P(6,1,   GPIO,   EMC, UART0, I2S0_RX_WS,  R, TIMER2,      R,      R,      0, ND);
305 LPC_P(6,2,   GPIO,   EMC, UART0, I2S0_RX_SDA, R, TIMER2,      R,      R,      0, ND);
306 LPC_P(6,3,   GPIO,  USB0, SGPIO,    EMC,      R, TIMER2,      R,      R,      0, ND);
307 LPC_P(6,4,   GPIO,  CTIN, UART0,    EMC,      R,      R,      R,      R,      0, ND);
308 LPC_P(6,5,   GPIO, CTOUT, UART0,    EMC,      R,      R,      R,      R,      0, ND);
309 LPC_P(6,6,   GPIO,   EMC, SGPIO,   USB0,      R, TIMER2,      R,      R,      0, ND);
310 LPC_P(6,7,      R,   EMC, SGPIO,   USB0,   GPIO, TIMER2,      R,      R,      0, ND);
311 LPC_P(6,8,      R,   EMC, SGPIO,   USB0,   GPIO, TIMER2,      R,      R,      0, ND);
312 LPC_P(6,9,   GPIO,     R,     R,    EMC,      R, TIMER2,      R,      R,      0, ND);
313 LPC_P(6,10,  GPIO, MCTRL,     R,    EMC,      R,      R,      R,      R,      0, ND);
314 LPC_P(6,11,  GPIO,     R,     R,    EMC,      R, TIMER2,      R,      R,      0, ND);
315 LPC_P(6,12,  GPIO, CTOUT,     R,    EMC,      R,      R,      R,      R,      0, ND);
316 LPC_P(7,0,   GPIO, CTOUT,     R,    LCD,      R,      R,      R,  SGPIO,      0, ND);
317 LPC_P(7,1,   GPIO, CTOUT,I2S0_TX_WS,LCD,LCD_ALT,      R,  UART2,  SGPIO,      0, ND);
318 LPC_P(7,2,   GPIO, CTIN,I2S0_TX_SDA,LCD,LCD_ALT,      R,  UART2,  SGPIO,      0, ND);
319 LPC_P(7,3,   GPIO, CTIN,      R,    LCD,LCD_ALT,      R,      R,      R,      0, ND);
320 LPC_P(7,4,   GPIO, CTOUT,     R,    LCD,LCD_ALT,  TRACE,      R,      R, ADC0|4, ND);
321 LPC_P(7,5,   GPIO, CTOUT,     R,    LCD,LCD_ALT,  TRACE,      R,      R, ADC0|3, ND);
322 LPC_P(7,6,   GPIO, CTOUT,     R,    LCD,      R,  TRACE,      R,      R,      0, ND);
323 LPC_P(7,7,   GPIO, CTOUT,     R,    LCD,      R,  TRACE,   ENET,  SGPIO, ADC1|6, ND);
324 LPC_P(8,0,   GPIO,  USB0,     R,  MCTRL,  SGPIO,      R,      R, TIMER0,      0, HD);
325 LPC_P(8,1,   GPIO,  USB0,     R,  MCTRL,  SGPIO,      R,      R, TIMER0,      0, HD);
326 LPC_P(8,2,   GPIO,  USB0,     R,  MCTRL,  SGPIO,      R,      R, TIMER0,      0, HD);
327 LPC_P(8,3,   GPIO,  USB1,     R,    LCD, LCD_ALT,     R,      R, TIMER0,      0, ND);
328 LPC_P(8,4,   GPIO,  USB1,     R,    LCD, LCD_ALT,     R,      R, TIMER0,      0, ND);
329 LPC_P(8,5,   GPIO,  USB1,     R,    LCD, LCD_ALT,     R,      R, TIMER0,      0, ND);
330 LPC_P(8,6,   GPIO,  USB1,     R,    LCD, LCD_ALT,     R,      R, TIMER0,      0, ND);
331 LPC_P(8,7,   GPIO,  USB1,     R,    LCD, LCD_ALT,     R,      R, TIMER0,      0, ND);
332 LPC_P(8,8,      R,  USB1,     R,      R,      R,      R,CGU_OUT,   I2S1,      0, ND);
333 LPC_P(9,0,   GPIO, MCTRL,     R,      R,      R,   ENET,  SGPIO,   SSP0,      0, ND);
334 LPC_P(9,1,   GPIO, MCTRL,     R,      R, I2S0_TX_WS,ENET, SGPIO,   SSP0,      0, ND);
335 LPC_P(9,2,   GPIO, MCTRL,     R,      R, I2S0_TX_SDA,ENET,SGPIO,   SSP0,      0, ND);
336 LPC_P(9,3,   GPIO, MCTRL,  USB1,      R,      R,   ENET,  SGPIO,  UART3,      0, ND);
337 LPC_P(9,4,      R, MCTRL,  USB1,      R,   GPIO,   ENET,  SGPIO,  UART3,      0, ND);
338 LPC_P(9,5,      R, MCTRL,  USB1,      R,   GPIO,   ENET,  SGPIO,  UART0,      0, ND);
339 LPC_P(9,6,   GPIO, MCTRL,  USB1,      R,      R,   ENET,  SGPIO,  UART0,      0, ND);
340 LPC_P(a,0,      R,     R,     R,      R,      R,   I2S1, CGU_OUT,     R,      0, ND);
341 LPC_P(a,1,   GPIO,   QEI,     R,  UART2,      R,      R,      R,      R,      0, HD);
342 LPC_P(a,2,   GPIO,   QEI,     R,  UART2,      R,      R,      R,      R,      0, HD);
343 LPC_P(a,3,   GPIO,   QEI,     R,      R,      R,      R,      R,      R,      0, HD);
344 LPC_P(a,4,      R, CTOUT,     R,    EMC,   GPIO,      R,      R,      R,      0, ND);
345 LPC_P(b,0,      R, CTOUT,   LCD,      R,   GPIO,      R,      R,      R,      0, ND);
346 LPC_P(b,1,      R,  USB1,   LCD,      R,   GPIO,  CTOUT,      R,      R,      0, ND);
347 LPC_P(b,2,      R,  USB1,   LCD,      R,   GPIO,  CTOUT,      R,      R,      0, ND);
348 LPC_P(b,3,      R,  USB1,   LCD,      R,   GPIO,  CTOUT,      R,      R,      0, ND);
349 LPC_P(b,4,      R,  USB1,   LCD,      R,   GPIO,   CTIN,      R,      R,      0, ND);
350 LPC_P(b,5,      R,  USB1,   LCD,      R,   GPIO,   CTIN, LCD_ALT,     R,      0, ND);
351 LPC_P(b,6,      R,  USB1,   LCD,      R,   GPIO,   CTIN, LCD_ALT,     R, ADC0|6, ND);
352 LPC_P(c,0,      R,  USB1,     R,   ENET,    LCD,      R,      R,  SDMMC, ADC1|1, ND);
353 LPC_P(c,1,   USB1,     R, UART1,   ENET,   GPIO,      R, TIMER3,  SDMMC,      0, ND);
354 LPC_P(c,2,   USB1,     R, UART1,   ENET,   GPIO,      R,      R,  SDMMC,      0, ND);
355 LPC_P(c,3,   USB1,     R, UART1,   ENET,   GPIO,      R,      R,  SDMMC, ADC1|0, ND);
356 LPC_P(c,4,      R,  USB1,     R,   ENET,   GPIO,      R, TIMER3,  SDMMC,      0, ND);
357 LPC_P(c,5,      R,  USB1,     R,   ENET,   GPIO,      R, TIMER3,  SDMMC,      0, ND);
358 LPC_P(c,6,      R,  USB1,     R,   ENET,   GPIO,      R, TIMER3,  SDMMC,      0, ND);
359 LPC_P(c,7,      R,  USB1,     R,   ENET,   GPIO,      R, TIMER3,  SDMMC,      0, ND);
360 LPC_P(c,8,      R,  USB1,     R,   ENET,   GPIO,      R, TIMER3,  SDMMC,      0, ND);
361 LPC_P(c,9,      R,  USB1,     R,   ENET,   GPIO,      R, TIMER3,  SDMMC,      0, ND);
362 LPC_P(c,10,     R,  USB1, UART1,      R,   GPIO,      R, TIMER3,  SDMMC,      0, ND);
363 LPC_P(c,11,     R,  USB1, UART1,      R,   GPIO,      R,      R,  SDMMC,      0, ND);
364 LPC_P(c,12,     R,     R, UART1,      R,   GPIO,  SGPIO, I2S0_TX_SDA,SDMMC,   0, ND);
365 LPC_P(c,13,     R,     R, UART1,      R,   GPIO,  SGPIO, I2S0_TX_WS, SDMMC,   0, ND);
366 LPC_P(c,14,     R,     R, UART1,      R,   GPIO,  SGPIO,   ENET,  SDMMC,      0, ND);
367 LPC_P(d,0,      R, CTOUT,   EMC,      R,   GPIO,      R,      R,  SGPIO,      0, ND);
368 LPC_P(d,1,      R,     R,   EMC,      R,   GPIO,  SDMMC,      R,  SGPIO,      0, ND);
369 LPC_P(d,2,      R, CTOUT,   EMC,      R,   GPIO,      R,      R,  SGPIO,      0, ND);
370 LPC_P(d,3,      R, CTOUT,   EMC,      R,   GPIO,      R,      R,  SGPIO,      0, ND);
371 LPC_P(d,4,      R, CTOUT,   EMC,      R,   GPIO,      R,      R,  SGPIO,      0, ND);
372 LPC_P(d,5,      R, CTOUT,   EMC,      R,   GPIO,      R,      R,  SGPIO,      0, ND);
373 LPC_P(d,6,      R, CTOUT,   EMC,      R,   GPIO,      R,      R,  SGPIO,      0, ND);
374 LPC_P(d,7,      R,  CTIN,   EMC,      R,   GPIO,      R,      R,  SGPIO,      0, ND);
375 LPC_P(d,8,      R,  CTIN,   EMC,      R,   GPIO,      R,      R,  SGPIO,      0, ND);
376 LPC_P(d,9,      R, CTOUT,   EMC,      R,   GPIO,      R,      R,  SGPIO,      0, ND);
377 LPC_P(d,10,     R,  CTIN,   EMC,      R,   GPIO,      R,      R,      R,      0, ND);
378 LPC_P(d,11,     R,     R,   EMC,      R,   GPIO,   USB1,  CTOUT,      R,      0, ND);
379 LPC_P(d,12,     R,     R,   EMC,      R,   GPIO,      R,  CTOUT,      R,      0, ND);
380 LPC_P(d,13,     R,  CTIN,   EMC,      R,   GPIO,      R,  CTOUT,      R,      0, ND);
381 LPC_P(d,14,     R,     R,   EMC,      R,   GPIO,      R,  CTOUT,      R,      0, ND);
382 LPC_P(d,15,     R,     R,   EMC,      R,   GPIO,  SDMMC,  CTOUT,      R,      0, ND);
383 LPC_P(d,16,     R,     R,   EMC,      R,   GPIO,  SDMMC,  CTOUT,      R,      0, ND);
384 LPC_P(e,0,      R,     R,     R,    EMC,   GPIO,   CAN1,      R,      R,      0, ND);
385 LPC_P(e,1,      R,     R,     R,    EMC,   GPIO,   CAN1,      R,      R,      0, ND);
386 LPC_P(e,2,ADCTRIG,  CAN0,     R,    EMC,   GPIO,      R,      R,      R,      0, ND);
387 LPC_P(e,3,      R,  CAN0,ADCTRIG,   EMC,   GPIO,      R,      R,      R,      0, ND);
388 LPC_P(e,4,      R,   NMI,     R,    EMC,   GPIO,      R,      R,      R,      0, ND);
389 LPC_P(e,5,      R, CTOUT, UART1,    EMC,   GPIO,      R,      R,      R,      0, ND);
390 LPC_P(e,6,      R, CTOUT, UART1,    EMC,   GPIO,      R,      R,      R,      0, ND);
391 LPC_P(e,7,      R, CTOUT, UART1,    EMC,   GPIO,      R,      R,      R,      0, ND);
392 LPC_P(e,8,      R, CTOUT, UART1,    EMC,   GPIO,      R,      R,      R,      0, ND);
393 LPC_P(e,9,      R,  CTIN, UART1,    EMC,   GPIO,      R,      R,      R,      0, ND);
394 LPC_P(e,10,     R,  CTIN, UART1,    EMC,   GPIO,      R,      R,      R,      0, ND);
395 LPC_P(e,11,     R, CTOUT, UART1,    EMC,   GPIO,      R,      R,      R,      0, ND);
396 LPC_P(e,12,     R, CTOUT, UART1,    EMC,   GPIO,      R,      R,      R,      0, ND);
397 LPC_P(e,13,     R, CTOUT,  I2C1,    EMC,   GPIO,      R,      R,      R,      0, ND);
398 LPC_P(e,14,     R,     R,     R,    EMC,   GPIO,      R,      R,      R,      0, ND);
399 LPC_P(e,15,     R, CTOUT,  I2C1,    EMC,   GPIO,      R,      R,      R,      0, ND);
400 LPC_P(f,0,   SSP0, CLKIN,     R,      R,      R,      R,      R,   I2S1,      0, ND);
401 LPC_P(f,1,      R,     R,  SSP0,      R,   GPIO,      R,  SGPIO,      R,      0, ND);
402 LPC_P(f,2,      R, UART3,  SSP0,      R,   GPIO,      R,  SGPIO,      R,      0, ND);
403 LPC_P(f,3,      R, UART3,  SSP0,      R,   GPIO,      R,  SGPIO,      R,      0, ND);
404 LPC_P(f,4,   SSP1, CLKIN, TRACE,      R,      R, R, I2S0_TX_MCLK,I2S0_RX_SCK, 0, ND);
405 LPC_P(f,5,      R, UART3,  SSP1,  TRACE,   GPIO,      R,  SGPIO,      R, ADC1|4, ND);
406 LPC_P(f,6,      R, UART3,  SSP1,  TRACE,   GPIO,      R,  SGPIO,   I2S1, ADC1|3, ND);
407 LPC_P(f,7,      R, UART3,  SSP1,  TRACE,   GPIO,      R,  SGPIO,   I2S1, ADC1|7, ND);
408 LPC_P(f,8,      R, UART0,  CTIN,  TRACE,   GPIO,      R,  SGPIO,      R, ADC0|2, ND);
409 LPC_P(f,9,      R, UART0, CTOUT,      R,   GPIO,      R,  SGPIO,      R, ADC1|2, ND);
410 LPC_P(f,10,     R, UART0,     R,      R,   GPIO,      R,  SDMMC,      R, ADC0|5, ND);
411 LPC_P(f,11,     R, UART0,     R,      R,   GPIO,      R,  SDMMC,      R, ADC1|5, ND);
412 
413 /*    Pin      Offset FUNC0  FUNC1  FUNC2  FUNC3  FUNC4    FUNC5   FUNC6      FUNC7 ANALOG TYPE */
414 LPC_N(clk0,     0xc00, EMC, CLKOUT,   R,     R,  SDMMC,   EMC_ALT,  SSP1,      ENET,  0, HS);
415 LPC_N(clk1,     0xc04, EMC, CLKOUT,   R,     R,      R,   CGU_OUT,   R,        I2S1,  0, HS);
416 LPC_N(clk2,     0xc08, EMC, CLKOUT,   R,     R,  SDMMC,   EMC_ALT,I2S0_TX_MCLK,I2S1,  0, HS);
417 LPC_N(clk3,     0xc0c, EMC, CLKOUT,   R,     R,      R,   CGU_OUT,   R,        I2S1,  0, HS);
418 LPC_N(usb1_dm,  0xc80, R,      R,     R,     R,      R,      R,      R,          R,   0, USB1);
419 LPC_N(usb1_dp,  0xc80, R,      R,     R,     R,      R,      R,      R,          R,   0, USB1);
420 LPC_N(i2c0_scl, 0xc84, R,      R,     R,     R,      R,      R,      R,          R,   0, I2C0);
421 LPC_N(i2c0_sda, 0xc84, R,      R,     R,     R,      R,      R,      R,          R,   0, I2C0);
422 
423 #define LPC18XX_PIN_P(port, pin) {			\
424 	.number = 0x##port * 32 + pin,			\
425 	.name = "p"#port"_"#pin,			\
426 	.drv_data = &lpc18xx_pin_p##port##_##pin 	\
427 }
428 
429 /* Pin numbers for special pins */
430 enum {
431 	PIN_CLK0 = 600,
432 	PIN_CLK1,
433 	PIN_CLK2,
434 	PIN_CLK3,
435 	PIN_USB1_DM,
436 	PIN_USB1_DP,
437 	PIN_I2C0_SCL,
438 	PIN_I2C0_SDA,
439 };
440 
441 #define LPC18XX_PIN(pname, n) {				\
442 	.number = n,					\
443 	.name = #pname,					\
444 	.drv_data = &lpc18xx_pin_##pname 		\
445 }
446 
447 static const struct pinctrl_pin_desc lpc18xx_pins[] = {
448 	LPC18XX_PIN_P(0,0),
449 	LPC18XX_PIN_P(0,1),
450 	LPC18XX_PIN_P(1,0),
451 	LPC18XX_PIN_P(1,1),
452 	LPC18XX_PIN_P(1,2),
453 	LPC18XX_PIN_P(1,3),
454 	LPC18XX_PIN_P(1,4),
455 	LPC18XX_PIN_P(1,5),
456 	LPC18XX_PIN_P(1,6),
457 	LPC18XX_PIN_P(1,7),
458 	LPC18XX_PIN_P(1,8),
459 	LPC18XX_PIN_P(1,9),
460 	LPC18XX_PIN_P(1,10),
461 	LPC18XX_PIN_P(1,11),
462 	LPC18XX_PIN_P(1,12),
463 	LPC18XX_PIN_P(1,13),
464 	LPC18XX_PIN_P(1,14),
465 	LPC18XX_PIN_P(1,15),
466 	LPC18XX_PIN_P(1,16),
467 	LPC18XX_PIN_P(1,17),
468 	LPC18XX_PIN_P(1,18),
469 	LPC18XX_PIN_P(1,19),
470 	LPC18XX_PIN_P(1,20),
471 	LPC18XX_PIN_P(2,0),
472 	LPC18XX_PIN_P(2,1),
473 	LPC18XX_PIN_P(2,2),
474 	LPC18XX_PIN_P(2,3),
475 	LPC18XX_PIN_P(2,4),
476 	LPC18XX_PIN_P(2,5),
477 	LPC18XX_PIN_P(2,6),
478 	LPC18XX_PIN_P(2,7),
479 	LPC18XX_PIN_P(2,8),
480 	LPC18XX_PIN_P(2,9),
481 	LPC18XX_PIN_P(2,10),
482 	LPC18XX_PIN_P(2,11),
483 	LPC18XX_PIN_P(2,12),
484 	LPC18XX_PIN_P(2,13),
485 	LPC18XX_PIN_P(3,0),
486 	LPC18XX_PIN_P(3,1),
487 	LPC18XX_PIN_P(3,2),
488 	LPC18XX_PIN_P(3,3),
489 	LPC18XX_PIN_P(3,4),
490 	LPC18XX_PIN_P(3,5),
491 	LPC18XX_PIN_P(3,6),
492 	LPC18XX_PIN_P(3,7),
493 	LPC18XX_PIN_P(3,8),
494 	LPC18XX_PIN_P(4,0),
495 	LPC18XX_PIN_P(4,1),
496 	LPC18XX_PIN_P(4,2),
497 	LPC18XX_PIN_P(4,3),
498 	LPC18XX_PIN_P(4,4),
499 	LPC18XX_PIN_P(4,5),
500 	LPC18XX_PIN_P(4,6),
501 	LPC18XX_PIN_P(4,7),
502 	LPC18XX_PIN_P(4,8),
503 	LPC18XX_PIN_P(4,9),
504 	LPC18XX_PIN_P(4,10),
505 	LPC18XX_PIN_P(5,0),
506 	LPC18XX_PIN_P(5,1),
507 	LPC18XX_PIN_P(5,2),
508 	LPC18XX_PIN_P(5,3),
509 	LPC18XX_PIN_P(5,4),
510 	LPC18XX_PIN_P(5,5),
511 	LPC18XX_PIN_P(5,6),
512 	LPC18XX_PIN_P(5,7),
513 	LPC18XX_PIN_P(6,0),
514 	LPC18XX_PIN_P(6,1),
515 	LPC18XX_PIN_P(6,2),
516 	LPC18XX_PIN_P(6,3),
517 	LPC18XX_PIN_P(6,4),
518 	LPC18XX_PIN_P(6,5),
519 	LPC18XX_PIN_P(6,6),
520 	LPC18XX_PIN_P(6,7),
521 	LPC18XX_PIN_P(6,8),
522 	LPC18XX_PIN_P(6,9),
523 	LPC18XX_PIN_P(6,10),
524 	LPC18XX_PIN_P(6,11),
525 	LPC18XX_PIN_P(6,12),
526 	LPC18XX_PIN_P(7,0),
527 	LPC18XX_PIN_P(7,1),
528 	LPC18XX_PIN_P(7,2),
529 	LPC18XX_PIN_P(7,3),
530 	LPC18XX_PIN_P(7,4),
531 	LPC18XX_PIN_P(7,5),
532 	LPC18XX_PIN_P(7,6),
533 	LPC18XX_PIN_P(7,7),
534 	LPC18XX_PIN_P(8,0),
535 	LPC18XX_PIN_P(8,1),
536 	LPC18XX_PIN_P(8,2),
537 	LPC18XX_PIN_P(8,3),
538 	LPC18XX_PIN_P(8,4),
539 	LPC18XX_PIN_P(8,5),
540 	LPC18XX_PIN_P(8,6),
541 	LPC18XX_PIN_P(8,7),
542 	LPC18XX_PIN_P(8,8),
543 	LPC18XX_PIN_P(9,0),
544 	LPC18XX_PIN_P(9,1),
545 	LPC18XX_PIN_P(9,2),
546 	LPC18XX_PIN_P(9,3),
547 	LPC18XX_PIN_P(9,4),
548 	LPC18XX_PIN_P(9,5),
549 	LPC18XX_PIN_P(9,6),
550 	LPC18XX_PIN_P(a,0),
551 	LPC18XX_PIN_P(a,1),
552 	LPC18XX_PIN_P(a,2),
553 	LPC18XX_PIN_P(a,3),
554 	LPC18XX_PIN_P(a,4),
555 	LPC18XX_PIN_P(b,0),
556 	LPC18XX_PIN_P(b,1),
557 	LPC18XX_PIN_P(b,2),
558 	LPC18XX_PIN_P(b,3),
559 	LPC18XX_PIN_P(b,4),
560 	LPC18XX_PIN_P(b,5),
561 	LPC18XX_PIN_P(b,6),
562 	LPC18XX_PIN_P(c,0),
563 	LPC18XX_PIN_P(c,1),
564 	LPC18XX_PIN_P(c,2),
565 	LPC18XX_PIN_P(c,3),
566 	LPC18XX_PIN_P(c,4),
567 	LPC18XX_PIN_P(c,5),
568 	LPC18XX_PIN_P(c,6),
569 	LPC18XX_PIN_P(c,7),
570 	LPC18XX_PIN_P(c,8),
571 	LPC18XX_PIN_P(c,9),
572 	LPC18XX_PIN_P(c,10),
573 	LPC18XX_PIN_P(c,11),
574 	LPC18XX_PIN_P(c,12),
575 	LPC18XX_PIN_P(c,13),
576 	LPC18XX_PIN_P(c,14),
577 	LPC18XX_PIN_P(d,0),
578 	LPC18XX_PIN_P(d,1),
579 	LPC18XX_PIN_P(d,2),
580 	LPC18XX_PIN_P(d,3),
581 	LPC18XX_PIN_P(d,4),
582 	LPC18XX_PIN_P(d,5),
583 	LPC18XX_PIN_P(d,6),
584 	LPC18XX_PIN_P(d,7),
585 	LPC18XX_PIN_P(d,8),
586 	LPC18XX_PIN_P(d,9),
587 	LPC18XX_PIN_P(d,10),
588 	LPC18XX_PIN_P(d,11),
589 	LPC18XX_PIN_P(d,12),
590 	LPC18XX_PIN_P(d,13),
591 	LPC18XX_PIN_P(d,14),
592 	LPC18XX_PIN_P(d,15),
593 	LPC18XX_PIN_P(d,16),
594 	LPC18XX_PIN_P(e,0),
595 	LPC18XX_PIN_P(e,1),
596 	LPC18XX_PIN_P(e,2),
597 	LPC18XX_PIN_P(e,3),
598 	LPC18XX_PIN_P(e,4),
599 	LPC18XX_PIN_P(e,5),
600 	LPC18XX_PIN_P(e,6),
601 	LPC18XX_PIN_P(e,7),
602 	LPC18XX_PIN_P(e,8),
603 	LPC18XX_PIN_P(e,9),
604 	LPC18XX_PIN_P(e,10),
605 	LPC18XX_PIN_P(e,11),
606 	LPC18XX_PIN_P(e,12),
607 	LPC18XX_PIN_P(e,13),
608 	LPC18XX_PIN_P(e,14),
609 	LPC18XX_PIN_P(e,15),
610 	LPC18XX_PIN_P(f,0),
611 	LPC18XX_PIN_P(f,1),
612 	LPC18XX_PIN_P(f,2),
613 	LPC18XX_PIN_P(f,3),
614 	LPC18XX_PIN_P(f,4),
615 	LPC18XX_PIN_P(f,5),
616 	LPC18XX_PIN_P(f,6),
617 	LPC18XX_PIN_P(f,7),
618 	LPC18XX_PIN_P(f,8),
619 	LPC18XX_PIN_P(f,9),
620 	LPC18XX_PIN_P(f,10),
621 	LPC18XX_PIN_P(f,11),
622 
623 	LPC18XX_PIN(clk0, PIN_CLK0),
624 	LPC18XX_PIN(clk1, PIN_CLK1),
625 	LPC18XX_PIN(clk2, PIN_CLK2),
626 	LPC18XX_PIN(clk3, PIN_CLK3),
627 	LPC18XX_PIN(usb1_dm,  PIN_USB1_DM),
628 	LPC18XX_PIN(usb1_dp,  PIN_USB1_DP),
629 	LPC18XX_PIN(i2c0_scl, PIN_I2C0_SCL),
630 	LPC18XX_PIN(i2c0_sda, PIN_I2C0_SDA),
631 };
632 
633 /* PIN_CONFIG_GPIO_PIN_INT: route gpio to the gpio pin interrupt controller */
634 #define PIN_CONFIG_GPIO_PIN_INT		(PIN_CONFIG_END + 1)
635 
636 static const struct pinconf_generic_params lpc18xx_params[] = {
637 	{"nxp,gpio-pin-interrupt", PIN_CONFIG_GPIO_PIN_INT, 0},
638 };
639 
640 #ifdef CONFIG_DEBUG_FS
641 static const struct pin_config_item lpc18xx_conf_items[ARRAY_SIZE(lpc18xx_params)] = {
642 	PCONFDUMP(PIN_CONFIG_GPIO_PIN_INT, "gpio pin int", NULL, true),
643 };
644 #endif
645 
646 static int lpc18xx_pconf_get_usb1(enum pin_config_param param, int *arg, u32 reg)
647 {
648 	switch (param) {
649 	case PIN_CONFIG_LOW_POWER_MODE:
650 		if (reg & LPC18XX_SCU_USB1_EPWR)
651 			*arg = 0;
652 		else
653 			*arg = 1;
654 		break;
655 
656 	case PIN_CONFIG_BIAS_DISABLE:
657 		if (reg & LPC18XX_SCU_USB1_EPD)
658 			return -EINVAL;
659 		break;
660 
661 	case PIN_CONFIG_BIAS_PULL_DOWN:
662 		if (reg & LPC18XX_SCU_USB1_EPD)
663 			*arg = 1;
664 		else
665 			return -EINVAL;
666 		break;
667 
668 	default:
669 		return -ENOTSUPP;
670 	}
671 
672 	return 0;
673 }
674 
675 static int lpc18xx_pconf_get_i2c0(enum pin_config_param param, int *arg, u32 reg,
676 				  unsigned pin)
677 {
678 	u8 shift;
679 
680 	if (pin == PIN_I2C0_SCL)
681 		shift = LPC18XX_SCU_I2C0_SCL_SHIFT;
682 	else
683 		shift = LPC18XX_SCU_I2C0_SDA_SHIFT;
684 
685 	switch (param) {
686 	case PIN_CONFIG_INPUT_ENABLE:
687 		if (reg & (LPC18XX_SCU_I2C0_EZI << shift))
688 			*arg = 1;
689 		else
690 			return -EINVAL;
691 		break;
692 
693 	case PIN_CONFIG_SLEW_RATE:
694 		if (reg & (LPC18XX_SCU_I2C0_EHD << shift))
695 			*arg = 1;
696 		else
697 			*arg = 0;
698 		break;
699 
700 	case PIN_CONFIG_INPUT_SCHMITT:
701 		if (reg & (LPC18XX_SCU_I2C0_EFP << shift))
702 			*arg = 3;
703 		else
704 			*arg = 50;
705 		break;
706 
707 	case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
708 		if (reg & (LPC18XX_SCU_I2C0_ZIF << shift))
709 			return -EINVAL;
710 		else
711 			*arg = 1;
712 		break;
713 
714 	default:
715 		return -ENOTSUPP;
716 	}
717 
718 	return 0;
719 }
720 
721 static int lpc18xx_pin_to_gpio(struct pinctrl_dev *pctldev, unsigned pin)
722 {
723 	struct pinctrl_gpio_range *range;
724 
725 	range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin);
726 	if (!range)
727 		return -EINVAL;
728 
729 	return pin - range->pin_base + range->base;
730 }
731 
732 static int lpc18xx_get_pintsel(void __iomem *addr, u32 val, int *arg)
733 {
734 	u32 reg_val;
735 	int i;
736 
737 	reg_val = readl(addr);
738 	for (i = 0; i < LPC18XX_SCU_IRQ_PER_PINTSEL; i++) {
739 		if ((reg_val & LPC18XX_SCU_PINTSEL_VAL_MASK) == val)
740 			return 0;
741 
742 		reg_val >>= BITS_PER_BYTE;
743 		*arg += 1;
744 	}
745 
746 	return -EINVAL;
747 }
748 
749 static u32 lpc18xx_gpio_to_pintsel_val(int gpio)
750 {
751 	unsigned int gpio_port, gpio_pin;
752 
753 	gpio_port = gpio / LPC18XX_GPIO_PINS_PER_PORT;
754 	gpio_pin  = gpio % LPC18XX_GPIO_PINS_PER_PORT;
755 
756 	return gpio_pin | (gpio_port << LPC18XX_SCU_PINTSEL_PORT_SHIFT);
757 }
758 
759 static int lpc18xx_pconf_get_gpio_pin_int(struct pinctrl_dev *pctldev,
760 					  int *arg, unsigned pin)
761 {
762 	struct lpc18xx_scu_data *scu = pinctrl_dev_get_drvdata(pctldev);
763 	int gpio, ret;
764 	u32 val;
765 
766 	gpio = lpc18xx_pin_to_gpio(pctldev, pin);
767 	if (gpio < 0)
768 		return -ENOTSUPP;
769 
770 	val = lpc18xx_gpio_to_pintsel_val(gpio);
771 
772 	/*
773 	 * Check if this pin has been enabled as a interrupt in any of the two
774 	 * PINTSEL registers. *arg indicates which interrupt number (0-7).
775 	 */
776 	*arg = 0;
777 	ret = lpc18xx_get_pintsel(scu->base + LPC18XX_SCU_PINTSEL0, val, arg);
778 	if (ret == 0)
779 		return ret;
780 
781 	return lpc18xx_get_pintsel(scu->base + LPC18XX_SCU_PINTSEL1, val, arg);
782 }
783 
784 static int lpc18xx_pconf_get_pin(struct pinctrl_dev *pctldev, unsigned param,
785 				 int *arg, u32 reg, unsigned pin,
786 				 struct lpc18xx_pin_caps *pin_cap)
787 {
788 	switch (param) {
789 	case PIN_CONFIG_BIAS_DISABLE:
790 		if ((!(reg & LPC18XX_SCU_PIN_EPD)) && (reg & LPC18XX_SCU_PIN_EPUN))
791 			;
792 		else
793 			return -EINVAL;
794 		break;
795 
796 	case PIN_CONFIG_BIAS_PULL_UP:
797 		if (reg & LPC18XX_SCU_PIN_EPUN)
798 			return -EINVAL;
799 		else
800 			*arg = 1;
801 		break;
802 
803 	case PIN_CONFIG_BIAS_PULL_DOWN:
804 		if (reg & LPC18XX_SCU_PIN_EPD)
805 			*arg = 1;
806 		else
807 			return -EINVAL;
808 		break;
809 
810 	case PIN_CONFIG_INPUT_ENABLE:
811 		if (reg & LPC18XX_SCU_PIN_EZI)
812 			*arg = 1;
813 		else
814 			return -EINVAL;
815 		break;
816 
817 	case PIN_CONFIG_SLEW_RATE:
818 		if (pin_cap->type == TYPE_HD)
819 			return -ENOTSUPP;
820 
821 		if (reg & LPC18XX_SCU_PIN_EHS)
822 			*arg = 1;
823 		else
824 			*arg = 0;
825 		break;
826 
827 	case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
828 		if (reg & LPC18XX_SCU_PIN_ZIF)
829 			return -EINVAL;
830 		else
831 			*arg = 1;
832 		break;
833 
834 	case PIN_CONFIG_DRIVE_STRENGTH:
835 		if (pin_cap->type != TYPE_HD)
836 			return -ENOTSUPP;
837 
838 		*arg = (reg & LPC18XX_SCU_PIN_EHD_MASK) >> LPC18XX_SCU_PIN_EHD_POS;
839 		switch (*arg) {
840 		case 3: *arg += 5;
841 			fallthrough;
842 		case 2: *arg += 5;
843 			fallthrough;
844 		case 1: *arg += 3;
845 			fallthrough;
846 		case 0: *arg += 4;
847 		}
848 		break;
849 
850 	case PIN_CONFIG_GPIO_PIN_INT:
851 		return lpc18xx_pconf_get_gpio_pin_int(pctldev, arg, pin);
852 
853 	default:
854 		return -ENOTSUPP;
855 	}
856 
857 	return 0;
858 }
859 
860 static struct lpc18xx_pin_caps *lpc18xx_get_pin_caps(unsigned pin)
861 {
862 	int i;
863 
864 	for (i = 0; i < ARRAY_SIZE(lpc18xx_pins); i++) {
865 		if (lpc18xx_pins[i].number == pin)
866 			return lpc18xx_pins[i].drv_data;
867 	}
868 
869 	return NULL;
870 }
871 
872 static int lpc18xx_pconf_get(struct pinctrl_dev *pctldev, unsigned pin,
873 			     unsigned long *config)
874 {
875 	struct lpc18xx_scu_data *scu = pinctrl_dev_get_drvdata(pctldev);
876 	enum pin_config_param param = pinconf_to_config_param(*config);
877 	struct lpc18xx_pin_caps *pin_cap;
878 	int ret, arg = 0;
879 	u32 reg;
880 
881 	pin_cap = lpc18xx_get_pin_caps(pin);
882 	if (!pin_cap)
883 		return -EINVAL;
884 
885 	reg = readl(scu->base + pin_cap->offset);
886 
887 	if (pin_cap->type == TYPE_I2C0)
888 		ret = lpc18xx_pconf_get_i2c0(param, &arg, reg, pin);
889 	else if (pin_cap->type == TYPE_USB1)
890 		ret = lpc18xx_pconf_get_usb1(param, &arg, reg);
891 	else
892 		ret = lpc18xx_pconf_get_pin(pctldev, param, &arg, reg, pin, pin_cap);
893 
894 	if (ret < 0)
895 		return ret;
896 
897 	*config = pinconf_to_config_packed(param, (u16)arg);
898 
899 	return 0;
900 }
901 
902 static int lpc18xx_pconf_set_usb1(struct pinctrl_dev *pctldev,
903 				  enum pin_config_param param,
904 				  u32 param_val, u32 *reg)
905 {
906 	switch (param) {
907 	case PIN_CONFIG_LOW_POWER_MODE:
908 		if (param_val)
909 			*reg &= ~LPC18XX_SCU_USB1_EPWR;
910 		else
911 			*reg |= LPC18XX_SCU_USB1_EPWR;
912 		break;
913 
914 	case PIN_CONFIG_BIAS_DISABLE:
915 		*reg &= ~LPC18XX_SCU_USB1_EPD;
916 		break;
917 
918 	case PIN_CONFIG_BIAS_PULL_DOWN:
919 		*reg |= LPC18XX_SCU_USB1_EPD;
920 		break;
921 
922 	default:
923 		dev_err(pctldev->dev, "Property not supported\n");
924 		return -ENOTSUPP;
925 	}
926 
927 	return 0;
928 }
929 
930 static int lpc18xx_pconf_set_i2c0(struct pinctrl_dev *pctldev,
931 				  enum pin_config_param param,
932 				  u32 param_val, u32 *reg,
933 				  unsigned pin)
934 {
935 	u8 shift;
936 
937 	if (pin == PIN_I2C0_SCL)
938 		shift = LPC18XX_SCU_I2C0_SCL_SHIFT;
939 	else
940 		shift = LPC18XX_SCU_I2C0_SDA_SHIFT;
941 
942 	switch (param) {
943 	case PIN_CONFIG_INPUT_ENABLE:
944 		if (param_val)
945 			*reg |= (LPC18XX_SCU_I2C0_EZI << shift);
946 		else
947 			*reg &= ~(LPC18XX_SCU_I2C0_EZI << shift);
948 		break;
949 
950 	case PIN_CONFIG_SLEW_RATE:
951 		if (param_val)
952 			*reg |= (LPC18XX_SCU_I2C0_EHD << shift);
953 		else
954 			*reg &= ~(LPC18XX_SCU_I2C0_EHD << shift);
955 		break;
956 
957 	case PIN_CONFIG_INPUT_SCHMITT:
958 		if (param_val == 3)
959 			*reg |= (LPC18XX_SCU_I2C0_EFP << shift);
960 		else if (param_val == 50)
961 			*reg &= ~(LPC18XX_SCU_I2C0_EFP << shift);
962 		else
963 			return -ENOTSUPP;
964 		break;
965 
966 	case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
967 		if (param_val)
968 			*reg &= ~(LPC18XX_SCU_I2C0_ZIF << shift);
969 		else
970 			*reg |= (LPC18XX_SCU_I2C0_ZIF << shift);
971 		break;
972 
973 	default:
974 		dev_err(pctldev->dev, "Property not supported\n");
975 		return -ENOTSUPP;
976 	}
977 
978 	return 0;
979 }
980 
981 static int lpc18xx_pconf_set_gpio_pin_int(struct pinctrl_dev *pctldev,
982 					  u32 param_val, unsigned pin)
983 {
984 	struct lpc18xx_scu_data *scu = pinctrl_dev_get_drvdata(pctldev);
985 	u32 val, reg_val, reg_offset = LPC18XX_SCU_PINTSEL0;
986 	int gpio;
987 
988 	if (param_val >= LPC18XX_GPIO_PIN_INT_MAX)
989 		return -EINVAL;
990 
991 	gpio = lpc18xx_pin_to_gpio(pctldev, pin);
992 	if (gpio < 0)
993 		return -ENOTSUPP;
994 
995 	val = lpc18xx_gpio_to_pintsel_val(gpio);
996 
997 	reg_offset += (param_val / LPC18XX_SCU_IRQ_PER_PINTSEL) * sizeof(u32);
998 
999 	reg_val = readl(scu->base + reg_offset);
1000 	reg_val &= ~LPC18XX_SCU_PINTSEL_VAL(LPC18XX_SCU_PINTSEL_VAL_MASK, param_val);
1001 	reg_val |= LPC18XX_SCU_PINTSEL_VAL(val, param_val);
1002 	writel(reg_val, scu->base + reg_offset);
1003 
1004 	return 0;
1005 }
1006 
1007 static int lpc18xx_pconf_set_pin(struct pinctrl_dev *pctldev, unsigned param,
1008 				 u32 param_val, u32 *reg, unsigned pin,
1009 				 struct lpc18xx_pin_caps *pin_cap)
1010 {
1011 	switch (param) {
1012 	case PIN_CONFIG_BIAS_DISABLE:
1013 		*reg &= ~LPC18XX_SCU_PIN_EPD;
1014 		*reg |= LPC18XX_SCU_PIN_EPUN;
1015 		break;
1016 
1017 	case PIN_CONFIG_BIAS_PULL_UP:
1018 		*reg &= ~LPC18XX_SCU_PIN_EPUN;
1019 		break;
1020 
1021 	case PIN_CONFIG_BIAS_PULL_DOWN:
1022 		*reg |= LPC18XX_SCU_PIN_EPD;
1023 		break;
1024 
1025 	case PIN_CONFIG_INPUT_ENABLE:
1026 		if (param_val)
1027 			*reg |= LPC18XX_SCU_PIN_EZI;
1028 		else
1029 			*reg &= ~LPC18XX_SCU_PIN_EZI;
1030 		break;
1031 
1032 	case PIN_CONFIG_SLEW_RATE:
1033 		if (pin_cap->type == TYPE_HD) {
1034 			dev_err(pctldev->dev, "Slew rate unsupported on high-drive pins\n");
1035 			return -ENOTSUPP;
1036 		}
1037 
1038 		if (param_val == 0)
1039 			*reg &= ~LPC18XX_SCU_PIN_EHS;
1040 		else
1041 			*reg |= LPC18XX_SCU_PIN_EHS;
1042 		break;
1043 
1044 	case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
1045 		if (param_val)
1046 			*reg &= ~LPC18XX_SCU_PIN_ZIF;
1047 		else
1048 			*reg |= LPC18XX_SCU_PIN_ZIF;
1049 		break;
1050 
1051 	case PIN_CONFIG_DRIVE_STRENGTH:
1052 		if (pin_cap->type != TYPE_HD) {
1053 			dev_err(pctldev->dev, "Drive strength available only on high-drive pins\n");
1054 			return -ENOTSUPP;
1055 		}
1056 		*reg &= ~LPC18XX_SCU_PIN_EHD_MASK;
1057 
1058 		switch (param_val) {
1059 		case 20: param_val -= 5;
1060 			fallthrough;
1061 		case 14: param_val -= 5;
1062 			fallthrough;
1063 		case  8: param_val -= 3;
1064 			fallthrough;
1065 		case  4: param_val -= 4;
1066 			 break;
1067 		default:
1068 			dev_err(pctldev->dev, "Drive strength %u unsupported\n", param_val);
1069 			return -ENOTSUPP;
1070 		}
1071 		*reg |= param_val << LPC18XX_SCU_PIN_EHD_POS;
1072 		break;
1073 
1074 	case PIN_CONFIG_GPIO_PIN_INT:
1075 		return lpc18xx_pconf_set_gpio_pin_int(pctldev, param_val, pin);
1076 
1077 	default:
1078 		dev_err(pctldev->dev, "Property not supported\n");
1079 		return -ENOTSUPP;
1080 	}
1081 
1082 	return 0;
1083 }
1084 
1085 static int lpc18xx_pconf_set(struct pinctrl_dev *pctldev, unsigned pin,
1086 			     unsigned long *configs, unsigned num_configs)
1087 {
1088 	struct lpc18xx_scu_data *scu = pinctrl_dev_get_drvdata(pctldev);
1089 	struct lpc18xx_pin_caps *pin_cap;
1090 	enum pin_config_param param;
1091 	u32 param_val;
1092 	u32 reg;
1093 	int ret;
1094 	int i;
1095 
1096 	pin_cap = lpc18xx_get_pin_caps(pin);
1097 	if (!pin_cap)
1098 		return -EINVAL;
1099 
1100 	reg = readl(scu->base + pin_cap->offset);
1101 
1102 	for (i = 0; i < num_configs; i++) {
1103 		param = pinconf_to_config_param(configs[i]);
1104 		param_val = pinconf_to_config_argument(configs[i]);
1105 
1106 		if (pin_cap->type == TYPE_I2C0)
1107 			ret = lpc18xx_pconf_set_i2c0(pctldev, param, param_val, &reg, pin);
1108 		else if (pin_cap->type == TYPE_USB1)
1109 			ret = lpc18xx_pconf_set_usb1(pctldev, param, param_val, &reg);
1110 		else
1111 			ret = lpc18xx_pconf_set_pin(pctldev, param, param_val, &reg, pin, pin_cap);
1112 
1113 		if (ret)
1114 			return ret;
1115 	}
1116 
1117 	writel(reg, scu->base + pin_cap->offset);
1118 
1119 	return 0;
1120 }
1121 
1122 static const struct pinconf_ops lpc18xx_pconf_ops = {
1123 	.is_generic	= true,
1124 	.pin_config_get	= lpc18xx_pconf_get,
1125 	.pin_config_set	= lpc18xx_pconf_set,
1126 };
1127 
1128 static int lpc18xx_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
1129 {
1130 	return ARRAY_SIZE(lpc18xx_function_names);
1131 }
1132 
1133 static const char *lpc18xx_pmx_get_func_name(struct pinctrl_dev *pctldev,
1134 					     unsigned function)
1135 {
1136 	return lpc18xx_function_names[function];
1137 }
1138 
1139 static int lpc18xx_pmx_get_func_groups(struct pinctrl_dev *pctldev,
1140 				       unsigned function,
1141 				       const char *const **groups,
1142 				       unsigned *const num_groups)
1143 {
1144 	struct lpc18xx_scu_data *scu = pinctrl_dev_get_drvdata(pctldev);
1145 
1146 	*groups  = scu->func[function].groups;
1147 	*num_groups = scu->func[function].ngroups;
1148 
1149 	return 0;
1150 }
1151 
1152 static int lpc18xx_pmx_set(struct pinctrl_dev *pctldev, unsigned function,
1153 			   unsigned group)
1154 {
1155 	struct lpc18xx_scu_data *scu = pinctrl_dev_get_drvdata(pctldev);
1156 	struct lpc18xx_pin_caps *pin = lpc18xx_pins[group].drv_data;
1157 	int func;
1158 	u32 reg;
1159 
1160 	/* Dedicated USB1 and I2C0 pins doesn't support muxing */
1161 	if (pin->type == TYPE_USB1) {
1162 		if (function == FUNC_USB1)
1163 			return 0;
1164 
1165 		goto fail;
1166 	}
1167 
1168 	if (pin->type == TYPE_I2C0) {
1169 		if (function == FUNC_I2C0)
1170 			return 0;
1171 
1172 		goto fail;
1173 	}
1174 
1175 	if (function == FUNC_ADC && (pin->analog & LPC18XX_ANALOG_PIN)) {
1176 		u32 offset;
1177 
1178 		writel(LPC18XX_SCU_ANALOG_PIN_CFG, scu->base + pin->offset);
1179 
1180 		if (LPC18XX_ANALOG_ADC(pin->analog) == 0)
1181 			offset = LPC18XX_SCU_REG_ENAIO0;
1182 		else
1183 			offset = LPC18XX_SCU_REG_ENAIO1;
1184 
1185 		reg = readl(scu->base + offset);
1186 		reg |= pin->analog & LPC18XX_ANALOG_BIT_MASK;
1187 		writel(reg, scu->base + offset);
1188 
1189 		return 0;
1190 	}
1191 
1192 	if (function == FUNC_DAC && (pin->analog & LPC18XX_ANALOG_PIN)) {
1193 		writel(LPC18XX_SCU_ANALOG_PIN_CFG, scu->base + pin->offset);
1194 
1195 		reg = readl(scu->base + LPC18XX_SCU_REG_ENAIO2);
1196 		reg |= LPC18XX_SCU_REG_ENAIO2_DAC;
1197 		writel(reg, scu->base + LPC18XX_SCU_REG_ENAIO2);
1198 
1199 		return 0;
1200 	}
1201 
1202 	for (func = 0; func < LPC18XX_SCU_FUNC_PER_PIN; func++) {
1203 		if (function == pin->functions[func])
1204 			break;
1205 	}
1206 
1207 	if (func >= LPC18XX_SCU_FUNC_PER_PIN)
1208 		goto fail;
1209 
1210 	reg = readl(scu->base + pin->offset);
1211 	reg &= ~LPC18XX_SCU_PIN_MODE_MASK;
1212 	writel(reg | func, scu->base + pin->offset);
1213 
1214 	return 0;
1215 fail:
1216 	dev_err(pctldev->dev, "Pin %s can't be %s\n", lpc18xx_pins[group].name,
1217 						      lpc18xx_function_names[function]);
1218 	return -EINVAL;
1219 }
1220 
1221 static const struct pinmux_ops lpc18xx_pmx_ops = {
1222 	.get_functions_count	= lpc18xx_pmx_get_funcs_count,
1223 	.get_function_name	= lpc18xx_pmx_get_func_name,
1224 	.get_function_groups	= lpc18xx_pmx_get_func_groups,
1225 	.set_mux		= lpc18xx_pmx_set,
1226 };
1227 
1228 static int lpc18xx_pctl_get_groups_count(struct pinctrl_dev *pctldev)
1229 {
1230 	return ARRAY_SIZE(lpc18xx_pins);
1231 }
1232 
1233 static const char *lpc18xx_pctl_get_group_name(struct pinctrl_dev *pctldev,
1234 					       unsigned group)
1235 {
1236 	return lpc18xx_pins[group].name;
1237 }
1238 
1239 static int lpc18xx_pctl_get_group_pins(struct pinctrl_dev *pctldev,
1240 				       unsigned group,
1241 				       const unsigned **pins,
1242 				       unsigned *num_pins)
1243 {
1244 	*pins = &lpc18xx_pins[group].number;
1245 	*num_pins = 1;
1246 
1247 	return 0;
1248 }
1249 
1250 static const struct pinctrl_ops lpc18xx_pctl_ops = {
1251 	.get_groups_count	= lpc18xx_pctl_get_groups_count,
1252 	.get_group_name		= lpc18xx_pctl_get_group_name,
1253 	.get_group_pins		= lpc18xx_pctl_get_group_pins,
1254 	.dt_node_to_map		= pinconf_generic_dt_node_to_map_pin,
1255 	.dt_free_map		= pinctrl_utils_free_map,
1256 };
1257 
1258 static struct pinctrl_desc lpc18xx_scu_desc = {
1259 	.name = "lpc18xx/43xx-scu",
1260 	.pins = lpc18xx_pins,
1261 	.npins = ARRAY_SIZE(lpc18xx_pins),
1262 	.pctlops = &lpc18xx_pctl_ops,
1263 	.pmxops = &lpc18xx_pmx_ops,
1264 	.confops = &lpc18xx_pconf_ops,
1265 	.num_custom_params = ARRAY_SIZE(lpc18xx_params),
1266 	.custom_params = lpc18xx_params,
1267 #ifdef CONFIG_DEBUG_FS
1268 	.custom_conf_items = lpc18xx_conf_items,
1269 #endif
1270 	.owner = THIS_MODULE,
1271 };
1272 
1273 static bool lpc18xx_valid_pin_function(unsigned pin, unsigned function)
1274 {
1275 	struct lpc18xx_pin_caps *p = lpc18xx_pins[pin].drv_data;
1276 	int i;
1277 
1278 	if (function == FUNC_DAC && p->analog == DAC)
1279 		return true;
1280 
1281 	if (function == FUNC_ADC && p->analog)
1282 		return true;
1283 
1284 	if (function == FUNC_I2C0 && p->type == TYPE_I2C0)
1285 		return true;
1286 
1287 	if (function == FUNC_USB1 && p->type == TYPE_USB1)
1288 		return true;
1289 
1290 	for (i = 0; i < LPC18XX_SCU_FUNC_PER_PIN; i++) {
1291 		if (function == p->functions[i])
1292 			return true;
1293 	}
1294 
1295 	return false;
1296 }
1297 
1298 static int lpc18xx_create_group_func_map(struct device *dev,
1299 					 struct lpc18xx_scu_data *scu)
1300 {
1301 	u16 pins[ARRAY_SIZE(lpc18xx_pins)];
1302 	int func, ngroups, i;
1303 
1304 	for (func = 0; func < FUNC_MAX; func++) {
1305 		for (ngroups = 0, i = 0; i < ARRAY_SIZE(lpc18xx_pins); i++) {
1306 			if (lpc18xx_valid_pin_function(i, func))
1307 				pins[ngroups++] = i;
1308 		}
1309 
1310 		scu->func[func].ngroups = ngroups;
1311 		scu->func[func].groups = devm_kcalloc(dev,
1312 						      ngroups, sizeof(char *),
1313 						      GFP_KERNEL);
1314 		if (!scu->func[func].groups)
1315 			return -ENOMEM;
1316 
1317 		for (i = 0; i < ngroups; i++)
1318 			scu->func[func].groups[i] = lpc18xx_pins[pins[i]].name;
1319 	}
1320 
1321 	return 0;
1322 }
1323 
1324 static int lpc18xx_scu_probe(struct platform_device *pdev)
1325 {
1326 	struct lpc18xx_scu_data *scu;
1327 	int ret;
1328 
1329 	scu = devm_kzalloc(&pdev->dev, sizeof(*scu), GFP_KERNEL);
1330 	if (!scu)
1331 		return -ENOMEM;
1332 
1333 	scu->base = devm_platform_ioremap_resource(pdev, 0);
1334 	if (IS_ERR(scu->base))
1335 		return PTR_ERR(scu->base);
1336 
1337 	scu->clk = devm_clk_get(&pdev->dev, NULL);
1338 	if (IS_ERR(scu->clk)) {
1339 		dev_err(&pdev->dev, "Input clock not found.\n");
1340 		return PTR_ERR(scu->clk);
1341 	}
1342 
1343 	ret = lpc18xx_create_group_func_map(&pdev->dev, scu);
1344 	if (ret) {
1345 		dev_err(&pdev->dev, "Unable to create group func map.\n");
1346 		return ret;
1347 	}
1348 
1349 	ret = clk_prepare_enable(scu->clk);
1350 	if (ret) {
1351 		dev_err(&pdev->dev, "Unable to enable clock.\n");
1352 		return ret;
1353 	}
1354 
1355 	platform_set_drvdata(pdev, scu);
1356 
1357 	scu->pctl = devm_pinctrl_register(&pdev->dev, &lpc18xx_scu_desc, scu);
1358 	if (IS_ERR(scu->pctl)) {
1359 		dev_err(&pdev->dev, "Could not register pinctrl driver\n");
1360 		clk_disable_unprepare(scu->clk);
1361 		return PTR_ERR(scu->pctl);
1362 	}
1363 
1364 	return 0;
1365 }
1366 
1367 static const struct of_device_id lpc18xx_scu_match[] = {
1368 	{ .compatible = "nxp,lpc1850-scu" },
1369 	{},
1370 };
1371 
1372 static struct platform_driver lpc18xx_scu_driver = {
1373 	.probe		= lpc18xx_scu_probe,
1374 	.driver = {
1375 		.name		= "lpc18xx-scu",
1376 		.of_match_table	= lpc18xx_scu_match,
1377 		.suppress_bind_attrs = true,
1378 	},
1379 };
1380 builtin_platform_driver(lpc18xx_scu_driver);
1381