1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Ingenic SoCs pinctrl driver 4 * 5 * Copyright (c) 2017 Paul Cercueil <paul@crapouillou.net> 6 * Copyright (c) 2019 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> 7 * Copyright (c) 2017, 2019 Paul Boddie <paul@boddie.org.uk> 8 */ 9 10 #include <linux/compiler.h> 11 #include <linux/gpio/driver.h> 12 #include <linux/interrupt.h> 13 #include <linux/io.h> 14 #include <linux/of_device.h> 15 #include <linux/of_irq.h> 16 #include <linux/of_platform.h> 17 #include <linux/pinctrl/pinctrl.h> 18 #include <linux/pinctrl/pinmux.h> 19 #include <linux/pinctrl/pinconf.h> 20 #include <linux/pinctrl/pinconf-generic.h> 21 #include <linux/platform_device.h> 22 #include <linux/regmap.h> 23 #include <linux/slab.h> 24 25 #include "core.h" 26 #include "pinconf.h" 27 #include "pinmux.h" 28 29 #define GPIO_PIN 0x00 30 #define GPIO_MSK 0x20 31 32 #define JZ4740_GPIO_DATA 0x10 33 #define JZ4740_GPIO_PULL_DIS 0x30 34 #define JZ4740_GPIO_FUNC 0x40 35 #define JZ4740_GPIO_SELECT 0x50 36 #define JZ4740_GPIO_DIR 0x60 37 #define JZ4740_GPIO_TRIG 0x70 38 #define JZ4740_GPIO_FLAG 0x80 39 40 #define JZ4760_GPIO_INT 0x10 41 #define JZ4760_GPIO_PAT1 0x30 42 #define JZ4760_GPIO_PAT0 0x40 43 #define JZ4760_GPIO_FLAG 0x50 44 #define JZ4760_GPIO_PEN 0x70 45 46 #define X1830_GPIO_PEL 0x110 47 #define X1830_GPIO_PEH 0x120 48 49 #define REG_SET(x) ((x) + 0x4) 50 #define REG_CLEAR(x) ((x) + 0x8) 51 52 #define REG_PZ_BASE(x) ((x) * 7) 53 #define REG_PZ_GID2LD(x) ((x) * 7 + 0xf0) 54 55 #define GPIO_PULL_DIS 0 56 #define GPIO_PULL_UP 1 57 #define GPIO_PULL_DOWN 2 58 59 #define PINS_PER_GPIO_CHIP 32 60 61 enum jz_version { 62 ID_JZ4740, 63 ID_JZ4725B, 64 ID_JZ4760, 65 ID_JZ4770, 66 ID_JZ4780, 67 ID_X1000, 68 ID_X1500, 69 ID_X1830, 70 }; 71 72 struct ingenic_chip_info { 73 unsigned int num_chips; 74 unsigned int reg_offset; 75 enum jz_version version; 76 77 const struct group_desc *groups; 78 unsigned int num_groups; 79 80 const struct function_desc *functions; 81 unsigned int num_functions; 82 83 const u32 *pull_ups, *pull_downs; 84 }; 85 86 struct ingenic_pinctrl { 87 struct device *dev; 88 struct regmap *map; 89 struct pinctrl_dev *pctl; 90 struct pinctrl_pin_desc *pdesc; 91 92 const struct ingenic_chip_info *info; 93 }; 94 95 struct ingenic_gpio_chip { 96 struct ingenic_pinctrl *jzpc; 97 struct gpio_chip gc; 98 struct irq_chip irq_chip; 99 unsigned int irq, reg_base; 100 }; 101 102 static const u32 jz4740_pull_ups[4] = { 103 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 104 }; 105 106 static const u32 jz4740_pull_downs[4] = { 107 0x00000000, 0x00000000, 0x00000000, 0x00000000, 108 }; 109 110 static int jz4740_mmc_1bit_pins[] = { 0x69, 0x68, 0x6a, }; 111 static int jz4740_mmc_4bit_pins[] = { 0x6b, 0x6c, 0x6d, }; 112 static int jz4740_uart0_data_pins[] = { 0x7a, 0x79, }; 113 static int jz4740_uart0_hwflow_pins[] = { 0x7e, 0x7f, }; 114 static int jz4740_uart1_data_pins[] = { 0x7e, 0x7f, }; 115 static int jz4740_lcd_8bit_pins[] = { 116 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x52, 0x53, 0x54, 117 }; 118 static int jz4740_lcd_16bit_pins[] = { 119 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, 0x55, 120 }; 121 static int jz4740_lcd_18bit_pins[] = { 0x50, 0x51, }; 122 static int jz4740_lcd_18bit_tft_pins[] = { 0x56, 0x57, 0x31, 0x32, }; 123 static int jz4740_nand_cs1_pins[] = { 0x39, }; 124 static int jz4740_nand_cs2_pins[] = { 0x3a, }; 125 static int jz4740_nand_cs3_pins[] = { 0x3b, }; 126 static int jz4740_nand_cs4_pins[] = { 0x3c, }; 127 static int jz4740_nand_fre_fwe_pins[] = { 0x5c, 0x5d, }; 128 static int jz4740_pwm_pwm0_pins[] = { 0x77, }; 129 static int jz4740_pwm_pwm1_pins[] = { 0x78, }; 130 static int jz4740_pwm_pwm2_pins[] = { 0x79, }; 131 static int jz4740_pwm_pwm3_pins[] = { 0x7a, }; 132 static int jz4740_pwm_pwm4_pins[] = { 0x7b, }; 133 static int jz4740_pwm_pwm5_pins[] = { 0x7c, }; 134 static int jz4740_pwm_pwm6_pins[] = { 0x7e, }; 135 static int jz4740_pwm_pwm7_pins[] = { 0x7f, }; 136 137 static int jz4740_mmc_1bit_funcs[] = { 0, 0, 0, }; 138 static int jz4740_mmc_4bit_funcs[] = { 0, 0, 0, }; 139 static int jz4740_uart0_data_funcs[] = { 1, 1, }; 140 static int jz4740_uart0_hwflow_funcs[] = { 1, 1, }; 141 static int jz4740_uart1_data_funcs[] = { 2, 2, }; 142 static int jz4740_lcd_8bit_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; 143 static int jz4740_lcd_16bit_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, }; 144 static int jz4740_lcd_18bit_funcs[] = { 0, 0, }; 145 static int jz4740_lcd_18bit_tft_funcs[] = { 0, 0, 0, 0, }; 146 static int jz4740_nand_cs1_funcs[] = { 0, }; 147 static int jz4740_nand_cs2_funcs[] = { 0, }; 148 static int jz4740_nand_cs3_funcs[] = { 0, }; 149 static int jz4740_nand_cs4_funcs[] = { 0, }; 150 static int jz4740_nand_fre_fwe_funcs[] = { 0, 0, }; 151 static int jz4740_pwm_pwm0_funcs[] = { 0, }; 152 static int jz4740_pwm_pwm1_funcs[] = { 0, }; 153 static int jz4740_pwm_pwm2_funcs[] = { 0, }; 154 static int jz4740_pwm_pwm3_funcs[] = { 0, }; 155 static int jz4740_pwm_pwm4_funcs[] = { 0, }; 156 static int jz4740_pwm_pwm5_funcs[] = { 0, }; 157 static int jz4740_pwm_pwm6_funcs[] = { 0, }; 158 static int jz4740_pwm_pwm7_funcs[] = { 0, }; 159 160 #define INGENIC_PIN_GROUP(name, id) \ 161 { \ 162 name, \ 163 id##_pins, \ 164 ARRAY_SIZE(id##_pins), \ 165 id##_funcs, \ 166 } 167 168 static const struct group_desc jz4740_groups[] = { 169 INGENIC_PIN_GROUP("mmc-1bit", jz4740_mmc_1bit), 170 INGENIC_PIN_GROUP("mmc-4bit", jz4740_mmc_4bit), 171 INGENIC_PIN_GROUP("uart0-data", jz4740_uart0_data), 172 INGENIC_PIN_GROUP("uart0-hwflow", jz4740_uart0_hwflow), 173 INGENIC_PIN_GROUP("uart1-data", jz4740_uart1_data), 174 INGENIC_PIN_GROUP("lcd-8bit", jz4740_lcd_8bit), 175 INGENIC_PIN_GROUP("lcd-16bit", jz4740_lcd_16bit), 176 INGENIC_PIN_GROUP("lcd-18bit", jz4740_lcd_18bit), 177 INGENIC_PIN_GROUP("lcd-18bit-tft", jz4740_lcd_18bit_tft), 178 { "lcd-no-pins", }, 179 INGENIC_PIN_GROUP("nand-cs1", jz4740_nand_cs1), 180 INGENIC_PIN_GROUP("nand-cs2", jz4740_nand_cs2), 181 INGENIC_PIN_GROUP("nand-cs3", jz4740_nand_cs3), 182 INGENIC_PIN_GROUP("nand-cs4", jz4740_nand_cs4), 183 INGENIC_PIN_GROUP("nand-fre-fwe", jz4740_nand_fre_fwe), 184 INGENIC_PIN_GROUP("pwm0", jz4740_pwm_pwm0), 185 INGENIC_PIN_GROUP("pwm1", jz4740_pwm_pwm1), 186 INGENIC_PIN_GROUP("pwm2", jz4740_pwm_pwm2), 187 INGENIC_PIN_GROUP("pwm3", jz4740_pwm_pwm3), 188 INGENIC_PIN_GROUP("pwm4", jz4740_pwm_pwm4), 189 INGENIC_PIN_GROUP("pwm5", jz4740_pwm_pwm5), 190 INGENIC_PIN_GROUP("pwm6", jz4740_pwm_pwm6), 191 INGENIC_PIN_GROUP("pwm7", jz4740_pwm_pwm7), 192 }; 193 194 static const char *jz4740_mmc_groups[] = { "mmc-1bit", "mmc-4bit", }; 195 static const char *jz4740_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; 196 static const char *jz4740_uart1_groups[] = { "uart1-data", }; 197 static const char *jz4740_lcd_groups[] = { 198 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-18bit-tft", "lcd-no-pins", 199 }; 200 static const char *jz4740_nand_groups[] = { 201 "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", "nand-fre-fwe", 202 }; 203 static const char *jz4740_pwm0_groups[] = { "pwm0", }; 204 static const char *jz4740_pwm1_groups[] = { "pwm1", }; 205 static const char *jz4740_pwm2_groups[] = { "pwm2", }; 206 static const char *jz4740_pwm3_groups[] = { "pwm3", }; 207 static const char *jz4740_pwm4_groups[] = { "pwm4", }; 208 static const char *jz4740_pwm5_groups[] = { "pwm5", }; 209 static const char *jz4740_pwm6_groups[] = { "pwm6", }; 210 static const char *jz4740_pwm7_groups[] = { "pwm7", }; 211 212 static const struct function_desc jz4740_functions[] = { 213 { "mmc", jz4740_mmc_groups, ARRAY_SIZE(jz4740_mmc_groups), }, 214 { "uart0", jz4740_uart0_groups, ARRAY_SIZE(jz4740_uart0_groups), }, 215 { "uart1", jz4740_uart1_groups, ARRAY_SIZE(jz4740_uart1_groups), }, 216 { "lcd", jz4740_lcd_groups, ARRAY_SIZE(jz4740_lcd_groups), }, 217 { "nand", jz4740_nand_groups, ARRAY_SIZE(jz4740_nand_groups), }, 218 { "pwm0", jz4740_pwm0_groups, ARRAY_SIZE(jz4740_pwm0_groups), }, 219 { "pwm1", jz4740_pwm1_groups, ARRAY_SIZE(jz4740_pwm1_groups), }, 220 { "pwm2", jz4740_pwm2_groups, ARRAY_SIZE(jz4740_pwm2_groups), }, 221 { "pwm3", jz4740_pwm3_groups, ARRAY_SIZE(jz4740_pwm3_groups), }, 222 { "pwm4", jz4740_pwm4_groups, ARRAY_SIZE(jz4740_pwm4_groups), }, 223 { "pwm5", jz4740_pwm5_groups, ARRAY_SIZE(jz4740_pwm5_groups), }, 224 { "pwm6", jz4740_pwm6_groups, ARRAY_SIZE(jz4740_pwm6_groups), }, 225 { "pwm7", jz4740_pwm7_groups, ARRAY_SIZE(jz4740_pwm7_groups), }, 226 }; 227 228 static const struct ingenic_chip_info jz4740_chip_info = { 229 .num_chips = 4, 230 .reg_offset = 0x100, 231 .version = ID_JZ4740, 232 .groups = jz4740_groups, 233 .num_groups = ARRAY_SIZE(jz4740_groups), 234 .functions = jz4740_functions, 235 .num_functions = ARRAY_SIZE(jz4740_functions), 236 .pull_ups = jz4740_pull_ups, 237 .pull_downs = jz4740_pull_downs, 238 }; 239 240 static int jz4725b_mmc0_1bit_pins[] = { 0x48, 0x49, 0x5c, }; 241 static int jz4725b_mmc0_4bit_pins[] = { 0x5d, 0x5b, 0x56, }; 242 static int jz4725b_mmc1_1bit_pins[] = { 0x7a, 0x7b, 0x7c, }; 243 static int jz4725b_mmc1_4bit_pins[] = { 0x7d, 0x7e, 0x7f, }; 244 static int jz4725b_uart_data_pins[] = { 0x4c, 0x4d, }; 245 static int jz4725b_nand_cs1_pins[] = { 0x55, }; 246 static int jz4725b_nand_cs2_pins[] = { 0x56, }; 247 static int jz4725b_nand_cs3_pins[] = { 0x57, }; 248 static int jz4725b_nand_cs4_pins[] = { 0x58, }; 249 static int jz4725b_nand_cle_ale_pins[] = { 0x48, 0x49 }; 250 static int jz4725b_nand_fre_fwe_pins[] = { 0x5c, 0x5d }; 251 static int jz4725b_pwm_pwm0_pins[] = { 0x4a, }; 252 static int jz4725b_pwm_pwm1_pins[] = { 0x4b, }; 253 static int jz4725b_pwm_pwm2_pins[] = { 0x4c, }; 254 static int jz4725b_pwm_pwm3_pins[] = { 0x4d, }; 255 static int jz4725b_pwm_pwm4_pins[] = { 0x4e, }; 256 static int jz4725b_pwm_pwm5_pins[] = { 0x4f, }; 257 static int jz4725b_lcd_8bit_pins[] = { 258 0x72, 0x73, 0x74, 259 0x60, 0x61, 0x62, 0x63, 260 0x64, 0x65, 0x66, 0x67, 261 }; 262 static int jz4725b_lcd_16bit_pins[] = { 263 0x68, 0x69, 0x6a, 0x6b, 264 0x6c, 0x6d, 0x6e, 0x6f, 265 }; 266 static int jz4725b_lcd_18bit_pins[] = { 0x70, 0x71, }; 267 static int jz4725b_lcd_24bit_pins[] = { 0x76, 0x77, 0x78, 0x79, }; 268 static int jz4725b_lcd_special_pins[] = { 0x76, 0x77, 0x78, 0x79, }; 269 static int jz4725b_lcd_generic_pins[] = { 0x75, }; 270 271 static int jz4725b_mmc0_1bit_funcs[] = { 1, 1, 1, }; 272 static int jz4725b_mmc0_4bit_funcs[] = { 1, 0, 1, }; 273 static int jz4725b_mmc1_1bit_funcs[] = { 0, 0, 0, }; 274 static int jz4725b_mmc1_4bit_funcs[] = { 0, 0, 0, }; 275 static int jz4725b_uart_data_funcs[] = { 1, 1, }; 276 static int jz4725b_nand_cs1_funcs[] = { 0, }; 277 static int jz4725b_nand_cs2_funcs[] = { 0, }; 278 static int jz4725b_nand_cs3_funcs[] = { 0, }; 279 static int jz4725b_nand_cs4_funcs[] = { 0, }; 280 static int jz4725b_nand_cle_ale_funcs[] = { 0, 0, }; 281 static int jz4725b_nand_fre_fwe_funcs[] = { 0, 0, }; 282 static int jz4725b_pwm_pwm0_funcs[] = { 0, }; 283 static int jz4725b_pwm_pwm1_funcs[] = { 0, }; 284 static int jz4725b_pwm_pwm2_funcs[] = { 0, }; 285 static int jz4725b_pwm_pwm3_funcs[] = { 0, }; 286 static int jz4725b_pwm_pwm4_funcs[] = { 0, }; 287 static int jz4725b_pwm_pwm5_funcs[] = { 0, }; 288 static int jz4725b_lcd_8bit_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; 289 static int jz4725b_lcd_16bit_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, }; 290 static int jz4725b_lcd_18bit_funcs[] = { 0, 0, }; 291 static int jz4725b_lcd_24bit_funcs[] = { 1, 1, 1, 1, }; 292 static int jz4725b_lcd_special_funcs[] = { 0, 0, 0, 0, }; 293 static int jz4725b_lcd_generic_funcs[] = { 0, }; 294 295 static const struct group_desc jz4725b_groups[] = { 296 INGENIC_PIN_GROUP("mmc0-1bit", jz4725b_mmc0_1bit), 297 INGENIC_PIN_GROUP("mmc0-4bit", jz4725b_mmc0_4bit), 298 INGENIC_PIN_GROUP("mmc1-1bit", jz4725b_mmc1_1bit), 299 INGENIC_PIN_GROUP("mmc1-4bit", jz4725b_mmc1_4bit), 300 INGENIC_PIN_GROUP("uart-data", jz4725b_uart_data), 301 INGENIC_PIN_GROUP("nand-cs1", jz4725b_nand_cs1), 302 INGENIC_PIN_GROUP("nand-cs2", jz4725b_nand_cs2), 303 INGENIC_PIN_GROUP("nand-cs3", jz4725b_nand_cs3), 304 INGENIC_PIN_GROUP("nand-cs4", jz4725b_nand_cs4), 305 INGENIC_PIN_GROUP("nand-cle-ale", jz4725b_nand_cle_ale), 306 INGENIC_PIN_GROUP("nand-fre-fwe", jz4725b_nand_fre_fwe), 307 INGENIC_PIN_GROUP("pwm0", jz4725b_pwm_pwm0), 308 INGENIC_PIN_GROUP("pwm1", jz4725b_pwm_pwm1), 309 INGENIC_PIN_GROUP("pwm2", jz4725b_pwm_pwm2), 310 INGENIC_PIN_GROUP("pwm3", jz4725b_pwm_pwm3), 311 INGENIC_PIN_GROUP("pwm4", jz4725b_pwm_pwm4), 312 INGENIC_PIN_GROUP("pwm5", jz4725b_pwm_pwm5), 313 INGENIC_PIN_GROUP("lcd-8bit", jz4725b_lcd_8bit), 314 INGENIC_PIN_GROUP("lcd-16bit", jz4725b_lcd_16bit), 315 INGENIC_PIN_GROUP("lcd-18bit", jz4725b_lcd_18bit), 316 INGENIC_PIN_GROUP("lcd-24bit", jz4725b_lcd_24bit), 317 INGENIC_PIN_GROUP("lcd-special", jz4725b_lcd_special), 318 INGENIC_PIN_GROUP("lcd-generic", jz4725b_lcd_generic), 319 }; 320 321 static const char *jz4725b_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", }; 322 static const char *jz4725b_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", }; 323 static const char *jz4725b_uart_groups[] = { "uart-data", }; 324 static const char *jz4725b_nand_groups[] = { 325 "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", 326 "nand-cle-ale", "nand-fre-fwe", 327 }; 328 static const char *jz4725b_pwm0_groups[] = { "pwm0", }; 329 static const char *jz4725b_pwm1_groups[] = { "pwm1", }; 330 static const char *jz4725b_pwm2_groups[] = { "pwm2", }; 331 static const char *jz4725b_pwm3_groups[] = { "pwm3", }; 332 static const char *jz4725b_pwm4_groups[] = { "pwm4", }; 333 static const char *jz4725b_pwm5_groups[] = { "pwm5", }; 334 static const char *jz4725b_lcd_groups[] = { 335 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit", 336 "lcd-special", "lcd-generic", 337 }; 338 339 static const struct function_desc jz4725b_functions[] = { 340 { "mmc0", jz4725b_mmc0_groups, ARRAY_SIZE(jz4725b_mmc0_groups), }, 341 { "mmc1", jz4725b_mmc1_groups, ARRAY_SIZE(jz4725b_mmc1_groups), }, 342 { "uart", jz4725b_uart_groups, ARRAY_SIZE(jz4725b_uart_groups), }, 343 { "nand", jz4725b_nand_groups, ARRAY_SIZE(jz4725b_nand_groups), }, 344 { "pwm0", jz4725b_pwm0_groups, ARRAY_SIZE(jz4725b_pwm0_groups), }, 345 { "pwm1", jz4725b_pwm1_groups, ARRAY_SIZE(jz4725b_pwm1_groups), }, 346 { "pwm2", jz4725b_pwm2_groups, ARRAY_SIZE(jz4725b_pwm2_groups), }, 347 { "pwm3", jz4725b_pwm3_groups, ARRAY_SIZE(jz4725b_pwm3_groups), }, 348 { "pwm4", jz4725b_pwm4_groups, ARRAY_SIZE(jz4725b_pwm4_groups), }, 349 { "pwm5", jz4725b_pwm5_groups, ARRAY_SIZE(jz4725b_pwm5_groups), }, 350 { "lcd", jz4725b_lcd_groups, ARRAY_SIZE(jz4725b_lcd_groups), }, 351 }; 352 353 static const struct ingenic_chip_info jz4725b_chip_info = { 354 .num_chips = 4, 355 .reg_offset = 0x100, 356 .version = ID_JZ4725B, 357 .groups = jz4725b_groups, 358 .num_groups = ARRAY_SIZE(jz4725b_groups), 359 .functions = jz4725b_functions, 360 .num_functions = ARRAY_SIZE(jz4725b_functions), 361 .pull_ups = jz4740_pull_ups, 362 .pull_downs = jz4740_pull_downs, 363 }; 364 365 static const u32 jz4760_pull_ups[6] = { 366 0xffffffff, 0xfffcf3ff, 0xffffffff, 0xffffcfff, 0xfffffb7c, 0xfffff00f, 367 }; 368 369 static const u32 jz4760_pull_downs[6] = { 370 0x00000000, 0x00030c00, 0x00000000, 0x00003000, 0x00000483, 0x00000ff0, 371 }; 372 373 static int jz4760_uart0_data_pins[] = { 0xa0, 0xa3, }; 374 static int jz4760_uart0_hwflow_pins[] = { 0xa1, 0xa2, }; 375 static int jz4760_uart1_data_pins[] = { 0x7a, 0x7c, }; 376 static int jz4760_uart1_hwflow_pins[] = { 0x7b, 0x7d, }; 377 static int jz4760_uart2_data_pins[] = { 0x5c, 0x5e, }; 378 static int jz4760_uart2_hwflow_pins[] = { 0x5d, 0x5f, }; 379 static int jz4760_uart3_data_pins[] = { 0x6c, 0x85, }; 380 static int jz4760_uart3_hwflow_pins[] = { 0x88, 0x89, }; 381 static int jz4760_mmc0_1bit_a_pins[] = { 0x12, 0x13, 0x14, }; 382 static int jz4760_mmc0_4bit_a_pins[] = { 0x15, 0x16, 0x17, }; 383 static int jz4760_mmc0_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; 384 static int jz4760_mmc0_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; 385 static int jz4760_mmc0_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, }; 386 static int jz4760_mmc1_1bit_d_pins[] = { 0x78, 0x79, 0x74, }; 387 static int jz4760_mmc1_4bit_d_pins[] = { 0x75, 0x76, 0x77, }; 388 static int jz4760_mmc1_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; 389 static int jz4760_mmc1_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; 390 static int jz4760_mmc1_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, }; 391 static int jz4760_mmc2_1bit_b_pins[] = { 0x3c, 0x3d, 0x34, }; 392 static int jz4760_mmc2_4bit_b_pins[] = { 0x35, 0x3e, 0x3f, }; 393 static int jz4760_mmc2_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; 394 static int jz4760_mmc2_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; 395 static int jz4760_mmc2_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, }; 396 static int jz4760_nemc_8bit_data_pins[] = { 397 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 398 }; 399 static int jz4760_nemc_16bit_data_pins[] = { 400 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 401 }; 402 static int jz4760_nemc_cle_ale_pins[] = { 0x20, 0x21, }; 403 static int jz4760_nemc_addr_pins[] = { 0x22, 0x23, 0x24, 0x25, }; 404 static int jz4760_nemc_rd_we_pins[] = { 0x10, 0x11, }; 405 static int jz4760_nemc_frd_fwe_pins[] = { 0x12, 0x13, }; 406 static int jz4760_nemc_wait_pins[] = { 0x1b, }; 407 static int jz4760_nemc_cs1_pins[] = { 0x15, }; 408 static int jz4760_nemc_cs2_pins[] = { 0x16, }; 409 static int jz4760_nemc_cs3_pins[] = { 0x17, }; 410 static int jz4760_nemc_cs4_pins[] = { 0x18, }; 411 static int jz4760_nemc_cs5_pins[] = { 0x19, }; 412 static int jz4760_nemc_cs6_pins[] = { 0x1a, }; 413 static int jz4760_i2c0_pins[] = { 0x7e, 0x7f, }; 414 static int jz4760_i2c1_pins[] = { 0x9e, 0x9f, }; 415 static int jz4760_cim_pins[] = { 416 0x26, 0x27, 0x28, 0x29, 417 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31, 418 }; 419 static int jz4760_lcd_24bit_pins[] = { 420 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 421 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, 422 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 423 0x58, 0x59, 0x5a, 0x5b, 424 }; 425 static int jz4760_pwm_pwm0_pins[] = { 0x80, }; 426 static int jz4760_pwm_pwm1_pins[] = { 0x81, }; 427 static int jz4760_pwm_pwm2_pins[] = { 0x82, }; 428 static int jz4760_pwm_pwm3_pins[] = { 0x83, }; 429 static int jz4760_pwm_pwm4_pins[] = { 0x84, }; 430 static int jz4760_pwm_pwm5_pins[] = { 0x85, }; 431 static int jz4760_pwm_pwm6_pins[] = { 0x6a, }; 432 static int jz4760_pwm_pwm7_pins[] = { 0x6b, }; 433 434 static int jz4760_uart0_data_funcs[] = { 0, 0, }; 435 static int jz4760_uart0_hwflow_funcs[] = { 0, 0, }; 436 static int jz4760_uart1_data_funcs[] = { 0, 0, }; 437 static int jz4760_uart1_hwflow_funcs[] = { 0, 0, }; 438 static int jz4760_uart2_data_funcs[] = { 0, 0, }; 439 static int jz4760_uart2_hwflow_funcs[] = { 0, 0, }; 440 static int jz4760_uart3_data_funcs[] = { 0, 1, }; 441 static int jz4760_uart3_hwflow_funcs[] = { 0, 0, }; 442 static int jz4760_mmc0_1bit_a_funcs[] = { 1, 1, 0, }; 443 static int jz4760_mmc0_4bit_a_funcs[] = { 1, 1, 1, }; 444 static int jz4760_mmc0_1bit_e_funcs[] = { 0, 0, 0, }; 445 static int jz4760_mmc0_4bit_e_funcs[] = { 0, 0, 0, }; 446 static int jz4760_mmc0_8bit_e_funcs[] = { 0, 0, 0, 0, }; 447 static int jz4760_mmc1_1bit_d_funcs[] = { 0, 0, 0, }; 448 static int jz4760_mmc1_4bit_d_funcs[] = { 0, 0, 0, }; 449 static int jz4760_mmc1_1bit_e_funcs[] = { 1, 1, 1, }; 450 static int jz4760_mmc1_4bit_e_funcs[] = { 1, 1, 1, }; 451 static int jz4760_mmc1_8bit_e_funcs[] = { 1, 1, 1, 1, }; 452 static int jz4760_mmc2_1bit_b_funcs[] = { 0, 0, 0, }; 453 static int jz4760_mmc2_4bit_b_funcs[] = { 0, 0, 0, }; 454 static int jz4760_mmc2_1bit_e_funcs[] = { 2, 2, 2, }; 455 static int jz4760_mmc2_4bit_e_funcs[] = { 2, 2, 2, }; 456 static int jz4760_mmc2_8bit_e_funcs[] = { 2, 2, 2, 2, }; 457 static int jz4760_nemc_8bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, }; 458 static int jz4760_nemc_16bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, }; 459 static int jz4760_nemc_cle_ale_funcs[] = { 0, 0, }; 460 static int jz4760_nemc_addr_funcs[] = { 0, 0, 0, 0, }; 461 static int jz4760_nemc_rd_we_funcs[] = { 0, 0, }; 462 static int jz4760_nemc_frd_fwe_funcs[] = { 0, 0, }; 463 static int jz4760_nemc_wait_funcs[] = { 0, }; 464 static int jz4760_nemc_cs1_funcs[] = { 0, }; 465 static int jz4760_nemc_cs2_funcs[] = { 0, }; 466 static int jz4760_nemc_cs3_funcs[] = { 0, }; 467 static int jz4760_nemc_cs4_funcs[] = { 0, }; 468 static int jz4760_nemc_cs5_funcs[] = { 0, }; 469 static int jz4760_nemc_cs6_funcs[] = { 0, }; 470 static int jz4760_i2c0_funcs[] = { 0, 0, }; 471 static int jz4760_i2c1_funcs[] = { 0, 0, }; 472 static int jz4760_cim_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; 473 static int jz4760_lcd_24bit_funcs[] = { 474 0, 0, 0, 0, 0, 0, 0, 0, 475 0, 0, 0, 0, 0, 0, 0, 0, 476 0, 0, 0, 0, 0, 0, 0, 0, 477 0, 0, 0, 0, 478 }; 479 static int jz4760_pwm_pwm0_funcs[] = { 0, }; 480 static int jz4760_pwm_pwm1_funcs[] = { 0, }; 481 static int jz4760_pwm_pwm2_funcs[] = { 0, }; 482 static int jz4760_pwm_pwm3_funcs[] = { 0, }; 483 static int jz4760_pwm_pwm4_funcs[] = { 0, }; 484 static int jz4760_pwm_pwm5_funcs[] = { 0, }; 485 static int jz4760_pwm_pwm6_funcs[] = { 0, }; 486 static int jz4760_pwm_pwm7_funcs[] = { 0, }; 487 488 static const struct group_desc jz4760_groups[] = { 489 INGENIC_PIN_GROUP("uart0-data", jz4760_uart0_data), 490 INGENIC_PIN_GROUP("uart0-hwflow", jz4760_uart0_hwflow), 491 INGENIC_PIN_GROUP("uart1-data", jz4760_uart1_data), 492 INGENIC_PIN_GROUP("uart1-hwflow", jz4760_uart1_hwflow), 493 INGENIC_PIN_GROUP("uart2-data", jz4760_uart2_data), 494 INGENIC_PIN_GROUP("uart2-hwflow", jz4760_uart2_hwflow), 495 INGENIC_PIN_GROUP("uart3-data", jz4760_uart3_data), 496 INGENIC_PIN_GROUP("uart3-hwflow", jz4760_uart3_hwflow), 497 INGENIC_PIN_GROUP("mmc0-1bit-a", jz4760_mmc0_1bit_a), 498 INGENIC_PIN_GROUP("mmc0-4bit-a", jz4760_mmc0_4bit_a), 499 INGENIC_PIN_GROUP("mmc0-1bit-e", jz4760_mmc0_1bit_e), 500 INGENIC_PIN_GROUP("mmc0-4bit-e", jz4760_mmc0_4bit_e), 501 INGENIC_PIN_GROUP("mmc0-8bit-e", jz4760_mmc0_8bit_e), 502 INGENIC_PIN_GROUP("mmc1-1bit-d", jz4760_mmc1_1bit_d), 503 INGENIC_PIN_GROUP("mmc1-4bit-d", jz4760_mmc1_4bit_d), 504 INGENIC_PIN_GROUP("mmc1-1bit-e", jz4760_mmc1_1bit_e), 505 INGENIC_PIN_GROUP("mmc1-4bit-e", jz4760_mmc1_4bit_e), 506 INGENIC_PIN_GROUP("mmc1-8bit-e", jz4760_mmc1_8bit_e), 507 INGENIC_PIN_GROUP("mmc2-1bit-b", jz4760_mmc2_1bit_b), 508 INGENIC_PIN_GROUP("mmc2-4bit-b", jz4760_mmc2_4bit_b), 509 INGENIC_PIN_GROUP("mmc2-1bit-e", jz4760_mmc2_1bit_e), 510 INGENIC_PIN_GROUP("mmc2-4bit-e", jz4760_mmc2_4bit_e), 511 INGENIC_PIN_GROUP("mmc2-8bit-e", jz4760_mmc2_8bit_e), 512 INGENIC_PIN_GROUP("nemc-8bit-data", jz4760_nemc_8bit_data), 513 INGENIC_PIN_GROUP("nemc-16bit-data", jz4760_nemc_16bit_data), 514 INGENIC_PIN_GROUP("nemc-cle-ale", jz4760_nemc_cle_ale), 515 INGENIC_PIN_GROUP("nemc-addr", jz4760_nemc_addr), 516 INGENIC_PIN_GROUP("nemc-rd-we", jz4760_nemc_rd_we), 517 INGENIC_PIN_GROUP("nemc-frd-fwe", jz4760_nemc_frd_fwe), 518 INGENIC_PIN_GROUP("nemc-wait", jz4760_nemc_wait), 519 INGENIC_PIN_GROUP("nemc-cs1", jz4760_nemc_cs1), 520 INGENIC_PIN_GROUP("nemc-cs2", jz4760_nemc_cs2), 521 INGENIC_PIN_GROUP("nemc-cs3", jz4760_nemc_cs3), 522 INGENIC_PIN_GROUP("nemc-cs4", jz4760_nemc_cs4), 523 INGENIC_PIN_GROUP("nemc-cs5", jz4760_nemc_cs5), 524 INGENIC_PIN_GROUP("nemc-cs6", jz4760_nemc_cs6), 525 INGENIC_PIN_GROUP("i2c0-data", jz4760_i2c0), 526 INGENIC_PIN_GROUP("i2c1-data", jz4760_i2c1), 527 INGENIC_PIN_GROUP("cim-data", jz4760_cim), 528 INGENIC_PIN_GROUP("lcd-24bit", jz4760_lcd_24bit), 529 { "lcd-no-pins", }, 530 INGENIC_PIN_GROUP("pwm0", jz4760_pwm_pwm0), 531 INGENIC_PIN_GROUP("pwm1", jz4760_pwm_pwm1), 532 INGENIC_PIN_GROUP("pwm2", jz4760_pwm_pwm2), 533 INGENIC_PIN_GROUP("pwm3", jz4760_pwm_pwm3), 534 INGENIC_PIN_GROUP("pwm4", jz4760_pwm_pwm4), 535 INGENIC_PIN_GROUP("pwm5", jz4760_pwm_pwm5), 536 INGENIC_PIN_GROUP("pwm6", jz4760_pwm_pwm6), 537 INGENIC_PIN_GROUP("pwm7", jz4760_pwm_pwm7), 538 }; 539 540 static const char *jz4760_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; 541 static const char *jz4760_uart1_groups[] = { "uart1-data", "uart1-hwflow", }; 542 static const char *jz4760_uart2_groups[] = { "uart2-data", "uart2-hwflow", }; 543 static const char *jz4760_uart3_groups[] = { "uart3-data", "uart3-hwflow", }; 544 static const char *jz4760_mmc0_groups[] = { 545 "mmc0-1bit-a", "mmc0-4bit-a", 546 "mmc0-1bit-e", "mmc0-4bit-e", "mmc0-8bit-e", 547 }; 548 static const char *jz4760_mmc1_groups[] = { 549 "mmc1-1bit-d", "mmc1-4bit-d", 550 "mmc1-1bit-e", "mmc1-4bit-e", "mmc1-8bit-e", 551 }; 552 static const char *jz4760_mmc2_groups[] = { 553 "mmc2-1bit-b", "mmc2-4bit-b", 554 "mmc2-1bit-e", "mmc2-4bit-e", "mmc2-8bit-e", 555 }; 556 static const char *jz4760_nemc_groups[] = { 557 "nemc-8bit-data", "nemc-16bit-data", "nemc-cle-ale", 558 "nemc-addr", "nemc-rd-we", "nemc-frd-fwe", "nemc-wait", 559 }; 560 static const char *jz4760_cs1_groups[] = { "nemc-cs1", }; 561 static const char *jz4760_cs2_groups[] = { "nemc-cs2", }; 562 static const char *jz4760_cs3_groups[] = { "nemc-cs3", }; 563 static const char *jz4760_cs4_groups[] = { "nemc-cs4", }; 564 static const char *jz4760_cs5_groups[] = { "nemc-cs5", }; 565 static const char *jz4760_cs6_groups[] = { "nemc-cs6", }; 566 static const char *jz4760_i2c0_groups[] = { "i2c0-data", }; 567 static const char *jz4760_i2c1_groups[] = { "i2c1-data", }; 568 static const char *jz4760_cim_groups[] = { "cim-data", }; 569 static const char *jz4760_lcd_groups[] = { "lcd-24bit", "lcd-no-pins", }; 570 static const char *jz4760_pwm0_groups[] = { "pwm0", }; 571 static const char *jz4760_pwm1_groups[] = { "pwm1", }; 572 static const char *jz4760_pwm2_groups[] = { "pwm2", }; 573 static const char *jz4760_pwm3_groups[] = { "pwm3", }; 574 static const char *jz4760_pwm4_groups[] = { "pwm4", }; 575 static const char *jz4760_pwm5_groups[] = { "pwm5", }; 576 static const char *jz4760_pwm6_groups[] = { "pwm6", }; 577 static const char *jz4760_pwm7_groups[] = { "pwm7", }; 578 579 static const struct function_desc jz4760_functions[] = { 580 { "uart0", jz4760_uart0_groups, ARRAY_SIZE(jz4760_uart0_groups), }, 581 { "uart1", jz4760_uart1_groups, ARRAY_SIZE(jz4760_uart1_groups), }, 582 { "uart2", jz4760_uart2_groups, ARRAY_SIZE(jz4760_uart2_groups), }, 583 { "uart3", jz4760_uart3_groups, ARRAY_SIZE(jz4760_uart3_groups), }, 584 { "mmc0", jz4760_mmc0_groups, ARRAY_SIZE(jz4760_mmc0_groups), }, 585 { "mmc1", jz4760_mmc1_groups, ARRAY_SIZE(jz4760_mmc1_groups), }, 586 { "mmc2", jz4760_mmc2_groups, ARRAY_SIZE(jz4760_mmc2_groups), }, 587 { "nemc", jz4760_nemc_groups, ARRAY_SIZE(jz4760_nemc_groups), }, 588 { "nemc-cs1", jz4760_cs1_groups, ARRAY_SIZE(jz4760_cs1_groups), }, 589 { "nemc-cs2", jz4760_cs2_groups, ARRAY_SIZE(jz4760_cs2_groups), }, 590 { "nemc-cs3", jz4760_cs3_groups, ARRAY_SIZE(jz4760_cs3_groups), }, 591 { "nemc-cs4", jz4760_cs4_groups, ARRAY_SIZE(jz4760_cs4_groups), }, 592 { "nemc-cs5", jz4760_cs5_groups, ARRAY_SIZE(jz4760_cs5_groups), }, 593 { "nemc-cs6", jz4760_cs6_groups, ARRAY_SIZE(jz4760_cs6_groups), }, 594 { "i2c0", jz4760_i2c0_groups, ARRAY_SIZE(jz4760_i2c0_groups), }, 595 { "i2c1", jz4760_i2c1_groups, ARRAY_SIZE(jz4760_i2c1_groups), }, 596 { "cim", jz4760_cim_groups, ARRAY_SIZE(jz4760_cim_groups), }, 597 { "lcd", jz4760_lcd_groups, ARRAY_SIZE(jz4760_lcd_groups), }, 598 { "pwm0", jz4760_pwm0_groups, ARRAY_SIZE(jz4760_pwm0_groups), }, 599 { "pwm1", jz4760_pwm1_groups, ARRAY_SIZE(jz4760_pwm1_groups), }, 600 { "pwm2", jz4760_pwm2_groups, ARRAY_SIZE(jz4760_pwm2_groups), }, 601 { "pwm3", jz4760_pwm3_groups, ARRAY_SIZE(jz4760_pwm3_groups), }, 602 { "pwm4", jz4760_pwm4_groups, ARRAY_SIZE(jz4760_pwm4_groups), }, 603 { "pwm5", jz4760_pwm5_groups, ARRAY_SIZE(jz4760_pwm5_groups), }, 604 { "pwm6", jz4760_pwm6_groups, ARRAY_SIZE(jz4760_pwm6_groups), }, 605 { "pwm7", jz4760_pwm7_groups, ARRAY_SIZE(jz4760_pwm7_groups), }, 606 }; 607 608 static const struct ingenic_chip_info jz4760_chip_info = { 609 .num_chips = 6, 610 .reg_offset = 0x100, 611 .version = ID_JZ4760, 612 .groups = jz4760_groups, 613 .num_groups = ARRAY_SIZE(jz4760_groups), 614 .functions = jz4760_functions, 615 .num_functions = ARRAY_SIZE(jz4760_functions), 616 .pull_ups = jz4760_pull_ups, 617 .pull_downs = jz4760_pull_downs, 618 }; 619 620 static const u32 jz4770_pull_ups[6] = { 621 0x3fffffff, 0xfff0030c, 0xffffffff, 0xffff4fff, 0xfffffb7c, 0xffa7f00f, 622 }; 623 624 static const u32 jz4770_pull_downs[6] = { 625 0x00000000, 0x000f0c03, 0x00000000, 0x0000b000, 0x00000483, 0x00580ff0, 626 }; 627 628 static int jz4770_uart0_data_pins[] = { 0xa0, 0xa3, }; 629 static int jz4770_uart0_hwflow_pins[] = { 0xa1, 0xa2, }; 630 static int jz4770_uart1_data_pins[] = { 0x7a, 0x7c, }; 631 static int jz4770_uart1_hwflow_pins[] = { 0x7b, 0x7d, }; 632 static int jz4770_uart2_data_pins[] = { 0x5c, 0x5e, }; 633 static int jz4770_uart2_hwflow_pins[] = { 0x5d, 0x5f, }; 634 static int jz4770_uart3_data_pins[] = { 0x6c, 0x85, }; 635 static int jz4770_uart3_hwflow_pins[] = { 0x88, 0x89, }; 636 static int jz4770_mmc0_1bit_a_pins[] = { 0x12, 0x13, 0x14, }; 637 static int jz4770_mmc0_4bit_a_pins[] = { 0x15, 0x16, 0x17, }; 638 static int jz4770_mmc0_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; 639 static int jz4770_mmc0_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; 640 static int jz4770_mmc0_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, }; 641 static int jz4770_mmc1_1bit_d_pins[] = { 0x78, 0x79, 0x74, }; 642 static int jz4770_mmc1_4bit_d_pins[] = { 0x75, 0x76, 0x77, }; 643 static int jz4770_mmc1_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; 644 static int jz4770_mmc1_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; 645 static int jz4770_mmc1_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, }; 646 static int jz4770_mmc2_1bit_b_pins[] = { 0x3c, 0x3d, 0x34, }; 647 static int jz4770_mmc2_4bit_b_pins[] = { 0x35, 0x3e, 0x3f, }; 648 static int jz4770_mmc2_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; 649 static int jz4770_mmc2_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; 650 static int jz4770_mmc2_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, }; 651 static int jz4770_nemc_8bit_data_pins[] = { 652 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 653 }; 654 static int jz4770_nemc_16bit_data_pins[] = { 655 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 656 }; 657 static int jz4770_nemc_cle_ale_pins[] = { 0x20, 0x21, }; 658 static int jz4770_nemc_addr_pins[] = { 0x22, 0x23, 0x24, 0x25, }; 659 static int jz4770_nemc_rd_we_pins[] = { 0x10, 0x11, }; 660 static int jz4770_nemc_frd_fwe_pins[] = { 0x12, 0x13, }; 661 static int jz4770_nemc_wait_pins[] = { 0x1b, }; 662 static int jz4770_nemc_cs1_pins[] = { 0x15, }; 663 static int jz4770_nemc_cs2_pins[] = { 0x16, }; 664 static int jz4770_nemc_cs3_pins[] = { 0x17, }; 665 static int jz4770_nemc_cs4_pins[] = { 0x18, }; 666 static int jz4770_nemc_cs5_pins[] = { 0x19, }; 667 static int jz4770_nemc_cs6_pins[] = { 0x1a, }; 668 static int jz4770_i2c0_pins[] = { 0x7e, 0x7f, }; 669 static int jz4770_i2c1_pins[] = { 0x9e, 0x9f, }; 670 static int jz4770_i2c2_pins[] = { 0xb0, 0xb1, }; 671 static int jz4770_cim_8bit_pins[] = { 672 0x26, 0x27, 0x28, 0x29, 673 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31, 674 }; 675 static int jz4770_cim_12bit_pins[] = { 676 0x32, 0x33, 0xb0, 0xb1, 677 }; 678 static int jz4770_lcd_24bit_pins[] = { 679 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 680 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, 681 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 682 0x58, 0x59, 0x5a, 0x5b, 683 }; 684 static int jz4770_pwm_pwm0_pins[] = { 0x80, }; 685 static int jz4770_pwm_pwm1_pins[] = { 0x81, }; 686 static int jz4770_pwm_pwm2_pins[] = { 0x82, }; 687 static int jz4770_pwm_pwm3_pins[] = { 0x83, }; 688 static int jz4770_pwm_pwm4_pins[] = { 0x84, }; 689 static int jz4770_pwm_pwm5_pins[] = { 0x85, }; 690 static int jz4770_pwm_pwm6_pins[] = { 0x6a, }; 691 static int jz4770_pwm_pwm7_pins[] = { 0x6b, }; 692 static int jz4770_mac_rmii_pins[] = { 693 0xa9, 0xab, 0xaa, 0xac, 0xa5, 0xa4, 0xad, 0xae, 0xa6, 0xa8, 694 }; 695 static int jz4770_mac_mii_pins[] = { 0xa7, 0xaf, }; 696 static int jz4770_otg_pins[] = { 0x8a, }; 697 698 static int jz4770_uart0_data_funcs[] = { 0, 0, }; 699 static int jz4770_uart0_hwflow_funcs[] = { 0, 0, }; 700 static int jz4770_uart1_data_funcs[] = { 0, 0, }; 701 static int jz4770_uart1_hwflow_funcs[] = { 0, 0, }; 702 static int jz4770_uart2_data_funcs[] = { 0, 0, }; 703 static int jz4770_uart2_hwflow_funcs[] = { 0, 0, }; 704 static int jz4770_uart3_data_funcs[] = { 0, 1, }; 705 static int jz4770_uart3_hwflow_funcs[] = { 0, 0, }; 706 static int jz4770_mmc0_1bit_a_funcs[] = { 1, 1, 0, }; 707 static int jz4770_mmc0_4bit_a_funcs[] = { 1, 1, 1, }; 708 static int jz4770_mmc0_1bit_e_funcs[] = { 0, 0, 0, }; 709 static int jz4770_mmc0_4bit_e_funcs[] = { 0, 0, 0, }; 710 static int jz4770_mmc0_8bit_e_funcs[] = { 0, 0, 0, 0, }; 711 static int jz4770_mmc1_1bit_d_funcs[] = { 0, 0, 0, }; 712 static int jz4770_mmc1_4bit_d_funcs[] = { 0, 0, 0, }; 713 static int jz4770_mmc1_1bit_e_funcs[] = { 1, 1, 1, }; 714 static int jz4770_mmc1_4bit_e_funcs[] = { 1, 1, 1, }; 715 static int jz4770_mmc1_8bit_e_funcs[] = { 1, 1, 1, 1, }; 716 static int jz4770_mmc2_1bit_b_funcs[] = { 0, 0, 0, }; 717 static int jz4770_mmc2_4bit_b_funcs[] = { 0, 0, 0, }; 718 static int jz4770_mmc2_1bit_e_funcs[] = { 2, 2, 2, }; 719 static int jz4770_mmc2_4bit_e_funcs[] = { 2, 2, 2, }; 720 static int jz4770_mmc2_8bit_e_funcs[] = { 2, 2, 2, 2, }; 721 static int jz4770_nemc_8bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, }; 722 static int jz4770_nemc_16bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, }; 723 static int jz4770_nemc_cle_ale_funcs[] = { 0, 0, }; 724 static int jz4770_nemc_addr_funcs[] = { 0, 0, 0, 0, }; 725 static int jz4770_nemc_rd_we_funcs[] = { 0, 0, }; 726 static int jz4770_nemc_frd_fwe_funcs[] = { 0, 0, }; 727 static int jz4770_nemc_wait_funcs[] = { 0, }; 728 static int jz4770_nemc_cs1_funcs[] = { 0, }; 729 static int jz4770_nemc_cs2_funcs[] = { 0, }; 730 static int jz4770_nemc_cs3_funcs[] = { 0, }; 731 static int jz4770_nemc_cs4_funcs[] = { 0, }; 732 static int jz4770_nemc_cs5_funcs[] = { 0, }; 733 static int jz4770_nemc_cs6_funcs[] = { 0, }; 734 static int jz4770_i2c0_funcs[] = { 0, 0, }; 735 static int jz4770_i2c1_funcs[] = { 0, 0, }; 736 static int jz4770_i2c2_funcs[] = { 2, 2, }; 737 static int jz4770_cim_8bit_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; 738 static int jz4770_cim_12bit_funcs[] = { 0, 0, 0, 0, }; 739 static int jz4770_lcd_24bit_funcs[] = { 740 0, 0, 0, 0, 0, 0, 0, 0, 741 0, 0, 0, 0, 0, 0, 0, 0, 742 0, 0, 0, 0, 0, 0, 0, 0, 743 0, 0, 0, 0, 744 }; 745 static int jz4770_pwm_pwm0_funcs[] = { 0, }; 746 static int jz4770_pwm_pwm1_funcs[] = { 0, }; 747 static int jz4770_pwm_pwm2_funcs[] = { 0, }; 748 static int jz4770_pwm_pwm3_funcs[] = { 0, }; 749 static int jz4770_pwm_pwm4_funcs[] = { 0, }; 750 static int jz4770_pwm_pwm5_funcs[] = { 0, }; 751 static int jz4770_pwm_pwm6_funcs[] = { 0, }; 752 static int jz4770_pwm_pwm7_funcs[] = { 0, }; 753 static int jz4770_mac_rmii_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; 754 static int jz4770_mac_mii_funcs[] = { 0, 0, }; 755 static int jz4770_otg_funcs[] = { 0, }; 756 757 static const struct group_desc jz4770_groups[] = { 758 INGENIC_PIN_GROUP("uart0-data", jz4770_uart0_data), 759 INGENIC_PIN_GROUP("uart0-hwflow", jz4770_uart0_hwflow), 760 INGENIC_PIN_GROUP("uart1-data", jz4770_uart1_data), 761 INGENIC_PIN_GROUP("uart1-hwflow", jz4770_uart1_hwflow), 762 INGENIC_PIN_GROUP("uart2-data", jz4770_uart2_data), 763 INGENIC_PIN_GROUP("uart2-hwflow", jz4770_uart2_hwflow), 764 INGENIC_PIN_GROUP("uart3-data", jz4770_uart3_data), 765 INGENIC_PIN_GROUP("uart3-hwflow", jz4770_uart3_hwflow), 766 INGENIC_PIN_GROUP("mmc0-1bit-a", jz4770_mmc0_1bit_a), 767 INGENIC_PIN_GROUP("mmc0-4bit-a", jz4770_mmc0_4bit_a), 768 INGENIC_PIN_GROUP("mmc0-1bit-e", jz4770_mmc0_1bit_e), 769 INGENIC_PIN_GROUP("mmc0-4bit-e", jz4770_mmc0_4bit_e), 770 INGENIC_PIN_GROUP("mmc0-8bit-e", jz4770_mmc0_8bit_e), 771 INGENIC_PIN_GROUP("mmc1-1bit-d", jz4770_mmc1_1bit_d), 772 INGENIC_PIN_GROUP("mmc1-4bit-d", jz4770_mmc1_4bit_d), 773 INGENIC_PIN_GROUP("mmc1-1bit-e", jz4770_mmc1_1bit_e), 774 INGENIC_PIN_GROUP("mmc1-4bit-e", jz4770_mmc1_4bit_e), 775 INGENIC_PIN_GROUP("mmc1-8bit-e", jz4770_mmc1_8bit_e), 776 INGENIC_PIN_GROUP("mmc2-1bit-b", jz4770_mmc2_1bit_b), 777 INGENIC_PIN_GROUP("mmc2-4bit-b", jz4770_mmc2_4bit_b), 778 INGENIC_PIN_GROUP("mmc2-1bit-e", jz4770_mmc2_1bit_e), 779 INGENIC_PIN_GROUP("mmc2-4bit-e", jz4770_mmc2_4bit_e), 780 INGENIC_PIN_GROUP("mmc2-8bit-e", jz4770_mmc2_8bit_e), 781 INGENIC_PIN_GROUP("nemc-8bit-data", jz4770_nemc_8bit_data), 782 INGENIC_PIN_GROUP("nemc-16bit-data", jz4770_nemc_16bit_data), 783 INGENIC_PIN_GROUP("nemc-cle-ale", jz4770_nemc_cle_ale), 784 INGENIC_PIN_GROUP("nemc-addr", jz4770_nemc_addr), 785 INGENIC_PIN_GROUP("nemc-rd-we", jz4770_nemc_rd_we), 786 INGENIC_PIN_GROUP("nemc-frd-fwe", jz4770_nemc_frd_fwe), 787 INGENIC_PIN_GROUP("nemc-wait", jz4770_nemc_wait), 788 INGENIC_PIN_GROUP("nemc-cs1", jz4770_nemc_cs1), 789 INGENIC_PIN_GROUP("nemc-cs2", jz4770_nemc_cs2), 790 INGENIC_PIN_GROUP("nemc-cs3", jz4770_nemc_cs3), 791 INGENIC_PIN_GROUP("nemc-cs4", jz4770_nemc_cs4), 792 INGENIC_PIN_GROUP("nemc-cs5", jz4770_nemc_cs5), 793 INGENIC_PIN_GROUP("nemc-cs6", jz4770_nemc_cs6), 794 INGENIC_PIN_GROUP("i2c0-data", jz4770_i2c0), 795 INGENIC_PIN_GROUP("i2c1-data", jz4770_i2c1), 796 INGENIC_PIN_GROUP("i2c2-data", jz4770_i2c2), 797 INGENIC_PIN_GROUP("cim-data-8bit", jz4770_cim_8bit), 798 INGENIC_PIN_GROUP("cim-data-12bit", jz4770_cim_12bit), 799 INGENIC_PIN_GROUP("lcd-24bit", jz4770_lcd_24bit), 800 { "lcd-no-pins", }, 801 INGENIC_PIN_GROUP("pwm0", jz4770_pwm_pwm0), 802 INGENIC_PIN_GROUP("pwm1", jz4770_pwm_pwm1), 803 INGENIC_PIN_GROUP("pwm2", jz4770_pwm_pwm2), 804 INGENIC_PIN_GROUP("pwm3", jz4770_pwm_pwm3), 805 INGENIC_PIN_GROUP("pwm4", jz4770_pwm_pwm4), 806 INGENIC_PIN_GROUP("pwm5", jz4770_pwm_pwm5), 807 INGENIC_PIN_GROUP("pwm6", jz4770_pwm_pwm6), 808 INGENIC_PIN_GROUP("pwm7", jz4770_pwm_pwm7), 809 INGENIC_PIN_GROUP("mac-rmii", jz4770_mac_rmii), 810 INGENIC_PIN_GROUP("mac-mii", jz4770_mac_mii), 811 INGENIC_PIN_GROUP("otg-vbus", jz4770_otg), 812 }; 813 814 static const char *jz4770_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; 815 static const char *jz4770_uart1_groups[] = { "uart1-data", "uart1-hwflow", }; 816 static const char *jz4770_uart2_groups[] = { "uart2-data", "uart2-hwflow", }; 817 static const char *jz4770_uart3_groups[] = { "uart3-data", "uart3-hwflow", }; 818 static const char *jz4770_mmc0_groups[] = { 819 "mmc0-1bit-a", "mmc0-4bit-a", 820 "mmc0-1bit-e", "mmc0-4bit-e", "mmc0-8bit-e", 821 }; 822 static const char *jz4770_mmc1_groups[] = { 823 "mmc1-1bit-d", "mmc1-4bit-d", 824 "mmc1-1bit-e", "mmc1-4bit-e", "mmc1-8bit-e", 825 }; 826 static const char *jz4770_mmc2_groups[] = { 827 "mmc2-1bit-b", "mmc2-4bit-b", 828 "mmc2-1bit-e", "mmc2-4bit-e", "mmc2-8bit-e", 829 }; 830 static const char *jz4770_nemc_groups[] = { 831 "nemc-8bit-data", "nemc-16bit-data", "nemc-cle-ale", 832 "nemc-addr", "nemc-rd-we", "nemc-frd-fwe", "nemc-wait", 833 }; 834 static const char *jz4770_cs1_groups[] = { "nemc-cs1", }; 835 static const char *jz4770_cs2_groups[] = { "nemc-cs2", }; 836 static const char *jz4770_cs3_groups[] = { "nemc-cs3", }; 837 static const char *jz4770_cs4_groups[] = { "nemc-cs4", }; 838 static const char *jz4770_cs5_groups[] = { "nemc-cs5", }; 839 static const char *jz4770_cs6_groups[] = { "nemc-cs6", }; 840 static const char *jz4770_i2c0_groups[] = { "i2c0-data", }; 841 static const char *jz4770_i2c1_groups[] = { "i2c1-data", }; 842 static const char *jz4770_i2c2_groups[] = { "i2c2-data", }; 843 static const char *jz4770_cim_groups[] = { "cim-data-8bit", "cim-data-12bit", }; 844 static const char *jz4770_lcd_groups[] = { "lcd-24bit", "lcd-no-pins", }; 845 static const char *jz4770_pwm0_groups[] = { "pwm0", }; 846 static const char *jz4770_pwm1_groups[] = { "pwm1", }; 847 static const char *jz4770_pwm2_groups[] = { "pwm2", }; 848 static const char *jz4770_pwm3_groups[] = { "pwm3", }; 849 static const char *jz4770_pwm4_groups[] = { "pwm4", }; 850 static const char *jz4770_pwm5_groups[] = { "pwm5", }; 851 static const char *jz4770_pwm6_groups[] = { "pwm6", }; 852 static const char *jz4770_pwm7_groups[] = { "pwm7", }; 853 static const char *jz4770_mac_groups[] = { "mac-rmii", "mac-mii", }; 854 static const char *jz4770_otg_groups[] = { "otg-vbus", }; 855 856 static const struct function_desc jz4770_functions[] = { 857 { "uart0", jz4770_uart0_groups, ARRAY_SIZE(jz4770_uart0_groups), }, 858 { "uart1", jz4770_uart1_groups, ARRAY_SIZE(jz4770_uart1_groups), }, 859 { "uart2", jz4770_uart2_groups, ARRAY_SIZE(jz4770_uart2_groups), }, 860 { "uart3", jz4770_uart3_groups, ARRAY_SIZE(jz4770_uart3_groups), }, 861 { "mmc0", jz4770_mmc0_groups, ARRAY_SIZE(jz4770_mmc0_groups), }, 862 { "mmc1", jz4770_mmc1_groups, ARRAY_SIZE(jz4770_mmc1_groups), }, 863 { "mmc2", jz4770_mmc2_groups, ARRAY_SIZE(jz4770_mmc2_groups), }, 864 { "nemc", jz4770_nemc_groups, ARRAY_SIZE(jz4770_nemc_groups), }, 865 { "nemc-cs1", jz4770_cs1_groups, ARRAY_SIZE(jz4770_cs1_groups), }, 866 { "nemc-cs2", jz4770_cs2_groups, ARRAY_SIZE(jz4770_cs2_groups), }, 867 { "nemc-cs3", jz4770_cs3_groups, ARRAY_SIZE(jz4770_cs3_groups), }, 868 { "nemc-cs4", jz4770_cs4_groups, ARRAY_SIZE(jz4770_cs4_groups), }, 869 { "nemc-cs5", jz4770_cs5_groups, ARRAY_SIZE(jz4770_cs5_groups), }, 870 { "nemc-cs6", jz4770_cs6_groups, ARRAY_SIZE(jz4770_cs6_groups), }, 871 { "i2c0", jz4770_i2c0_groups, ARRAY_SIZE(jz4770_i2c0_groups), }, 872 { "i2c1", jz4770_i2c1_groups, ARRAY_SIZE(jz4770_i2c1_groups), }, 873 { "i2c2", jz4770_i2c2_groups, ARRAY_SIZE(jz4770_i2c2_groups), }, 874 { "cim", jz4770_cim_groups, ARRAY_SIZE(jz4770_cim_groups), }, 875 { "lcd", jz4770_lcd_groups, ARRAY_SIZE(jz4770_lcd_groups), }, 876 { "pwm0", jz4770_pwm0_groups, ARRAY_SIZE(jz4770_pwm0_groups), }, 877 { "pwm1", jz4770_pwm1_groups, ARRAY_SIZE(jz4770_pwm1_groups), }, 878 { "pwm2", jz4770_pwm2_groups, ARRAY_SIZE(jz4770_pwm2_groups), }, 879 { "pwm3", jz4770_pwm3_groups, ARRAY_SIZE(jz4770_pwm3_groups), }, 880 { "pwm4", jz4770_pwm4_groups, ARRAY_SIZE(jz4770_pwm4_groups), }, 881 { "pwm5", jz4770_pwm5_groups, ARRAY_SIZE(jz4770_pwm5_groups), }, 882 { "pwm6", jz4770_pwm6_groups, ARRAY_SIZE(jz4770_pwm6_groups), }, 883 { "pwm7", jz4770_pwm7_groups, ARRAY_SIZE(jz4770_pwm7_groups), }, 884 { "mac", jz4770_mac_groups, ARRAY_SIZE(jz4770_mac_groups), }, 885 { "otg", jz4770_otg_groups, ARRAY_SIZE(jz4770_otg_groups), }, 886 }; 887 888 static const struct ingenic_chip_info jz4770_chip_info = { 889 .num_chips = 6, 890 .reg_offset = 0x100, 891 .version = ID_JZ4770, 892 .groups = jz4770_groups, 893 .num_groups = ARRAY_SIZE(jz4770_groups), 894 .functions = jz4770_functions, 895 .num_functions = ARRAY_SIZE(jz4770_functions), 896 .pull_ups = jz4770_pull_ups, 897 .pull_downs = jz4770_pull_downs, 898 }; 899 900 static int jz4780_uart2_data_pins[] = { 0x66, 0x67, }; 901 static int jz4780_uart2_hwflow_pins[] = { 0x65, 0x64, }; 902 static int jz4780_uart4_data_pins[] = { 0x54, 0x4a, }; 903 static int jz4780_mmc0_8bit_a_pins[] = { 0x04, 0x05, 0x06, 0x07, 0x18, }; 904 static int jz4780_i2c3_pins[] = { 0x6a, 0x6b, }; 905 static int jz4780_i2c4_e_pins[] = { 0x8c, 0x8d, }; 906 static int jz4780_i2c4_f_pins[] = { 0xb9, 0xb8, }; 907 static int jz4780_hdmi_ddc_pins[] = { 0xb9, 0xb8, }; 908 909 static int jz4780_uart2_data_funcs[] = { 1, 1, }; 910 static int jz4780_uart2_hwflow_funcs[] = { 1, 1, }; 911 static int jz4780_uart4_data_funcs[] = { 2, 2, }; 912 static int jz4780_mmc0_8bit_a_funcs[] = { 1, 1, 1, 1, 1, }; 913 static int jz4780_i2c3_funcs[] = { 1, 1, }; 914 static int jz4780_i2c4_e_funcs[] = { 1, 1, }; 915 static int jz4780_i2c4_f_funcs[] = { 1, 1, }; 916 static int jz4780_hdmi_ddc_funcs[] = { 0, 0, }; 917 918 static const struct group_desc jz4780_groups[] = { 919 INGENIC_PIN_GROUP("uart0-data", jz4770_uart0_data), 920 INGENIC_PIN_GROUP("uart0-hwflow", jz4770_uart0_hwflow), 921 INGENIC_PIN_GROUP("uart1-data", jz4770_uart1_data), 922 INGENIC_PIN_GROUP("uart1-hwflow", jz4770_uart1_hwflow), 923 INGENIC_PIN_GROUP("uart2-data", jz4780_uart2_data), 924 INGENIC_PIN_GROUP("uart2-hwflow", jz4780_uart2_hwflow), 925 INGENIC_PIN_GROUP("uart3-data", jz4770_uart3_data), 926 INGENIC_PIN_GROUP("uart3-hwflow", jz4770_uart3_hwflow), 927 INGENIC_PIN_GROUP("uart4-data", jz4780_uart4_data), 928 INGENIC_PIN_GROUP("mmc0-1bit-a", jz4770_mmc0_1bit_a), 929 INGENIC_PIN_GROUP("mmc0-4bit-a", jz4770_mmc0_4bit_a), 930 INGENIC_PIN_GROUP("mmc0-8bit-a", jz4780_mmc0_8bit_a), 931 INGENIC_PIN_GROUP("mmc0-1bit-e", jz4770_mmc0_1bit_e), 932 INGENIC_PIN_GROUP("mmc0-4bit-e", jz4770_mmc0_4bit_e), 933 INGENIC_PIN_GROUP("mmc1-1bit-d", jz4770_mmc1_1bit_d), 934 INGENIC_PIN_GROUP("mmc1-4bit-d", jz4770_mmc1_4bit_d), 935 INGENIC_PIN_GROUP("mmc1-1bit-e", jz4770_mmc1_1bit_e), 936 INGENIC_PIN_GROUP("mmc1-4bit-e", jz4770_mmc1_4bit_e), 937 INGENIC_PIN_GROUP("mmc2-1bit-b", jz4770_mmc2_1bit_b), 938 INGENIC_PIN_GROUP("mmc2-4bit-b", jz4770_mmc2_4bit_b), 939 INGENIC_PIN_GROUP("mmc2-1bit-e", jz4770_mmc2_1bit_e), 940 INGENIC_PIN_GROUP("mmc2-4bit-e", jz4770_mmc2_4bit_e), 941 INGENIC_PIN_GROUP("nemc-data", jz4770_nemc_8bit_data), 942 INGENIC_PIN_GROUP("nemc-cle-ale", jz4770_nemc_cle_ale), 943 INGENIC_PIN_GROUP("nemc-addr", jz4770_nemc_addr), 944 INGENIC_PIN_GROUP("nemc-rd-we", jz4770_nemc_rd_we), 945 INGENIC_PIN_GROUP("nemc-frd-fwe", jz4770_nemc_frd_fwe), 946 INGENIC_PIN_GROUP("nemc-wait", jz4770_nemc_wait), 947 INGENIC_PIN_GROUP("nemc-cs1", jz4770_nemc_cs1), 948 INGENIC_PIN_GROUP("nemc-cs2", jz4770_nemc_cs2), 949 INGENIC_PIN_GROUP("nemc-cs3", jz4770_nemc_cs3), 950 INGENIC_PIN_GROUP("nemc-cs4", jz4770_nemc_cs4), 951 INGENIC_PIN_GROUP("nemc-cs5", jz4770_nemc_cs5), 952 INGENIC_PIN_GROUP("nemc-cs6", jz4770_nemc_cs6), 953 INGENIC_PIN_GROUP("i2c0-data", jz4770_i2c0), 954 INGENIC_PIN_GROUP("i2c1-data", jz4770_i2c1), 955 INGENIC_PIN_GROUP("i2c2-data", jz4770_i2c2), 956 INGENIC_PIN_GROUP("i2c3-data", jz4780_i2c3), 957 INGENIC_PIN_GROUP("i2c4-data-e", jz4780_i2c4_e), 958 INGENIC_PIN_GROUP("i2c4-data-f", jz4780_i2c4_f), 959 INGENIC_PIN_GROUP("hdmi-ddc", jz4780_hdmi_ddc), 960 INGENIC_PIN_GROUP("cim-data", jz4770_cim_8bit), 961 INGENIC_PIN_GROUP("lcd-24bit", jz4770_lcd_24bit), 962 { "lcd-no-pins", }, 963 INGENIC_PIN_GROUP("pwm0", jz4770_pwm_pwm0), 964 INGENIC_PIN_GROUP("pwm1", jz4770_pwm_pwm1), 965 INGENIC_PIN_GROUP("pwm2", jz4770_pwm_pwm2), 966 INGENIC_PIN_GROUP("pwm3", jz4770_pwm_pwm3), 967 INGENIC_PIN_GROUP("pwm4", jz4770_pwm_pwm4), 968 INGENIC_PIN_GROUP("pwm5", jz4770_pwm_pwm5), 969 INGENIC_PIN_GROUP("pwm6", jz4770_pwm_pwm6), 970 INGENIC_PIN_GROUP("pwm7", jz4770_pwm_pwm7), 971 }; 972 973 static const char *jz4780_uart2_groups[] = { "uart2-data", "uart2-hwflow", }; 974 static const char *jz4780_uart4_groups[] = { "uart4-data", }; 975 static const char *jz4780_mmc0_groups[] = { 976 "mmc0-1bit-a", "mmc0-4bit-a", "mmc0-8bit-a", 977 "mmc0-1bit-e", "mmc0-4bit-e", 978 }; 979 static const char *jz4780_mmc1_groups[] = { 980 "mmc1-1bit-d", "mmc1-4bit-d", "mmc1-1bit-e", "mmc1-4bit-e", 981 }; 982 static const char *jz4780_mmc2_groups[] = { 983 "mmc2-1bit-b", "mmc2-4bit-b", "mmc2-1bit-e", "mmc2-4bit-e", 984 }; 985 static const char *jz4780_nemc_groups[] = { 986 "nemc-data", "nemc-cle-ale", "nemc-addr", 987 "nemc-rd-we", "nemc-frd-fwe", "nemc-wait", 988 }; 989 static const char *jz4780_i2c3_groups[] = { "i2c3-data", }; 990 static const char *jz4780_i2c4_groups[] = { "i2c4-data-e", "i2c4-data-f", }; 991 static const char *jz4780_cim_groups[] = { "cim-data", }; 992 static const char *jz4780_hdmi_ddc_groups[] = { "hdmi-ddc", }; 993 994 static const struct function_desc jz4780_functions[] = { 995 { "uart0", jz4770_uart0_groups, ARRAY_SIZE(jz4770_uart0_groups), }, 996 { "uart1", jz4770_uart1_groups, ARRAY_SIZE(jz4770_uart1_groups), }, 997 { "uart2", jz4780_uart2_groups, ARRAY_SIZE(jz4780_uart2_groups), }, 998 { "uart3", jz4770_uart3_groups, ARRAY_SIZE(jz4770_uart3_groups), }, 999 { "uart4", jz4780_uart4_groups, ARRAY_SIZE(jz4780_uart4_groups), }, 1000 { "mmc0", jz4780_mmc0_groups, ARRAY_SIZE(jz4780_mmc0_groups), }, 1001 { "mmc1", jz4780_mmc1_groups, ARRAY_SIZE(jz4780_mmc1_groups), }, 1002 { "mmc2", jz4780_mmc2_groups, ARRAY_SIZE(jz4780_mmc2_groups), }, 1003 { "nemc", jz4780_nemc_groups, ARRAY_SIZE(jz4780_nemc_groups), }, 1004 { "nemc-cs1", jz4770_cs1_groups, ARRAY_SIZE(jz4770_cs1_groups), }, 1005 { "nemc-cs2", jz4770_cs2_groups, ARRAY_SIZE(jz4770_cs2_groups), }, 1006 { "nemc-cs3", jz4770_cs3_groups, ARRAY_SIZE(jz4770_cs3_groups), }, 1007 { "nemc-cs4", jz4770_cs4_groups, ARRAY_SIZE(jz4770_cs4_groups), }, 1008 { "nemc-cs5", jz4770_cs5_groups, ARRAY_SIZE(jz4770_cs5_groups), }, 1009 { "nemc-cs6", jz4770_cs6_groups, ARRAY_SIZE(jz4770_cs6_groups), }, 1010 { "i2c0", jz4770_i2c0_groups, ARRAY_SIZE(jz4770_i2c0_groups), }, 1011 { "i2c1", jz4770_i2c1_groups, ARRAY_SIZE(jz4770_i2c1_groups), }, 1012 { "i2c2", jz4770_i2c2_groups, ARRAY_SIZE(jz4770_i2c2_groups), }, 1013 { "i2c3", jz4780_i2c3_groups, ARRAY_SIZE(jz4780_i2c3_groups), }, 1014 { "i2c4", jz4780_i2c4_groups, ARRAY_SIZE(jz4780_i2c4_groups), }, 1015 { "cim", jz4780_cim_groups, ARRAY_SIZE(jz4780_cim_groups), }, 1016 { "lcd", jz4770_lcd_groups, ARRAY_SIZE(jz4770_lcd_groups), }, 1017 { "pwm0", jz4770_pwm0_groups, ARRAY_SIZE(jz4770_pwm0_groups), }, 1018 { "pwm1", jz4770_pwm1_groups, ARRAY_SIZE(jz4770_pwm1_groups), }, 1019 { "pwm2", jz4770_pwm2_groups, ARRAY_SIZE(jz4770_pwm2_groups), }, 1020 { "pwm3", jz4770_pwm3_groups, ARRAY_SIZE(jz4770_pwm3_groups), }, 1021 { "pwm4", jz4770_pwm4_groups, ARRAY_SIZE(jz4770_pwm4_groups), }, 1022 { "pwm5", jz4770_pwm5_groups, ARRAY_SIZE(jz4770_pwm5_groups), }, 1023 { "pwm6", jz4770_pwm6_groups, ARRAY_SIZE(jz4770_pwm6_groups), }, 1024 { "pwm7", jz4770_pwm7_groups, ARRAY_SIZE(jz4770_pwm7_groups), }, 1025 { "hdmi-ddc", jz4780_hdmi_ddc_groups, 1026 ARRAY_SIZE(jz4780_hdmi_ddc_groups), }, 1027 }; 1028 1029 static const struct ingenic_chip_info jz4780_chip_info = { 1030 .num_chips = 6, 1031 .reg_offset = 0x100, 1032 .version = ID_JZ4780, 1033 .groups = jz4780_groups, 1034 .num_groups = ARRAY_SIZE(jz4780_groups), 1035 .functions = jz4780_functions, 1036 .num_functions = ARRAY_SIZE(jz4780_functions), 1037 .pull_ups = jz4770_pull_ups, 1038 .pull_downs = jz4770_pull_downs, 1039 }; 1040 1041 static const u32 x1000_pull_ups[4] = { 1042 0xffffffff, 0xfdffffff, 0x0dffffff, 0x0000003f, 1043 }; 1044 1045 static const u32 x1000_pull_downs[4] = { 1046 0x00000000, 0x02000000, 0x02000000, 0x00000000, 1047 }; 1048 1049 static int x1000_uart0_data_pins[] = { 0x4a, 0x4b, }; 1050 static int x1000_uart0_hwflow_pins[] = { 0x4c, 0x4d, }; 1051 static int x1000_uart1_data_a_pins[] = { 0x04, 0x05, }; 1052 static int x1000_uart1_data_d_pins[] = { 0x62, 0x63, }; 1053 static int x1000_uart1_hwflow_pins[] = { 0x64, 0x65, }; 1054 static int x1000_uart2_data_a_pins[] = { 0x02, 0x03, }; 1055 static int x1000_uart2_data_d_pins[] = { 0x65, 0x64, }; 1056 static int x1000_sfc_pins[] = { 0x1d, 0x1c, 0x1e, 0x1f, 0x1a, 0x1b, }; 1057 static int x1000_ssi_dt_a_22_pins[] = { 0x16, }; 1058 static int x1000_ssi_dt_a_29_pins[] = { 0x1d, }; 1059 static int x1000_ssi_dt_d_pins[] = { 0x62, }; 1060 static int x1000_ssi_dr_a_23_pins[] = { 0x17, }; 1061 static int x1000_ssi_dr_a_28_pins[] = { 0x1c, }; 1062 static int x1000_ssi_dr_d_pins[] = { 0x63, }; 1063 static int x1000_ssi_clk_a_24_pins[] = { 0x18, }; 1064 static int x1000_ssi_clk_a_26_pins[] = { 0x1a, }; 1065 static int x1000_ssi_clk_d_pins[] = { 0x60, }; 1066 static int x1000_ssi_gpc_a_20_pins[] = { 0x14, }; 1067 static int x1000_ssi_gpc_a_31_pins[] = { 0x1f, }; 1068 static int x1000_ssi_ce0_a_25_pins[] = { 0x19, }; 1069 static int x1000_ssi_ce0_a_27_pins[] = { 0x1b, }; 1070 static int x1000_ssi_ce0_d_pins[] = { 0x61, }; 1071 static int x1000_ssi_ce1_a_21_pins[] = { 0x15, }; 1072 static int x1000_ssi_ce1_a_30_pins[] = { 0x1e, }; 1073 static int x1000_mmc0_1bit_pins[] = { 0x18, 0x19, 0x17, }; 1074 static int x1000_mmc0_4bit_pins[] = { 0x16, 0x15, 0x14, }; 1075 static int x1000_mmc0_8bit_pins[] = { 0x13, 0x12, 0x11, 0x10, }; 1076 static int x1000_mmc1_1bit_pins[] = { 0x40, 0x41, 0x42, }; 1077 static int x1000_mmc1_4bit_pins[] = { 0x43, 0x44, 0x45, }; 1078 static int x1000_emc_8bit_data_pins[] = { 1079 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 1080 }; 1081 static int x1000_emc_16bit_data_pins[] = { 1082 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 1083 }; 1084 static int x1000_emc_addr_pins[] = { 1085 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 1086 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 1087 }; 1088 static int x1000_emc_rd_we_pins[] = { 0x30, 0x31, }; 1089 static int x1000_emc_wait_pins[] = { 0x34, }; 1090 static int x1000_emc_cs1_pins[] = { 0x32, }; 1091 static int x1000_emc_cs2_pins[] = { 0x33, }; 1092 static int x1000_i2c0_pins[] = { 0x38, 0x37, }; 1093 static int x1000_i2c1_a_pins[] = { 0x01, 0x00, }; 1094 static int x1000_i2c1_c_pins[] = { 0x5b, 0x5a, }; 1095 static int x1000_i2c2_pins[] = { 0x61, 0x60, }; 1096 static int x1000_cim_pins[] = { 1097 0x08, 0x09, 0x0a, 0x0b, 1098 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 0x0d, 0x0c, 1099 }; 1100 static int x1000_lcd_8bit_pins[] = { 1101 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 1102 0x30, 0x31, 0x32, 0x33, 0x34, 1103 }; 1104 static int x1000_lcd_16bit_pins[] = { 1105 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 1106 }; 1107 static int x1000_pwm_pwm0_pins[] = { 0x59, }; 1108 static int x1000_pwm_pwm1_pins[] = { 0x5a, }; 1109 static int x1000_pwm_pwm2_pins[] = { 0x5b, }; 1110 static int x1000_pwm_pwm3_pins[] = { 0x26, }; 1111 static int x1000_pwm_pwm4_pins[] = { 0x58, }; 1112 static int x1000_mac_pins[] = { 1113 0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x26, 1114 }; 1115 1116 static int x1000_uart0_data_funcs[] = { 0, 0, }; 1117 static int x1000_uart0_hwflow_funcs[] = { 0, 0, }; 1118 static int x1000_uart1_data_a_funcs[] = { 2, 2, }; 1119 static int x1000_uart1_data_d_funcs[] = { 1, 1, }; 1120 static int x1000_uart1_hwflow_funcs[] = { 1, 1, }; 1121 static int x1000_uart2_data_a_funcs[] = { 2, 2, }; 1122 static int x1000_uart2_data_d_funcs[] = { 0, 0, }; 1123 static int x1000_sfc_funcs[] = { 1, 1, 1, 1, 1, 1, }; 1124 static int x1000_ssi_dt_a_22_funcs[] = { 2, }; 1125 static int x1000_ssi_dt_a_29_funcs[] = { 2, }; 1126 static int x1000_ssi_dt_d_funcs[] = { 0, }; 1127 static int x1000_ssi_dr_a_23_funcs[] = { 2, }; 1128 static int x1000_ssi_dr_a_28_funcs[] = { 2, }; 1129 static int x1000_ssi_dr_d_funcs[] = { 0, }; 1130 static int x1000_ssi_clk_a_24_funcs[] = { 2, }; 1131 static int x1000_ssi_clk_a_26_funcs[] = { 2, }; 1132 static int x1000_ssi_clk_d_funcs[] = { 0, }; 1133 static int x1000_ssi_gpc_a_20_funcs[] = { 2, }; 1134 static int x1000_ssi_gpc_a_31_funcs[] = { 2, }; 1135 static int x1000_ssi_ce0_a_25_funcs[] = { 2, }; 1136 static int x1000_ssi_ce0_a_27_funcs[] = { 2, }; 1137 static int x1000_ssi_ce0_d_funcs[] = { 0, }; 1138 static int x1000_ssi_ce1_a_21_funcs[] = { 2, }; 1139 static int x1000_ssi_ce1_a_30_funcs[] = { 2, }; 1140 static int x1000_mmc0_1bit_funcs[] = { 1, 1, 1, }; 1141 static int x1000_mmc0_4bit_funcs[] = { 1, 1, 1, }; 1142 static int x1000_mmc0_8bit_funcs[] = { 1, 1, 1, 1, 1, }; 1143 static int x1000_mmc1_1bit_funcs[] = { 0, 0, 0, }; 1144 static int x1000_mmc1_4bit_funcs[] = { 0, 0, 0, }; 1145 static int x1000_emc_8bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, }; 1146 static int x1000_emc_16bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, }; 1147 static int x1000_emc_addr_funcs[] = { 1148 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1149 }; 1150 static int x1000_emc_rd_we_funcs[] = { 0, 0, }; 1151 static int x1000_emc_wait_funcs[] = { 0, }; 1152 static int x1000_emc_cs1_funcs[] = { 0, }; 1153 static int x1000_emc_cs2_funcs[] = { 0, }; 1154 static int x1000_i2c0_funcs[] = { 0, 0, }; 1155 static int x1000_i2c1_a_funcs[] = { 2, 2, }; 1156 static int x1000_i2c1_c_funcs[] = { 0, 0, }; 1157 static int x1000_i2c2_funcs[] = { 1, 1, }; 1158 static int x1000_cim_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, }; 1159 static int x1000_lcd_8bit_funcs[] = { 1160 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1161 }; 1162 static int x1000_lcd_16bit_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, }; 1163 static int x1000_pwm_pwm0_funcs[] = { 0, }; 1164 static int x1000_pwm_pwm1_funcs[] = { 1, }; 1165 static int x1000_pwm_pwm2_funcs[] = { 1, }; 1166 static int x1000_pwm_pwm3_funcs[] = { 2, }; 1167 static int x1000_pwm_pwm4_funcs[] = { 0, }; 1168 static int x1000_mac_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; 1169 1170 static const struct group_desc x1000_groups[] = { 1171 INGENIC_PIN_GROUP("uart0-data", x1000_uart0_data), 1172 INGENIC_PIN_GROUP("uart0-hwflow", x1000_uart0_hwflow), 1173 INGENIC_PIN_GROUP("uart1-data-a", x1000_uart1_data_a), 1174 INGENIC_PIN_GROUP("uart1-data-d", x1000_uart1_data_d), 1175 INGENIC_PIN_GROUP("uart1-hwflow", x1000_uart1_hwflow), 1176 INGENIC_PIN_GROUP("uart2-data-a", x1000_uart2_data_a), 1177 INGENIC_PIN_GROUP("uart2-data-d", x1000_uart2_data_d), 1178 INGENIC_PIN_GROUP("sfc", x1000_sfc), 1179 INGENIC_PIN_GROUP("ssi-dt-a-22", x1000_ssi_dt_a_22), 1180 INGENIC_PIN_GROUP("ssi-dt-a-29", x1000_ssi_dt_a_29), 1181 INGENIC_PIN_GROUP("ssi-dt-d", x1000_ssi_dt_d), 1182 INGENIC_PIN_GROUP("ssi-dr-a-23", x1000_ssi_dr_a_23), 1183 INGENIC_PIN_GROUP("ssi-dr-a-28", x1000_ssi_dr_a_28), 1184 INGENIC_PIN_GROUP("ssi-dr-d", x1000_ssi_dr_d), 1185 INGENIC_PIN_GROUP("ssi-clk-a-24", x1000_ssi_clk_a_24), 1186 INGENIC_PIN_GROUP("ssi-clk-a-26", x1000_ssi_clk_a_26), 1187 INGENIC_PIN_GROUP("ssi-clk-d", x1000_ssi_clk_d), 1188 INGENIC_PIN_GROUP("ssi-gpc-a-20", x1000_ssi_gpc_a_20), 1189 INGENIC_PIN_GROUP("ssi-gpc-a-31", x1000_ssi_gpc_a_31), 1190 INGENIC_PIN_GROUP("ssi-ce0-a-25", x1000_ssi_ce0_a_25), 1191 INGENIC_PIN_GROUP("ssi-ce0-a-27", x1000_ssi_ce0_a_27), 1192 INGENIC_PIN_GROUP("ssi-ce0-d", x1000_ssi_ce0_d), 1193 INGENIC_PIN_GROUP("ssi-ce1-a-21", x1000_ssi_ce1_a_21), 1194 INGENIC_PIN_GROUP("ssi-ce1-a-30", x1000_ssi_ce1_a_30), 1195 INGENIC_PIN_GROUP("mmc0-1bit", x1000_mmc0_1bit), 1196 INGENIC_PIN_GROUP("mmc0-4bit", x1000_mmc0_4bit), 1197 INGENIC_PIN_GROUP("mmc0-8bit", x1000_mmc0_8bit), 1198 INGENIC_PIN_GROUP("mmc1-1bit", x1000_mmc1_1bit), 1199 INGENIC_PIN_GROUP("mmc1-4bit", x1000_mmc1_4bit), 1200 INGENIC_PIN_GROUP("emc-8bit-data", x1000_emc_8bit_data), 1201 INGENIC_PIN_GROUP("emc-16bit-data", x1000_emc_16bit_data), 1202 INGENIC_PIN_GROUP("emc-addr", x1000_emc_addr), 1203 INGENIC_PIN_GROUP("emc-rd-we", x1000_emc_rd_we), 1204 INGENIC_PIN_GROUP("emc-wait", x1000_emc_wait), 1205 INGENIC_PIN_GROUP("emc-cs1", x1000_emc_cs1), 1206 INGENIC_PIN_GROUP("emc-cs2", x1000_emc_cs2), 1207 INGENIC_PIN_GROUP("i2c0-data", x1000_i2c0), 1208 INGENIC_PIN_GROUP("i2c1-data-a", x1000_i2c1_a), 1209 INGENIC_PIN_GROUP("i2c1-data-c", x1000_i2c1_c), 1210 INGENIC_PIN_GROUP("i2c2-data", x1000_i2c2), 1211 INGENIC_PIN_GROUP("cim-data", x1000_cim), 1212 INGENIC_PIN_GROUP("lcd-8bit", x1000_lcd_8bit), 1213 INGENIC_PIN_GROUP("lcd-16bit", x1000_lcd_16bit), 1214 { "lcd-no-pins", }, 1215 INGENIC_PIN_GROUP("pwm0", x1000_pwm_pwm0), 1216 INGENIC_PIN_GROUP("pwm1", x1000_pwm_pwm1), 1217 INGENIC_PIN_GROUP("pwm2", x1000_pwm_pwm2), 1218 INGENIC_PIN_GROUP("pwm3", x1000_pwm_pwm3), 1219 INGENIC_PIN_GROUP("pwm4", x1000_pwm_pwm4), 1220 INGENIC_PIN_GROUP("mac", x1000_mac), 1221 }; 1222 1223 static const char *x1000_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; 1224 static const char *x1000_uart1_groups[] = { 1225 "uart1-data-a", "uart1-data-d", "uart1-hwflow", 1226 }; 1227 static const char *x1000_uart2_groups[] = { "uart2-data-a", "uart2-data-d", }; 1228 static const char *x1000_sfc_groups[] = { "sfc", }; 1229 static const char *x1000_ssi_groups[] = { 1230 "ssi-dt-a-22", "ssi-dt-a-29", "ssi-dt-d", 1231 "ssi-dr-a-23", "ssi-dr-a-28", "ssi-dr-d", 1232 "ssi-clk-a-24", "ssi-clk-a-26", "ssi-clk-d", 1233 "ssi-gpc-a-20", "ssi-gpc-a-31", 1234 "ssi-ce0-a-25", "ssi-ce0-a-27", "ssi-ce0-d", 1235 "ssi-ce1-a-21", "ssi-ce1-a-30", 1236 }; 1237 static const char *x1000_mmc0_groups[] = { 1238 "mmc0-1bit", "mmc0-4bit", "mmc0-8bit", 1239 }; 1240 static const char *x1000_mmc1_groups[] = { 1241 "mmc1-1bit", "mmc1-4bit", 1242 }; 1243 static const char *x1000_emc_groups[] = { 1244 "emc-8bit-data", "emc-16bit-data", 1245 "emc-addr", "emc-rd-we", "emc-wait", 1246 }; 1247 static const char *x1000_cs1_groups[] = { "emc-cs1", }; 1248 static const char *x1000_cs2_groups[] = { "emc-cs2", }; 1249 static const char *x1000_i2c0_groups[] = { "i2c0-data", }; 1250 static const char *x1000_i2c1_groups[] = { "i2c1-data-a", "i2c1-data-c", }; 1251 static const char *x1000_i2c2_groups[] = { "i2c2-data", }; 1252 static const char *x1000_cim_groups[] = { "cim-data", }; 1253 static const char *x1000_lcd_groups[] = { 1254 "lcd-8bit", "lcd-16bit", "lcd-no-pins", 1255 }; 1256 static const char *x1000_pwm0_groups[] = { "pwm0", }; 1257 static const char *x1000_pwm1_groups[] = { "pwm1", }; 1258 static const char *x1000_pwm2_groups[] = { "pwm2", }; 1259 static const char *x1000_pwm3_groups[] = { "pwm3", }; 1260 static const char *x1000_pwm4_groups[] = { "pwm4", }; 1261 static const char *x1000_mac_groups[] = { "mac", }; 1262 1263 static const struct function_desc x1000_functions[] = { 1264 { "uart0", x1000_uart0_groups, ARRAY_SIZE(x1000_uart0_groups), }, 1265 { "uart1", x1000_uart1_groups, ARRAY_SIZE(x1000_uart1_groups), }, 1266 { "uart2", x1000_uart2_groups, ARRAY_SIZE(x1000_uart2_groups), }, 1267 { "sfc", x1000_sfc_groups, ARRAY_SIZE(x1000_sfc_groups), }, 1268 { "ssi", x1000_ssi_groups, ARRAY_SIZE(x1000_ssi_groups), }, 1269 { "mmc0", x1000_mmc0_groups, ARRAY_SIZE(x1000_mmc0_groups), }, 1270 { "mmc1", x1000_mmc1_groups, ARRAY_SIZE(x1000_mmc1_groups), }, 1271 { "emc", x1000_emc_groups, ARRAY_SIZE(x1000_emc_groups), }, 1272 { "emc-cs1", x1000_cs1_groups, ARRAY_SIZE(x1000_cs1_groups), }, 1273 { "emc-cs2", x1000_cs2_groups, ARRAY_SIZE(x1000_cs2_groups), }, 1274 { "i2c0", x1000_i2c0_groups, ARRAY_SIZE(x1000_i2c0_groups), }, 1275 { "i2c1", x1000_i2c1_groups, ARRAY_SIZE(x1000_i2c1_groups), }, 1276 { "i2c2", x1000_i2c2_groups, ARRAY_SIZE(x1000_i2c2_groups), }, 1277 { "cim", x1000_cim_groups, ARRAY_SIZE(x1000_cim_groups), }, 1278 { "lcd", x1000_lcd_groups, ARRAY_SIZE(x1000_lcd_groups), }, 1279 { "pwm0", x1000_pwm0_groups, ARRAY_SIZE(x1000_pwm0_groups), }, 1280 { "pwm1", x1000_pwm1_groups, ARRAY_SIZE(x1000_pwm1_groups), }, 1281 { "pwm2", x1000_pwm2_groups, ARRAY_SIZE(x1000_pwm2_groups), }, 1282 { "pwm3", x1000_pwm3_groups, ARRAY_SIZE(x1000_pwm3_groups), }, 1283 { "pwm4", x1000_pwm4_groups, ARRAY_SIZE(x1000_pwm4_groups), }, 1284 { "mac", x1000_mac_groups, ARRAY_SIZE(x1000_mac_groups), }, 1285 }; 1286 1287 static const struct ingenic_chip_info x1000_chip_info = { 1288 .num_chips = 4, 1289 .reg_offset = 0x100, 1290 .version = ID_X1000, 1291 .groups = x1000_groups, 1292 .num_groups = ARRAY_SIZE(x1000_groups), 1293 .functions = x1000_functions, 1294 .num_functions = ARRAY_SIZE(x1000_functions), 1295 .pull_ups = x1000_pull_ups, 1296 .pull_downs = x1000_pull_downs, 1297 }; 1298 1299 static int x1500_uart0_data_pins[] = { 0x4a, 0x4b, }; 1300 static int x1500_uart0_hwflow_pins[] = { 0x4c, 0x4d, }; 1301 static int x1500_uart1_data_a_pins[] = { 0x04, 0x05, }; 1302 static int x1500_uart1_data_d_pins[] = { 0x62, 0x63, }; 1303 static int x1500_uart1_hwflow_pins[] = { 0x64, 0x65, }; 1304 static int x1500_uart2_data_a_pins[] = { 0x02, 0x03, }; 1305 static int x1500_uart2_data_d_pins[] = { 0x65, 0x64, }; 1306 static int x1500_mmc_1bit_pins[] = { 0x18, 0x19, 0x17, }; 1307 static int x1500_mmc_4bit_pins[] = { 0x16, 0x15, 0x14, }; 1308 static int x1500_i2c0_pins[] = { 0x38, 0x37, }; 1309 static int x1500_i2c1_a_pins[] = { 0x01, 0x00, }; 1310 static int x1500_i2c1_c_pins[] = { 0x5b, 0x5a, }; 1311 static int x1500_i2c2_pins[] = { 0x61, 0x60, }; 1312 static int x1500_cim_pins[] = { 1313 0x08, 0x09, 0x0a, 0x0b, 1314 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 0x0d, 0x0c, 1315 }; 1316 static int x1500_pwm_pwm0_pins[] = { 0x59, }; 1317 static int x1500_pwm_pwm1_pins[] = { 0x5a, }; 1318 static int x1500_pwm_pwm2_pins[] = { 0x5b, }; 1319 static int x1500_pwm_pwm3_pins[] = { 0x26, }; 1320 static int x1500_pwm_pwm4_pins[] = { 0x58, }; 1321 1322 static int x1500_uart0_data_funcs[] = { 0, 0, }; 1323 static int x1500_uart0_hwflow_funcs[] = { 0, 0, }; 1324 static int x1500_uart1_data_a_funcs[] = { 2, 2, }; 1325 static int x1500_uart1_data_d_funcs[] = { 1, 1, }; 1326 static int x1500_uart1_hwflow_funcs[] = { 1, 1, }; 1327 static int x1500_uart2_data_a_funcs[] = { 2, 2, }; 1328 static int x1500_uart2_data_d_funcs[] = { 0, 0, }; 1329 static int x1500_mmc_1bit_funcs[] = { 1, 1, 1, }; 1330 static int x1500_mmc_4bit_funcs[] = { 1, 1, 1, }; 1331 static int x1500_i2c0_funcs[] = { 0, 0, }; 1332 static int x1500_i2c1_a_funcs[] = { 2, 2, }; 1333 static int x1500_i2c1_c_funcs[] = { 0, 0, }; 1334 static int x1500_i2c2_funcs[] = { 1, 1, }; 1335 static int x1500_cim_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, }; 1336 static int x1500_pwm_pwm0_funcs[] = { 0, }; 1337 static int x1500_pwm_pwm1_funcs[] = { 1, }; 1338 static int x1500_pwm_pwm2_funcs[] = { 1, }; 1339 static int x1500_pwm_pwm3_funcs[] = { 2, }; 1340 static int x1500_pwm_pwm4_funcs[] = { 0, }; 1341 1342 static const struct group_desc x1500_groups[] = { 1343 INGENIC_PIN_GROUP("uart0-data", x1500_uart0_data), 1344 INGENIC_PIN_GROUP("uart0-hwflow", x1500_uart0_hwflow), 1345 INGENIC_PIN_GROUP("uart1-data-a", x1500_uart1_data_a), 1346 INGENIC_PIN_GROUP("uart1-data-d", x1500_uart1_data_d), 1347 INGENIC_PIN_GROUP("uart1-hwflow", x1500_uart1_hwflow), 1348 INGENIC_PIN_GROUP("uart2-data-a", x1500_uart2_data_a), 1349 INGENIC_PIN_GROUP("uart2-data-d", x1500_uart2_data_d), 1350 INGENIC_PIN_GROUP("sfc", x1000_sfc), 1351 INGENIC_PIN_GROUP("mmc-1bit", x1500_mmc_1bit), 1352 INGENIC_PIN_GROUP("mmc-4bit", x1500_mmc_4bit), 1353 INGENIC_PIN_GROUP("i2c0-data", x1500_i2c0), 1354 INGENIC_PIN_GROUP("i2c1-data-a", x1500_i2c1_a), 1355 INGENIC_PIN_GROUP("i2c1-data-c", x1500_i2c1_c), 1356 INGENIC_PIN_GROUP("i2c2-data", x1500_i2c2), 1357 INGENIC_PIN_GROUP("cim-data", x1500_cim), 1358 { "lcd-no-pins", }, 1359 INGENIC_PIN_GROUP("pwm0", x1500_pwm_pwm0), 1360 INGENIC_PIN_GROUP("pwm1", x1500_pwm_pwm1), 1361 INGENIC_PIN_GROUP("pwm2", x1500_pwm_pwm2), 1362 INGENIC_PIN_GROUP("pwm3", x1500_pwm_pwm3), 1363 INGENIC_PIN_GROUP("pwm4", x1500_pwm_pwm4), 1364 }; 1365 1366 static const char *x1500_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; 1367 static const char *x1500_uart1_groups[] = { 1368 "uart1-data-a", "uart1-data-d", "uart1-hwflow", 1369 }; 1370 static const char *x1500_uart2_groups[] = { "uart2-data-a", "uart2-data-d", }; 1371 static const char *x1500_mmc_groups[] = { "mmc-1bit", "mmc-4bit", }; 1372 static const char *x1500_i2c0_groups[] = { "i2c0-data", }; 1373 static const char *x1500_i2c1_groups[] = { "i2c1-data-a", "i2c1-data-c", }; 1374 static const char *x1500_i2c2_groups[] = { "i2c2-data", }; 1375 static const char *x1500_cim_groups[] = { "cim-data", }; 1376 static const char *x1500_lcd_groups[] = { "lcd-no-pins", }; 1377 static const char *x1500_pwm0_groups[] = { "pwm0", }; 1378 static const char *x1500_pwm1_groups[] = { "pwm1", }; 1379 static const char *x1500_pwm2_groups[] = { "pwm2", }; 1380 static const char *x1500_pwm3_groups[] = { "pwm3", }; 1381 static const char *x1500_pwm4_groups[] = { "pwm4", }; 1382 1383 static const struct function_desc x1500_functions[] = { 1384 { "uart0", x1500_uart0_groups, ARRAY_SIZE(x1500_uart0_groups), }, 1385 { "uart1", x1500_uart1_groups, ARRAY_SIZE(x1500_uart1_groups), }, 1386 { "uart2", x1500_uart2_groups, ARRAY_SIZE(x1500_uart2_groups), }, 1387 { "sfc", x1000_sfc_groups, ARRAY_SIZE(x1000_sfc_groups), }, 1388 { "mmc", x1500_mmc_groups, ARRAY_SIZE(x1500_mmc_groups), }, 1389 { "i2c0", x1500_i2c0_groups, ARRAY_SIZE(x1500_i2c0_groups), }, 1390 { "i2c1", x1500_i2c1_groups, ARRAY_SIZE(x1500_i2c1_groups), }, 1391 { "i2c2", x1500_i2c2_groups, ARRAY_SIZE(x1500_i2c2_groups), }, 1392 { "cim", x1500_cim_groups, ARRAY_SIZE(x1500_cim_groups), }, 1393 { "lcd", x1500_lcd_groups, ARRAY_SIZE(x1500_lcd_groups), }, 1394 { "pwm0", x1500_pwm0_groups, ARRAY_SIZE(x1500_pwm0_groups), }, 1395 { "pwm1", x1500_pwm1_groups, ARRAY_SIZE(x1500_pwm1_groups), }, 1396 { "pwm2", x1500_pwm2_groups, ARRAY_SIZE(x1500_pwm2_groups), }, 1397 { "pwm3", x1500_pwm3_groups, ARRAY_SIZE(x1500_pwm3_groups), }, 1398 { "pwm4", x1500_pwm4_groups, ARRAY_SIZE(x1500_pwm4_groups), }, 1399 }; 1400 1401 static const struct ingenic_chip_info x1500_chip_info = { 1402 .num_chips = 4, 1403 .reg_offset = 0x100, 1404 .version = ID_X1500, 1405 .groups = x1500_groups, 1406 .num_groups = ARRAY_SIZE(x1500_groups), 1407 .functions = x1500_functions, 1408 .num_functions = ARRAY_SIZE(x1500_functions), 1409 .pull_ups = x1000_pull_ups, 1410 .pull_downs = x1000_pull_downs, 1411 }; 1412 1413 static const u32 x1830_pull_ups[4] = { 1414 0x5fdfffc0, 0xffffefff, 0x1ffffbff, 0x0fcff3fc, 1415 }; 1416 1417 static const u32 x1830_pull_downs[4] = { 1418 0x5fdfffc0, 0xffffefff, 0x1ffffbff, 0x0fcff3fc, 1419 }; 1420 1421 static int x1830_uart0_data_pins[] = { 0x33, 0x36, }; 1422 static int x1830_uart0_hwflow_pins[] = { 0x34, 0x35, }; 1423 static int x1830_uart1_data_pins[] = { 0x38, 0x37, }; 1424 static int x1830_sfc_pins[] = { 0x17, 0x18, 0x1a, 0x19, 0x1b, 0x1c, }; 1425 static int x1830_ssi0_dt_pins[] = { 0x4c, }; 1426 static int x1830_ssi0_dr_pins[] = { 0x4b, }; 1427 static int x1830_ssi0_clk_pins[] = { 0x4f, }; 1428 static int x1830_ssi0_gpc_pins[] = { 0x4d, }; 1429 static int x1830_ssi0_ce0_pins[] = { 0x50, }; 1430 static int x1830_ssi0_ce1_pins[] = { 0x4e, }; 1431 static int x1830_ssi1_dt_c_pins[] = { 0x53, }; 1432 static int x1830_ssi1_dr_c_pins[] = { 0x54, }; 1433 static int x1830_ssi1_clk_c_pins[] = { 0x57, }; 1434 static int x1830_ssi1_gpc_c_pins[] = { 0x55, }; 1435 static int x1830_ssi1_ce0_c_pins[] = { 0x58, }; 1436 static int x1830_ssi1_ce1_c_pins[] = { 0x56, }; 1437 static int x1830_ssi1_dt_d_pins[] = { 0x62, }; 1438 static int x1830_ssi1_dr_d_pins[] = { 0x63, }; 1439 static int x1830_ssi1_clk_d_pins[] = { 0x66, }; 1440 static int x1830_ssi1_gpc_d_pins[] = { 0x64, }; 1441 static int x1830_ssi1_ce0_d_pins[] = { 0x67, }; 1442 static int x1830_ssi1_ce1_d_pins[] = { 0x65, }; 1443 static int x1830_mmc0_1bit_pins[] = { 0x24, 0x25, 0x20, }; 1444 static int x1830_mmc0_4bit_pins[] = { 0x21, 0x22, 0x23, }; 1445 static int x1830_mmc1_1bit_pins[] = { 0x42, 0x43, 0x44, }; 1446 static int x1830_mmc1_4bit_pins[] = { 0x45, 0x46, 0x47, }; 1447 static int x1830_i2c0_pins[] = { 0x0c, 0x0d, }; 1448 static int x1830_i2c1_pins[] = { 0x39, 0x3a, }; 1449 static int x1830_i2c2_pins[] = { 0x5b, 0x5c, }; 1450 static int x1830_lcd_rgb_18bit_pins[] = { 1451 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 1452 0x68, 0x69, 0x6c, 0x6d, 0x6e, 0x6f, 1453 0x70, 0x71, 0x72, 0x73, 0x76, 0x77, 1454 0x78, 0x79, 0x7a, 0x7b, 1455 }; 1456 static int x1830_lcd_slcd_8bit_pins[] = { 1457 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x6c, 0x6d, 1458 0x69, 0x72, 0x73, 0x7b, 0x7a, 1459 }; 1460 static int x1830_lcd_slcd_16bit_pins[] = { 1461 0x6e, 0x6f, 0x70, 0x71, 0x76, 0x77, 0x78, 0x79, 1462 }; 1463 static int x1830_pwm_pwm0_b_pins[] = { 0x31, }; 1464 static int x1830_pwm_pwm0_c_pins[] = { 0x4b, }; 1465 static int x1830_pwm_pwm1_b_pins[] = { 0x32, }; 1466 static int x1830_pwm_pwm1_c_pins[] = { 0x4c, }; 1467 static int x1830_pwm_pwm2_c_8_pins[] = { 0x48, }; 1468 static int x1830_pwm_pwm2_c_13_pins[] = { 0x4d, }; 1469 static int x1830_pwm_pwm3_c_9_pins[] = { 0x49, }; 1470 static int x1830_pwm_pwm3_c_14_pins[] = { 0x4e, }; 1471 static int x1830_pwm_pwm4_c_15_pins[] = { 0x4f, }; 1472 static int x1830_pwm_pwm4_c_25_pins[] = { 0x59, }; 1473 static int x1830_pwm_pwm5_c_16_pins[] = { 0x50, }; 1474 static int x1830_pwm_pwm5_c_26_pins[] = { 0x5a, }; 1475 static int x1830_pwm_pwm6_c_17_pins[] = { 0x51, }; 1476 static int x1830_pwm_pwm6_c_27_pins[] = { 0x5b, }; 1477 static int x1830_pwm_pwm7_c_18_pins[] = { 0x52, }; 1478 static int x1830_pwm_pwm7_c_28_pins[] = { 0x5c, }; 1479 static int x1830_mac_pins[] = { 1480 0x29, 0x30, 0x2f, 0x28, 0x2e, 0x2d, 0x2a, 0x2b, 0x26, 0x27, 1481 }; 1482 1483 static int x1830_uart0_data_funcs[] = { 0, 0, }; 1484 static int x1830_uart0_hwflow_funcs[] = { 0, 0, }; 1485 static int x1830_uart1_data_funcs[] = { 0, 0, }; 1486 static int x1830_sfc_funcs[] = { 1, 1, 1, 1, 1, 1, }; 1487 static int x1830_ssi0_dt_funcs[] = { 0, }; 1488 static int x1830_ssi0_dr_funcs[] = { 0, }; 1489 static int x1830_ssi0_clk_funcs[] = { 0, }; 1490 static int x1830_ssi0_gpc_funcs[] = { 0, }; 1491 static int x1830_ssi0_ce0_funcs[] = { 0, }; 1492 static int x1830_ssi0_ce1_funcs[] = { 0, }; 1493 static int x1830_ssi1_dt_c_funcs[] = { 1, }; 1494 static int x1830_ssi1_dr_c_funcs[] = { 1, }; 1495 static int x1830_ssi1_clk_c_funcs[] = { 1, }; 1496 static int x1830_ssi1_gpc_c_funcs[] = { 1, }; 1497 static int x1830_ssi1_ce0_c_funcs[] = { 1, }; 1498 static int x1830_ssi1_ce1_c_funcs[] = { 1, }; 1499 static int x1830_ssi1_dt_d_funcs[] = { 2, }; 1500 static int x1830_ssi1_dr_d_funcs[] = { 2, }; 1501 static int x1830_ssi1_clk_d_funcs[] = { 2, }; 1502 static int x1830_ssi1_gpc_d_funcs[] = { 2, }; 1503 static int x1830_ssi1_ce0_d_funcs[] = { 2, }; 1504 static int x1830_ssi1_ce1_d_funcs[] = { 2, }; 1505 static int x1830_mmc0_1bit_funcs[] = { 0, 0, 0, }; 1506 static int x1830_mmc0_4bit_funcs[] = { 0, 0, 0, }; 1507 static int x1830_mmc1_1bit_funcs[] = { 0, 0, 0, }; 1508 static int x1830_mmc1_4bit_funcs[] = { 0, 0, 0, }; 1509 static int x1830_i2c0_funcs[] = { 1, 1, }; 1510 static int x1830_i2c1_funcs[] = { 0, 0, }; 1511 static int x1830_i2c2_funcs[] = { 1, 1, }; 1512 static int x1830_lcd_rgb_18bit_funcs[] = { 1513 0, 0, 0, 0, 0, 0, 1514 0, 0, 0, 0, 0, 0, 1515 0, 0, 0, 0, 0, 0, 1516 0, 0, 0, 0, 1517 }; 1518 static int x1830_lcd_slcd_8bit_funcs[] = { 1519 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1520 }; 1521 static int x1830_lcd_slcd_16bit_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, }; 1522 static int x1830_pwm_pwm0_b_funcs[] = { 0, }; 1523 static int x1830_pwm_pwm0_c_funcs[] = { 1, }; 1524 static int x1830_pwm_pwm1_b_funcs[] = { 0, }; 1525 static int x1830_pwm_pwm1_c_funcs[] = { 1, }; 1526 static int x1830_pwm_pwm2_c_8_funcs[] = { 0, }; 1527 static int x1830_pwm_pwm2_c_13_funcs[] = { 1, }; 1528 static int x1830_pwm_pwm3_c_9_funcs[] = { 0, }; 1529 static int x1830_pwm_pwm3_c_14_funcs[] = { 1, }; 1530 static int x1830_pwm_pwm4_c_15_funcs[] = { 1, }; 1531 static int x1830_pwm_pwm4_c_25_funcs[] = { 0, }; 1532 static int x1830_pwm_pwm5_c_16_funcs[] = { 1, }; 1533 static int x1830_pwm_pwm5_c_26_funcs[] = { 0, }; 1534 static int x1830_pwm_pwm6_c_17_funcs[] = { 1, }; 1535 static int x1830_pwm_pwm6_c_27_funcs[] = { 0, }; 1536 static int x1830_pwm_pwm7_c_18_funcs[] = { 1, }; 1537 static int x1830_pwm_pwm7_c_28_funcs[] = { 0, }; 1538 static int x1830_mac_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; 1539 1540 static const struct group_desc x1830_groups[] = { 1541 INGENIC_PIN_GROUP("uart0-data", x1830_uart0_data), 1542 INGENIC_PIN_GROUP("uart0-hwflow", x1830_uart0_hwflow), 1543 INGENIC_PIN_GROUP("uart1-data", x1830_uart1_data), 1544 INGENIC_PIN_GROUP("sfc", x1830_sfc), 1545 INGENIC_PIN_GROUP("ssi0-dt", x1830_ssi0_dt), 1546 INGENIC_PIN_GROUP("ssi0-dr", x1830_ssi0_dr), 1547 INGENIC_PIN_GROUP("ssi0-clk", x1830_ssi0_clk), 1548 INGENIC_PIN_GROUP("ssi0-gpc", x1830_ssi0_gpc), 1549 INGENIC_PIN_GROUP("ssi0-ce0", x1830_ssi0_ce0), 1550 INGENIC_PIN_GROUP("ssi0-ce1", x1830_ssi0_ce1), 1551 INGENIC_PIN_GROUP("ssi1-dt-c", x1830_ssi1_dt_c), 1552 INGENIC_PIN_GROUP("ssi1-dr-c", x1830_ssi1_dr_c), 1553 INGENIC_PIN_GROUP("ssi1-clk-c", x1830_ssi1_clk_c), 1554 INGENIC_PIN_GROUP("ssi1-gpc-c", x1830_ssi1_gpc_c), 1555 INGENIC_PIN_GROUP("ssi1-ce0-c", x1830_ssi1_ce0_c), 1556 INGENIC_PIN_GROUP("ssi1-ce1-c", x1830_ssi1_ce1_c), 1557 INGENIC_PIN_GROUP("ssi1-dt-d", x1830_ssi1_dt_d), 1558 INGENIC_PIN_GROUP("ssi1-dr-d", x1830_ssi1_dr_d), 1559 INGENIC_PIN_GROUP("ssi1-clk-d", x1830_ssi1_clk_d), 1560 INGENIC_PIN_GROUP("ssi1-gpc-d", x1830_ssi1_gpc_d), 1561 INGENIC_PIN_GROUP("ssi1-ce0-d", x1830_ssi1_ce0_d), 1562 INGENIC_PIN_GROUP("ssi1-ce1-d", x1830_ssi1_ce1_d), 1563 INGENIC_PIN_GROUP("mmc0-1bit", x1830_mmc0_1bit), 1564 INGENIC_PIN_GROUP("mmc0-4bit", x1830_mmc0_4bit), 1565 INGENIC_PIN_GROUP("mmc1-1bit", x1830_mmc1_1bit), 1566 INGENIC_PIN_GROUP("mmc1-4bit", x1830_mmc1_4bit), 1567 INGENIC_PIN_GROUP("i2c0-data", x1830_i2c0), 1568 INGENIC_PIN_GROUP("i2c1-data", x1830_i2c1), 1569 INGENIC_PIN_GROUP("i2c2-data", x1830_i2c2), 1570 INGENIC_PIN_GROUP("lcd-rgb-18bit", x1830_lcd_rgb_18bit), 1571 INGENIC_PIN_GROUP("lcd-slcd-8bit", x1830_lcd_slcd_8bit), 1572 INGENIC_PIN_GROUP("lcd-slcd-16bit", x1830_lcd_slcd_16bit), 1573 { "lcd-no-pins", }, 1574 INGENIC_PIN_GROUP("pwm0-b", x1830_pwm_pwm0_b), 1575 INGENIC_PIN_GROUP("pwm0-c", x1830_pwm_pwm0_c), 1576 INGENIC_PIN_GROUP("pwm1-b", x1830_pwm_pwm1_b), 1577 INGENIC_PIN_GROUP("pwm1-c", x1830_pwm_pwm1_c), 1578 INGENIC_PIN_GROUP("pwm2-c-8", x1830_pwm_pwm2_c_8), 1579 INGENIC_PIN_GROUP("pwm2-c-13", x1830_pwm_pwm2_c_13), 1580 INGENIC_PIN_GROUP("pwm3-c-9", x1830_pwm_pwm3_c_9), 1581 INGENIC_PIN_GROUP("pwm3-c-14", x1830_pwm_pwm3_c_14), 1582 INGENIC_PIN_GROUP("pwm4-c-15", x1830_pwm_pwm4_c_15), 1583 INGENIC_PIN_GROUP("pwm4-c-25", x1830_pwm_pwm4_c_25), 1584 INGENIC_PIN_GROUP("pwm5-c-16", x1830_pwm_pwm5_c_16), 1585 INGENIC_PIN_GROUP("pwm5-c-26", x1830_pwm_pwm5_c_26), 1586 INGENIC_PIN_GROUP("pwm6-c-17", x1830_pwm_pwm6_c_17), 1587 INGENIC_PIN_GROUP("pwm6-c-27", x1830_pwm_pwm6_c_27), 1588 INGENIC_PIN_GROUP("pwm7-c-18", x1830_pwm_pwm7_c_18), 1589 INGENIC_PIN_GROUP("pwm7-c-28", x1830_pwm_pwm7_c_28), 1590 INGENIC_PIN_GROUP("mac", x1830_mac), 1591 }; 1592 1593 static const char *x1830_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; 1594 static const char *x1830_uart1_groups[] = { "uart1-data", }; 1595 static const char *x1830_sfc_groups[] = { "sfc", }; 1596 static const char *x1830_ssi0_groups[] = { 1597 "ssi0-dt", "ssi0-dr", "ssi0-clk", "ssi0-gpc", "ssi0-ce0", "ssi0-ce1", 1598 }; 1599 static const char *x1830_ssi1_groups[] = { 1600 "ssi1-dt-c", "ssi1-dt-d", 1601 "ssi1-dr-c", "ssi1-dr-d", 1602 "ssi1-clk-c", "ssi1-clk-d", 1603 "ssi1-gpc-c", "ssi1-gpc-d", 1604 "ssi1-ce0-c", "ssi1-ce0-d", 1605 "ssi1-ce1-c", "ssi1-ce1-d", 1606 }; 1607 static const char *x1830_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", }; 1608 static const char *x1830_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", }; 1609 static const char *x1830_i2c0_groups[] = { "i2c0-data", }; 1610 static const char *x1830_i2c1_groups[] = { "i2c1-data", }; 1611 static const char *x1830_i2c2_groups[] = { "i2c2-data", }; 1612 static const char *x1830_lcd_groups[] = { 1613 "lcd-rgb-18bit", "lcd-slcd-8bit", "lcd-slcd-16bit", "lcd-no-pins", 1614 }; 1615 static const char *x1830_pwm0_groups[] = { "pwm0-b", "pwm0-c", }; 1616 static const char *x1830_pwm1_groups[] = { "pwm1-b", "pwm1-c", }; 1617 static const char *x1830_pwm2_groups[] = { "pwm2-c-8", "pwm2-c-13", }; 1618 static const char *x1830_pwm3_groups[] = { "pwm3-c-9", "pwm3-c-14", }; 1619 static const char *x1830_pwm4_groups[] = { "pwm4-c-15", "pwm4-c-25", }; 1620 static const char *x1830_pwm5_groups[] = { "pwm5-c-16", "pwm5-c-26", }; 1621 static const char *x1830_pwm6_groups[] = { "pwm6-c-17", "pwm6-c-27", }; 1622 static const char *x1830_pwm7_groups[] = { "pwm7-c-18", "pwm7-c-28", }; 1623 static const char *x1830_mac_groups[] = { "mac", }; 1624 1625 static const struct function_desc x1830_functions[] = { 1626 { "uart0", x1830_uart0_groups, ARRAY_SIZE(x1830_uart0_groups), }, 1627 { "uart1", x1830_uart1_groups, ARRAY_SIZE(x1830_uart1_groups), }, 1628 { "sfc", x1830_sfc_groups, ARRAY_SIZE(x1830_sfc_groups), }, 1629 { "ssi0", x1830_ssi0_groups, ARRAY_SIZE(x1830_ssi0_groups), }, 1630 { "ssi1", x1830_ssi1_groups, ARRAY_SIZE(x1830_ssi1_groups), }, 1631 { "mmc0", x1830_mmc0_groups, ARRAY_SIZE(x1830_mmc0_groups), }, 1632 { "mmc1", x1830_mmc1_groups, ARRAY_SIZE(x1830_mmc1_groups), }, 1633 { "i2c0", x1830_i2c0_groups, ARRAY_SIZE(x1830_i2c0_groups), }, 1634 { "i2c1", x1830_i2c1_groups, ARRAY_SIZE(x1830_i2c1_groups), }, 1635 { "i2c2", x1830_i2c2_groups, ARRAY_SIZE(x1830_i2c2_groups), }, 1636 { "lcd", x1830_lcd_groups, ARRAY_SIZE(x1830_lcd_groups), }, 1637 { "pwm0", x1830_pwm0_groups, ARRAY_SIZE(x1830_pwm0_groups), }, 1638 { "pwm1", x1830_pwm1_groups, ARRAY_SIZE(x1830_pwm1_groups), }, 1639 { "pwm2", x1830_pwm2_groups, ARRAY_SIZE(x1830_pwm2_groups), }, 1640 { "pwm3", x1830_pwm3_groups, ARRAY_SIZE(x1830_pwm3_groups), }, 1641 { "pwm4", x1830_pwm4_groups, ARRAY_SIZE(x1830_pwm4_groups), }, 1642 { "pwm5", x1830_pwm5_groups, ARRAY_SIZE(x1830_pwm4_groups), }, 1643 { "pwm6", x1830_pwm6_groups, ARRAY_SIZE(x1830_pwm4_groups), }, 1644 { "pwm7", x1830_pwm7_groups, ARRAY_SIZE(x1830_pwm4_groups), }, 1645 { "mac", x1830_mac_groups, ARRAY_SIZE(x1830_mac_groups), }, 1646 }; 1647 1648 static const struct ingenic_chip_info x1830_chip_info = { 1649 .num_chips = 4, 1650 .reg_offset = 0x1000, 1651 .version = ID_X1830, 1652 .groups = x1830_groups, 1653 .num_groups = ARRAY_SIZE(x1830_groups), 1654 .functions = x1830_functions, 1655 .num_functions = ARRAY_SIZE(x1830_functions), 1656 .pull_ups = x1830_pull_ups, 1657 .pull_downs = x1830_pull_downs, 1658 }; 1659 1660 static u32 ingenic_gpio_read_reg(struct ingenic_gpio_chip *jzgc, u8 reg) 1661 { 1662 unsigned int val; 1663 1664 regmap_read(jzgc->jzpc->map, jzgc->reg_base + reg, &val); 1665 1666 return (u32) val; 1667 } 1668 1669 static void ingenic_gpio_set_bit(struct ingenic_gpio_chip *jzgc, 1670 u8 reg, u8 offset, bool set) 1671 { 1672 if (set) 1673 reg = REG_SET(reg); 1674 else 1675 reg = REG_CLEAR(reg); 1676 1677 regmap_write(jzgc->jzpc->map, jzgc->reg_base + reg, BIT(offset)); 1678 } 1679 1680 static void ingenic_gpio_shadow_set_bit(struct ingenic_gpio_chip *jzgc, 1681 u8 reg, u8 offset, bool set) 1682 { 1683 if (set) 1684 reg = REG_SET(reg); 1685 else 1686 reg = REG_CLEAR(reg); 1687 1688 regmap_write(jzgc->jzpc->map, REG_PZ_BASE( 1689 jzgc->jzpc->info->reg_offset) + reg, BIT(offset)); 1690 } 1691 1692 static void ingenic_gpio_shadow_set_bit_load(struct ingenic_gpio_chip *jzgc) 1693 { 1694 regmap_write(jzgc->jzpc->map, REG_PZ_GID2LD( 1695 jzgc->jzpc->info->reg_offset), 1696 jzgc->gc.base / PINS_PER_GPIO_CHIP); 1697 } 1698 1699 static inline bool ingenic_gpio_get_value(struct ingenic_gpio_chip *jzgc, 1700 u8 offset) 1701 { 1702 unsigned int val = ingenic_gpio_read_reg(jzgc, GPIO_PIN); 1703 1704 return !!(val & BIT(offset)); 1705 } 1706 1707 static void ingenic_gpio_set_value(struct ingenic_gpio_chip *jzgc, 1708 u8 offset, int value) 1709 { 1710 if (jzgc->jzpc->info->version >= ID_JZ4760) 1711 ingenic_gpio_set_bit(jzgc, JZ4760_GPIO_PAT0, offset, !!value); 1712 else 1713 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_DATA, offset, !!value); 1714 } 1715 1716 static void irq_set_type(struct ingenic_gpio_chip *jzgc, 1717 u8 offset, unsigned int type) 1718 { 1719 u8 reg1, reg2; 1720 bool val1, val2; 1721 1722 switch (type) { 1723 case IRQ_TYPE_EDGE_RISING: 1724 val1 = val2 = true; 1725 break; 1726 case IRQ_TYPE_EDGE_FALLING: 1727 val1 = false; 1728 val2 = true; 1729 break; 1730 case IRQ_TYPE_LEVEL_HIGH: 1731 val1 = true; 1732 val2 = false; 1733 break; 1734 case IRQ_TYPE_LEVEL_LOW: 1735 default: 1736 val1 = val2 = false; 1737 break; 1738 } 1739 1740 if (jzgc->jzpc->info->version >= ID_JZ4760) { 1741 reg1 = JZ4760_GPIO_PAT1; 1742 reg2 = JZ4760_GPIO_PAT0; 1743 } else { 1744 reg1 = JZ4740_GPIO_TRIG; 1745 reg2 = JZ4740_GPIO_DIR; 1746 } 1747 1748 if (jzgc->jzpc->info->version >= ID_X1000) { 1749 ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, val1); 1750 ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, val2); 1751 ingenic_gpio_shadow_set_bit_load(jzgc); 1752 } else { 1753 ingenic_gpio_set_bit(jzgc, reg2, offset, val1); 1754 ingenic_gpio_set_bit(jzgc, reg1, offset, val2); 1755 } 1756 } 1757 1758 static void ingenic_gpio_irq_mask(struct irq_data *irqd) 1759 { 1760 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); 1761 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 1762 1763 ingenic_gpio_set_bit(jzgc, GPIO_MSK, irqd->hwirq, true); 1764 } 1765 1766 static void ingenic_gpio_irq_unmask(struct irq_data *irqd) 1767 { 1768 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); 1769 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 1770 1771 ingenic_gpio_set_bit(jzgc, GPIO_MSK, irqd->hwirq, false); 1772 } 1773 1774 static void ingenic_gpio_irq_enable(struct irq_data *irqd) 1775 { 1776 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); 1777 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 1778 int irq = irqd->hwirq; 1779 1780 if (jzgc->jzpc->info->version >= ID_JZ4760) 1781 ingenic_gpio_set_bit(jzgc, JZ4760_GPIO_INT, irq, true); 1782 else 1783 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, true); 1784 1785 ingenic_gpio_irq_unmask(irqd); 1786 } 1787 1788 static void ingenic_gpio_irq_disable(struct irq_data *irqd) 1789 { 1790 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); 1791 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 1792 int irq = irqd->hwirq; 1793 1794 ingenic_gpio_irq_mask(irqd); 1795 1796 if (jzgc->jzpc->info->version >= ID_JZ4760) 1797 ingenic_gpio_set_bit(jzgc, JZ4760_GPIO_INT, irq, false); 1798 else 1799 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, false); 1800 } 1801 1802 static void ingenic_gpio_irq_ack(struct irq_data *irqd) 1803 { 1804 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); 1805 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 1806 int irq = irqd->hwirq; 1807 bool high; 1808 1809 if (irqd_get_trigger_type(irqd) == IRQ_TYPE_EDGE_BOTH) { 1810 /* 1811 * Switch to an interrupt for the opposite edge to the one that 1812 * triggered the interrupt being ACKed. 1813 */ 1814 high = ingenic_gpio_get_value(jzgc, irq); 1815 if (high) 1816 irq_set_type(jzgc, irq, IRQ_TYPE_LEVEL_LOW); 1817 else 1818 irq_set_type(jzgc, irq, IRQ_TYPE_LEVEL_HIGH); 1819 } 1820 1821 if (jzgc->jzpc->info->version >= ID_JZ4760) 1822 ingenic_gpio_set_bit(jzgc, JZ4760_GPIO_FLAG, irq, false); 1823 else 1824 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_DATA, irq, true); 1825 } 1826 1827 static int ingenic_gpio_irq_set_type(struct irq_data *irqd, unsigned int type) 1828 { 1829 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); 1830 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 1831 1832 switch (type) { 1833 case IRQ_TYPE_EDGE_BOTH: 1834 case IRQ_TYPE_EDGE_RISING: 1835 case IRQ_TYPE_EDGE_FALLING: 1836 irq_set_handler_locked(irqd, handle_edge_irq); 1837 break; 1838 case IRQ_TYPE_LEVEL_HIGH: 1839 case IRQ_TYPE_LEVEL_LOW: 1840 irq_set_handler_locked(irqd, handle_level_irq); 1841 break; 1842 default: 1843 irq_set_handler_locked(irqd, handle_bad_irq); 1844 } 1845 1846 if (type == IRQ_TYPE_EDGE_BOTH) { 1847 /* 1848 * The hardware does not support interrupts on both edges. The 1849 * best we can do is to set up a single-edge interrupt and then 1850 * switch to the opposing edge when ACKing the interrupt. 1851 */ 1852 bool high = ingenic_gpio_get_value(jzgc, irqd->hwirq); 1853 1854 type = high ? IRQ_TYPE_LEVEL_LOW : IRQ_TYPE_LEVEL_HIGH; 1855 } 1856 1857 irq_set_type(jzgc, irqd->hwirq, type); 1858 return 0; 1859 } 1860 1861 static int ingenic_gpio_irq_set_wake(struct irq_data *irqd, unsigned int on) 1862 { 1863 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); 1864 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 1865 1866 return irq_set_irq_wake(jzgc->irq, on); 1867 } 1868 1869 static void ingenic_gpio_irq_handler(struct irq_desc *desc) 1870 { 1871 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 1872 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 1873 struct irq_chip *irq_chip = irq_data_get_irq_chip(&desc->irq_data); 1874 unsigned long flag, i; 1875 1876 chained_irq_enter(irq_chip, desc); 1877 1878 if (jzgc->jzpc->info->version >= ID_JZ4760) 1879 flag = ingenic_gpio_read_reg(jzgc, JZ4760_GPIO_FLAG); 1880 else 1881 flag = ingenic_gpio_read_reg(jzgc, JZ4740_GPIO_FLAG); 1882 1883 for_each_set_bit(i, &flag, 32) 1884 generic_handle_irq(irq_linear_revmap(gc->irq.domain, i)); 1885 chained_irq_exit(irq_chip, desc); 1886 } 1887 1888 static void ingenic_gpio_set(struct gpio_chip *gc, 1889 unsigned int offset, int value) 1890 { 1891 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 1892 1893 ingenic_gpio_set_value(jzgc, offset, value); 1894 } 1895 1896 static int ingenic_gpio_get(struct gpio_chip *gc, unsigned int offset) 1897 { 1898 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 1899 1900 return (int) ingenic_gpio_get_value(jzgc, offset); 1901 } 1902 1903 static int ingenic_gpio_direction_input(struct gpio_chip *gc, 1904 unsigned int offset) 1905 { 1906 return pinctrl_gpio_direction_input(gc->base + offset); 1907 } 1908 1909 static int ingenic_gpio_direction_output(struct gpio_chip *gc, 1910 unsigned int offset, int value) 1911 { 1912 ingenic_gpio_set(gc, offset, value); 1913 return pinctrl_gpio_direction_output(gc->base + offset); 1914 } 1915 1916 static inline void ingenic_config_pin(struct ingenic_pinctrl *jzpc, 1917 unsigned int pin, u8 reg, bool set) 1918 { 1919 unsigned int idx = pin % PINS_PER_GPIO_CHIP; 1920 unsigned int offt = pin / PINS_PER_GPIO_CHIP; 1921 1922 regmap_write(jzpc->map, offt * jzpc->info->reg_offset + 1923 (set ? REG_SET(reg) : REG_CLEAR(reg)), BIT(idx)); 1924 } 1925 1926 static inline void ingenic_shadow_config_pin(struct ingenic_pinctrl *jzpc, 1927 unsigned int pin, u8 reg, bool set) 1928 { 1929 unsigned int idx = pin % PINS_PER_GPIO_CHIP; 1930 1931 regmap_write(jzpc->map, REG_PZ_BASE(jzpc->info->reg_offset) + 1932 (set ? REG_SET(reg) : REG_CLEAR(reg)), BIT(idx)); 1933 } 1934 1935 static inline void ingenic_shadow_config_pin_load(struct ingenic_pinctrl *jzpc, 1936 unsigned int pin) 1937 { 1938 regmap_write(jzpc->map, REG_PZ_GID2LD(jzpc->info->reg_offset), 1939 pin / PINS_PER_GPIO_CHIP); 1940 } 1941 1942 static inline bool ingenic_get_pin_config(struct ingenic_pinctrl *jzpc, 1943 unsigned int pin, u8 reg) 1944 { 1945 unsigned int idx = pin % PINS_PER_GPIO_CHIP; 1946 unsigned int offt = pin / PINS_PER_GPIO_CHIP; 1947 unsigned int val; 1948 1949 regmap_read(jzpc->map, offt * jzpc->info->reg_offset + reg, &val); 1950 1951 return val & BIT(idx); 1952 } 1953 1954 static int ingenic_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) 1955 { 1956 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 1957 struct ingenic_pinctrl *jzpc = jzgc->jzpc; 1958 unsigned int pin = gc->base + offset; 1959 1960 if (jzpc->info->version >= ID_JZ4760) { 1961 if (ingenic_get_pin_config(jzpc, pin, JZ4760_GPIO_INT) || 1962 ingenic_get_pin_config(jzpc, pin, JZ4760_GPIO_PAT1)) 1963 return GPIO_LINE_DIRECTION_IN; 1964 return GPIO_LINE_DIRECTION_OUT; 1965 } 1966 1967 if (ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_SELECT)) 1968 return GPIO_LINE_DIRECTION_IN; 1969 1970 if (ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_DIR)) 1971 return GPIO_LINE_DIRECTION_OUT; 1972 1973 return GPIO_LINE_DIRECTION_IN; 1974 } 1975 1976 static const struct pinctrl_ops ingenic_pctlops = { 1977 .get_groups_count = pinctrl_generic_get_group_count, 1978 .get_group_name = pinctrl_generic_get_group_name, 1979 .get_group_pins = pinctrl_generic_get_group_pins, 1980 .dt_node_to_map = pinconf_generic_dt_node_to_map_all, 1981 .dt_free_map = pinconf_generic_dt_free_map, 1982 }; 1983 1984 static int ingenic_gpio_irq_request(struct irq_data *data) 1985 { 1986 struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data); 1987 int ret; 1988 1989 ret = ingenic_gpio_direction_input(gpio_chip, data->hwirq); 1990 if (ret) 1991 return ret; 1992 1993 return gpiochip_reqres_irq(gpio_chip, data->hwirq); 1994 } 1995 1996 static void ingenic_gpio_irq_release(struct irq_data *data) 1997 { 1998 struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data); 1999 2000 return gpiochip_relres_irq(gpio_chip, data->hwirq); 2001 } 2002 2003 static int ingenic_pinmux_set_pin_fn(struct ingenic_pinctrl *jzpc, 2004 int pin, int func) 2005 { 2006 unsigned int idx = pin % PINS_PER_GPIO_CHIP; 2007 unsigned int offt = pin / PINS_PER_GPIO_CHIP; 2008 2009 dev_dbg(jzpc->dev, "set pin P%c%u to function %u\n", 2010 'A' + offt, idx, func); 2011 2012 if (jzpc->info->version >= ID_X1000) { 2013 ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_INT, false); 2014 ingenic_shadow_config_pin(jzpc, pin, GPIO_MSK, false); 2015 ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_PAT1, func & 0x2); 2016 ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_PAT0, func & 0x1); 2017 ingenic_shadow_config_pin_load(jzpc, pin); 2018 } else if (jzpc->info->version >= ID_JZ4760) { 2019 ingenic_config_pin(jzpc, pin, JZ4760_GPIO_INT, false); 2020 ingenic_config_pin(jzpc, pin, GPIO_MSK, false); 2021 ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PAT1, func & 0x2); 2022 ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PAT0, func & 0x1); 2023 } else { 2024 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_FUNC, true); 2025 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_TRIG, func & 0x2); 2026 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_SELECT, func > 0); 2027 } 2028 2029 return 0; 2030 } 2031 2032 static int ingenic_pinmux_set_mux(struct pinctrl_dev *pctldev, 2033 unsigned int selector, unsigned int group) 2034 { 2035 struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev); 2036 struct function_desc *func; 2037 struct group_desc *grp; 2038 unsigned int i; 2039 2040 func = pinmux_generic_get_function(pctldev, selector); 2041 if (!func) 2042 return -EINVAL; 2043 2044 grp = pinctrl_generic_get_group(pctldev, group); 2045 if (!grp) 2046 return -EINVAL; 2047 2048 dev_dbg(pctldev->dev, "enable function %s group %s\n", 2049 func->name, grp->name); 2050 2051 for (i = 0; i < grp->num_pins; i++) { 2052 int *pin_modes = grp->data; 2053 2054 ingenic_pinmux_set_pin_fn(jzpc, grp->pins[i], pin_modes[i]); 2055 } 2056 2057 return 0; 2058 } 2059 2060 static int ingenic_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev, 2061 struct pinctrl_gpio_range *range, 2062 unsigned int pin, bool input) 2063 { 2064 struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev); 2065 unsigned int idx = pin % PINS_PER_GPIO_CHIP; 2066 unsigned int offt = pin / PINS_PER_GPIO_CHIP; 2067 2068 dev_dbg(pctldev->dev, "set pin P%c%u to %sput\n", 2069 'A' + offt, idx, input ? "in" : "out"); 2070 2071 if (jzpc->info->version >= ID_X1000) { 2072 ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_INT, false); 2073 ingenic_shadow_config_pin(jzpc, pin, GPIO_MSK, true); 2074 ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_PAT1, input); 2075 ingenic_shadow_config_pin_load(jzpc, pin); 2076 } else if (jzpc->info->version >= ID_JZ4760) { 2077 ingenic_config_pin(jzpc, pin, JZ4760_GPIO_INT, false); 2078 ingenic_config_pin(jzpc, pin, GPIO_MSK, true); 2079 ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PAT1, input); 2080 } else { 2081 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_SELECT, false); 2082 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_DIR, !input); 2083 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_FUNC, false); 2084 } 2085 2086 return 0; 2087 } 2088 2089 static const struct pinmux_ops ingenic_pmxops = { 2090 .get_functions_count = pinmux_generic_get_function_count, 2091 .get_function_name = pinmux_generic_get_function_name, 2092 .get_function_groups = pinmux_generic_get_function_groups, 2093 .set_mux = ingenic_pinmux_set_mux, 2094 .gpio_set_direction = ingenic_pinmux_gpio_set_direction, 2095 }; 2096 2097 static int ingenic_pinconf_get(struct pinctrl_dev *pctldev, 2098 unsigned int pin, unsigned long *config) 2099 { 2100 struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev); 2101 enum pin_config_param param = pinconf_to_config_param(*config); 2102 unsigned int idx = pin % PINS_PER_GPIO_CHIP; 2103 unsigned int offt = pin / PINS_PER_GPIO_CHIP; 2104 bool pull; 2105 2106 if (jzpc->info->version >= ID_JZ4760) 2107 pull = !ingenic_get_pin_config(jzpc, pin, JZ4760_GPIO_PEN); 2108 else 2109 pull = !ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_PULL_DIS); 2110 2111 switch (param) { 2112 case PIN_CONFIG_BIAS_DISABLE: 2113 if (pull) 2114 return -EINVAL; 2115 break; 2116 2117 case PIN_CONFIG_BIAS_PULL_UP: 2118 if (!pull || !(jzpc->info->pull_ups[offt] & BIT(idx))) 2119 return -EINVAL; 2120 break; 2121 2122 case PIN_CONFIG_BIAS_PULL_DOWN: 2123 if (!pull || !(jzpc->info->pull_downs[offt] & BIT(idx))) 2124 return -EINVAL; 2125 break; 2126 2127 default: 2128 return -ENOTSUPP; 2129 } 2130 2131 *config = pinconf_to_config_packed(param, 1); 2132 return 0; 2133 } 2134 2135 static void ingenic_set_bias(struct ingenic_pinctrl *jzpc, 2136 unsigned int pin, unsigned int bias) 2137 { 2138 if (jzpc->info->version >= ID_X1830) { 2139 unsigned int idx = pin % PINS_PER_GPIO_CHIP; 2140 unsigned int half = PINS_PER_GPIO_CHIP / 2; 2141 unsigned int idxh = pin % half * 2; 2142 unsigned int offt = pin / PINS_PER_GPIO_CHIP; 2143 2144 if (idx < half) { 2145 regmap_write(jzpc->map, offt * jzpc->info->reg_offset + 2146 REG_CLEAR(X1830_GPIO_PEL), 3 << idxh); 2147 regmap_write(jzpc->map, offt * jzpc->info->reg_offset + 2148 REG_SET(X1830_GPIO_PEL), bias << idxh); 2149 } else { 2150 regmap_write(jzpc->map, offt * jzpc->info->reg_offset + 2151 REG_CLEAR(X1830_GPIO_PEH), 3 << idxh); 2152 regmap_write(jzpc->map, offt * jzpc->info->reg_offset + 2153 REG_SET(X1830_GPIO_PEH), bias << idxh); 2154 } 2155 2156 } else if (jzpc->info->version >= ID_JZ4760) { 2157 ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PEN, !bias); 2158 } else { 2159 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_PULL_DIS, !bias); 2160 } 2161 } 2162 2163 static void ingenic_set_output_level(struct ingenic_pinctrl *jzpc, 2164 unsigned int pin, bool high) 2165 { 2166 if (jzpc->info->version >= ID_JZ4760) 2167 ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PAT0, high); 2168 else 2169 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_DATA, high); 2170 } 2171 2172 static int ingenic_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 2173 unsigned long *configs, unsigned int num_configs) 2174 { 2175 struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev); 2176 unsigned int idx = pin % PINS_PER_GPIO_CHIP; 2177 unsigned int offt = pin / PINS_PER_GPIO_CHIP; 2178 unsigned int cfg, arg; 2179 int ret; 2180 2181 for (cfg = 0; cfg < num_configs; cfg++) { 2182 switch (pinconf_to_config_param(configs[cfg])) { 2183 case PIN_CONFIG_BIAS_DISABLE: 2184 case PIN_CONFIG_BIAS_PULL_UP: 2185 case PIN_CONFIG_BIAS_PULL_DOWN: 2186 case PIN_CONFIG_OUTPUT: 2187 continue; 2188 default: 2189 return -ENOTSUPP; 2190 } 2191 } 2192 2193 for (cfg = 0; cfg < num_configs; cfg++) { 2194 arg = pinconf_to_config_argument(configs[cfg]); 2195 2196 switch (pinconf_to_config_param(configs[cfg])) { 2197 case PIN_CONFIG_BIAS_DISABLE: 2198 dev_dbg(jzpc->dev, "disable pull-over for pin P%c%u\n", 2199 'A' + offt, idx); 2200 ingenic_set_bias(jzpc, pin, GPIO_PULL_DIS); 2201 break; 2202 2203 case PIN_CONFIG_BIAS_PULL_UP: 2204 if (!(jzpc->info->pull_ups[offt] & BIT(idx))) 2205 return -EINVAL; 2206 dev_dbg(jzpc->dev, "set pull-up for pin P%c%u\n", 2207 'A' + offt, idx); 2208 ingenic_set_bias(jzpc, pin, GPIO_PULL_UP); 2209 break; 2210 2211 case PIN_CONFIG_BIAS_PULL_DOWN: 2212 if (!(jzpc->info->pull_downs[offt] & BIT(idx))) 2213 return -EINVAL; 2214 dev_dbg(jzpc->dev, "set pull-down for pin P%c%u\n", 2215 'A' + offt, idx); 2216 ingenic_set_bias(jzpc, pin, GPIO_PULL_DOWN); 2217 break; 2218 2219 case PIN_CONFIG_OUTPUT: 2220 ret = pinctrl_gpio_direction_output(pin); 2221 if (ret) 2222 return ret; 2223 2224 ingenic_set_output_level(jzpc, pin, arg); 2225 break; 2226 2227 default: 2228 /* unreachable */ 2229 break; 2230 } 2231 } 2232 2233 return 0; 2234 } 2235 2236 static int ingenic_pinconf_group_get(struct pinctrl_dev *pctldev, 2237 unsigned int group, unsigned long *config) 2238 { 2239 const unsigned int *pins; 2240 unsigned int i, npins, old = 0; 2241 int ret; 2242 2243 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); 2244 if (ret) 2245 return ret; 2246 2247 for (i = 0; i < npins; i++) { 2248 if (ingenic_pinconf_get(pctldev, pins[i], config)) 2249 return -ENOTSUPP; 2250 2251 /* configs do not match between two pins */ 2252 if (i && (old != *config)) 2253 return -ENOTSUPP; 2254 2255 old = *config; 2256 } 2257 2258 return 0; 2259 } 2260 2261 static int ingenic_pinconf_group_set(struct pinctrl_dev *pctldev, 2262 unsigned int group, unsigned long *configs, 2263 unsigned int num_configs) 2264 { 2265 const unsigned int *pins; 2266 unsigned int i, npins; 2267 int ret; 2268 2269 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); 2270 if (ret) 2271 return ret; 2272 2273 for (i = 0; i < npins; i++) { 2274 ret = ingenic_pinconf_set(pctldev, 2275 pins[i], configs, num_configs); 2276 if (ret) 2277 return ret; 2278 } 2279 2280 return 0; 2281 } 2282 2283 static const struct pinconf_ops ingenic_confops = { 2284 .is_generic = true, 2285 .pin_config_get = ingenic_pinconf_get, 2286 .pin_config_set = ingenic_pinconf_set, 2287 .pin_config_group_get = ingenic_pinconf_group_get, 2288 .pin_config_group_set = ingenic_pinconf_group_set, 2289 }; 2290 2291 static const struct regmap_config ingenic_pinctrl_regmap_config = { 2292 .reg_bits = 32, 2293 .val_bits = 32, 2294 .reg_stride = 4, 2295 }; 2296 2297 static const struct of_device_id ingenic_gpio_of_match[] __initconst = { 2298 { .compatible = "ingenic,jz4740-gpio", }, 2299 { .compatible = "ingenic,jz4725b-gpio", }, 2300 { .compatible = "ingenic,jz4760-gpio", }, 2301 { .compatible = "ingenic,jz4770-gpio", }, 2302 { .compatible = "ingenic,jz4780-gpio", }, 2303 { .compatible = "ingenic,x1000-gpio", }, 2304 { .compatible = "ingenic,x1830-gpio", }, 2305 {}, 2306 }; 2307 2308 static int __init ingenic_gpio_probe(struct ingenic_pinctrl *jzpc, 2309 struct device_node *node) 2310 { 2311 struct ingenic_gpio_chip *jzgc; 2312 struct device *dev = jzpc->dev; 2313 struct gpio_irq_chip *girq; 2314 unsigned int bank; 2315 int err; 2316 2317 err = of_property_read_u32(node, "reg", &bank); 2318 if (err) { 2319 dev_err(dev, "Cannot read \"reg\" property: %i\n", err); 2320 return err; 2321 } 2322 2323 jzgc = devm_kzalloc(dev, sizeof(*jzgc), GFP_KERNEL); 2324 if (!jzgc) 2325 return -ENOMEM; 2326 2327 jzgc->jzpc = jzpc; 2328 jzgc->reg_base = bank * jzpc->info->reg_offset; 2329 2330 jzgc->gc.label = devm_kasprintf(dev, GFP_KERNEL, "GPIO%c", 'A' + bank); 2331 if (!jzgc->gc.label) 2332 return -ENOMEM; 2333 2334 /* DO NOT EXPAND THIS: FOR BACKWARD GPIO NUMBERSPACE COMPATIBIBILITY 2335 * ONLY: WORK TO TRANSITION CONSUMERS TO USE THE GPIO DESCRIPTOR API IN 2336 * <linux/gpio/consumer.h> INSTEAD. 2337 */ 2338 jzgc->gc.base = bank * 32; 2339 2340 jzgc->gc.ngpio = 32; 2341 jzgc->gc.parent = dev; 2342 jzgc->gc.of_node = node; 2343 jzgc->gc.owner = THIS_MODULE; 2344 2345 jzgc->gc.set = ingenic_gpio_set; 2346 jzgc->gc.get = ingenic_gpio_get; 2347 jzgc->gc.direction_input = ingenic_gpio_direction_input; 2348 jzgc->gc.direction_output = ingenic_gpio_direction_output; 2349 jzgc->gc.get_direction = ingenic_gpio_get_direction; 2350 jzgc->gc.request = gpiochip_generic_request; 2351 jzgc->gc.free = gpiochip_generic_free; 2352 2353 jzgc->irq = irq_of_parse_and_map(node, 0); 2354 if (!jzgc->irq) 2355 return -EINVAL; 2356 2357 jzgc->irq_chip.name = jzgc->gc.label; 2358 jzgc->irq_chip.irq_enable = ingenic_gpio_irq_enable; 2359 jzgc->irq_chip.irq_disable = ingenic_gpio_irq_disable; 2360 jzgc->irq_chip.irq_unmask = ingenic_gpio_irq_unmask; 2361 jzgc->irq_chip.irq_mask = ingenic_gpio_irq_mask; 2362 jzgc->irq_chip.irq_ack = ingenic_gpio_irq_ack; 2363 jzgc->irq_chip.irq_set_type = ingenic_gpio_irq_set_type; 2364 jzgc->irq_chip.irq_set_wake = ingenic_gpio_irq_set_wake; 2365 jzgc->irq_chip.irq_request_resources = ingenic_gpio_irq_request; 2366 jzgc->irq_chip.irq_release_resources = ingenic_gpio_irq_release; 2367 jzgc->irq_chip.flags = IRQCHIP_MASK_ON_SUSPEND; 2368 2369 girq = &jzgc->gc.irq; 2370 girq->chip = &jzgc->irq_chip; 2371 girq->parent_handler = ingenic_gpio_irq_handler; 2372 girq->num_parents = 1; 2373 girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents), 2374 GFP_KERNEL); 2375 if (!girq->parents) 2376 return -ENOMEM; 2377 girq->parents[0] = jzgc->irq; 2378 girq->default_type = IRQ_TYPE_NONE; 2379 girq->handler = handle_level_irq; 2380 2381 err = devm_gpiochip_add_data(dev, &jzgc->gc, jzgc); 2382 if (err) 2383 return err; 2384 2385 return 0; 2386 } 2387 2388 static int __init ingenic_pinctrl_probe(struct platform_device *pdev) 2389 { 2390 struct device *dev = &pdev->dev; 2391 struct ingenic_pinctrl *jzpc; 2392 struct pinctrl_desc *pctl_desc; 2393 void __iomem *base; 2394 const struct ingenic_chip_info *chip_info; 2395 struct device_node *node; 2396 unsigned int i; 2397 int err; 2398 2399 jzpc = devm_kzalloc(dev, sizeof(*jzpc), GFP_KERNEL); 2400 if (!jzpc) 2401 return -ENOMEM; 2402 2403 base = devm_platform_ioremap_resource(pdev, 0); 2404 if (IS_ERR(base)) 2405 return PTR_ERR(base); 2406 2407 jzpc->map = devm_regmap_init_mmio(dev, base, 2408 &ingenic_pinctrl_regmap_config); 2409 if (IS_ERR(jzpc->map)) { 2410 dev_err(dev, "Failed to create regmap\n"); 2411 return PTR_ERR(jzpc->map); 2412 } 2413 2414 jzpc->dev = dev; 2415 jzpc->info = chip_info = of_device_get_match_data(dev); 2416 2417 pctl_desc = devm_kzalloc(&pdev->dev, sizeof(*pctl_desc), GFP_KERNEL); 2418 if (!pctl_desc) 2419 return -ENOMEM; 2420 2421 /* fill in pinctrl_desc structure */ 2422 pctl_desc->name = dev_name(dev); 2423 pctl_desc->owner = THIS_MODULE; 2424 pctl_desc->pctlops = &ingenic_pctlops; 2425 pctl_desc->pmxops = &ingenic_pmxops; 2426 pctl_desc->confops = &ingenic_confops; 2427 pctl_desc->npins = chip_info->num_chips * PINS_PER_GPIO_CHIP; 2428 pctl_desc->pins = jzpc->pdesc = devm_kcalloc(&pdev->dev, 2429 pctl_desc->npins, sizeof(*jzpc->pdesc), GFP_KERNEL); 2430 if (!jzpc->pdesc) 2431 return -ENOMEM; 2432 2433 for (i = 0; i < pctl_desc->npins; i++) { 2434 jzpc->pdesc[i].number = i; 2435 jzpc->pdesc[i].name = kasprintf(GFP_KERNEL, "P%c%d", 2436 'A' + (i / PINS_PER_GPIO_CHIP), 2437 i % PINS_PER_GPIO_CHIP); 2438 } 2439 2440 jzpc->pctl = devm_pinctrl_register(dev, pctl_desc, jzpc); 2441 if (IS_ERR(jzpc->pctl)) { 2442 dev_err(dev, "Failed to register pinctrl\n"); 2443 return PTR_ERR(jzpc->pctl); 2444 } 2445 2446 for (i = 0; i < chip_info->num_groups; i++) { 2447 const struct group_desc *group = &chip_info->groups[i]; 2448 2449 err = pinctrl_generic_add_group(jzpc->pctl, group->name, 2450 group->pins, group->num_pins, group->data); 2451 if (err < 0) { 2452 dev_err(dev, "Failed to register group %s\n", 2453 group->name); 2454 return err; 2455 } 2456 } 2457 2458 for (i = 0; i < chip_info->num_functions; i++) { 2459 const struct function_desc *func = &chip_info->functions[i]; 2460 2461 err = pinmux_generic_add_function(jzpc->pctl, func->name, 2462 func->group_names, func->num_group_names, 2463 func->data); 2464 if (err < 0) { 2465 dev_err(dev, "Failed to register function %s\n", 2466 func->name); 2467 return err; 2468 } 2469 } 2470 2471 dev_set_drvdata(dev, jzpc->map); 2472 2473 for_each_child_of_node(dev->of_node, node) { 2474 if (of_match_node(ingenic_gpio_of_match, node)) { 2475 err = ingenic_gpio_probe(jzpc, node); 2476 if (err) 2477 return err; 2478 } 2479 } 2480 2481 return 0; 2482 } 2483 2484 static const struct of_device_id ingenic_pinctrl_of_match[] = { 2485 { .compatible = "ingenic,jz4740-pinctrl", .data = &jz4740_chip_info }, 2486 { .compatible = "ingenic,jz4725b-pinctrl", .data = &jz4725b_chip_info }, 2487 { .compatible = "ingenic,jz4760-pinctrl", .data = &jz4760_chip_info }, 2488 { .compatible = "ingenic,jz4760b-pinctrl", .data = &jz4760_chip_info }, 2489 { .compatible = "ingenic,jz4770-pinctrl", .data = &jz4770_chip_info }, 2490 { .compatible = "ingenic,jz4780-pinctrl", .data = &jz4780_chip_info }, 2491 { .compatible = "ingenic,x1000-pinctrl", .data = &x1000_chip_info }, 2492 { .compatible = "ingenic,x1000e-pinctrl", .data = &x1000_chip_info }, 2493 { .compatible = "ingenic,x1500-pinctrl", .data = &x1500_chip_info }, 2494 { .compatible = "ingenic,x1830-pinctrl", .data = &x1830_chip_info }, 2495 {}, 2496 }; 2497 2498 static struct platform_driver ingenic_pinctrl_driver = { 2499 .driver = { 2500 .name = "pinctrl-ingenic", 2501 .of_match_table = ingenic_pinctrl_of_match, 2502 }, 2503 }; 2504 2505 static int __init ingenic_pinctrl_drv_register(void) 2506 { 2507 return platform_driver_probe(&ingenic_pinctrl_driver, 2508 ingenic_pinctrl_probe); 2509 } 2510 subsys_initcall(ingenic_pinctrl_drv_register); 2511