1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Ingenic SoCs pinctrl driver 4 * 5 * Copyright (c) 2017 Paul Cercueil <paul@crapouillou.net> 6 * Copyright (c) 2019 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> 7 * Copyright (c) 2017, 2019 Paul Boddie <paul@boddie.org.uk> 8 */ 9 10 #include <linux/compiler.h> 11 #include <linux/gpio/driver.h> 12 #include <linux/interrupt.h> 13 #include <linux/io.h> 14 #include <linux/of_device.h> 15 #include <linux/of_irq.h> 16 #include <linux/of_platform.h> 17 #include <linux/pinctrl/pinctrl.h> 18 #include <linux/pinctrl/pinmux.h> 19 #include <linux/pinctrl/pinconf.h> 20 #include <linux/pinctrl/pinconf-generic.h> 21 #include <linux/platform_device.h> 22 #include <linux/regmap.h> 23 #include <linux/slab.h> 24 25 #include "core.h" 26 #include "pinconf.h" 27 #include "pinmux.h" 28 29 #define GPIO_PIN 0x00 30 #define GPIO_MSK 0x20 31 32 #define JZ4740_GPIO_DATA 0x10 33 #define JZ4740_GPIO_PULL_DIS 0x30 34 #define JZ4740_GPIO_FUNC 0x40 35 #define JZ4740_GPIO_SELECT 0x50 36 #define JZ4740_GPIO_DIR 0x60 37 #define JZ4740_GPIO_TRIG 0x70 38 #define JZ4740_GPIO_FLAG 0x80 39 40 #define JZ4760_GPIO_INT 0x10 41 #define JZ4760_GPIO_PAT1 0x30 42 #define JZ4760_GPIO_PAT0 0x40 43 #define JZ4760_GPIO_FLAG 0x50 44 #define JZ4760_GPIO_PEN 0x70 45 46 #define X1830_GPIO_PEL 0x110 47 #define X1830_GPIO_PEH 0x120 48 49 #define REG_SET(x) ((x) + 0x4) 50 #define REG_CLEAR(x) ((x) + 0x8) 51 52 #define REG_PZ_BASE(x) ((x) * 7) 53 #define REG_PZ_GID2LD(x) ((x) * 7 + 0xf0) 54 55 #define GPIO_PULL_DIS 0 56 #define GPIO_PULL_UP 1 57 #define GPIO_PULL_DOWN 2 58 59 #define PINS_PER_GPIO_CHIP 32 60 61 enum jz_version { 62 ID_JZ4740, 63 ID_JZ4725B, 64 ID_JZ4760, 65 ID_JZ4770, 66 ID_JZ4780, 67 ID_X1000, 68 ID_X1500, 69 ID_X1830, 70 }; 71 72 struct ingenic_chip_info { 73 unsigned int num_chips; 74 unsigned int reg_offset; 75 enum jz_version version; 76 77 const struct group_desc *groups; 78 unsigned int num_groups; 79 80 const struct function_desc *functions; 81 unsigned int num_functions; 82 83 const u32 *pull_ups, *pull_downs; 84 }; 85 86 struct ingenic_pinctrl { 87 struct device *dev; 88 struct regmap *map; 89 struct pinctrl_dev *pctl; 90 struct pinctrl_pin_desc *pdesc; 91 92 const struct ingenic_chip_info *info; 93 }; 94 95 struct ingenic_gpio_chip { 96 struct ingenic_pinctrl *jzpc; 97 struct gpio_chip gc; 98 struct irq_chip irq_chip; 99 unsigned int irq, reg_base; 100 }; 101 102 static const u32 jz4740_pull_ups[4] = { 103 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 104 }; 105 106 static const u32 jz4740_pull_downs[4] = { 107 0x00000000, 0x00000000, 0x00000000, 0x00000000, 108 }; 109 110 static int jz4740_mmc_1bit_pins[] = { 0x69, 0x68, 0x6a, }; 111 static int jz4740_mmc_4bit_pins[] = { 0x6b, 0x6c, 0x6d, }; 112 static int jz4740_uart0_data_pins[] = { 0x7a, 0x79, }; 113 static int jz4740_uart0_hwflow_pins[] = { 0x7e, 0x7f, }; 114 static int jz4740_uart1_data_pins[] = { 0x7e, 0x7f, }; 115 static int jz4740_lcd_8bit_pins[] = { 116 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x52, 0x53, 0x54, 117 }; 118 static int jz4740_lcd_16bit_pins[] = { 119 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, 0x55, 120 }; 121 static int jz4740_lcd_18bit_pins[] = { 0x50, 0x51, }; 122 static int jz4740_lcd_18bit_tft_pins[] = { 0x56, 0x57, 0x31, 0x32, }; 123 static int jz4740_nand_cs1_pins[] = { 0x39, }; 124 static int jz4740_nand_cs2_pins[] = { 0x3a, }; 125 static int jz4740_nand_cs3_pins[] = { 0x3b, }; 126 static int jz4740_nand_cs4_pins[] = { 0x3c, }; 127 static int jz4740_nand_fre_fwe_pins[] = { 0x5c, 0x5d, }; 128 static int jz4740_pwm_pwm0_pins[] = { 0x77, }; 129 static int jz4740_pwm_pwm1_pins[] = { 0x78, }; 130 static int jz4740_pwm_pwm2_pins[] = { 0x79, }; 131 static int jz4740_pwm_pwm3_pins[] = { 0x7a, }; 132 static int jz4740_pwm_pwm4_pins[] = { 0x7b, }; 133 static int jz4740_pwm_pwm5_pins[] = { 0x7c, }; 134 static int jz4740_pwm_pwm6_pins[] = { 0x7e, }; 135 static int jz4740_pwm_pwm7_pins[] = { 0x7f, }; 136 137 138 #define INGENIC_PIN_GROUP_FUNCS(name, id, funcs) \ 139 { \ 140 name, \ 141 id##_pins, \ 142 ARRAY_SIZE(id##_pins), \ 143 funcs, \ 144 } 145 146 #define INGENIC_PIN_GROUP(name, id, func) \ 147 INGENIC_PIN_GROUP_FUNCS(name, id, (void *)(func)) 148 149 static const struct group_desc jz4740_groups[] = { 150 INGENIC_PIN_GROUP("mmc-1bit", jz4740_mmc_1bit, 0), 151 INGENIC_PIN_GROUP("mmc-4bit", jz4740_mmc_4bit, 0), 152 INGENIC_PIN_GROUP("uart0-data", jz4740_uart0_data, 1), 153 INGENIC_PIN_GROUP("uart0-hwflow", jz4740_uart0_hwflow, 1), 154 INGENIC_PIN_GROUP("uart1-data", jz4740_uart1_data, 2), 155 INGENIC_PIN_GROUP("lcd-8bit", jz4740_lcd_8bit, 0), 156 INGENIC_PIN_GROUP("lcd-16bit", jz4740_lcd_16bit, 0), 157 INGENIC_PIN_GROUP("lcd-18bit", jz4740_lcd_18bit, 0), 158 INGENIC_PIN_GROUP("lcd-18bit-tft", jz4740_lcd_18bit_tft, 0), 159 { "lcd-no-pins", }, 160 INGENIC_PIN_GROUP("nand-cs1", jz4740_nand_cs1, 0), 161 INGENIC_PIN_GROUP("nand-cs2", jz4740_nand_cs2, 0), 162 INGENIC_PIN_GROUP("nand-cs3", jz4740_nand_cs3, 0), 163 INGENIC_PIN_GROUP("nand-cs4", jz4740_nand_cs4, 0), 164 INGENIC_PIN_GROUP("nand-fre-fwe", jz4740_nand_fre_fwe, 0), 165 INGENIC_PIN_GROUP("pwm0", jz4740_pwm_pwm0, 0), 166 INGENIC_PIN_GROUP("pwm1", jz4740_pwm_pwm1, 0), 167 INGENIC_PIN_GROUP("pwm2", jz4740_pwm_pwm2, 0), 168 INGENIC_PIN_GROUP("pwm3", jz4740_pwm_pwm3, 0), 169 INGENIC_PIN_GROUP("pwm4", jz4740_pwm_pwm4, 0), 170 INGENIC_PIN_GROUP("pwm5", jz4740_pwm_pwm5, 0), 171 INGENIC_PIN_GROUP("pwm6", jz4740_pwm_pwm6, 0), 172 INGENIC_PIN_GROUP("pwm7", jz4740_pwm_pwm7, 0), 173 }; 174 175 static const char *jz4740_mmc_groups[] = { "mmc-1bit", "mmc-4bit", }; 176 static const char *jz4740_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; 177 static const char *jz4740_uart1_groups[] = { "uart1-data", }; 178 static const char *jz4740_lcd_groups[] = { 179 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-18bit-tft", "lcd-no-pins", 180 }; 181 static const char *jz4740_nand_groups[] = { 182 "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", "nand-fre-fwe", 183 }; 184 static const char *jz4740_pwm0_groups[] = { "pwm0", }; 185 static const char *jz4740_pwm1_groups[] = { "pwm1", }; 186 static const char *jz4740_pwm2_groups[] = { "pwm2", }; 187 static const char *jz4740_pwm3_groups[] = { "pwm3", }; 188 static const char *jz4740_pwm4_groups[] = { "pwm4", }; 189 static const char *jz4740_pwm5_groups[] = { "pwm5", }; 190 static const char *jz4740_pwm6_groups[] = { "pwm6", }; 191 static const char *jz4740_pwm7_groups[] = { "pwm7", }; 192 193 static const struct function_desc jz4740_functions[] = { 194 { "mmc", jz4740_mmc_groups, ARRAY_SIZE(jz4740_mmc_groups), }, 195 { "uart0", jz4740_uart0_groups, ARRAY_SIZE(jz4740_uart0_groups), }, 196 { "uart1", jz4740_uart1_groups, ARRAY_SIZE(jz4740_uart1_groups), }, 197 { "lcd", jz4740_lcd_groups, ARRAY_SIZE(jz4740_lcd_groups), }, 198 { "nand", jz4740_nand_groups, ARRAY_SIZE(jz4740_nand_groups), }, 199 { "pwm0", jz4740_pwm0_groups, ARRAY_SIZE(jz4740_pwm0_groups), }, 200 { "pwm1", jz4740_pwm1_groups, ARRAY_SIZE(jz4740_pwm1_groups), }, 201 { "pwm2", jz4740_pwm2_groups, ARRAY_SIZE(jz4740_pwm2_groups), }, 202 { "pwm3", jz4740_pwm3_groups, ARRAY_SIZE(jz4740_pwm3_groups), }, 203 { "pwm4", jz4740_pwm4_groups, ARRAY_SIZE(jz4740_pwm4_groups), }, 204 { "pwm5", jz4740_pwm5_groups, ARRAY_SIZE(jz4740_pwm5_groups), }, 205 { "pwm6", jz4740_pwm6_groups, ARRAY_SIZE(jz4740_pwm6_groups), }, 206 { "pwm7", jz4740_pwm7_groups, ARRAY_SIZE(jz4740_pwm7_groups), }, 207 }; 208 209 static const struct ingenic_chip_info jz4740_chip_info = { 210 .num_chips = 4, 211 .reg_offset = 0x100, 212 .version = ID_JZ4740, 213 .groups = jz4740_groups, 214 .num_groups = ARRAY_SIZE(jz4740_groups), 215 .functions = jz4740_functions, 216 .num_functions = ARRAY_SIZE(jz4740_functions), 217 .pull_ups = jz4740_pull_ups, 218 .pull_downs = jz4740_pull_downs, 219 }; 220 221 static int jz4725b_mmc0_1bit_pins[] = { 0x48, 0x49, 0x5c, }; 222 static int jz4725b_mmc0_4bit_pins[] = { 0x5d, 0x5b, 0x56, }; 223 static int jz4725b_mmc1_1bit_pins[] = { 0x7a, 0x7b, 0x7c, }; 224 static int jz4725b_mmc1_4bit_pins[] = { 0x7d, 0x7e, 0x7f, }; 225 static int jz4725b_uart_data_pins[] = { 0x4c, 0x4d, }; 226 static int jz4725b_nand_cs1_pins[] = { 0x55, }; 227 static int jz4725b_nand_cs2_pins[] = { 0x56, }; 228 static int jz4725b_nand_cs3_pins[] = { 0x57, }; 229 static int jz4725b_nand_cs4_pins[] = { 0x58, }; 230 static int jz4725b_nand_cle_ale_pins[] = { 0x48, 0x49 }; 231 static int jz4725b_nand_fre_fwe_pins[] = { 0x5c, 0x5d }; 232 static int jz4725b_pwm_pwm0_pins[] = { 0x4a, }; 233 static int jz4725b_pwm_pwm1_pins[] = { 0x4b, }; 234 static int jz4725b_pwm_pwm2_pins[] = { 0x4c, }; 235 static int jz4725b_pwm_pwm3_pins[] = { 0x4d, }; 236 static int jz4725b_pwm_pwm4_pins[] = { 0x4e, }; 237 static int jz4725b_pwm_pwm5_pins[] = { 0x4f, }; 238 static int jz4725b_lcd_8bit_pins[] = { 239 0x72, 0x73, 0x74, 240 0x60, 0x61, 0x62, 0x63, 241 0x64, 0x65, 0x66, 0x67, 242 }; 243 static int jz4725b_lcd_16bit_pins[] = { 244 0x68, 0x69, 0x6a, 0x6b, 245 0x6c, 0x6d, 0x6e, 0x6f, 246 }; 247 static int jz4725b_lcd_18bit_pins[] = { 0x70, 0x71, }; 248 static int jz4725b_lcd_24bit_pins[] = { 0x76, 0x77, 0x78, 0x79, }; 249 static int jz4725b_lcd_special_pins[] = { 0x76, 0x77, 0x78, 0x79, }; 250 static int jz4725b_lcd_generic_pins[] = { 0x75, }; 251 252 static u8 jz4725b_mmc0_4bit_funcs[] = { 1, 0, 1, }; 253 254 static const struct group_desc jz4725b_groups[] = { 255 INGENIC_PIN_GROUP("mmc0-1bit", jz4725b_mmc0_1bit, 1), 256 INGENIC_PIN_GROUP_FUNCS("mmc0-4bit", jz4725b_mmc0_4bit, 257 jz4725b_mmc0_4bit_funcs), 258 INGENIC_PIN_GROUP("mmc1-1bit", jz4725b_mmc1_1bit, 0), 259 INGENIC_PIN_GROUP("mmc1-4bit", jz4725b_mmc1_4bit, 0), 260 INGENIC_PIN_GROUP("uart-data", jz4725b_uart_data, 1), 261 INGENIC_PIN_GROUP("nand-cs1", jz4725b_nand_cs1, 0), 262 INGENIC_PIN_GROUP("nand-cs2", jz4725b_nand_cs2, 0), 263 INGENIC_PIN_GROUP("nand-cs3", jz4725b_nand_cs3, 0), 264 INGENIC_PIN_GROUP("nand-cs4", jz4725b_nand_cs4, 0), 265 INGENIC_PIN_GROUP("nand-cle-ale", jz4725b_nand_cle_ale, 0), 266 INGENIC_PIN_GROUP("nand-fre-fwe", jz4725b_nand_fre_fwe, 0), 267 INGENIC_PIN_GROUP("pwm0", jz4725b_pwm_pwm0, 0), 268 INGENIC_PIN_GROUP("pwm1", jz4725b_pwm_pwm1, 0), 269 INGENIC_PIN_GROUP("pwm2", jz4725b_pwm_pwm2, 0), 270 INGENIC_PIN_GROUP("pwm3", jz4725b_pwm_pwm3, 0), 271 INGENIC_PIN_GROUP("pwm4", jz4725b_pwm_pwm4, 0), 272 INGENIC_PIN_GROUP("pwm5", jz4725b_pwm_pwm5, 0), 273 INGENIC_PIN_GROUP("lcd-8bit", jz4725b_lcd_8bit, 0), 274 INGENIC_PIN_GROUP("lcd-16bit", jz4725b_lcd_16bit, 0), 275 INGENIC_PIN_GROUP("lcd-18bit", jz4725b_lcd_18bit, 0), 276 INGENIC_PIN_GROUP("lcd-24bit", jz4725b_lcd_24bit, 1), 277 INGENIC_PIN_GROUP("lcd-special", jz4725b_lcd_special, 0), 278 INGENIC_PIN_GROUP("lcd-generic", jz4725b_lcd_generic, 0), 279 }; 280 281 static const char *jz4725b_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", }; 282 static const char *jz4725b_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", }; 283 static const char *jz4725b_uart_groups[] = { "uart-data", }; 284 static const char *jz4725b_nand_groups[] = { 285 "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", 286 "nand-cle-ale", "nand-fre-fwe", 287 }; 288 static const char *jz4725b_pwm0_groups[] = { "pwm0", }; 289 static const char *jz4725b_pwm1_groups[] = { "pwm1", }; 290 static const char *jz4725b_pwm2_groups[] = { "pwm2", }; 291 static const char *jz4725b_pwm3_groups[] = { "pwm3", }; 292 static const char *jz4725b_pwm4_groups[] = { "pwm4", }; 293 static const char *jz4725b_pwm5_groups[] = { "pwm5", }; 294 static const char *jz4725b_lcd_groups[] = { 295 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit", 296 "lcd-special", "lcd-generic", 297 }; 298 299 static const struct function_desc jz4725b_functions[] = { 300 { "mmc0", jz4725b_mmc0_groups, ARRAY_SIZE(jz4725b_mmc0_groups), }, 301 { "mmc1", jz4725b_mmc1_groups, ARRAY_SIZE(jz4725b_mmc1_groups), }, 302 { "uart", jz4725b_uart_groups, ARRAY_SIZE(jz4725b_uart_groups), }, 303 { "nand", jz4725b_nand_groups, ARRAY_SIZE(jz4725b_nand_groups), }, 304 { "pwm0", jz4725b_pwm0_groups, ARRAY_SIZE(jz4725b_pwm0_groups), }, 305 { "pwm1", jz4725b_pwm1_groups, ARRAY_SIZE(jz4725b_pwm1_groups), }, 306 { "pwm2", jz4725b_pwm2_groups, ARRAY_SIZE(jz4725b_pwm2_groups), }, 307 { "pwm3", jz4725b_pwm3_groups, ARRAY_SIZE(jz4725b_pwm3_groups), }, 308 { "pwm4", jz4725b_pwm4_groups, ARRAY_SIZE(jz4725b_pwm4_groups), }, 309 { "pwm5", jz4725b_pwm5_groups, ARRAY_SIZE(jz4725b_pwm5_groups), }, 310 { "lcd", jz4725b_lcd_groups, ARRAY_SIZE(jz4725b_lcd_groups), }, 311 }; 312 313 static const struct ingenic_chip_info jz4725b_chip_info = { 314 .num_chips = 4, 315 .reg_offset = 0x100, 316 .version = ID_JZ4725B, 317 .groups = jz4725b_groups, 318 .num_groups = ARRAY_SIZE(jz4725b_groups), 319 .functions = jz4725b_functions, 320 .num_functions = ARRAY_SIZE(jz4725b_functions), 321 .pull_ups = jz4740_pull_ups, 322 .pull_downs = jz4740_pull_downs, 323 }; 324 325 static const u32 jz4760_pull_ups[6] = { 326 0xffffffff, 0xfffcf3ff, 0xffffffff, 0xffffcfff, 0xfffffb7c, 0xfffff00f, 327 }; 328 329 static const u32 jz4760_pull_downs[6] = { 330 0x00000000, 0x00030c00, 0x00000000, 0x00003000, 0x00000483, 0x00000ff0, 331 }; 332 333 static int jz4760_uart0_data_pins[] = { 0xa0, 0xa3, }; 334 static int jz4760_uart0_hwflow_pins[] = { 0xa1, 0xa2, }; 335 static int jz4760_uart1_data_pins[] = { 0x7a, 0x7c, }; 336 static int jz4760_uart1_hwflow_pins[] = { 0x7b, 0x7d, }; 337 static int jz4760_uart2_data_pins[] = { 0x5c, 0x5e, }; 338 static int jz4760_uart2_hwflow_pins[] = { 0x5d, 0x5f, }; 339 static int jz4760_uart3_data_pins[] = { 0x6c, 0x85, }; 340 static int jz4760_uart3_hwflow_pins[] = { 0x88, 0x89, }; 341 static int jz4760_mmc0_1bit_a_pins[] = { 0x12, 0x13, 0x14, }; 342 static int jz4760_mmc0_4bit_a_pins[] = { 0x15, 0x16, 0x17, }; 343 static int jz4760_mmc0_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; 344 static int jz4760_mmc0_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; 345 static int jz4760_mmc0_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, }; 346 static int jz4760_mmc1_1bit_d_pins[] = { 0x78, 0x79, 0x74, }; 347 static int jz4760_mmc1_4bit_d_pins[] = { 0x75, 0x76, 0x77, }; 348 static int jz4760_mmc1_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; 349 static int jz4760_mmc1_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; 350 static int jz4760_mmc1_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, }; 351 static int jz4760_mmc2_1bit_b_pins[] = { 0x3c, 0x3d, 0x34, }; 352 static int jz4760_mmc2_4bit_b_pins[] = { 0x35, 0x3e, 0x3f, }; 353 static int jz4760_mmc2_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; 354 static int jz4760_mmc2_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; 355 static int jz4760_mmc2_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, }; 356 static int jz4760_nemc_8bit_data_pins[] = { 357 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 358 }; 359 static int jz4760_nemc_16bit_data_pins[] = { 360 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 361 }; 362 static int jz4760_nemc_cle_ale_pins[] = { 0x20, 0x21, }; 363 static int jz4760_nemc_addr_pins[] = { 0x22, 0x23, 0x24, 0x25, }; 364 static int jz4760_nemc_rd_we_pins[] = { 0x10, 0x11, }; 365 static int jz4760_nemc_frd_fwe_pins[] = { 0x12, 0x13, }; 366 static int jz4760_nemc_wait_pins[] = { 0x1b, }; 367 static int jz4760_nemc_cs1_pins[] = { 0x15, }; 368 static int jz4760_nemc_cs2_pins[] = { 0x16, }; 369 static int jz4760_nemc_cs3_pins[] = { 0x17, }; 370 static int jz4760_nemc_cs4_pins[] = { 0x18, }; 371 static int jz4760_nemc_cs5_pins[] = { 0x19, }; 372 static int jz4760_nemc_cs6_pins[] = { 0x1a, }; 373 static int jz4760_i2c0_pins[] = { 0x7e, 0x7f, }; 374 static int jz4760_i2c1_pins[] = { 0x9e, 0x9f, }; 375 static int jz4760_cim_pins[] = { 376 0x26, 0x27, 0x28, 0x29, 377 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31, 378 }; 379 static int jz4760_lcd_24bit_pins[] = { 380 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 381 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, 382 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 383 0x58, 0x59, 0x5a, 0x5b, 384 }; 385 static int jz4760_pwm_pwm0_pins[] = { 0x80, }; 386 static int jz4760_pwm_pwm1_pins[] = { 0x81, }; 387 static int jz4760_pwm_pwm2_pins[] = { 0x82, }; 388 static int jz4760_pwm_pwm3_pins[] = { 0x83, }; 389 static int jz4760_pwm_pwm4_pins[] = { 0x84, }; 390 static int jz4760_pwm_pwm5_pins[] = { 0x85, }; 391 static int jz4760_pwm_pwm6_pins[] = { 0x6a, }; 392 static int jz4760_pwm_pwm7_pins[] = { 0x6b, }; 393 394 static u8 jz4760_uart3_data_funcs[] = { 0, 1, }; 395 static u8 jz4760_mmc0_1bit_a_funcs[] = { 1, 1, 0, }; 396 397 static const struct group_desc jz4760_groups[] = { 398 INGENIC_PIN_GROUP("uart0-data", jz4760_uart0_data, 0), 399 INGENIC_PIN_GROUP("uart0-hwflow", jz4760_uart0_hwflow, 0), 400 INGENIC_PIN_GROUP("uart1-data", jz4760_uart1_data, 0), 401 INGENIC_PIN_GROUP("uart1-hwflow", jz4760_uart1_hwflow, 0), 402 INGENIC_PIN_GROUP("uart2-data", jz4760_uart2_data, 0), 403 INGENIC_PIN_GROUP("uart2-hwflow", jz4760_uart2_hwflow, 0), 404 INGENIC_PIN_GROUP_FUNCS("uart3-data", jz4760_uart3_data, 405 jz4760_uart3_data_funcs), 406 INGENIC_PIN_GROUP("uart3-hwflow", jz4760_uart3_hwflow, 0), 407 INGENIC_PIN_GROUP_FUNCS("mmc0-1bit-a", jz4760_mmc0_1bit_a, 408 jz4760_mmc0_1bit_a_funcs), 409 INGENIC_PIN_GROUP("mmc0-4bit-a", jz4760_mmc0_4bit_a, 1), 410 INGENIC_PIN_GROUP("mmc0-1bit-e", jz4760_mmc0_1bit_e, 0), 411 INGENIC_PIN_GROUP("mmc0-4bit-e", jz4760_mmc0_4bit_e, 0), 412 INGENIC_PIN_GROUP("mmc0-8bit-e", jz4760_mmc0_8bit_e, 0), 413 INGENIC_PIN_GROUP("mmc1-1bit-d", jz4760_mmc1_1bit_d, 0), 414 INGENIC_PIN_GROUP("mmc1-4bit-d", jz4760_mmc1_4bit_d, 0), 415 INGENIC_PIN_GROUP("mmc1-1bit-e", jz4760_mmc1_1bit_e, 1), 416 INGENIC_PIN_GROUP("mmc1-4bit-e", jz4760_mmc1_4bit_e, 1), 417 INGENIC_PIN_GROUP("mmc1-8bit-e", jz4760_mmc1_8bit_e, 1), 418 INGENIC_PIN_GROUP("mmc2-1bit-b", jz4760_mmc2_1bit_b, 0), 419 INGENIC_PIN_GROUP("mmc2-4bit-b", jz4760_mmc2_4bit_b, 0), 420 INGENIC_PIN_GROUP("mmc2-1bit-e", jz4760_mmc2_1bit_e, 2), 421 INGENIC_PIN_GROUP("mmc2-4bit-e", jz4760_mmc2_4bit_e, 2), 422 INGENIC_PIN_GROUP("mmc2-8bit-e", jz4760_mmc2_8bit_e, 2), 423 INGENIC_PIN_GROUP("nemc-8bit-data", jz4760_nemc_8bit_data, 0), 424 INGENIC_PIN_GROUP("nemc-16bit-data", jz4760_nemc_16bit_data, 0), 425 INGENIC_PIN_GROUP("nemc-cle-ale", jz4760_nemc_cle_ale, 0), 426 INGENIC_PIN_GROUP("nemc-addr", jz4760_nemc_addr, 0), 427 INGENIC_PIN_GROUP("nemc-rd-we", jz4760_nemc_rd_we, 0), 428 INGENIC_PIN_GROUP("nemc-frd-fwe", jz4760_nemc_frd_fwe, 0), 429 INGENIC_PIN_GROUP("nemc-wait", jz4760_nemc_wait, 0), 430 INGENIC_PIN_GROUP("nemc-cs1", jz4760_nemc_cs1, 0), 431 INGENIC_PIN_GROUP("nemc-cs2", jz4760_nemc_cs2, 0), 432 INGENIC_PIN_GROUP("nemc-cs3", jz4760_nemc_cs3, 0), 433 INGENIC_PIN_GROUP("nemc-cs4", jz4760_nemc_cs4, 0), 434 INGENIC_PIN_GROUP("nemc-cs5", jz4760_nemc_cs5, 0), 435 INGENIC_PIN_GROUP("nemc-cs6", jz4760_nemc_cs6, 0), 436 INGENIC_PIN_GROUP("i2c0-data", jz4760_i2c0, 0), 437 INGENIC_PIN_GROUP("i2c1-data", jz4760_i2c1, 0), 438 INGENIC_PIN_GROUP("cim-data", jz4760_cim, 0), 439 INGENIC_PIN_GROUP("lcd-24bit", jz4760_lcd_24bit, 0), 440 { "lcd-no-pins", }, 441 INGENIC_PIN_GROUP("pwm0", jz4760_pwm_pwm0, 0), 442 INGENIC_PIN_GROUP("pwm1", jz4760_pwm_pwm1, 0), 443 INGENIC_PIN_GROUP("pwm2", jz4760_pwm_pwm2, 0), 444 INGENIC_PIN_GROUP("pwm3", jz4760_pwm_pwm3, 0), 445 INGENIC_PIN_GROUP("pwm4", jz4760_pwm_pwm4, 0), 446 INGENIC_PIN_GROUP("pwm5", jz4760_pwm_pwm5, 0), 447 INGENIC_PIN_GROUP("pwm6", jz4760_pwm_pwm6, 0), 448 INGENIC_PIN_GROUP("pwm7", jz4760_pwm_pwm7, 0), 449 }; 450 451 static const char *jz4760_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; 452 static const char *jz4760_uart1_groups[] = { "uart1-data", "uart1-hwflow", }; 453 static const char *jz4760_uart2_groups[] = { "uart2-data", "uart2-hwflow", }; 454 static const char *jz4760_uart3_groups[] = { "uart3-data", "uart3-hwflow", }; 455 static const char *jz4760_mmc0_groups[] = { 456 "mmc0-1bit-a", "mmc0-4bit-a", 457 "mmc0-1bit-e", "mmc0-4bit-e", "mmc0-8bit-e", 458 }; 459 static const char *jz4760_mmc1_groups[] = { 460 "mmc1-1bit-d", "mmc1-4bit-d", 461 "mmc1-1bit-e", "mmc1-4bit-e", "mmc1-8bit-e", 462 }; 463 static const char *jz4760_mmc2_groups[] = { 464 "mmc2-1bit-b", "mmc2-4bit-b", 465 "mmc2-1bit-e", "mmc2-4bit-e", "mmc2-8bit-e", 466 }; 467 static const char *jz4760_nemc_groups[] = { 468 "nemc-8bit-data", "nemc-16bit-data", "nemc-cle-ale", 469 "nemc-addr", "nemc-rd-we", "nemc-frd-fwe", "nemc-wait", 470 }; 471 static const char *jz4760_cs1_groups[] = { "nemc-cs1", }; 472 static const char *jz4760_cs2_groups[] = { "nemc-cs2", }; 473 static const char *jz4760_cs3_groups[] = { "nemc-cs3", }; 474 static const char *jz4760_cs4_groups[] = { "nemc-cs4", }; 475 static const char *jz4760_cs5_groups[] = { "nemc-cs5", }; 476 static const char *jz4760_cs6_groups[] = { "nemc-cs6", }; 477 static const char *jz4760_i2c0_groups[] = { "i2c0-data", }; 478 static const char *jz4760_i2c1_groups[] = { "i2c1-data", }; 479 static const char *jz4760_cim_groups[] = { "cim-data", }; 480 static const char *jz4760_lcd_groups[] = { "lcd-24bit", "lcd-no-pins", }; 481 static const char *jz4760_pwm0_groups[] = { "pwm0", }; 482 static const char *jz4760_pwm1_groups[] = { "pwm1", }; 483 static const char *jz4760_pwm2_groups[] = { "pwm2", }; 484 static const char *jz4760_pwm3_groups[] = { "pwm3", }; 485 static const char *jz4760_pwm4_groups[] = { "pwm4", }; 486 static const char *jz4760_pwm5_groups[] = { "pwm5", }; 487 static const char *jz4760_pwm6_groups[] = { "pwm6", }; 488 static const char *jz4760_pwm7_groups[] = { "pwm7", }; 489 490 static const struct function_desc jz4760_functions[] = { 491 { "uart0", jz4760_uart0_groups, ARRAY_SIZE(jz4760_uart0_groups), }, 492 { "uart1", jz4760_uart1_groups, ARRAY_SIZE(jz4760_uart1_groups), }, 493 { "uart2", jz4760_uart2_groups, ARRAY_SIZE(jz4760_uart2_groups), }, 494 { "uart3", jz4760_uart3_groups, ARRAY_SIZE(jz4760_uart3_groups), }, 495 { "mmc0", jz4760_mmc0_groups, ARRAY_SIZE(jz4760_mmc0_groups), }, 496 { "mmc1", jz4760_mmc1_groups, ARRAY_SIZE(jz4760_mmc1_groups), }, 497 { "mmc2", jz4760_mmc2_groups, ARRAY_SIZE(jz4760_mmc2_groups), }, 498 { "nemc", jz4760_nemc_groups, ARRAY_SIZE(jz4760_nemc_groups), }, 499 { "nemc-cs1", jz4760_cs1_groups, ARRAY_SIZE(jz4760_cs1_groups), }, 500 { "nemc-cs2", jz4760_cs2_groups, ARRAY_SIZE(jz4760_cs2_groups), }, 501 { "nemc-cs3", jz4760_cs3_groups, ARRAY_SIZE(jz4760_cs3_groups), }, 502 { "nemc-cs4", jz4760_cs4_groups, ARRAY_SIZE(jz4760_cs4_groups), }, 503 { "nemc-cs5", jz4760_cs5_groups, ARRAY_SIZE(jz4760_cs5_groups), }, 504 { "nemc-cs6", jz4760_cs6_groups, ARRAY_SIZE(jz4760_cs6_groups), }, 505 { "i2c0", jz4760_i2c0_groups, ARRAY_SIZE(jz4760_i2c0_groups), }, 506 { "i2c1", jz4760_i2c1_groups, ARRAY_SIZE(jz4760_i2c1_groups), }, 507 { "cim", jz4760_cim_groups, ARRAY_SIZE(jz4760_cim_groups), }, 508 { "lcd", jz4760_lcd_groups, ARRAY_SIZE(jz4760_lcd_groups), }, 509 { "pwm0", jz4760_pwm0_groups, ARRAY_SIZE(jz4760_pwm0_groups), }, 510 { "pwm1", jz4760_pwm1_groups, ARRAY_SIZE(jz4760_pwm1_groups), }, 511 { "pwm2", jz4760_pwm2_groups, ARRAY_SIZE(jz4760_pwm2_groups), }, 512 { "pwm3", jz4760_pwm3_groups, ARRAY_SIZE(jz4760_pwm3_groups), }, 513 { "pwm4", jz4760_pwm4_groups, ARRAY_SIZE(jz4760_pwm4_groups), }, 514 { "pwm5", jz4760_pwm5_groups, ARRAY_SIZE(jz4760_pwm5_groups), }, 515 { "pwm6", jz4760_pwm6_groups, ARRAY_SIZE(jz4760_pwm6_groups), }, 516 { "pwm7", jz4760_pwm7_groups, ARRAY_SIZE(jz4760_pwm7_groups), }, 517 }; 518 519 static const struct ingenic_chip_info jz4760_chip_info = { 520 .num_chips = 6, 521 .reg_offset = 0x100, 522 .version = ID_JZ4760, 523 .groups = jz4760_groups, 524 .num_groups = ARRAY_SIZE(jz4760_groups), 525 .functions = jz4760_functions, 526 .num_functions = ARRAY_SIZE(jz4760_functions), 527 .pull_ups = jz4760_pull_ups, 528 .pull_downs = jz4760_pull_downs, 529 }; 530 531 static const u32 jz4770_pull_ups[6] = { 532 0x3fffffff, 0xfff0030c, 0xffffffff, 0xffff4fff, 0xfffffb7c, 0xffa7f00f, 533 }; 534 535 static const u32 jz4770_pull_downs[6] = { 536 0x00000000, 0x000f0c03, 0x00000000, 0x0000b000, 0x00000483, 0x00580ff0, 537 }; 538 539 static int jz4770_uart0_data_pins[] = { 0xa0, 0xa3, }; 540 static int jz4770_uart0_hwflow_pins[] = { 0xa1, 0xa2, }; 541 static int jz4770_uart1_data_pins[] = { 0x7a, 0x7c, }; 542 static int jz4770_uart1_hwflow_pins[] = { 0x7b, 0x7d, }; 543 static int jz4770_uart2_data_pins[] = { 0x5c, 0x5e, }; 544 static int jz4770_uart2_hwflow_pins[] = { 0x5d, 0x5f, }; 545 static int jz4770_uart3_data_pins[] = { 0x6c, 0x85, }; 546 static int jz4770_uart3_hwflow_pins[] = { 0x88, 0x89, }; 547 static int jz4770_ssi0_dt_a_pins[] = { 0x15, }; 548 static int jz4770_ssi0_dt_b_pins[] = { 0x35, }; 549 static int jz4770_ssi0_dt_d_pins[] = { 0x75, }; 550 static int jz4770_ssi0_dt_e_pins[] = { 0x91, }; 551 static int jz4770_ssi0_dr_a_pins[] = { 0x14, }; 552 static int jz4770_ssi0_dr_b_pins[] = { 0x34, }; 553 static int jz4770_ssi0_dr_d_pins[] = { 0x74, }; 554 static int jz4770_ssi0_dr_e_pins[] = { 0x8e, }; 555 static int jz4770_ssi0_clk_a_pins[] = { 0x12, }; 556 static int jz4770_ssi0_clk_b_pins[] = { 0x3c, }; 557 static int jz4770_ssi0_clk_d_pins[] = { 0x78, }; 558 static int jz4770_ssi0_clk_e_pins[] = { 0x8f, }; 559 static int jz4770_ssi0_gpc_b_pins[] = { 0x3e, }; 560 static int jz4770_ssi0_gpc_d_pins[] = { 0x76, }; 561 static int jz4770_ssi0_gpc_e_pins[] = { 0x93, }; 562 static int jz4770_ssi0_ce0_a_pins[] = { 0x13, }; 563 static int jz4770_ssi0_ce0_b_pins[] = { 0x3d, }; 564 static int jz4770_ssi0_ce0_d_pins[] = { 0x79, }; 565 static int jz4770_ssi0_ce0_e_pins[] = { 0x90, }; 566 static int jz4770_ssi0_ce1_b_pins[] = { 0x3f, }; 567 static int jz4770_ssi0_ce1_d_pins[] = { 0x77, }; 568 static int jz4770_ssi0_ce1_e_pins[] = { 0x92, }; 569 static int jz4770_ssi1_dt_b_pins[] = { 0x35, }; 570 static int jz4770_ssi1_dt_d_pins[] = { 0x75, }; 571 static int jz4770_ssi1_dt_e_pins[] = { 0x91, }; 572 static int jz4770_ssi1_dr_b_pins[] = { 0x34, }; 573 static int jz4770_ssi1_dr_d_pins[] = { 0x74, }; 574 static int jz4770_ssi1_dr_e_pins[] = { 0x8e, }; 575 static int jz4770_ssi1_clk_b_pins[] = { 0x3c, }; 576 static int jz4770_ssi1_clk_d_pins[] = { 0x78, }; 577 static int jz4770_ssi1_clk_e_pins[] = { 0x8f, }; 578 static int jz4770_ssi1_gpc_b_pins[] = { 0x3e, }; 579 static int jz4770_ssi1_gpc_d_pins[] = { 0x76, }; 580 static int jz4770_ssi1_gpc_e_pins[] = { 0x93, }; 581 static int jz4770_ssi1_ce0_b_pins[] = { 0x3d, }; 582 static int jz4770_ssi1_ce0_d_pins[] = { 0x79, }; 583 static int jz4770_ssi1_ce0_e_pins[] = { 0x90, }; 584 static int jz4770_ssi1_ce1_b_pins[] = { 0x3f, }; 585 static int jz4770_ssi1_ce1_d_pins[] = { 0x77, }; 586 static int jz4770_ssi1_ce1_e_pins[] = { 0x92, }; 587 static int jz4770_mmc0_1bit_a_pins[] = { 0x12, 0x13, 0x14, }; 588 static int jz4770_mmc0_4bit_a_pins[] = { 0x15, 0x16, 0x17, }; 589 static int jz4770_mmc0_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; 590 static int jz4770_mmc0_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; 591 static int jz4770_mmc0_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, }; 592 static int jz4770_mmc1_1bit_d_pins[] = { 0x78, 0x79, 0x74, }; 593 static int jz4770_mmc1_4bit_d_pins[] = { 0x75, 0x76, 0x77, }; 594 static int jz4770_mmc1_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; 595 static int jz4770_mmc1_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; 596 static int jz4770_mmc1_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, }; 597 static int jz4770_mmc2_1bit_b_pins[] = { 0x3c, 0x3d, 0x34, }; 598 static int jz4770_mmc2_4bit_b_pins[] = { 0x35, 0x3e, 0x3f, }; 599 static int jz4770_mmc2_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; 600 static int jz4770_mmc2_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; 601 static int jz4770_mmc2_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, }; 602 static int jz4770_nemc_8bit_data_pins[] = { 603 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 604 }; 605 static int jz4770_nemc_16bit_data_pins[] = { 606 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 607 }; 608 static int jz4770_nemc_cle_ale_pins[] = { 0x20, 0x21, }; 609 static int jz4770_nemc_addr_pins[] = { 0x22, 0x23, 0x24, 0x25, }; 610 static int jz4770_nemc_rd_we_pins[] = { 0x10, 0x11, }; 611 static int jz4770_nemc_frd_fwe_pins[] = { 0x12, 0x13, }; 612 static int jz4770_nemc_wait_pins[] = { 0x1b, }; 613 static int jz4770_nemc_cs1_pins[] = { 0x15, }; 614 static int jz4770_nemc_cs2_pins[] = { 0x16, }; 615 static int jz4770_nemc_cs3_pins[] = { 0x17, }; 616 static int jz4770_nemc_cs4_pins[] = { 0x18, }; 617 static int jz4770_nemc_cs5_pins[] = { 0x19, }; 618 static int jz4770_nemc_cs6_pins[] = { 0x1a, }; 619 static int jz4770_i2c0_pins[] = { 0x7e, 0x7f, }; 620 static int jz4770_i2c1_pins[] = { 0x9e, 0x9f, }; 621 static int jz4770_i2c2_pins[] = { 0xb0, 0xb1, }; 622 static int jz4770_cim_8bit_pins[] = { 623 0x26, 0x27, 0x28, 0x29, 624 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31, 625 }; 626 static int jz4770_cim_12bit_pins[] = { 627 0x32, 0x33, 0xb0, 0xb1, 628 }; 629 static int jz4770_lcd_8bit_pins[] = { 630 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x4c, 0x4d, 631 0x48, 0x49, 0x52, 0x53, 632 }; 633 static int jz4770_lcd_24bit_pins[] = { 634 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 635 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, 636 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 637 0x58, 0x59, 0x5a, 0x5b, 638 }; 639 static int jz4770_pwm_pwm0_pins[] = { 0x80, }; 640 static int jz4770_pwm_pwm1_pins[] = { 0x81, }; 641 static int jz4770_pwm_pwm2_pins[] = { 0x82, }; 642 static int jz4770_pwm_pwm3_pins[] = { 0x83, }; 643 static int jz4770_pwm_pwm4_pins[] = { 0x84, }; 644 static int jz4770_pwm_pwm5_pins[] = { 0x85, }; 645 static int jz4770_pwm_pwm6_pins[] = { 0x6a, }; 646 static int jz4770_pwm_pwm7_pins[] = { 0x6b, }; 647 static int jz4770_mac_rmii_pins[] = { 648 0xa9, 0xab, 0xaa, 0xac, 0xa5, 0xa4, 0xad, 0xae, 0xa6, 0xa8, 649 }; 650 static int jz4770_mac_mii_pins[] = { 0xa7, 0xaf, }; 651 static int jz4770_otg_pins[] = { 0x8a, }; 652 653 static const struct group_desc jz4770_groups[] = { 654 INGENIC_PIN_GROUP("uart0-data", jz4770_uart0_data, 0), 655 INGENIC_PIN_GROUP("uart0-hwflow", jz4770_uart0_hwflow, 0), 656 INGENIC_PIN_GROUP("uart1-data", jz4770_uart1_data, 0), 657 INGENIC_PIN_GROUP("uart1-hwflow", jz4770_uart1_hwflow, 0), 658 INGENIC_PIN_GROUP("uart2-data", jz4770_uart2_data, 0), 659 INGENIC_PIN_GROUP("uart2-hwflow", jz4770_uart2_hwflow, 0), 660 INGENIC_PIN_GROUP_FUNCS("uart3-data", jz4770_uart3_data, 661 jz4760_uart3_data_funcs), 662 INGENIC_PIN_GROUP("uart3-hwflow", jz4770_uart3_hwflow, 0), 663 INGENIC_PIN_GROUP("ssi0-dt-a", jz4770_ssi0_dt_a, 2), 664 INGENIC_PIN_GROUP("ssi0-dt-b", jz4770_ssi0_dt_b, 1), 665 INGENIC_PIN_GROUP("ssi0-dt-d", jz4770_ssi0_dt_d, 1), 666 INGENIC_PIN_GROUP("ssi0-dt-e", jz4770_ssi0_dt_e, 0), 667 INGENIC_PIN_GROUP("ssi0-dr-a", jz4770_ssi0_dr_a, 1), 668 INGENIC_PIN_GROUP("ssi0-dr-b", jz4770_ssi0_dr_b, 1), 669 INGENIC_PIN_GROUP("ssi0-dr-d", jz4770_ssi0_dr_d, 1), 670 INGENIC_PIN_GROUP("ssi0-dr-e", jz4770_ssi0_dr_e, 0), 671 INGENIC_PIN_GROUP("ssi0-clk-a", jz4770_ssi0_clk_a, 2), 672 INGENIC_PIN_GROUP("ssi0-clk-b", jz4770_ssi0_clk_b, 1), 673 INGENIC_PIN_GROUP("ssi0-clk-d", jz4770_ssi0_clk_d, 1), 674 INGENIC_PIN_GROUP("ssi0-clk-e", jz4770_ssi0_clk_e, 0), 675 INGENIC_PIN_GROUP("ssi0-gpc-b", jz4770_ssi0_gpc_b, 1), 676 INGENIC_PIN_GROUP("ssi0-gpc-d", jz4770_ssi0_gpc_d, 1), 677 INGENIC_PIN_GROUP("ssi0-gpc-e", jz4770_ssi0_gpc_e, 0), 678 INGENIC_PIN_GROUP("ssi0-ce0-a", jz4770_ssi0_ce0_a, 2), 679 INGENIC_PIN_GROUP("ssi0-ce0-b", jz4770_ssi0_ce0_b, 1), 680 INGENIC_PIN_GROUP("ssi0-ce0-d", jz4770_ssi0_ce0_d, 1), 681 INGENIC_PIN_GROUP("ssi0-ce0-e", jz4770_ssi0_ce0_e, 0), 682 INGENIC_PIN_GROUP("ssi0-ce1-b", jz4770_ssi0_ce1_b, 1), 683 INGENIC_PIN_GROUP("ssi0-ce1-d", jz4770_ssi0_ce1_d, 1), 684 INGENIC_PIN_GROUP("ssi0-ce1-e", jz4770_ssi0_ce1_e, 0), 685 INGENIC_PIN_GROUP("ssi1-dt-b", jz4770_ssi1_dt_b, 2), 686 INGENIC_PIN_GROUP("ssi1-dt-d", jz4770_ssi1_dt_d, 2), 687 INGENIC_PIN_GROUP("ssi1-dt-e", jz4770_ssi1_dt_e, 1), 688 INGENIC_PIN_GROUP("ssi1-dr-b", jz4770_ssi1_dr_b, 2), 689 INGENIC_PIN_GROUP("ssi1-dr-d", jz4770_ssi1_dr_d, 2), 690 INGENIC_PIN_GROUP("ssi1-dr-e", jz4770_ssi1_dr_e, 1), 691 INGENIC_PIN_GROUP("ssi1-clk-b", jz4770_ssi1_clk_b, 2), 692 INGENIC_PIN_GROUP("ssi1-clk-d", jz4770_ssi1_clk_d, 2), 693 INGENIC_PIN_GROUP("ssi1-clk-e", jz4770_ssi1_clk_e, 1), 694 INGENIC_PIN_GROUP("ssi1-gpc-b", jz4770_ssi1_gpc_b, 2), 695 INGENIC_PIN_GROUP("ssi1-gpc-d", jz4770_ssi1_gpc_d, 2), 696 INGENIC_PIN_GROUP("ssi1-gpc-e", jz4770_ssi1_gpc_e, 1), 697 INGENIC_PIN_GROUP("ssi1-ce0-b", jz4770_ssi1_ce0_b, 2), 698 INGENIC_PIN_GROUP("ssi1-ce0-d", jz4770_ssi1_ce0_d, 2), 699 INGENIC_PIN_GROUP("ssi1-ce0-e", jz4770_ssi1_ce0_e, 1), 700 INGENIC_PIN_GROUP("ssi1-ce1-b", jz4770_ssi1_ce1_b, 2), 701 INGENIC_PIN_GROUP("ssi1-ce1-d", jz4770_ssi1_ce1_d, 2), 702 INGENIC_PIN_GROUP("ssi1-ce1-e", jz4770_ssi1_ce1_e, 1), 703 INGENIC_PIN_GROUP_FUNCS("mmc0-1bit-a", jz4770_mmc0_1bit_a, 704 jz4760_mmc0_1bit_a_funcs), 705 INGENIC_PIN_GROUP("mmc0-4bit-a", jz4770_mmc0_4bit_a, 1), 706 INGENIC_PIN_GROUP("mmc0-1bit-e", jz4770_mmc0_1bit_e, 0), 707 INGENIC_PIN_GROUP("mmc0-4bit-e", jz4770_mmc0_4bit_e, 0), 708 INGENIC_PIN_GROUP("mmc0-8bit-e", jz4770_mmc0_8bit_e, 0), 709 INGENIC_PIN_GROUP("mmc1-1bit-d", jz4770_mmc1_1bit_d, 0), 710 INGENIC_PIN_GROUP("mmc1-4bit-d", jz4770_mmc1_4bit_d, 0), 711 INGENIC_PIN_GROUP("mmc1-1bit-e", jz4770_mmc1_1bit_e, 1), 712 INGENIC_PIN_GROUP("mmc1-4bit-e", jz4770_mmc1_4bit_e, 1), 713 INGENIC_PIN_GROUP("mmc1-8bit-e", jz4770_mmc1_8bit_e, 1), 714 INGENIC_PIN_GROUP("mmc2-1bit-b", jz4770_mmc2_1bit_b, 0), 715 INGENIC_PIN_GROUP("mmc2-4bit-b", jz4770_mmc2_4bit_b, 0), 716 INGENIC_PIN_GROUP("mmc2-1bit-e", jz4770_mmc2_1bit_e, 2), 717 INGENIC_PIN_GROUP("mmc2-4bit-e", jz4770_mmc2_4bit_e, 2), 718 INGENIC_PIN_GROUP("mmc2-8bit-e", jz4770_mmc2_8bit_e, 2), 719 INGENIC_PIN_GROUP("nemc-8bit-data", jz4770_nemc_8bit_data, 0), 720 INGENIC_PIN_GROUP("nemc-16bit-data", jz4770_nemc_16bit_data, 0), 721 INGENIC_PIN_GROUP("nemc-cle-ale", jz4770_nemc_cle_ale, 0), 722 INGENIC_PIN_GROUP("nemc-addr", jz4770_nemc_addr, 0), 723 INGENIC_PIN_GROUP("nemc-rd-we", jz4770_nemc_rd_we, 0), 724 INGENIC_PIN_GROUP("nemc-frd-fwe", jz4770_nemc_frd_fwe, 0), 725 INGENIC_PIN_GROUP("nemc-wait", jz4770_nemc_wait, 0), 726 INGENIC_PIN_GROUP("nemc-cs1", jz4770_nemc_cs1, 0), 727 INGENIC_PIN_GROUP("nemc-cs2", jz4770_nemc_cs2, 0), 728 INGENIC_PIN_GROUP("nemc-cs3", jz4770_nemc_cs3, 0), 729 INGENIC_PIN_GROUP("nemc-cs4", jz4770_nemc_cs4, 0), 730 INGENIC_PIN_GROUP("nemc-cs5", jz4770_nemc_cs5, 0), 731 INGENIC_PIN_GROUP("nemc-cs6", jz4770_nemc_cs6, 0), 732 INGENIC_PIN_GROUP("i2c0-data", jz4770_i2c0, 0), 733 INGENIC_PIN_GROUP("i2c1-data", jz4770_i2c1, 0), 734 INGENIC_PIN_GROUP("i2c2-data", jz4770_i2c2, 2), 735 INGENIC_PIN_GROUP("cim-data-8bit", jz4770_cim_8bit, 0), 736 INGENIC_PIN_GROUP("cim-data-12bit", jz4770_cim_12bit, 0), 737 INGENIC_PIN_GROUP("lcd-8bit", jz4770_lcd_8bit, 0), 738 INGENIC_PIN_GROUP("lcd-24bit", jz4770_lcd_24bit, 0), 739 { "lcd-no-pins", }, 740 INGENIC_PIN_GROUP("pwm0", jz4770_pwm_pwm0, 0), 741 INGENIC_PIN_GROUP("pwm1", jz4770_pwm_pwm1, 0), 742 INGENIC_PIN_GROUP("pwm2", jz4770_pwm_pwm2, 0), 743 INGENIC_PIN_GROUP("pwm3", jz4770_pwm_pwm3, 0), 744 INGENIC_PIN_GROUP("pwm4", jz4770_pwm_pwm4, 0), 745 INGENIC_PIN_GROUP("pwm5", jz4770_pwm_pwm5, 0), 746 INGENIC_PIN_GROUP("pwm6", jz4770_pwm_pwm6, 0), 747 INGENIC_PIN_GROUP("pwm7", jz4770_pwm_pwm7, 0), 748 INGENIC_PIN_GROUP("mac-rmii", jz4770_mac_rmii, 0), 749 INGENIC_PIN_GROUP("mac-mii", jz4770_mac_mii, 0), 750 INGENIC_PIN_GROUP("otg-vbus", jz4770_otg, 0), 751 }; 752 753 static const char *jz4770_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; 754 static const char *jz4770_uart1_groups[] = { "uart1-data", "uart1-hwflow", }; 755 static const char *jz4770_uart2_groups[] = { "uart2-data", "uart2-hwflow", }; 756 static const char *jz4770_uart3_groups[] = { "uart3-data", "uart3-hwflow", }; 757 static const char *jz4770_ssi0_groups[] = { 758 "ssi0-dt-a", "ssi0-dt-b", "ssi0-dt-d", "ssi0-dt-e", 759 "ssi0-dr-a", "ssi0-dr-b", "ssi0-dr-d", "ssi0-dr-e", 760 "ssi0-clk-a", "ssi0-clk-b", "ssi0-clk-d", "ssi0-clk-e", 761 "ssi0-gpc-b", "ssi0-gpc-d", "ssi0-gpc-e", 762 "ssi0-ce0-a", "ssi0-ce0-b", "ssi0-ce0-d", "ssi0-ce0-e", 763 "ssi0-ce1-b", "ssi0-ce1-d", "ssi0-ce1-e", 764 }; 765 static const char *jz4770_ssi1_groups[] = { 766 "ssi1-dt-b", "ssi1-dt-d", "ssi1-dt-e", 767 "ssi1-dr-b", "ssi1-dr-d", "ssi1-dr-e", 768 "ssi1-clk-b", "ssi1-clk-d", "ssi1-clk-e", 769 "ssi1-gpc-b", "ssi1-gpc-d", "ssi1-gpc-e", 770 "ssi1-ce0-b", "ssi1-ce0-d", "ssi1-ce0-e", 771 "ssi1-ce1-b", "ssi1-ce1-d", "ssi1-ce1-e", 772 }; 773 static const char *jz4770_mmc0_groups[] = { 774 "mmc0-1bit-a", "mmc0-4bit-a", 775 "mmc0-1bit-e", "mmc0-4bit-e", "mmc0-8bit-e", 776 }; 777 static const char *jz4770_mmc1_groups[] = { 778 "mmc1-1bit-d", "mmc1-4bit-d", 779 "mmc1-1bit-e", "mmc1-4bit-e", "mmc1-8bit-e", 780 }; 781 static const char *jz4770_mmc2_groups[] = { 782 "mmc2-1bit-b", "mmc2-4bit-b", 783 "mmc2-1bit-e", "mmc2-4bit-e", "mmc2-8bit-e", 784 }; 785 static const char *jz4770_nemc_groups[] = { 786 "nemc-8bit-data", "nemc-16bit-data", "nemc-cle-ale", 787 "nemc-addr", "nemc-rd-we", "nemc-frd-fwe", "nemc-wait", 788 }; 789 static const char *jz4770_cs1_groups[] = { "nemc-cs1", }; 790 static const char *jz4770_cs2_groups[] = { "nemc-cs2", }; 791 static const char *jz4770_cs3_groups[] = { "nemc-cs3", }; 792 static const char *jz4770_cs4_groups[] = { "nemc-cs4", }; 793 static const char *jz4770_cs5_groups[] = { "nemc-cs5", }; 794 static const char *jz4770_cs6_groups[] = { "nemc-cs6", }; 795 static const char *jz4770_i2c0_groups[] = { "i2c0-data", }; 796 static const char *jz4770_i2c1_groups[] = { "i2c1-data", }; 797 static const char *jz4770_i2c2_groups[] = { "i2c2-data", }; 798 static const char *jz4770_cim_groups[] = { "cim-data-8bit", "cim-data-12bit", }; 799 static const char *jz4770_lcd_groups[] = { 800 "lcd-8bit", "lcd-24bit", "lcd-no-pins", 801 }; 802 static const char *jz4770_pwm0_groups[] = { "pwm0", }; 803 static const char *jz4770_pwm1_groups[] = { "pwm1", }; 804 static const char *jz4770_pwm2_groups[] = { "pwm2", }; 805 static const char *jz4770_pwm3_groups[] = { "pwm3", }; 806 static const char *jz4770_pwm4_groups[] = { "pwm4", }; 807 static const char *jz4770_pwm5_groups[] = { "pwm5", }; 808 static const char *jz4770_pwm6_groups[] = { "pwm6", }; 809 static const char *jz4770_pwm7_groups[] = { "pwm7", }; 810 static const char *jz4770_mac_groups[] = { "mac-rmii", "mac-mii", }; 811 static const char *jz4770_otg_groups[] = { "otg-vbus", }; 812 813 static const struct function_desc jz4770_functions[] = { 814 { "uart0", jz4770_uart0_groups, ARRAY_SIZE(jz4770_uart0_groups), }, 815 { "uart1", jz4770_uart1_groups, ARRAY_SIZE(jz4770_uart1_groups), }, 816 { "uart2", jz4770_uart2_groups, ARRAY_SIZE(jz4770_uart2_groups), }, 817 { "uart3", jz4770_uart3_groups, ARRAY_SIZE(jz4770_uart3_groups), }, 818 { "ssi0", jz4770_ssi0_groups, ARRAY_SIZE(jz4770_ssi0_groups), }, 819 { "ssi1", jz4770_ssi1_groups, ARRAY_SIZE(jz4770_ssi1_groups), }, 820 { "mmc0", jz4770_mmc0_groups, ARRAY_SIZE(jz4770_mmc0_groups), }, 821 { "mmc1", jz4770_mmc1_groups, ARRAY_SIZE(jz4770_mmc1_groups), }, 822 { "mmc2", jz4770_mmc2_groups, ARRAY_SIZE(jz4770_mmc2_groups), }, 823 { "nemc", jz4770_nemc_groups, ARRAY_SIZE(jz4770_nemc_groups), }, 824 { "nemc-cs1", jz4770_cs1_groups, ARRAY_SIZE(jz4770_cs1_groups), }, 825 { "nemc-cs2", jz4770_cs2_groups, ARRAY_SIZE(jz4770_cs2_groups), }, 826 { "nemc-cs3", jz4770_cs3_groups, ARRAY_SIZE(jz4770_cs3_groups), }, 827 { "nemc-cs4", jz4770_cs4_groups, ARRAY_SIZE(jz4770_cs4_groups), }, 828 { "nemc-cs5", jz4770_cs5_groups, ARRAY_SIZE(jz4770_cs5_groups), }, 829 { "nemc-cs6", jz4770_cs6_groups, ARRAY_SIZE(jz4770_cs6_groups), }, 830 { "i2c0", jz4770_i2c0_groups, ARRAY_SIZE(jz4770_i2c0_groups), }, 831 { "i2c1", jz4770_i2c1_groups, ARRAY_SIZE(jz4770_i2c1_groups), }, 832 { "i2c2", jz4770_i2c2_groups, ARRAY_SIZE(jz4770_i2c2_groups), }, 833 { "cim", jz4770_cim_groups, ARRAY_SIZE(jz4770_cim_groups), }, 834 { "lcd", jz4770_lcd_groups, ARRAY_SIZE(jz4770_lcd_groups), }, 835 { "pwm0", jz4770_pwm0_groups, ARRAY_SIZE(jz4770_pwm0_groups), }, 836 { "pwm1", jz4770_pwm1_groups, ARRAY_SIZE(jz4770_pwm1_groups), }, 837 { "pwm2", jz4770_pwm2_groups, ARRAY_SIZE(jz4770_pwm2_groups), }, 838 { "pwm3", jz4770_pwm3_groups, ARRAY_SIZE(jz4770_pwm3_groups), }, 839 { "pwm4", jz4770_pwm4_groups, ARRAY_SIZE(jz4770_pwm4_groups), }, 840 { "pwm5", jz4770_pwm5_groups, ARRAY_SIZE(jz4770_pwm5_groups), }, 841 { "pwm6", jz4770_pwm6_groups, ARRAY_SIZE(jz4770_pwm6_groups), }, 842 { "pwm7", jz4770_pwm7_groups, ARRAY_SIZE(jz4770_pwm7_groups), }, 843 { "mac", jz4770_mac_groups, ARRAY_SIZE(jz4770_mac_groups), }, 844 { "otg", jz4770_otg_groups, ARRAY_SIZE(jz4770_otg_groups), }, 845 }; 846 847 static const struct ingenic_chip_info jz4770_chip_info = { 848 .num_chips = 6, 849 .reg_offset = 0x100, 850 .version = ID_JZ4770, 851 .groups = jz4770_groups, 852 .num_groups = ARRAY_SIZE(jz4770_groups), 853 .functions = jz4770_functions, 854 .num_functions = ARRAY_SIZE(jz4770_functions), 855 .pull_ups = jz4770_pull_ups, 856 .pull_downs = jz4770_pull_downs, 857 }; 858 859 static const u32 jz4780_pull_ups[6] = { 860 0x3fffffff, 0xfff0f3fc, 0x0fffffff, 0xffff4fff, 0xfffffb7c, 0x7fa7f00f, 861 }; 862 863 static const u32 jz4780_pull_downs[6] = { 864 0x00000000, 0x000f0c03, 0x00000000, 0x0000b000, 0x00000483, 0x00580ff0, 865 }; 866 867 static int jz4780_uart2_data_pins[] = { 0x66, 0x67, }; 868 static int jz4780_uart2_hwflow_pins[] = { 0x65, 0x64, }; 869 static int jz4780_uart4_data_pins[] = { 0x54, 0x4a, }; 870 static int jz4780_ssi0_dt_a_19_pins[] = { 0x13, }; 871 static int jz4780_ssi0_dt_a_21_pins[] = { 0x15, }; 872 static int jz4780_ssi0_dt_a_28_pins[] = { 0x1c, }; 873 static int jz4780_ssi0_dt_b_pins[] = { 0x3d, }; 874 static int jz4780_ssi0_dt_d_pins[] = { 0x79, }; 875 static int jz4780_ssi0_dr_a_20_pins[] = { 0x14, }; 876 static int jz4780_ssi0_dr_a_27_pins[] = { 0x1b, }; 877 static int jz4780_ssi0_dr_b_pins[] = { 0x34, }; 878 static int jz4780_ssi0_dr_d_pins[] = { 0x74, }; 879 static int jz4780_ssi0_clk_a_pins[] = { 0x12, }; 880 static int jz4780_ssi0_clk_b_5_pins[] = { 0x25, }; 881 static int jz4780_ssi0_clk_b_28_pins[] = { 0x3c, }; 882 static int jz4780_ssi0_clk_d_pins[] = { 0x78, }; 883 static int jz4780_ssi0_gpc_b_pins[] = { 0x3e, }; 884 static int jz4780_ssi0_gpc_d_pins[] = { 0x76, }; 885 static int jz4780_ssi0_ce0_a_23_pins[] = { 0x17, }; 886 static int jz4780_ssi0_ce0_a_25_pins[] = { 0x19, }; 887 static int jz4780_ssi0_ce0_b_pins[] = { 0x3f, }; 888 static int jz4780_ssi0_ce0_d_pins[] = { 0x77, }; 889 static int jz4780_ssi0_ce1_b_pins[] = { 0x35, }; 890 static int jz4780_ssi0_ce1_d_pins[] = { 0x75, }; 891 static int jz4780_ssi1_dt_b_pins[] = { 0x3d, }; 892 static int jz4780_ssi1_dt_d_pins[] = { 0x79, }; 893 static int jz4780_ssi1_dr_b_pins[] = { 0x34, }; 894 static int jz4780_ssi1_dr_d_pins[] = { 0x74, }; 895 static int jz4780_ssi1_clk_b_pins[] = { 0x3c, }; 896 static int jz4780_ssi1_clk_d_pins[] = { 0x78, }; 897 static int jz4780_ssi1_gpc_b_pins[] = { 0x3e, }; 898 static int jz4780_ssi1_gpc_d_pins[] = { 0x76, }; 899 static int jz4780_ssi1_ce0_b_pins[] = { 0x3f, }; 900 static int jz4780_ssi1_ce0_d_pins[] = { 0x77, }; 901 static int jz4780_ssi1_ce1_b_pins[] = { 0x35, }; 902 static int jz4780_ssi1_ce1_d_pins[] = { 0x75, }; 903 static int jz4780_mmc0_8bit_a_pins[] = { 0x04, 0x05, 0x06, 0x07, 0x18, }; 904 static int jz4780_i2c3_pins[] = { 0x6a, 0x6b, }; 905 static int jz4780_i2c4_e_pins[] = { 0x8c, 0x8d, }; 906 static int jz4780_i2c4_f_pins[] = { 0xb9, 0xb8, }; 907 static int jz4780_i2s_data_tx_pins[] = { 0x87, }; 908 static int jz4780_i2s_data_rx_pins[] = { 0x86, }; 909 static int jz4780_i2s_clk_txrx_pins[] = { 0x6c, 0x6d, }; 910 static int jz4780_i2s_clk_rx_pins[] = { 0x88, 0x89, }; 911 static int jz4780_i2s_sysclk_pins[] = { 0x85, }; 912 static int jz4780_hdmi_ddc_pins[] = { 0xb9, 0xb8, }; 913 914 static u8 jz4780_i2s_clk_txrx_funcs[] = { 1, 0, }; 915 916 static const struct group_desc jz4780_groups[] = { 917 INGENIC_PIN_GROUP("uart0-data", jz4770_uart0_data, 0), 918 INGENIC_PIN_GROUP("uart0-hwflow", jz4770_uart0_hwflow, 0), 919 INGENIC_PIN_GROUP("uart1-data", jz4770_uart1_data, 0), 920 INGENIC_PIN_GROUP("uart1-hwflow", jz4770_uart1_hwflow, 0), 921 INGENIC_PIN_GROUP("uart2-data", jz4780_uart2_data, 1), 922 INGENIC_PIN_GROUP("uart2-hwflow", jz4780_uart2_hwflow, 1), 923 INGENIC_PIN_GROUP_FUNCS("uart3-data", jz4770_uart3_data, 924 jz4760_uart3_data_funcs), 925 INGENIC_PIN_GROUP("uart3-hwflow", jz4770_uart3_hwflow, 0), 926 INGENIC_PIN_GROUP("uart4-data", jz4780_uart4_data, 2), 927 INGENIC_PIN_GROUP("ssi0-dt-a-19", jz4780_ssi0_dt_a_19, 2), 928 INGENIC_PIN_GROUP("ssi0-dt-a-21", jz4780_ssi0_dt_a_21, 2), 929 INGENIC_PIN_GROUP("ssi0-dt-a-28", jz4780_ssi0_dt_a_28, 2), 930 INGENIC_PIN_GROUP("ssi0-dt-b", jz4780_ssi0_dt_b, 1), 931 INGENIC_PIN_GROUP("ssi0-dt-d", jz4780_ssi0_dt_d, 1), 932 INGENIC_PIN_GROUP("ssi0-dt-e", jz4770_ssi0_dt_e, 0), 933 INGENIC_PIN_GROUP("ssi0-dr-a-20", jz4780_ssi0_dr_a_20, 2), 934 INGENIC_PIN_GROUP("ssi0-dr-a-27", jz4780_ssi0_dr_a_27, 2), 935 INGENIC_PIN_GROUP("ssi0-dr-b", jz4780_ssi0_dr_b, 1), 936 INGENIC_PIN_GROUP("ssi0-dr-d", jz4780_ssi0_dr_d, 1), 937 INGENIC_PIN_GROUP("ssi0-dr-e", jz4770_ssi0_dr_e, 0), 938 INGENIC_PIN_GROUP("ssi0-clk-a", jz4780_ssi0_clk_a, 2), 939 INGENIC_PIN_GROUP("ssi0-clk-b-5", jz4780_ssi0_clk_b_5, 1), 940 INGENIC_PIN_GROUP("ssi0-clk-b-28", jz4780_ssi0_clk_b_28, 1), 941 INGENIC_PIN_GROUP("ssi0-clk-d", jz4780_ssi0_clk_d, 1), 942 INGENIC_PIN_GROUP("ssi0-clk-e", jz4770_ssi0_clk_e, 0), 943 INGENIC_PIN_GROUP("ssi0-gpc-b", jz4780_ssi0_gpc_b, 1), 944 INGENIC_PIN_GROUP("ssi0-gpc-d", jz4780_ssi0_gpc_d, 1), 945 INGENIC_PIN_GROUP("ssi0-gpc-e", jz4770_ssi0_gpc_e, 0), 946 INGENIC_PIN_GROUP("ssi0-ce0-a-23", jz4780_ssi0_ce0_a_23, 2), 947 INGENIC_PIN_GROUP("ssi0-ce0-a-25", jz4780_ssi0_ce0_a_25, 2), 948 INGENIC_PIN_GROUP("ssi0-ce0-b", jz4780_ssi0_ce0_b, 1), 949 INGENIC_PIN_GROUP("ssi0-ce0-d", jz4780_ssi0_ce0_d, 1), 950 INGENIC_PIN_GROUP("ssi0-ce0-e", jz4770_ssi0_ce0_e, 0), 951 INGENIC_PIN_GROUP("ssi0-ce1-b", jz4780_ssi0_ce1_b, 1), 952 INGENIC_PIN_GROUP("ssi0-ce1-d", jz4780_ssi0_ce1_d, 1), 953 INGENIC_PIN_GROUP("ssi0-ce1-e", jz4770_ssi0_ce1_e, 0), 954 INGENIC_PIN_GROUP("ssi1-dt-b", jz4780_ssi1_dt_b, 2), 955 INGENIC_PIN_GROUP("ssi1-dt-d", jz4780_ssi1_dt_d, 2), 956 INGENIC_PIN_GROUP("ssi1-dt-e", jz4770_ssi1_dt_e, 1), 957 INGENIC_PIN_GROUP("ssi1-dr-b", jz4780_ssi1_dr_b, 2), 958 INGENIC_PIN_GROUP("ssi1-dr-d", jz4780_ssi1_dr_d, 2), 959 INGENIC_PIN_GROUP("ssi1-dr-e", jz4770_ssi1_dr_e, 1), 960 INGENIC_PIN_GROUP("ssi1-clk-b", jz4780_ssi1_clk_b, 2), 961 INGENIC_PIN_GROUP("ssi1-clk-d", jz4780_ssi1_clk_d, 2), 962 INGENIC_PIN_GROUP("ssi1-clk-e", jz4770_ssi1_clk_e, 1), 963 INGENIC_PIN_GROUP("ssi1-gpc-b", jz4780_ssi1_gpc_b, 2), 964 INGENIC_PIN_GROUP("ssi1-gpc-d", jz4780_ssi1_gpc_d, 2), 965 INGENIC_PIN_GROUP("ssi1-gpc-e", jz4770_ssi1_gpc_e, 1), 966 INGENIC_PIN_GROUP("ssi1-ce0-b", jz4780_ssi1_ce0_b, 2), 967 INGENIC_PIN_GROUP("ssi1-ce0-d", jz4780_ssi1_ce0_d, 2), 968 INGENIC_PIN_GROUP("ssi1-ce0-e", jz4770_ssi1_ce0_e, 1), 969 INGENIC_PIN_GROUP("ssi1-ce1-b", jz4780_ssi1_ce1_b, 2), 970 INGENIC_PIN_GROUP("ssi1-ce1-d", jz4780_ssi1_ce1_d, 2), 971 INGENIC_PIN_GROUP("ssi1-ce1-e", jz4770_ssi1_ce1_e, 1), 972 INGENIC_PIN_GROUP_FUNCS("mmc0-1bit-a", jz4770_mmc0_1bit_a, 973 jz4760_mmc0_1bit_a_funcs), 974 INGENIC_PIN_GROUP("mmc0-4bit-a", jz4770_mmc0_4bit_a, 1), 975 INGENIC_PIN_GROUP("mmc0-8bit-a", jz4780_mmc0_8bit_a, 1), 976 INGENIC_PIN_GROUP("mmc0-1bit-e", jz4770_mmc0_1bit_e, 0), 977 INGENIC_PIN_GROUP("mmc0-4bit-e", jz4770_mmc0_4bit_e, 0), 978 INGENIC_PIN_GROUP("mmc1-1bit-d", jz4770_mmc1_1bit_d, 0), 979 INGENIC_PIN_GROUP("mmc1-4bit-d", jz4770_mmc1_4bit_d, 0), 980 INGENIC_PIN_GROUP("mmc1-1bit-e", jz4770_mmc1_1bit_e, 1), 981 INGENIC_PIN_GROUP("mmc1-4bit-e", jz4770_mmc1_4bit_e, 1), 982 INGENIC_PIN_GROUP("mmc2-1bit-b", jz4770_mmc2_1bit_b, 0), 983 INGENIC_PIN_GROUP("mmc2-4bit-b", jz4770_mmc2_4bit_b, 0), 984 INGENIC_PIN_GROUP("mmc2-1bit-e", jz4770_mmc2_1bit_e, 2), 985 INGENIC_PIN_GROUP("mmc2-4bit-e", jz4770_mmc2_4bit_e, 2), 986 INGENIC_PIN_GROUP("nemc-data", jz4770_nemc_8bit_data, 0), 987 INGENIC_PIN_GROUP("nemc-cle-ale", jz4770_nemc_cle_ale, 0), 988 INGENIC_PIN_GROUP("nemc-addr", jz4770_nemc_addr, 0), 989 INGENIC_PIN_GROUP("nemc-rd-we", jz4770_nemc_rd_we, 0), 990 INGENIC_PIN_GROUP("nemc-frd-fwe", jz4770_nemc_frd_fwe, 0), 991 INGENIC_PIN_GROUP("nemc-wait", jz4770_nemc_wait, 0), 992 INGENIC_PIN_GROUP("nemc-cs1", jz4770_nemc_cs1, 0), 993 INGENIC_PIN_GROUP("nemc-cs2", jz4770_nemc_cs2, 0), 994 INGENIC_PIN_GROUP("nemc-cs3", jz4770_nemc_cs3, 0), 995 INGENIC_PIN_GROUP("nemc-cs4", jz4770_nemc_cs4, 0), 996 INGENIC_PIN_GROUP("nemc-cs5", jz4770_nemc_cs5, 0), 997 INGENIC_PIN_GROUP("nemc-cs6", jz4770_nemc_cs6, 0), 998 INGENIC_PIN_GROUP("i2c0-data", jz4770_i2c0, 0), 999 INGENIC_PIN_GROUP("i2c1-data", jz4770_i2c1, 0), 1000 INGENIC_PIN_GROUP("i2c2-data", jz4770_i2c2, 2), 1001 INGENIC_PIN_GROUP("i2c3-data", jz4780_i2c3, 1), 1002 INGENIC_PIN_GROUP("i2c4-data-e", jz4780_i2c4_e, 1), 1003 INGENIC_PIN_GROUP("i2c4-data-f", jz4780_i2c4_f, 1), 1004 INGENIC_PIN_GROUP("i2s-data-tx", jz4780_i2s_data_tx, 0), 1005 INGENIC_PIN_GROUP("i2s-data-rx", jz4780_i2s_data_rx, 0), 1006 INGENIC_PIN_GROUP_FUNCS("i2s-clk-txrx", jz4780_i2s_clk_txrx, 1007 jz4780_i2s_clk_txrx_funcs), 1008 INGENIC_PIN_GROUP("i2s-clk-rx", jz4780_i2s_clk_rx, 1), 1009 INGENIC_PIN_GROUP("i2s-sysclk", jz4780_i2s_sysclk, 2), 1010 INGENIC_PIN_GROUP("hdmi-ddc", jz4780_hdmi_ddc, 0), 1011 INGENIC_PIN_GROUP("cim-data", jz4770_cim_8bit, 0), 1012 INGENIC_PIN_GROUP("cim-data-12bit", jz4770_cim_12bit, 0), 1013 INGENIC_PIN_GROUP("lcd-24bit", jz4770_lcd_24bit, 0), 1014 { "lcd-no-pins", }, 1015 INGENIC_PIN_GROUP("pwm0", jz4770_pwm_pwm0, 0), 1016 INGENIC_PIN_GROUP("pwm1", jz4770_pwm_pwm1, 0), 1017 INGENIC_PIN_GROUP("pwm2", jz4770_pwm_pwm2, 0), 1018 INGENIC_PIN_GROUP("pwm3", jz4770_pwm_pwm3, 0), 1019 INGENIC_PIN_GROUP("pwm4", jz4770_pwm_pwm4, 0), 1020 INGENIC_PIN_GROUP("pwm5", jz4770_pwm_pwm5, 0), 1021 INGENIC_PIN_GROUP("pwm6", jz4770_pwm_pwm6, 0), 1022 INGENIC_PIN_GROUP("pwm7", jz4770_pwm_pwm7, 0), 1023 }; 1024 1025 static const char *jz4780_uart2_groups[] = { "uart2-data", "uart2-hwflow", }; 1026 static const char *jz4780_uart4_groups[] = { "uart4-data", }; 1027 static const char *jz4780_ssi0_groups[] = { 1028 "ssi0-dt-a-19", "ssi0-dt-a-21", "ssi0-dt-a-28", "ssi0-dt-b", "ssi0-dt-d", "ssi0-dt-e", 1029 "ssi0-dr-a-20", "ssi0-dr-a-27", "ssi0-dr-b", "ssi0-dr-d", "ssi0-dr-e", 1030 "ssi0-clk-a", "ssi0-clk-b-5", "ssi0-clk-b-28", "ssi0-clk-d", "ssi0-clk-e", 1031 "ssi0-gpc-b", "ssi0-gpc-d", "ssi0-gpc-e", 1032 "ssi0-ce0-a-23", "ssi0-ce0-a-25", "ssi0-ce0-b", "ssi0-ce0-d", "ssi0-ce0-e", 1033 "ssi0-ce1-b", "ssi0-ce1-d", "ssi0-ce1-e", 1034 }; 1035 static const char *jz4780_ssi1_groups[] = { 1036 "ssi1-dt-b", "ssi1-dt-d", "ssi1-dt-e", 1037 "ssi1-dr-b", "ssi1-dr-d", "ssi1-dr-e", 1038 "ssi1-clk-b", "ssi1-clk-d", "ssi1-clk-e", 1039 "ssi1-gpc-b", "ssi1-gpc-d", "ssi1-gpc-e", 1040 "ssi1-ce0-b", "ssi1-ce0-d", "ssi1-ce0-e", 1041 "ssi1-ce1-b", "ssi1-ce1-d", "ssi1-ce1-e", 1042 }; 1043 static const char *jz4780_mmc0_groups[] = { 1044 "mmc0-1bit-a", "mmc0-4bit-a", "mmc0-8bit-a", 1045 "mmc0-1bit-e", "mmc0-4bit-e", 1046 }; 1047 static const char *jz4780_mmc1_groups[] = { 1048 "mmc1-1bit-d", "mmc1-4bit-d", "mmc1-1bit-e", "mmc1-4bit-e", 1049 }; 1050 static const char *jz4780_mmc2_groups[] = { 1051 "mmc2-1bit-b", "mmc2-4bit-b", "mmc2-1bit-e", "mmc2-4bit-e", 1052 }; 1053 static const char *jz4780_nemc_groups[] = { 1054 "nemc-data", "nemc-cle-ale", "nemc-addr", 1055 "nemc-rd-we", "nemc-frd-fwe", "nemc-wait", 1056 }; 1057 static const char *jz4780_i2c3_groups[] = { "i2c3-data", }; 1058 static const char *jz4780_i2c4_groups[] = { "i2c4-data-e", "i2c4-data-f", }; 1059 static const char *jz4780_i2s_groups[] = { 1060 "i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-clk-rx", "i2s-sysclk", 1061 }; 1062 static const char *jz4780_cim_groups[] = { "cim-data", }; 1063 static const char *jz4780_hdmi_ddc_groups[] = { "hdmi-ddc", }; 1064 1065 static const struct function_desc jz4780_functions[] = { 1066 { "uart0", jz4770_uart0_groups, ARRAY_SIZE(jz4770_uart0_groups), }, 1067 { "uart1", jz4770_uart1_groups, ARRAY_SIZE(jz4770_uart1_groups), }, 1068 { "uart2", jz4780_uart2_groups, ARRAY_SIZE(jz4780_uart2_groups), }, 1069 { "uart3", jz4770_uart3_groups, ARRAY_SIZE(jz4770_uart3_groups), }, 1070 { "uart4", jz4780_uart4_groups, ARRAY_SIZE(jz4780_uart4_groups), }, 1071 { "ssi0", jz4780_ssi0_groups, ARRAY_SIZE(jz4780_ssi0_groups), }, 1072 { "ssi1", jz4780_ssi1_groups, ARRAY_SIZE(jz4780_ssi1_groups), }, 1073 { "mmc0", jz4780_mmc0_groups, ARRAY_SIZE(jz4780_mmc0_groups), }, 1074 { "mmc1", jz4780_mmc1_groups, ARRAY_SIZE(jz4780_mmc1_groups), }, 1075 { "mmc2", jz4780_mmc2_groups, ARRAY_SIZE(jz4780_mmc2_groups), }, 1076 { "nemc", jz4780_nemc_groups, ARRAY_SIZE(jz4780_nemc_groups), }, 1077 { "nemc-cs1", jz4770_cs1_groups, ARRAY_SIZE(jz4770_cs1_groups), }, 1078 { "nemc-cs2", jz4770_cs2_groups, ARRAY_SIZE(jz4770_cs2_groups), }, 1079 { "nemc-cs3", jz4770_cs3_groups, ARRAY_SIZE(jz4770_cs3_groups), }, 1080 { "nemc-cs4", jz4770_cs4_groups, ARRAY_SIZE(jz4770_cs4_groups), }, 1081 { "nemc-cs5", jz4770_cs5_groups, ARRAY_SIZE(jz4770_cs5_groups), }, 1082 { "nemc-cs6", jz4770_cs6_groups, ARRAY_SIZE(jz4770_cs6_groups), }, 1083 { "i2c0", jz4770_i2c0_groups, ARRAY_SIZE(jz4770_i2c0_groups), }, 1084 { "i2c1", jz4770_i2c1_groups, ARRAY_SIZE(jz4770_i2c1_groups), }, 1085 { "i2c2", jz4770_i2c2_groups, ARRAY_SIZE(jz4770_i2c2_groups), }, 1086 { "i2c3", jz4780_i2c3_groups, ARRAY_SIZE(jz4780_i2c3_groups), }, 1087 { "i2c4", jz4780_i2c4_groups, ARRAY_SIZE(jz4780_i2c4_groups), }, 1088 { "i2s", jz4780_i2s_groups, ARRAY_SIZE(jz4780_i2s_groups), }, 1089 { "cim", jz4780_cim_groups, ARRAY_SIZE(jz4780_cim_groups), }, 1090 { "lcd", jz4770_lcd_groups, ARRAY_SIZE(jz4770_lcd_groups), }, 1091 { "pwm0", jz4770_pwm0_groups, ARRAY_SIZE(jz4770_pwm0_groups), }, 1092 { "pwm1", jz4770_pwm1_groups, ARRAY_SIZE(jz4770_pwm1_groups), }, 1093 { "pwm2", jz4770_pwm2_groups, ARRAY_SIZE(jz4770_pwm2_groups), }, 1094 { "pwm3", jz4770_pwm3_groups, ARRAY_SIZE(jz4770_pwm3_groups), }, 1095 { "pwm4", jz4770_pwm4_groups, ARRAY_SIZE(jz4770_pwm4_groups), }, 1096 { "pwm5", jz4770_pwm5_groups, ARRAY_SIZE(jz4770_pwm5_groups), }, 1097 { "pwm6", jz4770_pwm6_groups, ARRAY_SIZE(jz4770_pwm6_groups), }, 1098 { "pwm7", jz4770_pwm7_groups, ARRAY_SIZE(jz4770_pwm7_groups), }, 1099 { "hdmi-ddc", jz4780_hdmi_ddc_groups, 1100 ARRAY_SIZE(jz4780_hdmi_ddc_groups), }, 1101 }; 1102 1103 static const struct ingenic_chip_info jz4780_chip_info = { 1104 .num_chips = 6, 1105 .reg_offset = 0x100, 1106 .version = ID_JZ4780, 1107 .groups = jz4780_groups, 1108 .num_groups = ARRAY_SIZE(jz4780_groups), 1109 .functions = jz4780_functions, 1110 .num_functions = ARRAY_SIZE(jz4780_functions), 1111 .pull_ups = jz4780_pull_ups, 1112 .pull_downs = jz4780_pull_downs, 1113 }; 1114 1115 static const u32 x1000_pull_ups[4] = { 1116 0xffffffff, 0xfdffffff, 0x0dffffff, 0x0000003f, 1117 }; 1118 1119 static const u32 x1000_pull_downs[4] = { 1120 0x00000000, 0x02000000, 0x02000000, 0x00000000, 1121 }; 1122 1123 static int x1000_uart0_data_pins[] = { 0x4a, 0x4b, }; 1124 static int x1000_uart0_hwflow_pins[] = { 0x4c, 0x4d, }; 1125 static int x1000_uart1_data_a_pins[] = { 0x04, 0x05, }; 1126 static int x1000_uart1_data_d_pins[] = { 0x62, 0x63, }; 1127 static int x1000_uart1_hwflow_pins[] = { 0x64, 0x65, }; 1128 static int x1000_uart2_data_a_pins[] = { 0x02, 0x03, }; 1129 static int x1000_uart2_data_d_pins[] = { 0x65, 0x64, }; 1130 static int x1000_sfc_pins[] = { 0x1d, 0x1c, 0x1e, 0x1f, 0x1a, 0x1b, }; 1131 static int x1000_ssi_dt_a_22_pins[] = { 0x16, }; 1132 static int x1000_ssi_dt_a_29_pins[] = { 0x1d, }; 1133 static int x1000_ssi_dt_d_pins[] = { 0x62, }; 1134 static int x1000_ssi_dr_a_23_pins[] = { 0x17, }; 1135 static int x1000_ssi_dr_a_28_pins[] = { 0x1c, }; 1136 static int x1000_ssi_dr_d_pins[] = { 0x63, }; 1137 static int x1000_ssi_clk_a_24_pins[] = { 0x18, }; 1138 static int x1000_ssi_clk_a_26_pins[] = { 0x1a, }; 1139 static int x1000_ssi_clk_d_pins[] = { 0x60, }; 1140 static int x1000_ssi_gpc_a_20_pins[] = { 0x14, }; 1141 static int x1000_ssi_gpc_a_31_pins[] = { 0x1f, }; 1142 static int x1000_ssi_ce0_a_25_pins[] = { 0x19, }; 1143 static int x1000_ssi_ce0_a_27_pins[] = { 0x1b, }; 1144 static int x1000_ssi_ce0_d_pins[] = { 0x61, }; 1145 static int x1000_ssi_ce1_a_21_pins[] = { 0x15, }; 1146 static int x1000_ssi_ce1_a_30_pins[] = { 0x1e, }; 1147 static int x1000_mmc0_1bit_pins[] = { 0x18, 0x19, 0x17, }; 1148 static int x1000_mmc0_4bit_pins[] = { 0x16, 0x15, 0x14, }; 1149 static int x1000_mmc0_8bit_pins[] = { 0x13, 0x12, 0x11, 0x10, }; 1150 static int x1000_mmc1_1bit_pins[] = { 0x40, 0x41, 0x42, }; 1151 static int x1000_mmc1_4bit_pins[] = { 0x43, 0x44, 0x45, }; 1152 static int x1000_emc_8bit_data_pins[] = { 1153 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 1154 }; 1155 static int x1000_emc_16bit_data_pins[] = { 1156 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 1157 }; 1158 static int x1000_emc_addr_pins[] = { 1159 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 1160 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 1161 }; 1162 static int x1000_emc_rd_we_pins[] = { 0x30, 0x31, }; 1163 static int x1000_emc_wait_pins[] = { 0x34, }; 1164 static int x1000_emc_cs1_pins[] = { 0x32, }; 1165 static int x1000_emc_cs2_pins[] = { 0x33, }; 1166 static int x1000_i2c0_pins[] = { 0x38, 0x37, }; 1167 static int x1000_i2c1_a_pins[] = { 0x01, 0x00, }; 1168 static int x1000_i2c1_c_pins[] = { 0x5b, 0x5a, }; 1169 static int x1000_i2c2_pins[] = { 0x61, 0x60, }; 1170 static int x1000_i2s_data_tx_pins[] = { 0x24, }; 1171 static int x1000_i2s_data_rx_pins[] = { 0x23, }; 1172 static int x1000_i2s_clk_txrx_pins[] = { 0x21, 0x22, }; 1173 static int x1000_i2s_sysclk_pins[] = { 0x20, }; 1174 static int x1000_cim_pins[] = { 1175 0x08, 0x09, 0x0a, 0x0b, 1176 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 0x0d, 0x0c, 1177 }; 1178 static int x1000_lcd_8bit_pins[] = { 1179 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 1180 0x30, 0x31, 0x32, 0x33, 0x34, 1181 }; 1182 static int x1000_lcd_16bit_pins[] = { 1183 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 1184 }; 1185 static int x1000_pwm_pwm0_pins[] = { 0x59, }; 1186 static int x1000_pwm_pwm1_pins[] = { 0x5a, }; 1187 static int x1000_pwm_pwm2_pins[] = { 0x5b, }; 1188 static int x1000_pwm_pwm3_pins[] = { 0x26, }; 1189 static int x1000_pwm_pwm4_pins[] = { 0x58, }; 1190 static int x1000_mac_pins[] = { 1191 0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x26, 1192 }; 1193 1194 static const struct group_desc x1000_groups[] = { 1195 INGENIC_PIN_GROUP("uart0-data", x1000_uart0_data, 0), 1196 INGENIC_PIN_GROUP("uart0-hwflow", x1000_uart0_hwflow, 0), 1197 INGENIC_PIN_GROUP("uart1-data-a", x1000_uart1_data_a, 2), 1198 INGENIC_PIN_GROUP("uart1-data-d", x1000_uart1_data_d, 1), 1199 INGENIC_PIN_GROUP("uart1-hwflow", x1000_uart1_hwflow, 1), 1200 INGENIC_PIN_GROUP("uart2-data-a", x1000_uart2_data_a, 2), 1201 INGENIC_PIN_GROUP("uart2-data-d", x1000_uart2_data_d, 0), 1202 INGENIC_PIN_GROUP("sfc", x1000_sfc, 1), 1203 INGENIC_PIN_GROUP("ssi-dt-a-22", x1000_ssi_dt_a_22, 2), 1204 INGENIC_PIN_GROUP("ssi-dt-a-29", x1000_ssi_dt_a_29, 2), 1205 INGENIC_PIN_GROUP("ssi-dt-d", x1000_ssi_dt_d, 0), 1206 INGENIC_PIN_GROUP("ssi-dr-a-23", x1000_ssi_dr_a_23, 2), 1207 INGENIC_PIN_GROUP("ssi-dr-a-28", x1000_ssi_dr_a_28, 2), 1208 INGENIC_PIN_GROUP("ssi-dr-d", x1000_ssi_dr_d, 0), 1209 INGENIC_PIN_GROUP("ssi-clk-a-24", x1000_ssi_clk_a_24, 2), 1210 INGENIC_PIN_GROUP("ssi-clk-a-26", x1000_ssi_clk_a_26, 2), 1211 INGENIC_PIN_GROUP("ssi-clk-d", x1000_ssi_clk_d, 0), 1212 INGENIC_PIN_GROUP("ssi-gpc-a-20", x1000_ssi_gpc_a_20, 2), 1213 INGENIC_PIN_GROUP("ssi-gpc-a-31", x1000_ssi_gpc_a_31, 2), 1214 INGENIC_PIN_GROUP("ssi-ce0-a-25", x1000_ssi_ce0_a_25, 2), 1215 INGENIC_PIN_GROUP("ssi-ce0-a-27", x1000_ssi_ce0_a_27, 2), 1216 INGENIC_PIN_GROUP("ssi-ce0-d", x1000_ssi_ce0_d, 0), 1217 INGENIC_PIN_GROUP("ssi-ce1-a-21", x1000_ssi_ce1_a_21, 2), 1218 INGENIC_PIN_GROUP("ssi-ce1-a-30", x1000_ssi_ce1_a_30, 2), 1219 INGENIC_PIN_GROUP("mmc0-1bit", x1000_mmc0_1bit, 1), 1220 INGENIC_PIN_GROUP("mmc0-4bit", x1000_mmc0_4bit, 1), 1221 INGENIC_PIN_GROUP("mmc0-8bit", x1000_mmc0_8bit, 1), 1222 INGENIC_PIN_GROUP("mmc1-1bit", x1000_mmc1_1bit, 0), 1223 INGENIC_PIN_GROUP("mmc1-4bit", x1000_mmc1_4bit, 0), 1224 INGENIC_PIN_GROUP("emc-8bit-data", x1000_emc_8bit_data, 0), 1225 INGENIC_PIN_GROUP("emc-16bit-data", x1000_emc_16bit_data, 0), 1226 INGENIC_PIN_GROUP("emc-addr", x1000_emc_addr, 0), 1227 INGENIC_PIN_GROUP("emc-rd-we", x1000_emc_rd_we, 0), 1228 INGENIC_PIN_GROUP("emc-wait", x1000_emc_wait, 0), 1229 INGENIC_PIN_GROUP("emc-cs1", x1000_emc_cs1, 0), 1230 INGENIC_PIN_GROUP("emc-cs2", x1000_emc_cs2, 0), 1231 INGENIC_PIN_GROUP("i2c0-data", x1000_i2c0, 0), 1232 INGENIC_PIN_GROUP("i2c1-data-a", x1000_i2c1_a, 2), 1233 INGENIC_PIN_GROUP("i2c1-data-c", x1000_i2c1_c, 0), 1234 INGENIC_PIN_GROUP("i2c2-data", x1000_i2c2, 1), 1235 INGENIC_PIN_GROUP("i2s-data-tx", x1000_i2s_data_tx, 1), 1236 INGENIC_PIN_GROUP("i2s-data-rx", x1000_i2s_data_rx, 1), 1237 INGENIC_PIN_GROUP("i2s-clk-txrx", x1000_i2s_clk_txrx, 1), 1238 INGENIC_PIN_GROUP("i2s-sysclk", x1000_i2s_sysclk, 1), 1239 INGENIC_PIN_GROUP("cim-data", x1000_cim, 2), 1240 INGENIC_PIN_GROUP("lcd-8bit", x1000_lcd_8bit, 1), 1241 INGENIC_PIN_GROUP("lcd-16bit", x1000_lcd_16bit, 1), 1242 { "lcd-no-pins", }, 1243 INGENIC_PIN_GROUP("pwm0", x1000_pwm_pwm0, 0), 1244 INGENIC_PIN_GROUP("pwm1", x1000_pwm_pwm1, 1), 1245 INGENIC_PIN_GROUP("pwm2", x1000_pwm_pwm2, 1), 1246 INGENIC_PIN_GROUP("pwm3", x1000_pwm_pwm3, 2), 1247 INGENIC_PIN_GROUP("pwm4", x1000_pwm_pwm4, 0), 1248 INGENIC_PIN_GROUP("mac", x1000_mac, 1), 1249 }; 1250 1251 static const char *x1000_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; 1252 static const char *x1000_uart1_groups[] = { 1253 "uart1-data-a", "uart1-data-d", "uart1-hwflow", 1254 }; 1255 static const char *x1000_uart2_groups[] = { "uart2-data-a", "uart2-data-d", }; 1256 static const char *x1000_sfc_groups[] = { "sfc", }; 1257 static const char *x1000_ssi_groups[] = { 1258 "ssi-dt-a-22", "ssi-dt-a-29", "ssi-dt-d", 1259 "ssi-dr-a-23", "ssi-dr-a-28", "ssi-dr-d", 1260 "ssi-clk-a-24", "ssi-clk-a-26", "ssi-clk-d", 1261 "ssi-gpc-a-20", "ssi-gpc-a-31", 1262 "ssi-ce0-a-25", "ssi-ce0-a-27", "ssi-ce0-d", 1263 "ssi-ce1-a-21", "ssi-ce1-a-30", 1264 }; 1265 static const char *x1000_mmc0_groups[] = { 1266 "mmc0-1bit", "mmc0-4bit", "mmc0-8bit", 1267 }; 1268 static const char *x1000_mmc1_groups[] = { 1269 "mmc1-1bit", "mmc1-4bit", 1270 }; 1271 static const char *x1000_emc_groups[] = { 1272 "emc-8bit-data", "emc-16bit-data", 1273 "emc-addr", "emc-rd-we", "emc-wait", 1274 }; 1275 static const char *x1000_cs1_groups[] = { "emc-cs1", }; 1276 static const char *x1000_cs2_groups[] = { "emc-cs2", }; 1277 static const char *x1000_i2c0_groups[] = { "i2c0-data", }; 1278 static const char *x1000_i2c1_groups[] = { "i2c1-data-a", "i2c1-data-c", }; 1279 static const char *x1000_i2c2_groups[] = { "i2c2-data", }; 1280 static const char *x1000_i2s_groups[] = { 1281 "i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-sysclk", 1282 }; 1283 static const char *x1000_cim_groups[] = { "cim-data", }; 1284 static const char *x1000_lcd_groups[] = { 1285 "lcd-8bit", "lcd-16bit", "lcd-no-pins", 1286 }; 1287 static const char *x1000_pwm0_groups[] = { "pwm0", }; 1288 static const char *x1000_pwm1_groups[] = { "pwm1", }; 1289 static const char *x1000_pwm2_groups[] = { "pwm2", }; 1290 static const char *x1000_pwm3_groups[] = { "pwm3", }; 1291 static const char *x1000_pwm4_groups[] = { "pwm4", }; 1292 static const char *x1000_mac_groups[] = { "mac", }; 1293 1294 static const struct function_desc x1000_functions[] = { 1295 { "uart0", x1000_uart0_groups, ARRAY_SIZE(x1000_uart0_groups), }, 1296 { "uart1", x1000_uart1_groups, ARRAY_SIZE(x1000_uart1_groups), }, 1297 { "uart2", x1000_uart2_groups, ARRAY_SIZE(x1000_uart2_groups), }, 1298 { "sfc", x1000_sfc_groups, ARRAY_SIZE(x1000_sfc_groups), }, 1299 { "ssi", x1000_ssi_groups, ARRAY_SIZE(x1000_ssi_groups), }, 1300 { "mmc0", x1000_mmc0_groups, ARRAY_SIZE(x1000_mmc0_groups), }, 1301 { "mmc1", x1000_mmc1_groups, ARRAY_SIZE(x1000_mmc1_groups), }, 1302 { "emc", x1000_emc_groups, ARRAY_SIZE(x1000_emc_groups), }, 1303 { "emc-cs1", x1000_cs1_groups, ARRAY_SIZE(x1000_cs1_groups), }, 1304 { "emc-cs2", x1000_cs2_groups, ARRAY_SIZE(x1000_cs2_groups), }, 1305 { "i2c0", x1000_i2c0_groups, ARRAY_SIZE(x1000_i2c0_groups), }, 1306 { "i2c1", x1000_i2c1_groups, ARRAY_SIZE(x1000_i2c1_groups), }, 1307 { "i2c2", x1000_i2c2_groups, ARRAY_SIZE(x1000_i2c2_groups), }, 1308 { "i2s", x1000_i2s_groups, ARRAY_SIZE(x1000_i2s_groups), }, 1309 { "cim", x1000_cim_groups, ARRAY_SIZE(x1000_cim_groups), }, 1310 { "lcd", x1000_lcd_groups, ARRAY_SIZE(x1000_lcd_groups), }, 1311 { "pwm0", x1000_pwm0_groups, ARRAY_SIZE(x1000_pwm0_groups), }, 1312 { "pwm1", x1000_pwm1_groups, ARRAY_SIZE(x1000_pwm1_groups), }, 1313 { "pwm2", x1000_pwm2_groups, ARRAY_SIZE(x1000_pwm2_groups), }, 1314 { "pwm3", x1000_pwm3_groups, ARRAY_SIZE(x1000_pwm3_groups), }, 1315 { "pwm4", x1000_pwm4_groups, ARRAY_SIZE(x1000_pwm4_groups), }, 1316 { "mac", x1000_mac_groups, ARRAY_SIZE(x1000_mac_groups), }, 1317 }; 1318 1319 static const struct ingenic_chip_info x1000_chip_info = { 1320 .num_chips = 4, 1321 .reg_offset = 0x100, 1322 .version = ID_X1000, 1323 .groups = x1000_groups, 1324 .num_groups = ARRAY_SIZE(x1000_groups), 1325 .functions = x1000_functions, 1326 .num_functions = ARRAY_SIZE(x1000_functions), 1327 .pull_ups = x1000_pull_ups, 1328 .pull_downs = x1000_pull_downs, 1329 }; 1330 1331 static int x1500_uart0_data_pins[] = { 0x4a, 0x4b, }; 1332 static int x1500_uart0_hwflow_pins[] = { 0x4c, 0x4d, }; 1333 static int x1500_uart1_data_a_pins[] = { 0x04, 0x05, }; 1334 static int x1500_uart1_data_d_pins[] = { 0x62, 0x63, }; 1335 static int x1500_uart1_hwflow_pins[] = { 0x64, 0x65, }; 1336 static int x1500_uart2_data_a_pins[] = { 0x02, 0x03, }; 1337 static int x1500_uart2_data_d_pins[] = { 0x65, 0x64, }; 1338 static int x1500_mmc_1bit_pins[] = { 0x18, 0x19, 0x17, }; 1339 static int x1500_mmc_4bit_pins[] = { 0x16, 0x15, 0x14, }; 1340 static int x1500_i2c0_pins[] = { 0x38, 0x37, }; 1341 static int x1500_i2c1_a_pins[] = { 0x01, 0x00, }; 1342 static int x1500_i2c1_c_pins[] = { 0x5b, 0x5a, }; 1343 static int x1500_i2c2_pins[] = { 0x61, 0x60, }; 1344 static int x1500_i2s_data_tx_pins[] = { 0x24, }; 1345 static int x1500_i2s_data_rx_pins[] = { 0x23, }; 1346 static int x1500_i2s_clk_txrx_pins[] = { 0x21, 0x22, }; 1347 static int x1500_i2s_sysclk_pins[] = { 0x20, }; 1348 static int x1500_cim_pins[] = { 1349 0x08, 0x09, 0x0a, 0x0b, 1350 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 0x0d, 0x0c, 1351 }; 1352 static int x1500_pwm_pwm0_pins[] = { 0x59, }; 1353 static int x1500_pwm_pwm1_pins[] = { 0x5a, }; 1354 static int x1500_pwm_pwm2_pins[] = { 0x5b, }; 1355 static int x1500_pwm_pwm3_pins[] = { 0x26, }; 1356 static int x1500_pwm_pwm4_pins[] = { 0x58, }; 1357 1358 static const struct group_desc x1500_groups[] = { 1359 INGENIC_PIN_GROUP("uart0-data", x1500_uart0_data, 0), 1360 INGENIC_PIN_GROUP("uart0-hwflow", x1500_uart0_hwflow, 0), 1361 INGENIC_PIN_GROUP("uart1-data-a", x1500_uart1_data_a, 2), 1362 INGENIC_PIN_GROUP("uart1-data-d", x1500_uart1_data_d, 1), 1363 INGENIC_PIN_GROUP("uart1-hwflow", x1500_uart1_hwflow, 1), 1364 INGENIC_PIN_GROUP("uart2-data-a", x1500_uart2_data_a, 2), 1365 INGENIC_PIN_GROUP("uart2-data-d", x1500_uart2_data_d, 0), 1366 INGENIC_PIN_GROUP("sfc", x1000_sfc, 1), 1367 INGENIC_PIN_GROUP("mmc-1bit", x1500_mmc_1bit, 1), 1368 INGENIC_PIN_GROUP("mmc-4bit", x1500_mmc_4bit, 1), 1369 INGENIC_PIN_GROUP("i2c0-data", x1500_i2c0, 0), 1370 INGENIC_PIN_GROUP("i2c1-data-a", x1500_i2c1_a, 2), 1371 INGENIC_PIN_GROUP("i2c1-data-c", x1500_i2c1_c, 0), 1372 INGENIC_PIN_GROUP("i2c2-data", x1500_i2c2, 1), 1373 INGENIC_PIN_GROUP("i2s-data-tx", x1500_i2s_data_tx, 1), 1374 INGENIC_PIN_GROUP("i2s-data-rx", x1500_i2s_data_rx, 1), 1375 INGENIC_PIN_GROUP("i2s-clk-txrx", x1500_i2s_clk_txrx, 1), 1376 INGENIC_PIN_GROUP("i2s-sysclk", x1500_i2s_sysclk, 1), 1377 INGENIC_PIN_GROUP("cim-data", x1500_cim, 2), 1378 { "lcd-no-pins", }, 1379 INGENIC_PIN_GROUP("pwm0", x1500_pwm_pwm0, 0), 1380 INGENIC_PIN_GROUP("pwm1", x1500_pwm_pwm1, 1), 1381 INGENIC_PIN_GROUP("pwm2", x1500_pwm_pwm2, 1), 1382 INGENIC_PIN_GROUP("pwm3", x1500_pwm_pwm3, 2), 1383 INGENIC_PIN_GROUP("pwm4", x1500_pwm_pwm4, 0), 1384 }; 1385 1386 static const char *x1500_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; 1387 static const char *x1500_uart1_groups[] = { 1388 "uart1-data-a", "uart1-data-d", "uart1-hwflow", 1389 }; 1390 static const char *x1500_uart2_groups[] = { "uart2-data-a", "uart2-data-d", }; 1391 static const char *x1500_mmc_groups[] = { "mmc-1bit", "mmc-4bit", }; 1392 static const char *x1500_i2c0_groups[] = { "i2c0-data", }; 1393 static const char *x1500_i2c1_groups[] = { "i2c1-data-a", "i2c1-data-c", }; 1394 static const char *x1500_i2c2_groups[] = { "i2c2-data", }; 1395 static const char *x1500_i2s_groups[] = { 1396 "i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-sysclk", 1397 }; 1398 static const char *x1500_cim_groups[] = { "cim-data", }; 1399 static const char *x1500_lcd_groups[] = { "lcd-no-pins", }; 1400 static const char *x1500_pwm0_groups[] = { "pwm0", }; 1401 static const char *x1500_pwm1_groups[] = { "pwm1", }; 1402 static const char *x1500_pwm2_groups[] = { "pwm2", }; 1403 static const char *x1500_pwm3_groups[] = { "pwm3", }; 1404 static const char *x1500_pwm4_groups[] = { "pwm4", }; 1405 1406 static const struct function_desc x1500_functions[] = { 1407 { "uart0", x1500_uart0_groups, ARRAY_SIZE(x1500_uart0_groups), }, 1408 { "uart1", x1500_uart1_groups, ARRAY_SIZE(x1500_uart1_groups), }, 1409 { "uart2", x1500_uart2_groups, ARRAY_SIZE(x1500_uart2_groups), }, 1410 { "sfc", x1000_sfc_groups, ARRAY_SIZE(x1000_sfc_groups), }, 1411 { "mmc", x1500_mmc_groups, ARRAY_SIZE(x1500_mmc_groups), }, 1412 { "i2c0", x1500_i2c0_groups, ARRAY_SIZE(x1500_i2c0_groups), }, 1413 { "i2c1", x1500_i2c1_groups, ARRAY_SIZE(x1500_i2c1_groups), }, 1414 { "i2c2", x1500_i2c2_groups, ARRAY_SIZE(x1500_i2c2_groups), }, 1415 { "i2s", x1500_i2s_groups, ARRAY_SIZE(x1500_i2s_groups), }, 1416 { "cim", x1500_cim_groups, ARRAY_SIZE(x1500_cim_groups), }, 1417 { "lcd", x1500_lcd_groups, ARRAY_SIZE(x1500_lcd_groups), }, 1418 { "pwm0", x1500_pwm0_groups, ARRAY_SIZE(x1500_pwm0_groups), }, 1419 { "pwm1", x1500_pwm1_groups, ARRAY_SIZE(x1500_pwm1_groups), }, 1420 { "pwm2", x1500_pwm2_groups, ARRAY_SIZE(x1500_pwm2_groups), }, 1421 { "pwm3", x1500_pwm3_groups, ARRAY_SIZE(x1500_pwm3_groups), }, 1422 { "pwm4", x1500_pwm4_groups, ARRAY_SIZE(x1500_pwm4_groups), }, 1423 }; 1424 1425 static const struct ingenic_chip_info x1500_chip_info = { 1426 .num_chips = 4, 1427 .reg_offset = 0x100, 1428 .version = ID_X1500, 1429 .groups = x1500_groups, 1430 .num_groups = ARRAY_SIZE(x1500_groups), 1431 .functions = x1500_functions, 1432 .num_functions = ARRAY_SIZE(x1500_functions), 1433 .pull_ups = x1000_pull_ups, 1434 .pull_downs = x1000_pull_downs, 1435 }; 1436 1437 static const u32 x1830_pull_ups[4] = { 1438 0x5fdfffc0, 0xffffefff, 0x1ffffbff, 0x0fcff3fc, 1439 }; 1440 1441 static const u32 x1830_pull_downs[4] = { 1442 0x5fdfffc0, 0xffffefff, 0x1ffffbff, 0x0fcff3fc, 1443 }; 1444 1445 static int x1830_uart0_data_pins[] = { 0x33, 0x36, }; 1446 static int x1830_uart0_hwflow_pins[] = { 0x34, 0x35, }; 1447 static int x1830_uart1_data_pins[] = { 0x38, 0x37, }; 1448 static int x1830_sfc_pins[] = { 0x17, 0x18, 0x1a, 0x19, 0x1b, 0x1c, }; 1449 static int x1830_ssi0_dt_pins[] = { 0x4c, }; 1450 static int x1830_ssi0_dr_pins[] = { 0x4b, }; 1451 static int x1830_ssi0_clk_pins[] = { 0x4f, }; 1452 static int x1830_ssi0_gpc_pins[] = { 0x4d, }; 1453 static int x1830_ssi0_ce0_pins[] = { 0x50, }; 1454 static int x1830_ssi0_ce1_pins[] = { 0x4e, }; 1455 static int x1830_ssi1_dt_c_pins[] = { 0x53, }; 1456 static int x1830_ssi1_dr_c_pins[] = { 0x54, }; 1457 static int x1830_ssi1_clk_c_pins[] = { 0x57, }; 1458 static int x1830_ssi1_gpc_c_pins[] = { 0x55, }; 1459 static int x1830_ssi1_ce0_c_pins[] = { 0x58, }; 1460 static int x1830_ssi1_ce1_c_pins[] = { 0x56, }; 1461 static int x1830_ssi1_dt_d_pins[] = { 0x62, }; 1462 static int x1830_ssi1_dr_d_pins[] = { 0x63, }; 1463 static int x1830_ssi1_clk_d_pins[] = { 0x66, }; 1464 static int x1830_ssi1_gpc_d_pins[] = { 0x64, }; 1465 static int x1830_ssi1_ce0_d_pins[] = { 0x67, }; 1466 static int x1830_ssi1_ce1_d_pins[] = { 0x65, }; 1467 static int x1830_mmc0_1bit_pins[] = { 0x24, 0x25, 0x20, }; 1468 static int x1830_mmc0_4bit_pins[] = { 0x21, 0x22, 0x23, }; 1469 static int x1830_mmc1_1bit_pins[] = { 0x42, 0x43, 0x44, }; 1470 static int x1830_mmc1_4bit_pins[] = { 0x45, 0x46, 0x47, }; 1471 static int x1830_i2c0_pins[] = { 0x0c, 0x0d, }; 1472 static int x1830_i2c1_pins[] = { 0x39, 0x3a, }; 1473 static int x1830_i2c2_pins[] = { 0x5b, 0x5c, }; 1474 static int x1830_i2s_data_tx_pins[] = { 0x53, }; 1475 static int x1830_i2s_data_rx_pins[] = { 0x54, }; 1476 static int x1830_i2s_clk_txrx_pins[] = { 0x58, 0x52, }; 1477 static int x1830_i2s_clk_rx_pins[] = { 0x56, 0x55, }; 1478 static int x1830_i2s_sysclk_pins[] = { 0x57, }; 1479 static int x1830_lcd_rgb_18bit_pins[] = { 1480 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 1481 0x68, 0x69, 0x6c, 0x6d, 0x6e, 0x6f, 1482 0x70, 0x71, 0x72, 0x73, 0x76, 0x77, 1483 0x78, 0x79, 0x7a, 0x7b, 1484 }; 1485 static int x1830_lcd_slcd_8bit_pins[] = { 1486 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x6c, 0x6d, 1487 0x69, 0x72, 0x73, 0x7b, 0x7a, 1488 }; 1489 static int x1830_lcd_slcd_16bit_pins[] = { 1490 0x6e, 0x6f, 0x70, 0x71, 0x76, 0x77, 0x78, 0x79, 1491 }; 1492 static int x1830_pwm_pwm0_b_pins[] = { 0x31, }; 1493 static int x1830_pwm_pwm0_c_pins[] = { 0x4b, }; 1494 static int x1830_pwm_pwm1_b_pins[] = { 0x32, }; 1495 static int x1830_pwm_pwm1_c_pins[] = { 0x4c, }; 1496 static int x1830_pwm_pwm2_c_8_pins[] = { 0x48, }; 1497 static int x1830_pwm_pwm2_c_13_pins[] = { 0x4d, }; 1498 static int x1830_pwm_pwm3_c_9_pins[] = { 0x49, }; 1499 static int x1830_pwm_pwm3_c_14_pins[] = { 0x4e, }; 1500 static int x1830_pwm_pwm4_c_15_pins[] = { 0x4f, }; 1501 static int x1830_pwm_pwm4_c_25_pins[] = { 0x59, }; 1502 static int x1830_pwm_pwm5_c_16_pins[] = { 0x50, }; 1503 static int x1830_pwm_pwm5_c_26_pins[] = { 0x5a, }; 1504 static int x1830_pwm_pwm6_c_17_pins[] = { 0x51, }; 1505 static int x1830_pwm_pwm6_c_27_pins[] = { 0x5b, }; 1506 static int x1830_pwm_pwm7_c_18_pins[] = { 0x52, }; 1507 static int x1830_pwm_pwm7_c_28_pins[] = { 0x5c, }; 1508 static int x1830_mac_pins[] = { 1509 0x29, 0x30, 0x2f, 0x28, 0x2e, 0x2d, 0x2a, 0x2b, 0x26, 0x27, 1510 }; 1511 1512 static const struct group_desc x1830_groups[] = { 1513 INGENIC_PIN_GROUP("uart0-data", x1830_uart0_data, 0), 1514 INGENIC_PIN_GROUP("uart0-hwflow", x1830_uart0_hwflow, 0), 1515 INGENIC_PIN_GROUP("uart1-data", x1830_uart1_data, 0), 1516 INGENIC_PIN_GROUP("sfc", x1830_sfc, 1), 1517 INGENIC_PIN_GROUP("ssi0-dt", x1830_ssi0_dt, 0), 1518 INGENIC_PIN_GROUP("ssi0-dr", x1830_ssi0_dr, 0), 1519 INGENIC_PIN_GROUP("ssi0-clk", x1830_ssi0_clk, 0), 1520 INGENIC_PIN_GROUP("ssi0-gpc", x1830_ssi0_gpc, 0), 1521 INGENIC_PIN_GROUP("ssi0-ce0", x1830_ssi0_ce0, 0), 1522 INGENIC_PIN_GROUP("ssi0-ce1", x1830_ssi0_ce1, 0), 1523 INGENIC_PIN_GROUP("ssi1-dt-c", x1830_ssi1_dt_c, 1), 1524 INGENIC_PIN_GROUP("ssi1-dr-c", x1830_ssi1_dr_c, 1), 1525 INGENIC_PIN_GROUP("ssi1-clk-c", x1830_ssi1_clk_c, 1), 1526 INGENIC_PIN_GROUP("ssi1-gpc-c", x1830_ssi1_gpc_c, 1), 1527 INGENIC_PIN_GROUP("ssi1-ce0-c", x1830_ssi1_ce0_c, 1), 1528 INGENIC_PIN_GROUP("ssi1-ce1-c", x1830_ssi1_ce1_c, 1), 1529 INGENIC_PIN_GROUP("ssi1-dt-d", x1830_ssi1_dt_d, 2), 1530 INGENIC_PIN_GROUP("ssi1-dr-d", x1830_ssi1_dr_d, 2), 1531 INGENIC_PIN_GROUP("ssi1-clk-d", x1830_ssi1_clk_d, 2), 1532 INGENIC_PIN_GROUP("ssi1-gpc-d", x1830_ssi1_gpc_d, 2), 1533 INGENIC_PIN_GROUP("ssi1-ce0-d", x1830_ssi1_ce0_d, 2), 1534 INGENIC_PIN_GROUP("ssi1-ce1-d", x1830_ssi1_ce1_d, 2), 1535 INGENIC_PIN_GROUP("mmc0-1bit", x1830_mmc0_1bit, 0), 1536 INGENIC_PIN_GROUP("mmc0-4bit", x1830_mmc0_4bit, 0), 1537 INGENIC_PIN_GROUP("mmc1-1bit", x1830_mmc1_1bit, 0), 1538 INGENIC_PIN_GROUP("mmc1-4bit", x1830_mmc1_4bit, 0), 1539 INGENIC_PIN_GROUP("i2c0-data", x1830_i2c0, 1), 1540 INGENIC_PIN_GROUP("i2c1-data", x1830_i2c1, 0), 1541 INGENIC_PIN_GROUP("i2c2-data", x1830_i2c2, 1), 1542 INGENIC_PIN_GROUP("i2s-data-tx", x1830_i2s_data_tx, 0), 1543 INGENIC_PIN_GROUP("i2s-data-rx", x1830_i2s_data_rx, 0), 1544 INGENIC_PIN_GROUP("i2s-clk-txrx", x1830_i2s_clk_txrx, 0), 1545 INGENIC_PIN_GROUP("i2s-clk-rx", x1830_i2s_clk_rx, 0), 1546 INGENIC_PIN_GROUP("i2s-sysclk", x1830_i2s_sysclk, 0), 1547 INGENIC_PIN_GROUP("lcd-rgb-18bit", x1830_lcd_rgb_18bit, 0), 1548 INGENIC_PIN_GROUP("lcd-slcd-8bit", x1830_lcd_slcd_8bit, 1), 1549 INGENIC_PIN_GROUP("lcd-slcd-16bit", x1830_lcd_slcd_16bit, 1), 1550 { "lcd-no-pins", }, 1551 INGENIC_PIN_GROUP("pwm0-b", x1830_pwm_pwm0_b, 0), 1552 INGENIC_PIN_GROUP("pwm0-c", x1830_pwm_pwm0_c, 1), 1553 INGENIC_PIN_GROUP("pwm1-b", x1830_pwm_pwm1_b, 0), 1554 INGENIC_PIN_GROUP("pwm1-c", x1830_pwm_pwm1_c, 1), 1555 INGENIC_PIN_GROUP("pwm2-c-8", x1830_pwm_pwm2_c_8, 0), 1556 INGENIC_PIN_GROUP("pwm2-c-13", x1830_pwm_pwm2_c_13, 1), 1557 INGENIC_PIN_GROUP("pwm3-c-9", x1830_pwm_pwm3_c_9, 0), 1558 INGENIC_PIN_GROUP("pwm3-c-14", x1830_pwm_pwm3_c_14, 1), 1559 INGENIC_PIN_GROUP("pwm4-c-15", x1830_pwm_pwm4_c_15, 1), 1560 INGENIC_PIN_GROUP("pwm4-c-25", x1830_pwm_pwm4_c_25, 0), 1561 INGENIC_PIN_GROUP("pwm5-c-16", x1830_pwm_pwm5_c_16, 1), 1562 INGENIC_PIN_GROUP("pwm5-c-26", x1830_pwm_pwm5_c_26, 0), 1563 INGENIC_PIN_GROUP("pwm6-c-17", x1830_pwm_pwm6_c_17, 1), 1564 INGENIC_PIN_GROUP("pwm6-c-27", x1830_pwm_pwm6_c_27, 0), 1565 INGENIC_PIN_GROUP("pwm7-c-18", x1830_pwm_pwm7_c_18, 1), 1566 INGENIC_PIN_GROUP("pwm7-c-28", x1830_pwm_pwm7_c_28, 0), 1567 INGENIC_PIN_GROUP("mac", x1830_mac, 0), 1568 }; 1569 1570 static const char *x1830_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; 1571 static const char *x1830_uart1_groups[] = { "uart1-data", }; 1572 static const char *x1830_sfc_groups[] = { "sfc", }; 1573 static const char *x1830_ssi0_groups[] = { 1574 "ssi0-dt", "ssi0-dr", "ssi0-clk", "ssi0-gpc", "ssi0-ce0", "ssi0-ce1", 1575 }; 1576 static const char *x1830_ssi1_groups[] = { 1577 "ssi1-dt-c", "ssi1-dt-d", 1578 "ssi1-dr-c", "ssi1-dr-d", 1579 "ssi1-clk-c", "ssi1-clk-d", 1580 "ssi1-gpc-c", "ssi1-gpc-d", 1581 "ssi1-ce0-c", "ssi1-ce0-d", 1582 "ssi1-ce1-c", "ssi1-ce1-d", 1583 }; 1584 static const char *x1830_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", }; 1585 static const char *x1830_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", }; 1586 static const char *x1830_i2c0_groups[] = { "i2c0-data", }; 1587 static const char *x1830_i2c1_groups[] = { "i2c1-data", }; 1588 static const char *x1830_i2c2_groups[] = { "i2c2-data", }; 1589 static const char *x1830_i2s_groups[] = { 1590 "i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-clk-rx", "i2s-sysclk", 1591 }; 1592 static const char *x1830_lcd_groups[] = { 1593 "lcd-rgb-18bit", "lcd-slcd-8bit", "lcd-slcd-16bit", "lcd-no-pins", 1594 }; 1595 static const char *x1830_pwm0_groups[] = { "pwm0-b", "pwm0-c", }; 1596 static const char *x1830_pwm1_groups[] = { "pwm1-b", "pwm1-c", }; 1597 static const char *x1830_pwm2_groups[] = { "pwm2-c-8", "pwm2-c-13", }; 1598 static const char *x1830_pwm3_groups[] = { "pwm3-c-9", "pwm3-c-14", }; 1599 static const char *x1830_pwm4_groups[] = { "pwm4-c-15", "pwm4-c-25", }; 1600 static const char *x1830_pwm5_groups[] = { "pwm5-c-16", "pwm5-c-26", }; 1601 static const char *x1830_pwm6_groups[] = { "pwm6-c-17", "pwm6-c-27", }; 1602 static const char *x1830_pwm7_groups[] = { "pwm7-c-18", "pwm7-c-28", }; 1603 static const char *x1830_mac_groups[] = { "mac", }; 1604 1605 static const struct function_desc x1830_functions[] = { 1606 { "uart0", x1830_uart0_groups, ARRAY_SIZE(x1830_uart0_groups), }, 1607 { "uart1", x1830_uart1_groups, ARRAY_SIZE(x1830_uart1_groups), }, 1608 { "sfc", x1830_sfc_groups, ARRAY_SIZE(x1830_sfc_groups), }, 1609 { "ssi0", x1830_ssi0_groups, ARRAY_SIZE(x1830_ssi0_groups), }, 1610 { "ssi1", x1830_ssi1_groups, ARRAY_SIZE(x1830_ssi1_groups), }, 1611 { "mmc0", x1830_mmc0_groups, ARRAY_SIZE(x1830_mmc0_groups), }, 1612 { "mmc1", x1830_mmc1_groups, ARRAY_SIZE(x1830_mmc1_groups), }, 1613 { "i2c0", x1830_i2c0_groups, ARRAY_SIZE(x1830_i2c0_groups), }, 1614 { "i2c1", x1830_i2c1_groups, ARRAY_SIZE(x1830_i2c1_groups), }, 1615 { "i2c2", x1830_i2c2_groups, ARRAY_SIZE(x1830_i2c2_groups), }, 1616 { "i2s", x1830_i2s_groups, ARRAY_SIZE(x1830_i2s_groups), }, 1617 { "lcd", x1830_lcd_groups, ARRAY_SIZE(x1830_lcd_groups), }, 1618 { "pwm0", x1830_pwm0_groups, ARRAY_SIZE(x1830_pwm0_groups), }, 1619 { "pwm1", x1830_pwm1_groups, ARRAY_SIZE(x1830_pwm1_groups), }, 1620 { "pwm2", x1830_pwm2_groups, ARRAY_SIZE(x1830_pwm2_groups), }, 1621 { "pwm3", x1830_pwm3_groups, ARRAY_SIZE(x1830_pwm3_groups), }, 1622 { "pwm4", x1830_pwm4_groups, ARRAY_SIZE(x1830_pwm4_groups), }, 1623 { "pwm5", x1830_pwm5_groups, ARRAY_SIZE(x1830_pwm4_groups), }, 1624 { "pwm6", x1830_pwm6_groups, ARRAY_SIZE(x1830_pwm4_groups), }, 1625 { "pwm7", x1830_pwm7_groups, ARRAY_SIZE(x1830_pwm4_groups), }, 1626 { "mac", x1830_mac_groups, ARRAY_SIZE(x1830_mac_groups), }, 1627 }; 1628 1629 static const struct ingenic_chip_info x1830_chip_info = { 1630 .num_chips = 4, 1631 .reg_offset = 0x1000, 1632 .version = ID_X1830, 1633 .groups = x1830_groups, 1634 .num_groups = ARRAY_SIZE(x1830_groups), 1635 .functions = x1830_functions, 1636 .num_functions = ARRAY_SIZE(x1830_functions), 1637 .pull_ups = x1830_pull_ups, 1638 .pull_downs = x1830_pull_downs, 1639 }; 1640 1641 static u32 ingenic_gpio_read_reg(struct ingenic_gpio_chip *jzgc, u8 reg) 1642 { 1643 unsigned int val; 1644 1645 regmap_read(jzgc->jzpc->map, jzgc->reg_base + reg, &val); 1646 1647 return (u32) val; 1648 } 1649 1650 static void ingenic_gpio_set_bit(struct ingenic_gpio_chip *jzgc, 1651 u8 reg, u8 offset, bool set) 1652 { 1653 if (set) 1654 reg = REG_SET(reg); 1655 else 1656 reg = REG_CLEAR(reg); 1657 1658 regmap_write(jzgc->jzpc->map, jzgc->reg_base + reg, BIT(offset)); 1659 } 1660 1661 static void ingenic_gpio_shadow_set_bit(struct ingenic_gpio_chip *jzgc, 1662 u8 reg, u8 offset, bool set) 1663 { 1664 if (set) 1665 reg = REG_SET(reg); 1666 else 1667 reg = REG_CLEAR(reg); 1668 1669 regmap_write(jzgc->jzpc->map, REG_PZ_BASE( 1670 jzgc->jzpc->info->reg_offset) + reg, BIT(offset)); 1671 } 1672 1673 static void ingenic_gpio_shadow_set_bit_load(struct ingenic_gpio_chip *jzgc) 1674 { 1675 regmap_write(jzgc->jzpc->map, REG_PZ_GID2LD( 1676 jzgc->jzpc->info->reg_offset), 1677 jzgc->gc.base / PINS_PER_GPIO_CHIP); 1678 } 1679 1680 static inline bool ingenic_gpio_get_value(struct ingenic_gpio_chip *jzgc, 1681 u8 offset) 1682 { 1683 unsigned int val = ingenic_gpio_read_reg(jzgc, GPIO_PIN); 1684 1685 return !!(val & BIT(offset)); 1686 } 1687 1688 static void ingenic_gpio_set_value(struct ingenic_gpio_chip *jzgc, 1689 u8 offset, int value) 1690 { 1691 if (jzgc->jzpc->info->version >= ID_JZ4760) 1692 ingenic_gpio_set_bit(jzgc, JZ4760_GPIO_PAT0, offset, !!value); 1693 else 1694 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_DATA, offset, !!value); 1695 } 1696 1697 static void irq_set_type(struct ingenic_gpio_chip *jzgc, 1698 u8 offset, unsigned int type) 1699 { 1700 u8 reg1, reg2; 1701 bool val1, val2; 1702 1703 switch (type) { 1704 case IRQ_TYPE_EDGE_RISING: 1705 val1 = val2 = true; 1706 break; 1707 case IRQ_TYPE_EDGE_FALLING: 1708 val1 = false; 1709 val2 = true; 1710 break; 1711 case IRQ_TYPE_LEVEL_HIGH: 1712 val1 = true; 1713 val2 = false; 1714 break; 1715 case IRQ_TYPE_LEVEL_LOW: 1716 default: 1717 val1 = val2 = false; 1718 break; 1719 } 1720 1721 if (jzgc->jzpc->info->version >= ID_JZ4760) { 1722 reg1 = JZ4760_GPIO_PAT1; 1723 reg2 = JZ4760_GPIO_PAT0; 1724 } else { 1725 reg1 = JZ4740_GPIO_TRIG; 1726 reg2 = JZ4740_GPIO_DIR; 1727 } 1728 1729 if (jzgc->jzpc->info->version >= ID_X1000) { 1730 ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, val1); 1731 ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, val2); 1732 ingenic_gpio_shadow_set_bit_load(jzgc); 1733 } else { 1734 ingenic_gpio_set_bit(jzgc, reg2, offset, val1); 1735 ingenic_gpio_set_bit(jzgc, reg1, offset, val2); 1736 } 1737 } 1738 1739 static void ingenic_gpio_irq_mask(struct irq_data *irqd) 1740 { 1741 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); 1742 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 1743 1744 ingenic_gpio_set_bit(jzgc, GPIO_MSK, irqd->hwirq, true); 1745 } 1746 1747 static void ingenic_gpio_irq_unmask(struct irq_data *irqd) 1748 { 1749 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); 1750 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 1751 1752 ingenic_gpio_set_bit(jzgc, GPIO_MSK, irqd->hwirq, false); 1753 } 1754 1755 static void ingenic_gpio_irq_enable(struct irq_data *irqd) 1756 { 1757 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); 1758 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 1759 int irq = irqd->hwirq; 1760 1761 if (jzgc->jzpc->info->version >= ID_JZ4760) 1762 ingenic_gpio_set_bit(jzgc, JZ4760_GPIO_INT, irq, true); 1763 else 1764 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, true); 1765 1766 ingenic_gpio_irq_unmask(irqd); 1767 } 1768 1769 static void ingenic_gpio_irq_disable(struct irq_data *irqd) 1770 { 1771 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); 1772 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 1773 int irq = irqd->hwirq; 1774 1775 ingenic_gpio_irq_mask(irqd); 1776 1777 if (jzgc->jzpc->info->version >= ID_JZ4760) 1778 ingenic_gpio_set_bit(jzgc, JZ4760_GPIO_INT, irq, false); 1779 else 1780 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, false); 1781 } 1782 1783 static void ingenic_gpio_irq_ack(struct irq_data *irqd) 1784 { 1785 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); 1786 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 1787 int irq = irqd->hwirq; 1788 bool high; 1789 1790 if (irqd_get_trigger_type(irqd) == IRQ_TYPE_EDGE_BOTH) { 1791 /* 1792 * Switch to an interrupt for the opposite edge to the one that 1793 * triggered the interrupt being ACKed. 1794 */ 1795 high = ingenic_gpio_get_value(jzgc, irq); 1796 if (high) 1797 irq_set_type(jzgc, irq, IRQ_TYPE_LEVEL_LOW); 1798 else 1799 irq_set_type(jzgc, irq, IRQ_TYPE_LEVEL_HIGH); 1800 } 1801 1802 if (jzgc->jzpc->info->version >= ID_JZ4760) 1803 ingenic_gpio_set_bit(jzgc, JZ4760_GPIO_FLAG, irq, false); 1804 else 1805 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_DATA, irq, true); 1806 } 1807 1808 static int ingenic_gpio_irq_set_type(struct irq_data *irqd, unsigned int type) 1809 { 1810 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); 1811 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 1812 1813 switch (type) { 1814 case IRQ_TYPE_EDGE_BOTH: 1815 case IRQ_TYPE_EDGE_RISING: 1816 case IRQ_TYPE_EDGE_FALLING: 1817 irq_set_handler_locked(irqd, handle_edge_irq); 1818 break; 1819 case IRQ_TYPE_LEVEL_HIGH: 1820 case IRQ_TYPE_LEVEL_LOW: 1821 irq_set_handler_locked(irqd, handle_level_irq); 1822 break; 1823 default: 1824 irq_set_handler_locked(irqd, handle_bad_irq); 1825 } 1826 1827 if (type == IRQ_TYPE_EDGE_BOTH) { 1828 /* 1829 * The hardware does not support interrupts on both edges. The 1830 * best we can do is to set up a single-edge interrupt and then 1831 * switch to the opposing edge when ACKing the interrupt. 1832 */ 1833 bool high = ingenic_gpio_get_value(jzgc, irqd->hwirq); 1834 1835 type = high ? IRQ_TYPE_LEVEL_LOW : IRQ_TYPE_LEVEL_HIGH; 1836 } 1837 1838 irq_set_type(jzgc, irqd->hwirq, type); 1839 return 0; 1840 } 1841 1842 static int ingenic_gpio_irq_set_wake(struct irq_data *irqd, unsigned int on) 1843 { 1844 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); 1845 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 1846 1847 return irq_set_irq_wake(jzgc->irq, on); 1848 } 1849 1850 static void ingenic_gpio_irq_handler(struct irq_desc *desc) 1851 { 1852 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 1853 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 1854 struct irq_chip *irq_chip = irq_data_get_irq_chip(&desc->irq_data); 1855 unsigned long flag, i; 1856 1857 chained_irq_enter(irq_chip, desc); 1858 1859 if (jzgc->jzpc->info->version >= ID_JZ4760) 1860 flag = ingenic_gpio_read_reg(jzgc, JZ4760_GPIO_FLAG); 1861 else 1862 flag = ingenic_gpio_read_reg(jzgc, JZ4740_GPIO_FLAG); 1863 1864 for_each_set_bit(i, &flag, 32) 1865 generic_handle_irq(irq_linear_revmap(gc->irq.domain, i)); 1866 chained_irq_exit(irq_chip, desc); 1867 } 1868 1869 static void ingenic_gpio_set(struct gpio_chip *gc, 1870 unsigned int offset, int value) 1871 { 1872 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 1873 1874 ingenic_gpio_set_value(jzgc, offset, value); 1875 } 1876 1877 static int ingenic_gpio_get(struct gpio_chip *gc, unsigned int offset) 1878 { 1879 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 1880 1881 return (int) ingenic_gpio_get_value(jzgc, offset); 1882 } 1883 1884 static int ingenic_gpio_direction_input(struct gpio_chip *gc, 1885 unsigned int offset) 1886 { 1887 return pinctrl_gpio_direction_input(gc->base + offset); 1888 } 1889 1890 static int ingenic_gpio_direction_output(struct gpio_chip *gc, 1891 unsigned int offset, int value) 1892 { 1893 ingenic_gpio_set(gc, offset, value); 1894 return pinctrl_gpio_direction_output(gc->base + offset); 1895 } 1896 1897 static inline void ingenic_config_pin(struct ingenic_pinctrl *jzpc, 1898 unsigned int pin, u8 reg, bool set) 1899 { 1900 unsigned int idx = pin % PINS_PER_GPIO_CHIP; 1901 unsigned int offt = pin / PINS_PER_GPIO_CHIP; 1902 1903 regmap_write(jzpc->map, offt * jzpc->info->reg_offset + 1904 (set ? REG_SET(reg) : REG_CLEAR(reg)), BIT(idx)); 1905 } 1906 1907 static inline void ingenic_shadow_config_pin(struct ingenic_pinctrl *jzpc, 1908 unsigned int pin, u8 reg, bool set) 1909 { 1910 unsigned int idx = pin % PINS_PER_GPIO_CHIP; 1911 1912 regmap_write(jzpc->map, REG_PZ_BASE(jzpc->info->reg_offset) + 1913 (set ? REG_SET(reg) : REG_CLEAR(reg)), BIT(idx)); 1914 } 1915 1916 static inline void ingenic_shadow_config_pin_load(struct ingenic_pinctrl *jzpc, 1917 unsigned int pin) 1918 { 1919 regmap_write(jzpc->map, REG_PZ_GID2LD(jzpc->info->reg_offset), 1920 pin / PINS_PER_GPIO_CHIP); 1921 } 1922 1923 static inline bool ingenic_get_pin_config(struct ingenic_pinctrl *jzpc, 1924 unsigned int pin, u8 reg) 1925 { 1926 unsigned int idx = pin % PINS_PER_GPIO_CHIP; 1927 unsigned int offt = pin / PINS_PER_GPIO_CHIP; 1928 unsigned int val; 1929 1930 regmap_read(jzpc->map, offt * jzpc->info->reg_offset + reg, &val); 1931 1932 return val & BIT(idx); 1933 } 1934 1935 static int ingenic_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) 1936 { 1937 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 1938 struct ingenic_pinctrl *jzpc = jzgc->jzpc; 1939 unsigned int pin = gc->base + offset; 1940 1941 if (jzpc->info->version >= ID_JZ4760) { 1942 if (ingenic_get_pin_config(jzpc, pin, JZ4760_GPIO_INT) || 1943 ingenic_get_pin_config(jzpc, pin, JZ4760_GPIO_PAT1)) 1944 return GPIO_LINE_DIRECTION_IN; 1945 return GPIO_LINE_DIRECTION_OUT; 1946 } 1947 1948 if (ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_SELECT)) 1949 return GPIO_LINE_DIRECTION_IN; 1950 1951 if (ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_DIR)) 1952 return GPIO_LINE_DIRECTION_OUT; 1953 1954 return GPIO_LINE_DIRECTION_IN; 1955 } 1956 1957 static const struct pinctrl_ops ingenic_pctlops = { 1958 .get_groups_count = pinctrl_generic_get_group_count, 1959 .get_group_name = pinctrl_generic_get_group_name, 1960 .get_group_pins = pinctrl_generic_get_group_pins, 1961 .dt_node_to_map = pinconf_generic_dt_node_to_map_all, 1962 .dt_free_map = pinconf_generic_dt_free_map, 1963 }; 1964 1965 static int ingenic_gpio_irq_request(struct irq_data *data) 1966 { 1967 struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data); 1968 int ret; 1969 1970 ret = ingenic_gpio_direction_input(gpio_chip, data->hwirq); 1971 if (ret) 1972 return ret; 1973 1974 return gpiochip_reqres_irq(gpio_chip, data->hwirq); 1975 } 1976 1977 static void ingenic_gpio_irq_release(struct irq_data *data) 1978 { 1979 struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data); 1980 1981 return gpiochip_relres_irq(gpio_chip, data->hwirq); 1982 } 1983 1984 static int ingenic_pinmux_set_pin_fn(struct ingenic_pinctrl *jzpc, 1985 int pin, int func) 1986 { 1987 unsigned int idx = pin % PINS_PER_GPIO_CHIP; 1988 unsigned int offt = pin / PINS_PER_GPIO_CHIP; 1989 1990 dev_dbg(jzpc->dev, "set pin P%c%u to function %u\n", 1991 'A' + offt, idx, func); 1992 1993 if (jzpc->info->version >= ID_X1000) { 1994 ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_INT, false); 1995 ingenic_shadow_config_pin(jzpc, pin, GPIO_MSK, false); 1996 ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_PAT1, func & 0x2); 1997 ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_PAT0, func & 0x1); 1998 ingenic_shadow_config_pin_load(jzpc, pin); 1999 } else if (jzpc->info->version >= ID_JZ4760) { 2000 ingenic_config_pin(jzpc, pin, JZ4760_GPIO_INT, false); 2001 ingenic_config_pin(jzpc, pin, GPIO_MSK, false); 2002 ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PAT1, func & 0x2); 2003 ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PAT0, func & 0x1); 2004 } else { 2005 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_FUNC, true); 2006 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_TRIG, func & 0x2); 2007 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_SELECT, func > 0); 2008 } 2009 2010 return 0; 2011 } 2012 2013 static int ingenic_pinmux_set_mux(struct pinctrl_dev *pctldev, 2014 unsigned int selector, unsigned int group) 2015 { 2016 struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev); 2017 struct function_desc *func; 2018 struct group_desc *grp; 2019 unsigned int i; 2020 uintptr_t mode; 2021 u8 *pin_modes; 2022 2023 func = pinmux_generic_get_function(pctldev, selector); 2024 if (!func) 2025 return -EINVAL; 2026 2027 grp = pinctrl_generic_get_group(pctldev, group); 2028 if (!grp) 2029 return -EINVAL; 2030 2031 dev_dbg(pctldev->dev, "enable function %s group %s\n", 2032 func->name, grp->name); 2033 2034 mode = (uintptr_t)grp->data; 2035 if (mode <= 3) { 2036 for (i = 0; i < grp->num_pins; i++) 2037 ingenic_pinmux_set_pin_fn(jzpc, grp->pins[i], mode); 2038 } else { 2039 pin_modes = grp->data; 2040 2041 for (i = 0; i < grp->num_pins; i++) 2042 ingenic_pinmux_set_pin_fn(jzpc, grp->pins[i], pin_modes[i]); 2043 } 2044 2045 return 0; 2046 } 2047 2048 static int ingenic_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev, 2049 struct pinctrl_gpio_range *range, 2050 unsigned int pin, bool input) 2051 { 2052 struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev); 2053 unsigned int idx = pin % PINS_PER_GPIO_CHIP; 2054 unsigned int offt = pin / PINS_PER_GPIO_CHIP; 2055 2056 dev_dbg(pctldev->dev, "set pin P%c%u to %sput\n", 2057 'A' + offt, idx, input ? "in" : "out"); 2058 2059 if (jzpc->info->version >= ID_X1000) { 2060 ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_INT, false); 2061 ingenic_shadow_config_pin(jzpc, pin, GPIO_MSK, true); 2062 ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_PAT1, input); 2063 ingenic_shadow_config_pin_load(jzpc, pin); 2064 } else if (jzpc->info->version >= ID_JZ4760) { 2065 ingenic_config_pin(jzpc, pin, JZ4760_GPIO_INT, false); 2066 ingenic_config_pin(jzpc, pin, GPIO_MSK, true); 2067 ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PAT1, input); 2068 } else { 2069 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_SELECT, false); 2070 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_DIR, !input); 2071 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_FUNC, false); 2072 } 2073 2074 return 0; 2075 } 2076 2077 static const struct pinmux_ops ingenic_pmxops = { 2078 .get_functions_count = pinmux_generic_get_function_count, 2079 .get_function_name = pinmux_generic_get_function_name, 2080 .get_function_groups = pinmux_generic_get_function_groups, 2081 .set_mux = ingenic_pinmux_set_mux, 2082 .gpio_set_direction = ingenic_pinmux_gpio_set_direction, 2083 }; 2084 2085 static int ingenic_pinconf_get(struct pinctrl_dev *pctldev, 2086 unsigned int pin, unsigned long *config) 2087 { 2088 struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev); 2089 enum pin_config_param param = pinconf_to_config_param(*config); 2090 unsigned int idx = pin % PINS_PER_GPIO_CHIP; 2091 unsigned int offt = pin / PINS_PER_GPIO_CHIP; 2092 bool pull; 2093 2094 if (jzpc->info->version >= ID_JZ4760) 2095 pull = !ingenic_get_pin_config(jzpc, pin, JZ4760_GPIO_PEN); 2096 else 2097 pull = !ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_PULL_DIS); 2098 2099 switch (param) { 2100 case PIN_CONFIG_BIAS_DISABLE: 2101 if (pull) 2102 return -EINVAL; 2103 break; 2104 2105 case PIN_CONFIG_BIAS_PULL_UP: 2106 if (!pull || !(jzpc->info->pull_ups[offt] & BIT(idx))) 2107 return -EINVAL; 2108 break; 2109 2110 case PIN_CONFIG_BIAS_PULL_DOWN: 2111 if (!pull || !(jzpc->info->pull_downs[offt] & BIT(idx))) 2112 return -EINVAL; 2113 break; 2114 2115 default: 2116 return -ENOTSUPP; 2117 } 2118 2119 *config = pinconf_to_config_packed(param, 1); 2120 return 0; 2121 } 2122 2123 static void ingenic_set_bias(struct ingenic_pinctrl *jzpc, 2124 unsigned int pin, unsigned int bias) 2125 { 2126 if (jzpc->info->version >= ID_X1830) { 2127 unsigned int idx = pin % PINS_PER_GPIO_CHIP; 2128 unsigned int half = PINS_PER_GPIO_CHIP / 2; 2129 unsigned int idxh = pin % half * 2; 2130 unsigned int offt = pin / PINS_PER_GPIO_CHIP; 2131 2132 if (idx < half) { 2133 regmap_write(jzpc->map, offt * jzpc->info->reg_offset + 2134 REG_CLEAR(X1830_GPIO_PEL), 3 << idxh); 2135 regmap_write(jzpc->map, offt * jzpc->info->reg_offset + 2136 REG_SET(X1830_GPIO_PEL), bias << idxh); 2137 } else { 2138 regmap_write(jzpc->map, offt * jzpc->info->reg_offset + 2139 REG_CLEAR(X1830_GPIO_PEH), 3 << idxh); 2140 regmap_write(jzpc->map, offt * jzpc->info->reg_offset + 2141 REG_SET(X1830_GPIO_PEH), bias << idxh); 2142 } 2143 2144 } else if (jzpc->info->version >= ID_JZ4760) { 2145 ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PEN, !bias); 2146 } else { 2147 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_PULL_DIS, !bias); 2148 } 2149 } 2150 2151 static void ingenic_set_output_level(struct ingenic_pinctrl *jzpc, 2152 unsigned int pin, bool high) 2153 { 2154 if (jzpc->info->version >= ID_JZ4760) 2155 ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PAT0, high); 2156 else 2157 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_DATA, high); 2158 } 2159 2160 static int ingenic_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 2161 unsigned long *configs, unsigned int num_configs) 2162 { 2163 struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev); 2164 unsigned int idx = pin % PINS_PER_GPIO_CHIP; 2165 unsigned int offt = pin / PINS_PER_GPIO_CHIP; 2166 unsigned int cfg, arg; 2167 int ret; 2168 2169 for (cfg = 0; cfg < num_configs; cfg++) { 2170 switch (pinconf_to_config_param(configs[cfg])) { 2171 case PIN_CONFIG_BIAS_DISABLE: 2172 case PIN_CONFIG_BIAS_PULL_UP: 2173 case PIN_CONFIG_BIAS_PULL_DOWN: 2174 case PIN_CONFIG_OUTPUT: 2175 continue; 2176 default: 2177 return -ENOTSUPP; 2178 } 2179 } 2180 2181 for (cfg = 0; cfg < num_configs; cfg++) { 2182 arg = pinconf_to_config_argument(configs[cfg]); 2183 2184 switch (pinconf_to_config_param(configs[cfg])) { 2185 case PIN_CONFIG_BIAS_DISABLE: 2186 dev_dbg(jzpc->dev, "disable pull-over for pin P%c%u\n", 2187 'A' + offt, idx); 2188 ingenic_set_bias(jzpc, pin, GPIO_PULL_DIS); 2189 break; 2190 2191 case PIN_CONFIG_BIAS_PULL_UP: 2192 if (!(jzpc->info->pull_ups[offt] & BIT(idx))) 2193 return -EINVAL; 2194 dev_dbg(jzpc->dev, "set pull-up for pin P%c%u\n", 2195 'A' + offt, idx); 2196 ingenic_set_bias(jzpc, pin, GPIO_PULL_UP); 2197 break; 2198 2199 case PIN_CONFIG_BIAS_PULL_DOWN: 2200 if (!(jzpc->info->pull_downs[offt] & BIT(idx))) 2201 return -EINVAL; 2202 dev_dbg(jzpc->dev, "set pull-down for pin P%c%u\n", 2203 'A' + offt, idx); 2204 ingenic_set_bias(jzpc, pin, GPIO_PULL_DOWN); 2205 break; 2206 2207 case PIN_CONFIG_OUTPUT: 2208 ret = pinctrl_gpio_direction_output(pin); 2209 if (ret) 2210 return ret; 2211 2212 ingenic_set_output_level(jzpc, pin, arg); 2213 break; 2214 2215 default: 2216 /* unreachable */ 2217 break; 2218 } 2219 } 2220 2221 return 0; 2222 } 2223 2224 static int ingenic_pinconf_group_get(struct pinctrl_dev *pctldev, 2225 unsigned int group, unsigned long *config) 2226 { 2227 const unsigned int *pins; 2228 unsigned int i, npins, old = 0; 2229 int ret; 2230 2231 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); 2232 if (ret) 2233 return ret; 2234 2235 for (i = 0; i < npins; i++) { 2236 if (ingenic_pinconf_get(pctldev, pins[i], config)) 2237 return -ENOTSUPP; 2238 2239 /* configs do not match between two pins */ 2240 if (i && (old != *config)) 2241 return -ENOTSUPP; 2242 2243 old = *config; 2244 } 2245 2246 return 0; 2247 } 2248 2249 static int ingenic_pinconf_group_set(struct pinctrl_dev *pctldev, 2250 unsigned int group, unsigned long *configs, 2251 unsigned int num_configs) 2252 { 2253 const unsigned int *pins; 2254 unsigned int i, npins; 2255 int ret; 2256 2257 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); 2258 if (ret) 2259 return ret; 2260 2261 for (i = 0; i < npins; i++) { 2262 ret = ingenic_pinconf_set(pctldev, 2263 pins[i], configs, num_configs); 2264 if (ret) 2265 return ret; 2266 } 2267 2268 return 0; 2269 } 2270 2271 static const struct pinconf_ops ingenic_confops = { 2272 .is_generic = true, 2273 .pin_config_get = ingenic_pinconf_get, 2274 .pin_config_set = ingenic_pinconf_set, 2275 .pin_config_group_get = ingenic_pinconf_group_get, 2276 .pin_config_group_set = ingenic_pinconf_group_set, 2277 }; 2278 2279 static const struct regmap_config ingenic_pinctrl_regmap_config = { 2280 .reg_bits = 32, 2281 .val_bits = 32, 2282 .reg_stride = 4, 2283 }; 2284 2285 static const struct of_device_id ingenic_gpio_of_match[] __initconst = { 2286 { .compatible = "ingenic,jz4740-gpio", }, 2287 { .compatible = "ingenic,jz4725b-gpio", }, 2288 { .compatible = "ingenic,jz4760-gpio", }, 2289 { .compatible = "ingenic,jz4770-gpio", }, 2290 { .compatible = "ingenic,jz4780-gpio", }, 2291 { .compatible = "ingenic,x1000-gpio", }, 2292 { .compatible = "ingenic,x1830-gpio", }, 2293 {}, 2294 }; 2295 2296 static int __init ingenic_gpio_probe(struct ingenic_pinctrl *jzpc, 2297 struct device_node *node) 2298 { 2299 struct ingenic_gpio_chip *jzgc; 2300 struct device *dev = jzpc->dev; 2301 struct gpio_irq_chip *girq; 2302 unsigned int bank; 2303 int err; 2304 2305 err = of_property_read_u32(node, "reg", &bank); 2306 if (err) { 2307 dev_err(dev, "Cannot read \"reg\" property: %i\n", err); 2308 return err; 2309 } 2310 2311 jzgc = devm_kzalloc(dev, sizeof(*jzgc), GFP_KERNEL); 2312 if (!jzgc) 2313 return -ENOMEM; 2314 2315 jzgc->jzpc = jzpc; 2316 jzgc->reg_base = bank * jzpc->info->reg_offset; 2317 2318 jzgc->gc.label = devm_kasprintf(dev, GFP_KERNEL, "GPIO%c", 'A' + bank); 2319 if (!jzgc->gc.label) 2320 return -ENOMEM; 2321 2322 /* DO NOT EXPAND THIS: FOR BACKWARD GPIO NUMBERSPACE COMPATIBIBILITY 2323 * ONLY: WORK TO TRANSITION CONSUMERS TO USE THE GPIO DESCRIPTOR API IN 2324 * <linux/gpio/consumer.h> INSTEAD. 2325 */ 2326 jzgc->gc.base = bank * 32; 2327 2328 jzgc->gc.ngpio = 32; 2329 jzgc->gc.parent = dev; 2330 jzgc->gc.of_node = node; 2331 jzgc->gc.owner = THIS_MODULE; 2332 2333 jzgc->gc.set = ingenic_gpio_set; 2334 jzgc->gc.get = ingenic_gpio_get; 2335 jzgc->gc.direction_input = ingenic_gpio_direction_input; 2336 jzgc->gc.direction_output = ingenic_gpio_direction_output; 2337 jzgc->gc.get_direction = ingenic_gpio_get_direction; 2338 jzgc->gc.request = gpiochip_generic_request; 2339 jzgc->gc.free = gpiochip_generic_free; 2340 2341 jzgc->irq = irq_of_parse_and_map(node, 0); 2342 if (!jzgc->irq) 2343 return -EINVAL; 2344 2345 jzgc->irq_chip.name = jzgc->gc.label; 2346 jzgc->irq_chip.irq_enable = ingenic_gpio_irq_enable; 2347 jzgc->irq_chip.irq_disable = ingenic_gpio_irq_disable; 2348 jzgc->irq_chip.irq_unmask = ingenic_gpio_irq_unmask; 2349 jzgc->irq_chip.irq_mask = ingenic_gpio_irq_mask; 2350 jzgc->irq_chip.irq_ack = ingenic_gpio_irq_ack; 2351 jzgc->irq_chip.irq_set_type = ingenic_gpio_irq_set_type; 2352 jzgc->irq_chip.irq_set_wake = ingenic_gpio_irq_set_wake; 2353 jzgc->irq_chip.irq_request_resources = ingenic_gpio_irq_request; 2354 jzgc->irq_chip.irq_release_resources = ingenic_gpio_irq_release; 2355 jzgc->irq_chip.flags = IRQCHIP_MASK_ON_SUSPEND; 2356 2357 girq = &jzgc->gc.irq; 2358 girq->chip = &jzgc->irq_chip; 2359 girq->parent_handler = ingenic_gpio_irq_handler; 2360 girq->num_parents = 1; 2361 girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents), 2362 GFP_KERNEL); 2363 if (!girq->parents) 2364 return -ENOMEM; 2365 girq->parents[0] = jzgc->irq; 2366 girq->default_type = IRQ_TYPE_NONE; 2367 girq->handler = handle_level_irq; 2368 2369 err = devm_gpiochip_add_data(dev, &jzgc->gc, jzgc); 2370 if (err) 2371 return err; 2372 2373 return 0; 2374 } 2375 2376 static int __init ingenic_pinctrl_probe(struct platform_device *pdev) 2377 { 2378 struct device *dev = &pdev->dev; 2379 struct ingenic_pinctrl *jzpc; 2380 struct pinctrl_desc *pctl_desc; 2381 void __iomem *base; 2382 const struct ingenic_chip_info *chip_info; 2383 struct device_node *node; 2384 unsigned int i; 2385 int err; 2386 2387 jzpc = devm_kzalloc(dev, sizeof(*jzpc), GFP_KERNEL); 2388 if (!jzpc) 2389 return -ENOMEM; 2390 2391 base = devm_platform_ioremap_resource(pdev, 0); 2392 if (IS_ERR(base)) 2393 return PTR_ERR(base); 2394 2395 jzpc->map = devm_regmap_init_mmio(dev, base, 2396 &ingenic_pinctrl_regmap_config); 2397 if (IS_ERR(jzpc->map)) { 2398 dev_err(dev, "Failed to create regmap\n"); 2399 return PTR_ERR(jzpc->map); 2400 } 2401 2402 jzpc->dev = dev; 2403 jzpc->info = chip_info = of_device_get_match_data(dev); 2404 2405 pctl_desc = devm_kzalloc(&pdev->dev, sizeof(*pctl_desc), GFP_KERNEL); 2406 if (!pctl_desc) 2407 return -ENOMEM; 2408 2409 /* fill in pinctrl_desc structure */ 2410 pctl_desc->name = dev_name(dev); 2411 pctl_desc->owner = THIS_MODULE; 2412 pctl_desc->pctlops = &ingenic_pctlops; 2413 pctl_desc->pmxops = &ingenic_pmxops; 2414 pctl_desc->confops = &ingenic_confops; 2415 pctl_desc->npins = chip_info->num_chips * PINS_PER_GPIO_CHIP; 2416 pctl_desc->pins = jzpc->pdesc = devm_kcalloc(&pdev->dev, 2417 pctl_desc->npins, sizeof(*jzpc->pdesc), GFP_KERNEL); 2418 if (!jzpc->pdesc) 2419 return -ENOMEM; 2420 2421 for (i = 0; i < pctl_desc->npins; i++) { 2422 jzpc->pdesc[i].number = i; 2423 jzpc->pdesc[i].name = kasprintf(GFP_KERNEL, "P%c%d", 2424 'A' + (i / PINS_PER_GPIO_CHIP), 2425 i % PINS_PER_GPIO_CHIP); 2426 } 2427 2428 jzpc->pctl = devm_pinctrl_register(dev, pctl_desc, jzpc); 2429 if (IS_ERR(jzpc->pctl)) { 2430 dev_err(dev, "Failed to register pinctrl\n"); 2431 return PTR_ERR(jzpc->pctl); 2432 } 2433 2434 for (i = 0; i < chip_info->num_groups; i++) { 2435 const struct group_desc *group = &chip_info->groups[i]; 2436 2437 err = pinctrl_generic_add_group(jzpc->pctl, group->name, 2438 group->pins, group->num_pins, group->data); 2439 if (err < 0) { 2440 dev_err(dev, "Failed to register group %s\n", 2441 group->name); 2442 return err; 2443 } 2444 } 2445 2446 for (i = 0; i < chip_info->num_functions; i++) { 2447 const struct function_desc *func = &chip_info->functions[i]; 2448 2449 err = pinmux_generic_add_function(jzpc->pctl, func->name, 2450 func->group_names, func->num_group_names, 2451 func->data); 2452 if (err < 0) { 2453 dev_err(dev, "Failed to register function %s\n", 2454 func->name); 2455 return err; 2456 } 2457 } 2458 2459 dev_set_drvdata(dev, jzpc->map); 2460 2461 for_each_child_of_node(dev->of_node, node) { 2462 if (of_match_node(ingenic_gpio_of_match, node)) { 2463 err = ingenic_gpio_probe(jzpc, node); 2464 if (err) 2465 return err; 2466 } 2467 } 2468 2469 return 0; 2470 } 2471 2472 static const struct of_device_id ingenic_pinctrl_of_match[] = { 2473 { .compatible = "ingenic,jz4740-pinctrl", .data = &jz4740_chip_info }, 2474 { .compatible = "ingenic,jz4725b-pinctrl", .data = &jz4725b_chip_info }, 2475 { .compatible = "ingenic,jz4760-pinctrl", .data = &jz4760_chip_info }, 2476 { .compatible = "ingenic,jz4760b-pinctrl", .data = &jz4760_chip_info }, 2477 { .compatible = "ingenic,jz4770-pinctrl", .data = &jz4770_chip_info }, 2478 { .compatible = "ingenic,jz4780-pinctrl", .data = &jz4780_chip_info }, 2479 { .compatible = "ingenic,x1000-pinctrl", .data = &x1000_chip_info }, 2480 { .compatible = "ingenic,x1000e-pinctrl", .data = &x1000_chip_info }, 2481 { .compatible = "ingenic,x1500-pinctrl", .data = &x1500_chip_info }, 2482 { .compatible = "ingenic,x1830-pinctrl", .data = &x1830_chip_info }, 2483 {}, 2484 }; 2485 2486 static struct platform_driver ingenic_pinctrl_driver = { 2487 .driver = { 2488 .name = "pinctrl-ingenic", 2489 .of_match_table = ingenic_pinctrl_of_match, 2490 }, 2491 }; 2492 2493 static int __init ingenic_pinctrl_drv_register(void) 2494 { 2495 return platform_driver_probe(&ingenic_pinctrl_driver, 2496 ingenic_pinctrl_probe); 2497 } 2498 subsys_initcall(ingenic_pinctrl_drv_register); 2499