1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Ingenic SoCs pinctrl driver 4 * 5 * Copyright (c) 2017 Paul Cercueil <paul@crapouillou.net> 6 * Copyright (c) 2017, 2019 Paul Boddie <paul@boddie.org.uk> 7 * Copyright (c) 2019, 2020 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> 8 */ 9 10 #include <linux/compiler.h> 11 #include <linux/gpio/driver.h> 12 #include <linux/interrupt.h> 13 #include <linux/io.h> 14 #include <linux/kernel.h> 15 #include <linux/of_device.h> 16 #include <linux/of_irq.h> 17 #include <linux/of_platform.h> 18 #include <linux/pinctrl/pinctrl.h> 19 #include <linux/pinctrl/pinmux.h> 20 #include <linux/pinctrl/pinconf.h> 21 #include <linux/pinctrl/pinconf-generic.h> 22 #include <linux/platform_device.h> 23 #include <linux/regmap.h> 24 #include <linux/slab.h> 25 26 #include "core.h" 27 #include "pinconf.h" 28 #include "pinmux.h" 29 30 #define GPIO_PIN 0x00 31 #define GPIO_MSK 0x20 32 33 #define JZ4730_GPIO_DATA 0x00 34 #define JZ4730_GPIO_GPDIR 0x04 35 #define JZ4730_GPIO_GPPUR 0x0c 36 #define JZ4730_GPIO_GPALR 0x10 37 #define JZ4730_GPIO_GPAUR 0x14 38 #define JZ4730_GPIO_GPIDLR 0x18 39 #define JZ4730_GPIO_GPIDUR 0x1c 40 #define JZ4730_GPIO_GPIER 0x20 41 #define JZ4730_GPIO_GPIMR 0x24 42 #define JZ4730_GPIO_GPFR 0x28 43 44 #define JZ4740_GPIO_DATA 0x10 45 #define JZ4740_GPIO_PULL_DIS 0x30 46 #define JZ4740_GPIO_FUNC 0x40 47 #define JZ4740_GPIO_SELECT 0x50 48 #define JZ4740_GPIO_DIR 0x60 49 #define JZ4740_GPIO_TRIG 0x70 50 #define JZ4740_GPIO_FLAG 0x80 51 52 #define JZ4770_GPIO_INT 0x10 53 #define JZ4770_GPIO_PAT1 0x30 54 #define JZ4770_GPIO_PAT0 0x40 55 #define JZ4770_GPIO_FLAG 0x50 56 #define JZ4770_GPIO_PEN 0x70 57 58 #define X1830_GPIO_PEL 0x110 59 #define X1830_GPIO_PEH 0x120 60 #define X1830_GPIO_SR 0x150 61 #define X1830_GPIO_SMT 0x160 62 63 #define X2000_GPIO_EDG 0x70 64 #define X2000_GPIO_PEPU 0x80 65 #define X2000_GPIO_PEPD 0x90 66 #define X2000_GPIO_SR 0xd0 67 #define X2000_GPIO_SMT 0xe0 68 69 #define REG_SET(x) ((x) + 0x4) 70 #define REG_CLEAR(x) ((x) + 0x8) 71 72 #define REG_PZ_BASE(x) ((x) * 7) 73 #define REG_PZ_GID2LD(x) ((x) * 7 + 0xf0) 74 75 #define GPIO_PULL_DIS 0 76 #define GPIO_PULL_UP 1 77 #define GPIO_PULL_DOWN 2 78 79 #define PINS_PER_GPIO_CHIP 32 80 #define JZ4730_PINS_PER_PAIRED_REG 16 81 82 #define INGENIC_PIN_GROUP_FUNCS(name, id, funcs) \ 83 { \ 84 name, \ 85 id##_pins, \ 86 ARRAY_SIZE(id##_pins), \ 87 funcs, \ 88 } 89 90 #define INGENIC_PIN_GROUP(name, id, func) \ 91 INGENIC_PIN_GROUP_FUNCS(name, id, (void *)(func)) 92 93 enum jz_version { 94 ID_JZ4730, 95 ID_JZ4740, 96 ID_JZ4725B, 97 ID_JZ4750, 98 ID_JZ4755, 99 ID_JZ4760, 100 ID_JZ4770, 101 ID_JZ4775, 102 ID_JZ4780, 103 ID_X1000, 104 ID_X1500, 105 ID_X1830, 106 ID_X2000, 107 }; 108 109 struct ingenic_chip_info { 110 unsigned int num_chips; 111 unsigned int reg_offset; 112 enum jz_version version; 113 114 const struct group_desc *groups; 115 unsigned int num_groups; 116 117 const struct function_desc *functions; 118 unsigned int num_functions; 119 120 const u32 *pull_ups, *pull_downs; 121 }; 122 123 struct ingenic_pinctrl { 124 struct device *dev; 125 struct regmap *map; 126 struct pinctrl_dev *pctl; 127 struct pinctrl_pin_desc *pdesc; 128 129 const struct ingenic_chip_info *info; 130 }; 131 132 struct ingenic_gpio_chip { 133 struct ingenic_pinctrl *jzpc; 134 struct gpio_chip gc; 135 struct irq_chip irq_chip; 136 unsigned int irq, reg_base; 137 }; 138 139 static const u32 jz4730_pull_ups[4] = { 140 0x3fa3320f, 0xf200ffff, 0xffffffff, 0xffffffff, 141 }; 142 143 static const u32 jz4730_pull_downs[4] = { 144 0x00000df0, 0x0dff0000, 0x00000000, 0x00000000, 145 }; 146 147 static int jz4730_mmc_1bit_pins[] = { 0x27, 0x26, 0x22, }; 148 static int jz4730_mmc_4bit_pins[] = { 0x23, 0x24, 0x25, }; 149 static int jz4730_uart0_data_pins[] = { 0x7e, 0x7f, }; 150 static int jz4730_uart1_data_pins[] = { 0x18, 0x19, }; 151 static int jz4730_uart2_data_pins[] = { 0x6f, 0x7d, }; 152 static int jz4730_uart3_data_pins[] = { 0x10, 0x15, }; 153 static int jz4730_uart3_hwflow_pins[] = { 0x11, 0x17, }; 154 static int jz4730_lcd_8bit_pins[] = { 155 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 156 0x3a, 0x39, 0x38, 157 }; 158 static int jz4730_lcd_16bit_pins[] = { 159 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 160 }; 161 static int jz4730_lcd_special_pins[] = { 0x3d, 0x3c, 0x3e, 0x3f, }; 162 static int jz4730_lcd_generic_pins[] = { 0x3b, }; 163 static int jz4730_nand_cs1_pins[] = { 0x53, }; 164 static int jz4730_nand_cs2_pins[] = { 0x54, }; 165 static int jz4730_nand_cs3_pins[] = { 0x55, }; 166 static int jz4730_nand_cs4_pins[] = { 0x56, }; 167 static int jz4730_nand_cs5_pins[] = { 0x57, }; 168 static int jz4730_pwm_pwm0_pins[] = { 0x5e, }; 169 static int jz4730_pwm_pwm1_pins[] = { 0x5f, }; 170 171 static u8 jz4730_lcd_8bit_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, }; 172 173 static const struct group_desc jz4730_groups[] = { 174 INGENIC_PIN_GROUP("mmc-1bit", jz4730_mmc_1bit, 1), 175 INGENIC_PIN_GROUP("mmc-4bit", jz4730_mmc_4bit, 1), 176 INGENIC_PIN_GROUP("uart0-data", jz4730_uart0_data, 1), 177 INGENIC_PIN_GROUP("uart1-data", jz4730_uart1_data, 1), 178 INGENIC_PIN_GROUP("uart2-data", jz4730_uart2_data, 1), 179 INGENIC_PIN_GROUP("uart3-data", jz4730_uart3_data, 1), 180 INGENIC_PIN_GROUP("uart3-hwflow", jz4730_uart3_hwflow, 1), 181 INGENIC_PIN_GROUP_FUNCS("lcd-8bit", jz4730_lcd_8bit, jz4730_lcd_8bit_funcs), 182 INGENIC_PIN_GROUP("lcd-16bit", jz4730_lcd_16bit, 1), 183 INGENIC_PIN_GROUP("lcd-special", jz4730_lcd_special, 1), 184 INGENIC_PIN_GROUP("lcd-generic", jz4730_lcd_generic, 1), 185 INGENIC_PIN_GROUP("nand-cs1", jz4730_nand_cs1, 1), 186 INGENIC_PIN_GROUP("nand-cs2", jz4730_nand_cs2, 1), 187 INGENIC_PIN_GROUP("nand-cs3", jz4730_nand_cs3, 1), 188 INGENIC_PIN_GROUP("nand-cs4", jz4730_nand_cs4, 1), 189 INGENIC_PIN_GROUP("nand-cs5", jz4730_nand_cs5, 1), 190 INGENIC_PIN_GROUP("pwm0", jz4730_pwm_pwm0, 1), 191 INGENIC_PIN_GROUP("pwm1", jz4730_pwm_pwm1, 1), 192 }; 193 194 static const char *jz4730_mmc_groups[] = { "mmc-1bit", "mmc-4bit", }; 195 static const char *jz4730_uart0_groups[] = { "uart0-data", }; 196 static const char *jz4730_uart1_groups[] = { "uart1-data", }; 197 static const char *jz4730_uart2_groups[] = { "uart2-data", }; 198 static const char *jz4730_uart3_groups[] = { "uart3-data", "uart3-hwflow", }; 199 static const char *jz4730_lcd_groups[] = { 200 "lcd-8bit", "lcd-16bit", "lcd-special", "lcd-generic", 201 }; 202 static const char *jz4730_nand_groups[] = { 203 "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", "nand-cs5", 204 }; 205 static const char *jz4730_pwm0_groups[] = { "pwm0", }; 206 static const char *jz4730_pwm1_groups[] = { "pwm1", }; 207 208 static const struct function_desc jz4730_functions[] = { 209 { "mmc", jz4730_mmc_groups, ARRAY_SIZE(jz4730_mmc_groups), }, 210 { "uart0", jz4730_uart0_groups, ARRAY_SIZE(jz4730_uart0_groups), }, 211 { "uart1", jz4730_uart1_groups, ARRAY_SIZE(jz4730_uart1_groups), }, 212 { "uart2", jz4730_uart2_groups, ARRAY_SIZE(jz4730_uart2_groups), }, 213 { "uart3", jz4730_uart3_groups, ARRAY_SIZE(jz4730_uart3_groups), }, 214 { "lcd", jz4730_lcd_groups, ARRAY_SIZE(jz4730_lcd_groups), }, 215 { "nand", jz4730_nand_groups, ARRAY_SIZE(jz4730_nand_groups), }, 216 { "pwm0", jz4730_pwm0_groups, ARRAY_SIZE(jz4730_pwm0_groups), }, 217 { "pwm1", jz4730_pwm1_groups, ARRAY_SIZE(jz4730_pwm1_groups), }, 218 }; 219 220 static const struct ingenic_chip_info jz4730_chip_info = { 221 .num_chips = 4, 222 .reg_offset = 0x30, 223 .version = ID_JZ4730, 224 .groups = jz4730_groups, 225 .num_groups = ARRAY_SIZE(jz4730_groups), 226 .functions = jz4730_functions, 227 .num_functions = ARRAY_SIZE(jz4730_functions), 228 .pull_ups = jz4730_pull_ups, 229 .pull_downs = jz4730_pull_downs, 230 }; 231 232 static const u32 jz4740_pull_ups[4] = { 233 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 234 }; 235 236 static const u32 jz4740_pull_downs[4] = { 237 0x00000000, 0x00000000, 0x00000000, 0x00000000, 238 }; 239 240 static int jz4740_mmc_1bit_pins[] = { 0x69, 0x68, 0x6a, }; 241 static int jz4740_mmc_4bit_pins[] = { 0x6b, 0x6c, 0x6d, }; 242 static int jz4740_uart0_data_pins[] = { 0x7a, 0x79, }; 243 static int jz4740_uart0_hwflow_pins[] = { 0x7e, 0x7f, }; 244 static int jz4740_uart1_data_pins[] = { 0x7e, 0x7f, }; 245 static int jz4740_lcd_8bit_pins[] = { 246 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 247 0x52, 0x53, 0x54, 248 }; 249 static int jz4740_lcd_16bit_pins[] = { 250 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, 251 }; 252 static int jz4740_lcd_18bit_pins[] = { 0x50, 0x51, }; 253 static int jz4740_lcd_special_pins[] = { 0x31, 0x32, 0x56, 0x57, }; 254 static int jz4740_lcd_generic_pins[] = { 0x55, }; 255 static int jz4740_nand_cs1_pins[] = { 0x39, }; 256 static int jz4740_nand_cs2_pins[] = { 0x3a, }; 257 static int jz4740_nand_cs3_pins[] = { 0x3b, }; 258 static int jz4740_nand_cs4_pins[] = { 0x3c, }; 259 static int jz4740_nand_fre_fwe_pins[] = { 0x5c, 0x5d, }; 260 static int jz4740_pwm_pwm0_pins[] = { 0x77, }; 261 static int jz4740_pwm_pwm1_pins[] = { 0x78, }; 262 static int jz4740_pwm_pwm2_pins[] = { 0x79, }; 263 static int jz4740_pwm_pwm3_pins[] = { 0x7a, }; 264 static int jz4740_pwm_pwm4_pins[] = { 0x7b, }; 265 static int jz4740_pwm_pwm5_pins[] = { 0x7c, }; 266 static int jz4740_pwm_pwm6_pins[] = { 0x7e, }; 267 static int jz4740_pwm_pwm7_pins[] = { 0x7f, }; 268 269 static const struct group_desc jz4740_groups[] = { 270 INGENIC_PIN_GROUP("mmc-1bit", jz4740_mmc_1bit, 0), 271 INGENIC_PIN_GROUP("mmc-4bit", jz4740_mmc_4bit, 0), 272 INGENIC_PIN_GROUP("uart0-data", jz4740_uart0_data, 1), 273 INGENIC_PIN_GROUP("uart0-hwflow", jz4740_uart0_hwflow, 1), 274 INGENIC_PIN_GROUP("uart1-data", jz4740_uart1_data, 2), 275 INGENIC_PIN_GROUP("lcd-8bit", jz4740_lcd_8bit, 0), 276 INGENIC_PIN_GROUP("lcd-16bit", jz4740_lcd_16bit, 0), 277 INGENIC_PIN_GROUP("lcd-18bit", jz4740_lcd_18bit, 0), 278 INGENIC_PIN_GROUP("lcd-special", jz4740_lcd_special, 0), 279 INGENIC_PIN_GROUP("lcd-generic", jz4740_lcd_generic, 0), 280 INGENIC_PIN_GROUP("nand-cs1", jz4740_nand_cs1, 0), 281 INGENIC_PIN_GROUP("nand-cs2", jz4740_nand_cs2, 0), 282 INGENIC_PIN_GROUP("nand-cs3", jz4740_nand_cs3, 0), 283 INGENIC_PIN_GROUP("nand-cs4", jz4740_nand_cs4, 0), 284 INGENIC_PIN_GROUP("nand-fre-fwe", jz4740_nand_fre_fwe, 0), 285 INGENIC_PIN_GROUP("pwm0", jz4740_pwm_pwm0, 0), 286 INGENIC_PIN_GROUP("pwm1", jz4740_pwm_pwm1, 0), 287 INGENIC_PIN_GROUP("pwm2", jz4740_pwm_pwm2, 0), 288 INGENIC_PIN_GROUP("pwm3", jz4740_pwm_pwm3, 0), 289 INGENIC_PIN_GROUP("pwm4", jz4740_pwm_pwm4, 0), 290 INGENIC_PIN_GROUP("pwm5", jz4740_pwm_pwm5, 0), 291 INGENIC_PIN_GROUP("pwm6", jz4740_pwm_pwm6, 0), 292 INGENIC_PIN_GROUP("pwm7", jz4740_pwm_pwm7, 0), 293 }; 294 295 static const char *jz4740_mmc_groups[] = { "mmc-1bit", "mmc-4bit", }; 296 static const char *jz4740_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; 297 static const char *jz4740_uart1_groups[] = { "uart1-data", }; 298 static const char *jz4740_lcd_groups[] = { 299 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-special", "lcd-generic", 300 }; 301 static const char *jz4740_nand_groups[] = { 302 "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", "nand-fre-fwe", 303 }; 304 static const char *jz4740_pwm0_groups[] = { "pwm0", }; 305 static const char *jz4740_pwm1_groups[] = { "pwm1", }; 306 static const char *jz4740_pwm2_groups[] = { "pwm2", }; 307 static const char *jz4740_pwm3_groups[] = { "pwm3", }; 308 static const char *jz4740_pwm4_groups[] = { "pwm4", }; 309 static const char *jz4740_pwm5_groups[] = { "pwm5", }; 310 static const char *jz4740_pwm6_groups[] = { "pwm6", }; 311 static const char *jz4740_pwm7_groups[] = { "pwm7", }; 312 313 static const struct function_desc jz4740_functions[] = { 314 { "mmc", jz4740_mmc_groups, ARRAY_SIZE(jz4740_mmc_groups), }, 315 { "uart0", jz4740_uart0_groups, ARRAY_SIZE(jz4740_uart0_groups), }, 316 { "uart1", jz4740_uart1_groups, ARRAY_SIZE(jz4740_uart1_groups), }, 317 { "lcd", jz4740_lcd_groups, ARRAY_SIZE(jz4740_lcd_groups), }, 318 { "nand", jz4740_nand_groups, ARRAY_SIZE(jz4740_nand_groups), }, 319 { "pwm0", jz4740_pwm0_groups, ARRAY_SIZE(jz4740_pwm0_groups), }, 320 { "pwm1", jz4740_pwm1_groups, ARRAY_SIZE(jz4740_pwm1_groups), }, 321 { "pwm2", jz4740_pwm2_groups, ARRAY_SIZE(jz4740_pwm2_groups), }, 322 { "pwm3", jz4740_pwm3_groups, ARRAY_SIZE(jz4740_pwm3_groups), }, 323 { "pwm4", jz4740_pwm4_groups, ARRAY_SIZE(jz4740_pwm4_groups), }, 324 { "pwm5", jz4740_pwm5_groups, ARRAY_SIZE(jz4740_pwm5_groups), }, 325 { "pwm6", jz4740_pwm6_groups, ARRAY_SIZE(jz4740_pwm6_groups), }, 326 { "pwm7", jz4740_pwm7_groups, ARRAY_SIZE(jz4740_pwm7_groups), }, 327 }; 328 329 static const struct ingenic_chip_info jz4740_chip_info = { 330 .num_chips = 4, 331 .reg_offset = 0x100, 332 .version = ID_JZ4740, 333 .groups = jz4740_groups, 334 .num_groups = ARRAY_SIZE(jz4740_groups), 335 .functions = jz4740_functions, 336 .num_functions = ARRAY_SIZE(jz4740_functions), 337 .pull_ups = jz4740_pull_ups, 338 .pull_downs = jz4740_pull_downs, 339 }; 340 341 static int jz4725b_mmc0_1bit_pins[] = { 0x48, 0x49, 0x5c, }; 342 static int jz4725b_mmc0_4bit_pins[] = { 0x5d, 0x5b, 0x56, }; 343 static int jz4725b_mmc1_1bit_pins[] = { 0x7a, 0x7b, 0x7c, }; 344 static int jz4725b_mmc1_4bit_pins[] = { 0x7d, 0x7e, 0x7f, }; 345 static int jz4725b_uart_data_pins[] = { 0x4c, 0x4d, }; 346 static int jz4725b_lcd_8bit_pins[] = { 347 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 348 0x72, 0x73, 0x74, 349 }; 350 static int jz4725b_lcd_16bit_pins[] = { 351 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 352 }; 353 static int jz4725b_lcd_18bit_pins[] = { 0x70, 0x71, }; 354 static int jz4725b_lcd_24bit_pins[] = { 0x76, 0x77, 0x78, 0x79, }; 355 static int jz4725b_lcd_special_pins[] = { 0x76, 0x77, 0x78, 0x79, }; 356 static int jz4725b_lcd_generic_pins[] = { 0x75, }; 357 static int jz4725b_nand_cs1_pins[] = { 0x55, }; 358 static int jz4725b_nand_cs2_pins[] = { 0x56, }; 359 static int jz4725b_nand_cs3_pins[] = { 0x57, }; 360 static int jz4725b_nand_cs4_pins[] = { 0x58, }; 361 static int jz4725b_nand_cle_ale_pins[] = { 0x48, 0x49 }; 362 static int jz4725b_nand_fre_fwe_pins[] = { 0x5c, 0x5d }; 363 static int jz4725b_pwm_pwm0_pins[] = { 0x4a, }; 364 static int jz4725b_pwm_pwm1_pins[] = { 0x4b, }; 365 static int jz4725b_pwm_pwm2_pins[] = { 0x4c, }; 366 static int jz4725b_pwm_pwm3_pins[] = { 0x4d, }; 367 static int jz4725b_pwm_pwm4_pins[] = { 0x4e, }; 368 static int jz4725b_pwm_pwm5_pins[] = { 0x4f, }; 369 370 static u8 jz4725b_mmc0_4bit_funcs[] = { 1, 0, 1, }; 371 372 static const struct group_desc jz4725b_groups[] = { 373 INGENIC_PIN_GROUP("mmc0-1bit", jz4725b_mmc0_1bit, 1), 374 INGENIC_PIN_GROUP_FUNCS("mmc0-4bit", jz4725b_mmc0_4bit, 375 jz4725b_mmc0_4bit_funcs), 376 INGENIC_PIN_GROUP("mmc1-1bit", jz4725b_mmc1_1bit, 0), 377 INGENIC_PIN_GROUP("mmc1-4bit", jz4725b_mmc1_4bit, 0), 378 INGENIC_PIN_GROUP("uart-data", jz4725b_uart_data, 1), 379 INGENIC_PIN_GROUP("lcd-8bit", jz4725b_lcd_8bit, 0), 380 INGENIC_PIN_GROUP("lcd-16bit", jz4725b_lcd_16bit, 0), 381 INGENIC_PIN_GROUP("lcd-18bit", jz4725b_lcd_18bit, 0), 382 INGENIC_PIN_GROUP("lcd-24bit", jz4725b_lcd_24bit, 1), 383 INGENIC_PIN_GROUP("lcd-special", jz4725b_lcd_special, 0), 384 INGENIC_PIN_GROUP("lcd-generic", jz4725b_lcd_generic, 0), 385 INGENIC_PIN_GROUP("nand-cs1", jz4725b_nand_cs1, 0), 386 INGENIC_PIN_GROUP("nand-cs2", jz4725b_nand_cs2, 0), 387 INGENIC_PIN_GROUP("nand-cs3", jz4725b_nand_cs3, 0), 388 INGENIC_PIN_GROUP("nand-cs4", jz4725b_nand_cs4, 0), 389 INGENIC_PIN_GROUP("nand-cle-ale", jz4725b_nand_cle_ale, 0), 390 INGENIC_PIN_GROUP("nand-fre-fwe", jz4725b_nand_fre_fwe, 0), 391 INGENIC_PIN_GROUP("pwm0", jz4725b_pwm_pwm0, 0), 392 INGENIC_PIN_GROUP("pwm1", jz4725b_pwm_pwm1, 0), 393 INGENIC_PIN_GROUP("pwm2", jz4725b_pwm_pwm2, 0), 394 INGENIC_PIN_GROUP("pwm3", jz4725b_pwm_pwm3, 0), 395 INGENIC_PIN_GROUP("pwm4", jz4725b_pwm_pwm4, 0), 396 INGENIC_PIN_GROUP("pwm5", jz4725b_pwm_pwm5, 0), 397 }; 398 399 static const char *jz4725b_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", }; 400 static const char *jz4725b_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", }; 401 static const char *jz4725b_uart_groups[] = { "uart-data", }; 402 static const char *jz4725b_lcd_groups[] = { 403 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit", 404 "lcd-special", "lcd-generic", 405 }; 406 static const char *jz4725b_nand_groups[] = { 407 "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", 408 "nand-cle-ale", "nand-fre-fwe", 409 }; 410 static const char *jz4725b_pwm0_groups[] = { "pwm0", }; 411 static const char *jz4725b_pwm1_groups[] = { "pwm1", }; 412 static const char *jz4725b_pwm2_groups[] = { "pwm2", }; 413 static const char *jz4725b_pwm3_groups[] = { "pwm3", }; 414 static const char *jz4725b_pwm4_groups[] = { "pwm4", }; 415 static const char *jz4725b_pwm5_groups[] = { "pwm5", }; 416 417 static const struct function_desc jz4725b_functions[] = { 418 { "mmc0", jz4725b_mmc0_groups, ARRAY_SIZE(jz4725b_mmc0_groups), }, 419 { "mmc1", jz4725b_mmc1_groups, ARRAY_SIZE(jz4725b_mmc1_groups), }, 420 { "uart", jz4725b_uart_groups, ARRAY_SIZE(jz4725b_uart_groups), }, 421 { "nand", jz4725b_nand_groups, ARRAY_SIZE(jz4725b_nand_groups), }, 422 { "pwm0", jz4725b_pwm0_groups, ARRAY_SIZE(jz4725b_pwm0_groups), }, 423 { "pwm1", jz4725b_pwm1_groups, ARRAY_SIZE(jz4725b_pwm1_groups), }, 424 { "pwm2", jz4725b_pwm2_groups, ARRAY_SIZE(jz4725b_pwm2_groups), }, 425 { "pwm3", jz4725b_pwm3_groups, ARRAY_SIZE(jz4725b_pwm3_groups), }, 426 { "pwm4", jz4725b_pwm4_groups, ARRAY_SIZE(jz4725b_pwm4_groups), }, 427 { "pwm5", jz4725b_pwm5_groups, ARRAY_SIZE(jz4725b_pwm5_groups), }, 428 { "lcd", jz4725b_lcd_groups, ARRAY_SIZE(jz4725b_lcd_groups), }, 429 }; 430 431 static const struct ingenic_chip_info jz4725b_chip_info = { 432 .num_chips = 4, 433 .reg_offset = 0x100, 434 .version = ID_JZ4725B, 435 .groups = jz4725b_groups, 436 .num_groups = ARRAY_SIZE(jz4725b_groups), 437 .functions = jz4725b_functions, 438 .num_functions = ARRAY_SIZE(jz4725b_functions), 439 .pull_ups = jz4740_pull_ups, 440 .pull_downs = jz4740_pull_downs, 441 }; 442 443 static const u32 jz4750_pull_ups[6] = { 444 0xffffffff, 0xffffffff, 0x3fffffff, 0x7fffffff, 0x1fff3fff, 0x00ffffff, 445 }; 446 447 static const u32 jz4750_pull_downs[6] = { 448 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 449 }; 450 451 static int jz4750_uart0_data_pins[] = { 0xa4, 0xa5, }; 452 static int jz4750_uart0_hwflow_pins[] = { 0xa6, 0xa7, }; 453 static int jz4750_uart1_data_pins[] = { 0x90, 0x91, }; 454 static int jz4750_uart1_hwflow_pins[] = { 0x92, 0x93, }; 455 static int jz4750_uart2_data_pins[] = { 0x9b, 0x9a, }; 456 static int jz4750_uart3_data_pins[] = { 0xb0, 0xb1, }; 457 static int jz4750_uart3_hwflow_pins[] = { 0xb2, 0xb3, }; 458 static int jz4750_mmc0_1bit_pins[] = { 0xa8, 0xa9, 0xa0, }; 459 static int jz4750_mmc0_4bit_pins[] = { 0xa1, 0xa2, 0xa3, }; 460 static int jz4750_mmc0_8bit_pins[] = { 0xa4, 0xa5, 0xa6, 0xa7, }; 461 static int jz4750_mmc1_1bit_pins[] = { 0xae, 0xaf, 0xaa, }; 462 static int jz4750_mmc1_4bit_pins[] = { 0xab, 0xac, 0xad, }; 463 static int jz4750_i2c_pins[] = { 0x8c, 0x8d, }; 464 static int jz4750_cim_pins[] = { 465 0x89, 0x8b, 0x8a, 0x88, 466 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 467 }; 468 static int jz4750_lcd_8bit_pins[] = { 469 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 470 0x72, 0x73, 0x74, 471 }; 472 static int jz4750_lcd_16bit_pins[] = { 473 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 474 }; 475 static int jz4750_lcd_18bit_pins[] = { 0x70, 0x71, }; 476 static int jz4750_lcd_24bit_pins[] = { 0x76, 0x77, 0x78, 0x79, 0xb2, 0xb3, }; 477 static int jz4750_lcd_special_pins[] = { 0x76, 0x77, 0x78, 0x79, }; 478 static int jz4750_lcd_generic_pins[] = { 0x75, }; 479 static int jz4750_nand_cs1_pins[] = { 0x55, }; 480 static int jz4750_nand_cs2_pins[] = { 0x56, }; 481 static int jz4750_nand_cs3_pins[] = { 0x57, }; 482 static int jz4750_nand_cs4_pins[] = { 0x58, }; 483 static int jz4750_nand_fre_fwe_pins[] = { 0x5c, 0x5d, }; 484 static int jz4750_pwm_pwm0_pins[] = { 0x94, }; 485 static int jz4750_pwm_pwm1_pins[] = { 0x95, }; 486 static int jz4750_pwm_pwm2_pins[] = { 0x96, }; 487 static int jz4750_pwm_pwm3_pins[] = { 0x97, }; 488 static int jz4750_pwm_pwm4_pins[] = { 0x98, }; 489 static int jz4750_pwm_pwm5_pins[] = { 0x99, }; 490 491 static const struct group_desc jz4750_groups[] = { 492 INGENIC_PIN_GROUP("uart0-data", jz4750_uart0_data, 1), 493 INGENIC_PIN_GROUP("uart0-hwflow", jz4750_uart0_hwflow, 1), 494 INGENIC_PIN_GROUP("uart1-data", jz4750_uart1_data, 0), 495 INGENIC_PIN_GROUP("uart1-hwflow", jz4750_uart1_hwflow, 0), 496 INGENIC_PIN_GROUP("uart2-data", jz4750_uart2_data, 1), 497 INGENIC_PIN_GROUP("uart3-data", jz4750_uart3_data, 0), 498 INGENIC_PIN_GROUP("uart3-hwflow", jz4750_uart3_hwflow, 0), 499 INGENIC_PIN_GROUP("mmc0-1bit", jz4750_mmc0_1bit, 0), 500 INGENIC_PIN_GROUP("mmc0-4bit", jz4750_mmc0_4bit, 0), 501 INGENIC_PIN_GROUP("mmc0-8bit", jz4750_mmc0_8bit, 0), 502 INGENIC_PIN_GROUP("mmc1-1bit", jz4750_mmc1_1bit, 0), 503 INGENIC_PIN_GROUP("mmc1-4bit", jz4750_mmc1_4bit, 0), 504 INGENIC_PIN_GROUP("i2c-data", jz4750_i2c, 0), 505 INGENIC_PIN_GROUP("cim-data", jz4750_cim, 0), 506 INGENIC_PIN_GROUP("lcd-8bit", jz4750_lcd_8bit, 0), 507 INGENIC_PIN_GROUP("lcd-16bit", jz4750_lcd_16bit, 0), 508 INGENIC_PIN_GROUP("lcd-18bit", jz4750_lcd_18bit, 0), 509 INGENIC_PIN_GROUP("lcd-24bit", jz4750_lcd_24bit, 1), 510 INGENIC_PIN_GROUP("lcd-special", jz4750_lcd_special, 0), 511 INGENIC_PIN_GROUP("lcd-generic", jz4750_lcd_generic, 0), 512 INGENIC_PIN_GROUP("nand-cs1", jz4750_nand_cs1, 0), 513 INGENIC_PIN_GROUP("nand-cs2", jz4750_nand_cs2, 0), 514 INGENIC_PIN_GROUP("nand-cs3", jz4750_nand_cs3, 0), 515 INGENIC_PIN_GROUP("nand-cs4", jz4750_nand_cs4, 0), 516 INGENIC_PIN_GROUP("nand-fre-fwe", jz4750_nand_fre_fwe, 0), 517 INGENIC_PIN_GROUP("pwm0", jz4750_pwm_pwm0, 0), 518 INGENIC_PIN_GROUP("pwm1", jz4750_pwm_pwm1, 0), 519 INGENIC_PIN_GROUP("pwm2", jz4750_pwm_pwm2, 0), 520 INGENIC_PIN_GROUP("pwm3", jz4750_pwm_pwm3, 0), 521 INGENIC_PIN_GROUP("pwm4", jz4750_pwm_pwm4, 0), 522 INGENIC_PIN_GROUP("pwm5", jz4750_pwm_pwm5, 0), 523 }; 524 525 static const char *jz4750_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; 526 static const char *jz4750_uart1_groups[] = { "uart1-data", "uart1-hwflow", }; 527 static const char *jz4750_uart2_groups[] = { "uart2-data", }; 528 static const char *jz4750_uart3_groups[] = { "uart3-data", "uart3-hwflow", }; 529 static const char *jz4750_mmc0_groups[] = { 530 "mmc0-1bit", "mmc0-4bit", "mmc0-8bit", 531 }; 532 static const char *jz4750_mmc1_groups[] = { "mmc0-1bit", "mmc0-4bit", }; 533 static const char *jz4750_i2c_groups[] = { "i2c-data", }; 534 static const char *jz4750_cim_groups[] = { "cim-data", }; 535 static const char *jz4750_lcd_groups[] = { 536 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit", 537 "lcd-special", "lcd-generic", 538 }; 539 static const char *jz4750_nand_groups[] = { 540 "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", "nand-fre-fwe", 541 }; 542 static const char *jz4750_pwm0_groups[] = { "pwm0", }; 543 static const char *jz4750_pwm1_groups[] = { "pwm1", }; 544 static const char *jz4750_pwm2_groups[] = { "pwm2", }; 545 static const char *jz4750_pwm3_groups[] = { "pwm3", }; 546 static const char *jz4750_pwm4_groups[] = { "pwm4", }; 547 static const char *jz4750_pwm5_groups[] = { "pwm5", }; 548 549 static const struct function_desc jz4750_functions[] = { 550 { "uart0", jz4750_uart0_groups, ARRAY_SIZE(jz4750_uart0_groups), }, 551 { "uart1", jz4750_uart1_groups, ARRAY_SIZE(jz4750_uart1_groups), }, 552 { "uart2", jz4750_uart2_groups, ARRAY_SIZE(jz4750_uart2_groups), }, 553 { "uart3", jz4750_uart3_groups, ARRAY_SIZE(jz4750_uart3_groups), }, 554 { "mmc0", jz4750_mmc0_groups, ARRAY_SIZE(jz4750_mmc0_groups), }, 555 { "mmc1", jz4750_mmc1_groups, ARRAY_SIZE(jz4750_mmc1_groups), }, 556 { "i2c", jz4750_i2c_groups, ARRAY_SIZE(jz4750_i2c_groups), }, 557 { "cim", jz4750_cim_groups, ARRAY_SIZE(jz4750_cim_groups), }, 558 { "lcd", jz4750_lcd_groups, ARRAY_SIZE(jz4750_lcd_groups), }, 559 { "nand", jz4750_nand_groups, ARRAY_SIZE(jz4750_nand_groups), }, 560 { "pwm0", jz4750_pwm0_groups, ARRAY_SIZE(jz4750_pwm0_groups), }, 561 { "pwm1", jz4750_pwm1_groups, ARRAY_SIZE(jz4750_pwm1_groups), }, 562 { "pwm2", jz4750_pwm2_groups, ARRAY_SIZE(jz4750_pwm2_groups), }, 563 { "pwm3", jz4750_pwm3_groups, ARRAY_SIZE(jz4750_pwm3_groups), }, 564 { "pwm4", jz4750_pwm4_groups, ARRAY_SIZE(jz4750_pwm4_groups), }, 565 { "pwm5", jz4750_pwm5_groups, ARRAY_SIZE(jz4750_pwm5_groups), }, 566 }; 567 568 static const struct ingenic_chip_info jz4750_chip_info = { 569 .num_chips = 6, 570 .reg_offset = 0x100, 571 .version = ID_JZ4750, 572 .groups = jz4750_groups, 573 .num_groups = ARRAY_SIZE(jz4750_groups), 574 .functions = jz4750_functions, 575 .num_functions = ARRAY_SIZE(jz4750_functions), 576 .pull_ups = jz4750_pull_ups, 577 .pull_downs = jz4750_pull_downs, 578 }; 579 580 static const u32 jz4755_pull_ups[6] = { 581 0xffffffff, 0xffffffff, 0x0fffffff, 0xffffffff, 0x33dc3fff, 0x0000fc00, 582 }; 583 584 static const u32 jz4755_pull_downs[6] = { 585 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 586 }; 587 588 static int jz4755_uart0_data_pins[] = { 0x7c, 0x7d, }; 589 static int jz4755_uart0_hwflow_pins[] = { 0x7e, 0x7f, }; 590 static int jz4755_uart1_data_pins[] = { 0x97, 0x99, }; 591 static int jz4755_uart2_data_pins[] = { 0x9f, }; 592 static int jz4755_mmc0_1bit_pins[] = { 0x2f, 0x50, 0x5c, }; 593 static int jz4755_mmc0_4bit_pins[] = { 0x5d, 0x5b, 0x51, }; 594 static int jz4755_mmc1_1bit_pins[] = { 0x3a, 0x3d, 0x3c, }; 595 static int jz4755_mmc1_4bit_pins[] = { 0x3b, 0x3e, 0x3f, }; 596 static int jz4755_i2c_pins[] = { 0x8c, 0x8d, }; 597 static int jz4755_cim_pins[] = { 598 0x89, 0x8b, 0x8a, 0x88, 599 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 600 }; 601 static int jz4755_lcd_8bit_pins[] = { 602 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 603 0x72, 0x73, 0x74, 604 }; 605 static int jz4755_lcd_16bit_pins[] = { 606 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 607 }; 608 static int jz4755_lcd_18bit_pins[] = { 0x70, 0x71, }; 609 static int jz4755_lcd_24bit_pins[] = { 0x76, 0x77, 0x78, 0x79, 0x7a, 0x7b, }; 610 static int jz4755_lcd_special_pins[] = { 0x76, 0x77, 0x78, 0x79, }; 611 static int jz4755_lcd_generic_pins[] = { 0x75, }; 612 static int jz4755_nand_cs1_pins[] = { 0x55, }; 613 static int jz4755_nand_cs2_pins[] = { 0x56, }; 614 static int jz4755_nand_cs3_pins[] = { 0x57, }; 615 static int jz4755_nand_cs4_pins[] = { 0x58, }; 616 static int jz4755_nand_fre_fwe_pins[] = { 0x5c, 0x5d, }; 617 static int jz4755_pwm_pwm0_pins[] = { 0x94, }; 618 static int jz4755_pwm_pwm1_pins[] = { 0xab, }; 619 static int jz4755_pwm_pwm2_pins[] = { 0x96, }; 620 static int jz4755_pwm_pwm3_pins[] = { 0x97, }; 621 static int jz4755_pwm_pwm4_pins[] = { 0x98, }; 622 static int jz4755_pwm_pwm5_pins[] = { 0x99, }; 623 624 static u8 jz4755_mmc0_1bit_funcs[] = { 2, 2, 1, }; 625 static u8 jz4755_mmc0_4bit_funcs[] = { 1, 0, 1, }; 626 static u8 jz4755_lcd_24bit_funcs[] = { 1, 1, 1, 1, 0, 0, }; 627 628 static const struct group_desc jz4755_groups[] = { 629 INGENIC_PIN_GROUP("uart0-data", jz4755_uart0_data, 0), 630 INGENIC_PIN_GROUP("uart0-hwflow", jz4755_uart0_hwflow, 0), 631 INGENIC_PIN_GROUP("uart1-data", jz4755_uart1_data, 0), 632 INGENIC_PIN_GROUP("uart2-data", jz4755_uart2_data, 1), 633 INGENIC_PIN_GROUP_FUNCS("mmc0-1bit", jz4755_mmc0_1bit, 634 jz4755_mmc0_1bit_funcs), 635 INGENIC_PIN_GROUP_FUNCS("mmc0-4bit", jz4755_mmc0_4bit, 636 jz4755_mmc0_4bit_funcs), 637 INGENIC_PIN_GROUP("mmc1-1bit", jz4755_mmc1_1bit, 1), 638 INGENIC_PIN_GROUP("mmc1-4bit", jz4755_mmc1_4bit, 1), 639 INGENIC_PIN_GROUP("i2c-data", jz4755_i2c, 0), 640 INGENIC_PIN_GROUP("cim-data", jz4755_cim, 0), 641 INGENIC_PIN_GROUP("lcd-8bit", jz4755_lcd_8bit, 0), 642 INGENIC_PIN_GROUP("lcd-16bit", jz4755_lcd_16bit, 0), 643 INGENIC_PIN_GROUP("lcd-18bit", jz4755_lcd_18bit, 0), 644 INGENIC_PIN_GROUP_FUNCS("lcd-24bit", jz4755_lcd_24bit, 645 jz4755_lcd_24bit_funcs), 646 INGENIC_PIN_GROUP("lcd-special", jz4755_lcd_special, 0), 647 INGENIC_PIN_GROUP("lcd-generic", jz4755_lcd_generic, 0), 648 INGENIC_PIN_GROUP("nand-cs1", jz4755_nand_cs1, 0), 649 INGENIC_PIN_GROUP("nand-cs2", jz4755_nand_cs2, 0), 650 INGENIC_PIN_GROUP("nand-cs3", jz4755_nand_cs3, 0), 651 INGENIC_PIN_GROUP("nand-cs4", jz4755_nand_cs4, 0), 652 INGENIC_PIN_GROUP("nand-fre-fwe", jz4755_nand_fre_fwe, 0), 653 INGENIC_PIN_GROUP("pwm0", jz4755_pwm_pwm0, 0), 654 INGENIC_PIN_GROUP("pwm1", jz4755_pwm_pwm1, 1), 655 INGENIC_PIN_GROUP("pwm2", jz4755_pwm_pwm2, 0), 656 INGENIC_PIN_GROUP("pwm3", jz4755_pwm_pwm3, 0), 657 INGENIC_PIN_GROUP("pwm4", jz4755_pwm_pwm4, 0), 658 INGENIC_PIN_GROUP("pwm5", jz4755_pwm_pwm5, 0), 659 }; 660 661 static const char *jz4755_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; 662 static const char *jz4755_uart1_groups[] = { "uart1-data", }; 663 static const char *jz4755_uart2_groups[] = { "uart2-data", }; 664 static const char *jz4755_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", }; 665 static const char *jz4755_mmc1_groups[] = { "mmc0-1bit", "mmc0-4bit", }; 666 static const char *jz4755_i2c_groups[] = { "i2c-data", }; 667 static const char *jz4755_cim_groups[] = { "cim-data", }; 668 static const char *jz4755_lcd_groups[] = { 669 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit", 670 "lcd-special", "lcd-generic", 671 }; 672 static const char *jz4755_nand_groups[] = { 673 "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", "nand-fre-fwe", 674 }; 675 static const char *jz4755_pwm0_groups[] = { "pwm0", }; 676 static const char *jz4755_pwm1_groups[] = { "pwm1", }; 677 static const char *jz4755_pwm2_groups[] = { "pwm2", }; 678 static const char *jz4755_pwm3_groups[] = { "pwm3", }; 679 static const char *jz4755_pwm4_groups[] = { "pwm4", }; 680 static const char *jz4755_pwm5_groups[] = { "pwm5", }; 681 682 static const struct function_desc jz4755_functions[] = { 683 { "uart0", jz4755_uart0_groups, ARRAY_SIZE(jz4755_uart0_groups), }, 684 { "uart1", jz4755_uart1_groups, ARRAY_SIZE(jz4755_uart1_groups), }, 685 { "uart2", jz4755_uart2_groups, ARRAY_SIZE(jz4755_uart2_groups), }, 686 { "mmc0", jz4755_mmc0_groups, ARRAY_SIZE(jz4755_mmc0_groups), }, 687 { "mmc1", jz4755_mmc1_groups, ARRAY_SIZE(jz4755_mmc1_groups), }, 688 { "i2c", jz4755_i2c_groups, ARRAY_SIZE(jz4755_i2c_groups), }, 689 { "cim", jz4755_cim_groups, ARRAY_SIZE(jz4755_cim_groups), }, 690 { "lcd", jz4755_lcd_groups, ARRAY_SIZE(jz4755_lcd_groups), }, 691 { "nand", jz4755_nand_groups, ARRAY_SIZE(jz4755_nand_groups), }, 692 { "pwm0", jz4755_pwm0_groups, ARRAY_SIZE(jz4755_pwm0_groups), }, 693 { "pwm1", jz4755_pwm1_groups, ARRAY_SIZE(jz4755_pwm1_groups), }, 694 { "pwm2", jz4755_pwm2_groups, ARRAY_SIZE(jz4755_pwm2_groups), }, 695 { "pwm3", jz4755_pwm3_groups, ARRAY_SIZE(jz4755_pwm3_groups), }, 696 { "pwm4", jz4755_pwm4_groups, ARRAY_SIZE(jz4755_pwm4_groups), }, 697 { "pwm5", jz4755_pwm5_groups, ARRAY_SIZE(jz4755_pwm5_groups), }, 698 }; 699 700 static const struct ingenic_chip_info jz4755_chip_info = { 701 .num_chips = 6, 702 .reg_offset = 0x100, 703 .version = ID_JZ4755, 704 .groups = jz4755_groups, 705 .num_groups = ARRAY_SIZE(jz4755_groups), 706 .functions = jz4755_functions, 707 .num_functions = ARRAY_SIZE(jz4755_functions), 708 .pull_ups = jz4755_pull_ups, 709 .pull_downs = jz4755_pull_downs, 710 }; 711 712 static const u32 jz4760_pull_ups[6] = { 713 0xffffffff, 0xfffcf3ff, 0xffffffff, 0xffffcfff, 0xfffffb7c, 0xfffff00f, 714 }; 715 716 static const u32 jz4760_pull_downs[6] = { 717 0x00000000, 0x00030c00, 0x00000000, 0x00003000, 0x00000483, 0x00000ff0, 718 }; 719 720 static int jz4760_uart0_data_pins[] = { 0xa0, 0xa3, }; 721 static int jz4760_uart0_hwflow_pins[] = { 0xa1, 0xa2, }; 722 static int jz4760_uart1_data_pins[] = { 0x7a, 0x7c, }; 723 static int jz4760_uart1_hwflow_pins[] = { 0x7b, 0x7d, }; 724 static int jz4760_uart2_data_pins[] = { 0x5c, 0x5e, }; 725 static int jz4760_uart2_hwflow_pins[] = { 0x5d, 0x5f, }; 726 static int jz4760_uart3_data_pins[] = { 0x6c, 0x85, }; 727 static int jz4760_uart3_hwflow_pins[] = { 0x88, 0x89, }; 728 static int jz4760_mmc0_1bit_a_pins[] = { 0x12, 0x13, 0x14, }; 729 static int jz4760_mmc0_4bit_a_pins[] = { 0x15, 0x16, 0x17, }; 730 static int jz4760_mmc0_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; 731 static int jz4760_mmc0_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; 732 static int jz4760_mmc0_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, }; 733 static int jz4760_mmc1_1bit_d_pins[] = { 0x78, 0x79, 0x74, }; 734 static int jz4760_mmc1_4bit_d_pins[] = { 0x75, 0x76, 0x77, }; 735 static int jz4760_mmc1_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; 736 static int jz4760_mmc1_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; 737 static int jz4760_mmc1_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, }; 738 static int jz4760_mmc2_1bit_b_pins[] = { 0x3c, 0x3d, 0x34, }; 739 static int jz4760_mmc2_4bit_b_pins[] = { 0x35, 0x3e, 0x3f, }; 740 static int jz4760_mmc2_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; 741 static int jz4760_mmc2_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; 742 static int jz4760_mmc2_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, }; 743 static int jz4760_nemc_8bit_data_pins[] = { 744 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 745 }; 746 static int jz4760_nemc_16bit_data_pins[] = { 747 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 748 }; 749 static int jz4760_nemc_cle_ale_pins[] = { 0x20, 0x21, }; 750 static int jz4760_nemc_addr_pins[] = { 0x22, 0x23, 0x24, 0x25, }; 751 static int jz4760_nemc_rd_we_pins[] = { 0x10, 0x11, }; 752 static int jz4760_nemc_frd_fwe_pins[] = { 0x12, 0x13, }; 753 static int jz4760_nemc_wait_pins[] = { 0x1b, }; 754 static int jz4760_nemc_cs1_pins[] = { 0x15, }; 755 static int jz4760_nemc_cs2_pins[] = { 0x16, }; 756 static int jz4760_nemc_cs3_pins[] = { 0x17, }; 757 static int jz4760_nemc_cs4_pins[] = { 0x18, }; 758 static int jz4760_nemc_cs5_pins[] = { 0x19, }; 759 static int jz4760_nemc_cs6_pins[] = { 0x1a, }; 760 static int jz4760_i2c0_pins[] = { 0x7e, 0x7f, }; 761 static int jz4760_i2c1_pins[] = { 0x9e, 0x9f, }; 762 static int jz4760_cim_pins[] = { 763 0x26, 0x27, 0x28, 0x29, 764 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31, 765 }; 766 static int jz4760_lcd_8bit_pins[] = { 767 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x4c, 768 0x4d, 0x52, 0x53, 769 }; 770 static int jz4760_lcd_16bit_pins[] = { 771 0x4e, 0x4f, 0x50, 0x51, 0x56, 0x57, 0x58, 0x59, 772 }; 773 static int jz4760_lcd_18bit_pins[] = { 774 0x5a, 0x5b, 775 }; 776 static int jz4760_lcd_24bit_pins[] = { 777 0x40, 0x41, 0x4a, 0x4b, 0x54, 0x55, 778 }; 779 static int jz4760_lcd_special_pins[] = { 0x54, 0x4a, 0x41, 0x40, }; 780 static int jz4760_lcd_generic_pins[] = { 0x49, }; 781 static int jz4760_pwm_pwm0_pins[] = { 0x80, }; 782 static int jz4760_pwm_pwm1_pins[] = { 0x81, }; 783 static int jz4760_pwm_pwm2_pins[] = { 0x82, }; 784 static int jz4760_pwm_pwm3_pins[] = { 0x83, }; 785 static int jz4760_pwm_pwm4_pins[] = { 0x84, }; 786 static int jz4760_pwm_pwm5_pins[] = { 0x85, }; 787 static int jz4760_pwm_pwm6_pins[] = { 0x6a, }; 788 static int jz4760_pwm_pwm7_pins[] = { 0x6b, }; 789 static int jz4760_otg_pins[] = { 0x8a, }; 790 791 static u8 jz4760_uart3_data_funcs[] = { 0, 1, }; 792 static u8 jz4760_mmc0_1bit_a_funcs[] = { 1, 1, 0, }; 793 794 static const struct group_desc jz4760_groups[] = { 795 INGENIC_PIN_GROUP("uart0-data", jz4760_uart0_data, 0), 796 INGENIC_PIN_GROUP("uart0-hwflow", jz4760_uart0_hwflow, 0), 797 INGENIC_PIN_GROUP("uart1-data", jz4760_uart1_data, 0), 798 INGENIC_PIN_GROUP("uart1-hwflow", jz4760_uart1_hwflow, 0), 799 INGENIC_PIN_GROUP("uart2-data", jz4760_uart2_data, 0), 800 INGENIC_PIN_GROUP("uart2-hwflow", jz4760_uart2_hwflow, 0), 801 INGENIC_PIN_GROUP_FUNCS("uart3-data", jz4760_uart3_data, 802 jz4760_uart3_data_funcs), 803 INGENIC_PIN_GROUP("uart3-hwflow", jz4760_uart3_hwflow, 0), 804 INGENIC_PIN_GROUP_FUNCS("mmc0-1bit-a", jz4760_mmc0_1bit_a, 805 jz4760_mmc0_1bit_a_funcs), 806 INGENIC_PIN_GROUP("mmc0-4bit-a", jz4760_mmc0_4bit_a, 1), 807 INGENIC_PIN_GROUP("mmc0-1bit-e", jz4760_mmc0_1bit_e, 0), 808 INGENIC_PIN_GROUP("mmc0-4bit-e", jz4760_mmc0_4bit_e, 0), 809 INGENIC_PIN_GROUP("mmc0-8bit-e", jz4760_mmc0_8bit_e, 0), 810 INGENIC_PIN_GROUP("mmc1-1bit-d", jz4760_mmc1_1bit_d, 0), 811 INGENIC_PIN_GROUP("mmc1-4bit-d", jz4760_mmc1_4bit_d, 0), 812 INGENIC_PIN_GROUP("mmc1-1bit-e", jz4760_mmc1_1bit_e, 1), 813 INGENIC_PIN_GROUP("mmc1-4bit-e", jz4760_mmc1_4bit_e, 1), 814 INGENIC_PIN_GROUP("mmc1-8bit-e", jz4760_mmc1_8bit_e, 1), 815 INGENIC_PIN_GROUP("mmc2-1bit-b", jz4760_mmc2_1bit_b, 0), 816 INGENIC_PIN_GROUP("mmc2-4bit-b", jz4760_mmc2_4bit_b, 0), 817 INGENIC_PIN_GROUP("mmc2-1bit-e", jz4760_mmc2_1bit_e, 2), 818 INGENIC_PIN_GROUP("mmc2-4bit-e", jz4760_mmc2_4bit_e, 2), 819 INGENIC_PIN_GROUP("mmc2-8bit-e", jz4760_mmc2_8bit_e, 2), 820 INGENIC_PIN_GROUP("nemc-8bit-data", jz4760_nemc_8bit_data, 0), 821 INGENIC_PIN_GROUP("nemc-16bit-data", jz4760_nemc_16bit_data, 0), 822 INGENIC_PIN_GROUP("nemc-cle-ale", jz4760_nemc_cle_ale, 0), 823 INGENIC_PIN_GROUP("nemc-addr", jz4760_nemc_addr, 0), 824 INGENIC_PIN_GROUP("nemc-rd-we", jz4760_nemc_rd_we, 0), 825 INGENIC_PIN_GROUP("nemc-frd-fwe", jz4760_nemc_frd_fwe, 0), 826 INGENIC_PIN_GROUP("nemc-wait", jz4760_nemc_wait, 0), 827 INGENIC_PIN_GROUP("nemc-cs1", jz4760_nemc_cs1, 0), 828 INGENIC_PIN_GROUP("nemc-cs2", jz4760_nemc_cs2, 0), 829 INGENIC_PIN_GROUP("nemc-cs3", jz4760_nemc_cs3, 0), 830 INGENIC_PIN_GROUP("nemc-cs4", jz4760_nemc_cs4, 0), 831 INGENIC_PIN_GROUP("nemc-cs5", jz4760_nemc_cs5, 0), 832 INGENIC_PIN_GROUP("nemc-cs6", jz4760_nemc_cs6, 0), 833 INGENIC_PIN_GROUP("i2c0-data", jz4760_i2c0, 0), 834 INGENIC_PIN_GROUP("i2c1-data", jz4760_i2c1, 0), 835 INGENIC_PIN_GROUP("cim-data", jz4760_cim, 0), 836 INGENIC_PIN_GROUP("lcd-8bit", jz4760_lcd_8bit, 0), 837 INGENIC_PIN_GROUP("lcd-16bit", jz4760_lcd_16bit, 0), 838 INGENIC_PIN_GROUP("lcd-18bit", jz4760_lcd_18bit, 0), 839 INGENIC_PIN_GROUP("lcd-24bit", jz4760_lcd_24bit, 0), 840 INGENIC_PIN_GROUP("lcd-special", jz4760_lcd_special, 1), 841 INGENIC_PIN_GROUP("lcd-generic", jz4760_lcd_generic, 0), 842 INGENIC_PIN_GROUP("pwm0", jz4760_pwm_pwm0, 0), 843 INGENIC_PIN_GROUP("pwm1", jz4760_pwm_pwm1, 0), 844 INGENIC_PIN_GROUP("pwm2", jz4760_pwm_pwm2, 0), 845 INGENIC_PIN_GROUP("pwm3", jz4760_pwm_pwm3, 0), 846 INGENIC_PIN_GROUP("pwm4", jz4760_pwm_pwm4, 0), 847 INGENIC_PIN_GROUP("pwm5", jz4760_pwm_pwm5, 0), 848 INGENIC_PIN_GROUP("pwm6", jz4760_pwm_pwm6, 0), 849 INGENIC_PIN_GROUP("pwm7", jz4760_pwm_pwm7, 0), 850 INGENIC_PIN_GROUP("otg-vbus", jz4760_otg, 0), 851 }; 852 853 static const char *jz4760_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; 854 static const char *jz4760_uart1_groups[] = { "uart1-data", "uart1-hwflow", }; 855 static const char *jz4760_uart2_groups[] = { "uart2-data", "uart2-hwflow", }; 856 static const char *jz4760_uart3_groups[] = { "uart3-data", "uart3-hwflow", }; 857 static const char *jz4760_mmc0_groups[] = { 858 "mmc0-1bit-a", "mmc0-4bit-a", 859 "mmc0-1bit-e", "mmc0-4bit-e", "mmc0-8bit-e", 860 }; 861 static const char *jz4760_mmc1_groups[] = { 862 "mmc1-1bit-d", "mmc1-4bit-d", 863 "mmc1-1bit-e", "mmc1-4bit-e", "mmc1-8bit-e", 864 }; 865 static const char *jz4760_mmc2_groups[] = { 866 "mmc2-1bit-b", "mmc2-4bit-b", 867 "mmc2-1bit-e", "mmc2-4bit-e", "mmc2-8bit-e", 868 }; 869 static const char *jz4760_nemc_groups[] = { 870 "nemc-8bit-data", "nemc-16bit-data", "nemc-cle-ale", 871 "nemc-addr", "nemc-rd-we", "nemc-frd-fwe", "nemc-wait", 872 }; 873 static const char *jz4760_cs1_groups[] = { "nemc-cs1", }; 874 static const char *jz4760_cs2_groups[] = { "nemc-cs2", }; 875 static const char *jz4760_cs3_groups[] = { "nemc-cs3", }; 876 static const char *jz4760_cs4_groups[] = { "nemc-cs4", }; 877 static const char *jz4760_cs5_groups[] = { "nemc-cs5", }; 878 static const char *jz4760_cs6_groups[] = { "nemc-cs6", }; 879 static const char *jz4760_i2c0_groups[] = { "i2c0-data", }; 880 static const char *jz4760_i2c1_groups[] = { "i2c1-data", }; 881 static const char *jz4760_cim_groups[] = { "cim-data", }; 882 static const char *jz4760_lcd_groups[] = { 883 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit", 884 "lcd-special", "lcd-generic", 885 }; 886 static const char *jz4760_pwm0_groups[] = { "pwm0", }; 887 static const char *jz4760_pwm1_groups[] = { "pwm1", }; 888 static const char *jz4760_pwm2_groups[] = { "pwm2", }; 889 static const char *jz4760_pwm3_groups[] = { "pwm3", }; 890 static const char *jz4760_pwm4_groups[] = { "pwm4", }; 891 static const char *jz4760_pwm5_groups[] = { "pwm5", }; 892 static const char *jz4760_pwm6_groups[] = { "pwm6", }; 893 static const char *jz4760_pwm7_groups[] = { "pwm7", }; 894 static const char *jz4760_otg_groups[] = { "otg-vbus", }; 895 896 static const struct function_desc jz4760_functions[] = { 897 { "uart0", jz4760_uart0_groups, ARRAY_SIZE(jz4760_uart0_groups), }, 898 { "uart1", jz4760_uart1_groups, ARRAY_SIZE(jz4760_uart1_groups), }, 899 { "uart2", jz4760_uart2_groups, ARRAY_SIZE(jz4760_uart2_groups), }, 900 { "uart3", jz4760_uart3_groups, ARRAY_SIZE(jz4760_uart3_groups), }, 901 { "mmc0", jz4760_mmc0_groups, ARRAY_SIZE(jz4760_mmc0_groups), }, 902 { "mmc1", jz4760_mmc1_groups, ARRAY_SIZE(jz4760_mmc1_groups), }, 903 { "mmc2", jz4760_mmc2_groups, ARRAY_SIZE(jz4760_mmc2_groups), }, 904 { "nemc", jz4760_nemc_groups, ARRAY_SIZE(jz4760_nemc_groups), }, 905 { "nemc-cs1", jz4760_cs1_groups, ARRAY_SIZE(jz4760_cs1_groups), }, 906 { "nemc-cs2", jz4760_cs2_groups, ARRAY_SIZE(jz4760_cs2_groups), }, 907 { "nemc-cs3", jz4760_cs3_groups, ARRAY_SIZE(jz4760_cs3_groups), }, 908 { "nemc-cs4", jz4760_cs4_groups, ARRAY_SIZE(jz4760_cs4_groups), }, 909 { "nemc-cs5", jz4760_cs5_groups, ARRAY_SIZE(jz4760_cs5_groups), }, 910 { "nemc-cs6", jz4760_cs6_groups, ARRAY_SIZE(jz4760_cs6_groups), }, 911 { "i2c0", jz4760_i2c0_groups, ARRAY_SIZE(jz4760_i2c0_groups), }, 912 { "i2c1", jz4760_i2c1_groups, ARRAY_SIZE(jz4760_i2c1_groups), }, 913 { "cim", jz4760_cim_groups, ARRAY_SIZE(jz4760_cim_groups), }, 914 { "lcd", jz4760_lcd_groups, ARRAY_SIZE(jz4760_lcd_groups), }, 915 { "pwm0", jz4760_pwm0_groups, ARRAY_SIZE(jz4760_pwm0_groups), }, 916 { "pwm1", jz4760_pwm1_groups, ARRAY_SIZE(jz4760_pwm1_groups), }, 917 { "pwm2", jz4760_pwm2_groups, ARRAY_SIZE(jz4760_pwm2_groups), }, 918 { "pwm3", jz4760_pwm3_groups, ARRAY_SIZE(jz4760_pwm3_groups), }, 919 { "pwm4", jz4760_pwm4_groups, ARRAY_SIZE(jz4760_pwm4_groups), }, 920 { "pwm5", jz4760_pwm5_groups, ARRAY_SIZE(jz4760_pwm5_groups), }, 921 { "pwm6", jz4760_pwm6_groups, ARRAY_SIZE(jz4760_pwm6_groups), }, 922 { "pwm7", jz4760_pwm7_groups, ARRAY_SIZE(jz4760_pwm7_groups), }, 923 { "otg", jz4760_otg_groups, ARRAY_SIZE(jz4760_otg_groups), }, 924 }; 925 926 static const struct ingenic_chip_info jz4760_chip_info = { 927 .num_chips = 6, 928 .reg_offset = 0x100, 929 .version = ID_JZ4760, 930 .groups = jz4760_groups, 931 .num_groups = ARRAY_SIZE(jz4760_groups), 932 .functions = jz4760_functions, 933 .num_functions = ARRAY_SIZE(jz4760_functions), 934 .pull_ups = jz4760_pull_ups, 935 .pull_downs = jz4760_pull_downs, 936 }; 937 938 static const u32 jz4770_pull_ups[6] = { 939 0x3fffffff, 0xfff0030c, 0xffffffff, 0xffff4fff, 0xfffffb7c, 0xffa7f00f, 940 }; 941 942 static const u32 jz4770_pull_downs[6] = { 943 0x00000000, 0x000f0c03, 0x00000000, 0x0000b000, 0x00000483, 0x00580ff0, 944 }; 945 946 static int jz4770_uart0_data_pins[] = { 0xa0, 0xa3, }; 947 static int jz4770_uart0_hwflow_pins[] = { 0xa1, 0xa2, }; 948 static int jz4770_uart1_data_pins[] = { 0x7a, 0x7c, }; 949 static int jz4770_uart1_hwflow_pins[] = { 0x7b, 0x7d, }; 950 static int jz4770_uart2_data_pins[] = { 0x5c, 0x5e, }; 951 static int jz4770_uart2_hwflow_pins[] = { 0x5d, 0x5f, }; 952 static int jz4770_uart3_data_pins[] = { 0x6c, 0x85, }; 953 static int jz4770_uart3_hwflow_pins[] = { 0x88, 0x89, }; 954 static int jz4770_ssi0_dt_a_pins[] = { 0x15, }; 955 static int jz4770_ssi0_dt_b_pins[] = { 0x35, }; 956 static int jz4770_ssi0_dt_d_pins[] = { 0x75, }; 957 static int jz4770_ssi0_dt_e_pins[] = { 0x91, }; 958 static int jz4770_ssi0_dr_a_pins[] = { 0x14, }; 959 static int jz4770_ssi0_dr_b_pins[] = { 0x34, }; 960 static int jz4770_ssi0_dr_d_pins[] = { 0x74, }; 961 static int jz4770_ssi0_dr_e_pins[] = { 0x8e, }; 962 static int jz4770_ssi0_clk_a_pins[] = { 0x12, }; 963 static int jz4770_ssi0_clk_b_pins[] = { 0x3c, }; 964 static int jz4770_ssi0_clk_d_pins[] = { 0x78, }; 965 static int jz4770_ssi0_clk_e_pins[] = { 0x8f, }; 966 static int jz4770_ssi0_gpc_b_pins[] = { 0x3e, }; 967 static int jz4770_ssi0_gpc_d_pins[] = { 0x76, }; 968 static int jz4770_ssi0_gpc_e_pins[] = { 0x93, }; 969 static int jz4770_ssi0_ce0_a_pins[] = { 0x13, }; 970 static int jz4770_ssi0_ce0_b_pins[] = { 0x3d, }; 971 static int jz4770_ssi0_ce0_d_pins[] = { 0x79, }; 972 static int jz4770_ssi0_ce0_e_pins[] = { 0x90, }; 973 static int jz4770_ssi0_ce1_b_pins[] = { 0x3f, }; 974 static int jz4770_ssi0_ce1_d_pins[] = { 0x77, }; 975 static int jz4770_ssi0_ce1_e_pins[] = { 0x92, }; 976 static int jz4770_ssi1_dt_b_pins[] = { 0x35, }; 977 static int jz4770_ssi1_dt_d_pins[] = { 0x75, }; 978 static int jz4770_ssi1_dt_e_pins[] = { 0x91, }; 979 static int jz4770_ssi1_dr_b_pins[] = { 0x34, }; 980 static int jz4770_ssi1_dr_d_pins[] = { 0x74, }; 981 static int jz4770_ssi1_dr_e_pins[] = { 0x8e, }; 982 static int jz4770_ssi1_clk_b_pins[] = { 0x3c, }; 983 static int jz4770_ssi1_clk_d_pins[] = { 0x78, }; 984 static int jz4770_ssi1_clk_e_pins[] = { 0x8f, }; 985 static int jz4770_ssi1_gpc_b_pins[] = { 0x3e, }; 986 static int jz4770_ssi1_gpc_d_pins[] = { 0x76, }; 987 static int jz4770_ssi1_gpc_e_pins[] = { 0x93, }; 988 static int jz4770_ssi1_ce0_b_pins[] = { 0x3d, }; 989 static int jz4770_ssi1_ce0_d_pins[] = { 0x79, }; 990 static int jz4770_ssi1_ce0_e_pins[] = { 0x90, }; 991 static int jz4770_ssi1_ce1_b_pins[] = { 0x3f, }; 992 static int jz4770_ssi1_ce1_d_pins[] = { 0x77, }; 993 static int jz4770_ssi1_ce1_e_pins[] = { 0x92, }; 994 static int jz4770_mmc0_1bit_a_pins[] = { 0x12, 0x13, 0x14, }; 995 static int jz4770_mmc0_4bit_a_pins[] = { 0x15, 0x16, 0x17, }; 996 static int jz4770_mmc0_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; 997 static int jz4770_mmc0_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; 998 static int jz4770_mmc0_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, }; 999 static int jz4770_mmc1_1bit_d_pins[] = { 0x78, 0x79, 0x74, }; 1000 static int jz4770_mmc1_4bit_d_pins[] = { 0x75, 0x76, 0x77, }; 1001 static int jz4770_mmc1_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; 1002 static int jz4770_mmc1_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; 1003 static int jz4770_mmc1_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, }; 1004 static int jz4770_mmc2_1bit_b_pins[] = { 0x3c, 0x3d, 0x34, }; 1005 static int jz4770_mmc2_4bit_b_pins[] = { 0x35, 0x3e, 0x3f, }; 1006 static int jz4770_mmc2_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; 1007 static int jz4770_mmc2_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; 1008 static int jz4770_mmc2_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, }; 1009 static int jz4770_nemc_8bit_data_pins[] = { 1010 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 1011 }; 1012 static int jz4770_nemc_16bit_data_pins[] = { 1013 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 1014 }; 1015 static int jz4770_nemc_cle_ale_pins[] = { 0x20, 0x21, }; 1016 static int jz4770_nemc_addr_pins[] = { 0x22, 0x23, 0x24, 0x25, }; 1017 static int jz4770_nemc_rd_we_pins[] = { 0x10, 0x11, }; 1018 static int jz4770_nemc_frd_fwe_pins[] = { 0x12, 0x13, }; 1019 static int jz4770_nemc_wait_pins[] = { 0x1b, }; 1020 static int jz4770_nemc_cs1_pins[] = { 0x15, }; 1021 static int jz4770_nemc_cs2_pins[] = { 0x16, }; 1022 static int jz4770_nemc_cs3_pins[] = { 0x17, }; 1023 static int jz4770_nemc_cs4_pins[] = { 0x18, }; 1024 static int jz4770_nemc_cs5_pins[] = { 0x19, }; 1025 static int jz4770_nemc_cs6_pins[] = { 0x1a, }; 1026 static int jz4770_i2c0_pins[] = { 0x7e, 0x7f, }; 1027 static int jz4770_i2c1_pins[] = { 0x9e, 0x9f, }; 1028 static int jz4770_i2c2_pins[] = { 0xb0, 0xb1, }; 1029 static int jz4770_cim_8bit_pins[] = { 1030 0x26, 0x27, 0x28, 0x29, 1031 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31, 1032 }; 1033 static int jz4770_cim_12bit_pins[] = { 1034 0x32, 0x33, 0xb0, 0xb1, 1035 }; 1036 static int jz4770_lcd_8bit_pins[] = { 1037 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x4c, 0x4d, 1038 0x48, 0x52, 0x53, 1039 }; 1040 static int jz4770_lcd_16bit_pins[] = { 1041 0x4e, 0x4f, 0x50, 0x51, 0x56, 0x57, 0x58, 0x59, 1042 }; 1043 static int jz4770_lcd_18bit_pins[] = { 1044 0x5a, 0x5b, 1045 }; 1046 static int jz4770_lcd_24bit_pins[] = { 1047 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 1048 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, 1049 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 1050 0x58, 0x59, 0x5a, 0x5b, 1051 }; 1052 static int jz4770_lcd_special_pins[] = { 0x54, 0x4a, 0x41, 0x40, }; 1053 static int jz4770_lcd_generic_pins[] = { 0x49, }; 1054 static int jz4770_pwm_pwm0_pins[] = { 0x80, }; 1055 static int jz4770_pwm_pwm1_pins[] = { 0x81, }; 1056 static int jz4770_pwm_pwm2_pins[] = { 0x82, }; 1057 static int jz4770_pwm_pwm3_pins[] = { 0x83, }; 1058 static int jz4770_pwm_pwm4_pins[] = { 0x84, }; 1059 static int jz4770_pwm_pwm5_pins[] = { 0x85, }; 1060 static int jz4770_pwm_pwm6_pins[] = { 0x6a, }; 1061 static int jz4770_pwm_pwm7_pins[] = { 0x6b, }; 1062 static int jz4770_mac_rmii_pins[] = { 1063 0xa9, 0xab, 0xaa, 0xac, 0xa5, 0xa4, 0xad, 0xae, 0xa6, 0xa8, 1064 }; 1065 static int jz4770_mac_mii_pins[] = { 1066 0x7b, 0x7a, 0x7d, 0x7c, 0xa7, 0x24, 0xaf, 1067 }; 1068 1069 static const struct group_desc jz4770_groups[] = { 1070 INGENIC_PIN_GROUP("uart0-data", jz4770_uart0_data, 0), 1071 INGENIC_PIN_GROUP("uart0-hwflow", jz4770_uart0_hwflow, 0), 1072 INGENIC_PIN_GROUP("uart1-data", jz4770_uart1_data, 0), 1073 INGENIC_PIN_GROUP("uart1-hwflow", jz4770_uart1_hwflow, 0), 1074 INGENIC_PIN_GROUP("uart2-data", jz4770_uart2_data, 0), 1075 INGENIC_PIN_GROUP("uart2-hwflow", jz4770_uart2_hwflow, 0), 1076 INGENIC_PIN_GROUP_FUNCS("uart3-data", jz4770_uart3_data, 1077 jz4760_uart3_data_funcs), 1078 INGENIC_PIN_GROUP("uart3-hwflow", jz4770_uart3_hwflow, 0), 1079 INGENIC_PIN_GROUP("ssi0-dt-a", jz4770_ssi0_dt_a, 2), 1080 INGENIC_PIN_GROUP("ssi0-dt-b", jz4770_ssi0_dt_b, 1), 1081 INGENIC_PIN_GROUP("ssi0-dt-d", jz4770_ssi0_dt_d, 1), 1082 INGENIC_PIN_GROUP("ssi0-dt-e", jz4770_ssi0_dt_e, 0), 1083 INGENIC_PIN_GROUP("ssi0-dr-a", jz4770_ssi0_dr_a, 1), 1084 INGENIC_PIN_GROUP("ssi0-dr-b", jz4770_ssi0_dr_b, 1), 1085 INGENIC_PIN_GROUP("ssi0-dr-d", jz4770_ssi0_dr_d, 1), 1086 INGENIC_PIN_GROUP("ssi0-dr-e", jz4770_ssi0_dr_e, 0), 1087 INGENIC_PIN_GROUP("ssi0-clk-a", jz4770_ssi0_clk_a, 2), 1088 INGENIC_PIN_GROUP("ssi0-clk-b", jz4770_ssi0_clk_b, 1), 1089 INGENIC_PIN_GROUP("ssi0-clk-d", jz4770_ssi0_clk_d, 1), 1090 INGENIC_PIN_GROUP("ssi0-clk-e", jz4770_ssi0_clk_e, 0), 1091 INGENIC_PIN_GROUP("ssi0-gpc-b", jz4770_ssi0_gpc_b, 1), 1092 INGENIC_PIN_GROUP("ssi0-gpc-d", jz4770_ssi0_gpc_d, 1), 1093 INGENIC_PIN_GROUP("ssi0-gpc-e", jz4770_ssi0_gpc_e, 0), 1094 INGENIC_PIN_GROUP("ssi0-ce0-a", jz4770_ssi0_ce0_a, 2), 1095 INGENIC_PIN_GROUP("ssi0-ce0-b", jz4770_ssi0_ce0_b, 1), 1096 INGENIC_PIN_GROUP("ssi0-ce0-d", jz4770_ssi0_ce0_d, 1), 1097 INGENIC_PIN_GROUP("ssi0-ce0-e", jz4770_ssi0_ce0_e, 0), 1098 INGENIC_PIN_GROUP("ssi0-ce1-b", jz4770_ssi0_ce1_b, 1), 1099 INGENIC_PIN_GROUP("ssi0-ce1-d", jz4770_ssi0_ce1_d, 1), 1100 INGENIC_PIN_GROUP("ssi0-ce1-e", jz4770_ssi0_ce1_e, 0), 1101 INGENIC_PIN_GROUP("ssi1-dt-b", jz4770_ssi1_dt_b, 2), 1102 INGENIC_PIN_GROUP("ssi1-dt-d", jz4770_ssi1_dt_d, 2), 1103 INGENIC_PIN_GROUP("ssi1-dt-e", jz4770_ssi1_dt_e, 1), 1104 INGENIC_PIN_GROUP("ssi1-dr-b", jz4770_ssi1_dr_b, 2), 1105 INGENIC_PIN_GROUP("ssi1-dr-d", jz4770_ssi1_dr_d, 2), 1106 INGENIC_PIN_GROUP("ssi1-dr-e", jz4770_ssi1_dr_e, 1), 1107 INGENIC_PIN_GROUP("ssi1-clk-b", jz4770_ssi1_clk_b, 2), 1108 INGENIC_PIN_GROUP("ssi1-clk-d", jz4770_ssi1_clk_d, 2), 1109 INGENIC_PIN_GROUP("ssi1-clk-e", jz4770_ssi1_clk_e, 1), 1110 INGENIC_PIN_GROUP("ssi1-gpc-b", jz4770_ssi1_gpc_b, 2), 1111 INGENIC_PIN_GROUP("ssi1-gpc-d", jz4770_ssi1_gpc_d, 2), 1112 INGENIC_PIN_GROUP("ssi1-gpc-e", jz4770_ssi1_gpc_e, 1), 1113 INGENIC_PIN_GROUP("ssi1-ce0-b", jz4770_ssi1_ce0_b, 2), 1114 INGENIC_PIN_GROUP("ssi1-ce0-d", jz4770_ssi1_ce0_d, 2), 1115 INGENIC_PIN_GROUP("ssi1-ce0-e", jz4770_ssi1_ce0_e, 1), 1116 INGENIC_PIN_GROUP("ssi1-ce1-b", jz4770_ssi1_ce1_b, 2), 1117 INGENIC_PIN_GROUP("ssi1-ce1-d", jz4770_ssi1_ce1_d, 2), 1118 INGENIC_PIN_GROUP("ssi1-ce1-e", jz4770_ssi1_ce1_e, 1), 1119 INGENIC_PIN_GROUP_FUNCS("mmc0-1bit-a", jz4770_mmc0_1bit_a, 1120 jz4760_mmc0_1bit_a_funcs), 1121 INGENIC_PIN_GROUP("mmc0-4bit-a", jz4770_mmc0_4bit_a, 1), 1122 INGENIC_PIN_GROUP("mmc0-1bit-e", jz4770_mmc0_1bit_e, 0), 1123 INGENIC_PIN_GROUP("mmc0-4bit-e", jz4770_mmc0_4bit_e, 0), 1124 INGENIC_PIN_GROUP("mmc0-8bit-e", jz4770_mmc0_8bit_e, 0), 1125 INGENIC_PIN_GROUP("mmc1-1bit-d", jz4770_mmc1_1bit_d, 0), 1126 INGENIC_PIN_GROUP("mmc1-4bit-d", jz4770_mmc1_4bit_d, 0), 1127 INGENIC_PIN_GROUP("mmc1-1bit-e", jz4770_mmc1_1bit_e, 1), 1128 INGENIC_PIN_GROUP("mmc1-4bit-e", jz4770_mmc1_4bit_e, 1), 1129 INGENIC_PIN_GROUP("mmc1-8bit-e", jz4770_mmc1_8bit_e, 1), 1130 INGENIC_PIN_GROUP("mmc2-1bit-b", jz4770_mmc2_1bit_b, 0), 1131 INGENIC_PIN_GROUP("mmc2-4bit-b", jz4770_mmc2_4bit_b, 0), 1132 INGENIC_PIN_GROUP("mmc2-1bit-e", jz4770_mmc2_1bit_e, 2), 1133 INGENIC_PIN_GROUP("mmc2-4bit-e", jz4770_mmc2_4bit_e, 2), 1134 INGENIC_PIN_GROUP("mmc2-8bit-e", jz4770_mmc2_8bit_e, 2), 1135 INGENIC_PIN_GROUP("nemc-8bit-data", jz4770_nemc_8bit_data, 0), 1136 INGENIC_PIN_GROUP("nemc-16bit-data", jz4770_nemc_16bit_data, 0), 1137 INGENIC_PIN_GROUP("nemc-cle-ale", jz4770_nemc_cle_ale, 0), 1138 INGENIC_PIN_GROUP("nemc-addr", jz4770_nemc_addr, 0), 1139 INGENIC_PIN_GROUP("nemc-rd-we", jz4770_nemc_rd_we, 0), 1140 INGENIC_PIN_GROUP("nemc-frd-fwe", jz4770_nemc_frd_fwe, 0), 1141 INGENIC_PIN_GROUP("nemc-wait", jz4770_nemc_wait, 0), 1142 INGENIC_PIN_GROUP("nemc-cs1", jz4770_nemc_cs1, 0), 1143 INGENIC_PIN_GROUP("nemc-cs2", jz4770_nemc_cs2, 0), 1144 INGENIC_PIN_GROUP("nemc-cs3", jz4770_nemc_cs3, 0), 1145 INGENIC_PIN_GROUP("nemc-cs4", jz4770_nemc_cs4, 0), 1146 INGENIC_PIN_GROUP("nemc-cs5", jz4770_nemc_cs5, 0), 1147 INGENIC_PIN_GROUP("nemc-cs6", jz4770_nemc_cs6, 0), 1148 INGENIC_PIN_GROUP("i2c0-data", jz4770_i2c0, 0), 1149 INGENIC_PIN_GROUP("i2c1-data", jz4770_i2c1, 0), 1150 INGENIC_PIN_GROUP("i2c2-data", jz4770_i2c2, 2), 1151 INGENIC_PIN_GROUP("cim-data-8bit", jz4770_cim_8bit, 0), 1152 INGENIC_PIN_GROUP("cim-data-12bit", jz4770_cim_12bit, 0), 1153 INGENIC_PIN_GROUP("lcd-8bit", jz4770_lcd_8bit, 0), 1154 INGENIC_PIN_GROUP("lcd-16bit", jz4770_lcd_16bit, 0), 1155 INGENIC_PIN_GROUP("lcd-18bit", jz4770_lcd_18bit, 0), 1156 INGENIC_PIN_GROUP("lcd-24bit", jz4770_lcd_24bit, 0), 1157 INGENIC_PIN_GROUP("lcd-special", jz4770_lcd_special, 1), 1158 INGENIC_PIN_GROUP("lcd-generic", jz4770_lcd_generic, 0), 1159 INGENIC_PIN_GROUP("pwm0", jz4770_pwm_pwm0, 0), 1160 INGENIC_PIN_GROUP("pwm1", jz4770_pwm_pwm1, 0), 1161 INGENIC_PIN_GROUP("pwm2", jz4770_pwm_pwm2, 0), 1162 INGENIC_PIN_GROUP("pwm3", jz4770_pwm_pwm3, 0), 1163 INGENIC_PIN_GROUP("pwm4", jz4770_pwm_pwm4, 0), 1164 INGENIC_PIN_GROUP("pwm5", jz4770_pwm_pwm5, 0), 1165 INGENIC_PIN_GROUP("pwm6", jz4770_pwm_pwm6, 0), 1166 INGENIC_PIN_GROUP("pwm7", jz4770_pwm_pwm7, 0), 1167 INGENIC_PIN_GROUP("mac-rmii", jz4770_mac_rmii, 0), 1168 INGENIC_PIN_GROUP("mac-mii", jz4770_mac_mii, 0), 1169 INGENIC_PIN_GROUP("otg-vbus", jz4760_otg, 0), 1170 }; 1171 1172 static const char *jz4770_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; 1173 static const char *jz4770_uart1_groups[] = { "uart1-data", "uart1-hwflow", }; 1174 static const char *jz4770_uart2_groups[] = { "uart2-data", "uart2-hwflow", }; 1175 static const char *jz4770_uart3_groups[] = { "uart3-data", "uart3-hwflow", }; 1176 static const char *jz4770_ssi0_groups[] = { 1177 "ssi0-dt-a", "ssi0-dt-b", "ssi0-dt-d", "ssi0-dt-e", 1178 "ssi0-dr-a", "ssi0-dr-b", "ssi0-dr-d", "ssi0-dr-e", 1179 "ssi0-clk-a", "ssi0-clk-b", "ssi0-clk-d", "ssi0-clk-e", 1180 "ssi0-gpc-b", "ssi0-gpc-d", "ssi0-gpc-e", 1181 "ssi0-ce0-a", "ssi0-ce0-b", "ssi0-ce0-d", "ssi0-ce0-e", 1182 "ssi0-ce1-b", "ssi0-ce1-d", "ssi0-ce1-e", 1183 }; 1184 static const char *jz4770_ssi1_groups[] = { 1185 "ssi1-dt-b", "ssi1-dt-d", "ssi1-dt-e", 1186 "ssi1-dr-b", "ssi1-dr-d", "ssi1-dr-e", 1187 "ssi1-clk-b", "ssi1-clk-d", "ssi1-clk-e", 1188 "ssi1-gpc-b", "ssi1-gpc-d", "ssi1-gpc-e", 1189 "ssi1-ce0-b", "ssi1-ce0-d", "ssi1-ce0-e", 1190 "ssi1-ce1-b", "ssi1-ce1-d", "ssi1-ce1-e", 1191 }; 1192 static const char *jz4770_mmc0_groups[] = { 1193 "mmc0-1bit-a", "mmc0-4bit-a", 1194 "mmc0-1bit-e", "mmc0-4bit-e", "mmc0-8bit-e", 1195 }; 1196 static const char *jz4770_mmc1_groups[] = { 1197 "mmc1-1bit-d", "mmc1-4bit-d", 1198 "mmc1-1bit-e", "mmc1-4bit-e", "mmc1-8bit-e", 1199 }; 1200 static const char *jz4770_mmc2_groups[] = { 1201 "mmc2-1bit-b", "mmc2-4bit-b", 1202 "mmc2-1bit-e", "mmc2-4bit-e", "mmc2-8bit-e", 1203 }; 1204 static const char *jz4770_nemc_groups[] = { 1205 "nemc-8bit-data", "nemc-16bit-data", "nemc-cle-ale", 1206 "nemc-addr", "nemc-rd-we", "nemc-frd-fwe", "nemc-wait", 1207 }; 1208 static const char *jz4770_cs1_groups[] = { "nemc-cs1", }; 1209 static const char *jz4770_cs2_groups[] = { "nemc-cs2", }; 1210 static const char *jz4770_cs3_groups[] = { "nemc-cs3", }; 1211 static const char *jz4770_cs4_groups[] = { "nemc-cs4", }; 1212 static const char *jz4770_cs5_groups[] = { "nemc-cs5", }; 1213 static const char *jz4770_cs6_groups[] = { "nemc-cs6", }; 1214 static const char *jz4770_i2c0_groups[] = { "i2c0-data", }; 1215 static const char *jz4770_i2c1_groups[] = { "i2c1-data", }; 1216 static const char *jz4770_i2c2_groups[] = { "i2c2-data", }; 1217 static const char *jz4770_cim_groups[] = { "cim-data-8bit", "cim-data-12bit", }; 1218 static const char *jz4770_lcd_groups[] = { 1219 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit", 1220 "lcd-special", "lcd-generic", 1221 }; 1222 static const char *jz4770_pwm0_groups[] = { "pwm0", }; 1223 static const char *jz4770_pwm1_groups[] = { "pwm1", }; 1224 static const char *jz4770_pwm2_groups[] = { "pwm2", }; 1225 static const char *jz4770_pwm3_groups[] = { "pwm3", }; 1226 static const char *jz4770_pwm4_groups[] = { "pwm4", }; 1227 static const char *jz4770_pwm5_groups[] = { "pwm5", }; 1228 static const char *jz4770_pwm6_groups[] = { "pwm6", }; 1229 static const char *jz4770_pwm7_groups[] = { "pwm7", }; 1230 static const char *jz4770_mac_groups[] = { "mac-rmii", "mac-mii", }; 1231 1232 static const struct function_desc jz4770_functions[] = { 1233 { "uart0", jz4770_uart0_groups, ARRAY_SIZE(jz4770_uart0_groups), }, 1234 { "uart1", jz4770_uart1_groups, ARRAY_SIZE(jz4770_uart1_groups), }, 1235 { "uart2", jz4770_uart2_groups, ARRAY_SIZE(jz4770_uart2_groups), }, 1236 { "uart3", jz4770_uart3_groups, ARRAY_SIZE(jz4770_uart3_groups), }, 1237 { "ssi0", jz4770_ssi0_groups, ARRAY_SIZE(jz4770_ssi0_groups), }, 1238 { "ssi1", jz4770_ssi1_groups, ARRAY_SIZE(jz4770_ssi1_groups), }, 1239 { "mmc0", jz4770_mmc0_groups, ARRAY_SIZE(jz4770_mmc0_groups), }, 1240 { "mmc1", jz4770_mmc1_groups, ARRAY_SIZE(jz4770_mmc1_groups), }, 1241 { "mmc2", jz4770_mmc2_groups, ARRAY_SIZE(jz4770_mmc2_groups), }, 1242 { "nemc", jz4770_nemc_groups, ARRAY_SIZE(jz4770_nemc_groups), }, 1243 { "nemc-cs1", jz4770_cs1_groups, ARRAY_SIZE(jz4770_cs1_groups), }, 1244 { "nemc-cs2", jz4770_cs2_groups, ARRAY_SIZE(jz4770_cs2_groups), }, 1245 { "nemc-cs3", jz4770_cs3_groups, ARRAY_SIZE(jz4770_cs3_groups), }, 1246 { "nemc-cs4", jz4770_cs4_groups, ARRAY_SIZE(jz4770_cs4_groups), }, 1247 { "nemc-cs5", jz4770_cs5_groups, ARRAY_SIZE(jz4770_cs5_groups), }, 1248 { "nemc-cs6", jz4770_cs6_groups, ARRAY_SIZE(jz4770_cs6_groups), }, 1249 { "i2c0", jz4770_i2c0_groups, ARRAY_SIZE(jz4770_i2c0_groups), }, 1250 { "i2c1", jz4770_i2c1_groups, ARRAY_SIZE(jz4770_i2c1_groups), }, 1251 { "i2c2", jz4770_i2c2_groups, ARRAY_SIZE(jz4770_i2c2_groups), }, 1252 { "cim", jz4770_cim_groups, ARRAY_SIZE(jz4770_cim_groups), }, 1253 { "lcd", jz4770_lcd_groups, ARRAY_SIZE(jz4770_lcd_groups), }, 1254 { "pwm0", jz4770_pwm0_groups, ARRAY_SIZE(jz4770_pwm0_groups), }, 1255 { "pwm1", jz4770_pwm1_groups, ARRAY_SIZE(jz4770_pwm1_groups), }, 1256 { "pwm2", jz4770_pwm2_groups, ARRAY_SIZE(jz4770_pwm2_groups), }, 1257 { "pwm3", jz4770_pwm3_groups, ARRAY_SIZE(jz4770_pwm3_groups), }, 1258 { "pwm4", jz4770_pwm4_groups, ARRAY_SIZE(jz4770_pwm4_groups), }, 1259 { "pwm5", jz4770_pwm5_groups, ARRAY_SIZE(jz4770_pwm5_groups), }, 1260 { "pwm6", jz4770_pwm6_groups, ARRAY_SIZE(jz4770_pwm6_groups), }, 1261 { "pwm7", jz4770_pwm7_groups, ARRAY_SIZE(jz4770_pwm7_groups), }, 1262 { "mac", jz4770_mac_groups, ARRAY_SIZE(jz4770_mac_groups), }, 1263 { "otg", jz4760_otg_groups, ARRAY_SIZE(jz4760_otg_groups), }, 1264 }; 1265 1266 static const struct ingenic_chip_info jz4770_chip_info = { 1267 .num_chips = 6, 1268 .reg_offset = 0x100, 1269 .version = ID_JZ4770, 1270 .groups = jz4770_groups, 1271 .num_groups = ARRAY_SIZE(jz4770_groups), 1272 .functions = jz4770_functions, 1273 .num_functions = ARRAY_SIZE(jz4770_functions), 1274 .pull_ups = jz4770_pull_ups, 1275 .pull_downs = jz4770_pull_downs, 1276 }; 1277 1278 static const u32 jz4775_pull_ups[7] = { 1279 0x28ff00ff, 0xf030f3fc, 0x0fffffff, 0xfffe4000, 0xf0f0000c, 0x0000f00f, 0x0000f3c0, 1280 }; 1281 1282 static const u32 jz4775_pull_downs[7] = { 1283 0x00000000, 0x00030c03, 0x00000000, 0x00008000, 0x00000403, 0x00000ff0, 0x00030c00, 1284 }; 1285 1286 static int jz4775_uart0_data_pins[] = { 0xa0, 0xa3, }; 1287 static int jz4775_uart0_hwflow_pins[] = { 0xa1, 0xa2, }; 1288 static int jz4775_uart1_data_pins[] = { 0x7a, 0x7c, }; 1289 static int jz4775_uart1_hwflow_pins[] = { 0x7b, 0x7d, }; 1290 static int jz4775_uart2_data_c_pins[] = { 0x54, 0x4a, }; 1291 static int jz4775_uart2_data_f_pins[] = { 0xa5, 0xa4, }; 1292 static int jz4775_uart3_data_pins[] = { 0x1e, 0x1f, }; 1293 static int jz4775_ssi_dt_a_pins[] = { 0x13, }; 1294 static int jz4775_ssi_dt_d_pins[] = { 0x75, }; 1295 static int jz4775_ssi_dr_a_pins[] = { 0x14, }; 1296 static int jz4775_ssi_dr_d_pins[] = { 0x74, }; 1297 static int jz4775_ssi_clk_a_pins[] = { 0x12, }; 1298 static int jz4775_ssi_clk_d_pins[] = { 0x78, }; 1299 static int jz4775_ssi_gpc_pins[] = { 0x76, }; 1300 static int jz4775_ssi_ce0_a_pins[] = { 0x17, }; 1301 static int jz4775_ssi_ce0_d_pins[] = { 0x79, }; 1302 static int jz4775_ssi_ce1_pins[] = { 0x77, }; 1303 static int jz4775_mmc0_1bit_a_pins[] = { 0x12, 0x13, 0x14, }; 1304 static int jz4775_mmc0_4bit_a_pins[] = { 0x15, 0x16, 0x17, }; 1305 static int jz4775_mmc0_8bit_a_pins[] = { 0x04, 0x05, 0x06, 0x07, }; 1306 static int jz4775_mmc0_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; 1307 static int jz4775_mmc0_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; 1308 static int jz4775_mmc1_1bit_d_pins[] = { 0x78, 0x79, 0x74, }; 1309 static int jz4775_mmc1_4bit_d_pins[] = { 0x75, 0x76, 0x77, }; 1310 static int jz4775_mmc1_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; 1311 static int jz4775_mmc1_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; 1312 static int jz4775_mmc2_1bit_b_pins[] = { 0x3c, 0x3d, 0x34, }; 1313 static int jz4775_mmc2_4bit_b_pins[] = { 0x35, 0x3e, 0x3f, }; 1314 static int jz4775_mmc2_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; 1315 static int jz4775_mmc2_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; 1316 static int jz4775_nemc_8bit_data_pins[] = { 1317 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 1318 }; 1319 static int jz4775_nemc_16bit_data_pins[] = { 1320 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf, 0xd0, 0xd1, 1321 }; 1322 static int jz4775_nemc_cle_ale_pins[] = { 0x20, 0x21, }; 1323 static int jz4775_nemc_addr_pins[] = { 0x22, 0x23, 0x24, 0x25, }; 1324 static int jz4775_nemc_rd_we_pins[] = { 0x10, 0x11, }; 1325 static int jz4775_nemc_frd_fwe_pins[] = { 0x12, 0x13, }; 1326 static int jz4775_nemc_wait_pins[] = { 0x1b, }; 1327 static int jz4775_nemc_cs1_pins[] = { 0x15, }; 1328 static int jz4775_nemc_cs2_pins[] = { 0x16, }; 1329 static int jz4775_nemc_cs3_pins[] = { 0x17, }; 1330 static int jz4775_i2c0_pins[] = { 0x7e, 0x7f, }; 1331 static int jz4775_i2c1_pins[] = { 0x9e, 0x9f, }; 1332 static int jz4775_i2c2_pins[] = { 0x80, 0x83, }; 1333 static int jz4775_i2s_data_tx_pins[] = { 0xa3, }; 1334 static int jz4775_i2s_data_rx_pins[] = { 0xa2, }; 1335 static int jz4775_i2s_clk_txrx_pins[] = { 0xa0, 0xa1, }; 1336 static int jz4775_i2s_sysclk_pins[] = { 0x83, }; 1337 static int jz4775_dmic_pins[] = { 0xaa, 0xab, }; 1338 static int jz4775_cim_pins[] = { 1339 0x26, 0x27, 0x28, 0x29, 1340 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31, 1341 }; 1342 static int jz4775_lcd_8bit_pins[] = { 1343 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x4c, 0x4d, 1344 0x48, 0x52, 0x53, 1345 }; 1346 static int jz4775_lcd_16bit_pins[] = { 1347 0x4e, 0x4f, 0x50, 0x51, 0x56, 0x57, 0x58, 0x59, 1348 }; 1349 static int jz4775_lcd_18bit_pins[] = { 1350 0x5a, 0x5b, 1351 }; 1352 static int jz4775_lcd_24bit_pins[] = { 1353 0x40, 0x41, 0x4a, 0x4b, 0x54, 0x55, 1354 }; 1355 static int jz4775_lcd_special_pins[] = { 0x54, 0x4a, 0x41, 0x40, }; 1356 static int jz4775_lcd_generic_pins[] = { 0x49, }; 1357 static int jz4775_pwm_pwm0_pins[] = { 0x80, }; 1358 static int jz4775_pwm_pwm1_pins[] = { 0x81, }; 1359 static int jz4775_pwm_pwm2_pins[] = { 0x82, }; 1360 static int jz4775_pwm_pwm3_pins[] = { 0x83, }; 1361 static int jz4775_mac_rmii_pins[] = { 1362 0xa9, 0xab, 0xaa, 0xac, 0xa5, 0xa4, 0xad, 0xae, 0xa6, 0xa8, 1363 }; 1364 static int jz4775_mac_mii_pins[] = { 1365 0x7b, 0x7a, 0x7d, 0x7c, 0xa7, 0x24, 0xaf, 1366 }; 1367 static int jz4775_mac_rgmii_pins[] = { 1368 0xa9, 0x7b, 0x7a, 0xab, 0xaa, 0xac, 0x7d, 0x7c, 0xa5, 0xa4, 1369 0xad, 0xae, 0xa7, 0xa6, 1370 }; 1371 static int jz4775_mac_gmii_pins[] = { 1372 0x31, 0x30, 0x2f, 0x2e, 0x2d, 0x2c, 0x2b, 0x2a, 1373 0xa8, 0x28, 0x24, 0xaf, 1374 }; 1375 static int jz4775_otg_pins[] = { 0x8a, }; 1376 1377 static u8 jz4775_uart3_data_funcs[] = { 0, 1, }; 1378 static u8 jz4775_mac_mii_funcs[] = { 1, 1, 1, 1, 0, 1, 0, }; 1379 static u8 jz4775_mac_rgmii_funcs[] = { 1380 0, 1, 1, 0, 0, 0, 1, 1, 0, 0, 1381 0, 0, 0, 0, 1382 }; 1383 static u8 jz4775_mac_gmii_funcs[] = { 1384 1, 1, 1, 1, 1, 1, 1, 1, 1385 0, 1, 1, 0, 1386 }; 1387 1388 static const struct group_desc jz4775_groups[] = { 1389 INGENIC_PIN_GROUP("uart0-data", jz4775_uart0_data, 0), 1390 INGENIC_PIN_GROUP("uart0-hwflow", jz4775_uart0_hwflow, 0), 1391 INGENIC_PIN_GROUP("uart1-data", jz4775_uart1_data, 0), 1392 INGENIC_PIN_GROUP("uart1-hwflow", jz4775_uart1_hwflow, 0), 1393 INGENIC_PIN_GROUP("uart2-data-c", jz4775_uart2_data_c, 2), 1394 INGENIC_PIN_GROUP("uart2-data-f", jz4775_uart2_data_f, 1), 1395 INGENIC_PIN_GROUP_FUNCS("uart3-data", jz4775_uart3_data, 1396 jz4775_uart3_data_funcs), 1397 INGENIC_PIN_GROUP("ssi-dt-a", jz4775_ssi_dt_a, 2), 1398 INGENIC_PIN_GROUP("ssi-dt-d", jz4775_ssi_dt_d, 1), 1399 INGENIC_PIN_GROUP("ssi-dr-a", jz4775_ssi_dr_a, 2), 1400 INGENIC_PIN_GROUP("ssi-dr-d", jz4775_ssi_dr_d, 1), 1401 INGENIC_PIN_GROUP("ssi-clk-a", jz4775_ssi_clk_a, 2), 1402 INGENIC_PIN_GROUP("ssi-clk-d", jz4775_ssi_clk_d, 1), 1403 INGENIC_PIN_GROUP("ssi-gpc", jz4775_ssi_gpc, 1), 1404 INGENIC_PIN_GROUP("ssi-ce0-a", jz4775_ssi_ce0_a, 2), 1405 INGENIC_PIN_GROUP("ssi-ce0-d", jz4775_ssi_ce0_d, 1), 1406 INGENIC_PIN_GROUP("ssi-ce1", jz4775_ssi_ce1, 1), 1407 INGENIC_PIN_GROUP("mmc0-1bit-a", jz4775_mmc0_1bit_a, 1), 1408 INGENIC_PIN_GROUP("mmc0-4bit-a", jz4775_mmc0_4bit_a, 1), 1409 INGENIC_PIN_GROUP("mmc0-8bit-a", jz4775_mmc0_8bit_a, 1), 1410 INGENIC_PIN_GROUP("mmc0-1bit-e", jz4775_mmc0_1bit_e, 0), 1411 INGENIC_PIN_GROUP("mmc0-4bit-e", jz4775_mmc0_4bit_e, 0), 1412 INGENIC_PIN_GROUP("mmc1-1bit-d", jz4775_mmc1_1bit_d, 0), 1413 INGENIC_PIN_GROUP("mmc1-4bit-d", jz4775_mmc1_4bit_d, 0), 1414 INGENIC_PIN_GROUP("mmc1-1bit-e", jz4775_mmc1_1bit_e, 1), 1415 INGENIC_PIN_GROUP("mmc1-4bit-e", jz4775_mmc1_4bit_e, 1), 1416 INGENIC_PIN_GROUP("mmc2-1bit-b", jz4775_mmc2_1bit_b, 0), 1417 INGENIC_PIN_GROUP("mmc2-4bit-b", jz4775_mmc2_4bit_b, 0), 1418 INGENIC_PIN_GROUP("mmc2-1bit-e", jz4775_mmc2_1bit_e, 2), 1419 INGENIC_PIN_GROUP("mmc2-4bit-e", jz4775_mmc2_4bit_e, 2), 1420 INGENIC_PIN_GROUP("nemc-8bit-data", jz4775_nemc_8bit_data, 0), 1421 INGENIC_PIN_GROUP("nemc-16bit-data", jz4775_nemc_16bit_data, 1), 1422 INGENIC_PIN_GROUP("nemc-cle-ale", jz4775_nemc_cle_ale, 0), 1423 INGENIC_PIN_GROUP("nemc-addr", jz4775_nemc_addr, 0), 1424 INGENIC_PIN_GROUP("nemc-rd-we", jz4775_nemc_rd_we, 0), 1425 INGENIC_PIN_GROUP("nemc-frd-fwe", jz4775_nemc_frd_fwe, 0), 1426 INGENIC_PIN_GROUP("nemc-wait", jz4775_nemc_wait, 0), 1427 INGENIC_PIN_GROUP("nemc-cs1", jz4775_nemc_cs1, 0), 1428 INGENIC_PIN_GROUP("nemc-cs2", jz4775_nemc_cs2, 0), 1429 INGENIC_PIN_GROUP("nemc-cs3", jz4775_nemc_cs3, 0), 1430 INGENIC_PIN_GROUP("i2c0-data", jz4775_i2c0, 0), 1431 INGENIC_PIN_GROUP("i2c1-data", jz4775_i2c1, 0), 1432 INGENIC_PIN_GROUP("i2c2-data", jz4775_i2c2, 1), 1433 INGENIC_PIN_GROUP("i2s-data-tx", jz4775_i2s_data_tx, 1), 1434 INGENIC_PIN_GROUP("i2s-data-rx", jz4775_i2s_data_rx, 1), 1435 INGENIC_PIN_GROUP("i2s-clk-txrx", jz4775_i2s_clk_txrx, 1), 1436 INGENIC_PIN_GROUP("i2s-sysclk", jz4775_i2s_sysclk, 2), 1437 INGENIC_PIN_GROUP("dmic", jz4775_dmic, 1), 1438 INGENIC_PIN_GROUP("cim-data", jz4775_cim, 0), 1439 INGENIC_PIN_GROUP("lcd-8bit", jz4775_lcd_8bit, 0), 1440 INGENIC_PIN_GROUP("lcd-16bit", jz4775_lcd_16bit, 0), 1441 INGENIC_PIN_GROUP("lcd-18bit", jz4775_lcd_18bit, 0), 1442 INGENIC_PIN_GROUP("lcd-24bit", jz4775_lcd_24bit, 0), 1443 INGENIC_PIN_GROUP("lcd-generic", jz4775_lcd_generic, 0), 1444 INGENIC_PIN_GROUP("lcd-special", jz4775_lcd_special, 1), 1445 INGENIC_PIN_GROUP("pwm0", jz4775_pwm_pwm0, 0), 1446 INGENIC_PIN_GROUP("pwm1", jz4775_pwm_pwm1, 0), 1447 INGENIC_PIN_GROUP("pwm2", jz4775_pwm_pwm2, 0), 1448 INGENIC_PIN_GROUP("pwm3", jz4775_pwm_pwm3, 0), 1449 INGENIC_PIN_GROUP("mac-rmii", jz4775_mac_rmii, 0), 1450 INGENIC_PIN_GROUP_FUNCS("mac-mii", jz4775_mac_mii, 1451 jz4775_mac_mii_funcs), 1452 INGENIC_PIN_GROUP_FUNCS("mac-rgmii", jz4775_mac_rgmii, 1453 jz4775_mac_rgmii_funcs), 1454 INGENIC_PIN_GROUP_FUNCS("mac-gmii", jz4775_mac_gmii, 1455 jz4775_mac_gmii_funcs), 1456 INGENIC_PIN_GROUP("otg-vbus", jz4775_otg, 0), 1457 }; 1458 1459 static const char *jz4775_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; 1460 static const char *jz4775_uart1_groups[] = { "uart1-data", "uart1-hwflow", }; 1461 static const char *jz4775_uart2_groups[] = { "uart2-data-c", "uart2-data-f", }; 1462 static const char *jz4775_uart3_groups[] = { "uart3-data", }; 1463 static const char *jz4775_ssi_groups[] = { 1464 "ssi-dt-a", "ssi-dt-d", 1465 "ssi-dr-a", "ssi-dr-d", 1466 "ssi-clk-a", "ssi-clk-d", 1467 "ssi-gpc", 1468 "ssi-ce0-a", "ssi-ce0-d", 1469 "ssi-ce1", 1470 }; 1471 static const char *jz4775_mmc0_groups[] = { 1472 "mmc0-1bit-a", "mmc0-4bit-a", "mmc0-8bit-a", 1473 "mmc0-1bit-e", "mmc0-4bit-e", 1474 }; 1475 static const char *jz4775_mmc1_groups[] = { 1476 "mmc1-1bit-d", "mmc1-4bit-d", 1477 "mmc1-1bit-e", "mmc1-4bit-e", 1478 }; 1479 static const char *jz4775_mmc2_groups[] = { 1480 "mmc2-1bit-b", "mmc2-4bit-b", 1481 "mmc2-1bit-e", "mmc2-4bit-e", 1482 }; 1483 static const char *jz4775_nemc_groups[] = { 1484 "nemc-8bit-data", "nemc-16bit-data", "nemc-cle-ale", 1485 "nemc-addr", "nemc-rd-we", "nemc-frd-fwe", "nemc-wait", 1486 }; 1487 static const char *jz4775_cs1_groups[] = { "nemc-cs1", }; 1488 static const char *jz4775_cs2_groups[] = { "nemc-cs2", }; 1489 static const char *jz4775_cs3_groups[] = { "nemc-cs3", }; 1490 static const char *jz4775_i2c0_groups[] = { "i2c0-data", }; 1491 static const char *jz4775_i2c1_groups[] = { "i2c1-data", }; 1492 static const char *jz4775_i2c2_groups[] = { "i2c2-data", }; 1493 static const char *jz4775_i2s_groups[] = { 1494 "i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-sysclk", 1495 }; 1496 static const char *jz4775_dmic_groups[] = { "dmic", }; 1497 static const char *jz4775_cim_groups[] = { "cim-data", }; 1498 static const char *jz4775_lcd_groups[] = { 1499 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit", 1500 "lcd-special", "lcd-generic", 1501 }; 1502 static const char *jz4775_pwm0_groups[] = { "pwm0", }; 1503 static const char *jz4775_pwm1_groups[] = { "pwm1", }; 1504 static const char *jz4775_pwm2_groups[] = { "pwm2", }; 1505 static const char *jz4775_pwm3_groups[] = { "pwm3", }; 1506 static const char *jz4775_mac_groups[] = { 1507 "mac-rmii", "mac-mii", "mac-rgmii", "mac-gmii", 1508 }; 1509 static const char *jz4775_otg_groups[] = { "otg-vbus", }; 1510 1511 static const struct function_desc jz4775_functions[] = { 1512 { "uart0", jz4775_uart0_groups, ARRAY_SIZE(jz4775_uart0_groups), }, 1513 { "uart1", jz4775_uart1_groups, ARRAY_SIZE(jz4775_uart1_groups), }, 1514 { "uart2", jz4775_uart2_groups, ARRAY_SIZE(jz4775_uart2_groups), }, 1515 { "uart3", jz4775_uart3_groups, ARRAY_SIZE(jz4775_uart3_groups), }, 1516 { "ssi", jz4775_ssi_groups, ARRAY_SIZE(jz4775_ssi_groups), }, 1517 { "mmc0", jz4775_mmc0_groups, ARRAY_SIZE(jz4775_mmc0_groups), }, 1518 { "mmc1", jz4775_mmc1_groups, ARRAY_SIZE(jz4775_mmc1_groups), }, 1519 { "mmc2", jz4775_mmc2_groups, ARRAY_SIZE(jz4775_mmc2_groups), }, 1520 { "nemc", jz4775_nemc_groups, ARRAY_SIZE(jz4775_nemc_groups), }, 1521 { "nemc-cs1", jz4775_cs1_groups, ARRAY_SIZE(jz4775_cs1_groups), }, 1522 { "nemc-cs2", jz4775_cs2_groups, ARRAY_SIZE(jz4775_cs2_groups), }, 1523 { "nemc-cs3", jz4775_cs3_groups, ARRAY_SIZE(jz4775_cs3_groups), }, 1524 { "i2c0", jz4775_i2c0_groups, ARRAY_SIZE(jz4775_i2c0_groups), }, 1525 { "i2c1", jz4775_i2c1_groups, ARRAY_SIZE(jz4775_i2c1_groups), }, 1526 { "i2c2", jz4775_i2c2_groups, ARRAY_SIZE(jz4775_i2c2_groups), }, 1527 { "i2s", jz4775_i2s_groups, ARRAY_SIZE(jz4775_i2s_groups), }, 1528 { "dmic", jz4775_dmic_groups, ARRAY_SIZE(jz4775_dmic_groups), }, 1529 { "cim", jz4775_cim_groups, ARRAY_SIZE(jz4775_cim_groups), }, 1530 { "lcd", jz4775_lcd_groups, ARRAY_SIZE(jz4775_lcd_groups), }, 1531 { "pwm0", jz4775_pwm0_groups, ARRAY_SIZE(jz4775_pwm0_groups), }, 1532 { "pwm1", jz4775_pwm1_groups, ARRAY_SIZE(jz4775_pwm1_groups), }, 1533 { "pwm2", jz4775_pwm2_groups, ARRAY_SIZE(jz4775_pwm2_groups), }, 1534 { "pwm3", jz4775_pwm3_groups, ARRAY_SIZE(jz4775_pwm3_groups), }, 1535 { "mac", jz4775_mac_groups, ARRAY_SIZE(jz4775_mac_groups), }, 1536 { "otg", jz4775_otg_groups, ARRAY_SIZE(jz4775_otg_groups), }, 1537 }; 1538 1539 static const struct ingenic_chip_info jz4775_chip_info = { 1540 .num_chips = 7, 1541 .reg_offset = 0x100, 1542 .version = ID_JZ4775, 1543 .groups = jz4775_groups, 1544 .num_groups = ARRAY_SIZE(jz4775_groups), 1545 .functions = jz4775_functions, 1546 .num_functions = ARRAY_SIZE(jz4775_functions), 1547 .pull_ups = jz4775_pull_ups, 1548 .pull_downs = jz4775_pull_downs, 1549 }; 1550 1551 static const u32 jz4780_pull_ups[6] = { 1552 0x3fffffff, 0xfff0f3fc, 0x0fffffff, 0xffff4fff, 0xfffffb7c, 0x7fa7f00f, 1553 }; 1554 1555 static const u32 jz4780_pull_downs[6] = { 1556 0x00000000, 0x000f0c03, 0x00000000, 0x0000b000, 0x00000483, 0x00580ff0, 1557 }; 1558 1559 static int jz4780_uart2_data_pins[] = { 0x66, 0x67, }; 1560 static int jz4780_uart2_hwflow_pins[] = { 0x65, 0x64, }; 1561 static int jz4780_uart4_data_pins[] = { 0x54, 0x4a, }; 1562 static int jz4780_ssi0_dt_a_19_pins[] = { 0x13, }; 1563 static int jz4780_ssi0_dt_a_21_pins[] = { 0x15, }; 1564 static int jz4780_ssi0_dt_a_28_pins[] = { 0x1c, }; 1565 static int jz4780_ssi0_dt_b_pins[] = { 0x3d, }; 1566 static int jz4780_ssi0_dt_d_pins[] = { 0x79, }; 1567 static int jz4780_ssi0_dr_a_20_pins[] = { 0x14, }; 1568 static int jz4780_ssi0_dr_a_27_pins[] = { 0x1b, }; 1569 static int jz4780_ssi0_dr_b_pins[] = { 0x34, }; 1570 static int jz4780_ssi0_dr_d_pins[] = { 0x74, }; 1571 static int jz4780_ssi0_clk_a_pins[] = { 0x12, }; 1572 static int jz4780_ssi0_clk_b_5_pins[] = { 0x25, }; 1573 static int jz4780_ssi0_clk_b_28_pins[] = { 0x3c, }; 1574 static int jz4780_ssi0_clk_d_pins[] = { 0x78, }; 1575 static int jz4780_ssi0_gpc_b_pins[] = { 0x3e, }; 1576 static int jz4780_ssi0_gpc_d_pins[] = { 0x76, }; 1577 static int jz4780_ssi0_ce0_a_23_pins[] = { 0x17, }; 1578 static int jz4780_ssi0_ce0_a_25_pins[] = { 0x19, }; 1579 static int jz4780_ssi0_ce0_b_pins[] = { 0x3f, }; 1580 static int jz4780_ssi0_ce0_d_pins[] = { 0x77, }; 1581 static int jz4780_ssi0_ce1_b_pins[] = { 0x35, }; 1582 static int jz4780_ssi0_ce1_d_pins[] = { 0x75, }; 1583 static int jz4780_ssi1_dt_b_pins[] = { 0x3d, }; 1584 static int jz4780_ssi1_dt_d_pins[] = { 0x79, }; 1585 static int jz4780_ssi1_dr_b_pins[] = { 0x34, }; 1586 static int jz4780_ssi1_dr_d_pins[] = { 0x74, }; 1587 static int jz4780_ssi1_clk_b_pins[] = { 0x3c, }; 1588 static int jz4780_ssi1_clk_d_pins[] = { 0x78, }; 1589 static int jz4780_ssi1_gpc_b_pins[] = { 0x3e, }; 1590 static int jz4780_ssi1_gpc_d_pins[] = { 0x76, }; 1591 static int jz4780_ssi1_ce0_b_pins[] = { 0x3f, }; 1592 static int jz4780_ssi1_ce0_d_pins[] = { 0x77, }; 1593 static int jz4780_ssi1_ce1_b_pins[] = { 0x35, }; 1594 static int jz4780_ssi1_ce1_d_pins[] = { 0x75, }; 1595 static int jz4780_mmc0_8bit_a_pins[] = { 0x04, 0x05, 0x06, 0x07, 0x18, }; 1596 static int jz4780_i2c3_pins[] = { 0x6a, 0x6b, }; 1597 static int jz4780_i2c4_e_pins[] = { 0x8c, 0x8d, }; 1598 static int jz4780_i2c4_f_pins[] = { 0xb9, 0xb8, }; 1599 static int jz4780_i2s_data_tx_pins[] = { 0x87, }; 1600 static int jz4780_i2s_data_rx_pins[] = { 0x86, }; 1601 static int jz4780_i2s_clk_txrx_pins[] = { 0x6c, 0x6d, }; 1602 static int jz4780_i2s_clk_rx_pins[] = { 0x88, 0x89, }; 1603 static int jz4780_i2s_sysclk_pins[] = { 0x85, }; 1604 static int jz4780_dmic_pins[] = { 0x32, 0x33, }; 1605 static int jz4780_hdmi_ddc_pins[] = { 0xb9, 0xb8, }; 1606 1607 static u8 jz4780_i2s_clk_txrx_funcs[] = { 1, 0, }; 1608 1609 static const struct group_desc jz4780_groups[] = { 1610 INGENIC_PIN_GROUP("uart0-data", jz4770_uart0_data, 0), 1611 INGENIC_PIN_GROUP("uart0-hwflow", jz4770_uart0_hwflow, 0), 1612 INGENIC_PIN_GROUP("uart1-data", jz4770_uart1_data, 0), 1613 INGENIC_PIN_GROUP("uart1-hwflow", jz4770_uart1_hwflow, 0), 1614 INGENIC_PIN_GROUP("uart2-data", jz4780_uart2_data, 1), 1615 INGENIC_PIN_GROUP("uart2-hwflow", jz4780_uart2_hwflow, 1), 1616 INGENIC_PIN_GROUP_FUNCS("uart3-data", jz4770_uart3_data, 1617 jz4760_uart3_data_funcs), 1618 INGENIC_PIN_GROUP("uart3-hwflow", jz4770_uart3_hwflow, 0), 1619 INGENIC_PIN_GROUP("uart4-data", jz4780_uart4_data, 2), 1620 INGENIC_PIN_GROUP("ssi0-dt-a-19", jz4780_ssi0_dt_a_19, 2), 1621 INGENIC_PIN_GROUP("ssi0-dt-a-21", jz4780_ssi0_dt_a_21, 2), 1622 INGENIC_PIN_GROUP("ssi0-dt-a-28", jz4780_ssi0_dt_a_28, 2), 1623 INGENIC_PIN_GROUP("ssi0-dt-b", jz4780_ssi0_dt_b, 1), 1624 INGENIC_PIN_GROUP("ssi0-dt-d", jz4780_ssi0_dt_d, 1), 1625 INGENIC_PIN_GROUP("ssi0-dt-e", jz4770_ssi0_dt_e, 0), 1626 INGENIC_PIN_GROUP("ssi0-dr-a-20", jz4780_ssi0_dr_a_20, 2), 1627 INGENIC_PIN_GROUP("ssi0-dr-a-27", jz4780_ssi0_dr_a_27, 2), 1628 INGENIC_PIN_GROUP("ssi0-dr-b", jz4780_ssi0_dr_b, 1), 1629 INGENIC_PIN_GROUP("ssi0-dr-d", jz4780_ssi0_dr_d, 1), 1630 INGENIC_PIN_GROUP("ssi0-dr-e", jz4770_ssi0_dr_e, 0), 1631 INGENIC_PIN_GROUP("ssi0-clk-a", jz4780_ssi0_clk_a, 2), 1632 INGENIC_PIN_GROUP("ssi0-clk-b-5", jz4780_ssi0_clk_b_5, 1), 1633 INGENIC_PIN_GROUP("ssi0-clk-b-28", jz4780_ssi0_clk_b_28, 1), 1634 INGENIC_PIN_GROUP("ssi0-clk-d", jz4780_ssi0_clk_d, 1), 1635 INGENIC_PIN_GROUP("ssi0-clk-e", jz4770_ssi0_clk_e, 0), 1636 INGENIC_PIN_GROUP("ssi0-gpc-b", jz4780_ssi0_gpc_b, 1), 1637 INGENIC_PIN_GROUP("ssi0-gpc-d", jz4780_ssi0_gpc_d, 1), 1638 INGENIC_PIN_GROUP("ssi0-gpc-e", jz4770_ssi0_gpc_e, 0), 1639 INGENIC_PIN_GROUP("ssi0-ce0-a-23", jz4780_ssi0_ce0_a_23, 2), 1640 INGENIC_PIN_GROUP("ssi0-ce0-a-25", jz4780_ssi0_ce0_a_25, 2), 1641 INGENIC_PIN_GROUP("ssi0-ce0-b", jz4780_ssi0_ce0_b, 1), 1642 INGENIC_PIN_GROUP("ssi0-ce0-d", jz4780_ssi0_ce0_d, 1), 1643 INGENIC_PIN_GROUP("ssi0-ce0-e", jz4770_ssi0_ce0_e, 0), 1644 INGENIC_PIN_GROUP("ssi0-ce1-b", jz4780_ssi0_ce1_b, 1), 1645 INGENIC_PIN_GROUP("ssi0-ce1-d", jz4780_ssi0_ce1_d, 1), 1646 INGENIC_PIN_GROUP("ssi0-ce1-e", jz4770_ssi0_ce1_e, 0), 1647 INGENIC_PIN_GROUP("ssi1-dt-b", jz4780_ssi1_dt_b, 2), 1648 INGENIC_PIN_GROUP("ssi1-dt-d", jz4780_ssi1_dt_d, 2), 1649 INGENIC_PIN_GROUP("ssi1-dt-e", jz4770_ssi1_dt_e, 1), 1650 INGENIC_PIN_GROUP("ssi1-dr-b", jz4780_ssi1_dr_b, 2), 1651 INGENIC_PIN_GROUP("ssi1-dr-d", jz4780_ssi1_dr_d, 2), 1652 INGENIC_PIN_GROUP("ssi1-dr-e", jz4770_ssi1_dr_e, 1), 1653 INGENIC_PIN_GROUP("ssi1-clk-b", jz4780_ssi1_clk_b, 2), 1654 INGENIC_PIN_GROUP("ssi1-clk-d", jz4780_ssi1_clk_d, 2), 1655 INGENIC_PIN_GROUP("ssi1-clk-e", jz4770_ssi1_clk_e, 1), 1656 INGENIC_PIN_GROUP("ssi1-gpc-b", jz4780_ssi1_gpc_b, 2), 1657 INGENIC_PIN_GROUP("ssi1-gpc-d", jz4780_ssi1_gpc_d, 2), 1658 INGENIC_PIN_GROUP("ssi1-gpc-e", jz4770_ssi1_gpc_e, 1), 1659 INGENIC_PIN_GROUP("ssi1-ce0-b", jz4780_ssi1_ce0_b, 2), 1660 INGENIC_PIN_GROUP("ssi1-ce0-d", jz4780_ssi1_ce0_d, 2), 1661 INGENIC_PIN_GROUP("ssi1-ce0-e", jz4770_ssi1_ce0_e, 1), 1662 INGENIC_PIN_GROUP("ssi1-ce1-b", jz4780_ssi1_ce1_b, 2), 1663 INGENIC_PIN_GROUP("ssi1-ce1-d", jz4780_ssi1_ce1_d, 2), 1664 INGENIC_PIN_GROUP("ssi1-ce1-e", jz4770_ssi1_ce1_e, 1), 1665 INGENIC_PIN_GROUP_FUNCS("mmc0-1bit-a", jz4770_mmc0_1bit_a, 1666 jz4760_mmc0_1bit_a_funcs), 1667 INGENIC_PIN_GROUP("mmc0-4bit-a", jz4770_mmc0_4bit_a, 1), 1668 INGENIC_PIN_GROUP("mmc0-8bit-a", jz4780_mmc0_8bit_a, 1), 1669 INGENIC_PIN_GROUP("mmc0-1bit-e", jz4770_mmc0_1bit_e, 0), 1670 INGENIC_PIN_GROUP("mmc0-4bit-e", jz4770_mmc0_4bit_e, 0), 1671 INGENIC_PIN_GROUP("mmc1-1bit-d", jz4770_mmc1_1bit_d, 0), 1672 INGENIC_PIN_GROUP("mmc1-4bit-d", jz4770_mmc1_4bit_d, 0), 1673 INGENIC_PIN_GROUP("mmc1-1bit-e", jz4770_mmc1_1bit_e, 1), 1674 INGENIC_PIN_GROUP("mmc1-4bit-e", jz4770_mmc1_4bit_e, 1), 1675 INGENIC_PIN_GROUP("mmc2-1bit-b", jz4770_mmc2_1bit_b, 0), 1676 INGENIC_PIN_GROUP("mmc2-4bit-b", jz4770_mmc2_4bit_b, 0), 1677 INGENIC_PIN_GROUP("mmc2-1bit-e", jz4770_mmc2_1bit_e, 2), 1678 INGENIC_PIN_GROUP("mmc2-4bit-e", jz4770_mmc2_4bit_e, 2), 1679 INGENIC_PIN_GROUP("nemc-data", jz4770_nemc_8bit_data, 0), 1680 INGENIC_PIN_GROUP("nemc-cle-ale", jz4770_nemc_cle_ale, 0), 1681 INGENIC_PIN_GROUP("nemc-addr", jz4770_nemc_addr, 0), 1682 INGENIC_PIN_GROUP("nemc-rd-we", jz4770_nemc_rd_we, 0), 1683 INGENIC_PIN_GROUP("nemc-frd-fwe", jz4770_nemc_frd_fwe, 0), 1684 INGENIC_PIN_GROUP("nemc-wait", jz4770_nemc_wait, 0), 1685 INGENIC_PIN_GROUP("nemc-cs1", jz4770_nemc_cs1, 0), 1686 INGENIC_PIN_GROUP("nemc-cs2", jz4770_nemc_cs2, 0), 1687 INGENIC_PIN_GROUP("nemc-cs3", jz4770_nemc_cs3, 0), 1688 INGENIC_PIN_GROUP("nemc-cs4", jz4770_nemc_cs4, 0), 1689 INGENIC_PIN_GROUP("nemc-cs5", jz4770_nemc_cs5, 0), 1690 INGENIC_PIN_GROUP("nemc-cs6", jz4770_nemc_cs6, 0), 1691 INGENIC_PIN_GROUP("i2c0-data", jz4770_i2c0, 0), 1692 INGENIC_PIN_GROUP("i2c1-data", jz4770_i2c1, 0), 1693 INGENIC_PIN_GROUP("i2c2-data", jz4770_i2c2, 2), 1694 INGENIC_PIN_GROUP("i2c3-data", jz4780_i2c3, 1), 1695 INGENIC_PIN_GROUP("i2c4-data-e", jz4780_i2c4_e, 1), 1696 INGENIC_PIN_GROUP("i2c4-data-f", jz4780_i2c4_f, 1), 1697 INGENIC_PIN_GROUP("i2s-data-tx", jz4780_i2s_data_tx, 0), 1698 INGENIC_PIN_GROUP("i2s-data-rx", jz4780_i2s_data_rx, 0), 1699 INGENIC_PIN_GROUP_FUNCS("i2s-clk-txrx", jz4780_i2s_clk_txrx, 1700 jz4780_i2s_clk_txrx_funcs), 1701 INGENIC_PIN_GROUP("i2s-clk-rx", jz4780_i2s_clk_rx, 1), 1702 INGENIC_PIN_GROUP("i2s-sysclk", jz4780_i2s_sysclk, 2), 1703 INGENIC_PIN_GROUP("dmic", jz4780_dmic, 1), 1704 INGENIC_PIN_GROUP("hdmi-ddc", jz4780_hdmi_ddc, 0), 1705 INGENIC_PIN_GROUP("cim-data", jz4770_cim_8bit, 0), 1706 INGENIC_PIN_GROUP("cim-data-12bit", jz4770_cim_12bit, 0), 1707 INGENIC_PIN_GROUP("lcd-8bit", jz4770_lcd_8bit, 0), 1708 INGENIC_PIN_GROUP("lcd-16bit", jz4770_lcd_16bit, 0), 1709 INGENIC_PIN_GROUP("lcd-18bit", jz4770_lcd_18bit, 0), 1710 INGENIC_PIN_GROUP("lcd-24bit", jz4770_lcd_24bit, 0), 1711 INGENIC_PIN_GROUP("lcd-special", jz4770_lcd_special, 1), 1712 INGENIC_PIN_GROUP("lcd-generic", jz4770_lcd_generic, 0), 1713 INGENIC_PIN_GROUP("pwm0", jz4770_pwm_pwm0, 0), 1714 INGENIC_PIN_GROUP("pwm1", jz4770_pwm_pwm1, 0), 1715 INGENIC_PIN_GROUP("pwm2", jz4770_pwm_pwm2, 0), 1716 INGENIC_PIN_GROUP("pwm3", jz4770_pwm_pwm3, 0), 1717 INGENIC_PIN_GROUP("pwm4", jz4770_pwm_pwm4, 0), 1718 INGENIC_PIN_GROUP("pwm5", jz4770_pwm_pwm5, 0), 1719 INGENIC_PIN_GROUP("pwm6", jz4770_pwm_pwm6, 0), 1720 INGENIC_PIN_GROUP("pwm7", jz4770_pwm_pwm7, 0), 1721 }; 1722 1723 static const char *jz4780_uart2_groups[] = { "uart2-data", "uart2-hwflow", }; 1724 static const char *jz4780_uart4_groups[] = { "uart4-data", }; 1725 static const char *jz4780_ssi0_groups[] = { 1726 "ssi0-dt-a-19", "ssi0-dt-a-21", "ssi0-dt-a-28", "ssi0-dt-b", "ssi0-dt-d", "ssi0-dt-e", 1727 "ssi0-dr-a-20", "ssi0-dr-a-27", "ssi0-dr-b", "ssi0-dr-d", "ssi0-dr-e", 1728 "ssi0-clk-a", "ssi0-clk-b-5", "ssi0-clk-b-28", "ssi0-clk-d", "ssi0-clk-e", 1729 "ssi0-gpc-b", "ssi0-gpc-d", "ssi0-gpc-e", 1730 "ssi0-ce0-a-23", "ssi0-ce0-a-25", "ssi0-ce0-b", "ssi0-ce0-d", "ssi0-ce0-e", 1731 "ssi0-ce1-b", "ssi0-ce1-d", "ssi0-ce1-e", 1732 }; 1733 static const char *jz4780_ssi1_groups[] = { 1734 "ssi1-dt-b", "ssi1-dt-d", "ssi1-dt-e", 1735 "ssi1-dr-b", "ssi1-dr-d", "ssi1-dr-e", 1736 "ssi1-clk-b", "ssi1-clk-d", "ssi1-clk-e", 1737 "ssi1-gpc-b", "ssi1-gpc-d", "ssi1-gpc-e", 1738 "ssi1-ce0-b", "ssi1-ce0-d", "ssi1-ce0-e", 1739 "ssi1-ce1-b", "ssi1-ce1-d", "ssi1-ce1-e", 1740 }; 1741 static const char *jz4780_mmc0_groups[] = { 1742 "mmc0-1bit-a", "mmc0-4bit-a", "mmc0-8bit-a", 1743 "mmc0-1bit-e", "mmc0-4bit-e", 1744 }; 1745 static const char *jz4780_mmc1_groups[] = { 1746 "mmc1-1bit-d", "mmc1-4bit-d", "mmc1-1bit-e", "mmc1-4bit-e", 1747 }; 1748 static const char *jz4780_mmc2_groups[] = { 1749 "mmc2-1bit-b", "mmc2-4bit-b", "mmc2-1bit-e", "mmc2-4bit-e", 1750 }; 1751 static const char *jz4780_nemc_groups[] = { 1752 "nemc-data", "nemc-cle-ale", "nemc-addr", 1753 "nemc-rd-we", "nemc-frd-fwe", "nemc-wait", 1754 }; 1755 static const char *jz4780_i2c3_groups[] = { "i2c3-data", }; 1756 static const char *jz4780_i2c4_groups[] = { "i2c4-data-e", "i2c4-data-f", }; 1757 static const char *jz4780_i2s_groups[] = { 1758 "i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-clk-rx", "i2s-sysclk", 1759 }; 1760 static const char *jz4780_dmic_groups[] = { "dmic", }; 1761 static const char *jz4780_cim_groups[] = { "cim-data", }; 1762 static const char *jz4780_hdmi_ddc_groups[] = { "hdmi-ddc", }; 1763 1764 static const struct function_desc jz4780_functions[] = { 1765 { "uart0", jz4770_uart0_groups, ARRAY_SIZE(jz4770_uart0_groups), }, 1766 { "uart1", jz4770_uart1_groups, ARRAY_SIZE(jz4770_uart1_groups), }, 1767 { "uart2", jz4780_uart2_groups, ARRAY_SIZE(jz4780_uart2_groups), }, 1768 { "uart3", jz4770_uart3_groups, ARRAY_SIZE(jz4770_uart3_groups), }, 1769 { "uart4", jz4780_uart4_groups, ARRAY_SIZE(jz4780_uart4_groups), }, 1770 { "ssi0", jz4780_ssi0_groups, ARRAY_SIZE(jz4780_ssi0_groups), }, 1771 { "ssi1", jz4780_ssi1_groups, ARRAY_SIZE(jz4780_ssi1_groups), }, 1772 { "mmc0", jz4780_mmc0_groups, ARRAY_SIZE(jz4780_mmc0_groups), }, 1773 { "mmc1", jz4780_mmc1_groups, ARRAY_SIZE(jz4780_mmc1_groups), }, 1774 { "mmc2", jz4780_mmc2_groups, ARRAY_SIZE(jz4780_mmc2_groups), }, 1775 { "nemc", jz4780_nemc_groups, ARRAY_SIZE(jz4780_nemc_groups), }, 1776 { "nemc-cs1", jz4770_cs1_groups, ARRAY_SIZE(jz4770_cs1_groups), }, 1777 { "nemc-cs2", jz4770_cs2_groups, ARRAY_SIZE(jz4770_cs2_groups), }, 1778 { "nemc-cs3", jz4770_cs3_groups, ARRAY_SIZE(jz4770_cs3_groups), }, 1779 { "nemc-cs4", jz4770_cs4_groups, ARRAY_SIZE(jz4770_cs4_groups), }, 1780 { "nemc-cs5", jz4770_cs5_groups, ARRAY_SIZE(jz4770_cs5_groups), }, 1781 { "nemc-cs6", jz4770_cs6_groups, ARRAY_SIZE(jz4770_cs6_groups), }, 1782 { "i2c0", jz4770_i2c0_groups, ARRAY_SIZE(jz4770_i2c0_groups), }, 1783 { "i2c1", jz4770_i2c1_groups, ARRAY_SIZE(jz4770_i2c1_groups), }, 1784 { "i2c2", jz4770_i2c2_groups, ARRAY_SIZE(jz4770_i2c2_groups), }, 1785 { "i2c3", jz4780_i2c3_groups, ARRAY_SIZE(jz4780_i2c3_groups), }, 1786 { "i2c4", jz4780_i2c4_groups, ARRAY_SIZE(jz4780_i2c4_groups), }, 1787 { "i2s", jz4780_i2s_groups, ARRAY_SIZE(jz4780_i2s_groups), }, 1788 { "dmic", jz4780_dmic_groups, ARRAY_SIZE(jz4780_dmic_groups), }, 1789 { "cim", jz4780_cim_groups, ARRAY_SIZE(jz4780_cim_groups), }, 1790 { "lcd", jz4770_lcd_groups, ARRAY_SIZE(jz4770_lcd_groups), }, 1791 { "pwm0", jz4770_pwm0_groups, ARRAY_SIZE(jz4770_pwm0_groups), }, 1792 { "pwm1", jz4770_pwm1_groups, ARRAY_SIZE(jz4770_pwm1_groups), }, 1793 { "pwm2", jz4770_pwm2_groups, ARRAY_SIZE(jz4770_pwm2_groups), }, 1794 { "pwm3", jz4770_pwm3_groups, ARRAY_SIZE(jz4770_pwm3_groups), }, 1795 { "pwm4", jz4770_pwm4_groups, ARRAY_SIZE(jz4770_pwm4_groups), }, 1796 { "pwm5", jz4770_pwm5_groups, ARRAY_SIZE(jz4770_pwm5_groups), }, 1797 { "pwm6", jz4770_pwm6_groups, ARRAY_SIZE(jz4770_pwm6_groups), }, 1798 { "pwm7", jz4770_pwm7_groups, ARRAY_SIZE(jz4770_pwm7_groups), }, 1799 { "hdmi-ddc", jz4780_hdmi_ddc_groups, 1800 ARRAY_SIZE(jz4780_hdmi_ddc_groups), }, 1801 }; 1802 1803 static const struct ingenic_chip_info jz4780_chip_info = { 1804 .num_chips = 6, 1805 .reg_offset = 0x100, 1806 .version = ID_JZ4780, 1807 .groups = jz4780_groups, 1808 .num_groups = ARRAY_SIZE(jz4780_groups), 1809 .functions = jz4780_functions, 1810 .num_functions = ARRAY_SIZE(jz4780_functions), 1811 .pull_ups = jz4780_pull_ups, 1812 .pull_downs = jz4780_pull_downs, 1813 }; 1814 1815 static const u32 x1000_pull_ups[4] = { 1816 0xffffffff, 0xfdffffff, 0x0dffffff, 0x0000003f, 1817 }; 1818 1819 static const u32 x1000_pull_downs[4] = { 1820 0x00000000, 0x02000000, 0x02000000, 0x00000000, 1821 }; 1822 1823 static int x1000_uart0_data_pins[] = { 0x4a, 0x4b, }; 1824 static int x1000_uart0_hwflow_pins[] = { 0x4c, 0x4d, }; 1825 static int x1000_uart1_data_a_pins[] = { 0x04, 0x05, }; 1826 static int x1000_uart1_data_d_pins[] = { 0x62, 0x63, }; 1827 static int x1000_uart1_hwflow_pins[] = { 0x64, 0x65, }; 1828 static int x1000_uart2_data_a_pins[] = { 0x02, 0x03, }; 1829 static int x1000_uart2_data_d_pins[] = { 0x65, 0x64, }; 1830 static int x1000_sfc_pins[] = { 0x1d, 0x1c, 0x1e, 0x1f, 0x1a, 0x1b, }; 1831 static int x1000_ssi_dt_a_22_pins[] = { 0x16, }; 1832 static int x1000_ssi_dt_a_29_pins[] = { 0x1d, }; 1833 static int x1000_ssi_dt_d_pins[] = { 0x62, }; 1834 static int x1000_ssi_dr_a_23_pins[] = { 0x17, }; 1835 static int x1000_ssi_dr_a_28_pins[] = { 0x1c, }; 1836 static int x1000_ssi_dr_d_pins[] = { 0x63, }; 1837 static int x1000_ssi_clk_a_24_pins[] = { 0x18, }; 1838 static int x1000_ssi_clk_a_26_pins[] = { 0x1a, }; 1839 static int x1000_ssi_clk_d_pins[] = { 0x60, }; 1840 static int x1000_ssi_gpc_a_20_pins[] = { 0x14, }; 1841 static int x1000_ssi_gpc_a_31_pins[] = { 0x1f, }; 1842 static int x1000_ssi_ce0_a_25_pins[] = { 0x19, }; 1843 static int x1000_ssi_ce0_a_27_pins[] = { 0x1b, }; 1844 static int x1000_ssi_ce0_d_pins[] = { 0x61, }; 1845 static int x1000_ssi_ce1_a_21_pins[] = { 0x15, }; 1846 static int x1000_ssi_ce1_a_30_pins[] = { 0x1e, }; 1847 static int x1000_mmc0_1bit_pins[] = { 0x18, 0x19, 0x17, }; 1848 static int x1000_mmc0_4bit_pins[] = { 0x16, 0x15, 0x14, }; 1849 static int x1000_mmc0_8bit_pins[] = { 0x13, 0x12, 0x11, 0x10, }; 1850 static int x1000_mmc1_1bit_pins[] = { 0x40, 0x41, 0x42, }; 1851 static int x1000_mmc1_4bit_pins[] = { 0x43, 0x44, 0x45, }; 1852 static int x1000_emc_8bit_data_pins[] = { 1853 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 1854 }; 1855 static int x1000_emc_16bit_data_pins[] = { 1856 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 1857 }; 1858 static int x1000_emc_addr_pins[] = { 1859 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 1860 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 1861 }; 1862 static int x1000_emc_rd_we_pins[] = { 0x30, 0x31, }; 1863 static int x1000_emc_wait_pins[] = { 0x34, }; 1864 static int x1000_emc_cs1_pins[] = { 0x32, }; 1865 static int x1000_emc_cs2_pins[] = { 0x33, }; 1866 static int x1000_i2c0_pins[] = { 0x38, 0x37, }; 1867 static int x1000_i2c1_a_pins[] = { 0x01, 0x00, }; 1868 static int x1000_i2c1_c_pins[] = { 0x5b, 0x5a, }; 1869 static int x1000_i2c2_pins[] = { 0x61, 0x60, }; 1870 static int x1000_i2s_data_tx_pins[] = { 0x24, }; 1871 static int x1000_i2s_data_rx_pins[] = { 0x23, }; 1872 static int x1000_i2s_clk_txrx_pins[] = { 0x21, 0x22, }; 1873 static int x1000_i2s_sysclk_pins[] = { 0x20, }; 1874 static int x1000_dmic0_pins[] = { 0x35, 0x36, }; 1875 static int x1000_dmic1_pins[] = { 0x25, }; 1876 static int x1000_cim_pins[] = { 1877 0x08, 0x09, 0x0a, 0x0b, 1878 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 0x0d, 0x0c, 1879 }; 1880 static int x1000_lcd_8bit_pins[] = { 1881 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 1882 0x30, 0x31, 0x32, 0x33, 0x34, 1883 }; 1884 static int x1000_lcd_16bit_pins[] = { 1885 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 1886 }; 1887 static int x1000_pwm_pwm0_pins[] = { 0x59, }; 1888 static int x1000_pwm_pwm1_pins[] = { 0x5a, }; 1889 static int x1000_pwm_pwm2_pins[] = { 0x5b, }; 1890 static int x1000_pwm_pwm3_pins[] = { 0x26, }; 1891 static int x1000_pwm_pwm4_pins[] = { 0x58, }; 1892 static int x1000_mac_pins[] = { 1893 0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x26, 1894 }; 1895 1896 static const struct group_desc x1000_groups[] = { 1897 INGENIC_PIN_GROUP("uart0-data", x1000_uart0_data, 0), 1898 INGENIC_PIN_GROUP("uart0-hwflow", x1000_uart0_hwflow, 0), 1899 INGENIC_PIN_GROUP("uart1-data-a", x1000_uart1_data_a, 2), 1900 INGENIC_PIN_GROUP("uart1-data-d", x1000_uart1_data_d, 1), 1901 INGENIC_PIN_GROUP("uart1-hwflow", x1000_uart1_hwflow, 1), 1902 INGENIC_PIN_GROUP("uart2-data-a", x1000_uart2_data_a, 2), 1903 INGENIC_PIN_GROUP("uart2-data-d", x1000_uart2_data_d, 0), 1904 INGENIC_PIN_GROUP("sfc", x1000_sfc, 1), 1905 INGENIC_PIN_GROUP("ssi-dt-a-22", x1000_ssi_dt_a_22, 2), 1906 INGENIC_PIN_GROUP("ssi-dt-a-29", x1000_ssi_dt_a_29, 2), 1907 INGENIC_PIN_GROUP("ssi-dt-d", x1000_ssi_dt_d, 0), 1908 INGENIC_PIN_GROUP("ssi-dr-a-23", x1000_ssi_dr_a_23, 2), 1909 INGENIC_PIN_GROUP("ssi-dr-a-28", x1000_ssi_dr_a_28, 2), 1910 INGENIC_PIN_GROUP("ssi-dr-d", x1000_ssi_dr_d, 0), 1911 INGENIC_PIN_GROUP("ssi-clk-a-24", x1000_ssi_clk_a_24, 2), 1912 INGENIC_PIN_GROUP("ssi-clk-a-26", x1000_ssi_clk_a_26, 2), 1913 INGENIC_PIN_GROUP("ssi-clk-d", x1000_ssi_clk_d, 0), 1914 INGENIC_PIN_GROUP("ssi-gpc-a-20", x1000_ssi_gpc_a_20, 2), 1915 INGENIC_PIN_GROUP("ssi-gpc-a-31", x1000_ssi_gpc_a_31, 2), 1916 INGENIC_PIN_GROUP("ssi-ce0-a-25", x1000_ssi_ce0_a_25, 2), 1917 INGENIC_PIN_GROUP("ssi-ce0-a-27", x1000_ssi_ce0_a_27, 2), 1918 INGENIC_PIN_GROUP("ssi-ce0-d", x1000_ssi_ce0_d, 0), 1919 INGENIC_PIN_GROUP("ssi-ce1-a-21", x1000_ssi_ce1_a_21, 2), 1920 INGENIC_PIN_GROUP("ssi-ce1-a-30", x1000_ssi_ce1_a_30, 2), 1921 INGENIC_PIN_GROUP("mmc0-1bit", x1000_mmc0_1bit, 1), 1922 INGENIC_PIN_GROUP("mmc0-4bit", x1000_mmc0_4bit, 1), 1923 INGENIC_PIN_GROUP("mmc0-8bit", x1000_mmc0_8bit, 1), 1924 INGENIC_PIN_GROUP("mmc1-1bit", x1000_mmc1_1bit, 0), 1925 INGENIC_PIN_GROUP("mmc1-4bit", x1000_mmc1_4bit, 0), 1926 INGENIC_PIN_GROUP("emc-8bit-data", x1000_emc_8bit_data, 0), 1927 INGENIC_PIN_GROUP("emc-16bit-data", x1000_emc_16bit_data, 0), 1928 INGENIC_PIN_GROUP("emc-addr", x1000_emc_addr, 0), 1929 INGENIC_PIN_GROUP("emc-rd-we", x1000_emc_rd_we, 0), 1930 INGENIC_PIN_GROUP("emc-wait", x1000_emc_wait, 0), 1931 INGENIC_PIN_GROUP("emc-cs1", x1000_emc_cs1, 0), 1932 INGENIC_PIN_GROUP("emc-cs2", x1000_emc_cs2, 0), 1933 INGENIC_PIN_GROUP("i2c0-data", x1000_i2c0, 0), 1934 INGENIC_PIN_GROUP("i2c1-data-a", x1000_i2c1_a, 2), 1935 INGENIC_PIN_GROUP("i2c1-data-c", x1000_i2c1_c, 0), 1936 INGENIC_PIN_GROUP("i2c2-data", x1000_i2c2, 1), 1937 INGENIC_PIN_GROUP("i2s-data-tx", x1000_i2s_data_tx, 1), 1938 INGENIC_PIN_GROUP("i2s-data-rx", x1000_i2s_data_rx, 1), 1939 INGENIC_PIN_GROUP("i2s-clk-txrx", x1000_i2s_clk_txrx, 1), 1940 INGENIC_PIN_GROUP("i2s-sysclk", x1000_i2s_sysclk, 1), 1941 INGENIC_PIN_GROUP("dmic0", x1000_dmic0, 0), 1942 INGENIC_PIN_GROUP("dmic1", x1000_dmic1, 1), 1943 INGENIC_PIN_GROUP("cim-data", x1000_cim, 2), 1944 INGENIC_PIN_GROUP("lcd-8bit", x1000_lcd_8bit, 1), 1945 INGENIC_PIN_GROUP("lcd-16bit", x1000_lcd_16bit, 1), 1946 INGENIC_PIN_GROUP("pwm0", x1000_pwm_pwm0, 0), 1947 INGENIC_PIN_GROUP("pwm1", x1000_pwm_pwm1, 1), 1948 INGENIC_PIN_GROUP("pwm2", x1000_pwm_pwm2, 1), 1949 INGENIC_PIN_GROUP("pwm3", x1000_pwm_pwm3, 2), 1950 INGENIC_PIN_GROUP("pwm4", x1000_pwm_pwm4, 0), 1951 INGENIC_PIN_GROUP("mac", x1000_mac, 1), 1952 }; 1953 1954 static const char *x1000_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; 1955 static const char *x1000_uart1_groups[] = { 1956 "uart1-data-a", "uart1-data-d", "uart1-hwflow", 1957 }; 1958 static const char *x1000_uart2_groups[] = { "uart2-data-a", "uart2-data-d", }; 1959 static const char *x1000_sfc_groups[] = { "sfc", }; 1960 static const char *x1000_ssi_groups[] = { 1961 "ssi-dt-a-22", "ssi-dt-a-29", "ssi-dt-d", 1962 "ssi-dr-a-23", "ssi-dr-a-28", "ssi-dr-d", 1963 "ssi-clk-a-24", "ssi-clk-a-26", "ssi-clk-d", 1964 "ssi-gpc-a-20", "ssi-gpc-a-31", 1965 "ssi-ce0-a-25", "ssi-ce0-a-27", "ssi-ce0-d", 1966 "ssi-ce1-a-21", "ssi-ce1-a-30", 1967 }; 1968 static const char *x1000_mmc0_groups[] = { 1969 "mmc0-1bit", "mmc0-4bit", "mmc0-8bit", 1970 }; 1971 static const char *x1000_mmc1_groups[] = { 1972 "mmc1-1bit", "mmc1-4bit", 1973 }; 1974 static const char *x1000_emc_groups[] = { 1975 "emc-8bit-data", "emc-16bit-data", 1976 "emc-addr", "emc-rd-we", "emc-wait", 1977 }; 1978 static const char *x1000_cs1_groups[] = { "emc-cs1", }; 1979 static const char *x1000_cs2_groups[] = { "emc-cs2", }; 1980 static const char *x1000_i2c0_groups[] = { "i2c0-data", }; 1981 static const char *x1000_i2c1_groups[] = { "i2c1-data-a", "i2c1-data-c", }; 1982 static const char *x1000_i2c2_groups[] = { "i2c2-data", }; 1983 static const char *x1000_i2s_groups[] = { 1984 "i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-sysclk", 1985 }; 1986 static const char *x1000_dmic_groups[] = { "dmic0", "dmic1", }; 1987 static const char *x1000_cim_groups[] = { "cim-data", }; 1988 static const char *x1000_lcd_groups[] = { "lcd-8bit", "lcd-16bit", }; 1989 static const char *x1000_pwm0_groups[] = { "pwm0", }; 1990 static const char *x1000_pwm1_groups[] = { "pwm1", }; 1991 static const char *x1000_pwm2_groups[] = { "pwm2", }; 1992 static const char *x1000_pwm3_groups[] = { "pwm3", }; 1993 static const char *x1000_pwm4_groups[] = { "pwm4", }; 1994 static const char *x1000_mac_groups[] = { "mac", }; 1995 1996 static const struct function_desc x1000_functions[] = { 1997 { "uart0", x1000_uart0_groups, ARRAY_SIZE(x1000_uart0_groups), }, 1998 { "uart1", x1000_uart1_groups, ARRAY_SIZE(x1000_uart1_groups), }, 1999 { "uart2", x1000_uart2_groups, ARRAY_SIZE(x1000_uart2_groups), }, 2000 { "sfc", x1000_sfc_groups, ARRAY_SIZE(x1000_sfc_groups), }, 2001 { "ssi", x1000_ssi_groups, ARRAY_SIZE(x1000_ssi_groups), }, 2002 { "mmc0", x1000_mmc0_groups, ARRAY_SIZE(x1000_mmc0_groups), }, 2003 { "mmc1", x1000_mmc1_groups, ARRAY_SIZE(x1000_mmc1_groups), }, 2004 { "emc", x1000_emc_groups, ARRAY_SIZE(x1000_emc_groups), }, 2005 { "emc-cs1", x1000_cs1_groups, ARRAY_SIZE(x1000_cs1_groups), }, 2006 { "emc-cs2", x1000_cs2_groups, ARRAY_SIZE(x1000_cs2_groups), }, 2007 { "i2c0", x1000_i2c0_groups, ARRAY_SIZE(x1000_i2c0_groups), }, 2008 { "i2c1", x1000_i2c1_groups, ARRAY_SIZE(x1000_i2c1_groups), }, 2009 { "i2c2", x1000_i2c2_groups, ARRAY_SIZE(x1000_i2c2_groups), }, 2010 { "i2s", x1000_i2s_groups, ARRAY_SIZE(x1000_i2s_groups), }, 2011 { "dmic", x1000_dmic_groups, ARRAY_SIZE(x1000_dmic_groups), }, 2012 { "cim", x1000_cim_groups, ARRAY_SIZE(x1000_cim_groups), }, 2013 { "lcd", x1000_lcd_groups, ARRAY_SIZE(x1000_lcd_groups), }, 2014 { "pwm0", x1000_pwm0_groups, ARRAY_SIZE(x1000_pwm0_groups), }, 2015 { "pwm1", x1000_pwm1_groups, ARRAY_SIZE(x1000_pwm1_groups), }, 2016 { "pwm2", x1000_pwm2_groups, ARRAY_SIZE(x1000_pwm2_groups), }, 2017 { "pwm3", x1000_pwm3_groups, ARRAY_SIZE(x1000_pwm3_groups), }, 2018 { "pwm4", x1000_pwm4_groups, ARRAY_SIZE(x1000_pwm4_groups), }, 2019 { "mac", x1000_mac_groups, ARRAY_SIZE(x1000_mac_groups), }, 2020 }; 2021 2022 static const struct ingenic_chip_info x1000_chip_info = { 2023 .num_chips = 4, 2024 .reg_offset = 0x100, 2025 .version = ID_X1000, 2026 .groups = x1000_groups, 2027 .num_groups = ARRAY_SIZE(x1000_groups), 2028 .functions = x1000_functions, 2029 .num_functions = ARRAY_SIZE(x1000_functions), 2030 .pull_ups = x1000_pull_ups, 2031 .pull_downs = x1000_pull_downs, 2032 }; 2033 2034 static int x1500_uart0_data_pins[] = { 0x4a, 0x4b, }; 2035 static int x1500_uart0_hwflow_pins[] = { 0x4c, 0x4d, }; 2036 static int x1500_uart1_data_a_pins[] = { 0x04, 0x05, }; 2037 static int x1500_uart1_data_d_pins[] = { 0x62, 0x63, }; 2038 static int x1500_uart1_hwflow_pins[] = { 0x64, 0x65, }; 2039 static int x1500_uart2_data_a_pins[] = { 0x02, 0x03, }; 2040 static int x1500_uart2_data_d_pins[] = { 0x65, 0x64, }; 2041 static int x1500_mmc_1bit_pins[] = { 0x18, 0x19, 0x17, }; 2042 static int x1500_mmc_4bit_pins[] = { 0x16, 0x15, 0x14, }; 2043 static int x1500_i2c0_pins[] = { 0x38, 0x37, }; 2044 static int x1500_i2c1_a_pins[] = { 0x01, 0x00, }; 2045 static int x1500_i2c1_c_pins[] = { 0x5b, 0x5a, }; 2046 static int x1500_i2c2_pins[] = { 0x61, 0x60, }; 2047 static int x1500_i2s_data_tx_pins[] = { 0x24, }; 2048 static int x1500_i2s_data_rx_pins[] = { 0x23, }; 2049 static int x1500_i2s_clk_txrx_pins[] = { 0x21, 0x22, }; 2050 static int x1500_i2s_sysclk_pins[] = { 0x20, }; 2051 static int x1500_dmic0_pins[] = { 0x35, 0x36, }; 2052 static int x1500_dmic1_pins[] = { 0x25, }; 2053 static int x1500_cim_pins[] = { 2054 0x08, 0x09, 0x0a, 0x0b, 2055 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 0x0d, 0x0c, 2056 }; 2057 static int x1500_pwm_pwm0_pins[] = { 0x59, }; 2058 static int x1500_pwm_pwm1_pins[] = { 0x5a, }; 2059 static int x1500_pwm_pwm2_pins[] = { 0x5b, }; 2060 static int x1500_pwm_pwm3_pins[] = { 0x26, }; 2061 static int x1500_pwm_pwm4_pins[] = { 0x58, }; 2062 2063 static const struct group_desc x1500_groups[] = { 2064 INGENIC_PIN_GROUP("uart0-data", x1500_uart0_data, 0), 2065 INGENIC_PIN_GROUP("uart0-hwflow", x1500_uart0_hwflow, 0), 2066 INGENIC_PIN_GROUP("uart1-data-a", x1500_uart1_data_a, 2), 2067 INGENIC_PIN_GROUP("uart1-data-d", x1500_uart1_data_d, 1), 2068 INGENIC_PIN_GROUP("uart1-hwflow", x1500_uart1_hwflow, 1), 2069 INGENIC_PIN_GROUP("uart2-data-a", x1500_uart2_data_a, 2), 2070 INGENIC_PIN_GROUP("uart2-data-d", x1500_uart2_data_d, 0), 2071 INGENIC_PIN_GROUP("sfc", x1000_sfc, 1), 2072 INGENIC_PIN_GROUP("mmc-1bit", x1500_mmc_1bit, 1), 2073 INGENIC_PIN_GROUP("mmc-4bit", x1500_mmc_4bit, 1), 2074 INGENIC_PIN_GROUP("i2c0-data", x1500_i2c0, 0), 2075 INGENIC_PIN_GROUP("i2c1-data-a", x1500_i2c1_a, 2), 2076 INGENIC_PIN_GROUP("i2c1-data-c", x1500_i2c1_c, 0), 2077 INGENIC_PIN_GROUP("i2c2-data", x1500_i2c2, 1), 2078 INGENIC_PIN_GROUP("i2s-data-tx", x1500_i2s_data_tx, 1), 2079 INGENIC_PIN_GROUP("i2s-data-rx", x1500_i2s_data_rx, 1), 2080 INGENIC_PIN_GROUP("i2s-clk-txrx", x1500_i2s_clk_txrx, 1), 2081 INGENIC_PIN_GROUP("i2s-sysclk", x1500_i2s_sysclk, 1), 2082 INGENIC_PIN_GROUP("dmic0", x1500_dmic0, 0), 2083 INGENIC_PIN_GROUP("dmic1", x1500_dmic1, 1), 2084 INGENIC_PIN_GROUP("cim-data", x1500_cim, 2), 2085 INGENIC_PIN_GROUP("pwm0", x1500_pwm_pwm0, 0), 2086 INGENIC_PIN_GROUP("pwm1", x1500_pwm_pwm1, 1), 2087 INGENIC_PIN_GROUP("pwm2", x1500_pwm_pwm2, 1), 2088 INGENIC_PIN_GROUP("pwm3", x1500_pwm_pwm3, 2), 2089 INGENIC_PIN_GROUP("pwm4", x1500_pwm_pwm4, 0), 2090 }; 2091 2092 static const char *x1500_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; 2093 static const char *x1500_uart1_groups[] = { 2094 "uart1-data-a", "uart1-data-d", "uart1-hwflow", 2095 }; 2096 static const char *x1500_uart2_groups[] = { "uart2-data-a", "uart2-data-d", }; 2097 static const char *x1500_mmc_groups[] = { "mmc-1bit", "mmc-4bit", }; 2098 static const char *x1500_i2c0_groups[] = { "i2c0-data", }; 2099 static const char *x1500_i2c1_groups[] = { "i2c1-data-a", "i2c1-data-c", }; 2100 static const char *x1500_i2c2_groups[] = { "i2c2-data", }; 2101 static const char *x1500_i2s_groups[] = { 2102 "i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-sysclk", 2103 }; 2104 static const char *x1500_dmic_groups[] = { "dmic0", "dmic1", }; 2105 static const char *x1500_cim_groups[] = { "cim-data", }; 2106 static const char *x1500_pwm0_groups[] = { "pwm0", }; 2107 static const char *x1500_pwm1_groups[] = { "pwm1", }; 2108 static const char *x1500_pwm2_groups[] = { "pwm2", }; 2109 static const char *x1500_pwm3_groups[] = { "pwm3", }; 2110 static const char *x1500_pwm4_groups[] = { "pwm4", }; 2111 2112 static const struct function_desc x1500_functions[] = { 2113 { "uart0", x1500_uart0_groups, ARRAY_SIZE(x1500_uart0_groups), }, 2114 { "uart1", x1500_uart1_groups, ARRAY_SIZE(x1500_uart1_groups), }, 2115 { "uart2", x1500_uart2_groups, ARRAY_SIZE(x1500_uart2_groups), }, 2116 { "sfc", x1000_sfc_groups, ARRAY_SIZE(x1000_sfc_groups), }, 2117 { "mmc", x1500_mmc_groups, ARRAY_SIZE(x1500_mmc_groups), }, 2118 { "i2c0", x1500_i2c0_groups, ARRAY_SIZE(x1500_i2c0_groups), }, 2119 { "i2c1", x1500_i2c1_groups, ARRAY_SIZE(x1500_i2c1_groups), }, 2120 { "i2c2", x1500_i2c2_groups, ARRAY_SIZE(x1500_i2c2_groups), }, 2121 { "i2s", x1500_i2s_groups, ARRAY_SIZE(x1500_i2s_groups), }, 2122 { "dmic", x1500_dmic_groups, ARRAY_SIZE(x1500_dmic_groups), }, 2123 { "cim", x1500_cim_groups, ARRAY_SIZE(x1500_cim_groups), }, 2124 { "pwm0", x1500_pwm0_groups, ARRAY_SIZE(x1500_pwm0_groups), }, 2125 { "pwm1", x1500_pwm1_groups, ARRAY_SIZE(x1500_pwm1_groups), }, 2126 { "pwm2", x1500_pwm2_groups, ARRAY_SIZE(x1500_pwm2_groups), }, 2127 { "pwm3", x1500_pwm3_groups, ARRAY_SIZE(x1500_pwm3_groups), }, 2128 { "pwm4", x1500_pwm4_groups, ARRAY_SIZE(x1500_pwm4_groups), }, 2129 }; 2130 2131 static const struct ingenic_chip_info x1500_chip_info = { 2132 .num_chips = 4, 2133 .reg_offset = 0x100, 2134 .version = ID_X1500, 2135 .groups = x1500_groups, 2136 .num_groups = ARRAY_SIZE(x1500_groups), 2137 .functions = x1500_functions, 2138 .num_functions = ARRAY_SIZE(x1500_functions), 2139 .pull_ups = x1000_pull_ups, 2140 .pull_downs = x1000_pull_downs, 2141 }; 2142 2143 static const u32 x1830_pull_ups[4] = { 2144 0x5fdfffc0, 0xffffefff, 0x1ffffbff, 0x0fcff3fc, 2145 }; 2146 2147 static const u32 x1830_pull_downs[4] = { 2148 0x5fdfffc0, 0xffffefff, 0x1ffffbff, 0x0fcff3fc, 2149 }; 2150 2151 static int x1830_uart0_data_pins[] = { 0x33, 0x36, }; 2152 static int x1830_uart0_hwflow_pins[] = { 0x34, 0x35, }; 2153 static int x1830_uart1_data_pins[] = { 0x38, 0x37, }; 2154 static int x1830_sfc_pins[] = { 0x17, 0x18, 0x1a, 0x19, 0x1b, 0x1c, }; 2155 static int x1830_ssi0_dt_pins[] = { 0x4c, }; 2156 static int x1830_ssi0_dr_pins[] = { 0x4b, }; 2157 static int x1830_ssi0_clk_pins[] = { 0x4f, }; 2158 static int x1830_ssi0_gpc_pins[] = { 0x4d, }; 2159 static int x1830_ssi0_ce0_pins[] = { 0x50, }; 2160 static int x1830_ssi0_ce1_pins[] = { 0x4e, }; 2161 static int x1830_ssi1_dt_c_pins[] = { 0x53, }; 2162 static int x1830_ssi1_dt_d_pins[] = { 0x62, }; 2163 static int x1830_ssi1_dr_c_pins[] = { 0x54, }; 2164 static int x1830_ssi1_dr_d_pins[] = { 0x63, }; 2165 static int x1830_ssi1_clk_c_pins[] = { 0x57, }; 2166 static int x1830_ssi1_clk_d_pins[] = { 0x66, }; 2167 static int x1830_ssi1_gpc_c_pins[] = { 0x55, }; 2168 static int x1830_ssi1_gpc_d_pins[] = { 0x64, }; 2169 static int x1830_ssi1_ce0_c_pins[] = { 0x58, }; 2170 static int x1830_ssi1_ce0_d_pins[] = { 0x67, }; 2171 static int x1830_ssi1_ce1_c_pins[] = { 0x56, }; 2172 static int x1830_ssi1_ce1_d_pins[] = { 0x65, }; 2173 static int x1830_mmc0_1bit_pins[] = { 0x24, 0x25, 0x20, }; 2174 static int x1830_mmc0_4bit_pins[] = { 0x21, 0x22, 0x23, }; 2175 static int x1830_mmc1_1bit_pins[] = { 0x42, 0x43, 0x44, }; 2176 static int x1830_mmc1_4bit_pins[] = { 0x45, 0x46, 0x47, }; 2177 static int x1830_i2c0_pins[] = { 0x0c, 0x0d, }; 2178 static int x1830_i2c1_pins[] = { 0x39, 0x3a, }; 2179 static int x1830_i2c2_pins[] = { 0x5b, 0x5c, }; 2180 static int x1830_i2s_data_tx_pins[] = { 0x53, }; 2181 static int x1830_i2s_data_rx_pins[] = { 0x54, }; 2182 static int x1830_i2s_clk_txrx_pins[] = { 0x58, 0x52, }; 2183 static int x1830_i2s_clk_rx_pins[] = { 0x56, 0x55, }; 2184 static int x1830_i2s_sysclk_pins[] = { 0x57, }; 2185 static int x1830_dmic0_pins[] = { 0x48, 0x59, }; 2186 static int x1830_dmic1_pins[] = { 0x5a, }; 2187 static int x1830_lcd_tft_8bit_pins[] = { 2188 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 2189 0x68, 0x73, 0x72, 0x69, 2190 }; 2191 static int x1830_lcd_tft_24bit_pins[] = { 2192 0x6c, 0x6d, 0x6e, 0x6f, 0x70, 0x71, 2193 0x76, 0x77, 0x78, 0x79, 0x7a, 0x7b, 2194 }; 2195 static int x1830_lcd_slcd_8bit_pins[] = { 2196 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x6c, 0x6d, 2197 0x69, 0x72, 0x73, 0x7b, 0x7a, 2198 }; 2199 static int x1830_lcd_slcd_16bit_pins[] = { 2200 0x6e, 0x6f, 0x70, 0x71, 0x76, 0x77, 0x78, 0x79, 2201 }; 2202 static int x1830_pwm_pwm0_b_pins[] = { 0x31, }; 2203 static int x1830_pwm_pwm0_c_pins[] = { 0x4b, }; 2204 static int x1830_pwm_pwm1_b_pins[] = { 0x32, }; 2205 static int x1830_pwm_pwm1_c_pins[] = { 0x4c, }; 2206 static int x1830_pwm_pwm2_c_8_pins[] = { 0x48, }; 2207 static int x1830_pwm_pwm2_c_13_pins[] = { 0x4d, }; 2208 static int x1830_pwm_pwm3_c_9_pins[] = { 0x49, }; 2209 static int x1830_pwm_pwm3_c_14_pins[] = { 0x4e, }; 2210 static int x1830_pwm_pwm4_c_15_pins[] = { 0x4f, }; 2211 static int x1830_pwm_pwm4_c_25_pins[] = { 0x59, }; 2212 static int x1830_pwm_pwm5_c_16_pins[] = { 0x50, }; 2213 static int x1830_pwm_pwm5_c_26_pins[] = { 0x5a, }; 2214 static int x1830_pwm_pwm6_c_17_pins[] = { 0x51, }; 2215 static int x1830_pwm_pwm6_c_27_pins[] = { 0x5b, }; 2216 static int x1830_pwm_pwm7_c_18_pins[] = { 0x52, }; 2217 static int x1830_pwm_pwm7_c_28_pins[] = { 0x5c, }; 2218 static int x1830_mac_pins[] = { 2219 0x29, 0x30, 0x2f, 0x28, 0x2e, 0x2d, 0x2a, 0x2b, 0x26, 0x27, 2220 }; 2221 2222 static const struct group_desc x1830_groups[] = { 2223 INGENIC_PIN_GROUP("uart0-data", x1830_uart0_data, 0), 2224 INGENIC_PIN_GROUP("uart0-hwflow", x1830_uart0_hwflow, 0), 2225 INGENIC_PIN_GROUP("uart1-data", x1830_uart1_data, 0), 2226 INGENIC_PIN_GROUP("sfc", x1830_sfc, 1), 2227 INGENIC_PIN_GROUP("ssi0-dt", x1830_ssi0_dt, 0), 2228 INGENIC_PIN_GROUP("ssi0-dr", x1830_ssi0_dr, 0), 2229 INGENIC_PIN_GROUP("ssi0-clk", x1830_ssi0_clk, 0), 2230 INGENIC_PIN_GROUP("ssi0-gpc", x1830_ssi0_gpc, 0), 2231 INGENIC_PIN_GROUP("ssi0-ce0", x1830_ssi0_ce0, 0), 2232 INGENIC_PIN_GROUP("ssi0-ce1", x1830_ssi0_ce1, 0), 2233 INGENIC_PIN_GROUP("ssi1-dt-c", x1830_ssi1_dt_c, 1), 2234 INGENIC_PIN_GROUP("ssi1-dr-c", x1830_ssi1_dr_c, 1), 2235 INGENIC_PIN_GROUP("ssi1-clk-c", x1830_ssi1_clk_c, 1), 2236 INGENIC_PIN_GROUP("ssi1-gpc-c", x1830_ssi1_gpc_c, 1), 2237 INGENIC_PIN_GROUP("ssi1-ce0-c", x1830_ssi1_ce0_c, 1), 2238 INGENIC_PIN_GROUP("ssi1-ce1-c", x1830_ssi1_ce1_c, 1), 2239 INGENIC_PIN_GROUP("ssi1-dt-d", x1830_ssi1_dt_d, 2), 2240 INGENIC_PIN_GROUP("ssi1-dr-d", x1830_ssi1_dr_d, 2), 2241 INGENIC_PIN_GROUP("ssi1-clk-d", x1830_ssi1_clk_d, 2), 2242 INGENIC_PIN_GROUP("ssi1-gpc-d", x1830_ssi1_gpc_d, 2), 2243 INGENIC_PIN_GROUP("ssi1-ce0-d", x1830_ssi1_ce0_d, 2), 2244 INGENIC_PIN_GROUP("ssi1-ce1-d", x1830_ssi1_ce1_d, 2), 2245 INGENIC_PIN_GROUP("mmc0-1bit", x1830_mmc0_1bit, 0), 2246 INGENIC_PIN_GROUP("mmc0-4bit", x1830_mmc0_4bit, 0), 2247 INGENIC_PIN_GROUP("mmc1-1bit", x1830_mmc1_1bit, 0), 2248 INGENIC_PIN_GROUP("mmc1-4bit", x1830_mmc1_4bit, 0), 2249 INGENIC_PIN_GROUP("i2c0-data", x1830_i2c0, 1), 2250 INGENIC_PIN_GROUP("i2c1-data", x1830_i2c1, 0), 2251 INGENIC_PIN_GROUP("i2c2-data", x1830_i2c2, 1), 2252 INGENIC_PIN_GROUP("i2s-data-tx", x1830_i2s_data_tx, 0), 2253 INGENIC_PIN_GROUP("i2s-data-rx", x1830_i2s_data_rx, 0), 2254 INGENIC_PIN_GROUP("i2s-clk-txrx", x1830_i2s_clk_txrx, 0), 2255 INGENIC_PIN_GROUP("i2s-clk-rx", x1830_i2s_clk_rx, 0), 2256 INGENIC_PIN_GROUP("i2s-sysclk", x1830_i2s_sysclk, 0), 2257 INGENIC_PIN_GROUP("dmic0", x1830_dmic0, 2), 2258 INGENIC_PIN_GROUP("dmic1", x1830_dmic1, 2), 2259 INGENIC_PIN_GROUP("lcd-tft-8bit", x1830_lcd_tft_8bit, 0), 2260 INGENIC_PIN_GROUP("lcd-tft-24bit", x1830_lcd_tft_24bit, 0), 2261 INGENIC_PIN_GROUP("lcd-slcd-8bit", x1830_lcd_slcd_8bit, 1), 2262 INGENIC_PIN_GROUP("lcd-slcd-16bit", x1830_lcd_slcd_16bit, 1), 2263 INGENIC_PIN_GROUP("pwm0-b", x1830_pwm_pwm0_b, 0), 2264 INGENIC_PIN_GROUP("pwm0-c", x1830_pwm_pwm0_c, 1), 2265 INGENIC_PIN_GROUP("pwm1-b", x1830_pwm_pwm1_b, 0), 2266 INGENIC_PIN_GROUP("pwm1-c", x1830_pwm_pwm1_c, 1), 2267 INGENIC_PIN_GROUP("pwm2-c-8", x1830_pwm_pwm2_c_8, 0), 2268 INGENIC_PIN_GROUP("pwm2-c-13", x1830_pwm_pwm2_c_13, 1), 2269 INGENIC_PIN_GROUP("pwm3-c-9", x1830_pwm_pwm3_c_9, 0), 2270 INGENIC_PIN_GROUP("pwm3-c-14", x1830_pwm_pwm3_c_14, 1), 2271 INGENIC_PIN_GROUP("pwm4-c-15", x1830_pwm_pwm4_c_15, 1), 2272 INGENIC_PIN_GROUP("pwm4-c-25", x1830_pwm_pwm4_c_25, 0), 2273 INGENIC_PIN_GROUP("pwm5-c-16", x1830_pwm_pwm5_c_16, 1), 2274 INGENIC_PIN_GROUP("pwm5-c-26", x1830_pwm_pwm5_c_26, 0), 2275 INGENIC_PIN_GROUP("pwm6-c-17", x1830_pwm_pwm6_c_17, 1), 2276 INGENIC_PIN_GROUP("pwm6-c-27", x1830_pwm_pwm6_c_27, 0), 2277 INGENIC_PIN_GROUP("pwm7-c-18", x1830_pwm_pwm7_c_18, 1), 2278 INGENIC_PIN_GROUP("pwm7-c-28", x1830_pwm_pwm7_c_28, 0), 2279 INGENIC_PIN_GROUP("mac", x1830_mac, 0), 2280 }; 2281 2282 static const char *x1830_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; 2283 static const char *x1830_uart1_groups[] = { "uart1-data", }; 2284 static const char *x1830_sfc_groups[] = { "sfc", }; 2285 static const char *x1830_ssi0_groups[] = { 2286 "ssi0-dt", "ssi0-dr", "ssi0-clk", "ssi0-gpc", "ssi0-ce0", "ssi0-ce1", 2287 }; 2288 static const char *x1830_ssi1_groups[] = { 2289 "ssi1-dt-c", "ssi1-dt-d", 2290 "ssi1-dr-c", "ssi1-dr-d", 2291 "ssi1-clk-c", "ssi1-clk-d", 2292 "ssi1-gpc-c", "ssi1-gpc-d", 2293 "ssi1-ce0-c", "ssi1-ce0-d", 2294 "ssi1-ce1-c", "ssi1-ce1-d", 2295 }; 2296 static const char *x1830_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", }; 2297 static const char *x1830_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", }; 2298 static const char *x1830_i2c0_groups[] = { "i2c0-data", }; 2299 static const char *x1830_i2c1_groups[] = { "i2c1-data", }; 2300 static const char *x1830_i2c2_groups[] = { "i2c2-data", }; 2301 static const char *x1830_i2s_groups[] = { 2302 "i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-clk-rx", "i2s-sysclk", 2303 }; 2304 static const char *x1830_dmic_groups[] = { "dmic0", "dmic1", }; 2305 static const char *x1830_lcd_groups[] = { 2306 "lcd-tft-8bit", "lcd-tft-24bit", "lcd-slcd-8bit", "lcd-slcd-16bit", 2307 }; 2308 static const char *x1830_pwm0_groups[] = { "pwm0-b", "pwm0-c", }; 2309 static const char *x1830_pwm1_groups[] = { "pwm1-b", "pwm1-c", }; 2310 static const char *x1830_pwm2_groups[] = { "pwm2-c-8", "pwm2-c-13", }; 2311 static const char *x1830_pwm3_groups[] = { "pwm3-c-9", "pwm3-c-14", }; 2312 static const char *x1830_pwm4_groups[] = { "pwm4-c-15", "pwm4-c-25", }; 2313 static const char *x1830_pwm5_groups[] = { "pwm5-c-16", "pwm5-c-26", }; 2314 static const char *x1830_pwm6_groups[] = { "pwm6-c-17", "pwm6-c-27", }; 2315 static const char *x1830_pwm7_groups[] = { "pwm7-c-18", "pwm7-c-28", }; 2316 static const char *x1830_mac_groups[] = { "mac", }; 2317 2318 static const struct function_desc x1830_functions[] = { 2319 { "uart0", x1830_uart0_groups, ARRAY_SIZE(x1830_uart0_groups), }, 2320 { "uart1", x1830_uart1_groups, ARRAY_SIZE(x1830_uart1_groups), }, 2321 { "sfc", x1830_sfc_groups, ARRAY_SIZE(x1830_sfc_groups), }, 2322 { "ssi0", x1830_ssi0_groups, ARRAY_SIZE(x1830_ssi0_groups), }, 2323 { "ssi1", x1830_ssi1_groups, ARRAY_SIZE(x1830_ssi1_groups), }, 2324 { "mmc0", x1830_mmc0_groups, ARRAY_SIZE(x1830_mmc0_groups), }, 2325 { "mmc1", x1830_mmc1_groups, ARRAY_SIZE(x1830_mmc1_groups), }, 2326 { "i2c0", x1830_i2c0_groups, ARRAY_SIZE(x1830_i2c0_groups), }, 2327 { "i2c1", x1830_i2c1_groups, ARRAY_SIZE(x1830_i2c1_groups), }, 2328 { "i2c2", x1830_i2c2_groups, ARRAY_SIZE(x1830_i2c2_groups), }, 2329 { "i2s", x1830_i2s_groups, ARRAY_SIZE(x1830_i2s_groups), }, 2330 { "dmic", x1830_dmic_groups, ARRAY_SIZE(x1830_dmic_groups), }, 2331 { "lcd", x1830_lcd_groups, ARRAY_SIZE(x1830_lcd_groups), }, 2332 { "pwm0", x1830_pwm0_groups, ARRAY_SIZE(x1830_pwm0_groups), }, 2333 { "pwm1", x1830_pwm1_groups, ARRAY_SIZE(x1830_pwm1_groups), }, 2334 { "pwm2", x1830_pwm2_groups, ARRAY_SIZE(x1830_pwm2_groups), }, 2335 { "pwm3", x1830_pwm3_groups, ARRAY_SIZE(x1830_pwm3_groups), }, 2336 { "pwm4", x1830_pwm4_groups, ARRAY_SIZE(x1830_pwm4_groups), }, 2337 { "pwm5", x1830_pwm5_groups, ARRAY_SIZE(x1830_pwm4_groups), }, 2338 { "pwm6", x1830_pwm6_groups, ARRAY_SIZE(x1830_pwm4_groups), }, 2339 { "pwm7", x1830_pwm7_groups, ARRAY_SIZE(x1830_pwm4_groups), }, 2340 { "mac", x1830_mac_groups, ARRAY_SIZE(x1830_mac_groups), }, 2341 }; 2342 2343 static const struct ingenic_chip_info x1830_chip_info = { 2344 .num_chips = 4, 2345 .reg_offset = 0x1000, 2346 .version = ID_X1830, 2347 .groups = x1830_groups, 2348 .num_groups = ARRAY_SIZE(x1830_groups), 2349 .functions = x1830_functions, 2350 .num_functions = ARRAY_SIZE(x1830_functions), 2351 .pull_ups = x1830_pull_ups, 2352 .pull_downs = x1830_pull_downs, 2353 }; 2354 2355 static const u32 x2000_pull_ups[5] = { 2356 0x0003ffff, 0xffffffff, 0x1ff0ffff, 0xc7fe3f3f, 0x8fff003f, 2357 }; 2358 2359 static const u32 x2000_pull_downs[5] = { 2360 0x0003ffff, 0xffffffff, 0x1ff0ffff, 0x00000000, 0x8fff003f, 2361 }; 2362 2363 static int x2000_uart0_data_pins[] = { 0x77, 0x78, }; 2364 static int x2000_uart0_hwflow_pins[] = { 0x79, 0x7a, }; 2365 static int x2000_uart1_data_pins[] = { 0x57, 0x58, }; 2366 static int x2000_uart1_hwflow_pins[] = { 0x55, 0x56, }; 2367 static int x2000_uart2_data_pins[] = { 0x7e, 0x7f, }; 2368 static int x2000_uart3_data_c_pins[] = { 0x59, 0x5a, }; 2369 static int x2000_uart3_data_d_pins[] = { 0x62, 0x63, }; 2370 static int x2000_uart3_hwflow_c_pins[] = { 0x5b, 0x5c, }; 2371 static int x2000_uart3_hwflow_d_pins[] = { 0x60, 0x61, }; 2372 static int x2000_uart4_data_a_pins[] = { 0x02, 0x03, }; 2373 static int x2000_uart4_data_c_pins[] = { 0x4b, 0x4c, }; 2374 static int x2000_uart4_hwflow_a_pins[] = { 0x00, 0x01, }; 2375 static int x2000_uart4_hwflow_c_pins[] = { 0x49, 0x4a, }; 2376 static int x2000_uart5_data_a_pins[] = { 0x04, 0x05, }; 2377 static int x2000_uart5_data_c_pins[] = { 0x45, 0x46, }; 2378 static int x2000_uart6_data_a_pins[] = { 0x06, 0x07, }; 2379 static int x2000_uart6_data_c_pins[] = { 0x47, 0x48, }; 2380 static int x2000_uart7_data_a_pins[] = { 0x08, 0x09, }; 2381 static int x2000_uart7_data_c_pins[] = { 0x41, 0x42, }; 2382 static int x2000_uart8_data_pins[] = { 0x3c, 0x3d, }; 2383 static int x2000_uart9_data_pins[] = { 0x3e, 0x3f, }; 2384 static int x2000_sfc0_d_pins[] = { 0x73, 0x74, 0x75, 0x76, 0x71, 0x72, }; 2385 static int x2000_sfc0_e_pins[] = { 0x92, 0x93, 0x94, 0x95, 0x90, 0x91, }; 2386 static int x2000_sfc1_pins[] = { 0x77, 0x78, 0x79, 0x7a, }; 2387 static int x2000_ssi0_dt_b_pins[] = { 0x3e, }; 2388 static int x2000_ssi0_dt_d_pins[] = { 0x69, }; 2389 static int x2000_ssi0_dr_b_pins[] = { 0x3d, }; 2390 static int x2000_ssi0_dr_d_pins[] = { 0x6a, }; 2391 static int x2000_ssi0_clk_b_pins[] = { 0x3f, }; 2392 static int x2000_ssi0_clk_d_pins[] = { 0x68, }; 2393 static int x2000_ssi0_ce0_b_pins[] = { 0x3c, }; 2394 static int x2000_ssi0_ce0_d_pins[] = { 0x6d, }; 2395 static int x2000_ssi1_dt_c_pins[] = { 0x4b, }; 2396 static int x2000_ssi1_dt_d_pins[] = { 0x72, }; 2397 static int x2000_ssi1_dt_e_pins[] = { 0x91, }; 2398 static int x2000_ssi1_dr_c_pins[] = { 0x4a, }; 2399 static int x2000_ssi1_dr_d_pins[] = { 0x73, }; 2400 static int x2000_ssi1_dr_e_pins[] = { 0x92, }; 2401 static int x2000_ssi1_clk_c_pins[] = { 0x4c, }; 2402 static int x2000_ssi1_clk_d_pins[] = { 0x71, }; 2403 static int x2000_ssi1_clk_e_pins[] = { 0x90, }; 2404 static int x2000_ssi1_ce0_c_pins[] = { 0x49, }; 2405 static int x2000_ssi1_ce0_d_pins[] = { 0x76, }; 2406 static int x2000_ssi1_ce0_e_pins[] = { 0x95, }; 2407 static int x2000_mmc0_1bit_pins[] = { 0x71, 0x72, 0x73, }; 2408 static int x2000_mmc0_4bit_pins[] = { 0x74, 0x75, 0x75, }; 2409 static int x2000_mmc0_8bit_pins[] = { 0x77, 0x78, 0x79, 0x7a, }; 2410 static int x2000_mmc1_1bit_pins[] = { 0x68, 0x69, 0x6a, }; 2411 static int x2000_mmc1_4bit_pins[] = { 0x6b, 0x6c, 0x6d, }; 2412 static int x2000_mmc2_1bit_pins[] = { 0x80, 0x81, 0x82, }; 2413 static int x2000_mmc2_4bit_pins[] = { 0x83, 0x84, 0x85, }; 2414 static int x2000_emc_8bit_data_pins[] = { 2415 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 2416 }; 2417 static int x2000_emc_16bit_data_pins[] = { 2418 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f, 2419 }; 2420 static int x2000_emc_addr_pins[] = { 2421 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 2422 0x28, 0x29, 0x2a, 0x2b, 0x2c, 2423 }; 2424 static int x2000_emc_rd_we_pins[] = { 0x2d, 0x2e, }; 2425 static int x2000_emc_wait_pins[] = { 0x2f, }; 2426 static int x2000_emc_cs1_pins[] = { 0x57, }; 2427 static int x2000_emc_cs2_pins[] = { 0x58, }; 2428 static int x2000_i2c0_pins[] = { 0x4e, 0x4d, }; 2429 static int x2000_i2c1_c_pins[] = { 0x58, 0x57, }; 2430 static int x2000_i2c1_d_pins[] = { 0x6c, 0x6b, }; 2431 static int x2000_i2c2_b_pins[] = { 0x37, 0x36, }; 2432 static int x2000_i2c2_d_pins[] = { 0x75, 0x74, }; 2433 static int x2000_i2c2_e_pins[] = { 0x94, 0x93, }; 2434 static int x2000_i2c3_a_pins[] = { 0x11, 0x10, }; 2435 static int x2000_i2c3_d_pins[] = { 0x7f, 0x7e, }; 2436 static int x2000_i2c4_c_pins[] = { 0x5a, 0x59, }; 2437 static int x2000_i2c4_d_pins[] = { 0x61, 0x60, }; 2438 static int x2000_i2c5_c_pins[] = { 0x5c, 0x5b, }; 2439 static int x2000_i2c5_d_pins[] = { 0x65, 0x64, }; 2440 static int x2000_i2s1_data_tx_pins[] = { 0x47, }; 2441 static int x2000_i2s1_data_rx_pins[] = { 0x44, }; 2442 static int x2000_i2s1_clk_tx_pins[] = { 0x45, 0x46, }; 2443 static int x2000_i2s1_clk_rx_pins[] = { 0x42, 0x43, }; 2444 static int x2000_i2s1_sysclk_tx_pins[] = { 0x48, }; 2445 static int x2000_i2s1_sysclk_rx_pins[] = { 0x41, }; 2446 static int x2000_i2s2_data_rx0_pins[] = { 0x0a, }; 2447 static int x2000_i2s2_data_rx1_pins[] = { 0x0b, }; 2448 static int x2000_i2s2_data_rx2_pins[] = { 0x0c, }; 2449 static int x2000_i2s2_data_rx3_pins[] = { 0x0d, }; 2450 static int x2000_i2s2_clk_rx_pins[] = { 0x11, 0x09, }; 2451 static int x2000_i2s2_sysclk_rx_pins[] = { 0x07, }; 2452 static int x2000_i2s3_data_tx0_pins[] = { 0x03, }; 2453 static int x2000_i2s3_data_tx1_pins[] = { 0x04, }; 2454 static int x2000_i2s3_data_tx2_pins[] = { 0x05, }; 2455 static int x2000_i2s3_data_tx3_pins[] = { 0x06, }; 2456 static int x2000_i2s3_clk_tx_pins[] = { 0x10, 0x02, }; 2457 static int x2000_i2s3_sysclk_tx_pins[] = { 0x00, }; 2458 static int x2000_dmic0_pins[] = { 0x54, 0x55, }; 2459 static int x2000_dmic1_pins[] = { 0x56, }; 2460 static int x2000_dmic2_pins[] = { 0x57, }; 2461 static int x2000_dmic3_pins[] = { 0x58, }; 2462 static int x2000_cim_8bit_pins[] = { 2463 0x0e, 0x0c, 0x0d, 0x4f, 2464 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 2465 }; 2466 static int x2000_cim_12bit_pins[] = { 0x08, 0x09, 0x0a, 0x0b, }; 2467 static int x2000_lcd_tft_8bit_pins[] = { 2468 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 2469 0x38, 0x3a, 0x39, 0x3b, 2470 }; 2471 static int x2000_lcd_tft_16bit_pins[] = { 2472 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 2473 }; 2474 static int x2000_lcd_tft_18bit_pins[] = { 2475 0x30, 0x31, 2476 }; 2477 static int x2000_lcd_tft_24bit_pins[] = { 2478 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 2479 }; 2480 static int x2000_lcd_slcd_8bit_pins[] = { 2481 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 2482 0x3a, 0x38, 0x3b, 0x30, 0x39, 2483 }; 2484 static int x2000_pwm_pwm0_c_pins[] = { 0x40, }; 2485 static int x2000_pwm_pwm0_d_pins[] = { 0x7e, }; 2486 static int x2000_pwm_pwm1_c_pins[] = { 0x41, }; 2487 static int x2000_pwm_pwm1_d_pins[] = { 0x7f, }; 2488 static int x2000_pwm_pwm2_c_pins[] = { 0x42, }; 2489 static int x2000_pwm_pwm2_e_pins[] = { 0x80, }; 2490 static int x2000_pwm_pwm3_c_pins[] = { 0x43, }; 2491 static int x2000_pwm_pwm3_e_pins[] = { 0x81, }; 2492 static int x2000_pwm_pwm4_c_pins[] = { 0x44, }; 2493 static int x2000_pwm_pwm4_e_pins[] = { 0x82, }; 2494 static int x2000_pwm_pwm5_c_pins[] = { 0x45, }; 2495 static int x2000_pwm_pwm5_e_pins[] = { 0x83, }; 2496 static int x2000_pwm_pwm6_c_pins[] = { 0x46, }; 2497 static int x2000_pwm_pwm6_e_pins[] = { 0x84, }; 2498 static int x2000_pwm_pwm7_c_pins[] = { 0x47, }; 2499 static int x2000_pwm_pwm7_e_pins[] = { 0x85, }; 2500 static int x2000_pwm_pwm8_pins[] = { 0x48, }; 2501 static int x2000_pwm_pwm9_pins[] = { 0x49, }; 2502 static int x2000_pwm_pwm10_pins[] = { 0x4a, }; 2503 static int x2000_pwm_pwm11_pins[] = { 0x4b, }; 2504 static int x2000_pwm_pwm12_pins[] = { 0x4c, }; 2505 static int x2000_pwm_pwm13_pins[] = { 0x4d, }; 2506 static int x2000_pwm_pwm14_pins[] = { 0x4e, }; 2507 static int x2000_pwm_pwm15_pins[] = { 0x4f, }; 2508 static int x2000_mac0_rmii_pins[] = { 2509 0x4b, 0x47, 0x46, 0x4a, 0x43, 0x42, 0x4c, 0x4d, 0x4e, 0x41, 2510 }; 2511 static int x2000_mac0_rgmii_pins[] = { 2512 0x4b, 0x49, 0x48, 0x47, 0x46, 0x4a, 0x45, 0x44, 0x43, 0x42, 2513 0x4c, 0x4d, 0x4f, 0x4e, 0x41, 2514 }; 2515 static int x2000_mac1_rmii_pins[] = { 2516 0x32, 0x2d, 0x2c, 0x31, 0x29, 0x28, 0x33, 0x34, 0x35, 0x37, 2517 }; 2518 static int x2000_mac1_rgmii_pins[] = { 2519 0x32, 0x2f, 0x2e, 0x2d, 0x2c, 0x31, 0x2b, 0x2a, 0x29, 0x28, 2520 0x33, 0x34, 0x36, 0x35, 0x37, 2521 }; 2522 static int x2000_otg_pins[] = { 0x96, }; 2523 2524 static u8 x2000_cim_8bit_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, }; 2525 2526 static const struct group_desc x2000_groups[] = { 2527 INGENIC_PIN_GROUP("uart0-data", x2000_uart0_data, 2), 2528 INGENIC_PIN_GROUP("uart0-hwflow", x2000_uart0_hwflow, 2), 2529 INGENIC_PIN_GROUP("uart1-data", x2000_uart1_data, 1), 2530 INGENIC_PIN_GROUP("uart1-hwflow", x2000_uart1_hwflow, 1), 2531 INGENIC_PIN_GROUP("uart2-data", x2000_uart2_data, 0), 2532 INGENIC_PIN_GROUP("uart3-data-c", x2000_uart3_data_c, 0), 2533 INGENIC_PIN_GROUP("uart3-data-d", x2000_uart3_data_d, 1), 2534 INGENIC_PIN_GROUP("uart3-hwflow-c", x2000_uart3_hwflow_c, 0), 2535 INGENIC_PIN_GROUP("uart3-hwflow-d", x2000_uart3_hwflow_d, 1), 2536 INGENIC_PIN_GROUP("uart4-data-a", x2000_uart4_data_a, 1), 2537 INGENIC_PIN_GROUP("uart4-data-c", x2000_uart4_data_c, 3), 2538 INGENIC_PIN_GROUP("uart4-hwflow-a", x2000_uart4_hwflow_a, 1), 2539 INGENIC_PIN_GROUP("uart4-hwflow-c", x2000_uart4_hwflow_c, 3), 2540 INGENIC_PIN_GROUP("uart5-data-a", x2000_uart5_data_a, 1), 2541 INGENIC_PIN_GROUP("uart5-data-c", x2000_uart5_data_c, 3), 2542 INGENIC_PIN_GROUP("uart6-data-a", x2000_uart6_data_a, 1), 2543 INGENIC_PIN_GROUP("uart6-data-c", x2000_uart6_data_c, 3), 2544 INGENIC_PIN_GROUP("uart7-data-a", x2000_uart7_data_a, 1), 2545 INGENIC_PIN_GROUP("uart7-data-c", x2000_uart7_data_c, 3), 2546 INGENIC_PIN_GROUP("uart8-data", x2000_uart8_data, 3), 2547 INGENIC_PIN_GROUP("uart9-data", x2000_uart9_data, 3), 2548 INGENIC_PIN_GROUP("sfc0-d", x2000_sfc0_d, 1), 2549 INGENIC_PIN_GROUP("sfc0-e", x2000_sfc0_e, 0), 2550 INGENIC_PIN_GROUP("sfc1", x2000_sfc1, 1), 2551 INGENIC_PIN_GROUP("ssi0-dt-b", x2000_ssi0_dt_b, 1), 2552 INGENIC_PIN_GROUP("ssi0-dt-d", x2000_ssi0_dt_d, 1), 2553 INGENIC_PIN_GROUP("ssi0-dr-b", x2000_ssi0_dr_b, 1), 2554 INGENIC_PIN_GROUP("ssi0-dr-d", x2000_ssi0_dr_d, 1), 2555 INGENIC_PIN_GROUP("ssi0-clk-b", x2000_ssi0_clk_b, 1), 2556 INGENIC_PIN_GROUP("ssi0-clk-d", x2000_ssi0_clk_d, 1), 2557 INGENIC_PIN_GROUP("ssi0-ce0-b", x2000_ssi0_ce0_b, 1), 2558 INGENIC_PIN_GROUP("ssi0-ce0-d", x2000_ssi0_ce0_d, 1), 2559 INGENIC_PIN_GROUP("ssi1-dt-c", x2000_ssi1_dt_c, 2), 2560 INGENIC_PIN_GROUP("ssi1-dt-d", x2000_ssi1_dt_d, 2), 2561 INGENIC_PIN_GROUP("ssi1-dt-e", x2000_ssi1_dt_e, 1), 2562 INGENIC_PIN_GROUP("ssi1-dr-c", x2000_ssi1_dr_c, 2), 2563 INGENIC_PIN_GROUP("ssi1-dr-d", x2000_ssi1_dr_d, 2), 2564 INGENIC_PIN_GROUP("ssi1-dr-e", x2000_ssi1_dr_e, 1), 2565 INGENIC_PIN_GROUP("ssi1-clk-c", x2000_ssi1_clk_c, 2), 2566 INGENIC_PIN_GROUP("ssi1-clk-d", x2000_ssi1_clk_d, 2), 2567 INGENIC_PIN_GROUP("ssi1-clk-e", x2000_ssi1_clk_e, 1), 2568 INGENIC_PIN_GROUP("ssi1-ce0-c", x2000_ssi1_ce0_c, 2), 2569 INGENIC_PIN_GROUP("ssi1-ce0-d", x2000_ssi1_ce0_d, 2), 2570 INGENIC_PIN_GROUP("ssi1-ce0-e", x2000_ssi1_ce0_e, 1), 2571 INGENIC_PIN_GROUP("mmc0-1bit", x2000_mmc0_1bit, 0), 2572 INGENIC_PIN_GROUP("mmc0-4bit", x2000_mmc0_4bit, 0), 2573 INGENIC_PIN_GROUP("mmc0-8bit", x2000_mmc0_8bit, 0), 2574 INGENIC_PIN_GROUP("mmc1-1bit", x2000_mmc1_1bit, 0), 2575 INGENIC_PIN_GROUP("mmc1-4bit", x2000_mmc1_4bit, 0), 2576 INGENIC_PIN_GROUP("mmc2-1bit", x2000_mmc2_1bit, 0), 2577 INGENIC_PIN_GROUP("mmc2-4bit", x2000_mmc2_4bit, 0), 2578 INGENIC_PIN_GROUP("emc-8bit-data", x2000_emc_8bit_data, 0), 2579 INGENIC_PIN_GROUP("emc-16bit-data", x2000_emc_16bit_data, 0), 2580 INGENIC_PIN_GROUP("emc-addr", x2000_emc_addr, 0), 2581 INGENIC_PIN_GROUP("emc-rd-we", x2000_emc_rd_we, 0), 2582 INGENIC_PIN_GROUP("emc-wait", x2000_emc_wait, 0), 2583 INGENIC_PIN_GROUP("emc-cs1", x2000_emc_cs1, 3), 2584 INGENIC_PIN_GROUP("emc-cs2", x2000_emc_cs2, 3), 2585 INGENIC_PIN_GROUP("i2c0-data", x2000_i2c0, 3), 2586 INGENIC_PIN_GROUP("i2c1-data-c", x2000_i2c1_c, 2), 2587 INGENIC_PIN_GROUP("i2c1-data-d", x2000_i2c1_d, 1), 2588 INGENIC_PIN_GROUP("i2c2-data-b", x2000_i2c2_b, 2), 2589 INGENIC_PIN_GROUP("i2c2-data-d", x2000_i2c2_d, 2), 2590 INGENIC_PIN_GROUP("i2c2-data-e", x2000_i2c2_e, 1), 2591 INGENIC_PIN_GROUP("i2c3-data-a", x2000_i2c3_a, 0), 2592 INGENIC_PIN_GROUP("i2c3-data-d", x2000_i2c3_d, 1), 2593 INGENIC_PIN_GROUP("i2c4-data-c", x2000_i2c4_c, 1), 2594 INGENIC_PIN_GROUP("i2c4-data-d", x2000_i2c4_d, 2), 2595 INGENIC_PIN_GROUP("i2c5-data-c", x2000_i2c5_c, 1), 2596 INGENIC_PIN_GROUP("i2c5-data-d", x2000_i2c5_d, 1), 2597 INGENIC_PIN_GROUP("i2s1-data-tx", x2000_i2s1_data_tx, 2), 2598 INGENIC_PIN_GROUP("i2s1-data-rx", x2000_i2s1_data_rx, 2), 2599 INGENIC_PIN_GROUP("i2s1-clk-tx", x2000_i2s1_clk_tx, 2), 2600 INGENIC_PIN_GROUP("i2s1-clk-rx", x2000_i2s1_clk_rx, 2), 2601 INGENIC_PIN_GROUP("i2s1-sysclk-tx", x2000_i2s1_sysclk_tx, 2), 2602 INGENIC_PIN_GROUP("i2s1-sysclk-rx", x2000_i2s1_sysclk_rx, 2), 2603 INGENIC_PIN_GROUP("i2s2-data-rx0", x2000_i2s2_data_rx0, 2), 2604 INGENIC_PIN_GROUP("i2s2-data-rx1", x2000_i2s2_data_rx1, 2), 2605 INGENIC_PIN_GROUP("i2s2-data-rx2", x2000_i2s2_data_rx2, 2), 2606 INGENIC_PIN_GROUP("i2s2-data-rx3", x2000_i2s2_data_rx3, 2), 2607 INGENIC_PIN_GROUP("i2s2-clk-rx", x2000_i2s2_clk_rx, 2), 2608 INGENIC_PIN_GROUP("i2s2-sysclk-rx", x2000_i2s2_sysclk_rx, 2), 2609 INGENIC_PIN_GROUP("i2s3-data-tx0", x2000_i2s3_data_tx0, 2), 2610 INGENIC_PIN_GROUP("i2s3-data-tx1", x2000_i2s3_data_tx1, 2), 2611 INGENIC_PIN_GROUP("i2s3-data-tx2", x2000_i2s3_data_tx2, 2), 2612 INGENIC_PIN_GROUP("i2s3-data-tx3", x2000_i2s3_data_tx3, 2), 2613 INGENIC_PIN_GROUP("i2s3-clk-tx", x2000_i2s3_clk_tx, 2), 2614 INGENIC_PIN_GROUP("i2s3-sysclk-tx", x2000_i2s3_sysclk_tx, 2), 2615 INGENIC_PIN_GROUP("dmic0", x2000_dmic0, 0), 2616 INGENIC_PIN_GROUP("dmic1", x2000_dmic1, 0), 2617 INGENIC_PIN_GROUP("dmic2", x2000_dmic2, 0), 2618 INGENIC_PIN_GROUP("dmic3", x2000_dmic3, 0), 2619 INGENIC_PIN_GROUP_FUNCS("cim-data-8bit", x2000_cim_8bit, 2620 x2000_cim_8bit_funcs), 2621 INGENIC_PIN_GROUP("cim-data-12bit", x2000_cim_12bit, 0), 2622 INGENIC_PIN_GROUP("lcd-tft-8bit", x2000_lcd_tft_8bit, 1), 2623 INGENIC_PIN_GROUP("lcd-tft-16bit", x2000_lcd_tft_16bit, 1), 2624 INGENIC_PIN_GROUP("lcd-tft-18bit", x2000_lcd_tft_18bit, 1), 2625 INGENIC_PIN_GROUP("lcd-tft-24bit", x2000_lcd_tft_24bit, 1), 2626 INGENIC_PIN_GROUP("lcd-slcd-8bit", x2000_lcd_slcd_8bit, 2), 2627 INGENIC_PIN_GROUP("lcd-slcd-16bit", x2000_lcd_tft_16bit, 2), 2628 INGENIC_PIN_GROUP("pwm0-c", x2000_pwm_pwm0_c, 0), 2629 INGENIC_PIN_GROUP("pwm0-d", x2000_pwm_pwm0_d, 2), 2630 INGENIC_PIN_GROUP("pwm1-c", x2000_pwm_pwm1_c, 0), 2631 INGENIC_PIN_GROUP("pwm1-d", x2000_pwm_pwm1_d, 2), 2632 INGENIC_PIN_GROUP("pwm2-c", x2000_pwm_pwm2_c, 0), 2633 INGENIC_PIN_GROUP("pwm2-e", x2000_pwm_pwm2_e, 1), 2634 INGENIC_PIN_GROUP("pwm3-c", x2000_pwm_pwm3_c, 0), 2635 INGENIC_PIN_GROUP("pwm3-e", x2000_pwm_pwm3_e, 1), 2636 INGENIC_PIN_GROUP("pwm4-c", x2000_pwm_pwm4_c, 0), 2637 INGENIC_PIN_GROUP("pwm4-e", x2000_pwm_pwm4_e, 1), 2638 INGENIC_PIN_GROUP("pwm5-c", x2000_pwm_pwm5_c, 0), 2639 INGENIC_PIN_GROUP("pwm5-e", x2000_pwm_pwm5_e, 1), 2640 INGENIC_PIN_GROUP("pwm6-c", x2000_pwm_pwm6_c, 0), 2641 INGENIC_PIN_GROUP("pwm6-e", x2000_pwm_pwm6_e, 1), 2642 INGENIC_PIN_GROUP("pwm7-c", x2000_pwm_pwm7_c, 0), 2643 INGENIC_PIN_GROUP("pwm7-e", x2000_pwm_pwm7_e, 1), 2644 INGENIC_PIN_GROUP("pwm8", x2000_pwm_pwm8, 0), 2645 INGENIC_PIN_GROUP("pwm9", x2000_pwm_pwm9, 0), 2646 INGENIC_PIN_GROUP("pwm10", x2000_pwm_pwm10, 0), 2647 INGENIC_PIN_GROUP("pwm11", x2000_pwm_pwm11, 0), 2648 INGENIC_PIN_GROUP("pwm12", x2000_pwm_pwm12, 0), 2649 INGENIC_PIN_GROUP("pwm13", x2000_pwm_pwm13, 0), 2650 INGENIC_PIN_GROUP("pwm14", x2000_pwm_pwm14, 0), 2651 INGENIC_PIN_GROUP("pwm15", x2000_pwm_pwm15, 0), 2652 INGENIC_PIN_GROUP("mac0-rmii", x2000_mac0_rmii, 1), 2653 INGENIC_PIN_GROUP("mac0-rgmii", x2000_mac0_rgmii, 1), 2654 INGENIC_PIN_GROUP("mac1-rmii", x2000_mac1_rmii, 3), 2655 INGENIC_PIN_GROUP("mac1-rgmii", x2000_mac1_rgmii, 3), 2656 INGENIC_PIN_GROUP("otg-vbus", x2000_otg, 0), 2657 }; 2658 2659 static const char *x2000_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; 2660 static const char *x2000_uart1_groups[] = { "uart1-data", "uart1-hwflow", }; 2661 static const char *x2000_uart2_groups[] = { "uart2-data", }; 2662 static const char *x2000_uart3_groups[] = { 2663 "uart3-data-c", "uart3-data-d", "uart3-hwflow-c", "uart3-hwflow-d", 2664 }; 2665 static const char *x2000_uart4_groups[] = { 2666 "uart4-data-a", "uart4-data-c", "uart4-hwflow-a", "uart4-hwflow-c", 2667 }; 2668 static const char *x2000_uart5_groups[] = { "uart5-data-a", "uart5-data-c", }; 2669 static const char *x2000_uart6_groups[] = { "uart6-data-a", "uart6-data-c", }; 2670 static const char *x2000_uart7_groups[] = { "uart7-data-a", "uart7-data-c", }; 2671 static const char *x2000_uart8_groups[] = { "uart8-data", }; 2672 static const char *x2000_uart9_groups[] = { "uart9-data", }; 2673 static const char *x2000_sfc_groups[] = { "sfc0-d", "sfc0-e", "sfc1", }; 2674 static const char *x2000_ssi0_groups[] = { 2675 "ssi0-dt-b", "ssi0-dt-d", 2676 "ssi0-dr-b", "ssi0-dr-d", 2677 "ssi0-clk-b", "ssi0-clk-d", 2678 "ssi0-ce0-b", "ssi0-ce0-d", 2679 }; 2680 static const char *x2000_ssi1_groups[] = { 2681 "ssi1-dt-c", "ssi1-dt-d", "ssi1-dt-e", 2682 "ssi1-dr-c", "ssi1-dr-d", "ssi1-dr-e", 2683 "ssi1-clk-c", "ssi1-clk-d", "ssi1-clk-e", 2684 "ssi1-ce0-c", "ssi1-ce0-d", "ssi1-ce0-e", 2685 }; 2686 static const char *x2000_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", "mmc0-8bit", }; 2687 static const char *x2000_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", }; 2688 static const char *x2000_mmc2_groups[] = { "mmc2-1bit", "mmc2-4bit", }; 2689 static const char *x2000_emc_groups[] = { 2690 "emc-8bit-data", "emc-16bit-data", 2691 "emc-addr", "emc-rd-we", "emc-wait", 2692 }; 2693 static const char *x2000_cs1_groups[] = { "emc-cs1", }; 2694 static const char *x2000_cs2_groups[] = { "emc-cs2", }; 2695 static const char *x2000_i2c0_groups[] = { "i2c0-data", }; 2696 static const char *x2000_i2c1_groups[] = { "i2c1-data-c", "i2c1-data-d", }; 2697 static const char *x2000_i2c2_groups[] = { "i2c2-data-b", "i2c2-data-d", }; 2698 static const char *x2000_i2c3_groups[] = { "i2c3-data-a", "i2c3-data-d", }; 2699 static const char *x2000_i2c4_groups[] = { "i2c4-data-c", "i2c4-data-d", }; 2700 static const char *x2000_i2c5_groups[] = { "i2c5-data-c", "i2c5-data-d", }; 2701 static const char *x2000_i2s1_groups[] = { 2702 "i2s1-data-tx", "i2s1-data-rx", 2703 "i2s1-clk-tx", "i2s1-clk-rx", 2704 "i2s1-sysclk-tx", "i2s1-sysclk-rx", 2705 }; 2706 static const char *x2000_i2s2_groups[] = { 2707 "i2s2-data-rx0", "i2s2-data-rx1", "i2s2-data-rx2", "i2s2-data-rx3", 2708 "i2s2-clk-rx", "i2s2-sysclk-rx", 2709 }; 2710 static const char *x2000_i2s3_groups[] = { 2711 "i2s3-data-tx0", "i2s3-data-tx1", "i2s3-data-tx2", "i2s3-data-tx3", 2712 "i2s3-clk-tx", "i2s3-sysclk-tx", 2713 }; 2714 static const char *x2000_dmic_groups[] = { "dmic0", "dmic1", "dmic2", "dmic3", }; 2715 static const char *x2000_cim_groups[] = { "cim-data-8bit", "cim-data-12bit", }; 2716 static const char *x2000_lcd_groups[] = { 2717 "lcd-tft-8bit", "lcd-tft-16bit", "lcd-tft-18bit", "lcd-tft-24bit", 2718 "lcd-slcd-8bit", "lcd-slcd-16bit", 2719 }; 2720 static const char *x2000_pwm0_groups[] = { "pwm0-c", "pwm0-d", }; 2721 static const char *x2000_pwm1_groups[] = { "pwm1-c", "pwm1-d", }; 2722 static const char *x2000_pwm2_groups[] = { "pwm2-c", "pwm2-e", }; 2723 static const char *x2000_pwm3_groups[] = { "pwm3-c", "pwm3-r", }; 2724 static const char *x2000_pwm4_groups[] = { "pwm4-c", "pwm4-e", }; 2725 static const char *x2000_pwm5_groups[] = { "pwm5-c", "pwm5-e", }; 2726 static const char *x2000_pwm6_groups[] = { "pwm6-c", "pwm6-e", }; 2727 static const char *x2000_pwm7_groups[] = { "pwm7-c", "pwm7-e", }; 2728 static const char *x2000_pwm8_groups[] = { "pwm8", }; 2729 static const char *x2000_pwm9_groups[] = { "pwm9", }; 2730 static const char *x2000_pwm10_groups[] = { "pwm10", }; 2731 static const char *x2000_pwm11_groups[] = { "pwm11", }; 2732 static const char *x2000_pwm12_groups[] = { "pwm12", }; 2733 static const char *x2000_pwm13_groups[] = { "pwm13", }; 2734 static const char *x2000_pwm14_groups[] = { "pwm14", }; 2735 static const char *x2000_pwm15_groups[] = { "pwm15", }; 2736 static const char *x2000_mac0_groups[] = { "mac0-rmii", "mac0-rgmii", }; 2737 static const char *x2000_mac1_groups[] = { "mac1-rmii", "mac1-rgmii", }; 2738 static const char *x2000_otg_groups[] = { "otg-vbus", }; 2739 2740 static const struct function_desc x2000_functions[] = { 2741 { "uart0", x2000_uart0_groups, ARRAY_SIZE(x2000_uart0_groups), }, 2742 { "uart1", x2000_uart1_groups, ARRAY_SIZE(x2000_uart1_groups), }, 2743 { "uart2", x2000_uart2_groups, ARRAY_SIZE(x2000_uart2_groups), }, 2744 { "uart3", x2000_uart3_groups, ARRAY_SIZE(x2000_uart3_groups), }, 2745 { "uart4", x2000_uart4_groups, ARRAY_SIZE(x2000_uart4_groups), }, 2746 { "uart5", x2000_uart5_groups, ARRAY_SIZE(x2000_uart5_groups), }, 2747 { "uart6", x2000_uart6_groups, ARRAY_SIZE(x2000_uart6_groups), }, 2748 { "uart7", x2000_uart7_groups, ARRAY_SIZE(x2000_uart7_groups), }, 2749 { "uart8", x2000_uart8_groups, ARRAY_SIZE(x2000_uart8_groups), }, 2750 { "uart9", x2000_uart9_groups, ARRAY_SIZE(x2000_uart9_groups), }, 2751 { "sfc", x2000_sfc_groups, ARRAY_SIZE(x2000_sfc_groups), }, 2752 { "ssi0", x2000_ssi0_groups, ARRAY_SIZE(x2000_ssi0_groups), }, 2753 { "ssi1", x2000_ssi1_groups, ARRAY_SIZE(x2000_ssi1_groups), }, 2754 { "mmc0", x2000_mmc0_groups, ARRAY_SIZE(x2000_mmc0_groups), }, 2755 { "mmc1", x2000_mmc1_groups, ARRAY_SIZE(x2000_mmc1_groups), }, 2756 { "mmc2", x2000_mmc2_groups, ARRAY_SIZE(x2000_mmc2_groups), }, 2757 { "emc", x2000_emc_groups, ARRAY_SIZE(x2000_emc_groups), }, 2758 { "emc-cs1", x2000_cs1_groups, ARRAY_SIZE(x2000_cs1_groups), }, 2759 { "emc-cs2", x2000_cs2_groups, ARRAY_SIZE(x2000_cs2_groups), }, 2760 { "i2c0", x2000_i2c0_groups, ARRAY_SIZE(x2000_i2c0_groups), }, 2761 { "i2c1", x2000_i2c1_groups, ARRAY_SIZE(x2000_i2c1_groups), }, 2762 { "i2c2", x2000_i2c2_groups, ARRAY_SIZE(x2000_i2c2_groups), }, 2763 { "i2c3", x2000_i2c3_groups, ARRAY_SIZE(x2000_i2c3_groups), }, 2764 { "i2c4", x2000_i2c4_groups, ARRAY_SIZE(x2000_i2c4_groups), }, 2765 { "i2c5", x2000_i2c5_groups, ARRAY_SIZE(x2000_i2c5_groups), }, 2766 { "i2s1", x2000_i2s1_groups, ARRAY_SIZE(x2000_i2s1_groups), }, 2767 { "i2s2", x2000_i2s2_groups, ARRAY_SIZE(x2000_i2s2_groups), }, 2768 { "i2s3", x2000_i2s3_groups, ARRAY_SIZE(x2000_i2s3_groups), }, 2769 { "dmic", x2000_dmic_groups, ARRAY_SIZE(x2000_dmic_groups), }, 2770 { "cim", x2000_cim_groups, ARRAY_SIZE(x2000_cim_groups), }, 2771 { "lcd", x2000_lcd_groups, ARRAY_SIZE(x2000_lcd_groups), }, 2772 { "pwm0", x2000_pwm0_groups, ARRAY_SIZE(x2000_pwm0_groups), }, 2773 { "pwm1", x2000_pwm1_groups, ARRAY_SIZE(x2000_pwm1_groups), }, 2774 { "pwm2", x2000_pwm2_groups, ARRAY_SIZE(x2000_pwm2_groups), }, 2775 { "pwm3", x2000_pwm3_groups, ARRAY_SIZE(x2000_pwm3_groups), }, 2776 { "pwm4", x2000_pwm4_groups, ARRAY_SIZE(x2000_pwm4_groups), }, 2777 { "pwm5", x2000_pwm5_groups, ARRAY_SIZE(x2000_pwm5_groups), }, 2778 { "pwm6", x2000_pwm6_groups, ARRAY_SIZE(x2000_pwm6_groups), }, 2779 { "pwm7", x2000_pwm7_groups, ARRAY_SIZE(x2000_pwm7_groups), }, 2780 { "pwm8", x2000_pwm8_groups, ARRAY_SIZE(x2000_pwm8_groups), }, 2781 { "pwm9", x2000_pwm9_groups, ARRAY_SIZE(x2000_pwm9_groups), }, 2782 { "pwm10", x2000_pwm10_groups, ARRAY_SIZE(x2000_pwm10_groups), }, 2783 { "pwm11", x2000_pwm11_groups, ARRAY_SIZE(x2000_pwm11_groups), }, 2784 { "pwm12", x2000_pwm12_groups, ARRAY_SIZE(x2000_pwm12_groups), }, 2785 { "pwm13", x2000_pwm13_groups, ARRAY_SIZE(x2000_pwm13_groups), }, 2786 { "pwm14", x2000_pwm14_groups, ARRAY_SIZE(x2000_pwm14_groups), }, 2787 { "pwm15", x2000_pwm15_groups, ARRAY_SIZE(x2000_pwm15_groups), }, 2788 { "mac0", x2000_mac0_groups, ARRAY_SIZE(x2000_mac0_groups), }, 2789 { "mac1", x2000_mac1_groups, ARRAY_SIZE(x2000_mac1_groups), }, 2790 { "otg", x2000_otg_groups, ARRAY_SIZE(x2000_otg_groups), }, 2791 }; 2792 2793 static const struct ingenic_chip_info x2000_chip_info = { 2794 .num_chips = 5, 2795 .reg_offset = 0x100, 2796 .version = ID_X2000, 2797 .groups = x2000_groups, 2798 .num_groups = ARRAY_SIZE(x2000_groups), 2799 .functions = x2000_functions, 2800 .num_functions = ARRAY_SIZE(x2000_functions), 2801 .pull_ups = x2000_pull_ups, 2802 .pull_downs = x2000_pull_downs, 2803 }; 2804 2805 static u32 ingenic_gpio_read_reg(struct ingenic_gpio_chip *jzgc, u8 reg) 2806 { 2807 unsigned int val; 2808 2809 regmap_read(jzgc->jzpc->map, jzgc->reg_base + reg, &val); 2810 2811 return (u32) val; 2812 } 2813 2814 static void ingenic_gpio_set_bit(struct ingenic_gpio_chip *jzgc, 2815 u8 reg, u8 offset, bool set) 2816 { 2817 if (jzgc->jzpc->info->version == ID_JZ4730) { 2818 regmap_update_bits(jzgc->jzpc->map, jzgc->reg_base + reg, 2819 BIT(offset), set ? BIT(offset) : 0); 2820 return; 2821 } 2822 2823 if (set) 2824 reg = REG_SET(reg); 2825 else 2826 reg = REG_CLEAR(reg); 2827 2828 regmap_write(jzgc->jzpc->map, jzgc->reg_base + reg, BIT(offset)); 2829 } 2830 2831 static void ingenic_gpio_shadow_set_bit(struct ingenic_gpio_chip *jzgc, 2832 u8 reg, u8 offset, bool set) 2833 { 2834 if (set) 2835 reg = REG_SET(reg); 2836 else 2837 reg = REG_CLEAR(reg); 2838 2839 regmap_write(jzgc->jzpc->map, REG_PZ_BASE( 2840 jzgc->jzpc->info->reg_offset) + reg, BIT(offset)); 2841 } 2842 2843 static void ingenic_gpio_shadow_set_bit_load(struct ingenic_gpio_chip *jzgc) 2844 { 2845 regmap_write(jzgc->jzpc->map, REG_PZ_GID2LD( 2846 jzgc->jzpc->info->reg_offset), 2847 jzgc->gc.base / PINS_PER_GPIO_CHIP); 2848 } 2849 2850 static void jz4730_gpio_set_bits(struct ingenic_gpio_chip *jzgc, 2851 u8 reg_upper, u8 reg_lower, u8 offset, u8 value) 2852 { 2853 /* 2854 * JZ4730 function and IRQ registers support two-bits-per-pin 2855 * definitions, split into two groups of 16. 2856 */ 2857 u8 reg = offset < JZ4730_PINS_PER_PAIRED_REG ? reg_lower : reg_upper; 2858 unsigned int idx = offset % JZ4730_PINS_PER_PAIRED_REG; 2859 unsigned int mask = GENMASK(1, 0) << idx * 2; 2860 2861 regmap_update_bits(jzgc->jzpc->map, jzgc->reg_base + reg, mask, value << (idx * 2)); 2862 } 2863 2864 static inline bool ingenic_gpio_get_value(struct ingenic_gpio_chip *jzgc, 2865 u8 offset) 2866 { 2867 unsigned int val = ingenic_gpio_read_reg(jzgc, GPIO_PIN); 2868 2869 return !!(val & BIT(offset)); 2870 } 2871 2872 static void ingenic_gpio_set_value(struct ingenic_gpio_chip *jzgc, 2873 u8 offset, int value) 2874 { 2875 if (jzgc->jzpc->info->version >= ID_JZ4770) 2876 ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_PAT0, offset, !!value); 2877 else if (jzgc->jzpc->info->version >= ID_JZ4740) 2878 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_DATA, offset, !!value); 2879 else 2880 ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_DATA, offset, !!value); 2881 } 2882 2883 static void irq_set_type(struct ingenic_gpio_chip *jzgc, 2884 u8 offset, unsigned int type) 2885 { 2886 u8 reg1, reg2; 2887 bool val1, val2, val3; 2888 2889 switch (type) { 2890 case IRQ_TYPE_EDGE_BOTH: 2891 val1 = val2 = false; 2892 val3 = true; 2893 break; 2894 case IRQ_TYPE_EDGE_RISING: 2895 val1 = val2 = true; 2896 val3 = false; 2897 break; 2898 case IRQ_TYPE_EDGE_FALLING: 2899 val1 = val3 = false; 2900 val2 = true; 2901 break; 2902 case IRQ_TYPE_LEVEL_HIGH: 2903 val1 = true; 2904 val2 = val3 = false; 2905 break; 2906 case IRQ_TYPE_LEVEL_LOW: 2907 default: 2908 val1 = val2 = val3 = false; 2909 break; 2910 } 2911 2912 if (jzgc->jzpc->info->version >= ID_JZ4770) { 2913 reg1 = JZ4770_GPIO_PAT1; 2914 reg2 = JZ4770_GPIO_PAT0; 2915 } else if (jzgc->jzpc->info->version >= ID_JZ4740) { 2916 reg1 = JZ4740_GPIO_TRIG; 2917 reg2 = JZ4740_GPIO_DIR; 2918 } else { 2919 ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPDIR, offset, false); 2920 jz4730_gpio_set_bits(jzgc, JZ4730_GPIO_GPIDUR, 2921 JZ4730_GPIO_GPIDLR, offset, (val2 << 1) | val1); 2922 return; 2923 } 2924 2925 if (jzgc->jzpc->info->version >= ID_X2000) { 2926 ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, val1); 2927 ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, val2); 2928 ingenic_gpio_shadow_set_bit_load(jzgc); 2929 ingenic_gpio_set_bit(jzgc, X2000_GPIO_EDG, offset, val3); 2930 } else if (jzgc->jzpc->info->version >= ID_X1000) { 2931 ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, val1); 2932 ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, val2); 2933 ingenic_gpio_shadow_set_bit_load(jzgc); 2934 } else { 2935 ingenic_gpio_set_bit(jzgc, reg2, offset, val1); 2936 ingenic_gpio_set_bit(jzgc, reg1, offset, val2); 2937 } 2938 } 2939 2940 static void ingenic_gpio_irq_mask(struct irq_data *irqd) 2941 { 2942 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); 2943 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 2944 int irq = irqd->hwirq; 2945 2946 if (jzgc->jzpc->info->version >= ID_JZ4740) 2947 ingenic_gpio_set_bit(jzgc, GPIO_MSK, irq, true); 2948 else 2949 ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPIMR, irq, true); 2950 } 2951 2952 static void ingenic_gpio_irq_unmask(struct irq_data *irqd) 2953 { 2954 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); 2955 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 2956 int irq = irqd->hwirq; 2957 2958 if (jzgc->jzpc->info->version >= ID_JZ4740) 2959 ingenic_gpio_set_bit(jzgc, GPIO_MSK, irq, false); 2960 else 2961 ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPIMR, irq, false); 2962 } 2963 2964 static void ingenic_gpio_irq_enable(struct irq_data *irqd) 2965 { 2966 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); 2967 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 2968 int irq = irqd->hwirq; 2969 2970 if (jzgc->jzpc->info->version >= ID_JZ4770) 2971 ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_INT, irq, true); 2972 else if (jzgc->jzpc->info->version >= ID_JZ4740) 2973 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, true); 2974 else 2975 ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPIER, irq, true); 2976 2977 ingenic_gpio_irq_unmask(irqd); 2978 } 2979 2980 static void ingenic_gpio_irq_disable(struct irq_data *irqd) 2981 { 2982 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); 2983 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 2984 int irq = irqd->hwirq; 2985 2986 ingenic_gpio_irq_mask(irqd); 2987 2988 if (jzgc->jzpc->info->version >= ID_JZ4770) 2989 ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_INT, irq, false); 2990 else if (jzgc->jzpc->info->version >= ID_JZ4740) 2991 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, false); 2992 else 2993 ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPIER, irq, false); 2994 } 2995 2996 static void ingenic_gpio_irq_ack(struct irq_data *irqd) 2997 { 2998 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); 2999 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 3000 int irq = irqd->hwirq; 3001 bool high; 3002 3003 if ((irqd_get_trigger_type(irqd) == IRQ_TYPE_EDGE_BOTH) && 3004 (jzgc->jzpc->info->version < ID_X2000)) { 3005 /* 3006 * Switch to an interrupt for the opposite edge to the one that 3007 * triggered the interrupt being ACKed. 3008 */ 3009 high = ingenic_gpio_get_value(jzgc, irq); 3010 if (high) 3011 irq_set_type(jzgc, irq, IRQ_TYPE_LEVEL_LOW); 3012 else 3013 irq_set_type(jzgc, irq, IRQ_TYPE_LEVEL_HIGH); 3014 } 3015 3016 if (jzgc->jzpc->info->version >= ID_JZ4770) 3017 ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_FLAG, irq, false); 3018 else if (jzgc->jzpc->info->version >= ID_JZ4740) 3019 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_DATA, irq, true); 3020 else 3021 ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPFR, irq, false); 3022 } 3023 3024 static int ingenic_gpio_irq_set_type(struct irq_data *irqd, unsigned int type) 3025 { 3026 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); 3027 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 3028 3029 switch (type) { 3030 case IRQ_TYPE_EDGE_BOTH: 3031 case IRQ_TYPE_EDGE_RISING: 3032 case IRQ_TYPE_EDGE_FALLING: 3033 irq_set_handler_locked(irqd, handle_edge_irq); 3034 break; 3035 case IRQ_TYPE_LEVEL_HIGH: 3036 case IRQ_TYPE_LEVEL_LOW: 3037 irq_set_handler_locked(irqd, handle_level_irq); 3038 break; 3039 default: 3040 irq_set_handler_locked(irqd, handle_bad_irq); 3041 } 3042 3043 if ((type == IRQ_TYPE_EDGE_BOTH) && (jzgc->jzpc->info->version < ID_X2000)) { 3044 /* 3045 * The hardware does not support interrupts on both edges. The 3046 * best we can do is to set up a single-edge interrupt and then 3047 * switch to the opposing edge when ACKing the interrupt. 3048 */ 3049 bool high = ingenic_gpio_get_value(jzgc, irqd->hwirq); 3050 3051 type = high ? IRQ_TYPE_LEVEL_LOW : IRQ_TYPE_LEVEL_HIGH; 3052 } 3053 3054 irq_set_type(jzgc, irqd->hwirq, type); 3055 return 0; 3056 } 3057 3058 static int ingenic_gpio_irq_set_wake(struct irq_data *irqd, unsigned int on) 3059 { 3060 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); 3061 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 3062 3063 return irq_set_irq_wake(jzgc->irq, on); 3064 } 3065 3066 static void ingenic_gpio_irq_handler(struct irq_desc *desc) 3067 { 3068 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 3069 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 3070 struct irq_chip *irq_chip = irq_data_get_irq_chip(&desc->irq_data); 3071 unsigned long flag, i; 3072 3073 chained_irq_enter(irq_chip, desc); 3074 3075 if (jzgc->jzpc->info->version >= ID_JZ4770) 3076 flag = ingenic_gpio_read_reg(jzgc, JZ4770_GPIO_FLAG); 3077 else if (jzgc->jzpc->info->version >= ID_JZ4740) 3078 flag = ingenic_gpio_read_reg(jzgc, JZ4740_GPIO_FLAG); 3079 else 3080 flag = ingenic_gpio_read_reg(jzgc, JZ4730_GPIO_GPFR); 3081 3082 for_each_set_bit(i, &flag, 32) 3083 generic_handle_irq(irq_linear_revmap(gc->irq.domain, i)); 3084 chained_irq_exit(irq_chip, desc); 3085 } 3086 3087 static void ingenic_gpio_set(struct gpio_chip *gc, 3088 unsigned int offset, int value) 3089 { 3090 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 3091 3092 ingenic_gpio_set_value(jzgc, offset, value); 3093 } 3094 3095 static int ingenic_gpio_get(struct gpio_chip *gc, unsigned int offset) 3096 { 3097 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 3098 3099 return (int) ingenic_gpio_get_value(jzgc, offset); 3100 } 3101 3102 static int ingenic_gpio_direction_input(struct gpio_chip *gc, 3103 unsigned int offset) 3104 { 3105 return pinctrl_gpio_direction_input(gc->base + offset); 3106 } 3107 3108 static int ingenic_gpio_direction_output(struct gpio_chip *gc, 3109 unsigned int offset, int value) 3110 { 3111 ingenic_gpio_set(gc, offset, value); 3112 return pinctrl_gpio_direction_output(gc->base + offset); 3113 } 3114 3115 static inline void ingenic_config_pin(struct ingenic_pinctrl *jzpc, 3116 unsigned int pin, unsigned int reg, bool set) 3117 { 3118 unsigned int idx = pin % PINS_PER_GPIO_CHIP; 3119 unsigned int offt = pin / PINS_PER_GPIO_CHIP; 3120 3121 if (set) { 3122 if (jzpc->info->version >= ID_JZ4740) 3123 regmap_write(jzpc->map, offt * jzpc->info->reg_offset + 3124 REG_SET(reg), BIT(idx)); 3125 else 3126 regmap_set_bits(jzpc->map, offt * jzpc->info->reg_offset + 3127 reg, BIT(idx)); 3128 } else { 3129 if (jzpc->info->version >= ID_JZ4740) 3130 regmap_write(jzpc->map, offt * jzpc->info->reg_offset + 3131 REG_CLEAR(reg), BIT(idx)); 3132 else 3133 regmap_clear_bits(jzpc->map, offt * jzpc->info->reg_offset + 3134 reg, BIT(idx)); 3135 } 3136 } 3137 3138 static inline void ingenic_shadow_config_pin(struct ingenic_pinctrl *jzpc, 3139 unsigned int pin, u8 reg, bool set) 3140 { 3141 unsigned int idx = pin % PINS_PER_GPIO_CHIP; 3142 3143 regmap_write(jzpc->map, REG_PZ_BASE(jzpc->info->reg_offset) + 3144 (set ? REG_SET(reg) : REG_CLEAR(reg)), BIT(idx)); 3145 } 3146 3147 static inline void ingenic_shadow_config_pin_load(struct ingenic_pinctrl *jzpc, 3148 unsigned int pin) 3149 { 3150 regmap_write(jzpc->map, REG_PZ_GID2LD(jzpc->info->reg_offset), 3151 pin / PINS_PER_GPIO_CHIP); 3152 } 3153 3154 static inline void jz4730_config_pin_function(struct ingenic_pinctrl *jzpc, 3155 unsigned int pin, u8 reg_upper, u8 reg_lower, u8 value) 3156 { 3157 /* 3158 * JZ4730 function and IRQ registers support two-bits-per-pin 3159 * definitions, split into two groups of 16. 3160 */ 3161 unsigned int idx = pin % JZ4730_PINS_PER_PAIRED_REG; 3162 unsigned int mask = GENMASK(1, 0) << idx * 2; 3163 unsigned int offt = pin / PINS_PER_GPIO_CHIP; 3164 u8 reg = (pin % PINS_PER_GPIO_CHIP) < JZ4730_PINS_PER_PAIRED_REG ? reg_lower : reg_upper; 3165 3166 regmap_update_bits(jzpc->map, offt * jzpc->info->reg_offset + reg, 3167 mask, value << (idx * 2)); 3168 } 3169 3170 static inline bool ingenic_get_pin_config(struct ingenic_pinctrl *jzpc, 3171 unsigned int pin, unsigned int reg) 3172 { 3173 unsigned int idx = pin % PINS_PER_GPIO_CHIP; 3174 unsigned int offt = pin / PINS_PER_GPIO_CHIP; 3175 unsigned int val; 3176 3177 regmap_read(jzpc->map, offt * jzpc->info->reg_offset + reg, &val); 3178 3179 return val & BIT(idx); 3180 } 3181 3182 static int ingenic_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) 3183 { 3184 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 3185 struct ingenic_pinctrl *jzpc = jzgc->jzpc; 3186 unsigned int pin = gc->base + offset; 3187 3188 if (jzpc->info->version >= ID_JZ4770) { 3189 if (ingenic_get_pin_config(jzpc, pin, JZ4770_GPIO_INT) || 3190 ingenic_get_pin_config(jzpc, pin, JZ4770_GPIO_PAT1)) 3191 return GPIO_LINE_DIRECTION_IN; 3192 return GPIO_LINE_DIRECTION_OUT; 3193 } else if (jzpc->info->version == ID_JZ4730) { 3194 if (!ingenic_get_pin_config(jzpc, pin, JZ4730_GPIO_GPDIR)) 3195 return GPIO_LINE_DIRECTION_IN; 3196 return GPIO_LINE_DIRECTION_OUT; 3197 } 3198 3199 if (ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_SELECT)) 3200 return GPIO_LINE_DIRECTION_IN; 3201 3202 if (ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_DIR)) 3203 return GPIO_LINE_DIRECTION_OUT; 3204 3205 return GPIO_LINE_DIRECTION_IN; 3206 } 3207 3208 static const struct pinctrl_ops ingenic_pctlops = { 3209 .get_groups_count = pinctrl_generic_get_group_count, 3210 .get_group_name = pinctrl_generic_get_group_name, 3211 .get_group_pins = pinctrl_generic_get_group_pins, 3212 .dt_node_to_map = pinconf_generic_dt_node_to_map_all, 3213 .dt_free_map = pinconf_generic_dt_free_map, 3214 }; 3215 3216 static int ingenic_gpio_irq_request(struct irq_data *data) 3217 { 3218 struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data); 3219 int ret; 3220 3221 ret = ingenic_gpio_direction_input(gpio_chip, data->hwirq); 3222 if (ret) 3223 return ret; 3224 3225 return gpiochip_reqres_irq(gpio_chip, data->hwirq); 3226 } 3227 3228 static void ingenic_gpio_irq_release(struct irq_data *data) 3229 { 3230 struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data); 3231 3232 return gpiochip_relres_irq(gpio_chip, data->hwirq); 3233 } 3234 3235 static int ingenic_pinmux_set_pin_fn(struct ingenic_pinctrl *jzpc, 3236 int pin, int func) 3237 { 3238 unsigned int idx = pin % PINS_PER_GPIO_CHIP; 3239 unsigned int offt = pin / PINS_PER_GPIO_CHIP; 3240 3241 dev_dbg(jzpc->dev, "set pin P%c%u to function %u\n", 3242 'A' + offt, idx, func); 3243 3244 if (jzpc->info->version >= ID_X1000) { 3245 ingenic_shadow_config_pin(jzpc, pin, JZ4770_GPIO_INT, false); 3246 ingenic_shadow_config_pin(jzpc, pin, GPIO_MSK, false); 3247 ingenic_shadow_config_pin(jzpc, pin, JZ4770_GPIO_PAT1, func & 0x2); 3248 ingenic_shadow_config_pin(jzpc, pin, JZ4770_GPIO_PAT0, func & 0x1); 3249 ingenic_shadow_config_pin_load(jzpc, pin); 3250 } else if (jzpc->info->version >= ID_JZ4770) { 3251 ingenic_config_pin(jzpc, pin, JZ4770_GPIO_INT, false); 3252 ingenic_config_pin(jzpc, pin, GPIO_MSK, false); 3253 ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PAT1, func & 0x2); 3254 ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PAT0, func & 0x1); 3255 } else if (jzpc->info->version >= ID_JZ4740) { 3256 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_FUNC, true); 3257 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_TRIG, func & 0x2); 3258 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_SELECT, func & 0x1); 3259 } else { 3260 ingenic_config_pin(jzpc, pin, JZ4730_GPIO_GPIER, false); 3261 jz4730_config_pin_function(jzpc, pin, JZ4730_GPIO_GPAUR, JZ4730_GPIO_GPALR, func); 3262 } 3263 3264 return 0; 3265 } 3266 3267 static int ingenic_pinmux_set_mux(struct pinctrl_dev *pctldev, 3268 unsigned int selector, unsigned int group) 3269 { 3270 struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev); 3271 struct function_desc *func; 3272 struct group_desc *grp; 3273 unsigned int i; 3274 uintptr_t mode; 3275 u8 *pin_modes; 3276 3277 func = pinmux_generic_get_function(pctldev, selector); 3278 if (!func) 3279 return -EINVAL; 3280 3281 grp = pinctrl_generic_get_group(pctldev, group); 3282 if (!grp) 3283 return -EINVAL; 3284 3285 dev_dbg(pctldev->dev, "enable function %s group %s\n", 3286 func->name, grp->name); 3287 3288 mode = (uintptr_t)grp->data; 3289 if (mode <= 3) { 3290 for (i = 0; i < grp->num_pins; i++) 3291 ingenic_pinmux_set_pin_fn(jzpc, grp->pins[i], mode); 3292 } else { 3293 pin_modes = grp->data; 3294 3295 for (i = 0; i < grp->num_pins; i++) 3296 ingenic_pinmux_set_pin_fn(jzpc, grp->pins[i], pin_modes[i]); 3297 } 3298 3299 return 0; 3300 } 3301 3302 static int ingenic_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev, 3303 struct pinctrl_gpio_range *range, 3304 unsigned int pin, bool input) 3305 { 3306 struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev); 3307 unsigned int idx = pin % PINS_PER_GPIO_CHIP; 3308 unsigned int offt = pin / PINS_PER_GPIO_CHIP; 3309 3310 dev_dbg(pctldev->dev, "set pin P%c%u to %sput\n", 3311 'A' + offt, idx, input ? "in" : "out"); 3312 3313 if (jzpc->info->version >= ID_X1000) { 3314 ingenic_shadow_config_pin(jzpc, pin, JZ4770_GPIO_INT, false); 3315 ingenic_shadow_config_pin(jzpc, pin, GPIO_MSK, true); 3316 ingenic_shadow_config_pin(jzpc, pin, JZ4770_GPIO_PAT1, input); 3317 ingenic_shadow_config_pin_load(jzpc, pin); 3318 } else if (jzpc->info->version >= ID_JZ4770) { 3319 ingenic_config_pin(jzpc, pin, JZ4770_GPIO_INT, false); 3320 ingenic_config_pin(jzpc, pin, GPIO_MSK, true); 3321 ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PAT1, input); 3322 } else if (jzpc->info->version >= ID_JZ4740) { 3323 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_SELECT, false); 3324 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_DIR, !input); 3325 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_FUNC, false); 3326 } else { 3327 ingenic_config_pin(jzpc, pin, JZ4730_GPIO_GPIER, false); 3328 ingenic_config_pin(jzpc, pin, JZ4730_GPIO_GPDIR, !input); 3329 jz4730_config_pin_function(jzpc, pin, JZ4730_GPIO_GPAUR, JZ4730_GPIO_GPALR, 0); 3330 } 3331 3332 return 0; 3333 } 3334 3335 static const struct pinmux_ops ingenic_pmxops = { 3336 .get_functions_count = pinmux_generic_get_function_count, 3337 .get_function_name = pinmux_generic_get_function_name, 3338 .get_function_groups = pinmux_generic_get_function_groups, 3339 .set_mux = ingenic_pinmux_set_mux, 3340 .gpio_set_direction = ingenic_pinmux_gpio_set_direction, 3341 }; 3342 3343 static int ingenic_pinconf_get(struct pinctrl_dev *pctldev, 3344 unsigned int pin, unsigned long *config) 3345 { 3346 struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev); 3347 enum pin_config_param param = pinconf_to_config_param(*config); 3348 unsigned int idx = pin % PINS_PER_GPIO_CHIP; 3349 unsigned int offt = pin / PINS_PER_GPIO_CHIP; 3350 unsigned int arg = 1; 3351 unsigned int bias, reg; 3352 bool pull, pullup, pulldown; 3353 3354 if (jzpc->info->version >= ID_X2000) { 3355 pullup = ingenic_get_pin_config(jzpc, pin, X2000_GPIO_PEPU) && 3356 !ingenic_get_pin_config(jzpc, pin, X2000_GPIO_PEPD) && 3357 (jzpc->info->pull_ups[offt] & BIT(idx)); 3358 pulldown = ingenic_get_pin_config(jzpc, pin, X2000_GPIO_PEPD) && 3359 !ingenic_get_pin_config(jzpc, pin, X2000_GPIO_PEPU) && 3360 (jzpc->info->pull_downs[offt] & BIT(idx)); 3361 3362 } else if (jzpc->info->version >= ID_X1830) { 3363 unsigned int half = PINS_PER_GPIO_CHIP / 2; 3364 unsigned int idxh = (pin % half) * 2; 3365 3366 if (idx < half) 3367 regmap_read(jzpc->map, offt * jzpc->info->reg_offset + 3368 X1830_GPIO_PEL, &bias); 3369 else 3370 regmap_read(jzpc->map, offt * jzpc->info->reg_offset + 3371 X1830_GPIO_PEH, &bias); 3372 3373 bias = (bias >> idxh) & (GPIO_PULL_UP | GPIO_PULL_DOWN); 3374 3375 pullup = (bias == GPIO_PULL_UP) && (jzpc->info->pull_ups[offt] & BIT(idx)); 3376 pulldown = (bias == GPIO_PULL_DOWN) && (jzpc->info->pull_downs[offt] & BIT(idx)); 3377 3378 } else { 3379 if (jzpc->info->version >= ID_JZ4770) 3380 pull = !ingenic_get_pin_config(jzpc, pin, JZ4770_GPIO_PEN); 3381 else if (jzpc->info->version >= ID_JZ4740) 3382 pull = !ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_PULL_DIS); 3383 else 3384 pull = ingenic_get_pin_config(jzpc, pin, JZ4730_GPIO_GPPUR); 3385 3386 pullup = pull && (jzpc->info->pull_ups[offt] & BIT(idx)); 3387 pulldown = pull && (jzpc->info->pull_downs[offt] & BIT(idx)); 3388 } 3389 3390 switch (param) { 3391 case PIN_CONFIG_BIAS_DISABLE: 3392 if (pullup || pulldown) 3393 return -EINVAL; 3394 3395 break; 3396 3397 case PIN_CONFIG_BIAS_PULL_UP: 3398 if (!pullup) 3399 return -EINVAL; 3400 3401 break; 3402 3403 case PIN_CONFIG_BIAS_PULL_DOWN: 3404 if (!pulldown) 3405 return -EINVAL; 3406 3407 break; 3408 3409 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 3410 if (jzpc->info->version >= ID_X2000) 3411 reg = X2000_GPIO_SMT; 3412 else if (jzpc->info->version >= ID_X1830) 3413 reg = X1830_GPIO_SMT; 3414 else 3415 return -EINVAL; 3416 3417 arg = !!ingenic_get_pin_config(jzpc, pin, reg); 3418 break; 3419 3420 case PIN_CONFIG_SLEW_RATE: 3421 if (jzpc->info->version >= ID_X2000) 3422 reg = X2000_GPIO_SR; 3423 else if (jzpc->info->version >= ID_X1830) 3424 reg = X1830_GPIO_SR; 3425 else 3426 return -EINVAL; 3427 3428 arg = !!ingenic_get_pin_config(jzpc, pin, reg); 3429 break; 3430 3431 default: 3432 return -ENOTSUPP; 3433 } 3434 3435 *config = pinconf_to_config_packed(param, arg); 3436 return 0; 3437 } 3438 3439 static void ingenic_set_bias(struct ingenic_pinctrl *jzpc, 3440 unsigned int pin, unsigned int bias) 3441 { 3442 if (jzpc->info->version >= ID_X2000) { 3443 switch (bias) { 3444 case PIN_CONFIG_BIAS_PULL_UP: 3445 ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPD, false); 3446 ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPU, true); 3447 break; 3448 3449 case PIN_CONFIG_BIAS_PULL_DOWN: 3450 ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPU, false); 3451 ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPD, true); 3452 break; 3453 3454 case PIN_CONFIG_BIAS_DISABLE: 3455 default: 3456 ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPU, false); 3457 ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPD, false); 3458 } 3459 3460 } else if (jzpc->info->version >= ID_X1830) { 3461 unsigned int idx = pin % PINS_PER_GPIO_CHIP; 3462 unsigned int half = PINS_PER_GPIO_CHIP / 2; 3463 unsigned int idxh = (pin % half) * 2; 3464 unsigned int offt = pin / PINS_PER_GPIO_CHIP; 3465 3466 if (idx < half) { 3467 regmap_write(jzpc->map, offt * jzpc->info->reg_offset + 3468 REG_CLEAR(X1830_GPIO_PEL), 3 << idxh); 3469 regmap_write(jzpc->map, offt * jzpc->info->reg_offset + 3470 REG_SET(X1830_GPIO_PEL), bias << idxh); 3471 } else { 3472 regmap_write(jzpc->map, offt * jzpc->info->reg_offset + 3473 REG_CLEAR(X1830_GPIO_PEH), 3 << idxh); 3474 regmap_write(jzpc->map, offt * jzpc->info->reg_offset + 3475 REG_SET(X1830_GPIO_PEH), bias << idxh); 3476 } 3477 3478 } else if (jzpc->info->version >= ID_JZ4770) { 3479 ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PEN, !bias); 3480 } else if (jzpc->info->version >= ID_JZ4740) { 3481 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_PULL_DIS, !bias); 3482 } else { 3483 ingenic_config_pin(jzpc, pin, JZ4730_GPIO_GPPUR, bias); 3484 } 3485 } 3486 3487 static void ingenic_set_schmitt_trigger(struct ingenic_pinctrl *jzpc, 3488 unsigned int pin, bool enable) 3489 { 3490 if (jzpc->info->version >= ID_X2000) 3491 ingenic_config_pin(jzpc, pin, X2000_GPIO_SMT, enable); 3492 else 3493 ingenic_config_pin(jzpc, pin, X1830_GPIO_SMT, enable); 3494 } 3495 3496 static void ingenic_set_output_level(struct ingenic_pinctrl *jzpc, 3497 unsigned int pin, bool high) 3498 { 3499 if (jzpc->info->version >= ID_JZ4770) 3500 ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PAT0, high); 3501 else if (jzpc->info->version >= ID_JZ4740) 3502 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_DATA, high); 3503 else 3504 ingenic_config_pin(jzpc, pin, JZ4730_GPIO_DATA, high); 3505 } 3506 3507 static void ingenic_set_slew_rate(struct ingenic_pinctrl *jzpc, 3508 unsigned int pin, unsigned int slew) 3509 { 3510 if (jzpc->info->version >= ID_X2000) 3511 ingenic_config_pin(jzpc, pin, X2000_GPIO_SR, slew); 3512 else 3513 ingenic_config_pin(jzpc, pin, X1830_GPIO_SR, slew); 3514 } 3515 3516 static int ingenic_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 3517 unsigned long *configs, unsigned int num_configs) 3518 { 3519 struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev); 3520 unsigned int idx = pin % PINS_PER_GPIO_CHIP; 3521 unsigned int offt = pin / PINS_PER_GPIO_CHIP; 3522 unsigned int cfg, arg; 3523 int ret; 3524 3525 for (cfg = 0; cfg < num_configs; cfg++) { 3526 switch (pinconf_to_config_param(configs[cfg])) { 3527 case PIN_CONFIG_BIAS_DISABLE: 3528 case PIN_CONFIG_BIAS_PULL_UP: 3529 case PIN_CONFIG_BIAS_PULL_DOWN: 3530 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 3531 case PIN_CONFIG_OUTPUT: 3532 case PIN_CONFIG_SLEW_RATE: 3533 continue; 3534 default: 3535 return -ENOTSUPP; 3536 } 3537 } 3538 3539 for (cfg = 0; cfg < num_configs; cfg++) { 3540 arg = pinconf_to_config_argument(configs[cfg]); 3541 3542 switch (pinconf_to_config_param(configs[cfg])) { 3543 case PIN_CONFIG_BIAS_DISABLE: 3544 dev_dbg(jzpc->dev, "disable pull-over for pin P%c%u\n", 3545 'A' + offt, idx); 3546 ingenic_set_bias(jzpc, pin, GPIO_PULL_DIS); 3547 break; 3548 3549 case PIN_CONFIG_BIAS_PULL_UP: 3550 if (!(jzpc->info->pull_ups[offt] & BIT(idx))) 3551 return -EINVAL; 3552 dev_dbg(jzpc->dev, "set pull-up for pin P%c%u\n", 3553 'A' + offt, idx); 3554 ingenic_set_bias(jzpc, pin, GPIO_PULL_UP); 3555 break; 3556 3557 case PIN_CONFIG_BIAS_PULL_DOWN: 3558 if (!(jzpc->info->pull_downs[offt] & BIT(idx))) 3559 return -EINVAL; 3560 dev_dbg(jzpc->dev, "set pull-down for pin P%c%u\n", 3561 'A' + offt, idx); 3562 ingenic_set_bias(jzpc, pin, GPIO_PULL_DOWN); 3563 break; 3564 3565 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 3566 if (jzpc->info->version < ID_X1830) 3567 return -EINVAL; 3568 3569 ingenic_set_schmitt_trigger(jzpc, pin, arg); 3570 break; 3571 3572 case PIN_CONFIG_OUTPUT: 3573 ret = pinctrl_gpio_direction_output(pin); 3574 if (ret) 3575 return ret; 3576 3577 ingenic_set_output_level(jzpc, pin, arg); 3578 break; 3579 3580 case PIN_CONFIG_SLEW_RATE: 3581 if (jzpc->info->version < ID_X1830) 3582 return -EINVAL; 3583 3584 ingenic_set_slew_rate(jzpc, pin, arg); 3585 break; 3586 3587 default: 3588 /* unreachable */ 3589 break; 3590 } 3591 } 3592 3593 return 0; 3594 } 3595 3596 static int ingenic_pinconf_group_get(struct pinctrl_dev *pctldev, 3597 unsigned int group, unsigned long *config) 3598 { 3599 const unsigned int *pins; 3600 unsigned int i, npins, old = 0; 3601 int ret; 3602 3603 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); 3604 if (ret) 3605 return ret; 3606 3607 for (i = 0; i < npins; i++) { 3608 if (ingenic_pinconf_get(pctldev, pins[i], config)) 3609 return -ENOTSUPP; 3610 3611 /* configs do not match between two pins */ 3612 if (i && (old != *config)) 3613 return -ENOTSUPP; 3614 3615 old = *config; 3616 } 3617 3618 return 0; 3619 } 3620 3621 static int ingenic_pinconf_group_set(struct pinctrl_dev *pctldev, 3622 unsigned int group, unsigned long *configs, 3623 unsigned int num_configs) 3624 { 3625 const unsigned int *pins; 3626 unsigned int i, npins; 3627 int ret; 3628 3629 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); 3630 if (ret) 3631 return ret; 3632 3633 for (i = 0; i < npins; i++) { 3634 ret = ingenic_pinconf_set(pctldev, 3635 pins[i], configs, num_configs); 3636 if (ret) 3637 return ret; 3638 } 3639 3640 return 0; 3641 } 3642 3643 static const struct pinconf_ops ingenic_confops = { 3644 .is_generic = true, 3645 .pin_config_get = ingenic_pinconf_get, 3646 .pin_config_set = ingenic_pinconf_set, 3647 .pin_config_group_get = ingenic_pinconf_group_get, 3648 .pin_config_group_set = ingenic_pinconf_group_set, 3649 }; 3650 3651 static const struct regmap_config ingenic_pinctrl_regmap_config = { 3652 .reg_bits = 32, 3653 .val_bits = 32, 3654 .reg_stride = 4, 3655 }; 3656 3657 static const struct of_device_id ingenic_gpio_of_match[] __initconst = { 3658 { .compatible = "ingenic,jz4730-gpio", }, 3659 { .compatible = "ingenic,jz4740-gpio", }, 3660 { .compatible = "ingenic,jz4725b-gpio", }, 3661 { .compatible = "ingenic,jz4750-gpio", }, 3662 { .compatible = "ingenic,jz4755-gpio", }, 3663 { .compatible = "ingenic,jz4760-gpio", }, 3664 { .compatible = "ingenic,jz4770-gpio", }, 3665 { .compatible = "ingenic,jz4775-gpio", }, 3666 { .compatible = "ingenic,jz4780-gpio", }, 3667 { .compatible = "ingenic,x1000-gpio", }, 3668 { .compatible = "ingenic,x1830-gpio", }, 3669 { .compatible = "ingenic,x2000-gpio", }, 3670 {}, 3671 }; 3672 3673 static int __init ingenic_gpio_probe(struct ingenic_pinctrl *jzpc, 3674 struct device_node *node) 3675 { 3676 struct ingenic_gpio_chip *jzgc; 3677 struct device *dev = jzpc->dev; 3678 struct gpio_irq_chip *girq; 3679 unsigned int bank; 3680 int err; 3681 3682 err = of_property_read_u32(node, "reg", &bank); 3683 if (err) { 3684 dev_err(dev, "Cannot read \"reg\" property: %i\n", err); 3685 return err; 3686 } 3687 3688 jzgc = devm_kzalloc(dev, sizeof(*jzgc), GFP_KERNEL); 3689 if (!jzgc) 3690 return -ENOMEM; 3691 3692 jzgc->jzpc = jzpc; 3693 jzgc->reg_base = bank * jzpc->info->reg_offset; 3694 3695 jzgc->gc.label = devm_kasprintf(dev, GFP_KERNEL, "GPIO%c", 'A' + bank); 3696 if (!jzgc->gc.label) 3697 return -ENOMEM; 3698 3699 /* DO NOT EXPAND THIS: FOR BACKWARD GPIO NUMBERSPACE COMPATIBIBILITY 3700 * ONLY: WORK TO TRANSITION CONSUMERS TO USE THE GPIO DESCRIPTOR API IN 3701 * <linux/gpio/consumer.h> INSTEAD. 3702 */ 3703 jzgc->gc.base = bank * 32; 3704 3705 jzgc->gc.ngpio = 32; 3706 jzgc->gc.parent = dev; 3707 jzgc->gc.of_node = node; 3708 jzgc->gc.owner = THIS_MODULE; 3709 3710 jzgc->gc.set = ingenic_gpio_set; 3711 jzgc->gc.get = ingenic_gpio_get; 3712 jzgc->gc.direction_input = ingenic_gpio_direction_input; 3713 jzgc->gc.direction_output = ingenic_gpio_direction_output; 3714 jzgc->gc.get_direction = ingenic_gpio_get_direction; 3715 jzgc->gc.request = gpiochip_generic_request; 3716 jzgc->gc.free = gpiochip_generic_free; 3717 3718 jzgc->irq = irq_of_parse_and_map(node, 0); 3719 if (!jzgc->irq) 3720 return -EINVAL; 3721 3722 jzgc->irq_chip.name = jzgc->gc.label; 3723 jzgc->irq_chip.irq_enable = ingenic_gpio_irq_enable; 3724 jzgc->irq_chip.irq_disable = ingenic_gpio_irq_disable; 3725 jzgc->irq_chip.irq_unmask = ingenic_gpio_irq_unmask; 3726 jzgc->irq_chip.irq_mask = ingenic_gpio_irq_mask; 3727 jzgc->irq_chip.irq_ack = ingenic_gpio_irq_ack; 3728 jzgc->irq_chip.irq_set_type = ingenic_gpio_irq_set_type; 3729 jzgc->irq_chip.irq_set_wake = ingenic_gpio_irq_set_wake; 3730 jzgc->irq_chip.irq_request_resources = ingenic_gpio_irq_request; 3731 jzgc->irq_chip.irq_release_resources = ingenic_gpio_irq_release; 3732 jzgc->irq_chip.flags = IRQCHIP_MASK_ON_SUSPEND; 3733 3734 girq = &jzgc->gc.irq; 3735 girq->chip = &jzgc->irq_chip; 3736 girq->parent_handler = ingenic_gpio_irq_handler; 3737 girq->num_parents = 1; 3738 girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents), 3739 GFP_KERNEL); 3740 if (!girq->parents) 3741 return -ENOMEM; 3742 3743 girq->parents[0] = jzgc->irq; 3744 girq->default_type = IRQ_TYPE_NONE; 3745 girq->handler = handle_level_irq; 3746 3747 err = devm_gpiochip_add_data(dev, &jzgc->gc, jzgc); 3748 if (err) 3749 return err; 3750 3751 return 0; 3752 } 3753 3754 static int __init ingenic_pinctrl_probe(struct platform_device *pdev) 3755 { 3756 struct device *dev = &pdev->dev; 3757 struct ingenic_pinctrl *jzpc; 3758 struct pinctrl_desc *pctl_desc; 3759 void __iomem *base; 3760 const struct ingenic_chip_info *chip_info; 3761 struct device_node *node; 3762 unsigned int i; 3763 int err; 3764 3765 chip_info = of_device_get_match_data(dev); 3766 if (!chip_info) { 3767 dev_err(dev, "Unsupported SoC\n"); 3768 return -EINVAL; 3769 } 3770 3771 jzpc = devm_kzalloc(dev, sizeof(*jzpc), GFP_KERNEL); 3772 if (!jzpc) 3773 return -ENOMEM; 3774 3775 base = devm_platform_ioremap_resource(pdev, 0); 3776 if (IS_ERR(base)) 3777 return PTR_ERR(base); 3778 3779 jzpc->map = devm_regmap_init_mmio(dev, base, 3780 &ingenic_pinctrl_regmap_config); 3781 if (IS_ERR(jzpc->map)) { 3782 dev_err(dev, "Failed to create regmap\n"); 3783 return PTR_ERR(jzpc->map); 3784 } 3785 3786 jzpc->dev = dev; 3787 jzpc->info = chip_info; 3788 3789 pctl_desc = devm_kzalloc(&pdev->dev, sizeof(*pctl_desc), GFP_KERNEL); 3790 if (!pctl_desc) 3791 return -ENOMEM; 3792 3793 /* fill in pinctrl_desc structure */ 3794 pctl_desc->name = dev_name(dev); 3795 pctl_desc->owner = THIS_MODULE; 3796 pctl_desc->pctlops = &ingenic_pctlops; 3797 pctl_desc->pmxops = &ingenic_pmxops; 3798 pctl_desc->confops = &ingenic_confops; 3799 pctl_desc->npins = chip_info->num_chips * PINS_PER_GPIO_CHIP; 3800 pctl_desc->pins = jzpc->pdesc = devm_kcalloc(&pdev->dev, 3801 pctl_desc->npins, sizeof(*jzpc->pdesc), GFP_KERNEL); 3802 if (!jzpc->pdesc) 3803 return -ENOMEM; 3804 3805 for (i = 0; i < pctl_desc->npins; i++) { 3806 jzpc->pdesc[i].number = i; 3807 jzpc->pdesc[i].name = kasprintf(GFP_KERNEL, "P%c%d", 3808 'A' + (i / PINS_PER_GPIO_CHIP), 3809 i % PINS_PER_GPIO_CHIP); 3810 } 3811 3812 jzpc->pctl = devm_pinctrl_register(dev, pctl_desc, jzpc); 3813 if (IS_ERR(jzpc->pctl)) { 3814 dev_err(dev, "Failed to register pinctrl\n"); 3815 return PTR_ERR(jzpc->pctl); 3816 } 3817 3818 for (i = 0; i < chip_info->num_groups; i++) { 3819 const struct group_desc *group = &chip_info->groups[i]; 3820 3821 err = pinctrl_generic_add_group(jzpc->pctl, group->name, 3822 group->pins, group->num_pins, group->data); 3823 if (err < 0) { 3824 dev_err(dev, "Failed to register group %s\n", 3825 group->name); 3826 return err; 3827 } 3828 } 3829 3830 for (i = 0; i < chip_info->num_functions; i++) { 3831 const struct function_desc *func = &chip_info->functions[i]; 3832 3833 err = pinmux_generic_add_function(jzpc->pctl, func->name, 3834 func->group_names, func->num_group_names, 3835 func->data); 3836 if (err < 0) { 3837 dev_err(dev, "Failed to register function %s\n", 3838 func->name); 3839 return err; 3840 } 3841 } 3842 3843 dev_set_drvdata(dev, jzpc->map); 3844 3845 for_each_child_of_node(dev->of_node, node) { 3846 if (of_match_node(ingenic_gpio_of_match, node)) { 3847 err = ingenic_gpio_probe(jzpc, node); 3848 if (err) { 3849 of_node_put(node); 3850 return err; 3851 } 3852 } 3853 } 3854 3855 return 0; 3856 } 3857 3858 #define IF_ENABLED(cfg, ptr) PTR_IF(IS_ENABLED(cfg), (ptr)) 3859 3860 static const struct of_device_id ingenic_pinctrl_of_match[] = { 3861 { 3862 .compatible = "ingenic,jz4730-pinctrl", 3863 .data = IF_ENABLED(CONFIG_MACH_JZ4730, &jz4730_chip_info) 3864 }, 3865 { 3866 .compatible = "ingenic,jz4740-pinctrl", 3867 .data = IF_ENABLED(CONFIG_MACH_JZ4740, &jz4740_chip_info) 3868 }, 3869 { 3870 .compatible = "ingenic,jz4725b-pinctrl", 3871 .data = IF_ENABLED(CONFIG_MACH_JZ4725B, &jz4725b_chip_info) 3872 }, 3873 { 3874 .compatible = "ingenic,jz4750-pinctrl", 3875 .data = IF_ENABLED(CONFIG_MACH_JZ4750, &jz4750_chip_info) 3876 }, 3877 { 3878 .compatible = "ingenic,jz4755-pinctrl", 3879 .data = IF_ENABLED(CONFIG_MACH_JZ4755, &jz4755_chip_info) 3880 }, 3881 { 3882 .compatible = "ingenic,jz4760-pinctrl", 3883 .data = IF_ENABLED(CONFIG_MACH_JZ4760, &jz4760_chip_info) 3884 }, 3885 { 3886 .compatible = "ingenic,jz4760b-pinctrl", 3887 .data = IF_ENABLED(CONFIG_MACH_JZ4760, &jz4760_chip_info) 3888 }, 3889 { 3890 .compatible = "ingenic,jz4770-pinctrl", 3891 .data = IF_ENABLED(CONFIG_MACH_JZ4770, &jz4770_chip_info) 3892 }, 3893 { 3894 .compatible = "ingenic,jz4775-pinctrl", 3895 .data = IF_ENABLED(CONFIG_MACH_JZ4775, &jz4775_chip_info) 3896 }, 3897 { 3898 .compatible = "ingenic,jz4780-pinctrl", 3899 .data = IF_ENABLED(CONFIG_MACH_JZ4780, &jz4780_chip_info) 3900 }, 3901 { 3902 .compatible = "ingenic,x1000-pinctrl", 3903 .data = IF_ENABLED(CONFIG_MACH_X1000, &x1000_chip_info) 3904 }, 3905 { 3906 .compatible = "ingenic,x1000e-pinctrl", 3907 .data = IF_ENABLED(CONFIG_MACH_X1000, &x1000_chip_info) 3908 }, 3909 { 3910 .compatible = "ingenic,x1500-pinctrl", 3911 .data = IF_ENABLED(CONFIG_MACH_X1500, &x1500_chip_info) 3912 }, 3913 { 3914 .compatible = "ingenic,x1830-pinctrl", 3915 .data = IF_ENABLED(CONFIG_MACH_X1830, &x1830_chip_info) 3916 }, 3917 { 3918 .compatible = "ingenic,x2000-pinctrl", 3919 .data = IF_ENABLED(CONFIG_MACH_X2000, &x2000_chip_info) 3920 }, 3921 { 3922 .compatible = "ingenic,x2000e-pinctrl", 3923 .data = IF_ENABLED(CONFIG_MACH_X2000, &x2000_chip_info) 3924 }, 3925 { /* sentinel */ }, 3926 }; 3927 3928 static struct platform_driver ingenic_pinctrl_driver = { 3929 .driver = { 3930 .name = "pinctrl-ingenic", 3931 .of_match_table = ingenic_pinctrl_of_match, 3932 }, 3933 }; 3934 3935 static int __init ingenic_pinctrl_drv_register(void) 3936 { 3937 return platform_driver_probe(&ingenic_pinctrl_driver, 3938 ingenic_pinctrl_probe); 3939 } 3940 subsys_initcall(ingenic_pinctrl_drv_register); 3941